From eff3560d64fda22ec5c4568dc06f7d3f9a5feef5 Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Mon, 20 Nov 2023 06:16:16 -0500 Subject: [bsp] remove gd32 in the root --- .github/workflows/action.yml | 4 - .../manual_trigger_scons_except_STM32_all.yml | 7 - .../manual_trigger_scons_fail_bsp_all.yml | 3 - bsp/README.md | 7 - bsp/gd32105c-eval/.config | 1063 ------ bsp/gd32105c-eval/.ignore_format.yml | 8 - bsp/gd32105c-eval/Kconfig | 25 - .../Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h | 381 --- .../CMSIS/GD/GD32F10x/Include/system_gd32f10x.h | 60 - .../GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s | 390 --- .../GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s | 371 -- .../GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s | 328 -- .../GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s | 371 -- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s | 529 --- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s | 491 --- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s | 400 --- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s | 491 --- .../CMSIS/GD/GD32F10x/Source/system_gd32f10x.c | 1028 ------ bsp/gd32105c-eval/Libraries/CMSIS/core_cm3.h | 1638 --------- bsp/gd32105c-eval/Libraries/CMSIS/core_cmFunc.h | 637 ---- bsp/gd32105c-eval/Libraries/CMSIS/core_cmInstr.h | 880 ----- .../Include/gd32f10x_adc.h | 368 -- .../Include/gd32f10x_bkp.h | 230 -- .../Include/gd32f10x_can.h | 725 ---- .../Include/gd32f10x_crc.h | 81 - .../Include/gd32f10x_dac.h | 250 -- .../Include/gd32f10x_dbg.h | 152 - .../Include/gd32f10x_dma.h | 289 -- .../Include/gd32f10x_enet.h | 1498 -------- .../Include/gd32f10x_exmc.h | 432 --- .../Include/gd32f10x_exti.h | 258 -- .../Include/gd32f10x_fmc.h | 370 -- .../Include/gd32f10x_fwdgt.h | 108 - .../Include/gd32f10x_gpio.h | 497 --- .../Include/gd32f10x_i2c.h | 346 -- .../Include/gd32f10x_misc.h | 95 - .../Include/gd32f10x_pmu.h | 129 - .../Include/gd32f10x_rcu.h | 924 ----- .../Include/gd32f10x_rtc.h | 152 - .../Include/gd32f10x_sdio.h | 430 --- .../Include/gd32f10x_spi.h | 328 -- .../Include/gd32f10x_timer.h | 730 ---- .../Include/gd32f10x_usart.h | 378 -- .../Include/gd32f10x_wwdgt.h | 90 - .../Source/gd32f10x_adc.c | 933 ----- .../Source/gd32f10x_bkp.c | 296 -- .../Source/gd32f10x_can.c | 993 ------ .../Source/gd32f10x_crc.c | 131 - .../Source/gd32f10x_dac.c | 559 --- .../Source/gd32f10x_dbg.c | 153 - .../Source/gd32f10x_dma.c | 737 ---- .../Source/gd32f10x_enet.c | 3074 ----------------- .../Source/gd32f10x_exmc.c | 646 ---- .../Source/gd32f10x_exti.c | 256 -- .../Source/gd32f10x_fmc.c | 965 ------ .../Source/gd32f10x_fwdgt.c | 155 - .../Source/gd32f10x_gpio.c | 539 --- .../Source/gd32f10x_i2c.c | 707 ---- .../Source/gd32f10x_misc.c | 187 - .../Source/gd32f10x_pmu.c | 265 -- .../Source/gd32f10x_rcu.c | 1193 ------- .../Source/gd32f10x_rtc.c | 277 -- .../Source/gd32f10x_sdio.c | 814 ----- .../Source/gd32f10x_spi.c | 718 ---- .../Source/gd32f10x_timer.c | 2004 ----------- .../Source/gd32f10x_usart.c | 767 ----- .../Source/gd32f10x_wwdgt.c | 150 - .../GD32F10x_usbd_driver/Include/usbd_core.h | 217 -- .../GD32F10x_usbd_driver/Include/usbd_int.h | 62 - .../GD32F10x_usbd_driver/Include/usbd_pwr.h | 52 - .../GD32F10x_usbd_driver/Include/usbd_regs.h | 297 -- .../GD32F10x_usbd_driver/Include/usbd_std.h | 221 -- .../GD32F10x_usbd_driver/Source/usbd_core.c | 455 --- .../GD32F10x_usbd_driver/Source/usbd_int.c | 458 --- .../GD32F10x_usbd_driver/Source/usbd_pwr.c | 159 - .../GD32F10x_usbd_driver/Source/usbd_std.c | 868 ----- .../GD32F10x_usbfs_driver/Include/usb_core.h | 304 -- .../GD32F10x_usbfs_driver/Include/usb_defines.h | 128 - .../GD32F10x_usbfs_driver/Include/usb_regs.h | 596 ---- .../GD32F10x_usbfs_driver/Include/usb_std.h | 216 -- .../GD32F10x_usbfs_driver/Include/usbd_core.h | 81 - .../GD32F10x_usbfs_driver/Include/usbd_int.h | 57 - .../GD32F10x_usbfs_driver/Include/usbd_std.h | 98 - .../GD32F10x_usbfs_driver/Include/usbh_core.h | 310 -- .../GD32F10x_usbfs_driver/Include/usbh_ctrl.h | 73 - .../GD32F10x_usbfs_driver/Include/usbh_hcs.h | 73 - .../GD32F10x_usbfs_driver/Include/usbh_int.h | 58 - .../GD32F10x_usbfs_driver/Include/usbh_std.h | 101 - .../GD32F10x_usbfs_driver/Source/usb_core.c | 974 ------ .../GD32F10x_usbfs_driver/Source/usbd_core.c | 503 --- .../GD32F10x_usbfs_driver/Source/usbd_int.c | 663 ---- .../GD32F10x_usbfs_driver/Source/usbd_std.c | 727 ---- .../GD32F10x_usbfs_driver/Source/usbh_core.c | 737 ---- .../GD32F10x_usbfs_driver/Source/usbh_ctrl.c | 639 ---- .../GD32F10x_usbfs_driver/Source/usbh_hcs.c | 185 - .../GD32F10x_usbfs_driver/Source/usbh_int.c | 612 ---- .../GD32F10x_usbfs_driver/Source/usbh_std.c | 834 ----- bsp/gd32105c-eval/Libraries/SConscript | 33 - bsp/gd32105c-eval/README.md | 93 - bsp/gd32105c-eval/SConscript | 14 - bsp/gd32105c-eval/SConstruct | 40 - bsp/gd32105c-eval/applications/SConscript | 15 - bsp/gd32105c-eval/applications/main.c | 34 - bsp/gd32105c-eval/board/linker_script/gd32_rom.icf | 40 - bsp/gd32105c-eval/board/linker_script/gd32_rom.ld | 142 - bsp/gd32105c-eval/board/linker_script/gd32_rom.sct | 15 - bsp/gd32105c-eval/drivers/Kconfig | 69 - bsp/gd32105c-eval/drivers/SConscript | 33 - bsp/gd32105c-eval/drivers/board.c | 83 - bsp/gd32105c-eval/drivers/board.h | 44 - bsp/gd32105c-eval/drivers/drv_comm.h | 27 - bsp/gd32105c-eval/drivers/drv_gpio.c | 552 --- bsp/gd32105c-eval/drivers/drv_gpio.h | 39 - bsp/gd32105c-eval/drivers/drv_i2c.c | 373 -- bsp/gd32105c-eval/drivers/drv_i2c.h | 15 - bsp/gd32105c-eval/drivers/drv_spi.c | 297 -- bsp/gd32105c-eval/drivers/drv_spi.h | 15 - bsp/gd32105c-eval/drivers/drv_spi_flash.c | 70 - bsp/gd32105c-eval/drivers/drv_usart.c | 374 -- bsp/gd32105c-eval/drivers/drv_usart.h | 15 - bsp/gd32105c-eval/drivers/gd32f10x_libopt.h | 67 - bsp/gd32105c-eval/list/context_rvds.lst | 520 --- bsp/gd32105c-eval/list/startup_gd32f10x_cl.lst | 1851 ---------- bsp/gd32105c-eval/project.ewd | 2834 --------------- bsp/gd32105c-eval/project.ewp | 2258 ------------ bsp/gd32105c-eval/project.eww | 10 - bsp/gd32105c-eval/project.uvoptx | 177 - bsp/gd32105c-eval/project.uvprojx | 1234 ------- bsp/gd32105c-eval/rtconfig.h | 273 -- bsp/gd32105c-eval/rtconfig.py | 126 - bsp/gd32105c-eval/template.ewp | 1889 ---------- bsp/gd32105c-eval/template.uvoptx | 177 - bsp/gd32105c-eval/template.uvprojx | 405 --- bsp/gd32107c-eval/.config | 1063 ------ bsp/gd32107c-eval/.ignore_format.yml | 8 - bsp/gd32107c-eval/Kconfig | 25 - .../Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h | 381 --- .../CMSIS/GD/GD32F10x/Include/system_gd32f10x.h | 60 - .../GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s | 390 --- .../GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s | 371 -- .../GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s | 328 -- .../GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s | 371 -- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s | 529 --- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s | 491 --- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s | 400 --- .../GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s | 491 --- .../CMSIS/GD/GD32F10x/Source/system_gd32f10x.c | 1028 ------ bsp/gd32107c-eval/Libraries/CMSIS/core_cm3.h | 1638 --------- bsp/gd32107c-eval/Libraries/CMSIS/core_cmFunc.h | 637 ---- bsp/gd32107c-eval/Libraries/CMSIS/core_cmInstr.h | 880 ----- .../Include/gd32f10x_adc.h | 368 -- .../Include/gd32f10x_bkp.h | 230 -- .../Include/gd32f10x_can.h | 725 ---- .../Include/gd32f10x_crc.h | 81 - .../Include/gd32f10x_dac.h | 250 -- .../Include/gd32f10x_dbg.h | 152 - .../Include/gd32f10x_dma.h | 289 -- .../Include/gd32f10x_enet.h | 1498 -------- .../Include/gd32f10x_exmc.h | 432 --- .../Include/gd32f10x_exti.h | 258 -- .../Include/gd32f10x_fmc.h | 370 -- .../Include/gd32f10x_fwdgt.h | 108 - .../Include/gd32f10x_gpio.h | 497 --- .../Include/gd32f10x_i2c.h | 346 -- .../Include/gd32f10x_misc.h | 95 - .../Include/gd32f10x_pmu.h | 129 - .../Include/gd32f10x_rcu.h | 924 ----- .../Include/gd32f10x_rtc.h | 152 - .../Include/gd32f10x_sdio.h | 430 --- .../Include/gd32f10x_spi.h | 328 -- .../Include/gd32f10x_timer.h | 730 ---- .../Include/gd32f10x_usart.h | 378 -- .../Include/gd32f10x_wwdgt.h | 90 - .../Source/gd32f10x_adc.c | 933 ----- .../Source/gd32f10x_bkp.c | 296 -- .../Source/gd32f10x_can.c | 993 ------ .../Source/gd32f10x_crc.c | 131 - .../Source/gd32f10x_dac.c | 559 --- .../Source/gd32f10x_dbg.c | 153 - .../Source/gd32f10x_dma.c | 737 ---- .../Source/gd32f10x_enet.c | 3074 ----------------- .../Source/gd32f10x_exmc.c | 646 ---- .../Source/gd32f10x_exti.c | 256 -- .../Source/gd32f10x_fmc.c | 965 ------ .../Source/gd32f10x_fwdgt.c | 155 - .../Source/gd32f10x_gpio.c | 539 --- .../Source/gd32f10x_i2c.c | 707 ---- .../Source/gd32f10x_misc.c | 187 - .../Source/gd32f10x_pmu.c | 265 -- .../Source/gd32f10x_rcu.c | 1193 ------- .../Source/gd32f10x_rtc.c | 277 -- .../Source/gd32f10x_sdio.c | 814 ----- .../Source/gd32f10x_spi.c | 718 ---- .../Source/gd32f10x_timer.c | 2004 ----------- .../Source/gd32f10x_usart.c | 767 ----- .../Source/gd32f10x_wwdgt.c | 150 - .../GD32F10x_usbd_driver/Include/usbd_core.h | 217 -- .../GD32F10x_usbd_driver/Include/usbd_int.h | 62 - .../GD32F10x_usbd_driver/Include/usbd_pwr.h | 52 - .../GD32F10x_usbd_driver/Include/usbd_regs.h | 297 -- .../GD32F10x_usbd_driver/Include/usbd_std.h | 221 -- .../GD32F10x_usbd_driver/Source/usbd_core.c | 455 --- .../GD32F10x_usbd_driver/Source/usbd_int.c | 458 --- .../GD32F10x_usbd_driver/Source/usbd_pwr.c | 159 - .../GD32F10x_usbd_driver/Source/usbd_std.c | 868 ----- .../GD32F10x_usbfs_driver/Include/usb_core.h | 304 -- .../GD32F10x_usbfs_driver/Include/usb_defines.h | 128 - .../GD32F10x_usbfs_driver/Include/usb_regs.h | 596 ---- .../GD32F10x_usbfs_driver/Include/usb_std.h | 216 -- .../GD32F10x_usbfs_driver/Include/usbd_core.h | 81 - .../GD32F10x_usbfs_driver/Include/usbd_int.h | 57 - .../GD32F10x_usbfs_driver/Include/usbd_std.h | 98 - .../GD32F10x_usbfs_driver/Include/usbh_core.h | 310 -- .../GD32F10x_usbfs_driver/Include/usbh_ctrl.h | 73 - .../GD32F10x_usbfs_driver/Include/usbh_hcs.h | 73 - .../GD32F10x_usbfs_driver/Include/usbh_int.h | 58 - .../GD32F10x_usbfs_driver/Include/usbh_std.h | 101 - .../GD32F10x_usbfs_driver/Source/usb_core.c | 974 ------ .../GD32F10x_usbfs_driver/Source/usbd_core.c | 503 --- .../GD32F10x_usbfs_driver/Source/usbd_int.c | 663 ---- .../GD32F10x_usbfs_driver/Source/usbd_std.c | 727 ---- .../GD32F10x_usbfs_driver/Source/usbh_core.c | 737 ---- .../GD32F10x_usbfs_driver/Source/usbh_ctrl.c | 639 ---- .../GD32F10x_usbfs_driver/Source/usbh_hcs.c | 185 - .../GD32F10x_usbfs_driver/Source/usbh_int.c | 612 ---- .../GD32F10x_usbfs_driver/Source/usbh_std.c | 834 ----- bsp/gd32107c-eval/Libraries/SConscript | 33 - bsp/gd32107c-eval/README.md | 93 - bsp/gd32107c-eval/SConscript | 14 - bsp/gd32107c-eval/SConstruct | 40 - bsp/gd32107c-eval/applications/SConscript | 15 - bsp/gd32107c-eval/applications/main.c | 34 - bsp/gd32107c-eval/board/linker_script/gd32_rom.icf | 40 - bsp/gd32107c-eval/board/linker_script/gd32_rom.ld | 142 - bsp/gd32107c-eval/board/linker_script/gd32_rom.sct | 15 - bsp/gd32107c-eval/drivers/Kconfig | 69 - bsp/gd32107c-eval/drivers/SConscript | 33 - bsp/gd32107c-eval/drivers/board.c | 83 - bsp/gd32107c-eval/drivers/board.h | 44 - bsp/gd32107c-eval/drivers/drv_comm.h | 27 - bsp/gd32107c-eval/drivers/drv_gpio.c | 552 --- bsp/gd32107c-eval/drivers/drv_gpio.h | 39 - bsp/gd32107c-eval/drivers/drv_i2c.c | 373 -- bsp/gd32107c-eval/drivers/drv_i2c.h | 15 - bsp/gd32107c-eval/drivers/drv_spi.c | 297 -- bsp/gd32107c-eval/drivers/drv_spi.h | 15 - bsp/gd32107c-eval/drivers/drv_spi_flash.c | 70 - bsp/gd32107c-eval/drivers/drv_usart.c | 374 -- bsp/gd32107c-eval/drivers/drv_usart.h | 15 - bsp/gd32107c-eval/drivers/gd32f10x_libopt.h | 67 - bsp/gd32107c-eval/project.ewd | 2966 ---------------- bsp/gd32107c-eval/project.ewp | 2258 ------------ bsp/gd32107c-eval/project.eww | 10 - bsp/gd32107c-eval/project.uvoptx | 177 - bsp/gd32107c-eval/project.uvprojx | 1234 ------- bsp/gd32107c-eval/rtconfig.h | 273 -- bsp/gd32107c-eval/rtconfig.py | 126 - bsp/gd32107c-eval/template.ewp | 1889 ---------- bsp/gd32107c-eval/template.uvoptx | 177 - bsp/gd32107c-eval/template.uvprojx | 405 --- bsp/gd32303e-eval/.config | 1048 ------ bsp/gd32303e-eval/Kconfig | 84 - .../Libraries/CMSIS/GD/GD32F30x/Include/gd32f30x.h | 329 -- .../CMSIS/GD/GD32F30x/Include/system_gd32f30x.h | 58 - .../GD/GD32F30x/Source/ARM/startup_gd32f30x_cl.s | 359 -- .../GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s | 339 -- .../GD/GD32F30x/Source/ARM/startup_gd32f30x_xd.s | 339 -- .../GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S | 257 -- .../GD/GD32F30x/Source/IAR/startup_gd32f30x_cl.s | 501 --- .../GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s | 463 --- .../GD/GD32F30x/Source/IAR/startup_gd32f30x_xd.s | 463 --- .../CMSIS/GD/GD32F30x/Source/system_gd32f30x.c | 987 ------ bsp/gd32303e-eval/Libraries/CMSIS/core_cm4.h | 1790 ---------- bsp/gd32303e-eval/Libraries/CMSIS/core_cm4_simd.h | 697 ---- bsp/gd32303e-eval/Libraries/CMSIS/core_cmFunc.h | 616 ---- bsp/gd32303e-eval/Libraries/CMSIS/core_cmInstr.h | 618 ---- .../Include/gd32f30x_adc.h | 371 -- .../Include/gd32f30x_bkp.h | 218 -- .../Include/gd32f30x_can.h | 680 ---- .../Include/gd32f30x_crc.h | 55 - .../Include/gd32f30x_ctc.h | 161 - .../Include/gd32f30x_dac.h | 220 -- .../Include/gd32f30x_dbg.h | 119 - .../Include/gd32f30x_dma.h | 259 -- .../Include/gd32f30x_enet.h | 1680 --------- .../Include/gd32f30x_exmc.h | 420 --- .../Include/gd32f30x_exti.h | 229 -- .../Include/gd32f30x_fmc.h | 343 -- .../Include/gd32f30x_fwdgt.h | 79 - .../Include/gd32f30x_gpio.h | 504 --- .../Include/gd32f30x_i2c.h | 301 -- .../Include/gd32f30x_misc.h | 68 - .../Include/gd32f30x_pmu.h | 160 - .../Include/gd32f30x_rcu.h | 1027 ------ .../Include/gd32f30x_rtc.h | 111 - .../Include/gd32f30x_sdio.h | 404 --- .../Include/gd32f30x_spi.h | 328 -- .../Include/gd32f30x_timer.h | 716 ---- .../Include/gd32f30x_usart.h | 418 --- .../Include/gd32f30x_wwdgt.h | 63 - .../Source/gd32f30x_adc.c | 915 ----- .../Source/gd32f30x_bkp.c | 302 -- .../Source/gd32f30x_can.c | 846 ----- .../Source/gd32f30x_crc.c | 101 - .../Source/gd32f30x_ctc.c | 344 -- .../Source/gd32f30x_dac.c | 508 --- .../Source/gd32f30x_dbg.c | 125 - .../Source/gd32f30x_dma.c | 651 ---- .../Source/gd32f30x_enet.c | 3615 -------------------- .../Source/gd32f30x_exmc.c | 629 ---- .../Source/gd32f30x_exti.c | 227 -- .../Source/gd32f30x_fmc.c | 927 ----- .../Source/gd32f30x_fwdgt.c | 120 - .../Source/gd32f30x_gpio.c | 531 --- .../Source/gd32f30x_i2c.c | 683 ---- .../Source/gd32f30x_misc.c | 146 - .../Source/gd32f30x_pmu.c | 342 -- .../Source/gd32f30x_rcu.c | 1276 ------- .../Source/gd32f30x_rtc.c | 203 -- .../Source/gd32f30x_sdio.c | 772 ----- .../Source/gd32f30x_spi.c | 792 ----- .../Source/gd32f30x_timer.c | 1872 ---------- .../Source/gd32f30x_usart.c | 841 ----- .../Source/gd32f30x_wwdgt.c | 122 - .../GD32F30x_usbd_driver/Include/usbd_core.h | 191 -- .../GD32F30x_usbd_driver/Include/usbd_int.h | 32 - .../GD32F30x_usbd_driver/Include/usbd_pwr.h | 25 - .../GD32F30x_usbd_driver/Include/usbd_regs.h | 270 -- .../GD32F30x_usbd_driver/Include/usbd_std.h | 194 -- .../GD32F30x_usbd_driver/Source/usbd_core.c | 389 --- .../GD32F30x_usbd_driver/Source/usbd_int.c | 331 -- .../GD32F30x_usbd_driver/Source/usbd_pwr.c | 132 - .../GD32F30x_usbd_driver/Source/usbd_std.c | 834 ----- .../GD32F30x_usbfs_driver/Include/usb_core.h | 276 -- .../GD32F30x_usbfs_driver/Include/usb_defines.h | 100 - .../GD32F30x_usbfs_driver/Include/usb_regs.h | 630 ---- .../GD32F30x_usbfs_driver/Include/usb_std.h | 188 - .../GD32F30x_usbfs_driver/Include/usbd_core.h | 54 - .../GD32F30x_usbfs_driver/Include/usbd_int.h | 29 - .../GD32F30x_usbfs_driver/Include/usbd_std.h | 70 - .../GD32F30x_usbfs_driver/Include/usbh_core.h | 283 -- .../GD32F30x_usbfs_driver/Include/usbh_ctrl.h | 45 - .../GD32F30x_usbfs_driver/Include/usbh_hcs.h | 46 - .../GD32F30x_usbfs_driver/Include/usbh_int.h | 30 - .../GD32F30x_usbfs_driver/Include/usbh_std.h | 74 - .../GD32F30x_usbfs_driver/Source/usb_core.c | 935 ----- .../GD32F30x_usbfs_driver/Source/usbd_core.c | 476 --- .../GD32F30x_usbfs_driver/Source/usbd_int.c | 648 ---- .../GD32F30x_usbfs_driver/Source/usbd_std.c | 693 ---- .../GD32F30x_usbfs_driver/Source/usbh_core.c | 710 ---- .../GD32F30x_usbfs_driver/Source/usbh_ctrl.c | 612 ---- .../GD32F30x_usbfs_driver/Source/usbh_hcs.c | 158 - .../GD32F30x_usbfs_driver/Source/usbh_int.c | 576 ---- .../GD32F30x_usbfs_driver/Source/usbh_std.c | 807 ----- bsp/gd32303e-eval/Libraries/SConscript | 33 - bsp/gd32303e-eval/README.md | 93 - .../RTE/_rt-thread_gd32f30x/RTE_Components.h | 20 - bsp/gd32303e-eval/SConscript | 14 - bsp/gd32303e-eval/SConstruct | 40 - bsp/gd32303e-eval/applications/SConscript | 15 - bsp/gd32303e-eval/applications/main.c | 23 - bsp/gd32303e-eval/drivers/SConscript | 37 - bsp/gd32303e-eval/drivers/board.c | 83 - bsp/gd32303e-eval/drivers/board.h | 43 - bsp/gd32303e-eval/drivers/drv_gpio.c | 577 ---- bsp/gd32303e-eval/drivers/drv_gpio.h | 14 - bsp/gd32303e-eval/drivers/drv_i2c.c | 374 -- bsp/gd32303e-eval/drivers/drv_i2c.h | 15 - bsp/gd32303e-eval/drivers/drv_soft_spi.c | 303 -- bsp/gd32303e-eval/drivers/drv_soft_spi.h | 24 - bsp/gd32303e-eval/drivers/drv_spi.c | 298 -- bsp/gd32303e-eval/drivers/drv_spi.h | 15 - bsp/gd32303e-eval/drivers/drv_spi_flash.c | 71 - bsp/gd32303e-eval/drivers/drv_usart.c | 376 -- bsp/gd32303e-eval/drivers/drv_usart.h | 15 - bsp/gd32303e-eval/drivers/gd32f303e_eval.c | 206 -- bsp/gd32303e-eval/drivers/gd32f303e_eval.h | 137 - bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c | 496 --- bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h | 208 -- bsp/gd32303e-eval/drivers/gd32f30x_libopt.h | 42 - bsp/gd32303e-eval/gd32_rom.icf | 40 - bsp/gd32303e-eval/gd32_rom.ld | 142 - bsp/gd32303e-eval/gd32_rom.sct | 15 - bsp/gd32303e-eval/project.ewd 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bsp/gd32vf103v-eval/rtconfig.h delete mode 100644 bsp/gd32vf103v-eval/rtconfig.py diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 79ecee518e..bf73a23781 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -216,9 +216,6 @@ jobs: - "gd32/arm/gd32407v-start" - "gd32/arm/gd32450z-eval" - "gd32/arm/gd32470z-lckfb" - - "gd32e230k-start" - - "gd32303e-eval" - - "gd32450z-eval" - "n32/n32g43xcl-stb" - "n32/n32g45xcl-stb" - "n32/n32g45xml-stb" @@ -292,7 +289,6 @@ jobs: - RTT_BSP: "riscv-none" RTT_TOOL_CHAIN: "sourcery-riscv-none-embed" SUB_RTT_BSP: - - "gd32vf103v-eval" - "k210" - RTT_BSP: "riscv64-unknown" RTT_TOOL_CHAIN: "sourcery-riscv64-unknown-elf" diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 32bae273a7..fa8f40f0c5 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -117,13 +117,6 @@ jobs: - {RTT_BSP_NAME: "gd32_arm_gd32470z-lckfb", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32/arm/gd32470z-lckfb"} - {RTT_BSP_NAME: "gd32_risc-v_gd32vf103r-start", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed", RTT_BSP: "gd32/risc-v/gd32vf103r-start"} - {RTT_BSP_NAME: "gd32_risc-v_gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed", RTT_BSP: "gd32/risc-v/gd32vf103v-eval"} - #- {RTT_BSP_NAME: "gd32105c-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32105c-eval"} #编译错误 - #- {RTT_BSP_NAME: "gd32107c-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32107c-eval"} #编译错误 - - {RTT_BSP_NAME: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32303e-eval"} - #- {RTT_BSP_NAME: "gd32350r-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32350r-eval"} #编译错误 - - {RTT_BSP_NAME: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32450z-eval"} - - {RTT_BSP_NAME: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32e230k-start"} - - {RTT_BSP_NAME: "gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed", RTT_BSP: "gd32vf103v-eval"} - {RTT_BSP_NAME: "hc32_ev_hc32f460_lqfp100_v2", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32/ev_hc32f460_lqfp100_v2"} - {RTT_BSP_NAME: "hc32_ev_hc32f4a0_lqfp176", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32/ev_hc32f4a0_lqfp176"} #- {RTT_BSP_NAME: "hc32l136", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32l136"} #编译错误 diff --git a/.github/workflows/manual_trigger_scons_fail_bsp_all.yml b/.github/workflows/manual_trigger_scons_fail_bsp_all.yml index 7156595e96..e6ae43130f 100644 --- a/.github/workflows/manual_trigger_scons_fail_bsp_all.yml +++ b/.github/workflows/manual_trigger_scons_fail_bsp_all.yml @@ -56,9 +56,6 @@ jobs: - {RTT_BSP_NAME: "essemi_es32f365x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "essemi/es32f365x"} #GCC link文件没支æŒå¥½ - {RTT_BSP_NAME: "fm33lc026", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "fm33lc026"} #GCC - {RTT_BSP_NAME: "ft2004", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "ft2004"} #编译错误 - - {RTT_BSP_NAME: "gd32105c-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32105c-eval"} #编译错误 - - {RTT_BSP_NAME: "gd32107c-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32107c-eval"} #编译错误 - - {RTT_BSP_NAME: "gd32350r-eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "gd32350r-eval"} #编译错误 - {RTT_BSP_NAME: "hc32l136", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hc32l136"} #编译错误 - {RTT_BSP_NAME: "hk32_hk32f030c8-mini", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "hk32/hk32f030c8-mini"} #scons dist有问题 - {RTT_BSP_NAME: "imx_imx6ull-smart", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "imx/imx6ull-smart"} # toolchainè¿˜æ²¡æ”¯æŒ diff --git a/bsp/README.md b/bsp/README.md index 1627568c0b..5558199b8a 100644 --- a/bsp/README.md +++ b/bsp/README.md @@ -97,13 +97,6 @@ RT-THREAD bsp company list - [mm32f103x](mm32f103x) - 兆易创新GD32 - [gd32](gd32) series - - [gd32350r-eval](gd32350r-eval) - - [gd32450z-eval](gd32450z-eval) - - [gd32e230k-start](gd32e230k-start) - - [gd32vf103v-eval](gd32vf103v-eval) - - [gd32303e-eval](gd32303e-eval) - - [gd32107c-eval](gd32107c-eval) - - [gd32105c-eval](gd32105c-eval) - Realtek - [amebaz](amebaz) - 国民科技N32 diff --git a/bsp/gd32105c-eval/.config b/bsp/gd32105c-eval/.config deleted file mode 100644 index c87443e7b2..0000000000 --- a/bsp/gd32105c-eval/.config +++ /dev/null @@ -1,1063 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_INIT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50002 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=16 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=4 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_MQUEUE is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -# CONFIG_RT_USING_I2C_BITOPS is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -CONFIG_RT_USING_SFUD=y -CONFIG_RT_SFUD_USING_SFDP=y -CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y -# CONFIG_RT_SFUD_USING_QSPI is not set -CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 -# CONFIG_RT_DEBUG_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_KTIME is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# - -# -# Hardware Drivers Config -# - -# -# Onboard Peripheral Drivers -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_GD32F1=y -CONFIG_SOC_GD32105C=y -CONFIG_RT_USING_USART0=y -# CONFIG_RT_USING_USART1 is not set -# CONFIG_RT_USING_USART2 is not set -# CONFIG_RT_USING_UART3 is not set -CONFIG_RT_USING_SPI0=y -# CONFIG_RT_USING_SPI1 is not set -# CONFIG_RT_USING_SPI2 is not set -CONFIG_RT_USING_I2C0=y -# CONFIG_RT_USING_I2C1 is not set - -# -# Board extended module Drivers -# diff --git a/bsp/gd32105c-eval/.ignore_format.yml b/bsp/gd32105c-eval/.ignore_format.yml deleted file mode 100644 index d570c52faf..0000000000 --- a/bsp/gd32105c-eval/.ignore_format.yml +++ /dev/null @@ -1,8 +0,0 @@ -# files format check exclude path, please follow the instructions below to modify; -# If you need to exclude an entire folder, add the folder path in dir_path; -# If you need to exclude a file, add the path to the file in file_path. - -file_path: - -dir_path: -- Libraries diff --git a/bsp/gd32105c-eval/Kconfig b/bsp/gd32105c-eval/Kconfig deleted file mode 100644 index bead9b5eea..0000000000 --- a/bsp/gd32105c-eval/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "drivers/Kconfig" - - - - - diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h deleted file mode 100644 index e525f3c0c6..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h +++ /dev/null @@ -1,381 +0,0 @@ -/*! - \file gd32f10x.h - \brief general definitions for GD32F10x - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_H -#define GD32F10X_H - -#ifdef cplusplus - extern "C" { -#endif - -/* define GD32F10x */ -#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) - /* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */ - /* #define GD32F10X_HD */ /*!< GD32F10X_HD: GD32 High density Value Line devices */ - /* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */ - /* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */ -#endif /* define GD32F10x */ - -#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) - #error "Please select the target GD32F10x device in gd32f10x.h file" -#endif /* undefine GD32F10x tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined HXTAL_VALUE -#ifdef GD32F10X_CL -#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ -#else -#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ -#endif /* HXTAL_VALUE */ -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* GD32F10x firmware library version number V2.0 */ -#define __GD32F10x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __GD32F10x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32F10x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32F10x_STDPERIPH_VERSION ((__GD32F10x_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32F10x_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32F10x_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32F10x_STDPERIPH_VERSION_RC)) - -/* configuration of the Cortex-M3 processor and core peripherals */ -#define __MPU_PRESENT 0 /*!< GD32F10x do not provide MPU */ -#define __NVIC_PRIO_BITS 4 /*!< GD32F10x uses 4 bits for the priority levels */ -#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ -/* define interrupt number */ -typedef enum IRQn -{ - /* Cortex-M3 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 system tick interrupt */ - - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ - RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ - FMC_IRQn = 4, /*!< FMC interrupt */ - RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ - EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ - EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ - EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ - EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ - EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ - DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ - DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ - DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ - DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ - DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ - DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ - -#ifdef GD32F10X_MD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ -#endif /* GD32F10X_MD */ - -#ifdef GD32F10X_HD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ - TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ - TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ - TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - ADC2_IRQn = 47, /*!< ADC2 global interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - SDIO_IRQn = 49, /*!< SDIO global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ -#endif /* GD32F10X_HD */ - -#ifdef GD32F10X_XD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - ADC2_IRQn = 47, /*!< ADC2 global interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - SDIO_IRQn = 49, /*!< SDIO global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ -#endif /* GD32F10X_XD */ - -#ifdef GD32F10X_CL - CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ - USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ - TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ - TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ - TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ - ENET_IRQn = 61, /*!< ENET global interrupt */ - ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS global interrupt */ -#endif /* GD32F10X_CL */ - -} IRQn_Type; - -/* includes */ -#include "core_cm3.h" -#include "system_gd32f10x.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ -#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ - -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ -#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ - -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ -#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */ -#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ -#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ - -/* advanced peripheral bus 2 memory map */ -#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ - -/* advanced high performance bus 1 memory map */ -#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ -#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ -#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - -/* define marco USE_STDPERIPH_DRIVER */ -#if !defined USE_STDPERIPH_DRIVER -#define USE_STDPERIPH_DRIVER -#endif -#ifdef USE_STDPERIPH_DRIVER -#include "gd32f10x_libopt.h" -#endif /* USE_STDPERIPH_DRIVER */ - -#ifdef cplusplus -} -#endif -#endif diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h deleted file mode 100644 index 6bd00fb99d..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h +++ /dev/null @@ -1,60 +0,0 @@ -/*! - \file system_gd32f10x.h - \brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for - GD32F10x Device Series -*/ - -/* - Copyright (c) 2012 ARM LIMITED - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32F10X_H -#define SYSTEM_GD32F10X_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit(void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32F10X_H */ diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s deleted file mode 100644 index a3ffa4c752..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s +++ /dev/null @@ -1,390 +0,0 @@ -;/*! -; \file startup_gd32f10x_cl.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBFS_WKUP_IRQHandler ; 58:USBFS WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; 64:EXMC - DCD 0 ; Reserved - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD ENET_IRQHandler ; 77:Ethernet - DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI line - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT CAN0_TX_IRQHandler [WEAK] - EXPORT CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_IRQHandler [WEAK] - EXPORT TIMER0_UP_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBFS_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_IRQHandler [WEAK] - EXPORT TIMER7_UP_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT ENET_WKUP_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_EWMC_IRQHandler [WEAK] - EXPORT USBFS_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -CAN0_TX_IRQHandler -CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_IRQHandler -TIMER0_UP_IRQHandler -TIMER0_TRG_CMT_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBFS_WKUP_IRQHandler -TIMER7_BRK_IRQHandler -TIMER7_UP_IRQHandler -TIMER7_TRG_CMT_IRQHandler -TIMER7_Channel_IRQHandler -EXMC_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -ENET_IRQHandler -ENET_WKUP_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_EWMC_IRQHandler -USBFS_IRQHandler - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s deleted file mode 100644 index fe768cc3a9..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s +++ /dev/null @@ -1,371 +0,0 @@ -;/*! -; \file startup_gd32f10x_hd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_IRQHandler [WEAK] - EXPORT TIMER0_UP_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_IRQHandler [WEAK] - EXPORT TIMER7_UP_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_4_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_IRQHandler -TIMER0_UP_IRQHandler -TIMER0_TRG_CMT_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -TIMER7_BRK_IRQHandler -TIMER7_UP_IRQHandler -TIMER7_TRG_CMT_IRQHandler -TIMER7_Channel_IRQHandler -ADC2_IRQHandler -EXMC_IRQHandler -SDIO_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_4_IRQHandler - - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s deleted file mode 100644 index c567fee5c1..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s +++ /dev/null @@ -1,328 +0,0 @@ -;/*! -; \file startup_gd32f10x_md.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; 64:EXMC - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_IRQHandler [WEAK] - EXPORT TIMER0_UP_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_IRQHandler -TIMER0_UP_IRQHandler -TIMER0_TRG_CMT_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -EXMC_IRQHandler - - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s deleted file mode 100644 index 3db249b8e5..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s +++ /dev/null @@ -1,371 +0,0 @@ -;/*! -; \file startup_gd32f10x_xd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 global - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 global - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 global - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break Interrupt and TIMER11 global - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update Interrupt and TIMER12 global - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt and TIMER13 global - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] - EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] - EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_4_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_TIMER8_IRQHandler -TIMER0_UP_TIMER9_IRQHandler -TIMER0_TRG_CMT_TIMER10_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -TIMER7_BRK_TIMER11_IRQHandler -TIMER7_UP_TIMER12_IRQHandler -TIMER7_TRG_CMT_TIMER13_IRQHandler -TIMER7_Channel_IRQHandler -ADC2_IRQHandler -EXMC_IRQHandler -SDIO_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_4_IRQHandler - - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s deleted file mode 100644 index 8d614ecf3e..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s +++ /dev/null @@ -1,529 +0,0 @@ -;/*! -; \file startup_gd32f10x_cl.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; Vector Number 35,CAN0 TX - DCD CAN0_RX0_IRQHandler ; Vector Number 36,CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break - DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt - DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; Vector Number 64,EXMC - DCD 0 ; Reserved - DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 - DCD SPI2_IRQHandler ; Vector Number 67,SPI2 - DCD UART3_IRQHandler ; Vector Number 68,UART3 - DCD UART4_IRQHandler ; Vector Number 69,UART4 - DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 - DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 - DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; Vector Number 75,DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; Vector Number 76,DMA1 Channel4 - DCD ENET_IRQHandler ; Vector Number 77,Ethernet - DCD ENET_WKUP_IRQHandler ; Vector Number 78,Ethernet Wakeup through EXTI line - DCD CAN1_TX_IRQHandler ; Vector Number 79,CAN1 TX - DCD CAN1_RX0_IRQHandler ; Vector Number 80,CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; Vector Number 81,CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; Vector Number 82,CAN1 EWMC - DCD USBFS_IRQHandler ; Vector Number 83,USBFS -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_TX_IRQHandler - B CAN0_TX_IRQHandler - - PUBWEAK CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX0_IRQHandler - B CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_IRQHandler - B TIMER0_BRK_IRQHandler - - PUBWEAK TIMER0_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_IRQHandler - B TIMER0_UP_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_IRQHandler - B TIMER0_TRG_CMT_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBFS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_WKUP_IRQHandler - B USBFS_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_IRQHandler - B TIMER7_BRK_IRQHandler - - PUBWEAK TIMER7_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_IRQHandler - B TIMER7_UP_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_IRQHandler - B TIMER7_TRG_CMT_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK ENET_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_WKUP_IRQHandler - B ENET_WKUP_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_EWMC_IRQHandler - B CAN1_EWMC_IRQHandler - - PUBWEAK USBFS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_IRQHandler - B USBFS_IRQHandler - - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s deleted file mode 100644 index 0cd9ade897..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s +++ /dev/null @@ -1,491 +0,0 @@ -;/*! -; \file startup_gd32f10x_hd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break - DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt - DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; Vector Number 63,ADC2 - DCD EXMC_IRQHandler ; Vector Number 64,EXMC - DCD SDIO_IRQHandler ; Vector Number 65,SDIO - DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 - DCD SPI2_IRQHandler ; Vector Number 67,SPI2 - DCD UART3_IRQHandler ; Vector Number 68,UART3 - DCD UART4_IRQHandler ; Vector Number 69,UART4 - DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 - DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 - DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_IRQHandler - B TIMER0_BRK_IRQHandler - - PUBWEAK TIMER0_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_IRQHandler - B TIMER0_UP_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_IRQHandler - B TIMER0_TRG_CMT_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_IRQHandler - B TIMER7_BRK_IRQHandler - - PUBWEAK TIMER7_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_IRQHandler - B TIMER7_UP_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_IRQHandler - B TIMER7_TRG_CMT_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_4_IRQHandler - B DMA1_Channel3_4_IRQHandler - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s deleted file mode 100644 index bc0d386613..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s +++ /dev/null @@ -1,400 +0,0 @@ -;/*! -; \file startup_gd32f10x_md.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break - DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; Vector Number 64,EXMC -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_IRQHandler - B TIMER0_BRK_IRQHandler - - PUBWEAK TIMER0_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_IRQHandler - B TIMER0_UP_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_IRQHandler - B TIMER0_TRG_CMT_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s deleted file mode 100644 index 4f52b7d5fa..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s +++ /dev/null @@ -1,491 +0,0 @@ -;/*! -; \file startup_gd32f10x_xd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; Vector Number 40,TIMER0 Break and TIMER8 global - DCD TIMER0_UP_TIMER9_IRQHandler ; Vector Number 41,TIMER0 Update and TIMER9 global - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_TIMER11_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt and TIMER11 global - DCD TIMER7_UP_TIMER12_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt and TIMER12 global - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 global - DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; Vector Number 63,ADC2 - DCD EXMC_IRQHandler ; Vector Number 64,EXMC - DCD SDIO_IRQHandler ; Vector Number 65,SDIO - DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 - DCD SPI2_IRQHandler ; Vector Number 67,SPI2 - DCD UART3_IRQHandler ; Vector Number 68,UART3 - DCD UART4_IRQHandler ; Vector Number 69,UART4 - DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 - DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 - DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_TIMER8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_TIMER8_IRQHandler - B TIMER0_BRK_TIMER8_IRQHandler - - PUBWEAK TIMER0_UP_TIMER9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_TIMER9_IRQHandler - B TIMER0_UP_TIMER9_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_TIMER10_IRQHandler - B TIMER0_TRG_CMT_TIMER10_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_TIMER11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_TIMER11_IRQHandler - B TIMER7_BRK_TIMER11_IRQHandler - - PUBWEAK TIMER7_UP_TIMER12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_TIMER12_IRQHandler - B TIMER7_UP_TIMER12_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_TIMER13_IRQHandler - B TIMER7_TRG_CMT_TIMER13_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_4_IRQHandler - B DMA1_Channel3_4_IRQHandler - - END diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c b/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c deleted file mode 100644 index 699179711a..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c +++ /dev/null @@ -1,1028 +0,0 @@ -/*! - \file system_gd32f10x.c - \brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for - GD32F10x Device Series -*/ - -/* - Copyright (c) 2012 ARM LIMITED - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32f10x.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -/* select a system clock by uncommenting the following line */ -/* use IRC8M */ -//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) - -/* use HXTAL (XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */ -//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) -//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) -//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) -//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) -#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) - -#define SEL_IRC8M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLL 0x02U - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; -static void system_clock_48m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; -static void system_clock_72m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; -static void system_clock_108m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; -static void system_clock_hxtal(void); -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; -static void system_clock_24m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; -static void system_clock_36m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; -static void system_clock_48m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; -static void system_clock_56m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; -static void system_clock_96m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; -static void system_clock_108m_hxtal(void); -#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_HXTAL - system_clock_hxtal(); -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) - system_clock_24m_hxtal(); -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) - system_clock_36m_hxtal(); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) - system_clock_48m_hxtal(); -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) - system_clock_56m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) - system_clock_96m_hxtal(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) - system_clock_108m_hxtal(); - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) - system_clock_48m_irc8m(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) - system_clock_108m_irc8m(); -#endif /* __SYSTEM_CLOCK_HXTAL */ -} - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit(void) -{ - /* reset the RCC clock configuration to the default reset state */ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); - - /* reset HXTALEN, CKMEN, PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - - /* Reset HXTALBPS bit */ - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - - /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ - -#ifdef GD32F10X_CL - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); - - RCU_CFG1 = 0x00000000U; -#else - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | - RCU_CFG0_USBDPSC | RCU_CFG0_PLLMF_4); -#endif /* GD32F10X_CL */ - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* reset HXTALEN, CKMEN and PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x009F0000U; -#elif defined(GD32F10X_CL) - /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x00FF0000U; -#endif - - /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ - system_clock_config(); -} - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate(void) -{ - uint32_t scss; - uint32_t pllsel, predv0sel, pllmf, ck_src; -#ifdef GD32F10X_CL - uint32_t predv0, predv1, pll1mf; -#endif /* GD32F10X_CL */ - - scss = GET_BITS(RCU_CFG0, 2, 3); - - switch (scss) - { - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - - if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE / 2U; - }else{ - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); - - /* PREDV0 input source clock divided by 2 */ - if(RCU_CFG0_PREDV0 == predv0sel){ - ck_src = HXTAL_VALUE / 2U; - } -#elif defined(GD32F10X_CL) - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - - /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ - pllmf |= 0x10U; - } - - if(pllmf >= 15U){ - pllmf += 1U; - }else{ - pllmf += 2U; - } - - SystemCoreClock = ck_src * pllmf; - -#ifdef GD32F10X_CL - if(15U == pllmf){ - /* PLL source clock multiply by 6.5 */ - SystemCoreClock = ck_src * 6U + ck_src / 2U; - } -#endif /* GD32F10X_CL */ - - break; - - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } -} - -#ifdef __SYSTEM_CLOCK_HXTAL -/*! - \brief configure the system clock to HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) -/*! - \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_24m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 6 = 24 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL6; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) -/*! - \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_36m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 9 = 36 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL9; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -/*! - \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL12; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) -/*! - \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_56m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 14 = 56 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL14; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL18; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -/*! - \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL24; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -/*! - \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL27; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) -/*! - \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL12; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL18; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -/*! - \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL27; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#endif diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/core_cm3.h b/bsp/gd32105c-eval/Libraries/CMSIS/core_cm3.h deleted file mode 100644 index 1b661b4421..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/core_cm3.h +++ /dev/null @@ -1,1638 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32105c-eval/Libraries/CMSIS/core_cmFunc.h deleted file mode 100644 index 01089f1333..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,637 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32105c-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32105c-eval/Libraries/CMSIS/core_cmInstr.h deleted file mode 100644 index 856b4c3c61..0000000000 --- a/bsp/gd32105c-eval/Libraries/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,880 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h deleted file mode 100644 index bb61cd73b5..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h +++ /dev/null @@ -1,368 +0,0 @@ -/*! - \file gd32f10x_adc.h - \brief definitions for the ADC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_ADC_H -#define GD32F10x_ADC_H - -#include "gd32f10x.h" - -/* ADC definitions */ -#define ADC0 ADC_BASE -#define ADC1 (ADC_BASE + 0x400U) -#define ADC2 (ADC_BASE + 0x1800U) - -/* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - -/* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx x=0..2 */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ -#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ - -/* constants definitions */ -/* adc_stat register value */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - -/* scan mode */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ - -/* inserted channel group convert automatically */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ - -/* ADC sync mode */ -#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ -#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ -#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ -#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ - -/* adc_ctl1 register value */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ - -/* continuous mode */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -/* for ADC0 and ADC1 regular channel */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ -/* for ADC2 regular channel */ -#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */ -#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */ -#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */ - -/* external trigger mode for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -/* for ADC0 and ADC1 inserted channel */ -#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */ -#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ -/* for ADC2 inserted channel */ -#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */ -#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */ -#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */ -#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */ -#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - -/* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - -/* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - -/* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - -/* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ - -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ - -/* ADC interrupt */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* function declarations */ -/* initialization config */ -/* reset ADC */ -void adc_deinit(uint32_t adc_periph); -/* configure the ADC sync mode */ -void adc_mode_config(uint32_t mode); -/* enable or disable ADC special function */ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); -/* enable ADC interface */ -void adc_enable(uint32_t adc_periph); -/* disable ADC interface */ -void adc_disable(uint32_t adc_periph); -/* ADC calibration and reset calibration */ -void adc_calibration_enable(uint32_t adc_periph); -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); - -/* DMA config */ -/* enable DMA request */ -void adc_dma_mode_enable(uint32_t adc_periph); -/* disable DMA request */ -void adc_dma_mode_disable(uint32_t adc_periph); - -/* regular group and inserted group config */ -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); - -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); - -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); -/* configure ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); - -/* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); -/* read the last ADC0 and ADC1 conversion result data in sync mode */ -uint32_t adc_sync_mode_convert_value_read(void); - -/* watchdog config */ -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); - -/* interrupt & flag functions */ -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); -/* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); -/* get the bit state of ADCx software inserted channel start conversion */ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); - -#endif /* GD32F10x_ADC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h deleted file mode 100644 index 73f93252fe..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h +++ /dev/null @@ -1,230 +0,0 @@ -/*! - \file gd32f10x_bkp.h - \brief definitions for the BKP - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_BKP_H -#define GD32F10X_BKP_H - -#include "gd32f10x.h" - -/* BKP definitions */ -#define BKP BKP_BASE /*!< BKP base address */ - -/* registers definitions */ -#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ -#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ -#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ -#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ -#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ -#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ -#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ -#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ -#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ -#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ -#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ -#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ -#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ -#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ -#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ -#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ -#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ -#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ -#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ -#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ -#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ -#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ -#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ -#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ -#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ -#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ -#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ -#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ -#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ -#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ -#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ -#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ -#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ -#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ -#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ -#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ -#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ -#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ -#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ -#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ -#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ -#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ -#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ -#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ -#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ - -/* bits definitions */ -/* BKP_DATA */ -#define BKP_DATA BITS(0,15) /*!< backup data */ - -/* BKP_OCTL */ -#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ -#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ -#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ - -/* BKP_TPCTL */ -#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ -#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ - -/* BKP_TPCS */ -#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ -#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ -#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ -#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ -#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ - -/* constants definitions */ -/* BKP data register number */ -typedef enum -{ - BKP_DATA_0 = 1, /*!< BKP data register 0 */ - BKP_DATA_1, /*!< BKP data register 1 */ - BKP_DATA_2, /*!< BKP data register 2 */ - BKP_DATA_3, /*!< BKP data register 3 */ - BKP_DATA_4, /*!< BKP data register 4 */ - BKP_DATA_5, /*!< BKP data register 5 */ - BKP_DATA_6, /*!< BKP data register 6 */ - BKP_DATA_7, /*!< BKP data register 7 */ - BKP_DATA_8, /*!< BKP data register 8 */ - BKP_DATA_9, /*!< BKP data register 9 */ - BKP_DATA_10, /*!< BKP data register 10 */ - BKP_DATA_11, /*!< BKP data register 11 */ - BKP_DATA_12, /*!< BKP data register 12 */ - BKP_DATA_13, /*!< BKP data register 13 */ - BKP_DATA_14, /*!< BKP data register 14 */ - BKP_DATA_15, /*!< BKP data register 15 */ - BKP_DATA_16, /*!< BKP data register 16 */ - BKP_DATA_17, /*!< BKP data register 17 */ - BKP_DATA_18, /*!< BKP data register 18 */ - BKP_DATA_19, /*!< BKP data register 19 */ - BKP_DATA_20, /*!< BKP data register 20 */ - BKP_DATA_21, /*!< BKP data register 21 */ - BKP_DATA_22, /*!< BKP data register 22 */ - BKP_DATA_23, /*!< BKP data register 23 */ - BKP_DATA_24, /*!< BKP data register 24 */ - BKP_DATA_25, /*!< BKP data register 25 */ - BKP_DATA_26, /*!< BKP data register 26 */ - BKP_DATA_27, /*!< BKP data register 27 */ - BKP_DATA_28, /*!< BKP data register 28 */ - BKP_DATA_29, /*!< BKP data register 29 */ - BKP_DATA_30, /*!< BKP data register 30 */ - BKP_DATA_31, /*!< BKP data register 31 */ - BKP_DATA_32, /*!< BKP data register 32 */ - BKP_DATA_33, /*!< BKP data register 33 */ - BKP_DATA_34, /*!< BKP data register 34 */ - BKP_DATA_35, /*!< BKP data register 35 */ - BKP_DATA_36, /*!< BKP data register 36 */ - BKP_DATA_37, /*!< BKP data register 37 */ - BKP_DATA_38, /*!< BKP data register 38 */ - BKP_DATA_39, /*!< BKP data register 39 */ - BKP_DATA_40, /*!< BKP data register 40 */ - BKP_DATA_41, /*!< BKP data register 41 */ -}bkp_data_register_enum; - -/* BKP register */ -#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) -#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) - -/* get data of BKP data register */ -#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - -/* RTC clock calibration value */ -#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/* RTC output selection */ -#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ -#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ - -/* tamper pin active level */ -#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ -#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ - -/* tamper flag */ -#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ - -/* tamper interrupt flag */ -#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ -/* function declarations */ -/* reset BKP registers */ -void bkp_deinit(void); -/* write BKP data register */ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); -/* read BKP data register */ -uint16_t bkp_data_read(bkp_data_register_enum register_number); - -/* RTC related functions */ -/* enable RTC clock calibration output */ -void bkp_rtc_calibration_output_enable(void); -/* disable RTC clock calibration output */ -void bkp_rtc_calibration_output_disable(void); -/* enable RTC alarm or second signal output */ -void bkp_rtc_signal_output_enable(void); -/* disable RTC alarm or second signal output */ -void bkp_rtc_signal_output_disable(void); -/* select RTC output */ -void bkp_rtc_output_select(uint16_t outputsel); -/* set RTC clock calibration value */ -void bkp_rtc_calibration_value_set(uint8_t value); - -/* tamper pin related functions */ -/* enable tamper pin detection */ -void bkp_tamper_detection_enable(void); -/* disable tamper pin detection */ -void bkp_tamper_detection_disable(void); -/* set tamper pin active level */ -void bkp_tamper_active_level_set(uint16_t level); - -/* interrupt & flag functions */ -/* enable tamper interrupt */ -void bkp_interrupt_enable(void); -/* disable tamper interrupt */ -void bkp_interrupt_disable(void); -/* get tamper flag state */ -FlagStatus bkp_flag_get(void); -/* clear tamper flag state */ -void bkp_flag_clear(void); -/* get tamper interrupt flag state */ -FlagStatus bkp_interrupt_flag_get(void); -/* clear tamper interrupt flag state */ -void bkp_interrupt_flag_clear(void); - -#endif /* GD32F10X_BKP_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h deleted file mode 100644 index 0e5ae1f251..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h +++ /dev/null @@ -1,725 +0,0 @@ -/*! - \file gd32f10x_can.h - \brief definitions for the CAN - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_CAN_H -#define GD32F10x_CAN_H - -#include "gd32f10x.h" - -/* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ - -/* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ - -/* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ - -/* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ - -/* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ - -/* bits definitions */ -/* CAN_CTL */ -#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ -#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ -#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ -#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ -#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ -#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ -#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ -#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ -#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ -#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ - -/* CAN_STAT */ -#define CAN_STAT_IWS BIT(0) /*!< initial working state */ -#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ -#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ -#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ -#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ -#define CAN_STAT_TS BIT(8) /*!< transmitting state */ -#define CAN_STAT_RS BIT(9) /*!< receiving state */ -#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ -#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ - -/* CAN_TSTAT */ -#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ -#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ -#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ -#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ -#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ -#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ -#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ -#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ -#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ -#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ -#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ -#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ -#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ -#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ -#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ -#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ -#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ -#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ -#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ -#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ -#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - -/* CAN_RFIFO0 */ -#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ -#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ -#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - -/* CAN_RFIFO1 */ -#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ -#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ -#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ - -/* CAN_INTEN */ -#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ -#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ -#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ -#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ -#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ -#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ -#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ -#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ -#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ - -/* CAN_ERR */ -#define CAN_ERR_WERR BIT(0) /*!< warning error */ -#define CAN_ERR_PERR BIT(1) /*!< passive error */ -#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ -#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ -#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ -#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ - -/* CAN_BT */ -#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ -#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ -#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ -#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ -#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ -#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - -/* CAN_TMIx */ -#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ -#define CAN_TMI_FT BIT(1) /*!< frame type */ -#define CAN_TMI_FF BIT(2) /*!< frame format */ -#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_TMPx */ -#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ -#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_TMDATA0x */ -#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ -#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ -#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ -#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ - -/* CAN_TMDATA1x */ -#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ -#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ -#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ -#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ - -/* CAN_RFIFOMIx */ -#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ -#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ -#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_RFIFOMPx */ -#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ -#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ -#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_RFIFOMDATA0x */ -#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ -#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ -#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ -#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ - -/* CAN_RFIFOMDATA1x */ -#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ -#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ -#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ -#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ - -/* CAN_FCTL */ -#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ -#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ - -/* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ - -/* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ - -/* CAN_FAFIFO */ -#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ - -/* CAN_FW */ -#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ - -/* CAN_FxDATAy */ -#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ - -/* consts definitions */ -/* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) -#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ -#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ -#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ -#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ -#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ - -/* CAN flags */ -typedef enum -{ - /* flags in TSTAT register */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ - /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ - /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ - /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -}can_flag_enum; - -/* CAN interrupt flags */ -typedef enum -{ - /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ - /* interrupt flags in TSTAT register */ - CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ - CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ - CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ -}can_interrupt_flag_enum; - -/* CAN initiliaze parameters struct */ -typedef struct -{ - uint8_t working_mode; /*!< CAN working mode */ - uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ - uint8_t time_segment_1; /*!< time segment 1 */ - uint8_t time_segment_2; /*!< time segment 2 */ - ControlStatus time_triggered; /*!< time triggered communication mode */ - ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ - ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ - ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ - ControlStatus trans_fifo_order; /*!< transmit FIFO order */ - uint16_t prescaler; /*!< baudrate prescaler */ -}can_parameter_struct; - -/* CAN transmit message struct */ -typedef struct -{ - uint32_t tx_sfid; /*!< standard format frame identifier */ - uint32_t tx_efid; /*!< extended format frame identifier */ - uint8_t tx_ff; /*!< format of frame, standard or extended format */ - uint8_t tx_ft; /*!< type of frame, data or remote */ - uint8_t tx_dlen; /*!< data length */ - uint8_t tx_data[8]; /*!< transmit data */ -}can_trasnmit_message_struct; - -/* CAN receive message struct */ -typedef struct -{ - uint32_t rx_sfid; /*!< standard format frame identifier */ - uint32_t rx_efid; /*!< extended format frame identifier */ - uint8_t rx_ff; /*!< format of frame, standard or extended format */ - uint8_t rx_ft; /*!< type of frame, data or remote */ - uint8_t rx_dlen; /*!< data length */ - uint8_t rx_data[8]; /*!< receive data */ - uint8_t rx_fi; /*!< filtering index */ -} can_receive_message_struct; - -/* CAN filter parameters struct */ -typedef struct -{ - uint16_t filter_list_high; /*!< filter list number high bits*/ - uint16_t filter_list_low; /*!< filter list number low bits */ - uint16_t filter_mask_high; /*!< filter mask number high bits */ - uint16_t filter_mask_low; /*!< filter mask number low bits */ - uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ - uint16_t filter_number; /*!< filter number */ - uint16_t filter_mode; /*!< filter mode, list or mask */ - uint16_t filter_bits; /*!< filter scale */ - ControlStatus filter_enable; /*!< filter work or not */ -}can_filter_parameter_struct; - -/* CAN errors */ -typedef enum -{ - CAN_ERROR_NONE = 0, /*!< no error */ - CAN_ERROR_FILL, /*!< fill error */ - CAN_ERROR_FORMATE, /*!< format error */ - CAN_ERROR_ACK, /*!< ACK error */ - CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ - CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ - CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG, /*!< software configure */ -}can_error_enum; - -/* transmit states */ -typedef enum -{ - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ -}can_transmit_state_enum; - -typedef enum -{ - CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ - CAN_FILTER_STRUCT, /* CAN filter parameters struct */ - CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ - CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -}can_struct_type_enum; - -/* CAN baudrate prescaler*/ -#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) - -/* CAN bit segment 1*/ -#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) - -/* CAN bit segment 2*/ -#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) - -/* CAN resynchronization jump width*/ -#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) - -/* CAN communication mode*/ -#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) - -/* CAN FDATA high 16 bits */ -#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) - -/* CAN FDATA low 16 bits */ -#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) - -/* CAN1 filter start bank_number*/ -#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) - -/* CAN transmit mailbox extended identifier*/ -#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) - -/* CAN transmit mailbox standard identifier*/ -#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) - -/* transmit data byte 0 */ -#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 1 */ -#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 2 */ -#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 3 */ -#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* transmit data byte 4 */ -#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 5 */ -#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 6 */ -#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 7 */ -#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* receive mailbox extended identifier*/ -#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) - -/* receive mailbox standrad identifier*/ -#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) - -/* receive data length */ -#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) - -/* the index of the filter by which the frame is passed */ -#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 0 */ -#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 1 */ -#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 2 */ -#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 3 */ -#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* receive data byte 4 */ -#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 5 */ -#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 6 */ -#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 7 */ -#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* error number */ -#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) - -/* transmit error count */ -#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive error count */ -#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* CAN errors */ -#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ - -#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ - -/* CAN communication mode */ -#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ -#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ -#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ -#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ - -/* CAN resynchronisation jump width */ -#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ - -/* CAN time segment 1 */ -#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ -#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ -#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ -#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ -#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ -#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ -#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ -#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ -#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ - -/* CAN time segment 2 */ -#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ - -/* CAN mailbox number */ -#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ -#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ -#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ -#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ - -/* CAN frame format */ -#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ -#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ - -/* CAN receive fifo */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ - -/* frame number of receive fifo */ -#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ - -#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ -#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ - -/* CAN working mode */ -#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ -#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ -#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ - -/* filter bits */ -#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ -#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ - -/* filter mode */ -#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ -#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ - -/* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ - -/* frame type */ -#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ -#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ - -/* CAN timeout */ -#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ - -/* interrupt enable bits */ -#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ -#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ -#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ -#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ -#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ -#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ -#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ -#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ -#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ -#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ - -/* function declarations */ -/* deinitialize CAN */ -void can_deinit(uint32_t can_periph); -/* initialize CAN struct */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct); -/* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); -/* set can1 fliter start bank number */ -void can1_filter_start_bank(uint8_t start_bank); -/* enable functions */ -/* CAN debug freeze enable */ -void can_debug_freeze_enable(uint32_t can_periph); -/* CAN debug freeze disable */ -void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time trigger mode enable */ -void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time trigger mode disable */ -void can_time_trigger_mode_disable(uint32_t can_periph); - -/* transmit functions */ -/* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); -/* get CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); -/* stop CAN transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); -/* CAN release fifo */ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive message length */ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); -/* CAN working mode */ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); -/* CAN wakeup from sleep mode */ -ErrStatus can_wakeup(uint32_t can_periph); - -/* CAN get error */ -can_error_enum can_error_get(uint32_t can_periph); -/* get CAN receive error number */ -uint8_t can_receive_error_number_get(uint32_t can_periph); -/* get CAN transmit error number */ -uint8_t can_transmit_error_number_get(uint32_t can_periph); - -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* CAN get flag state */ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); -/* CAN clear flag state */ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag); -/* CAN get interrupt flag state */ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); -/* CAN clear interrupt flag state */ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); - -#endif /* GD32F10x_CAN_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h deleted file mode 100644 index 9f2781ff26..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h +++ /dev/null @@ -1,81 +0,0 @@ -/*! - \file gd32f10x_crc.h - \brief definitions for the CRC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_CRC_H -#define GD32F10X_CRC_H - -#include "gd32f10x.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* reset data register to the value of initializaiton data register */ -void crc_data_register_reset(void); -/* read the value of the data register */ -uint32_t crc_data_register_read(void); - -/* read the value of the free data register */ -uint8_t crc_free_data_register_read(void); -/* write data to the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* calculate the CRC value of a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* calculate the CRC value of an array of 32-bit values */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32F10X_CRC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h deleted file mode 100644 index aa9e70bbf8..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h +++ /dev/null @@ -1,250 +0,0 @@ -/*! - \file gd32f10x_dac.h - \brief definitions for the DAC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_DAC_H -#define GD32F10X_DAC_H - -#include "gd32f10x.h" - -/* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 0U -#define DAC1 1U - -/* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ - -/* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - -/* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - -/* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - -/* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - -/* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - -/* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - -/* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - -/* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - -/* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - -/* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - -/* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - -/* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ - -/* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ - -/* constants definitions */ -/* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ -#elif defined(GD32F10X_CL) -#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - -/* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - -/* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ - -/* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ - -/* function declarations */ -/* initialization functions */ -/* deinitialize DAC */ -void dac_deinit(void); -/* enable DAC */ -void dac_enable(uint32_t dac_periph); -/* disable DAC */ -void dac_disable(uint32_t dac_periph); -/* enable DAC DMA */ -void dac_dma_enable(uint32_t dac_periph); -/* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); -/* enable DAC output buffer */ -void dac_output_buffer_enable(uint32_t dac_periph); -/* disable DAC output buffer */ -void dac_output_buffer_disable(uint32_t dac_periph); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); - -/* DAC trigger configuration */ -/* enable DAC trigger */ -void dac_trigger_enable(uint32_t dac_periph); -/* disable DAC trigger */ -void dac_trigger_disable(uint32_t dac_periph); -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); -/* enable DAC software trigger */ -void dac_software_trigger_enable(uint32_t dac_periph); -/* disable DAC software trigger */ -void dac_software_trigger_disable(uint32_t dac_periph); - -/* DAC wave mode configuration */ -/* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); -/* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); -/* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); - -/* DAC concurrent mode configuration */ -/* enable DAC concurrent mode */ -void dac_concurrent_enable(void); -/* disable DAC concurrent mode */ -void dac_concurrent_disable(void); -/* enable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_enable(void); -/* disable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_disable(void); -/* enable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_enable(void); -/* disable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_disable(void); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); - -#endif /* GD32F10X_DAC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h deleted file mode 100644 index d9248414b8..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h +++ /dev/null @@ -1,152 +0,0 @@ -/*! - \file gd32f10x_dbg.h - \brief definitions for the DBG - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_DBG_H -#define GD32F10X_DBG_H - -#include "gd32f10x.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL */ -#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ -#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ -#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ -#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ -#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ -#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ -#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ -#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ -#define DBG_CTL_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ -#define DBG_CTL_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ -#ifdef GD32F10x_CL -#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ -#endif /* GD32F10x_CL */ -#ifdef GD32F10X_XD -#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ -#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ -#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ -#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ -#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ -#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ -#endif /* GD32F10x_XD */ - -/* constants definitions */ -/* debug hold when core is halted */ -typedef enum -{ - DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ - DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ - DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ - DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ - DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ - DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ - DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ -#ifdef GD32F10x_CL - DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ -#endif /* GD32F10x_CL */ -#if (defined(GD32F10x_XD) || defined(GD32F10x_CL)) - DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ - DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ -#endif /* GD32F10x_XD || GD32F10x_CL*/ -}dbg_periph_enum; - -/* DBG low power mode configurations */ -#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* DBG_CTL0_TRACE_MODE configurations */ -#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) -#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ -#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ -#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ -#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ - -/* function declarations */ -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* low power behavior configuration */ -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* peripheral behavior configuration */ -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -/* trace pin assignment configuration */ -/* enable trace pin assignment */ -void dbg_trace_pin_enable(void); -/* disable trace pin assignment */ -void dbg_trace_pin_disable(void); -/* set trace pin mode */ -void dbg_trace_pin_mode_set(uint32_t trace_mode); - -#endif /* GD32F10x_DBG_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h deleted file mode 100644 index 3a90e8d690..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h +++ /dev/null @@ -1,289 +0,0 @@ -/*! - \file gd32f10x_dma.h - \brief definitions for the DMA - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_DMA_H -#define GD32F10X_DMA_H - -#include "gd32f10x.h" - -/* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ - -/* registers definitions */ -#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ - -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ - -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ - -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ - -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ - -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ - -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ - -#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL, x=0..6 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT, x=0..6 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR, x=0..6 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR, x=0..6 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA channel 0 */ - DMA_CH1, /*!< DMA channel 1 */ - DMA_CH2, /*!< DMA channel 2 */ - DMA_CH3, /*!< DMA channel 3 */ - DMA_CH4, /*!< DMA channel 4 */ - DMA_CH5, /*!< DMA channel 5 */ - DMA_CH6 /*!< DMA channel 6 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ - -} dma_parameter_struct; - -#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_register address */ -#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ -/* circular mode */ -#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */ -#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ - -/* memory to memory mode */ -#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ -#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ - -/* function declarations */ -/* DMA deinitialization and initialization functions */ -/* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); -/* initialize the parameters of DMA struct with the default values */ -void dma_struct_para_init(dma_parameter_struct* init_struct); -/* initialize DMA channel */ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); -/* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); - -/* DMA configuration functions */ -/* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set DMA memory base address */ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); - -/* flag and interrupt functions */ -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the flag of a DMA channel */ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the interrupt flag of a DMA channel */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); - -#endif /* GD32F10X_DMA_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h deleted file mode 100644 index 310fb2f8d8..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h +++ /dev/null @@ -1,1498 +0,0 @@ -/*! - \file gd32f10x_enet.h - \brief definitions for the ENET - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_ENET_H -#define GD32F10x_ENET_H - -#include "gd32f10x.h" -#include - -#define IF_USE_EXTERNPHY_LIB 0 -#if (1 == IF_USE_EXTERNPHY_LIB) -#include "phy.h" -#endif - -#ifndef ENET_RXBUF_NUM -#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ -#endif - -#ifndef ENET_TXBUF_NUM -#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ -#endif - -#ifndef ENET_RXBUF_SIZE -#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ -#endif - -#ifndef ENET_TXBUF_SIZE -#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ -#endif - -/* #define USE_DELAY */ - -#ifndef _PHY_H_ -#define DP83848 0 -#define LAN8700 1 -#define PHY_TYPE DP83848 - -#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ - -/* PHY read write timeouts */ -#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ -#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ - -/* PHY delay */ -#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ -#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ - -/* PHY register address */ -#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ -#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ - -/* PHY basic control register */ -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ - -/* PHY basic status register */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ - -#if(PHY_TYPE == LAN8700) -#define PHY_SR 31U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ -#elif(PHY_TYPE == DP83848) -#define PHY_SR 16U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ -#endif /* PHY_TYPE */ - -#endif /* _PHY_H_ */ - - -/* ENET definitions */ -#define ENET ENET_BASE - -/* registers definitions */ -#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ -#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ -#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ -#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ -#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ -#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ -#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ -#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ -#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ -#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ -#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ -#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ -#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ -#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ -#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ -#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ -#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ -#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ -#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ -#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ - -#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ -#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ -#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ -#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ -#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ -#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ -#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ -#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ -#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ -#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ -#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ - -#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ -#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ -#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ -#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ -#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ -#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ -#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ -#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ - -#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ -#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ -#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ -#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ -#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ -#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ -#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ -#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ -#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ -#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ -#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ - -/* bits definitions */ -/* ENET_MAC_CFG */ -#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ -#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ -#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ -#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ -#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ -#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ -#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ -#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ -#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ -#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ -#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ -#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ -#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ -#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ - -/* ENET_MAC_FRMF */ -#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ -#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - -/* ENET_MAC_HLH */ -#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - -/* ENET_MAC_HLL */ -#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - -/* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - -/* ENET_MAC_PHY_DATA */ -#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - -/* ENET_MAC_FCTL */ -#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ -#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ -#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ -#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ -#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ -#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - -/* ENET_MAC_FCTH */ -#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ -#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - -/* ENET_MAC_VLT */ -#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ -#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - -/* ENET_MAC_RWFF */ -#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ -#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ -#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ -#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ -#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ -#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ -#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ -#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ - -/* ENET_MAC_INTF */ -#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ -#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ -#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ -#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ -#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ - -/* ENET_MAC_INTMSK */ -#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ -#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ - -/* ENET_MAC_ADDR0H */ -#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ -#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - -/* ENET_MAC_ADDR0L */ -#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - -/* ENET_MAC_ADDR1H */ -#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR1L */ -#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - -/* ENET_MAC_ADDR2H */ -#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ -#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR2L */ -#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - -/* ENET_MAC_ADDR3H */ -#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ -#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR3L */ -#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - -/* ENET_MSC_CTL */ -#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ -#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ -#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ -#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ - -/* ENET_MSC_RINTF */ -#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ -#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ -#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - -/* ENET_MSC_TINTF */ -#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ -#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ -#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ - -/* ENET_MSC_RINTMSK */ -#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ -#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ -#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - -/* ENET_MSC_TINTMSK */ -#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - -/* ENET_MSC_SCCNT */ -#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - -/* ENET_MSC_MSCCNT */ -#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - -/* ENET_MSC_TGFCNT */ -#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - -/* ENET_MSC_RFCECNT */ -#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - -/* ENET_MSC_RFAECNT */ -#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - -/* ENET_MSC_RGUFCNT */ -#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - -/* ENET_PTP_TSCTL */ -#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ -#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ -#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ -#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ -#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ -#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ - -/* ENET_PTP_SSINC */ -#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - -/* ENET_PTP_TSH */ -#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - -/* ENET_PTP_TSL */ -#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ -#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - -/* ENET_PTP_TSUH */ -#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - -/* ENET_PTP_TSUL */ -#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ -#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ - -/* ENET_PTP_TSADDEND */ -#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ - -/* ENET_PTP_ETH */ -#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - -/* ENET_PTP_ETL */ -#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - -/* ENET_DMA_BCTL */ -#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ -#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ -#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ -#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ -#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ -#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ -#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ -#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ -#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ -#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ - -/* ENET_DMA_TPEN */ -#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - -/* ENET_DMA_RPEN */ -#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ - -/* ENET_DMA_RDTADDR */ -#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - -/* ENET_DMA_TDTADDR */ -#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - -/* ENET_DMA_STAT */ -#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ -#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ -#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ -#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ -#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ -#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ -#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ -#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ -#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ -#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ -#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ -#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ -#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ -#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ -#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ -#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ -#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ -#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ -#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ -#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ -#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - -/* ENET_DMA_CTL */ -#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ -#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ -#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ -#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ -#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ -#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ -#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ -#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ -#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ -#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ -#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ -#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - -/* ENET_DMA_INTEN */ -#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ -#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ -#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ -#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ -#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ -#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ -#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ -#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ -#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ -#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ -#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ -#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ -#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - -/* ENET_DMA_MFBOCNT */ -#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ -#define ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */ -#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ -#define ENET_DMA_MFBOCNT_OBFOC BIT(28) /*!< Overflow bit for FIFO overflow counter */ - -/* ENET_DMA_CTDADDR */ -#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ - -/* ENET_DMA_CRDADDR */ -#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - -/* ENET_DMA_CTBADDR */ -#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - -/* ENET_DMA_CRBADDR */ -#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ - -/* ENET DMA Tx descriptor TDES0 */ -#define ENET_TDES0_DB BIT(0) /*!< deferred */ -#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ -#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ -#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ -#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ -#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ -#define ENET_TDES0_LCO BIT(9) /*!< late collision */ -#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ -#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ -#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ -#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ -#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ -#define ENET_TDES0_ES BIT(15) /*!< error summary */ -#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ -#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ -#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ -#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ -#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ -#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ -#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ -#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ -#define ENET_TDES0_FSG BIT(28) /*!< first segment */ -#define ENET_TDES0_LSG BIT(29) /*!< last segment */ -#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ -#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ - -/* ENET DMA Tx descriptor TDES1 */ -#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ -#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ - -/* ENET DMA Tx descriptor TDES2 */ -#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ - -/* ENET DMA Tx descriptor TDES3 */ -#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ - -/* ENET DMA Rx descriptor RDES0 */ -#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ -#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ -#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ -#define ENET_RDES0_RERR BIT(3) /*!< receive error */ -#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ -#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ -#define ENET_RDES0_LCO BIT(6) /*!< late collision */ -#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ -#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ -#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ -#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ -#define ENET_RDES0_LERR BIT(12) /*!< length error */ -#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ -#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ -#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ -#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ -#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ -#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ - -/* ENET DMA Rx descriptor RDES1 */ -#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ -#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ -#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ -#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ -#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ - -/* ENET DMA Rx descriptor RDES2 */ -#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ - -/* ENET DMA Rx descriptor RDES3 */ -#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ - -/* constants definitions */ -/* define bit position and its register index offset */ -#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) -#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* ENET clock range judgement */ -#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) - -/* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) -#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) -#define ENET_ADDRH_BASE ((ENET) + 0x40U) -#define ENET_ADDRL_BASE ((ENET) + 0x44U) -#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) - -/* register offset */ -#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ -#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ -#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ -#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ - -#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ -#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ -#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ -#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ -#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ -#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ -#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ -#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ -#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ -#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ - -#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ -#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ -#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ -#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ -#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ -#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ -#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ -#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ - -/* ENET status flag get */ -typedef enum -{ - /* ENET_MAC_WUM register */ - ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ - /* ENET_MAC_FCTL register */ - ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ - /* ENET_MAC_INTF register */ - ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ - ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ - ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ - ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_flag_enum; - -/* ENET stutus flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_flag_clear_enum; - -/* ENET interrupt enable/disable */ -typedef enum -{ - /* ENET_MAC_INTMSK register */ - ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ - ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ - ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ - ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ - ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ - ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ - ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ - ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ - ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ - ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ - ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ - ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ - ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ - ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ - ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ - ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ - ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ - ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ - ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ - ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ - ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ - ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ - ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ -}enet_int_enum; - -/* ENET interrupt flag get */ -typedef enum -{ - /* ENET_MAC_INTF register */ - ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_int_flag_enum; - -/* ENET interrupt flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_int_flag_clear_enum; - -/* current RX/TX descriptor/buffer/descriptor table address get */ -typedef enum -{ - ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ - ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ - ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ - ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ - ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ - ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ -}enet_desc_reg_enum; - -/* MAC statistics counter get */ -typedef enum -{ - ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ - ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ - ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ - ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ - ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ - ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; - -/* function option, used for ENET initialization */ -typedef enum -{ - FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ - DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ - DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ - DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ - STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ - DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ - VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ - FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ - HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ - HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ - FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ - HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ - TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ - INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ -}enet_option_enum; - -/* phy mode and mac loopback configurations */ -typedef enum -{ - ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ - ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ - ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ - ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ - ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ - ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ -}enet_mediamode_enum; - -/* IP frame checksum function */ -typedef enum -{ - ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ - ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ - ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped */ -}enet_chksumconf_enum; - -/* received frame filter function */ -typedef enum -{ - ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ - ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ - ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ - ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ -}enet_frmrecept_enum; - -/* register group value get */ -typedef enum -{ - ALL_MAC_REG = 0, /*!< MAC register group */ - ALL_MSC_REG = 22, /*!< MSC register group */ - ALL_PTP_REG = 33, /*!< PTP register group */ - ALL_DMA_REG = 44, /*!< DMA register group */ -}enet_registers_type_enum; - -/* dma direction select */ -typedef enum -{ - ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ - ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ -}enet_dmadirection_enum; - -/* PHY operation direction select */ -typedef enum -{ - ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ - ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ -}enet_phydirection_enum; - -/* register operation direction select */ -typedef enum -{ - ENET_REG_READ, /*!< read register */ - ENET_REG_WRITE /*!< write register */ -}enet_regdirection_enum; - -/* ENET MAC addresses */ -typedef enum -{ - ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ - ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ - ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ - ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ -}enet_macaddress_enum; - -/* descriptor information */ -typedef enum -{ - TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ - TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ - RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ - RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ - RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ - RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ -}enet_descstate_enum; - -/* structure for initialization of the ENET */ -typedef struct -{ - uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ - uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ - uint32_t dma_maxburst; /*!< DMA max burst related parameters */ - uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ - uint32_t store_forward_mode; /*!< store forward mode related parameters */ - uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ - uint32_t flow_control; /*!< flow control related parameters */ - uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ - uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ - uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ - uint32_t timer_config; /*!< frame timer related parameters */ - uint32_t interframegap; /*!< inter frame gap related parameters */ -}enet_initpara_struct; - -/* structure for ENET DMA desciptors */ -typedef struct -{ - uint32_t status; /*!< status */ - uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ - uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ - uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ -} enet_descriptors_struct; - -/* structure of PTP system time */ -typedef struct -{ - uint32_t second; /*!< second of system time */ - uint32_t nanosecond; /*!< nanosecond of system time */ - uint32_t sign; /*!< sign of system time */ -}enet_ptp_systime_struct; - -/* mac_cfg register value */ -#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ -#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ -#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ -#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ - -#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ -#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ -#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ -#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ -#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ -#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ -#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ -#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ - -#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ -#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - -#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ -#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ - -#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ -#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - -#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ -#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ - -#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ -#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ - -#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ -#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ - -#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ -#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ - -#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ -#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ - -#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ -#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ - -#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ -#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ -#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ - -#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ -#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ - -/* mac_frmf register value */ -#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ -#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ -#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ -#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ -#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - -#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ -#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - -#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ -#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ -#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ -#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ -#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ - -#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ -#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - -#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ - -#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ -#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - -#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ -#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ -#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ -#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ -#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ -#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ -#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ - -#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ -#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ -#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ -#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ - -/* mac_phy_ctl register value */ -#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ -#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ -#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ -#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ -#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ - -#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ - -#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ - -/* mac_phy_data register value */ -#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ - -/* mac_fctl register value */ -#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ -#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ -#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ -#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ - -#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ - -#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ -#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - -#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ -#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ -#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ - -#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ - -#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - -#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ -/* mac_vlt register value */ -#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - -#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ -#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ - -/* mac_wum register value */ -#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ -#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ -#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ -#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ - -/* mac_addr0h register value */ -#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ - -/* mac_addrxh register value, x = 1,2,3 */ -#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ - -#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ -#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ -#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ -#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ - -#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ -#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - -/* mac_fcth register value */ -#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ -#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ -#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ -#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ -#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ -#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ -#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ -#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ - -#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ -#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ -#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ -#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ - -/* msc_ctl register value */ -#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ -#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ -#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ - -/* ptp_tsctl register value */ -#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ -#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ - -/* ptp_ssinc register value */ -#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ - -/* ptp_tsl register value */ -#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - -#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ -#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ - -#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ - -/* ptp_tsul register value */ -#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ - -#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ -#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ - -/* dma_bctl register value */ -#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ -#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ - -#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ -#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ -#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ -#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ -#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ - -#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ -#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ -#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ -#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ -#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ - -#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ -#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ - -#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ -#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ -#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ -#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ -#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ -#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ -#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ -#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ -#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ - -#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ -#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ - -#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ -#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ - -/* dma_stat register value */ -#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ -#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ -#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ -#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ -#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ -#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ -#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ - -#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ -#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ -#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ -#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ -#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ -#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ -#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ - -#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ -#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ -#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ -#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ - -/* dma_ctl register value */ -#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ -#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ -#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ -#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ - -#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ -#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ -#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ -#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ -#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ -#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ -#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ -#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ - -#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ -#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ - -#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ -#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ - -#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ -#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ -#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ - -#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ -#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ - -#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ -#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ -#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ - -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ - -#define ENET_SECONDFRAME_OPT_ENABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode enable*/ -#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ -#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ - -/* dma_mfbocnt register value */ -#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ - -#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ - -/* dma tx descriptor tdes0 register value */ -#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ -#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ - -#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ - -/* dma tx descriptor tdes1 register value */ -#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ - -#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ - -/* dma rx descriptor rdes0 register value */ -#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ -#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ - -/* dma rx descriptor rdes1 register value */ -#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ -#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ - -#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ - -#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ - -/* dma rx descriptor rdes4 register value */ -#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ -#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ - -#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ -#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ - -/* ENET register mask value */ -#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ -#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ -#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ -#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ - -#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ -#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ - -typedef enum{ - ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ - ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ - ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ - ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ -}enet_ptp_function_enum; - - -/* ENET remote wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ - -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ - -/* ENET delay timeout */ -#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ -#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ - -/* function declarations */ -/* main function */ -/* deinitialize the ENET, and reset structure parameters for ENET initialization */ -void enet_deinit(void); -/* configure the parameters which are usually less cared for initialization */ -void enet_initpara_config(enet_option_enum option, uint32_t para); -/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); -/* reset all core internal registers located in CLK_TX and CLK_RX */ -ErrStatus enet_software_reset(void); -/* check receive frame valid and return frame size */ -uint32_t enet_rxframe_size_get(void); -/* initialize the dma tx/rx descriptors's parameters in chain mode */ -void enet_descriptors_chain_init(enet_dmadirection_enum direction); -/* initialize the dma tx/rx descriptors's parameters in ring mode */ -void enet_descriptors_ring_init(enet_dmadirection_enum direction); -/* handle current received frame data to application buffer */ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); -/* handle current received frame but without data copy to application buffer */ -#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) -/* handle application buffer data to transmit it */ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); -/* handle current transmit frame but without data copy from application buffer */ -#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) -/* configure the transmit IP frame checksum offload calculation and insertion */ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); -/* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); -/* ENET Tx and Rx function disable (include MAC and DMA module) */ -void enet_disable(void); -/* configure MAC address */ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); - -/* get the ENET MAC/MSC/PTP/DMA status flag */ -FlagStatus enet_flag_get(enet_flag_enum enet_flag); -/* clear the ENET DMA status flag */ -void enet_flag_clear(enet_flag_clear_enum enet_flag); -/* enable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_enable(enet_int_enum enet_int); -/* disable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_disable(enet_int_enum enet_int); -/* get ENET MAC/MSC/DMA interrupt flag */ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); -/* clear ENET DMA interrupt flag */ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); - -/* MAC function */ -/* ENET Tx function enable (include MAC and DMA module) */ -void enet_tx_enable(void); -/* ENET Tx function disable (include MAC and DMA module) */ -void enet_tx_disable(void); -/* ENET Rx function enable (include MAC and DMA module) */ -void enet_rx_enable(void); -/* ENET Rx function disable (include MAC and DMA module) */ -void enet_rx_disable(void); -/* put registers value into the application buffer */ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); -/* enable the MAC address filter */ -void enet_address_filter_enable(enet_macaddress_enum mac_addr); -/* disable the MAC address filter */ -void enet_address_filter_disable(enet_macaddress_enum mac_addr); -/* configure the MAC address filter */ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); -/* PHY interface configuration (configure SMI clock and reset PHY chip) */ -ErrStatus enet_phy_config(void); -/* write to/read from a PHY register */ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); -/* enable the loopback function of phy chip */ -ErrStatus enet_phyloopback_enable(void); -/* disable the loopback function of phy chip */ -ErrStatus enet_phyloopback_disable(void); -/* enable ENET forward feature */ -void enet_forward_feature_enable(uint32_t feature); -/* disable ENET forward feature */ -void enet_forward_feature_disable(uint32_t feature); -/* enable ENET fliter feature */ -void enet_fliter_feature_enable(uint32_t feature); -/* disable ENET fliter feature */ -void enet_fliter_feature_disable(uint32_t feature); - -/* flow control function */ -/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ -ErrStatus enet_pauseframe_generate(void); -/* configure the pause frame detect type */ -void enet_pauseframe_detect_config(uint32_t detect); -/* configure the pause frame parameters */ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); -/* configure the threshold of the flow control(deactive and active threshold) */ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); -/* enable ENET flow control feature */ -void enet_flowcontrol_feature_enable(uint32_t feature); -/* disable ENET flow control feature */ -void enet_flowcontrol_feature_disable(uint32_t feature); - -/* DMA function */ -/* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); -/* poll the dma transmission/reception enable */ -void enet_dmaprocess_resume(enet_dmadirection_enum direction); -/* check and recover the Rx process */ -void enet_rxprocess_check_recovery(void); -/* flush the ENET transmit fifo, and wait until the flush operation completes */ -ErrStatus enet_txfifo_flush(void); -/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); -/* get the Tx or Rx descriptor information */ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); -/* get the number of missed frames during receiving */ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); - -/* descriptor function */ -/* get the bit flag of ENET dma descriptor */ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); -/* set the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); -/* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will set */ -void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will not set */ -void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc); -/* drop current receive frame */ -void enet_rxframe_drop(void); -/* enable DMA feature */ -void enet_dma_feature_enable(uint32_t feature); -/* disable DMA feature */ -void enet_dma_feature_disable(uint32_t feature); - -/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); -/* handle current received frame but without data copy to application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) -/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); -/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) - -/* WUM function */ -/* wakeup frame filter register pointer reset */ -void enet_wum_filter_register_pointer_reset(void); -/* set the remote wakeup frame registers */ -void enet_wum_filter_config(uint32_t pdata[]); -/* enable wakeup management features */ -void enet_wum_feature_enable(uint32_t feature); -/* disable wakeup management features */ -void enet_wum_feature_disable(uint32_t feature); - -/* MSC function */ -/* reset the MAC statistics counters */ -void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ -void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ -void enet_msc_feature_disable(uint32_t feature); -/* get MAC statistics counter */ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); - -/* PTP function */ -/* change subsecond to nanosecond */ -uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond); -/* change nanosecond to subsecond */ -uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond); -/* enable the PTP features */ -void enet_ptp_feature_enable(uint32_t feature); -/* disable the PTP features */ -void enet_ptp_feature_disable(uint32_t feature); -/* configure the PTP timestamp function */ -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); -/* configure the PTP system time subsecond increment value */ -void enet_ptp_subsecond_increment_config(uint32_t subsecond); -/* adjusting the PTP clock frequency only in fine update mode */ -void enet_ptp_timestamp_addend_config(uint32_t add); -/* initializing or adding/subtracting to second of the PTP system time */ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); -/* configure the PTP expected target time */ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); -/* get the PTP current system time */ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); -/* configure and start PTP timestamp counter */ -void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg); -/* adjust frequency in fine method by configure addend register */ -void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); -/* update system time in coarse method */ -void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); -/* set system time in fine method */ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); -/* get the ptp flag status */ -FlagStatus enet_ptp_flag_get(uint32_t flag); - -/* internal function */ -/* reset the ENET initpara struct, call it before using enet_initpara_config() */ -void enet_initpara_reset(void); -/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ -static void enet_default_init(void); -#ifdef USE_DELAY -/* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms -#else -/* insert a delay time */ -static void enet_delay(uint32_t ncount); -/* default _ENET_DELAY_ function with less precise timing */ -#define _ENET_DELAY_ enet_delay -#endif - -#endif /* GD32F10X_ENET_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h deleted file mode 100644 index b9b1478a04..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h +++ /dev/null @@ -1,432 +0,0 @@ -/*! - \file gd32f10x_exmc.h - \brief definitions for the EXMC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_EXMC_H -#define GD32F10X_EXMC_H - -#include "gd32f10x.h" - -/* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ - -/* registers definitions */ -/* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ - -#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */ -#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */ -#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */ - -#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */ -#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */ -#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */ - -#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */ -#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */ -#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */ - -/* NAND/PC card */ -#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */ -#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */ -#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */ -#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */ -#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */ - -#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */ -#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */ -#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */ -#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */ -#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */ - -#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */ -#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */ -#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */ -#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */ -#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ - -/* bits definitions */ -/* NOR/PSRAM */ -/* EXMC_SNCTLx,x=0..3 */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ -#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ - -/* EXMC_SNTCFGx,x=0..3 */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* EXMC_SNWTCFGx,x=0..3 */ -#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNWTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNWTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* NAND/PC card */ -/* EXMC_NPCTLx,x=1..3 */ -#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ -#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ -#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ -#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ -#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ -#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ -#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ -#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ - -/* EXMC_NPINTENx,x=1..3 */ -#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ -#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ -#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ -#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ -#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ -#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ -#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ - -/* EXMC_NPCTCFGx,x=1..3 */ -#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ -#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ -#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ -#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ - -/* EXMC_NPATCFGx,x=1..3 */ -#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ -#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ -#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ -#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ - -/* EXMC_PIOTCFG3 */ -#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ -#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ -#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ -#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ - -/* EXMC_NECCx,x=1,2 */ -#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ - -/* constants definitions */ -/* EXMC NOR/SRAM timing initialize struct */ -typedef struct -{ - uint32_t asyn_access_mode; /*!< asynchronous access mode */ - uint32_t syn_data_latency; /*!< configure the data latency */ - uint32_t syn_clk_division; /*!< configure the clock divide ratio */ - uint32_t bus_latency; /*!< configure the bus latency */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ - uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ -}exmc_norsram_timing_parameter_struct; - -/* EXMC NOR/SRAM initialize struct */ -typedef struct -{ - uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ - uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ - uint32_t extended_mode; /*!< enable or disable the extended mode */ - uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ - uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ - uint32_t memory_write; /*!< enable or disable the write operation */ - uint32_t nwait_config; /*!< NWAIT signal configuration */ - uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ - uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ - uint32_t burst_mode; /*!< enable or disable the burst mode */ - uint32_t databus_width; /*!< specifies the databus width of external memory */ - uint32_t memory_type; /*!< specifies the type of external memory */ - uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing - parameters for read if the extended mode is used */ - exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ -}exmc_norsram_parameter_struct; - -/* EXMC NAND/PC card timing initialize struct */ -typedef struct -{ - uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ - uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ - uint32_t waittime; /*!< configure the minimum wait time */ - uint32_t setuptime; /*!< configure the address setup time */ -}exmc_nand_pccard_timing_parameter_struct; - -/* EXMC NAND initialize struct */ -typedef struct -{ - uint32_t nand_bank; /*!< select the bank of NAND */ - uint32_t ecc_size; /*!< the page size for the ECC calculation */ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ - uint32_t databus_width; /*!< the NAND flash databus width */ - uint32_t wait_feature; /*!< enables or disables the wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ -}exmc_nand_parameter_struct; - -/* EXMC PC card initialize struct */ -typedef struct -{ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t wait_feature; /*!< enables or disables the Wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ - exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ -}exmc_pccard_parameter_struct;; - -/* EXMC register address */ -#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */ - -#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */ - -/* NOR bank memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ - -/* NOR bank memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - -/* asynchronous access mode */ -#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ -#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ -#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ -#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ - -/* data latency for NOR flash */ -#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ -#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ -#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ -#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ -#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ -#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ -#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ -#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ -#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ -#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ -#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ -#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ -#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ -#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ -#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ -#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ - -/* synchronous clock divide ratio */ -#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ - -/* ECC size */ -#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ -#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ -#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ -#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ -#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ -#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ - -/* ALE to RE delay */ -#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ -#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ -#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ -#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ -#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ -#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ -#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ -#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ -#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ -#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ -#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ -#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ -#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ -#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ -#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ -#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ - -/* CLE to RE delay */ -#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ -#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ -#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ -#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ -#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ -#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ -#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ -#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ -#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ -#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ -#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ -#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ -#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ -#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ -#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ -#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ - -/* NAND bank memory data bus width */ -#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ -#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ - -/* EXMC NOR/SRAM bank region definition */ -#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ -#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ -#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ -#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ - -/* EXMC NOR/SRAM write mode */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ -#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */ - -/* EXMC NWAIT signal configuration */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ -#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ - -/* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ - -/* EXMC NAND/PC card bank definition */ -#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ -#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ -#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ - -/* EXMC flag bits */ -#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ -#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ -#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ -#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ - -/* EXMC interrupt flag bits */ -#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ -#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ -#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ - -/* function declarations */ -/* deinitialize EXMC NOR/SRAM region */ -void exmc_norsram_deinit(uint32_t norsram_region); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* initialize EXMC NOR/SRAM region */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* EXMC NOR/SRAM bank enable */ -void exmc_norsram_enable(uint32_t norsram_region); -/* EXMC NOR/SRAM bank disable */ -void exmc_norsram_disable(uint32_t norsram_region); - -/* deinitialize EXMC NAND bank */ -void exmc_nand_deinit(uint32_t nand_bank); -/* initialize EXMC NAND bank */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* exmc_nand_init_struct parameter initialize */ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* EXMC NAND bank enable */ -void exmc_nand_enable(uint32_t nand_bank); -/* EXMC NAND bank disable */ -void exmc_nand_disable(uint32_t nand_bank); -/* enable or disable the EXMC NAND ECC function */ -void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue); -/* get the EXMC ECC value */ -uint32_t exmc_ecc_get(uint32_t nand_bank); - -/* deinitialize EXMC PC card bank */ -void exmc_pccard_deinit(void); -/* initialize EXMC PC card bank */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* exmc_pccard_parameter_struct parameter initialize */ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* EXMC PC card bank enable */ -void exmc_pccard_enable(void); -/* EXMC PC card bank disable */ -void exmc_pccard_disable(void); - -/* enable EXMC interrupt */ -void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source); -/* disable EXMC interrupt */ -void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source); -/* check EXMC flag is set or not */ -FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag); -/* clear EXMC flag */ -void exmc_flag_clear(uint32_t bank, uint32_t flag); -/* check EXMC flag is set or not */ -FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source); -/* clear EXMC flag */ -void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source); - -#endif /* GD32F10X_EXMC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h deleted file mode 100644 index 9822671976..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h +++ /dev/null @@ -1,258 +0,0 @@ -/*! - \file gd32f10x_exti.h - \brief definitions for the EXTI - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_EXTI_H -#define GD32F10X_EXTI_H - -#include "gd32f10x.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ -#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ -#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ -#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ -#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ -#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum -{ - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ -}exti_line_enum; - -/* external interrupt and event */ -typedef enum -{ - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum -{ - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising edge and falling edge trigger */ -}exti_trig_type_enum; - -/* function declarations */ -/* initialization, EXTI lines configuration functions */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - -/* interrupt & flag functions */ -/* get EXTI lines pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); -/* enable the EXTI software interrupt event */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable the EXTI software interrupt event */ -void exti_software_interrupt_disable(exti_line_enum linex); - -#endif /* GD32F10X_EXTI_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h deleted file mode 100644 index f5969b6436..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h +++ /dev/null @@ -1,370 +0,0 @@ -/*! - \file gd32f10x_fmc.h - \brief definitions for the FMC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_FMC_H -#define GD32F10X_FMC_H - -#include "gd32f10x.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option bytes base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ -#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ -#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ -#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ -#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ -#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ -#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ -#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ -#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ -#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ -#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ -#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ -#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ - -/* FMC_KEY0 */ -#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT0 */ -#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL0 */ -#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ -#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ -#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ -#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ -#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR0 */ -#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ -#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ -#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ -#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - -/* FMC_WP */ -#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ - -/* FMC_KEY1 */ -#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ - -/* FMC_STAT1 */ -#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL1 */ -#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ -#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ -#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ -#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ -#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR1 */ -#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */ - -/* FMC_WSEN */ -#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* define the FMC bit position and its register index offset */ -#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) -#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) -#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) - -/* configuration register */ -#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ -#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ -#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ -#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ -#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ - -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ -}fmc_state_enum; - -/* FMC interrupt enable */ -typedef enum -{ - FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ - FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ - FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ - FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ -}fmc_int_enum; - -/* FMC flags */ -typedef enum -{ - FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ - FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ - FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ - FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ - FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ - FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ - FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ - FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ - FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ -}fmc_flag_enum; - -/* FMC interrupt flags */ -typedef enum -{ - FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ - FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ - FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ - FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ -}fmc_interrupt_flag_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* FMC wait state counter */ -#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ -#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ -#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ - -/* option bytes software/hardware free watch dog timer */ -#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ -#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ - -/* option bytes reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ - -/* option bytes reset or not entering standby mode */ -#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ -#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ - -/* option bytes boot bank value */ -#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ -#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ - -#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ - -/* read protect configure */ -#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ -#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ - -/* OB_SPC */ -#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ -#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ - -/* OB_USER */ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ -#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ - -/* OB_WP0 */ -#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ - -/* OB_WP1 */ -#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ - -/* OB_WP2 */ -#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ - -/* OB_WP3 */ -#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ - -/* option bytes write protection */ -#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ -#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ -#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ -#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ -#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ -#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ -#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ -#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ -#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ -#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ -#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ -#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ -#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ -#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ -#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ -#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ -#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ -#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ -#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ -#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ -#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ - -/* FMC timeout */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ - -/* FMC BANK address */ -#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ -#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ -#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* set the FMC wait state counter */ -void fmc_wscnt_set(uint32_t wscnt); -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* unlock the FMC bank0 operation */ -void fmc_bank0_unlock(void); -/* unlock the FMC bank1 operation */ -void fmc_bank1_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* lock the bank0 FMC operation */ -void fmc_bank0_lock(void); -/* lock the bank1 FMC operation */ -void fmc_bank1_lock(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC erase whole bank0 */ -fmc_state_enum fmc_bank0_erase(void); -/* FMC erase whole bank1 */ -fmc_state_enum fmc_bank1_erase(void); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* erase the option byte */ -fmc_state_enum ob_erase(void); -/* enable write protect */ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); -/* configure the option byte security protection */ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte */ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); -/* program option bytes data */ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data); -/* get the FMC option byte user */ -uint8_t ob_user_get(void); -/* get OB_DATA in register FMC_OBSTAT */ -uint16_t ob_data_get(void); -/* get the FMC option byte write protection */ -uint32_t ob_write_protection_get(void); -/* get option byte security protection code value */ -FlagStatus ob_spc_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* check flag is set or not */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC flag */ -void fmc_flag_clear(uint32_t flag); -/* get FMC interrupt flag state */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); -/* clear FMC interrupt flag state */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); -/* return the FMC bank0 state */ -fmc_state_enum fmc_bank0_state_get(void); -/* return the FMC bank1 state */ -fmc_state_enum fmc_bank1_state_get(void); -/* check FMC bank0 ready or not */ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); -/* check FMC bank1 ready or not */ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); - -#endif /* GD32F10X_FMC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h deleted file mode 100644 index 2d22177e1e..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h +++ /dev/null @@ -1,108 +0,0 @@ -/*! - \file gd32f10x_fwdgt.h - \brief definitions for the FWDGT - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_FWDGT_H -#define GD32F10X_FWDGT_H - -#include "gd32f10x.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE /*!< FWDGT base address */ - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ - -/* constants definitions */ -/* psc register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32F10X_FWDGT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h deleted file mode 100644 index 3b6b53a36d..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h +++ /dev/null @@ -1,497 +0,0 @@ -/*! - \file gd32f10x_gpio.h - \brief definitions for the GPIO - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_GPIO_H -#define GD32F10x_GPIO_H - -#include "gd32f10x.h" - -/* GPIOx(x=A,B,C,D,E,F,G) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOE (GPIO_BASE + 0x00001000U) -#define GPIOF (GPIO_BASE + 0x00001400U) -#define GPIOG (GPIO_BASE + 0x00001800U) - -/* AFIO definitions */ -#define AFIO AFIO_BASE - -/* registers definitions */ - -/* GPIO registers definitions */ -#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ -#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ - -/* AFIO registers definitions */ -#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ -#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ -#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ -#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ -#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ -#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ -#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ - -/* bits definitions */ -/* GPIO_CTL0 */ -#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ -#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ -#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ -#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ -#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ -#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ -#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ -#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ -#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ -#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ -#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ -#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ -#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ -#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ -#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ -#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ - -/* GPIO_CTL1 */ -#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ -#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ -#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ -#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ -#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ -#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ -#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ -#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ -#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ -#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ -#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ -#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ -#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ -#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ -#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ -#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* AFIO_EC */ -#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ -#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ -#define AFIO_EC_EOE BIT(7) /*!< event output enable */ - -/* AFIO_PCF0 */ -#ifdef GD32F10X_CL -/* memory map and bit definitions for GD32F10X_CL devices */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ -#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ -#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ -#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ -#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ -#define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ -#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ - -#else -/* memory map and bit definitions for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_REMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ -#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ -#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -#endif /* GD32F10X_CL */ - -/* AFIO_EXTISS0 */ -#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ -#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ -#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ -#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ - -/* AFIO_EXTISS1 */ -#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ -#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ -#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ -#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ - -/* AFIO_EXTISS2 */ -#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ -#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ -#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ -#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ - -/* AFIO_EXTISS3 */ -#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ -#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ -#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ -#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ - -/* AFIO_PCF1 */ -#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ -#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ -#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ -#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ -#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ -#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* GPIO mode values set */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) -#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) - -/* GPIO mode definitions */ -#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ -#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ -#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ -#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ -#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ -#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ -#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ -#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ - -/* GPIO output max speed value */ -#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ - -/* GPIO event output port definitions */ -#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ -#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ -#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ -#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ -#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ - -/* GPIO output port source definitions */ -#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ -#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ -#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ -#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ -#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ -#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ -#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ - -/* GPIO event output pin definitions */ -#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ -#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ -#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ -#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ -#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ -#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ -#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ -#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ -#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ -#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ -#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ -#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ -#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ -#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ -#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ -#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ - -/* GPIO output pin source definitions */ -#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ -#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ -#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ -#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ -#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ -#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ -#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ -#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ -#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ -#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ -#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ -#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ -#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ -#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ -#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ -#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* GPIO remap definitions */ -#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ -#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ -#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ -#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ -#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ -#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ -#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ -#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ -#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ -#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ -#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ -#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN partial remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN full remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ -#if (defined(GD32F10X_CL) || defined(GD32F10X_HD)) -#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) */ -#endif /* GD32F10X_CL||GD32F10X_HD */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U) /*!< ADC0 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U) /*!< ADC1 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ -#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ -#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled and SW-DP enabled */ -#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled and SW-DP disabled */ -#ifdef GD32F10X_CL -#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping(only for GD32F10X_CL devices) */ -#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping(only for GD32F10X_CL devices) */ -#define GPIO_ENET_REMAP ((uint32_t)0x00200020U) /*!< ENET remapping(only for GD32F10X_CL devices) */ -#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping(only for GD32F10X_CL devices) */ -#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping(only for GD32F10X_CL devices) */ -#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) */ -#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U) /*!< ethernet PTP PPS remapping(only for GD32F10X_CL devices) */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD -#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U) /*!< TIMER8 remapping */ -#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U) /*!< TIMER9 remapping */ -#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U) /*!< TIMER10 remapping */ -#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U) /*!< TIMER12 remapping */ -#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U) /*!< TIMER13 remapping */ -#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ -#endif /* GD32F10X_XD */ - -#ifdef GD32F10X_CL -/* ethernet MII or RMII PHY selection */ -#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ -#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ -#endif /* GD32F10X_CL */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* reset alternate function I/O(AFIO) */ -void gpio_afio_deinit(void); -/* GPIO parameter initialization */ -void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* configure GPIO pin remap */ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); - -/* select GPIO pin exti sources */ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); -/* configure GPIO pin event output */ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); -/* enable GPIO pin event output */ -void gpio_event_output_enable(void); -/* disable GPIO pin event output */ -void gpio_event_output_disable(void); - -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -#ifdef GD32F10X_CL -/* select ethernet MII or RMII PHY */ -void gpio_ethernet_phy_select(uint32_t gpio_enetsel); -#endif /* GD32F10X_CL */ - - -#endif /* GD32F10x_GPIO_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h deleted file mode 100644 index ab884837dc..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h +++ /dev/null @@ -1,346 +0,0 @@ -/*! - \file gd32f10x_i2c.h - \brief definitions for the I2C - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_I2C_H -#define GD32F10X_I2C_H - -#include "gd32f10x.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking register */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ - -/* I2C flags */ -typedef enum -{ - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ -}i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ -}i2c_interrupt_flag_enum; - -/* I2C interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ -}i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* dual-address mode switch */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); - -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); - -#endif /* GD32E10X_I2C_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h deleted file mode 100644 index 1c692733c8..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h +++ /dev/null @@ -1,95 +0,0 @@ -/*! - \file gd32f10x_misc.h - \brief definitions for the MISC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_MISC_H -#define GD32F10X_MISC_H - -#include "gd32f10x.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ -/* set the priority group */ -void nvic_priority_group_set(uint32_t nvic_prigroup); - -/* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); -/* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32F10X_MISC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h deleted file mode 100644 index 3805d75ad5..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h +++ /dev/null @@ -1,129 +0,0 @@ -/*! - \file gd32f10x_pmu.h - \brief definitions for the PMU - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_PMU_H -#define GD32F10X_PMU_H - -#include "gd32f10x.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU registers */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* set PMU mode */ -/* PMU work at sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(void); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(void); - -/* backup related functions */ -/* enable write access to the registers in backup domain */ -void pmu_backup_write_enable(void); -/* disable write access to the registers in backup domain */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag_reset); - -#endif /* GD32F10X_PMU_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h deleted file mode 100644 index 7053c053f4..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h +++ /dev/null @@ -1,924 +0,0 @@ -/*! - \file gd32f10x_rcu.h - \brief definitions for the RCU - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_RCU_H -#define GD32F10X_RCU_H - -#include "gd32f10x.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ -#elif defined(GD32F10X_CL) -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* bits definitions */ -/* RCU_CTL */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#elif defined(GD32F10X_CL) -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ -#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ -#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ -#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_CFG0 */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#elif defined(GD32F10X_CL) -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_INT */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#elif defined(GD32F10X_CL) -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ -#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ -#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ -#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ -#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ -#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ -#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ -#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ -#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ -#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ -#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ -#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ -#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#ifndef GD32F10X_CL -#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD -#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ -#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ -#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ -#endif /* GD32F10X_XD */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ -#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ -#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ -#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ -#ifdef GD32F10X_XD -#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ -#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ -#endif /* GD32F10X_XD */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ -#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ -#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ -#ifdef GD32F10X_CL -#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ -#endif /* GD32F10X_CL */ -#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ -#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ -#elif defined(GD32F10X_CL) -#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ -#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ -#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ -#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ -#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ -#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ -#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ -#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ -#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ -#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ -#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ -#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ -#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#ifndef GD32F10X_CL -#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD -#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ -#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ -#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ -#endif /* GD32F10X_XD */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ -#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ -#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ -#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ -#ifdef GD32F10X_XD -#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ -#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ -#endif /* GD32F10X_XD */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ -#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ -#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ -#ifdef GD32F10X_CL -#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ -#endif /* GD32F10X_CL */ -#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -#ifdef GD32F10X_CL -/* RCU_AHBRST */ -#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ -#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ -#endif /* GD32F10X_CL */ - -#if defined(GD32F10X_CL) -/* RCU_CFG1 */ -#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ -#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ -#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ -#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ -#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ -#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ -#endif /* GD32F10X_CL */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -/* peripherals enable */ -#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ -#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ -#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ - -/* peripherals reset */ -#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ -#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ -#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ -#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ - -/* clock control */ -#define CTL_REG_OFFSET 0x00U /*!< control register offset */ -#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ - -/* clock stabilization and stuck interrupt */ -#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ - -/* configuration register */ -#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ -#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ - -/* peripheral clock enable */ -typedef enum -{ - /* AHB peripherals */ - RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ - RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ - RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ - RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ -#elif defined(GD32F10X_CL) - RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ - RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ - RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ - RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ -#if defined(GD32F10X_XD) - RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ - RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ -#endif /* GD32F10X_XD */ - RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ -#ifdef GD32F10X_CL - RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ -#endif /* GD32F10X_CL */ - RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ - RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - - /* APB2 peripherals */ - RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ - RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ - RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ - RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ - RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ - RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ - RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ - RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ -#ifndef GD32F10X_CL - RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD - RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ - RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ - RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ -#endif /* GD32F10X_XD */ -}rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum -{ - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ -}rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum -{ - /* AHB peripherals */ -#ifdef GD32F10X_CL - RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ -#endif /* GD32F10X_CL */ - - /* APB1 peripherals */ - RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ - RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ - RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ - RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ -#ifdef GD32F10X_XD - RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ - RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ -#endif /* GD32F10X_XD */ - RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ - RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ - RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ - RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ - RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ - RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ -#ifdef GD32F10X_CL - RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ -#endif /* GD32F10X_CL */ - RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ - RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ - RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - - /* APB2 peripherals */ - RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ - RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ - RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ - RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ - RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ - RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ - RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ -#ifndef GD32F10X_CL - RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD - RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ - RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ - RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ -#endif /* GD32F10X_XD */ -}rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum -{ - /* clock stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ -#ifdef GD32F10X_CL - RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ - RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ -#endif /* GD32F10X_CL */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ - /* reset source flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ -}rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ -#ifdef GD32F10X_CL - RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ - RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ -#endif /* GD32F10X_CL */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ -}rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ -#ifdef GD32F10X_CL - RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ -#endif /* GD32F10X_CL */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ -}rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum -{ - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ -#ifdef GD32F10X_CL - RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ - RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ -#endif /* GD32F10X_CL */ -}rcu_int_enum; - -/* oscillator types */ -typedef enum -{ - RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ - RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ -#ifdef GD32F10X_CL - RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ - RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ -#endif /* GD32F10X_CL */ -}rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum -{ - CK_SYS = 0, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ -}rcu_clock_freq_enum; - -/* RCU_CFG0 register bit define */ -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC prescaler select */ -#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ -#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ -#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ -#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ -#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ -#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ -#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ - -/* PLL clock multiplication factor */ -#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ - -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ -#elif defined(GD32F10X_CL) -#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ - -/* USBD/USBFS prescaler select */ -#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ -#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ -#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ -#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ - -/* CKOUT0 clock source selection */ -#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ -#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ -#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ -#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ -#ifdef GD32F10X_CL -#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ -#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ -#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ -#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ -#endif /* GD32F10X_CL */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ -#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - -/* PREDV0 division factor */ -#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ -#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ -#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ -#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ -#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ -#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ -#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ -#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ -#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ -#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ -#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ -#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ -#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ -#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ -#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ -#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - -/* PREDV1 division factor */ -#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ -#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ -#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ -#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ -#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ -#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ -#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ -#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ -#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ -#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ -#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ -#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ -#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ -#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ -#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ -#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - -/* PLL1 clock multiplication factor */ -#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ -#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ -#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ -#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ -#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ -#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ -#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ -#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ -#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ -#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - -/* PLL2 clock multiplication factor */ -#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ -#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ -#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ -#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ -#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ -#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ -#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ -#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ -#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ -#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ - -#ifdef GD32F10X_CL -/* PREDV0 input clock source selection */ -#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ -#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ - -/* I2S1 clock source selection */ -#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ -#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ - -/* I2S2 clock source selection */ -#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ -#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ -#endif /* GD32F10X_CL */ - -/* deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ - -/* function declarations */ -/* initialization, peripheral clock enable/disable functions */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP domain */ -void rcu_bkp_reset_enable(void); -/* disable the BKP domain reset */ -void rcu_bkp_reset_disable(void); - -/* clock configuration functions */ -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the CK_OUT0 clock source and divider */ -void rcu_ckout0_config(uint32_t ckout0_src); -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_div); -#elif defined(GD32F10X_CL) -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); -/* configure the PREDV1 division factor */ -void rcu_predv1_config(uint32_t predv1_div); -/* configure the PLL1 clock */ -void rcu_pll1_config(uint32_t pll_mul); -/* configure the PLL2 clock */ -void rcu_pll2_config(uint32_t pll_mul); -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* peripheral clock configuration functions */ -/* configure the ADC division factor */ -void rcu_adc_clock_config(uint32_t adc_psc); -/* configure the USBD/USBFS prescaler factor */ -void rcu_usb_clock_config(uint32_t usb_psc); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -#ifdef GD32F10X_CL -/* configure the I2S1 clock source selection */ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source); -/* configure the I2S2 clock source selection */ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source); -#endif /* GD32F10X_CL */ - -/* interrupt & flag functions */ -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* oscillator configuration functions */ -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32F10X_RCU_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h deleted file mode 100644 index 580617014f..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h +++ /dev/null @@ -1,152 +0,0 @@ -/*! - \file gd32f10x_rtc.h - \brief definitions for the RTC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_RTC_H -#define GD32F10X_RTC_H - -#include "gd32f10x.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ -#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ -#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ -#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ -#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ -#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ -#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ -#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ -#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ -#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ - -/* bits definitions */ -/* RTC_INTEN */ -#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ -#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ -#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ - -/* RTC_CTL */ -#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ -#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ -#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ -#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ -#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ -#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - -/* RTC_PSCH */ -#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ - -/* RTC_PSCL */ -#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ - -/* RTC_DIVH */ -#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ - -/* RTC_DIVL */ -#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ - -/* RTC_CNTH */ -#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ - -/* RTC_CNTL */ -#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ - -/* RTC_ALRMH */ -#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ - -/* RTC_ALRML */ -#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ - -/* constants definitions */ -/* RTC interrupt enable or disable definitions */ -#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ -#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ -#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ - -/* RTC interrupt flag definitions */ -#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ - -/* RTC flag definitions */ -#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ -#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ - -/* function declarations */ -/* initialization functions */ -/* enter RTC configuration mode */ -void rtc_configuration_mode_enter(void); -/* exit RTC configuration mode */ -void rtc_configuration_mode_exit(void); -/* set RTC counter value */ -void rtc_counter_set(uint32_t cnt); -/* set RTC prescaler value */ -void rtc_prescaler_set(uint32_t psc); - -/* operation functions */ -/* wait RTC last write operation finished flag set */ -void rtc_lwoff_wait(void); -/* wait RTC registers synchronized flag set */ -void rtc_register_sync_wait(void); -/* set RTC alarm value */ -void rtc_alarm_config(uint32_t alarm); -/* get RTC counter value */ -uint32_t rtc_counter_get(void); -/* get RTC divider value */ -uint32_t rtc_divider_get(void); - -/* flag & interrupt functions */ -/* get RTC flag status */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear RTC flag status */ -void rtc_flag_clear(uint32_t flag); -/* get RTC interrupt flag status */ -FlagStatus rtc_interrupt_flag_get(uint32_t flag); -/* clear RTC interrupt flag status */ -void rtc_interrupt_flag_clear(uint32_t flag); -/* enable RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disable RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); - -#endif /* GD32F10X_RTC_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h deleted file mode 100644 index c905e10200..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h +++ /dev/null @@ -1,430 +0,0 @@ -/*! - \file gd32f10x_sdio.h - \brief definitions for the SDIO - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_SDIO_H -#define GD32F10X_SDIO_H - -#include "gd32f10x.h" - -/* SDIO definitions */ -#define SDIO SDIO_BASE - -/* registers definitions */ -#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ -#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ -#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ -#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ -#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ -#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ -#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ -#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ -#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ -#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ -#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ -#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ -#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ -#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ -#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ -#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ -#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ -#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ - -/* bits definitions */ -/* SDIO_PWRCTL */ -#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ - -/* SDIO_CLKCTL */ -#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ -#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ -#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ -#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ -#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ -#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ - -/* SDIO_CMDAGMT */ -#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ - -/* SDIO_CMDCTL */ -#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ -#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ -#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ -#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ -#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ -#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ -#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ -#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ -#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ - -/* SDIO_DATATO */ -#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ - -/* SDIO_DATALEN */ -#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ - -/* SDIO_DATACTL */ -#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ -#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ -#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ -#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ -#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ -#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ -#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ -#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ -#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ - -/* SDIO_STAT */ -#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ -#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ -#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ -#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ -#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ -#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ -#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ -#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ -#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ -#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ -#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ -#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ -#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ -#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ -#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ -#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ -#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ -#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ -#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ -#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ -#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ -#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ -#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ -#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ - -/* SDIO_INTC */ -#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ -#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ -#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ -#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ -#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ -#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ -#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ -#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ -#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ -#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ -#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ -#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ -#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ - -/* SDIO_INTEN */ -#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ -#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ -#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ -#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ -#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ -#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ -#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ -#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ -#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ -#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ -#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ -#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ -#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ -#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ -#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ -#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ -#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ -#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ -#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ -#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ -#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ -#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ -#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ -#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ - -/* SDIO_FIFO */ -#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ - -/* constants definitions */ -/* SDIO flags */ -#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ -#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ -#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ -#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ -#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ -#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ -#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ -#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ -#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ -#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ -#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ -#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ -#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ -#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ -#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ -#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ -#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ -#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ -#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ -#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ -#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ -#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ -#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ -#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ - -/* SDIO interrupt enable or disable */ -#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ -#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ -#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ -#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ -#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ -#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ -#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ -#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ -#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ -#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ -#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ -#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ -#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ -#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ -#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ -#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ -#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ -#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ -#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ -#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ -#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ -#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ -#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ -#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ - -/* SDIO interrupt flags */ -#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ -#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ -#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ -#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ -#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */ -#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */ -#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ -#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ -#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */ -#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */ -#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ -#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ -#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ -#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ -#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */ -#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */ -#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */ -#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */ -#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */ -#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */ -#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ -#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ -#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ -#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ - -/* SDIO power control */ -#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ -#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ - -/* SDIO card bus mode control */ -#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ -#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ -#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ - -/* SDIO_CLK clock edge selection */ -#define SDIO_SDIOCLKEDGE_RISING ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ -#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ - -/* clock bypass enable or disable */ -#define SDIO_CLOCKBYPASS_DISABLE ((uint32_t)0x00000000U)/*!< no bypass */ -#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ - -/* SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */ -#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ - -/* SDIO command response type */ -#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ -#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ -#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ - -/* command state machine wait type */ -#define SDIO_WAITTYPE_NO ((uint32_t)0x00000000U)/*!< not wait interrupt */ -#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ -#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ - -#define SDIO_RESPONSE0 ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */ -#define SDIO_RESPONSE1 ((uint32_t)0x00000001U)/*!< card response[95:64] */ -#define SDIO_RESPONSE2 ((uint32_t)0x00000002U)/*!< card response[63:32] */ -#define SDIO_RESPONSE3 ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */ - -/* SDIO data block size */ -#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ -#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ -#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ -#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ -#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ -#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ -#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ -#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ -#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ -#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ -#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ -#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ -#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ -#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ -#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ - -/* SDIO data transfer mode */ -#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000U)/*!< block transfer */ -#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ - -/* SDIO data transfer direction */ -#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000U)/*!< write data to card */ -#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ - -/* SDIO read wait type */ -#define SDIO_READWAITTYPE_DAT2 ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */ -#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ - -/* function declarations */ -/* deinitialize the SDIO */ -void sdio_deinit(void); -/* configure the SDIO clock */ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); -/* enable hardware clock control */ -void sdio_hardware_clock_enable(void); -/* disable hardware clock control */ -void sdio_hardware_clock_disable(void); -/* set different SDIO card bus mode */ -void sdio_bus_mode_set(uint32_t bus_mode); -/* set the SDIO power state */ -void sdio_power_state_set(uint32_t power_state); -/* get the SDIO power state */ -uint32_t sdio_power_state_get(void); -/* enable SDIO_CLK clock output */ -void sdio_clock_enable(void); -/* disable SDIO_CLK clock output */ -void sdio_clock_disable(void); - -/* configure the command index, argument, response type, wait type and CSM to send command */ -/* configure the command and response */ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); -/* set the command state machine wait type */ -void sdio_wait_type_set(uint32_t wait_type); -/* enable the CSM(command state machine) */ -void sdio_csm_enable(void); -/* disable the CSM(command state machine) */ -void sdio_csm_disable(void); -/* get the last response command index */ -uint8_t sdio_command_index_get(void); -/* get the response for the last received command */ -uint32_t sdio_response_get(uint32_t responsex); - -/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ -/* configure the data timeout, data length and data block size */ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); -/* configure the data transfer mode and direction */ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); -/* enable the DSM(data state machine) for data transfer */ -void sdio_dsm_enable(void); -/* disable the DSM(data state machine) */ -void sdio_dsm_disable(void); -/* write data(one word) to the transmit FIFO */ -void sdio_data_write(uint32_t data); -/* read data(one word) from the receive FIFO */ -uint32_t sdio_data_read(void); -/* get the number of remaining data bytes to be transferred to card */ -uint32_t sdio_data_counter_get(void); -/* get the number of words remaining to be written or read from FIFO */ -uint32_t sdio_fifo_counter_get(void); -/* enable the DMA request for SDIO */ -void sdio_dma_enable(void); -/* disable the DMA request for SDIO */ -void sdio_dma_disable(void); - -/* get the flags state of SDIO */ -FlagStatus sdio_flag_get(uint32_t flag); -/* clear the pending flags of SDIO */ -void sdio_flag_clear(uint32_t flag); -/* enable the SDIO interrupt */ -void sdio_interrupt_enable(uint32_t int_flag); -/* disable the SDIO interrupt */ -void sdio_interrupt_disable(uint32_t int_flag); -/* get the interrupt flags state of SDIO */ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); -/* clear the interrupt pending flags of SDIO */ -void sdio_interrupt_flag_clear(uint32_t int_flag); - -/* enable the read wait mode(SD I/O only) */ -void sdio_readwait_enable(void); -/* disable the read wait mode(SD I/O only) */ -void sdio_readwait_disable(void); -/* enable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_enable(void); -/* disable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_disable(void); -/* set the read wait type(SD I/O only) */ -void sdio_readwait_type_set(uint32_t readwait_type); -/* enable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_enable(void); -/* disable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_disable(void); -/* enable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_enable(void); -/* disable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_disable(void); - -/* enable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_enable(void); -/* disable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_disable(void); -/* enable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_enable(void); -/* disable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_disable(void); -/* enable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_enable(void); -/* disable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_disable(void); - -#endif /* GD32F10X_SDIO_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h deleted file mode 100644 index 0cd8c26786..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h +++ /dev/null @@ -1,328 +0,0 @@ -/*! - \file gd32f10x_spi.h - \brief definitions for the SPI - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_SPI_H -#define GD32F10X_SPI_H - -#include "gd32f10x.h" - -/* SPIx(x=0,1,2) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE -#define SPI2 (SPI_BASE + 0x00000400U) - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial value */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC value */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC value */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct -{ - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI frame size */ -#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ -#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ - -/* function declarations */ -/* SPI/I2S deinitialization and initialization functions */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); -/* initialize SPI parameter */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph,uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* NSS functions */ -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* DMA communication */ -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); - -/* normal mode communication */ -/* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); - -/* flag and interrupt functions */ -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -#endif /* GD32F10X_SPI_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h deleted file mode 100644 index 01af9b655c..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h +++ /dev/null @@ -1,730 +0,0 @@ -/*! - \file gd32f10x_timer.h - \brief definitions for the TIMER - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_TIMER_H -#define GD32F10X_TIMER_H - -#include "gd32f10x.h" - -/* TIMERx(x=0..13) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER1 (TIMER_BASE + 0x00000000U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER3 (TIMER_BASE + 0x00000800U) -#define TIMER4 (TIMER_BASE + 0x00000C00U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER6 (TIMER_BASE + 0x00001400U) -#define TIMER7 (TIMER_BASE + 0x00013400U) -#define TIMER8 (TIMER_BASE + 0x00014C00U) -#define TIMER9 (TIMER_BASE + 0x00015000U) -#define TIMER10 (TIMER_BASE + 0x00015400U) -#define TIMER11 (TIMER_BASE + 0x00001800U) -#define TIMER12 (TIMER_BASE + 0x00001C00U) -#define TIMER13 (TIMER_BASE + 0x00002000U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* constants definitions */ -/* TIMER init parameter struct definitions */ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint32_t period; /*!< period value */ - uint16_t clockdivision; /*!< clock division value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions*/ -typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint16_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint16_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ -#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ -#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ -#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ -#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ -#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ -#define TIMER_INT_FLAG_BRK TIMER_INT_BRK - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ - -/* channel enable state */ -#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ - -/* channel complementary output enable state */ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< frozen mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< set the channel output */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< clear the channel output */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle on match */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ - -/* timer input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ - -/* TIMERx(x=0..4,7..13) write CHxVAL register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ - -/* function declarations */ -/* TIMER timebase */ -/* deinit a TIMER */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct* initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a TIMER */ -void timer_enable(uint32_t timer_periph); -/* disable a TIMER */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint32_t update); - -/* timer DMA and event */ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); - -/* TIMER master and slave */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); - -/* TIMER interrupt and flag */ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flag */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flag */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -#endif /* GD32E10X_TIMER_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h deleted file mode 100644 index b0af23732f..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h +++ /dev/null @@ -1,378 +0,0 @@ -/*! - \file gd32f10x_usart.h - \brief definitions for the USART - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.1, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_USART_H -#define GD32F10X_USART_H - -#include "gd32f10x.h" - -/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ -#define USART1 USART_BASE /*!< USART1 base address */ -#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ -#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ -#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ -#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ - -/* registers definitions */ -#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ -#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ -#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ -#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ -#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ - -/* bits definitions */ -/* USARTx_STAT */ -#define USART_STAT_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT_TC BIT(6) /*!< transmission complete */ -#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ - -/* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ - -/* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* constants definitions */ -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) - -/* register offset */ -#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ -#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ - -/* USART flags */ -typedef enum -{ - /* flags in STAT register */ - USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ -}usart_interrupt_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ - -/* USART CK length */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART DMA request for receive configure */ -#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ - -/* USART DMA request for transmission configure */ -#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ - -/* USART RTS configure */ -#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ - -/* USART CTS configure */ -#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); - -/* USART normal mode communication */ -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* LIN mode enable */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* LIN mode disable */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); -/* send break frame */ -void usart_send_break(uint32_t usart_periph); - -/* half-duplex communication */ -/* half-duplex enable */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* half-duplex disable */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* clock enable */ -void usart_synchronous_clock_enable(uint32_t usart_periph); -/* clock disable */ -void usart_synchronous_clock_disable(uint32_t usart_periph); -/* configure usart synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* guard time value configure in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut); -/* smartcard mode enable */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* smartcard mode disable */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* NACK enable in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* NACK disable in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); - -/* flag functions */ -/* get flag in STAT register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT register */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); - -/* interrupt functions */ -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); -/* clear interrupt flag in STAT register */ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); -#endif /* GD32F10X_USART_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h deleted file mode 100644 index c548139baa..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h +++ /dev/null @@ -1,90 +0,0 @@ -/*! - \file gd32f10x_wwdgt.h - \brief definitions for the WWDGT - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_WWDGT_H -#define GD32F10X_WWDGT_H - -#include "gd32f10x.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE /*!< WWDGT base address */ - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32F10X_WWDGT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c deleted file mode 100644 index ab628288bf..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c +++ /dev/null @@ -1,933 +0,0 @@ -/*! - \file gd32f10x_adc.c - \brief ADC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_adc.h" - -/* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) - -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) - -/* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) - -/* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) - -/* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) - -/*! - \brief reset ADC - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_deinit(uint32_t adc_periph) -{ - switch(adc_periph){ - case ADC0: - /* reset ADC0 */ - rcu_periph_reset_enable(RCU_ADC0RST); - rcu_periph_reset_disable(RCU_ADC0RST); - break; - case ADC1: - /* reset ADC1 */ - rcu_periph_reset_enable(RCU_ADC1RST); - rcu_periph_reset_disable(RCU_ADC1RST); - break; -#ifndef GD32F10X_CL - case ADC2: - rcu_periph_reset_enable(RCU_ADC2RST); - rcu_periph_reset_disable(RCU_ADC2RST); - break; -#endif /* GD32F10X_CL */ - default: - break; - } -} - -/*! - \brief configure the ADC sync mode - \param[in] mode: ADC mode - only one parameter can be selected which is shown as below: - \arg ADC_MODE_FREE: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only - \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only - \param[out] none - \retval none -*/ -void adc_mode_config(uint32_t mode) -{ - ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); - ADC_CTL0(ADC0) |= mode; -} - -/*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] function: the function to config - only one parameter can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (function & ADC_SCAN_MODE)){ - /* enable scan mode */ - ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* enable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* enable continuous mode */ - ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ - /* disable scan mode */ - ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* disable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* disable continuous mode */ - ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment){ - /* MSB alignment */ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ - /* LSB alignment */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief enable ADC interface - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_enable(uint32_t adc_periph) -{ - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ - /* enable ADC */ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_disable(uint32_t adc_periph) -{ - /* disable ADC */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_calibration_enable(uint32_t adc_periph) -{ - /* reset the selected ADC1 calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ - } -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief enable DMA request - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - /* enable DMA request */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - /* disable DMA request */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel, the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) -{ - /* disable discontinuous mode of regular & inserted channel */ - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* config the number of conversions in discontinuous mode */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - /* enable regular channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ - default: - break; - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure the length of regular channel group */ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - case ADC_INSERTED_CHANNEL: - /* configure the length of inserted channel group */ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ - /* the regular group sequence rank is smaller than six */ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); - ADC_RSQ2(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ - /* the regular group sequence rank is smaller than twelve */ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); - ADC_RSQ1(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ - /* the regular group sequence rank is smaller than sixteen */ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); - ADC_RSQ0(adc_periph) = rsq; - }else{ - } - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the regular group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the regular group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - /* get inserted channel group length */ - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); - isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); - ADC_ISQ(adc_periph) = isq; - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the inserted group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the inserted group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] inserted_channel: insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset: the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - - if(num <= ADC_OFFSET_LENGTH){ - /* calculate the offset of the register */ - num = num * ADC_OFFSET_SHIFT_LENGTH; - /* config the offset of the selected channels */ - REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief configure ADC external trigger source - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected - for regular channel: - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select - \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 - \arg ADC2_EXTTRIG_REGULAR_T2_CH0: TIMER2 CH0 event select - \arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select - \arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select - \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select - \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select - \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select - \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC2_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC2_EXTTRIG_INSERTED_T3_CH2: TIMER3 CH2 event select - \arg ADC2_EXTTRIG_INSERTED_T7_CH1: TIMER7 CH1 event select - \arg ADC2_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select - \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select - \arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select - \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief configure ADC external trigger - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* enable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* enable ADC inserted channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; - } - }else{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief enable ADC software trigger - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* enable ADC regular channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* enable ADC inserted channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(uint32_t adc_periph) -{ - return (uint16_t)(ADC_RDATA(adc_periph)); -} - -/*! - \brief read ADC inserted group data register - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] inserted_channel: insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - /* read the data of channel 0 */ - idata = ADC_IDATA0(adc_periph); - break; - case ADC_INSERTED_CHANNEL_1: - /* read the data of channel 1 */ - idata = ADC_IDATA1(adc_periph); - break; - case ADC_INSERTED_CHANNEL_2: - /* read the data of channel 2 */ - idata = ADC_IDATA2(adc_periph); - break; - case ADC_INSERTED_CHANNEL_3: - /* read the data of channel 3 */ - idata = ADC_IDATA3(adc_periph); - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief read the last ADC0 and ADC1 conversion result data in sync mode - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint32_t adc_sync_mode_convert_value_read(void) -{ - /* return conversion value */ - return ADC_RDATA(ADC0); -} - - -/*! - \brief configure ADC analog watchdog single channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - /* analog watchdog channel select */ - ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - /* inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_watchdog_disable(uint32_t adc_periph) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] low_threshold: analog watchdog low threshold, 0..4095 - \param[in] high_threshold: analog watchdog high threshold, 0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) -{ - ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); -} - -/*! - \brief get the ADC flag bits - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) -{ - FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag bits - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_flag: the adc flag bits - one or more parameters can be selected which are shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); -} - -/*! - \brief get the bit state of ADCx software start conversion - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the bit state of ADCx software inserted channel start conversion - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the ADC interrupt bits - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc interrupt bits - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch(adc_interrupt){ - case ADC_INT_FLAG_WDE: - /* get the ADC analog watchdog interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear the ADC flag - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc status flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief enable ADC interrupt - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc interrupt - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* enable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - } - /* enable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - } - /* enable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc interrupt flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* disable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; - } - /* disable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; - } - /* disable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; - } -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c deleted file mode 100644 index 69e0c6a93b..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c +++ /dev/null @@ -1,296 +0,0 @@ -/*! - \file gd32f10x_bkp.c - \brief BKP driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_bkp.h" - -/* BKP register bits offset */ -#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) - -/*! - \brief reset BKP registers - \param[in] none - \param[out] none - \retval none -*/ -void bkp_deinit(void) -{ - /* reset BKP domain register*/ - rcu_bkp_reset_enable(); - rcu_bkp_reset_disable(); -} - -/*! - \brief write BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[in] data: the data to be write in BKP data register - \param[out] none - \retval none -*/ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) -{ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - BKP_DATA10_41(register_number - 1U) = data; - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - BKP_DATA0_9(register_number - 1U) = data; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief read BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[out] none - \retval data of BKP data register -*/ -uint16_t bkp_data_read(bkp_data_register_enum register_number) -{ - uint16_t data = 0U; - - /* get the data from the BKP data register */ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - data = BKP_DATA10_41(register_number - 1U); - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - data = BKP_DATA0_9(register_number - 1U); - }else{ - /* illegal parameters */ - } - return data; -} - -/*! - \brief enable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; -} - -/*! - \brief disable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; -} - -/*! - \brief enable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; -} - -/*! - \brief disable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; -} - -/*! - \brief select RTC output - \param[in] outputsel: RTC output selection - only one parameter can be selected which is shown as below: - \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output - \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output - \param[out] none - \retval none -*/ -void bkp_rtc_output_select(uint16_t outputsel) -{ - uint16_t ctl = 0U; - - /* configure BKP_OCTL_ROSEL with outputsel */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_ROSEL; - ctl |= outputsel; - BKP_OCTL = ctl; -} - -/*! - \brief set RTC clock calibration value - \param[in] value: RTC clock calibration value - \arg 0x00 - 0x7F - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_value_set(uint8_t value) -{ - uint16_t ctl; - - /* configure BKP_OCTL_RCCV with value */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_RCCV; - ctl |= (uint16_t)OCTL_RCCV(value); - BKP_OCTL = ctl; -} - -/*! - \brief enable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_enable(void) -{ - BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; -} - -/*! - \brief disable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_disable(void) -{ - BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; -} - -/*! - \brief set tamper pin active level - \param[in] level: tamper active level - only one parameter can be selected which is shown as below: - \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high - \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low - \param[out] none - \retval none -*/ -void bkp_tamper_active_level_set(uint16_t level) -{ - uint16_t ctl = 0U; - - /* configure BKP_TPCTL_TPAL with level */ - ctl = BKP_TPCTL; - ctl &= (uint16_t)~BKP_TPCTL_TPAL; - ctl |= level; - BKP_TPCTL = ctl; -} - -/*! - \brief enable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_enable(void) -{ - BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; -} - -/*! - \brief disable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_disable(void) -{ - BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; -} - -/*! - \brief get tamper flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_flag_get(void) -{ - if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear tamper flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} - -/*! - \brief get tamper interrupt flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_interrupt_flag_get(void) -{ - if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear tamper interrupt flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c deleted file mode 100644 index 95ca2dd050..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c +++ /dev/null @@ -1,993 +0,0 @@ -/*! - \file gd32f10x_can.c - \brief CAN driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_can.h" - -#define CAN_ERROR_HANDLE(s) do{}while(1) - -/*! - \brief deinitialize CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_deinit(uint32_t can_periph) -{ -#ifdef GD32F10x_CL - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - }else{ - rcu_periph_reset_enable(RCU_CAN1RST); - rcu_periph_reset_disable(RCU_CAN1RST); - } -#else - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - } -#endif -} - -/*! - \brief initialize CAN parameter struct with a default value - \param[in] type: the type of CAN parameter struct - only one parameter can be selected which is shown as below: - \arg CAN_INIT_STRUCT: the CAN initial struct - \arg CAN_FILTER_STRUCT: the CAN filter struct - \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct - \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct - \param[in] p_struct: the pointer of the specific struct - \param[out] none - \retval none -*/ -void can_struct_para_init(can_struct_type_enum type, void* p_struct) -{ - uint8_t i; - - /* get type of the struct */ - switch(type){ - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE; - ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; - - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; - - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; - } - - ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; - - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; - } - - ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct*)p_struct)->rx_efid = 0U; - ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct*)p_struct)->rx_fi = 0U; - ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; - - break; - - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); - } -} - -/*! - \brief initialize CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] can_parameter_init: parameters for CAN initializtion - \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) - \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) - \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) - \arg time_triggered: ENABLE or DISABLE - \arg auto_bus_off_recovery: ENABLE or DISABLE - \arg auto_wake_up: ENABLE or DISABLE - \arg auto_retrans: ENABLE or DISABLE - \arg rec_fifo_overwrite: ENABLE or DISABLE - \arg trans_fifo_order: ENABLE or DISABLE - \arg prescaler: 0x0000 - 0x03FF - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) -{ - uint32_t timeout = CAN_TIMEOUT; - ErrStatus flag = ERROR; - - /* disable sleep mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - /* enable initialize mode */ - CAN_CTL(can_periph) |= CAN_CTL_IWMOD; - /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - /* set the bit timing register */ - CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ - BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ - BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ - BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ - BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); - - /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ - CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; - } - /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ - CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_AWU; - } - /* automatic retransmission mode disable*/ - if(ENABLE == can_parameter_init->auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ARD; - } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } - /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ - CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } - /* disable initialize mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; - timeout = CAN_TIMEOUT; - /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check exit initialize mode */ - if(0U != timeout){ - flag = SUCCESS; - } - } - return flag; -} - -/*! - \brief initialize CAN filter - \param[in] can_filter_parameter_init: struct for CAN filter initialization - \arg filter_list_high: 0x0000 - 0xFFFF - \arg filter_list_low: 0x0000 - 0xFFFF - \arg filter_mask_high: 0x0000 - 0xFFFF - \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - \arg filter_number: 0 - 27 - \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - \arg filter_enable: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) -{ - uint32_t val = 0U; - - val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* disable filter */ - CAN_FW(CAN0) &= ~(uint32_t)val; - - /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ - /* set filter 16 bits */ - CAN_FSCFG(CAN0) &= ~(uint32_t)val; - /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); - } - /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ - /* set filter 32 bits */ - CAN_FSCFG(CAN0) |= (uint32_t)val; - /* 32 bits list or first 32 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* 32 bits mask or second 32 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); - } - - /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ - /* mask mode */ - CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ - /* list mode */ - CAN_FMCFG(CAN0) |= (uint32_t)val; - } - - /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ - /* FIFO0 */ - CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - }else{ - /* FIFO1 */ - CAN_FAFIFO(CAN0) |= (uint32_t)val; - } - - /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ - - CAN_FW(CAN0) |= (uint32_t)val; - } - - /* filter lock enable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief set CAN1 fliter start bank number - \param[in] start_bank: CAN1 start bank number - only one parameter can be selected which is shown as below: - \arg (1..27) - \param[out] none - \retval none -*/ -void can1_filter_start_bank(uint8_t start_bank) -{ - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* set CAN1 filter start number */ - CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; - CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief enable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_debug_freeze_enable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) |= CAN_CTL_DFZ; -#ifdef GD32F10x_CL - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - }else{ - dbg_periph_enable(DBG_CAN1_HOLD); - } -#else - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - } -#endif -} - -/*! - \brief disable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_debug_freeze_disable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; -#ifdef GD32F10x_CL - if(CAN0 == can_periph){ - dbg_periph_disable(DBG_CAN0_HOLD); - }else{ - dbg_periph_disable(DBG_CAN1_HOLD); - } -#else - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - } -#endif -} - -/*! - \brief enable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_time_trigger_mode_enable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* enable the tcc mode */ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - /* enable time stamp */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; - } -} - -/*! - \brief disable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_time_trigger_mode_disable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* disable the TCC mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - /* reset TSEN bits */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; - } -} - -/*! - \brief transmit CAN message - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] transmit_message: struct for CAN transmit message - \arg tx_sfid: 0x00000000 - 0x000007FF - \arg tx_efid: 0x00000000 - 0x1FFFFFFF - \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg tx_dlenc: 1 - 7 - \arg tx_data[]: 0x00 - 0xFF - \param[out] none - \retval mailbox_number -*/ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) -{ - uint8_t mailbox_number = CAN_MAILBOX0; - - /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ - mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ - mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ - mailbox_number = CAN_MAILBOX2; - }else{ - mailbox_number = CAN_NOMAILBOX; - } - /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number){ - return CAN_NOMAILBOX; - } - - CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ - /* set transmit mailbox standard identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ - /* set transmit mailbox extended identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); - } - /* set the data length */ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; - CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; - /* set the data */ - CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); - CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); - /* enable transmission */ - CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; - - return mailbox_number; -} - -/*! - \brief get CAN transmit state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOX(x=0,1,2) - \param[out] none - \retval can_transmit_state_enum -*/ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) -{ - can_transmit_state_enum state = CAN_TRANSMIT_FAILED; - uint32_t val = 0U; - - /* check selected mailbox state */ - switch(mailbox_number){ - /* mailbox0 */ - case CAN_MAILBOX0: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); - break; - /* mailbox1 */ - case CAN_MAILBOX1: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); - break; - /* mailbox2 */ - case CAN_MAILBOX2: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); - break; - default: - val = CAN_TRANSMIT_FAILED; - break; - } - - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): - state = CAN_TRANSMIT_PENDING; - break; - /* mailbox0 transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_OK; - break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_OK; - break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_OK; - break; - /* transmit failed */ - default: - state = CAN_TRANSMIT_FAILED; - break; - } - return state; -} - -/*! - \brief stop CAN transmission - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOXx(x=0,1,2) - \param[out] none - \retval none -*/ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) -{ - if(CAN_MAILBOX0 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ - } - }else if(CAN_MAILBOX1 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ - } - }else if(CAN_MAILBOX2 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ - } - }else{ - /* illegal parameters */ - } -} - -/*! - \brief CAN receive message - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] receive_message: struct for CAN receive message - \arg rx_sfid: 0x00000000 - 0x000007FF - \arg rx_efid: 0x00000000 - 0x1FFFFFFF - \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg rx_dlenc: 1 - 7 - \arg rx_data[]: 0x00 - 0xFF - \arg rx_fi: 0 - 27 - \retval none -*/ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) -{ - /* get the frame format */ - receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ - /* get standard identifier */ - receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ - /* get extended identifier */ - receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); - } - - /* get frame type */ - receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* filtering index */ - receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - /* get recevie data length */ - receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - - /* receive data */ - receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - - /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - } -} - -/*! - \brief release FIFO0 - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval none -*/ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) -{ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ - /* illegal parameters */ - CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); - } -} - -/*! - \brief CAN receive message length - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval message length -*/ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) -{ - uint8_t val = 0U; - - if(CAN_FIFO0 == fifo_number){ - /* FIFO0 */ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ - /* FIFO1 */ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ - /* illegal parameters */ - } - return val; -} - -/*! - \brief set CAN working mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] can_working_mode - only one parameter can be selected which is shown as below: - \arg CAN_MODE_INITIALIZE - \arg CAN_MODE_NORMAL - \arg CAN_MODE_SLEEP - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) -{ - ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if(CAN_MODE_INITIALIZE == working_mode){ - /* disable sleep mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); - /* set initialize mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_NORMAL == working_mode){ - /* enter normal mode */ - CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ - timeout--; - } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_SLEEP == working_mode){ - /* disable initialize mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); - /* set sleep mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; - /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else{ - flag = ERROR; - } - return flag; -} - -/*! - \brief wake up CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_wakeup(uint32_t can_periph) -{ - ErrStatus flag = ERROR; - uint32_t timeout = CAN_TIMEOUT; - - /* wakeup */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ - timeout--; - } - /* check state */ - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - return flag; -} - -/*! - \brief get CAN error type - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval can_error_enum - \arg CAN_ERROR_NONE: no error - \arg CAN_ERROR_FILL: fill error - \arg CAN_ERROR_FORMATE: format error - \arg CAN_ERROR_ACK: ACK error - \arg CAN_ERROR_BITRECESSIVE: bit recessive - \arg CAN_ERROR_BITDOMINANTER: bit dominant error - \arg CAN_ERROR_CRC: CRC error - \arg CAN_ERROR_SOFTWARECFG: software configure -*/ -can_error_enum can_error_get(uint32_t can_periph) -{ - can_error_enum error; - error = CAN_ERROR_NONE; - - /* get error type */ - error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); - return error; -} - -/*! - \brief get CAN receive error number - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval error number -*/ -uint8_t can_receive_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - /* get error count */ - val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief get CAN transmit error number - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval error number -*/ -uint8_t can_transmit_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - -/*! - \brief get CAN flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ - /* get flag and interrupt enable state */ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \param[out] none - \retval none -*/ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag) -{ - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); -} - -/*! - \brief get CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval none -*/ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c deleted file mode 100644 index 0173e9f507..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c +++ /dev/null @@ -1,131 +0,0 @@ -/*! - \file gd32f10x_crc.c - \brief CRC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_crc.h" - -#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) -#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_DATA = CRC_DATA_RESET_VALUE; - CRC_FDATA = CRC_FDATA_RESET_VALUE; - CRC_CTL = (uint32_t)CRC_CTL_RST; -} - -/*! - \brief reset data register to the value of initializaiton data register - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the value of the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the value of the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write data to the free data register - \param[in] free_data: specify 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief calculate the CRC value of a 32-bit data - \param[in] sdata: specified 32-bit data - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return (CRC_DATA); -} - -/*! - \brief calculate the CRC value of an array of 32-bit values - \param[in] array: pointer to an array of 32-bit values - \param[in] size: size of the array - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for(index = 0U; index < size; index++){ - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c deleted file mode 100644 index b5114a2739..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c +++ /dev/null @@ -1,559 +0,0 @@ -/*! - \file gd32f10x_dac.c - \brief DAC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_dac.h" - -/* DAC register bit offset */ -#define DAC1_REG_OFFSET ((uint32_t)16U) -#define DH_12BIT_OFFSET ((uint32_t)16U) -#define DH_8BIT_OFFSET ((uint32_t)8U) - -/*! - \brief deinitialize DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_deinit(void) -{ - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); -} - -/*! - \brief enable DAC - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DEN0; - }else{ - DAC_CTL |= DAC_CTL_DEN1; - } -} - -/*! - \brief disable DAC - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DEN1; - } -} - -/*! - \brief enable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ - DAC_CTL |= DAC_CTL_DDMAEN1; - } -} - -/*! - \brief disable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DDMAEN1; - } -} - -/*! - \brief enable DAC output buffer - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ - DAC_CTL &= ~DAC_CTL_DBOFF1; - } -} - -/*! - \brief disable DAC output buffer - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DBOFF0; - }else{ - DAC_CTL |= DAC_CTL_DBOFF1; - } -} - -/*! - \brief get DAC output value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if(DAC0 == dac_periph){ - /* store the DAC0 output value */ - data = (uint16_t)DAC0_DO; - }else{ - /* store the DAC1 output value */ - data = (uint16_t)DAC1_DO; - } - return data; -} - -/*! - \brief set the DAC specified data holding register value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] dac_align - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data: data to be loaded - \param[out] none - \retval none -*/ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) -{ - if(DAC0 == dac_periph){ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } - }else{ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } - } -} - -/*! - \brief enable DAC trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DTEN0; - }else{ - DAC_CTL |= DAC_CTL_DTEN1; - } -} - -/*! - \brief disable DAC trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DTEN1; - } -} - -/*! - \brief set DAC trigger source - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] triggersource: external triggers of DAC - only one parameter can be selected which is shown as below: - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F10X_CL) - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO - \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO - \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F10X_MD and GD32F10X_HD and GD32F10X_XD) - \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger - \param[out] none - \retval none -*/ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; - }else{ - /* configure DAC1 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC software trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \retval none -*/ -void dac_software_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; - }else{ - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; - } -} - -/*! - \brief configure DAC wave mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] wave_mode - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_DISABLE: wave disable - \arg DAC_WAVE_MODE_LFSR: LFSR noise mode - \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode - \param[out] none - \retval none -*/ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM0; - DAC_CTL |= wave_mode; - }else{ - /* configure DAC1 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC wave bit width - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] bit_width - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= bit_width; - }else{ - /* configure DAC1 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (bit_width << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC LFSR noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] unmask_bits - only one parameter can be selected which is shown as below: - \arg DAC_LFSR_BIT0: unmask the LFSR bit0 - \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] - \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] - \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] - \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] - \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] - \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] - \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] - \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] - \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] - \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] - \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] - \param[out] none - \retval none -*/ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= unmask_bits; - }else{ - /* configure DAC1 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC triangle noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] amplitude - only one parameter can be selected which is shown as below: - \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 - \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 - \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 - \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 - \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 - \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 - \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 - \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 - \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 - \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 - \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 - \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 - \param[out] none - \retval none -*/ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= amplitude; - }else{ - /* configure DAC1 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (amplitude << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL |= (ctl); -} - -/*! - \brief disable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL &= (~ctl); -} - -/*! - \brief enable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_enable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); -} - -/*! - \brief disable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_disable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT &= (~swt); -} - -/*! - \brief enable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL &= (~ctl); -} - -/*! - \brief disable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL |= (ctl); -} - -/*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded - \param[out] none - \retval none -*/ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) -{ - uint32_t data = 0U; - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; - DACC_R8DH = data; - break; - default: - break; - } -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c deleted file mode 100644 index f8b74c727f..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c +++ /dev/null @@ -1,153 +0,0 @@ -/*! - \file gd32f10x_dbg.c - \brief DBG driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_dbg.h" - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_CTL |= (uint32_t)dbg_periph; -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_CTL &= ~(uint32_t)dbg_periph; -} - -/*! - \brief enable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_enable(void) -{ - DBG_CTL |= DBG_CTL_TRACE_IOEN; -} - -/*! - \brief disable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_disable(void) -{ - DBG_CTL &= ~DBG_CTL_TRACE_IOEN; -} - -/*! - \brief trace pin mode selection - \param[in] trace_mode: - only one parameter can be selected which is shown as below: - \arg TRACE_MODE_ASYNC: trace pin used for async mode - \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 - \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 - \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 - \param[out] none - \retval none -*/ -void dbg_trace_pin_mode_set(uint32_t trace_mode) -{ - DBG_CTL &= ~DBG_CTL_TRACE_MODE; - DBG_CTL |= trace_mode; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c deleted file mode 100644 index 801d69130d..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c +++ /dev/null @@ -1,737 +0,0 @@ -/*! - \file gd32f10x_dma.c - \brief DMA driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_dma.h" - -#define DMA_WRONG_HANDLE while(1){} - - /* check whether peripheral matches channels or not */ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); - -/*! - \brief deinitialize DMA a channel registers - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is deinitialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* disable DMA a channel */ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_struct_para_init(dma_parameter_struct* init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; - init_struct->number = 0U; - init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; - init_struct->priority = DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is initialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* configure peripheral base address */ - DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width, */ - ctl = DMA_CHCTL(dma_periph, channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); - DMA_CHCTL(dma_periph, channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - }else{ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set peripheral base address - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHPADDR(dma_periph, channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set memory base address - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHMADDR(dma_periph, channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] number: the number of remaining data to be transferred by the DMA - \arg 0x0000-0xFFFF - \param[out] none - \retval none -*/ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - return (uint32_t)DMA_CHCNT(dma_periph, channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] priority: priority Level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] mwidth: transfer data width of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] pwidth: transfer data width of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - if(DMA_PERIPHERAL_TO_MEMORY == direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - /* check whether the flag is set or not */ - if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ - reval = SET; - }else{ - reval = RESET; - } - - return reval; -} - -/*! - \brief clear the flag of a DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch(flag){ - case DMA_INT_FLAG_FTF: - /* check whether the full transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - /* check whether the half transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - /* check whether the error interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; - break; - default: - DMA_WRONG_HANDLE - } - - /* when the interrupt flag is set and enabled, return SET */ - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~source; -} - -/*! - \brief check whether peripheral and channels match - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) -{ - ErrStatus val = SUCCESS; - - if(DMA1 == dma_periph){ - /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ - if(channelx > DMA_CH4){ - val = ERROR; - } - } - - return val; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c deleted file mode 100644 index e614de1670..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c +++ /dev/null @@ -1,3074 +0,0 @@ -/*! - \file gd32f10x_enet.c - \brief ENET driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_enet.h" - -#ifdef GD32F10X_CL - -#if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#elif defined ( __ICCARM__ ) /*!< IAR compiler */ -#pragma data_alignment=4 -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -#pragma data_alignment=4 -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -#pragma data_alignment=4 -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -#pragma data_alignment=4 -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#endif /* __CC_ARM */ - -/* global transmit and receive descriptors pointers */ -enet_descriptors_struct *dma_current_txdesc; -enet_descriptors_struct *dma_current_rxdesc; - -/* structure pointer of ptp descriptor for normal mode */ -enet_descriptors_struct *dma_current_ptp_txdesc = NULL; -enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; - -/* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; - -static uint32_t enet_unknow_err = 0U; - -/* array of register offset for debug information get */ -static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, - -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C, -0x1050, 0x1054}; - - -/*! - \brief deinitialize the ENET, and reset structure parameters for ENET initialization - \param[in] none - \param[out] none - \retval none -*/ -void enet_deinit(void) -{ - rcu_periph_reset_enable(RCU_ENETRST); - rcu_periph_reset_disable(RCU_ENETRST); - enet_initpara_reset(); -} - -/*! - \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise - configuration will be no effect - \param[in] option: different function option, which is related to several parameters, - only one parameter can be selected which is shown as below, refer to enet_option_enum - \arg FORWARD_OPTION: choose to configure the frame forward related parameters - \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters - \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters - \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters - \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters - \arg VLAN_OPTION: choose to configure vlan related parameters - \arg FLOWCTL_OPTION: choose to configure flow control related parameters - \arg HASHH_OPTION: choose to configure hash high - \arg HASHL_OPTION: choose to configure hash low - \arg FILTER_OPTION: choose to configure frame filter related parameters - \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters - \arg TIMER_OPTION: choose to configure time counter related parameters - \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option - all the related parameters should be configured which are shown as below - FORWARD_OPTION related parameters: - - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; - - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; - - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . - DMABUS_OPTION related parameters: - - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; - - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; - DMA_MAXBURST_OPTION related parameters: - - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ - ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ - ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ - ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ - ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; - - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ - ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ - ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ - ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ - ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; - - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; - DMA_ARBITRATION_OPTION related parameters: - - ENET_ARBITRATION_RXPRIORTX / ENET_ARBITRATION_RXTX_1_1 - / ENET_ARBITRATION_RXTX_2_1/ ENET_ARBITRATION_RXTX_3_1 - / ENET_ARBITRATION_RXTX_4_1. - STORE_OPTION related parameters: - - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; - - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; - - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ - ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; - - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ - ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ - ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ - ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . - DMA_OPTION related parameters: - - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; - - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE . - VLAN_OPTION related parameters: - - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; - - MAC_VLT_VLTI(regval) . - FLOWCTL_OPTION related parameters: - - MAC_FCTL_PTM(regval) ; - - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ - ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; - - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . - HASHH_OPTION related parameters: - - 0x0~0xFFFF FFFFU - HASHL_OPTION related parameters: - - 0x0~0xFFFF FFFFU - FILTER_OPTION related parameters: - - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ - ENET_SRC_FILTER_DISABLE ; - - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; - - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ - ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; - - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ - ENET_UNICAST_FILTER_PERFECT ; - - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ - ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . - HALFDUPLEX_OPTION related parameters: - - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; - - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; - - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; - - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ - ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; - - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . - TIMER_OPTION related parameters: - - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; - - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; - INTERFRAMEGAP_OPTION related parameters: - - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ - ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ - ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ - ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . - \param[out] none - \retval none -*/ -void enet_initpara_config(enet_option_enum option, uint32_t para) -{ - switch(option){ - case FORWARD_OPTION: - /* choose to configure forward_frame, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; - enet_initpara.forward_frame = para; - break; - case DMABUS_OPTION: - /* choose to configure dmabus_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; - enet_initpara.dmabus_mode = para; - break; - case DMA_MAXBURST_OPTION: - /* choose to configure dma_maxburst, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; - enet_initpara.dma_maxburst = para; - break; - case DMA_ARBITRATION_OPTION: - /* choose to configure dma_arbitration, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; - enet_initpara.dma_arbitration = para; - break; - case STORE_OPTION: - /* choose to configure store_forward_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)STORE_OPTION; - enet_initpara.store_forward_mode = para; - break; - case DMA_OPTION: - /* choose to configure dma_function, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - enet_initpara.dma_function = para; - break; - case VLAN_OPTION: - /* choose to configure vlan_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; - enet_initpara.vlan_config = para; - break; - case FLOWCTL_OPTION: - /* choose to configure flow_control, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; - enet_initpara.flow_control = para; - break; - case HASHH_OPTION: - /* choose to configure hashtable_high, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; - enet_initpara.hashtable_high = para; - break; - case HASHL_OPTION: - /* choose to configure hashtable_low, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; - enet_initpara.hashtable_low = para; - break; - case FILTER_OPTION: - /* choose to configure framesfilter_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; - enet_initpara.framesfilter_mode = para; - break; - case HALFDUPLEX_OPTION: - /* choose to configure halfduplex_param, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; - enet_initpara.halfduplex_param = para; - break; - case TIMER_OPTION: - /* choose to configure timer_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; - break; - case INTERFRAMEGAP_OPTION: - /* choose to configure interframegap, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; - enet_initpara.interframegap = para; - break; - default: - break; - } -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared - parameters - \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum - \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation - \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex - \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex - \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex - \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex - \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII - \param[in] checksum: IP frame checksum offload function, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum - \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function - \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function - \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped - \param[in] recept: frame filter function, only one parameter can be selected - which is shown as below, refer to enet_frmrecept_enum - \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled - \arg ENET_RECEIVEALL: all received frame are forwarded to application - \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames - \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) -{ - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; - uint32_t media_temp = 0U; - uint32_t timeout = 0U; - uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; - - /* PHY interface configuration, configure SMI clock and reset PHY chip */ - if(ERROR == enet_phy_config()){ - _ENET_DELAY_(PHY_RESETDELAY); - if(ERROR == enet_phy_config()){ - return enet_state; - } - } - /* initialize ENET peripheral with generally concerned parameters */ - enet_default_init(); - - /* 1st, configure mediamode */ - media_temp = (uint32_t)mediamode; - /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ - /* wait for PHY_LINKED_STATUS bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; - timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* enable auto-negotiation */ - phy_value = PHY_AUTONEGOTIATION; - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - - /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_AUTONEGO_COMPLETE; - timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); - /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ - media_temp = ENET_MODE_FULLDUPLEX; - }else{ - media_temp = ENET_MODE_HALFDUPLEX; - } - /* configure the communication speed of MAC following the auto-negotiation result */ - if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ - media_temp |= ENET_SPEEDMODE_10M; - }else{ - media_temp |= ENET_SPEEDMODE_100M; - } - }else{ - phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); - phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - /* PHY configuration need some time */ - _ENET_DELAY_(PHY_CONFIGDELAY); - } - /* after configuring the PHY, use mediamode to configure registers */ - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); - reg_value |= media_temp; - ENET_MAC_CFG = reg_value; - - - /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ - ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~ENET_DMA_CTL_DTCERFD; - reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); - ENET_DMA_CTL = reg_value; - } - - /* 3rd, configure recept */ - ENET_MAC_FRMF |= (uint32_t)recept; - - /* 4th, configure different function options */ - /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ - reg_temp = enet_initpara.forward_frame; - - reg_value = ENET_MAC_CFG; - temp = reg_temp; - /* configure ENET_MAC_CFG register */ - reg_value &= (~ENET_MAC_CFG_APCD); - temp &= ENET_MAC_CFG_APCD; - reg_value |= temp; - ENET_MAC_CFG = reg_value; - - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); - temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); - reg_value |= (temp >> 2); - ENET_DMA_CTL = reg_value; - } - - /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ - temp = enet_initpara.dmabus_mode; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ - temp = enet_initpara.dma_maxburst; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ - temp = enet_initpara.dma_arbitration; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ - temp = enet_initpara.store_forward_mode; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - } - - /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ - reg_temp = enet_initpara.dma_function; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); - reg_value |= reg_temp; - ENET_DMA_CTL = reg_value; - } - - /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ - reg_temp = enet_initpara.vlan_config; - - reg_value = ENET_MAC_VLT; - /* configure ENET_MAC_VLT register */ - reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); - reg_value |= reg_temp; - ENET_MAC_VLT = reg_value; - } - - /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ - reg_temp = enet_initpara.flow_control; - - reg_value = ENET_MAC_FCTL; - temp = reg_temp; - /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - reg_value |= temp; - ENET_MAC_FCTL = reg_value; - - reg_value = ENET_MAC_FCTH; - temp = reg_temp; - /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); - reg_value |= (temp >> 8); - ENET_MAC_FCTH = reg_value; - } - - /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ - ENET_MAC_HLH = enet_initpara.hashtable_high; - } - - /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ - ENET_MAC_HLL = enet_initpara.hashtable_low; - } - - /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ - reg_temp = enet_initpara.framesfilter_mode; - - reg_value = ENET_MAC_FRMF; - /* configure ENET_MAC_FRMF register */ - reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); - reg_value |= reg_temp; - ENET_MAC_FRMF = reg_value; - } - - /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ - reg_temp = enet_initpara.halfduplex_param; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ - reg_temp = enet_initpara.timer_config; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ - reg_temp = enet_initpara.interframegap; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~ENET_MAC_CFG_IGBS; - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - enet_state = SUCCESS; - return enet_state; -} - -/*! - \brief reset all core internal registers located in CLK_TX and CLK_RX - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_software_reset(void) -{ - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - uint32_t dma_flag; - - /* reset all core internal registers located in CLK_TX and CLK_RX */ - ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - - /* wait for reset operation complete */ - do{ - dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); - timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - - /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief check receive frame valid and return frame size - \param[in] none - \param[out] none - \retval size of received frame: 0x0 - 0x3FFF -*/ -uint32_t enet_rxframe_size_get(void) -{ - uint32_t size = 0U; - uint32_t status; - - /* get rdes0 information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - - /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ - return 0U; - } - - /* if has any error, or the frame uses two or more descriptors */ - if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; - } - - /* if is an ethernet-type frame, and IP frame payload error occurred */ - if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; - } - - /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ - if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ - /* get the size of the received data including CRC */ - size = GET_RDES0_FRML(status); - /* substract the CRC size */ - size = size - 4U; - }else{ - enet_unknow_err++; - enet_rxframe_drop(); - - return 1U; - } - - /* return packet size */ - return size; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_chain_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode */ - desc_status = ENET_TDES0_TCHM; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; - } - } -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_ring_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc; - enet_descriptors_struct *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* set buffer1 size */ - desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - } -} - -/*! - \brief handle current received frame data to application buffer - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] buffer: pointer to the received frame data - note -- if the input is NULL, user should copy data in application by himself - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status); - size = size - 4U; - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); - } - - }else{ - /* return ERROR */ - return ERROR; - } - } - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief handle application buffer data to transmit it - \param[in] buffer: pointer to the frame data to be transmitted, - note -- if the input is NULL, user should handle the data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) -{ - uint32_t offset = 0U; - uint32_t dma_tbu_flag, dma_tu_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief configure the transmit IP frame checksum offload calculation and insertion - \param[in] desc: the descriptor pointer which users want to configure - \param[in] checksum: IP frame checksum configuration - only one parameter can be selected which is shown as below - \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled - \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled - \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header - \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated - \param[out] none - \retval none -*/ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) -{ - desc->status &= ~ENET_TDES0_CM; - desc->status |= checksum; -} - -/*! - \brief ENET Tx and Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_enable(void) -{ - enet_tx_enable(); - enet_rx_enable(); -} - -/*! - \brief ENET Tx and Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_disable(void) -{ - enet_tx_disable(); - enet_rx_disable(); -} - -/*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: set MAC address 0 filter - \arg ENET_MAC_ADDRESS1: set MAC address 1 filter - \arg ENET_MAC_ADDRESS2: set MAC address 2 filter - \arg ENET_MAC_ADDRESS3: set MAC address 3 filter - \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \param[out] none - \retval none -*/ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); - REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); -} - -/*! - \brief get MAC address - \param[in] mac_addr: select which MAC address will be get, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: get MAC address 0 filter - \arg ENET_MAC_ADDRESS1: get MAC address 1 filter - \arg ENET_MAC_ADDRESS2: get MAC address 2 filter - \arg ENET_MAC_ADDRESS3: get MAC address 3 filter - \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \retval none -*/ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); - paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); - paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); - paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); - paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); - paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); -} - -/*! - \brief get the ENET MAC/MSC/PTP/DMA status flag - \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, - only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag - \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag - \arg ENET_MAC_FLAG_WUM: WUM status flag - \arg ENET_MAC_FLAG_MSC: MSC status flag - \arg ENET_MAC_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag - \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag - \arg ENET_PTP_FLAG_TTM: target time match flag - \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_FLAG_TS: transmit status flag - \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_FLAG_RO: receive overflow status flag - \arg ENET_DMA_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_FLAG_RS: receive status flag - \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_FLAG_ET: early transmit status flag - \arg ENET_DMA_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_FLAG_ER: early receive status flag - \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag - \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag - \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag - \arg ENET_DMA_FLAG_MSC: MSC status flag - \arg ENET_DMA_FLAG_WUM: WUM status flag - \arg ENET_DMA_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_flag_get(enet_flag_enum enet_flag) -{ - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the ENET DMA status flag - \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear - \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear - \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear - \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear - \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear - \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear - \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear - \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear - \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear - \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear - \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear - \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear - \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear - \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear - \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear - \param[out] none - \retval none -*/ -void enet_flag_clear(enet_flag_clear_enum enet_flag) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); -} - -/*! - \brief enable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_enable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief disable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_disable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief get ENET MAC/MSC/DMA interrupt flag - \param[in] int_flag: ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_FLAG_WUM: WUM status flag - \arg ENET_MAC_INT_FLAG_MSC: MSC status flag - \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag - \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_INT_FLAG_TS: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS: receive status flag - \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER: early receive status flag - \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_INT_FLAG_MSC: MSC status flag - \arg ENET_DMA_INT_FLAG_WUM: WUM status flag - \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) -{ - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear ENET DMA interrupt flag - \param[in] int_flag_clear: clear ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag - \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag - \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag - \param[out] none - \retval none -*/ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); -} - -/*! - \brief ENET Tx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_TEN; - enet_txfifo_flush(); - ENET_DMA_CTL |= ENET_DMA_CTL_STE; -} - -/*! - \brief ENET Tx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; - enet_txfifo_flush(); - ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; -} - -/*! - \brief ENET Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_REN; - ENET_DMA_CTL |= ENET_DMA_CTL_SRE; -} - -/*! - \brief ENET Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; - ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; -} - -/*! - \brief put registers value into the application buffer - \param[in] type: register type which will be get, refer to enet_registers_type_enum, - only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH - \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT - \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL - \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR - \param[in] num: the number of registers that the user want to get - \param[out] preg: the application buffer pointer for storing the register value - \retval none -*/ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) -{ - uint32_t offset = 0U, max = 0U, limit = 0U; - - offset = (uint32_t)type; - max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - - /* prevent element in this array is out of range */ - if(max > limit){ - max = limit; - } - - for(; offset < max; offset++){ - /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); - preg++; - } -} - -/*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable - \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_enable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief disable the MAC address filter - \param[in] mac_addr: select which MAC address will be disable, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_disable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief configure the MAC address filter - \param[in] mac_addr: select which MAC address will be configured, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter - \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter - \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter - \param[in] addr_mask: select which MAC address bytes will be mask, - one or more parameters can be selected which are shown as below - \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits - \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits - \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits - \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits - \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits - \param[in] filter_type: select which MAC address filter type will be selected, - only one parameter can be selected which is shown as below - \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame - \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame - \param[out] none - \retval none -*/ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) -{ - uint32_t reg; - - /* get the address filter register value which is to be configured */ - reg = REG32(ENET_ADDRH_BASE + mac_addr); - - /* clear and configure the address filter register */ - reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); - reg |= (addr_mask | filter_type); - REG32(ENET_ADDRH_BASE + mac_addr) = reg; -} - -/*! - \brief PHY interface configuration (configure SMI clock and reset PHY chip) - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_config(void) -{ - uint32_t ahbclk; - uint32_t reg; - uint16_t phy_value; - ErrStatus enet_state = ERROR; - - /* clear the previous MDC clock */ - reg = ENET_MAC_PHY_CTL; - reg &= ~ENET_MAC_PHY_CTL_CLR; - - /* get the HCLK frequency */ - ahbclk = rcu_clock_freq_get(CK_AHB); - - /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ - reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ - reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){ - reg |= ENET_MDC_HCLK_DIV42; - }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV62; - }else{ - return enet_state; - } - ENET_MAC_PHY_CTL = reg; - - /* reset PHY */ - phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - /* PHY reset need some time */ - _ENET_DELAY_(ENET_DELAY_TO); - - /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - - /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief write to / read from a PHY register - \param[in] direction: only one parameter can be selected which is shown as below - \arg ENET_PHY_WRITE: write data to phy register - \arg ENET_PHY_READ: read data from phy register - \param[in] phy_address: 0x0 - 0x1F - \param[in] phy_reg: 0x0 - 0x1F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction - \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) -{ - uint32_t reg, phy_flag; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* configure ENET_MAC_PHY_CTL with write/read operation */ - reg = ENET_MAC_PHY_CTL; - reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); - - /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; - } - - /* do PHY write/read operation, and wait the operation complete */ - ENET_MAC_PHY_CTL = reg; - do{ - phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); - timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - - /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ - enet_state = SUCCESS; - } - - /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; - } - - return enet_state; -} - -/*! - \brief enable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_enable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* enable the PHY loopback mode */ - temp_phy |= PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief disable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_disable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* disable the PHY loopback mode */ - temp_phy &= (uint16_t)~PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief enable ENET forward feature - \param[in] feature: the feature of ENET forward mode, - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames - \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames - \param[out] none - \retval none -*/ -void enet_forward_feature_enable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG |= mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); - ENET_DMA_CTL |= (mask >> 2); -} - -/*! - \brief disable ENET forward feature - \param[in] feature: the feature of ENET forward mode, - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function - \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_forward_feature_disable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG &= ~mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); - ENET_DMA_CTL &= ~(mask >> 2); -} - -/*! - \brief enable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_enable(uint32_t feature) -{ - ENET_MAC_FRMF |= feature; -} - -/*! - \brief disable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_disable(uint32_t feature) -{ - ENET_MAC_FRMF &= ~feature; -} - -/*! - \brief generate the pause frame, ENET will send pause frame after enable transmit flow control - this function only use in full-dulex mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_pauseframe_generate(void) -{ - ErrStatus enet_state =ERROR; - uint32_t temp = 0U; - - /* in full-duplex mode, must make sure this bit is 0 before writing register */ - temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ - ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; - enet_state = SUCCESS; - } - return enet_state; -} - -/*! - \brief configure the pause frame detect type - \param[in] detect: pause frame detect type, - only one parameter can be selected which is shown as below - \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also - use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified - in IEEE802.3 can be detected - \param[out] none - \retval none -*/ -void enet_pauseframe_detect_config(uint32_t detect) -{ - ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; - ENET_MAC_FCTL |= detect; -} - -/*! - \brief configure the pause frame parameters - \param[in] pausetime: pause time in transmit pause control frame - \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, - this value must make sure to be less than configured pause time, only one parameter can be - selected which is shown as below - \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times - \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times - \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times - \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times - \param[out] none - \retval none -*/ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) -{ - ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); - ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); -} - -/*! - \brief configure the threshold of the flow control(deactive and active threshold) - \param[in] deactive: the threshold of the deactive flow control, this value - should always be less than active flow control value, only one - parameter can be selected which is shown as below - \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[in] active: the threshold of the active flow control, only one parameter - can be selected which is shown as below - \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[out] none - \retval none -*/ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) -{ - ENET_MAC_FCTH = ((deactive | active) >> 8); -} - -/*! - \brief enable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_enable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL |= feature; -} - -/*! - \brief disable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_disable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL &= ~feature; -} - -/*! - \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: dma transmit process - \arg ENET_DMA_RX: dma receive process - \param[out] none - \retval state of dma process, the value range shows below: - ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, - ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, - ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, - ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING -*/ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) -{ - uint32_t reval; - reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); - return reval; -} - -/*! - \brief poll the DMA transmission/reception enable by writing any value to the - ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA transmit process - \arg ENET_DMA_RX: DMA receive process - \param[out] none - \retval none -*/ -void enet_dmaprocess_resume(enet_dmadirection_enum direction) -{ - if(ENET_DMA_TX == direction){ - ENET_DMA_TPEN = 0U; - }else{ - ENET_DMA_RPEN = 0U; - } -} - -/*! - \brief check and recover the Rx process - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxprocess_check_recovery(void) -{ - uint32_t status; - - /* get DAV information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with - receive descriptor address pointer updated by RxDMA controller */ - if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; - } -} - -/*! - \brief flush the ENET transmit FIFO, and wait until the flush operation completes - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_txfifo_flush(void) -{ - uint32_t flush_state; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; - /* wait until the flush operation completes */ - do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; - timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(RESET == flush_state){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table - \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, - only one parameter can be selected which is shown as below - \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table - \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by - the RxDMA controller - \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller - \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table - \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by - the TxDMA controller - \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none - \retval address value -*/ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) -{ - uint32_t reval = 0U; - - reval = REG32((ENET) +(uint32_t)addr_get); - return reval; -} - -/*! - \brief get the Tx or Rx descriptor information - \param[in] desc: the descriptor pointer which users want to get information - \param[in] info_get: the descriptor information type which is selected, - only one parameter can be selected which is shown as below - \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size - \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size - \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer - \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted - \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame - \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame - \param[out] none - \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter -*/ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) -{ - uint32_t reval = 0xFFFFFFFFU; - - switch(info_get){ - case RXDESC_BUFFER_1_SIZE: - reval = GET_RDES1_RB1S(desc->control_buffer_size); - break; - case RXDESC_BUFFER_2_SIZE: - reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: - reval = GET_RDES0_FRML(desc->status); - if(reval > 4U){ - reval = reval - 4U; - }else{ - reval = 0U; - } - break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_COLLISION_COUNT: - reval = GET_TDES0_COCNT(desc->status); - break; - default: - break; - } - return reval; -} - -/*! - \brief get the number of missed frames during receiving - \param[in] none - \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO - \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller - \retval none -*/ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) -{ - uint32_t temp_counter = 0U; - - temp_counter = ENET_DMA_MFBOCNT; - *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); - *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); -} - -/*! - \brief get the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to get flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred - \arg ENET_TDES0_UFE: underflow error - \arg ENET_TDES0_EXD: excessive deferral - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_ECO: excessive collision - \arg ENET_TDES0_LCO: late collision - \arg ENET_TDES0_NCA: no carrier - \arg ENET_TDES0_LCA: loss of carrier - \arg ENET_TDES0_IPPE: IP payload error - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_JT: jabber timeout - \arg ENET_TDES0_ES: error summary - \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error - \arg ENET_RDES0_CERR: CRC error - \arg ENET_RDES0_DBERR: dribble bit error - \arg ENET_RDES0_RERR: receive error - \arg ENET_RDES0_RWDT: receive watchdog timeout - \arg ENET_RDES0_FRMT: frame type - \arg ENET_RDES0_LCO: late collision - \arg ENET_RDES0_IPHERR: IP frame header error - \arg ENET_RDES0_LDES: last descriptor - \arg ENET_RDES0_FDES: first descriptor - \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error - \arg ENET_RDES0_LERR: length error - \arg ENET_RDES0_SAFF: SA filter fail - \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary - \arg ENET_RDES0_DAFF: destination address filter fail - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - FlagStatus enet_flag = RESET; - - if ((uint32_t)RESET != (desc->status & desc_flag)){ - enet_flag = SET; - } - - return enet_flag; -} - -/*! - \brief set the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to set flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status |= desc_flag; -} - -/*! - \brief clear the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to clear flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status &= ~desc_flag; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will set - \param[in] desc: the descriptor pointer which users want to configure - \param[out] none - \retval none -*/ -void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc) -{ - desc->control_buffer_size &= ~ENET_RDES1_DINTC; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will not set - \param[in] desc: the descriptor pointer which users want to configure - \param[out] none - \retval none -*/ -void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc) -{ - desc->control_buffer_size |= ENET_RDES1_DINTC; -} - -/*! - \brief drop current receive frame - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxframe_drop(void) -{ - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - } - - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - } - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc++; - } - } - } -} - -/*! - \brief enable DMA feature - \param[in] feature: the feature of DMA mode, - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_enable(uint32_t feature) -{ - ENET_DMA_CTL |= feature; -} - -/*! - \brief disable DMA feature - \param[in] feature: the feature of DMA mode, - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_disable(uint32_t feature) -{ - ENET_DMA_CTL &= ~feature; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select ring mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive ring mode and set buffer1 size */ - desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] timestamp: pointer to the table which stores the timestamp high and low - \param[out] buffer: pointer to the application buffer - note -- if the input is NULL, user should copy data in application by himself - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); - } - - }else{ - return ERROR; - } - } - /* copy timestamp value from Rx descriptor to application array */ - timestamp[0] = dma_current_rxdesc->buffer1_addr; - timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; - - dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; - dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_rxdesc ++; - } - } - - return SUCCESS; -} - -/*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode - \param[in] buffer: pointer on the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) -{ - uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->buffer1_addr; - timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; - } - dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; - dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_txdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; - } - } - return SUCCESS; -} - -/*! - \brief wakeup frame filter register pointer reset - \param[in] none - \param[out] none - \retval none -*/ -void enet_wum_filter_register_pointer_reset(void) -{ - ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; -} - -/*! - \brief set the remote wakeup frame registers - \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) - \param[out] none - \retval none -*/ -void enet_wum_filter_config(uint32_t pdata[]) -{ - uint32_t num = 0U; - - /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ - ENET_MAC_RWFF = pdata[num]; - } -} - -/*! - \brief enable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_WUM_POWER_DOWN: power down mode - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_enable(uint32_t feature) -{ - ENET_MAC_WUM |= feature; -} - -/*! - \brief disable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_disable(uint32_t feature) -{ - ENET_MAC_WUM &= (~feature); -} - -/*! - \brief reset the MAC statistics counters - \param[in] none - \param[out] none - \retval none -*/ -void enet_msc_counters_reset(void) -{ - /* reset all counters */ - ENET_MSC_CTL |= ENET_MSC_CTL_CTR; -} - -/*! - \brief enable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_enable(uint32_t feature) -{ - ENET_MSC_CTL |= feature; -} - -/*! - \brief disable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_disable(uint32_t feature) -{ - ENET_MSC_CTL &= (~feature); -} - -/*! - \brief get MAC statistics counter - \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, - only one parameter can be selected which is shown as below - \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter - \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter - \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter - \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter - \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter - \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter - \param[out] none - \retval the MSC counter value -*/ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) -{ - uint32_t reval; - - reval = REG32((ENET + (uint32_t)counter)); - - return reval; -} - -/*! - \brief change subsecond to nanosecond - \param[in] subsecond: subsecond value - \param[out] none - \retval the nanosecond value -*/ -uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) -{ - uint64_t val = subsecond * 1000000000Ull; - val >>= 31; - return (uint32_t)val; -} - -/*! - \brief change nanosecond to subsecond - \param[in] nanosecond: nanosecond value - \param[out] none - \retval the subsecond value -*/ -uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond) -{ - uint64_t val = nanosecond * 0x80000000Ull; - val /= 1000000000U; - return (uint32_t)val; -} - -/*! - \brief enable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \param[out] none - \retval none -*/ -void enet_ptp_feature_enable(uint32_t feature) -{ - ENET_PTP_TSCTL |= feature; -} - -/*! - \brief disable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \param[out] none - \retval none -*/ -void enet_ptp_feature_disable(uint32_t feature) -{ - ENET_PTP_TSCTL &= ~feature; -} - -/*! - \brief configure the PTP timestamp function - \param[in] func: only one parameter can be selected which is shown as below - \arg ENET_PTP_ADDEND_UPDATE: addend register update - \arg ENET_PTP_SYSTIME_UPDATE: timestamp update - \arg ENET_PTP_SYSTIME_INIT: timestamp initialize - \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating - \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ - -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) -{ - uint32_t temp_config = 0U, temp_state = 0U; - uint32_t timeout = 0U; - ErrStatus enet_state = SUCCESS; - - switch(func){ - case ENET_PTP_ADDEND_UPDATE: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } - break; - case ENET_PTP_SYSTIME_UPDATE: - /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; - case ENET_PTP_SYSTIME_INIT: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; - default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; - } - break; - } - - return enet_state; -} - -/*! - \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time, - this value must be between 0 and 0xFF - \param[out] none - \retval none -*/ -void enet_ptp_subsecond_increment_config(uint32_t subsecond) -{ - ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); -} - -/*! - \brief adjusting the clock frequency only in fine update mode - \param[in] add: the value will be added to the accumulator register to achieve time synchronization - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_addend_config(uint32_t add) -{ - ENET_PTP_TSADDEND = add; -} - -/*! - \brief initialize or add/subtract to second of the system time - \param[in] sign: timestamp update positive or negative sign, - only one parameter can be selected which is shown as below - \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time - \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time - \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time - with 0.46 ns accuracy if required accuracy is 20 ns - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) -{ - ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); -} - -/*! - \brief configure the expected target time - \param[in] second: the expected target second time - \param[in] nanosecond: the expected target nanosecond time (signed) - \param[out] none - \retval none -*/ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) -{ - ENET_PTP_ETH = second; - ENET_PTP_ETL = nanosecond; -} - -/*! - \brief get the current system time - \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \retval none -*/ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) -{ - uint32_t temp_sec = 0U, temp_subs = 0U; - - /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; - temp_subs = (uint32_t)ENET_PTP_TSL; - - /* get sysytem time and construct the enet_ptp_systime_struct structure */ - systime_struct->second = temp_sec; - systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); - systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); - systime_struct->sign = GET_PTP_TSL_STS(temp_subs); -} - -/*! - \brief configure and start PTP timestamp counter - \param[in] updatemethod: method for updating - \arg ENET_PTP_FINEMODE: fine correction method - \arg ENET_PTP_COARSEMODE: coarse correction method - \param[in] init_sec: second value for initializing system time - \param[in] init_subsec: subsecond value for initializing system time - \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used) - \param[in] accuracy_cfg: the value to be added to the subsecond value of system time - \param[out] none - \retval none -*/ -void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) -{ - /* mask the timestamp trigger interrupt */ - enet_interrupt_disable(ENET_MAC_INT_TMSTIM); - - /* enable timestamp */ - enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP); - - /* configure system time subsecond increment based on the PTP clock frequency */ - enet_ptp_subsecond_increment_config(accuracy_cfg); - - if(ENET_PTP_FINEMODE == updatemethod){ - /* fine correction method: configure the timestamp addend, then update */ - enet_ptp_timestamp_addend_config(carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); - /* wait until update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ - } - } - - /* choose the fine correction method */ - enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod); - - /* initialize the system time */ - enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); -} - -/*! - \brief adjust frequency in fine method by configure addend register - \param[in] carry_cfg: the value to be added to the accumulator register - \param[out] none - \retval none -*/ -void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) -{ - /* re-configure the timestamp addend, then update */ - enet_ptp_timestamp_addend_config((uint32_t)carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); -} - -/*! - \brief update system time in coarse method - \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \param[out] none - \retval none -*/ -void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct) -{ - uint32_t subsecond_val; - uint32_t carry_cfg; - - subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); - - /* save the carry_cfg value */ - carry_cfg = ENET_PTP_TSADDEND_TMSA; - - /* update the system time */ - enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); - - /* wait until the update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ - } - - /* write back the carry_cfg value, then update */ - enet_ptp_timestamp_addend_config(carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); -} - -/*! - \brief set system time in fine method - \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \param[out] none - \retval none -*/ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) -{ - uint32_t subsecond_val; - - subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); - - /* initialize the system time */ - enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); - - /* wait until the system time initialzation finished */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ - } -} - -/*! - \brief get the ptp flag status - \param[in] flag: ptp flag status to be checked - \arg ENET_PTP_ADDEND_UPDATE: addend register update - \arg ENET_PTP_SYSTIME_UPDATE: timestamp update - \arg ENET_PTP_SYSTIME_INIT: timestamp initialize - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_ptp_flag_get(uint32_t flag) -{ - FlagStatus bitstatus = RESET; - - if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ - bitstatus = SET; - } - - return bitstatus; -} - -/*! - \brief reset the ENET initpara struct, call it before using enet_initpara_config() - \param[in] none - \param[out] none - \retval none -*/ -void enet_initpara_reset(void) -{ - enet_initpara.option_enable = 0U; - enet_initpara.forward_frame = 0U; - enet_initpara.dmabus_mode = 0U; - enet_initpara.dma_maxburst = 0U; - enet_initpara.dma_arbitration = 0U; - enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; - enet_initpara.vlan_config = 0U; - enet_initpara.flow_control = 0U; - enet_initpara.hashtable_high = 0U; - enet_initpara.hashtable_low = 0U; - enet_initpara.framesfilter_mode = 0U; - enet_initpara.halfduplex_param = 0U; - enet_initpara.timer_config = 0U; - enet_initpara.interframegap = 0U; -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() - \param[in] none - \param[out] none - \retval none -*/ -static void enet_default_init(void) -{ - uint32_t reg_value = 0U; - - /* MAC */ - /* configure ENET_MAC_CFG register */ - reg_value = ENET_MAC_CFG; - reg_value &= MAC_CFG_MASK; - reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; - ENET_MAC_CFG = reg_value; - - /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; - - /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ - ENET_MAC_HLH = 0x0U; - - ENET_MAC_HLL = 0x0U; - - /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ - reg_value = ENET_MAC_FCTL; - reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; - ENET_MAC_FCTL = reg_value; - - ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - - /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); - - /* DMA */ - /* configure ENET_DMA_CTL register */ - reg_value = ENET_DMA_CTL; - reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; - ENET_DMA_CTL = reg_value; - - /* configure ENET_DMA_BCTL register */ - reg_value = ENET_DMA_BCTL; - reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE; - ENET_DMA_BCTL = reg_value; -} - -#ifndef USE_DELAY -/*! - \brief insert a delay time - \param[in] ncount: specifies the delay time length - \param[out] none - \param[out] none -*/ -static void enet_delay(uint32_t ncount) -{ - uint32_t delay_time = 0U; - - for(delay_time = ncount; delay_time != 0U; delay_time--){ - } -} -#endif /* USE_DELAY */ - -#endif /* GD32F10X_CL */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c deleted file mode 100644 index 641e716ca1..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c +++ /dev/null @@ -1,646 +0,0 @@ -/*! - \file gd32f10x_exmc.c - \brief EXMC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_exmc.h" - -/* EXMC bank0 register reset value */ -#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU) -#define BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U) -#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) -#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) - -/* EXMC bank1/2 register reset mask*/ -#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) - -/* EXMC bank3 register reset mask*/ -#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) - -/* EXMC register bit offset */ -#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) -#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) -#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) -#define SNCTL_WREN_OFFSET ((uint32_t)12U) -#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) -#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) -#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) - -#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) -#define SNTCFG_DSET_OFFSET ((uint32_t)8U) -#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) - -#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) -#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) -#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) - -#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) -#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) - -#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) -#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) - -#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) -#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) -#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) - -#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) -#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) -#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) - -#define INTEN_INTS_OFFSET ((uint32_t)3U) - -/*! - \brief deinitialize EXMC NOR/SRAM region - \param[in] norsram_region: select the region of bank0 - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_deinit(uint32_t norsram_region) -{ - /* reset the registers */ - if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){ - EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; - }else{ - EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET; - } - - EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET; - EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET; -} - -/*! - \brief initialize EXMC NOR/SRAM region - \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 - write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE - asyn_wait: ENABLE or DISABLE - nwait_signal: ENABLE or DISABLE - memory_write: ENABLE or DISABLE - nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING - wrap_burst_mode: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH - burst_mode: ENABLE or DISABLE - databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR - address_data_mux: ENABLE or DISABLE - read_write_timing: struct exmc_norsram_timing_parameter_struct set the time - write_timing: struct exmc_norsram_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; - - /* get the register value */ - snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); - - /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRMUX )); - - snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - - sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| - (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | - (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | - (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )| - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ - snctl |= (uint32_t)EXMC_SNCTL_NREN; - } - - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode){ - snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) | - (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)| - (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) | - exmc_norsram_init_struct->write_timing->asyn_access_mode); - }else{ - snwtcfg = BANK0_SNWTCFG_RESET; - } - - /* configure the registers */ - EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; - EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; - EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; -} - -/*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - /* configure the structure with default value */ - exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; - exmc_norsram_init_struct->address_data_mux = ENABLE; - exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; - exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; - exmc_norsram_init_struct->burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - exmc_norsram_init_struct->wrap_burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; - exmc_norsram_init_struct->memory_write = ENABLE; - exmc_norsram_init_struct->nwait_signal = ENABLE; - exmc_norsram_init_struct->extended_mode = DISABLE; - exmc_norsram_init_struct->asyn_wait = DISABLE; - exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - - /* read/write timing configure */ - exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; - exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; - exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - - /* write timing configure, when extended mode is used */ - exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; -} - -/*! - \brief enable EXMC NOR/PSRAM bank region - \param[in] norsram_region: specifie the region of NOR/PSRAM bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_enable(uint32_t norsram_region) -{ - EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief disable EXMC NOR/PSRAM bank region - \param[in] norsram_region: specifie the region of NOR/PSRAM Bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_disable(uint32_t norsram_region) -{ - EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief deinitialize EXMC NAND bank - \param[in] nand_bank: select the bank of NAND - \arg EXMC_BANKx_NAND(x=1..2) - \param[out] none - \retval none -*/ -void exmc_nand_deinit(uint32_t nand_bank) -{ - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ - EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET; - EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET; - EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET; - EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET; -} - -/*! - \brief initialize EXMC NAND bank - \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter - nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND - ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - ecc_logic: ENABLE or DISABLE - databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - - npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| - EXMC_NPCTL_NDTP | - exmc_nand_init_struct->databus_width | - (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| - exmc_nand_init_struct->ecc_size | - exmc_nand_init_struct->ctr_latency | - exmc_nand_init_struct->atr_latency; - - npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ - EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; - EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; - EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; -} - -/*! - \brief initialize the struct exmc_nand_init_struct - \param[in] none - \param[out] the initialized struct exmc_nand_init_struct pointer - \retval none -*/ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - /* configure the structure with default value */ - exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; - exmc_nand_init_struct->wait_feature = DISABLE; - exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; - exmc_nand_init_struct->ecc_logic = DISABLE; - exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; - exmc_nand_init_struct->ctr_latency = 0x0U; - exmc_nand_init_struct->atr_latency = 0x0U; - exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; - exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief enable NAND bank - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_enable(uint32_t nand_bank) -{ - EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable NAND bank - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_disable(uint32_t nand_bank) -{ - EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN; -} - -/*! - \brief enable or disable the EXMC NAND ECC function - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue) -{ - if (ENABLE == newvalue){ - /* enable the selected NAND bank ECC function */ - EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN; - }else{ - /* disable the selected NAND bank ECC function */ - EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN; - } -} - -/*! - \brief get the EXMC ECC value - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval the error correction code(ECC) value -*/ -uint32_t exmc_ecc_get(uint32_t nand_bank) -{ - return (EXMC_NECC(nand_bank)); -} - -/*! - \brief deinitialize EXMC PC card bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_deinit(void) -{ - /* EXMC_BANK3_PCCARD */ - EXMC_NPCTL3 = BANK3_NPCTL_RESET; - EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; - EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; - EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; - EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; -} - -/*! - \brief initialize EXMC PC card bank - \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the EXMC bank3 PC card control register */ - EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; - - /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) | - (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )| - (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | - (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | - ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )| - ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); -} - -/*! - \brief initialize the struct exmc_pccard_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer - \retval none -*/ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the structure with default value */ - exmc_pccard_init_struct->wait_feature = DISABLE; - exmc_pccard_init_struct->ctr_latency = 0x0U; - exmc_pccard_init_struct->atr_latency = 0x0U; - exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief enable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_enable(void) -{ - EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_disable(void) -{ - EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; -} - -/*! - \brief enable EXMC interrupt - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source) -{ - /* NAND bank1, bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) |= interrupt_source; -} - -/*! - \brief disable EXMC interrupt - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~interrupt_source; -} - -/*! - \brief check EXMC flag is set or not - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC Card bank - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag) -{ - uint32_t status = 0x00000000U; - - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(bank); - - if ((status & flag) != (uint32_t)flag ){ - /* flag is reset */ - return RESET; - }else{ - /* flag is set */ - return SET; - } -} - -/*! - \brief clear EXMC flag - \param[in] bank: specifie the NAND bank, PCCARD bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] flag: specify get which flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \param[out] none - \retval none -*/ -void exmc_flag_clear(uint32_t bank, uint32_t flag) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~flag; -} - -/*! - \brief check EXMC interrupt flag is set or not - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source) -{ - uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; - - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(bank); - interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); - - interrupt_enable = (status & interrupt_source); - - if ((interrupt_enable) && (interrupt_state)){ - /* interrupt flag is set */ - return SET; - }else{ - /* interrupt flag is reset */ - return RESET; - } -} - -/*! - \brief clear EXMC interrupt flag - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source) -{ - /* NAND bank1, bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c deleted file mode 100644 index dcda291314..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c +++ /dev/null @@ -1,256 +0,0 @@ -/*! - \file gd32f10x_exti.c - \brief EXTI driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_exti.h" - -#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = EXTI_REG_RESET_VALUE; - EXTI_EVEN = EXTI_REG_RESET_VALUE; - EXTI_RTEN = EXTI_REG_RESET_VALUE; - EXTI_FTEN = EXTI_REG_RESET_VALUE; - EXTI_SWIEV = EXTI_REG_RESET_VALUE; -} - -/*! - \brief initialize the EXTI - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling edge trigger - \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch(trig_type){ - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI lines flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c deleted file mode 100644 index 83da3519e0..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c +++ /dev/null @@ -1,965 +0,0 @@ -/*! - \file gd32f10x_fmc.c - \brief FMC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_fmc.h" - -/*! - \brief set the wait state counter value - \param[in] wscnt£ºwait state counter value - \arg WS_WSCNT_0: FMC 0 wait state - \arg WS_WSCNT_1: FMC 1 wait state - \arg WS_WSCNT_2: FMC 2 wait state - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint32_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief unlock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ - /* write the FMC unlock key */ - FMC_KEY0 = UNLOCK_KEY0; - FMC_KEY0 = UNLOCK_KEY1; - } - - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* write the FMC unlock key */ - if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ - FMC_KEY1 = UNLOCK_KEY0; - FMC_KEY1 = UNLOCK_KEY1; - } - } -} - -/*! - \brief unlock the FMC bank0 operation - this function can be used for all GD32F10x devices. - for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. - for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank0_unlock(void) -{ - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ - /* write the FMC unlock key */ - FMC_KEY0 = UNLOCK_KEY0; - FMC_KEY0 = UNLOCK_KEY1; - } -} - -/*! - \brief unlock the FMC bank1 operation - this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank1_unlock(void) -{ - if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ - /* write the FMC unlock key */ - FMC_KEY1 = UNLOCK_KEY0; - FMC_KEY1 = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit */ - FMC_CTL0 |= FMC_CTL0_LK; - - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* set the LK bit */ - FMC_CTL1 |= FMC_CTL1_LK; - } -} - -/*! - \brief lock the FMC bank0 operation - this function can be used for all GD32F10X devices. - for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. - for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank0_lock(void) -{ - /* set the LK bit*/ - FMC_CTL0 |= FMC_CTL0_LK; -} - -/*! - \brief lock the FMC bank1 operation - this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank1_lock(void) -{ - /* set the LK bit*/ - FMC_CTL1 |= FMC_CTL1_LK; -} - -/*! - \brief erase page - \param[in] page_address: the page address to be erased. - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state; - - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > page_address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_PER; - FMC_ADDR0 = page_address; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL0 &= ~FMC_CTL0_PER; - } - }else{ - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL1 |= FMC_CTL1_PER; - FMC_ADDR1 = page_address; - if(FMC_OBSTAT & FMC_OBSTAT_SPC){ - FMC_ADDR0 = page_address; - } - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL1 &= ~FMC_CTL1_PER; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_PER; - FMC_ADDR0 = page_address; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL0 &= ~FMC_CTL0_PER; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state; - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL1 |= FMC_CTL1_MER; - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL1 &= ~FMC_CTL1_MER; - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase bank0 - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start FMC bank0 erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief erase bank1 - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start FMC bank1 erase */ - FMC_CTL1 |= FMC_CTL1_MER; - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL1 &= ~FMC_CTL1_MER; - } - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL1 |= FMC_CTL1_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL1 &= ~FMC_CTL1_PG; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a half word at the corresponding address - \param[in] address: address to program - \param[in] data: halfword to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - if(FMC_BANK0_SIZE > FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL1 |= FMC_CTL1_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL1 &= ~FMC_CTL1_PG; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } - - /* wait until OBWEN bit is set by hardware */ - while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ - } -} - -/*! - \brief lock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWEN bit */ - FMC_CTL0 &= ~FMC_CTL0_OBWEN; -} - -/*! - \brief erase the FMC option byte - unlock the FMC_CTL0 and option byte before calling this function - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_erase(void) -{ - uint16_t temp_spc = FMC_NSPC; - - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - /* check the option byte security protection value */ - if(RESET != ob_spc_get()){ - temp_spc = FMC_USPC; - } - - if(FMC_READY == fmc_state){ - - /* start erase the option byte */ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - /* no security protection */ - OB_SPC = (uint16_t)temp_spc; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if - you want to protect the corresponding pages. meanwhile, sector - macro could used to set specific sector write protected. - one or more parameters can be selected which are shown as below: - \arg OB_WPx(x = 0..31): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) -{ - uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; - - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - ob_wp = (uint32_t)(~ob_wp); - temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); - temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); - temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); - temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); - - if(FMC_READY == fmc_state){ - - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - if(0xFFU != temp_wp0){ - OB_WP0 = temp_wp0; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ - OB_WP1 = temp_wp1; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ - OB_WP2 = temp_wp2; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ - OB_WP3 = temp_wp3; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection - only one parameter can be selected which is shown as below: - \arg FMC_NSPC: no security protection - \arg FMC_USPC: under security protection - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc) -{ - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - - /* start the option byte program */ - FMC_CTL0 |= FMC_CTL0_OBPG; - - OB_SPC = (uint16_t)ob_spc; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option byte - \param[in] ob_fwdgt: option byte watchdog value - \arg OB_FWDGT_SW: software free watchdog - \arg OB_FWDGT_HW: hardware free watchdog - \param[in] ob_deepsleep: option byte deepsleep reset value - \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \param[in] ob_stdby:option byte standby reset value - \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \param[in] ob_boot: specifies the option byte boot bank value - \arg OB_BOOT_B0: boot from bank0 - \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) -{ - fmc_state_enum fmc_state = FMC_READY; - uint8_t temp; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); - OB_USER = (uint16_t)temp; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program option bytes data - \param[in] address: the option bytes address to be programmed - \param[in] data: the byte to be programmed - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data) -{ - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - REG16(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC user option byte - \param[in] none - \param[out] none - \retval the FMC user option byte values -*/ -uint8_t ob_user_get(void) -{ - /* return the FMC user option byte value */ - return (uint8_t)(FMC_OBSTAT >> 2U); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> 10U); -} - -/*! - \brief get the FMC option byte write protection - \param[in] none - \param[out] none - \retval the FMC write protection option byte value -*/ -uint32_t ob_write_protection_get(void) -{ - /* return the FMC write protection option byte value */ - return FMC_WP; -} - -/*! - \brief get the FMC option byte security protection - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ob_spc_get(void) -{ - FlagStatus spc_state = RESET; - - if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ - spc_state = SET; - }else{ - spc_state = RESET; - } - return spc_state; -} - -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief check flag is set or not - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit - \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit - \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit - \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit - \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit - \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit - \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit - \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit - \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the FMC flag - \param[in] flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit - \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit - \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit - \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit - \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit - \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); -} - -/*! - \brief get FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit - \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); - }else{ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); - } - - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit - \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) -{ - FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); -} - -/*! - \brief get the FMC bank0 state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ - fmc_state = FMC_PGERR; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC bank1 state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ - fmc_state = FMC_PGERR; - } - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC bank0 is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_bank0_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC bank1 is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_bank1_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c deleted file mode 100644 index 0025c9a572..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c +++ /dev/null @@ -1,155 +0,0 @@ -/*! - \file gd32f10x_fwdgt.c - \brief FWDGT driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_fwdgt.h" - -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status){ - return ERROR; - } - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status){ - return ERROR; - } - FWDGT_RLD = RLD_RLD(reload_value); - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(FWDGT_STAT & flag){ - return SET; - } - - return RESET; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c deleted file mode 100644 index d8bdd709bb..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c +++ /dev/null @@ -1,539 +0,0 @@ -/*! - \file gd32f10x_gpio.c - \brief GPIO driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_gpio.h" - -#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ -#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ -#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ -#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ -#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ -#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ -#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ -#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ -#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch(gpio_periph){ - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOD: - /* reset GPIOD */ - rcu_periph_reset_enable(RCU_GPIODRST); - rcu_periph_reset_disable(RCU_GPIODRST); - break; - case GPIOE: - /* reset GPIOE */ - rcu_periph_reset_enable(RCU_GPIOERST); - rcu_periph_reset_disable(RCU_GPIOERST); - break; - case GPIOF: - /* reset GPIOF */ - rcu_periph_reset_enable(RCU_GPIOFRST); - rcu_periph_reset_disable(RCU_GPIOFRST); - break; - case GPIOG: - /* reset GPIOG */ - rcu_periph_reset_enable(RCU_GPIOGRST); - rcu_periph_reset_disable(RCU_GPIOGRST); - break; - default: - break; - } -} - -/*! - \brief reset alternate function I/O(AFIO) - \param[in] none - \param[out] none - \retval none -*/ -void gpio_afio_deinit(void) -{ - rcu_periph_reset_enable(RCU_AFRST); - rcu_periph_reset_disable(RCU_AFRST); -} - -/*! - \brief GPIO parameter initialization - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] mode: gpio pin mode - only one parameter can be selected which is shown as below: - \arg GPIO_MODE_AIN: analog input mode - \arg GPIO_MODE_IN_FLOATING: floating input mode - \arg GPIO_MODE_IPD: pull-down input mode - \arg GPIO_MODE_IPU: pull-up input mode - \arg GPIO_MODE_OUT_OD: GPIO output with open-drain - \arg GPIO_MODE_OUT_PP: GPIO output with push-pull - \arg GPIO_MODE_AF_OD: AFIO output with open-drain - \arg GPIO_MODE_AF_PP: AFIO output with push-pull - \param[in] speed: gpio output max speed value - only one parameter can be selected which is shown as below: - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - - \param[out] none - \retval none -*/ -void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t temp_mode = 0U; - uint32_t reg = 0U; - - /* GPIO mode configuration */ - temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); - - /* GPIO speed configuration */ - if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ - /* output mode max speed:10MHz,2MHz,50MHz */ - temp_mode |= (uint32_t)speed; - } - - /* configure the eight low port pins with GPIO_CTL0 */ - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL0(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL0 register */ - GPIO_CTL0(gpio_periph) = reg; - } - } - /* configure the eight high port pins with GPIO_CTL1 */ - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL1(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i - 8U); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i - 8U, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL1 register */ - GPIO_CTL1(gpio_periph) = reg; - } - } -} - -/*! - \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if(RESET != bit_value){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] data: specify the value to be written to the port output data register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph,uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval input status of gpio pin: SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO port input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval input status of gpio all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t)(GPIO_ISTAT(gpio_periph)); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval output status of gpio pin: SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO port output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval output status of gpio all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return ((uint16_t)GPIO_OCTL(gpio_periph)); -} - -/*! - \brief configure GPIO pin remap - \param[in] gpio_remap: select the pin to remap - \arg GPIO_SPI0_REMAP: SPI0 remapping - \arg GPIO_I2C0_REMAP: I2C0 remapping - \arg GPIO_USART0_REMAP: USART0 remapping - \arg GPIO_USART1_REMAP: USART1 remapping - \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping - \arg GPIO_USART2_FULL_REMAP: USART2 full remapping - \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping - \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping - \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping - \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping - \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping - \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping - \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping - \arg GPIO_TIMER3_REMAP: TIMER3 remapping - \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F10X_CL devices) - \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F10X_CL devices) - \arg GPIO_PD01_REMAP: PD01 remapping - \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) - \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices) - \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices) - \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST - \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled - \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled - \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL devices) - \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) - \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices) - \arg GPIO_TIMER8_REMAP: TIMER8 remapping - \arg GPIO_TIMER9_REMAP: TIMER9 remapping - \arg GPIO_TIMER10_REMAP: TIMER10 remapping - \arg GPIO_TIMER12_REMAP: TIMER12 remapping - \arg GPIO_TIMER13_REMAP: TIMER13 remapping - \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) -{ - uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; - - if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ - /* get AFIO_PCF1 regiter value */ - temp_reg = AFIO_PCF1; - }else{ - /* get AFIO_PCF0 regiter value */ - temp_reg = AFIO_PCF0; - } - - temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; - remap1 = remap & LSB_16BIT_MASK; - - /* judge pin remap type */ - if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ - temp_reg &= PCF_SWJCFG_MASK; - AFIO_PCF0 &= PCF_SWJCFG_MASK; - }else if(PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)){ - remap2 = ((uint32_t)0x03U) << temp_mask; - temp_reg &= ~remap2; - temp_reg |= ~PCF_SWJCFG_MASK; - }else{ - temp_reg &= ~(remap1 << ((remap >> 0x15U)*0x10U)); - temp_reg |= ~PCF_SWJCFG_MASK; - } - - /* set pin remap value */ - if(DISABLE != newvalue){ - temp_reg |= (remap1 << ((remap >> 0x15U)*0x10U)); - } - - if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ - /* set AFIO_PCF1 regiter value */ - AFIO_PCF1 = temp_reg; - }else{ - /* set AFIO_PCF0 regiter value */ - AFIO_PCF0 = temp_reg; - } -} - -/*! - \brief select GPIO pin exti sources - \param[in] gpio_outputport: gpio event output port - \arg GPIO_PORT_SOURCE_GPIOA: output port source A - \arg GPIO_PORT_SOURCE_GPIOB: output port source B - \arg GPIO_PORT_SOURCE_GPIOC: output port source C - \arg GPIO_PORT_SOURCE_GPIOD: output port source D - \arg GPIO_PORT_SOURCE_GPIOE: output port source E - \arg GPIO_PORT_SOURCE_GPIOF: output port source F - \arg GPIO_PORT_SOURCE_GPIOG: output port source G - \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) -{ - uint32_t source = 0U; - source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); - - /* select EXTI sources */ - if(GPIO_PIN_SOURCE_4 > output_pin){ - /* select EXTI0/EXTI1/EXTI2/EXTI3 */ - AFIO_EXTISS0 &= ~source; - AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else if(GPIO_PIN_SOURCE_8 > output_pin){ - /* select EXTI4/EXTI5/EXTI6/EXTI7 */ - AFIO_EXTISS1 &= ~source; - AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else if(GPIO_PIN_SOURCE_12 > output_pin){ - /* select EXTI8/EXTI9/EXTI10/EXTI11 */ - AFIO_EXTISS2 &= ~source; - AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else{ - /* select EXTI12/EXTI13/EXTI14/EXTI15 */ - AFIO_EXTISS3 &= ~source; - AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } -} - -/*! - \brief configure GPIO pin event output - \param[in] output_port: gpio event output port - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PORT_GPIOA: event output port A - \arg GPIO_EVENT_PORT_GPIOB: event output port B - \arg GPIO_EVENT_PORT_GPIOC: event output port C - \arg GPIO_EVENT_PORT_GPIOD: event output port D - \arg GPIO_EVENT_PORT_GPIOE: event output port E - \arg GPIO_EVENT_PORT_GPIOE: event output port F - \arg GPIO_EVENT_PORT_GPIOE: event output port G - \param[in] output_pin: - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PIN_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) -{ - uint32_t reg = 0U; - reg = AFIO_EC; - - /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ - reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); - - reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); - reg |= (uint32_t)output_pin; - - AFIO_EC = reg; -} - -/*! - \brief enable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_enable(void) -{ - AFIO_EC |= AFIO_EC_EOE; -} - -/*! - \brief disable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_disable(void) -{ - AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); -} - -/*! - \brief lock GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -#ifdef GD32F10X_CL -/*! - \brief select ethernet MII or RMII PHY - \param[in] gpio_enetsel: ethernet MII or RMII PHY selection - \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY - \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY - \param[out] none - \retval none -*/ -void gpio_ethernet_phy_select(uint32_t gpio_enetsel) -{ - /* clear AFIO_PCF0_ENET_PHY_SEL bit */ - AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); - - /* select MII or RMII PHY */ - AFIO_PCF0 |= (uint32_t)gpio_enetsel; -} -#endif diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c deleted file mode 100644 index fa1ae96d23..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c +++ /dev/null @@ -1,707 +0,0 @@ -/*! - \file gd32f10x_i2c.c - \brief I2C driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch(i2c_periph){ - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - \param[in] dutycyc: duty cycle in fast mode - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) = I2CCLK_MAX; - }else if(risetime <= I2CCLK_MIN){ - I2C_RT(i2c_periph) = I2CCLK_MIN; - }else{ - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - }else if(400000U >= clkspeed){ - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if(0U == (clkc & I2C_CKCFG_CLKC)){ - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - }else{ - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief configure I2C POAP position - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ - addr = addr & I2C_TRANSMITTER; - }else{ - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief dual-address mode switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dualaddr: - only one parameter can be selected which is shown as below: - \arg I2C_DUADEN_DISABLE: disable dual-address mode - \arg I2C_DUADEN_ENABLE: enable dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) -{ - if(I2C_DUADEN_ENABLE == dualaddr){ - I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; - }else{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); - } -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none -*/ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_DISSTRC); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C PEC calculation on or off - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none -*/ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>STAT1_PECV_OFFSET); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable or disable I2C ARP protocol in SMBus switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] arpstate: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(I2C_FLAG_ADDSEND == flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ - intenable = 1U; - }else{ - intenable = 0U; - } - } - if((0U != flagstatus) && (0U != intenable)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - if(I2C_INT_FLAG_ADDSEND == int_flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c deleted file mode 100644 index 1a96627b3a..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c +++ /dev/null @@ -1,187 +0,0 @@ -/*! - \file gd32f10x_misc.c - \brief MISC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_misc.h" - -/*! - \brief set the priority group - \param[in] nvic_prigroup: the NVIC priority group - \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority - \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority - \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority - \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority - \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority - \param[out] none - \retval none -*/ -void nvic_priority_group_set(uint32_t nvic_prigroup) -{ - /* set the priority group value */ - SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; -} - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set - \param[in] nvic_irq_sub_priority: the subpriority needed to set - \param[out] none - \retval none -*/ -void nvic_irq_enable(uint8_t nvic_irq, - uint8_t nvic_irq_pre_priority, - uint8_t nvic_irq_sub_priority) -{ - uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; - - /* use the priority group value to get the temp_pre and the temp_sub */ - switch ((SCB->AIRCR) & (uint32_t)0x700U) { - case NVIC_PRIGROUP_PRE0_SUB4: - temp_pre = 0U; - temp_sub = 0x4U; - break; - case NVIC_PRIGROUP_PRE1_SUB3: - temp_pre = 1U; - temp_sub = 0x3U; - break; - case NVIC_PRIGROUP_PRE2_SUB2: - temp_pre = 2U; - temp_sub = 0x2U; - break; - case NVIC_PRIGROUP_PRE3_SUB1: - temp_pre = 3U; - temp_sub = 0x1U; - break; - case NVIC_PRIGROUP_PRE4_SUB0: - temp_pre = 4U; - temp_sub = 0x0U; - break; - default: - nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre = 2U; - temp_sub = 0x2U; - break; - } - - /* get the temp_priority to fill the NVIC->IP register */ - temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); - temp_priority = temp_priority << 0x04U; - NVIC->IP[nvic_irq] = (uint8_t)temp_priority; - - /* enable the selected IRQ */ - NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(uint8_t nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - \arg NVIC_VECTTAB_RAM: RAM base address - \are NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c deleted file mode 100644 index 33052db8d1..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c +++ /dev/null @@ -1,265 +0,0 @@ -/*! - \file gd32f10x_pmu.c - \brief PMU driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_pmu.h" - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - only one parameter can be selected which is shown as below: - \arg PMU_LVDT_0: voltage threshold is 2.2V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.5V - \arg PMU_LVDT_4: voltage threshold is 2.6V - \arg PMU_LVDT_5: voltage threshold is 2.7V - \arg PMU_LVDT_6: voltage threshold is 2.8V - \arg PMU_LVDT_7: voltage threshold is 2.9V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo: - only one parameter can be selected which is shown as below: - \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) -{ - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ - __WFI(); - }else{ - __SEV(); - __WFE(); - __WFE(); - } - /* reset sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief enable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(void) -{ - PMU_CS |= PMU_CS_WUPEN; -} - -/*! - \brief disable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(void) -{ - PMU_CS &= ~PMU_CS_WUPEN; -} - -/*! - \brief enable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief get flag state - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \param[out] none - \retval FlagStatus SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - if(PMU_CS & flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag bit - \param[in] flag_reset: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag_reset) -{ - switch(flag_reset){ - case PMU_FLAG_RESET_WAKEUP: - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - break; - case PMU_FLAG_RESET_STANDBY: - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - break; - default : - break; - } -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c deleted file mode 100644 index 579831ccaf..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c +++ /dev/null @@ -1,1193 +0,0 @@ -/*! - \file gd32f10x_rcu.c - \brief RCU driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_rcu.h" - -/* define clock source */ -#define SEL_IRC8M ((uint16_t)0U) -#define SEL_HXTAL ((uint16_t)1U) -#define SEL_PLL ((uint16_t)2U) - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - rcu_osci_stab_wait(RCU_IRC8M); - - /* reset CFG0 register */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | - RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2); -#elif defined(GD32F10X_CL) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4); -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - RCU_CTL &= ~RCU_CTL_HXTALBPS; -#ifdef GD32F10X_CL - RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); -#endif /* GD32F10X_CL */ - - /* reset INT and CFG1 register */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_INT = 0x009f0000U; -#elif defined(GD32F10X_CL) - RCU_INT = 0x00ff0000U; - RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | - RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL); -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF : alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF: alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP domain - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP domain reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - reg &= ~RCU_CFG0_SCS; - RCU_CFG0 = (reg | ck_sys); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source - \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source - \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the AHBPSC bits and set according to ck_ahb */ - reg &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (reg | ck_ahb); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB1PSC and set according to ck_apb1 */ - reg &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (reg | ck_apb1); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB2PSC and set according to ck_apb2 */ - reg &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (reg | ck_apb2); -} - -/*! - \brief configure the CK_OUT0 clock source - \param[in] ckout0_src: CK_OUT0 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT0SRC_NONE: no clock selected - \arg RCU_CKOUT0SRC_CKSYS: system clock selected - \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected - \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected - \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected - \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected - \arg RCU_CKOUT0SRC_EXT1: EXT1 selected - \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected - \param[out] none - \retval none -*/ -void rcu_ckout0_config(uint32_t ckout0_src) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the CKOUT0SRC, set according to ckout0_src */ - reg &= ~RCU_CFG0_CKOUT0SEL; - RCU_CFG0 = (reg | ckout0_src); -} - -/*! - \brief configure the main PLL clock - \param[in] pll_src: PLL clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL - \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL_MULx (XD series x = 2..32, CL series x = 2..14, 6.5, 16..32) - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - - /* PLL clock source and multiplication factor configuration */ - reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - reg |= (pll_src | pll_mul); - - RCU_CFG0 = reg; -} - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -/*! - \brief configure the PREDV0 division factor - \param[in] predv0_div: PREDV0 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0_DIVx, x = 1,2 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - /* reset PREDV0 bit */ - reg &= ~RCU_CFG0_PREDV0; - if(RCU_PREDV0_DIV2 == predv0_div){ - /* set the PREDV0 bit */ - reg |= RCU_CFG0_PREDV0; - } - - RCU_CFG0 = reg; -} -#elif defined(GD32F10X_CL) -/*! - \brief configure the PREDV0 division factor and clock source - \param[in] predv0_source: PREDV0 input clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock - \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock - \param[in] predv0_div: PREDV0 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset PREDV0SEL and PREDV0 bits */ - reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); - /* set the PREDV0SEL and PREDV0 division factor */ - reg |= (predv0_source | predv0_div); - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PREDV1 division factor - \param[in] predv1_div: PREDV1 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV1_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv1_config(uint32_t predv1_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset the PREDV1 bits */ - reg &= ~RCU_CFG1_PREDV1; - /* set the PREDV1 division factor */ - reg |= predv1_div; - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PLL1 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL1_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll1_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL1MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the PLL2 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL2_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll2_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL2MF; - RCU_CFG1 |= pll_mul; -} -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/*! - \brief configure the ADC prescaler factor - \param[in] adc_psc: ADC prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 - \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 - \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 - \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 - \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 - \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(uint32_t adc_psc) -{ - uint32_t reg0; - - /* reset the ADCPSC bits */ - reg0 = RCU_CFG0; - reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); - - /* set the ADC prescaler factor */ - switch(adc_psc){ - case RCU_CKADC_CKAPB2_DIV2: - case RCU_CKADC_CKAPB2_DIV4: - case RCU_CKADC_CKAPB2_DIV6: - case RCU_CKADC_CKAPB2_DIV8: - reg0 |= (adc_psc << 14); - break; - - case RCU_CKADC_CKAPB2_DIV12: - case RCU_CKADC_CKAPB2_DIV16: - adc_psc &= ~BIT(2); - reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); - break; - - default: - break; - } - - /* set the register */ - RCU_CFG0 = reg0; -} - -/*! - \brief configure the USBD/USBFS prescaler factor - \param[in] usb_psc: USB prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 - \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 - \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 - \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 - \param[out] none - \retval none -*/ -void rcu_usb_clock_config(uint32_t usb_psc) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* configure the USBD/USBFS prescaler factor */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - reg &= ~RCU_CFG0_USBDPSC; -#elif defined(GD32F10X_CL) - reg &= ~RCU_CFG0_USBFSPSC; -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - RCU_CFG0 = (reg | usb_psc); -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - uint32_t reg; - - reg = RCU_BDCTL; - /* reset the RTCSRC bits and set according to rtc_clock_source */ - reg &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL = (reg | rtc_clock_source); -} - -#ifdef GD32F10X_CL -/*! - \brief configure the I2S1 clock source selection - \param[in] i2s_clock_source: I2S1 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock - \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock - \param[out] none - \retval none -*/ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S1SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S1SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief configure the I2S2 clock source selection - \param[in] i2s_clock_source: I2S2 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock - \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock - \param[out] none - \retval none -*/ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S2SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S2SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} -#endif /* GD32F10X_CL */ - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) - \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - - switch(osci){ - /* wait HXTAL stable */ - case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ - reval = SUCCESS; - } - break; - -#ifdef GD32F10X_CL - /* wait PLL1 stable */ - case RCU_PLL1_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ - reval = SUCCESS; - } - break; - /* wait PLL2 stable */ - case RCU_PLL2_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ - reval = SUCCESS; - } - break; -#endif /* GD32F10X_CL */ - - default: - break; - } - - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* enable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg | RCU_CTL_HXTALBPS); - break; - /* enable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F10X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F10X_CL */ - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* disable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); - break; - /* disable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F10X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F10X_CL */ - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) -{ - uint32_t reg; - - reg = RCU_CTL; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - reg &= ~RCU_CTL_IRC8MADJ; - RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws, ck_freq = 0U; - uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp; -#ifdef GD32F10X_CL - uint32_t predv0, predv1, pll1mf; -#endif /* GD32F10X_CL */ - - /* exponent of AHB, APB1 and APB2 clock divider */ - uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if(RCU_PLLSRC_HXTAL == pllsel) { - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); - /* PREDV0 input source clock divided by 2 */ - if(RCU_CFG0_PREDV0 == predv0sel){ - ck_src = HXTAL_VALUE/2U; - } -#elif defined(GD32F10X_CL) - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ - predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; -#endif /* GD32F10X_HD and GD32F10X_XD */ - }else{ - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE/2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ - pllmf |= 0x10U; - } - if(pllmf < 15U){ - pllmf += 2U; - }else{ - pllmf += 1U; - } - - cksys_freq = ck_src * pllmf; - - #ifdef GD32F10X_CL - if(15U == pllmf){ - /* PLL source clock multiply by 6.5 */ - cksys_freq = ck_src * 6U + ck_src / 2U; - } - #endif /* GD32F10X_CL */ - - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock){ - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c deleted file mode 100644 index 27fe2cfe70..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c +++ /dev/null @@ -1,277 +0,0 @@ -/*! - \file gd32f10x_rtc.c - \brief RTC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_rtc.h" - -/* RTC register high / low bits mask */ -#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ -#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ - -/* RTC register high bits offset */ -#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) - -/*! - \brief enter RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_enter(void) -{ - RTC_CTL |= RTC_CTL_CMF; -} - -/*! - \brief exit RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_exit(void) -{ - RTC_CTL &= ~RTC_CTL_CMF; -} - -/*! - \brief set RTC counter value - \param[in] cnt: RTC counter value - \param[out] none - \retval none -*/ -void rtc_counter_set(uint32_t cnt) -{ - rtc_configuration_mode_enter(); - /* set the RTC counter high bits */ - RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); - /* set the RTC counter low bits */ - RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief set RTC prescaler value - \param[in] psc: RTC prescaler value - \param[out] none - \retval none -*/ -void rtc_prescaler_set(uint32_t psc) -{ - rtc_configuration_mode_enter(); - /* set the RTC prescaler high bits */ - RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); - /* set the RTC prescaler low bits */ - RTC_PSCL = (psc & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief wait RTC last write operation finished flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_lwoff_wait(void) -{ - /* loop until LWOFF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ - } -} - -/*! - \brief wait RTC registers synchronized flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_register_sync_wait(void) -{ - /* clear RSYNF flag */ - RTC_CTL &= ~RTC_CTL_RSYNF; - /* loop until RSYNF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ - } -} - -/*! - \brief set RTC alarm value - \param[in] alarm: RTC alarm value - \param[out] none - \retval none -*/ -void rtc_alarm_config(uint32_t alarm) -{ - rtc_configuration_mode_enter(); - /* set the alarm high bits */ - RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); - /* set the alarm low bits */ - RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief get RTC counter value - \param[in] none - \param[out] none - \retval RTC counter value -*/ -uint32_t rtc_counter_get(void) -{ - uint32_t temp = 0x0U; - - temp = RTC_CNTL; - temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); - return temp; -} - -/*! - \brief get RTC divider value - \param[in] none - \param[out] none - \retval RTC divider value -*/ -uint32_t rtc_divider_get(void) -{ - uint32_t temp = 0x00U; - - temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); - temp |= RTC_DIVL; - return temp; -} - -/*! - \brief get RTC flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \arg RTC_FLAG_LWOF: last write operation finished flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear RTC flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - /* clear RTC flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief get RTC interrupt flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_interrupt_flag_get(uint32_t flag) -{ - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear RTC interrupt flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval none -*/ -void rtc_interrupt_flag_clear(uint32_t flag) -{ - /* clear RTC interrupt flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief enable RTC interrupt - \param[in] interrupt: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - RTC_INTEN |= interrupt; -} - -/*! - \brief disable RTC interrupt - \param[in] interrupt: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - RTC_INTEN &= ~interrupt; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c deleted file mode 100644 index d609f282ed..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c +++ /dev/null @@ -1,814 +0,0 @@ -/*! - \file gd32f10x_sdio.c - \brief SDIO driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_sdio.h" - -#define DEFAULT_RESET_VALUE 0x00000000U - -/*! - \brief deinitialize the SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_deinit(void) -{ - SDIO_PWRCTL = DEFAULT_RESET_VALUE; - SDIO_CLKCTL = DEFAULT_RESET_VALUE; - SDIO_CMDAGMT = DEFAULT_RESET_VALUE; - SDIO_CMDCTL = DEFAULT_RESET_VALUE; - SDIO_DATATO = DEFAULT_RESET_VALUE; - SDIO_DATALEN = DEFAULT_RESET_VALUE; - SDIO_DATACTL = DEFAULT_RESET_VALUE; - SDIO_INTC = DEFAULT_RESET_VALUE; - SDIO_INTEN = DEFAULT_RESET_VALUE; -} - -/*! - \brief configure the SDIO clock - \param[in] clock_edge: SDIO_CLK clock edge - only one parameter can be selected which is shown as below: - \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK - \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK - \param[in] clock_bypass: clock bypass - only one parameter can be selected which is shown as below: - \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass - \arg SDIO_CLOCKBYPASS_DISABLE: no bypass - \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving - only one parameter can be selected which is shown as below: - \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle - \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on - \param[in] clock_division: clock division, less than 256 - \param[out] none - \retval none -*/ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) -{ - uint32_t clock_config = 0U; - clock_config = SDIO_CLKCTL; - /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ - clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV); - - /* configure the SDIO_CLKCTL according to the parameters */ - clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); - SDIO_CLKCTL = clock_config; -} - -/*! - \brief enable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief disable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief set different SDIO card bus mode - \param[in] bus_mode: SDIO card bus mode - only one parameter can be selected which is shown as below: - \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode - \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode - \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode - \param[out] none - \retval none -*/ -void sdio_bus_mode_set(uint32_t bus_mode) -{ - /* reset the SDIO card bus mode bits and set according to bus_mode */ - SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; - SDIO_CLKCTL |= bus_mode; -} - -/*! - \brief set the SDIO power state - \param[in] power_state: SDIO power state - only one parameter can be selected which is shown as below: - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off - \param[out] none - \retval none -*/ -void sdio_power_state_set(uint32_t power_state) -{ - SDIO_PWRCTL = power_state; -} - -/*! - \brief get the SDIO power state - \param[in] none - \param[out] none - \retval SDIO power state - only one parameter can be selected which is shown as below: - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off -*/ -uint32_t sdio_power_state_get(void) -{ - return SDIO_PWRCTL; -} - -/*! - \brief enable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; -} - -/*! - \brief disable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; -} - -/*! - \brief configure the command and response - \param[in] cmd_index: command index, refer to the related specifications - \param[in] cmd_argument: command argument, refer to the related specifications - \param[in] response_type: response type - only one parameter can be selected which is shown as below: - \arg SDIO_RESPONSETYPE_NO: no response - \arg SDIO_RESPONSETYPE_SHORT: short response - \arg SDIO_RESPONSETYPE_LONG: long response - \param[out] none - \retval none -*/ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) -{ - uint32_t cmd_config = 0U; - /* reset the command index, command argument and response type */ - SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; - SDIO_CMDAGMT = cmd_argument; - cmd_config = SDIO_CMDCTL; - cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); - /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ - cmd_config |= (cmd_index | response_type); - SDIO_CMDCTL = cmd_config; -} - -/*! - \brief set the command state machine wait type - \param[in] wait_type: wait type - only one parameter can be selected which is shown as below: - \arg SDIO_WAITTYPE_NO: not wait interrupt - \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt - \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer - \param[out] none - \retval none -*/ -void sdio_wait_type_set(uint32_t wait_type) -{ - /* reset INTWAIT and WAITDEND */ - SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); - /* set the wait type according to wait_type */ - SDIO_CMDCTL |= wait_type; -} - -/*! - \brief enable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; -} - -/*! - \brief disable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; -} - -/*! - \brief get the last response command index - \param[in] none - \param[out] none - \retval last response command index -*/ -uint8_t sdio_command_index_get(void) -{ - return (uint8_t)SDIO_RSPCMDIDX; -} - -/*! - \brief get the response for the last received command - \param[in] responsex: SDIO response - only one parameter can be selected which is shown as below: - \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] - \arg SDIO_RESPONSE1: card response[95:64] - \arg SDIO_RESPONSE2: card response[63:32] - \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 - \param[out] none - \retval response for the last received command -*/ -uint32_t sdio_response_get(uint32_t responsex) -{ - uint32_t resp_content = 0U; - switch(responsex){ - case SDIO_RESPONSE0: - resp_content = SDIO_RESP0; - break; - case SDIO_RESPONSE1: - resp_content = SDIO_RESP1; - break; - case SDIO_RESPONSE2: - resp_content = SDIO_RESP2; - break; - case SDIO_RESPONSE3: - resp_content = SDIO_RESP3; - break; - default: - break; - } - return resp_content; -} - -/*! - \brief configure the data timeout, data length and data block size - \param[in] data_timeout: data timeout period in card bus clock periods - \param[in] data_length: number of data bytes to be transferred - \param[in] data_blocksize: size of data block for block transfer - only one parameter can be selected which is shown as below: - \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte - \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes - \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes - \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes - \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes - \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes - \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes - \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes - \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes - \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes - \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes - \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes - \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes - \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes - \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes - \param[out] none - \retval none -*/ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) -{ - /* reset data timeout, data length and data block size */ - SDIO_DATATO &= ~SDIO_DATATO_DATATO; - SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; - SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; - /* configure the related parameters of data */ - SDIO_DATATO = data_timeout; - SDIO_DATALEN = data_length; - SDIO_DATACTL |= data_blocksize; -} - -/*! - \brief configure the data transfer mode and direction - \param[in] transfer_mode: mode of data transfer - only one parameter can be selected which is shown as below: - \arg SDIO_TRANSMODE_BLOCK: block transfer - \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer - \param[in] transfer_direction: data transfer direction, read or write - only one parameter can be selected which is shown as below: - \arg SDIO_TRANSDIRECTION_TOCARD: write data to card - \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card - \param[out] none - \retval none -*/ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) -{ - uint32_t data_trans = 0U; - /* reset the data transfer mode, transfer direction and set according to the parameters */ - data_trans = SDIO_DATACTL; - data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); - data_trans |= (transfer_mode | transfer_direction); - SDIO_DATACTL = data_trans; -} - -/*! - \brief enable the DSM(data state machine) for data transfer - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DATAEN; -} - -/*! - \brief disable the DSM(data state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; -} - -/*! - \brief write data(one word) to the transmit FIFO - \param[in] data: 32-bit data write to card - \param[out] none - \retval none -*/ -void sdio_data_write(uint32_t data) -{ - SDIO_FIFO = data; -} - -/*! - \brief read data(one word) from the receive FIFO - \param[in] none - \param[out] none - \retval received data -*/ -uint32_t sdio_data_read(void) -{ - return SDIO_FIFO; -} - -/*! - \brief get the number of remaining data bytes to be transferred to card - \param[in] none - \param[out] none - \retval number of remaining data bytes to be transferred -*/ -uint32_t sdio_data_counter_get(void) -{ - return SDIO_DATACNT; -} - -/*! - \brief get the number of words remaining to be written or read from FIFO - \param[in] none - \param[out] none - \retval remaining number of words -*/ -uint32_t sdio_fifo_counter_get(void) -{ - return SDIO_FIFOCNT; -} - -/*! - \brief enable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DMAEN; -} - -/*! - \brief disable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; -} - -/*! - \brief get the flags state of SDIO - \param[in] flag: flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_CMDRUN: command transmission in progress flag - \arg SDIO_FLAG_TXRUN: data transmission in progress flag - \arg SDIO_FLAG_RXRUN: data reception in progress flag - \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO - \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO - \arg SDIO_FLAG_TFF: transmit FIFO is full flag - \arg SDIO_FLAG_RFF: receive FIFO is full flag - \arg SDIO_FLAG_TFE: transmit FIFO is empty flag - \arg SDIO_FLAG_RFE: receive FIFO is empty flag - \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag - \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_flag_get(uint32_t flag) -{ - FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & flag)){ - temp_flag = SET; - } - return temp_flag; -} - -/*! - \brief clear the pending flags of SDIO - \param[in] flag: flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_flag_clear(uint32_t flag) -{ - SDIO_INTC = flag; -} - -/*! - \brief enable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_enable(uint32_t int_flag) -{ - SDIO_INTEN |= int_flag; -} - -/*! - \brief disable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_disable(uint32_t int_flag) -{ - SDIO_INTEN &= ~int_flag; -} - -/*! - \brief get the interrupt flags state of SDIO - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt - \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt - \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt - \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt - \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt - \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt - \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) -{ - uint32_t state = 0U; - state = SDIO_STAT; - if(state & int_flag){ - state = SDIO_INTEN; - /* check whether the corresponding bit in SDIO_INTEN is set or not */ - if(state & int_flag){ - return SET; - } - } - return RESET; -} - -/*! - \brief clear the interrupt pending flags of SDIO - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag - \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_interrupt_flag_clear(uint32_t int_flag) -{ - SDIO_INTC = int_flag; -} - -/*! - \brief enable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWEN; -} - -/*! - \brief disable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; -} - -/*! - \brief enable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; -} - -/*! - \brief disable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; -} - -/*! - \brief set the read wait type(SD I/O only) - \param[in] readwait_type: SD I/O read wait type - only one parameter can be selected which is shown as below: - \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK - \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] - \param[out] none - \retval none -*/ -void sdio_readwait_type_set(uint32_t readwait_type) -{ - if(SDIO_READWAITTYPE_CLK == readwait_type){ - SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; - }else{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; - } -} - -/*! - \brief enable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_IOEN; -} - -/*! - \brief disable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; -} - -/*! - \brief enable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief disable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief enable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; -} - -/*! - \brief disable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; -} - -/*! - \brief enable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_enable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; -} - -/*! - \brief disable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_disable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; -} - -/*! - \brief enable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; -} - -/*! - \brief disable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c deleted file mode 100644 index c0fb893ccc..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c +++ /dev/null @@ -1,718 +0,0 @@ -/*! - \file gd32f10x_spi.c - \brief SPI driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_spi.h" - -/* SPI/I2S parameter initialization mask */ -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -/* I2S clock source selection, multiplication and division mask */ -#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ -#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ -#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ -#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ - -/* default value and offset */ -#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ -#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ -#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph){ - case SPI0: - /* reset SPI0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 and I2S1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - case SPI2: - /* reset SPI2 and I2S2 */ - rcu_periph_reset_enable(RCU_SPI2RST); - rcu_periph_reset_disable(RCU_SPI2RST); - break; - default : - break; - } -} - -/*! - \brief initialize the parameters of SPI struct with the default values - \param[in] spi_struct: SPI parameter stuct - \param[out] none - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct* spi_struct) -{ - /* set the SPI struct with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; -} - -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval none -*/ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ - uint32_t reg = 0U; - reg = SPI_CTL0(spi_periph); - reg &= SPI_INIT_MASK; - - /* select SPI as master or slave */ - reg |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg |= spi_struct->trans_mode; - /* select SPI frame size */ - reg |= spi_struct->frame_size; - /* select SPI NSS use hardware or software */ - reg |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg |= spi_struct->endian; - /* select SPI polarity and phase */ - reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg |= spi_struct->prescale; - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg; - - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPIx(x=1,2) - \param[in] mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg = 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPIx(x=1,2) - \param[in] audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; - -#ifdef GD32F10X_CL - /* get the I2S clock source */ - if(SPI1 == ((uint32_t)spi_periph)){ - /* I2S1 clock source selection */ - clks = I2S1_CLOCK_SEL; - }else{ - /* I2S2 clock source selection */ - clks = I2S2_CLOCK_SEL; - } - - if(0U != (RCU_CFG1 & clks)){ - /* get RCU PLL2 clock multiplication factor */ - clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); - - if((clks > 5U) && (clks < 15U)){ - /* multiplier is between 8 and 14 */ - clks += 2U; - }else{ - if(15U == clks){ - /* multiplier is 20 */ - clks = 20U; - } - } - - /* get the PREDV1 value */ - i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); - /* calculate I2S clock based on PLL2 and PREDV1 */ - i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); - }else{ - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - } -#else - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); -#endif /* GD32F10X_CL */ - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout){ - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)){ - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \param[out] none - \retval none -*/ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* configure SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= (uint32_t)frame_format; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - SPI_DATA(spi_periph) = (uint32_t)data; -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - return ((uint16_t)SPI_DATA(spi_periph)); -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) -{ - if(SPI_CRC_TX == crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt flag status - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - /*get SPI/I2S interrupt flag status */ - if((0U != reg1) && (0U != reg2)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] flag: SPI/I2S flag status - one or more parameters can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(RESET != (SPI_STAT(spi_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c deleted file mode 100644 index 236eedf9be..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c +++ /dev/null @@ -1,2004 +0,0 @@ -/*! - \file gd32f10x_timer.c - \brief TIMER driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_timer.h" - -/* TIMER init parameter mask */ -#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ -#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ -#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ - -/*! - \brief deinit a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph){ - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER1: - /* reset TIMER1 */ - rcu_periph_reset_enable(RCU_TIMER1RST); - rcu_periph_reset_disable(RCU_TIMER1RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER3: - /* reset TIMER3 */ - rcu_periph_reset_enable(RCU_TIMER3RST); - rcu_periph_reset_disable(RCU_TIMER3RST); - break; - case TIMER4: - /* reset TIMER4 */ - rcu_periph_reset_enable(RCU_TIMER4RST); - rcu_periph_reset_disable(RCU_TIMER4RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER6: - /* reset TIMER6 */ - rcu_periph_reset_enable(RCU_TIMER6RST); - rcu_periph_reset_disable(RCU_TIMER6RST); - break; - case TIMER7: - /* reset TIMER7 */ - rcu_periph_reset_enable(RCU_TIMER7RST); - rcu_periph_reset_disable(RCU_TIMER7RST); - break; -#ifdef GD32F10X_XD - case TIMER8: - /* reset TIMER8 */ - rcu_periph_reset_enable(RCU_TIMER8RST); - rcu_periph_reset_disable(RCU_TIMER8RST); - break; - case TIMER9: - /* reset TIMER9 */ - rcu_periph_reset_enable(RCU_TIMER9RST); - rcu_periph_reset_disable(RCU_TIMER9RST); - break; - case TIMER10: - /* reset TIMER10 */ - rcu_periph_reset_enable(RCU_TIMER10RST); - rcu_periph_reset_disable(RCU_TIMER10RST); - break; - case TIMER11: - /* reset TIMER11 */ - rcu_periph_reset_enable(RCU_TIMER11RST); - rcu_periph_reset_disable(RCU_TIMER11RST); - break; - case TIMER12: - /* reset TIMER12 */ - rcu_periph_reset_enable(RCU_TIMER12RST); - rcu_periph_reset_disable(RCU_TIMER12RST); - break; - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; -#endif /* GD32F10X_XD */ - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct* initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock,0~65535 - alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP, - TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN - period: counter auto reload value,0~65535 - clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || - (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || - (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){ - TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); - } - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] prescaler: prescaler value - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] repetition: the counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] autoreload: the counter auto-reload value - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] counter: the counter value - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0..8,11) - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, - or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint32_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: timer DMA source enable - only one parameter can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: timer DMA source disable - only one parameter can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA disable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request disable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA disable,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: please refer to the following parameters - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: please refer to the following parameters - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | - ((uint32_t)(breakpara->ideloffstate)) | - ((uint32_t)(breakpara->deadtime)) | - ((uint32_t)(breakpara->breakpolarity)) | - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode)) | - ((uint32_t)(breakpara->breakstate))) ; -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief enable or disable TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl){ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U); - } - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U); - } - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U); - } - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] pulse: channel output pulse value - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \arg TIMER_CH_3: TIMER channel3 - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, - TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) - icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, - TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, - TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel){ - case TIMER_CH_0: - /* read TIMER channel 0 capture compare register value */ - count_value = TIMER_CH0CV(timer_periph); - break; - case TIMER_CH_1: - /* read TIMER channel 1 capture compare register value */ - count_value = TIMER_CH1CV(timer_periph); - break; - case TIMER_CH_2: - /* read TIMER channel 2 capture compare register value */ - count_value = TIMER_CH2CV(timer_periph); - break; - case TIMER_CH_3: - /* read TIMER channel 3 capture compare register value */ - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ - icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ - icpolarity = TIMER_IC_POLARITY_RISING; - } - /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ - icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel){ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: please refer to the following parameters - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0..7) - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) -{ - /* configure the quadrature decoder mode */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - /* configure input capture selection */ - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - /* configure channel input capture polarity */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph,intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] expolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active high or rising edge active - \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source disable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)flag); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c deleted file mode 100644 index 3e6c97ee6f..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c +++ /dev/null @@ -1,767 +0,0 @@ -/*! - \file gd32f10x_usart.c - \brief USART driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.1, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_usart.h" - -/*! - \brief reset USART/UART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph){ - case USART0: - /* reset USART0 */ - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - /* reset USART1 */ - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - case USART2: - /* reset USART2 */ - rcu_periph_reset_enable(RCU_USART2RST); - rcu_periph_reset_disable(RCU_USART2RST); - break; - case UART3: - /* reset UART3 */ - rcu_periph_reset_enable(RCU_UART3RST); - rcu_periph_reset_disable(RCU_UART3RST); - break; - case UART4: - /* reset UART4 */ - rcu_periph_reset_enable(RCU_UART4RST); - rcu_periph_reset_disable(RCU_UART4RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ - case USART0: - /* get USART0 clock */ - uclk=rcu_clock_freq_get(CK_APB2); - break; - case USART1: - /* get USART1 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case USART2: - /* get USART2 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART3: - /* get UART3 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART4: - /* get UART4 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; - intdiv = udiv & (0x0000fff0U); - fradiv = udiv & (0x0000000fU); - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] paritycfg: configure USART parity - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg ; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - /* configure USART stop bits */ - USART_CTL1(usart_periph) |= stblen; -} -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_TEN; - ctl |= txconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_REN; - ctl |= rxconfig; - /* configure receiver mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_DATA(usart_periph) = USART_DATA_DATA & data; -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); -} - -/*! - \brief configure the address of the USART in wake up by address match mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] addr: address of USART/UART - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); -} - -/*! - \brief receiver in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_RWU; -} - -/*! - \brief receiver in active mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wmethod: two methods be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mask - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief configure lin break frame length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] lblen: lin break frame length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits - \arg USART_LBLEN_11B: 11 bits - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); -} - -/*! - \brief send break frame - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_send_break(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; -} - -/*! - \brief enable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] clen: CK length - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame - \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] gaut: guard time value - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) -{ - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] psc: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) -{ - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] irlp: IrDA low-power or normal - only one parameter can be selected which is shown as below: - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] hardwareflow: enable or disable RTS - only one parameter can be selected which is shown as below: - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_RTSEN; - ctl |= rtsconfig; - /* configure RTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] hardwareflow: enable or disable CTS - only one parameter can be selected which is shown as below: - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_CTSEN; - ctl |= ctsconfig; - /* configure CTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for reception - only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENR; - ctl |= dmacmd; - /* configure DMA reception */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for transmission - only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENT; - ctl |= dmacmd; - /* configure DMA transmission */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief get flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag - \arg USART_FLAG_TBE: transmit data buffer empty - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_IDLEF: IDLE frame detected flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_PERR: parity error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_PERR: parity error interrupt and flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag - \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag - \param[out] none - \retval FlagStatus -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if(flagstatus && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART interrupt flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART interrupt flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_CTS: CTS change flag - \arg USART_INT_FLAG_LBD: LIN break detected flag - \arg USART_INT_FLAG_TC: transmission complete - \arg USART_INT_FLAG_RBNE: read data buffer not empty - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) -{ - USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c b/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c deleted file mode 100644 index 633b50423b..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c +++ /dev/null @@ -1,150 +0,0 @@ -/*! - \file gd32f10x_wwdgt.c - \brief WWDGT driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_wwdgt.h" - -/* write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -/* write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00 - 0x7F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F - \param[in] window: 0x00 - 0x7F - \param[in] prescaler: wwdgt prescaler value - only one parameter can be selected which is shown as below: - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - uint32_t reg_cfg = 0U, reg_ctl = 0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); - reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= CFG_WIN(window); - reg_cfg |= prescaler; - reg_ctl |= CTL_CNT(counter); - - WWDGT_CTL = reg_ctl; - WWDGT_CFG = reg_cfg; -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if(WWDGT_STAT & WWDGT_STAT_EWIF){ - return SET; - } - - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (~WWDGT_STAT_EWIF); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h deleted file mode 100644 index 189be18bae..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h +++ /dev/null @@ -1,217 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device driver core - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usbd_regs.h" - -/* interrupt flag mask which decide what event should be handled by application */ -#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ - | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE) - -#ifdef LPM_ENABLED -#undef IER_MASK - -#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ - | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE | CTL_L1REQIE) -#endif /* LPM_ENABLED */ - -/* USB device endpoint0 max packet size */ -#define USBD_EP0_MAX_SIZE 64U - -#define USBD_CONTRL_STATUS_TX() do \ -{ \ - pbuf_reg->tx_count = 0U; \ - USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \ -} while(0) - -#define USBD_CONTRL_STATUS_RX() do \ -{ \ - USBD_STATUS_OUT_SET(EP0); \ - USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \ -} while(0) - -#define ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT) - -/* USB device endpoint type */ -typedef enum -{ - ENDP_CONTROL = 0, /*!< control endpoint type value */ - ENDP_ISOC, /*!< isochronous endpoint type value */ - ENDP_BULK, /*!< bulk endpoint type value */ - ENDP_INT /*!< interupt endpoint type value */ -}usbd_eptype_enum; - -/* USB device endpoint kind */ -typedef enum -{ - ENDP_SNG_BUF = 0, /*!< single buffer endpoint type value */ - ENDP_DBL_BUF /*!< double buffer endpoint type value */ -}usbd_epkind_enum; - -/* transfer direction */ -typedef enum -{ - USBD_RX = 0, /*!< receive direction type value */ - USBD_TX /*!< transmit direction type value */ -}usbd_dir_enum; - -/* USB device status */ -typedef enum -{ - USBD_UNCONNECTED = 0, /*!< USB device unconnected status */ - USBD_DEFAULT, /*!< USB device default status */ - USBD_ADDRESSED, /*!< USB device addressed status */ - USBD_CONFIGURED, /*!< USB device configured status */ - USBD_SUSPENDED, /*!< USB device suspended status */ - USBD_CONNECTED /*!< USB device connected status */ -}usbd_run_status_enum; - -/* USB device operation state */ -typedef enum -{ - USBD_OK = 0, /*!< USB device ok */ - USBD_BUSY, /*!< USB device busy */ - USBD_FAIL /*!< USB device fail */ -}usbd_status_enum; - -typedef struct -{ - uint16_t tx_addr; /*!< transmission address */ - uint16_t reserved0; - uint16_t tx_count; /*!< transmission count */ - uint16_t reserved1; - uint16_t rx_addr; /*!< reception address */ - uint16_t reserved2; - uint16_t rx_count; /*!< reception count */ - uint16_t reserved3; -}usbd_ep_buf_struct; - -/* USB endpoint structure */ -typedef struct -{ - /* basic parameters */ - uint8_t stall; /*!< endpoint stall status */ - uint32_t maxpacket; /*!< the maxpacket of the endpoint */ - - /* transaction level parameters */ - uint8_t *trs_buf; /*!< transaction buffer address */ - uint32_t trs_len; /*!< transaction buffer length */ - uint32_t trs_count; /*!< transaction data counts */ -}usb_ep_struct; - -/* USB standard device request structure */ -typedef struct -{ - uint8_t bmRequestType; /*!< the property of the request */ - uint8_t bRequest; /*!< the code of the request */ - uint16_t wValue; /*!< the value of the request which used to choose the different request in the same code request */ - uint16_t wIndex; /*!< USB standard device request index */ - uint16_t wLength; /*!< the return datas length that the host wants to get */ -}usb_device_req_struct; - -/* USB core driver struct */ -typedef struct -{ - /* basic parameters */ - uint8_t config_num; /*!< the number of the USB device configuration */ - __IO uint8_t status; /*!< USB device status */ - uint8_t prev_status; /*!< the previous USB device status */ - uint8_t remote_wakeup; /*!< the flag that point out the device whether support the remote wakeup function */ - - /* the parameters which needs in control transfer */ - uint8_t setup_packet[8]; /*!< the buffer used to store the setup packet */ - uint32_t ctl_count; /*!< the datas length of control transfer request */ - - /* device endpoints */ - usb_ep_struct in_ep[EP_COUNT]; /*!< the in direction endpoints */ - usb_ep_struct out_ep[EP_COUNT]; /*!< the out direction endpoints */ - -#ifdef LPM_ENABLED - uint8_t *bos_desc; /*!< BOS descriptor */ -#endif /* LPM_ENABLED */ - - uint8_t *dev_desc; /*!< device descriptor */ - uint8_t *config_desc; /*!< configuration descriptor */ - void* const *strings; /*!< configuration strings */ - - /* device class handler */ - usbd_status_enum (*class_init) (void *pudev, uint8_t config_index); - usbd_status_enum (*class_deinit) (void *pudev, uint8_t config_index); - usbd_status_enum (*class_req_handler) (void *pudev, usb_device_req_struct *req); - usbd_status_enum (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num); -}usbd_core_handle_struct; - -extern uint32_t g_free_buf_addr; -extern usbd_ep_buf_struct *pbuf_reg; - -/* function declarations */ -/* device core register initialization */ -void usbd_core_init (usbd_core_handle_struct *pudev); -/* device core register configure when stop device */ -void usbd_core_deinit (void); - -/* free buffer used from application by toggling the SW_BUF byte */ -void user_buffer_free (uint8_t ep_num, uint8_t dir); - -/* endpoint initialization */ -void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *pep_desc); -/* configure the endpoint when it is disabled */ -void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* set an endpoint to stall status */ -void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* write datas from user fifo to USBRAM */ -void usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); -/* read datas from USBRAM to user fifo */ -void usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); - -/* get the endpoint status */ -uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr); - -/* get the received data length */ -uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h deleted file mode 100644 index a524ea615f..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h +++ /dev/null @@ -1,62 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device interrupt handler header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" -#include "usbd_std.h" -#include "usbd_pwr.h" - -/* constants definitions */ -extern usbd_core_handle_struct usb_device_dev; - -typedef struct -{ - uint8_t (*SOF) (usbd_core_handle_struct *pudev); /*!< SOF ISR callback */ -}usbd_int_cb_struct; - -extern usbd_int_cb_struct *usbd_int_fops; - -/* function declarations */ -/* USB device interrupt service routine */ -void usbd_isr (void); -/* handle USB high priority successful transfer event */ -uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev); - -#endif /* USBD_INT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h deleted file mode 100644 index c0e6a21a19..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h +++ /dev/null @@ -1,52 +0,0 @@ -/*! - \file usbd_pwr.h - \brief USB device power management functions prototype - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_PWR_H -#define USBD_PWR_H - -#include "usbd_core.h" - -/* function declarations */ -/* USB wakeup first operation is to wakeup mcu */ -void resume_mcu (void); -/* set USB device to suspend mode */ -void usbd_suspend (void); -/* start to remote wakeup */ -void usbd_remote_wakeup_active (void); - -#endif /* USBD_PWR_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h deleted file mode 100644 index ef3c5c8fcc..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h +++ /dev/null @@ -1,297 +0,0 @@ -/*! - \file usbd_regs.h - \brief USB device registers - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_REGS_H -#define USBD_REGS_H - -#include "usbd_conf.h" - -/* USB device registers base address */ -#define USBD USBD_BASE -#define USBD_RAM (APB1_BUS_BASE + 0x00006000U) - -/* registers definitions */ -/* common registers */ -#define USBD_CTL (REG32(USBD + 0x40U)) /*!< control register */ -#define USBD_INTF (REG32(USBD + 0x44U)) /*!< interrupt flag register */ -#define USBD_STAT (REG32(USBD + 0x48U)) /*!< status register */ -#define USBD_DADDR (REG32(USBD + 0x4CU)) /*!< device address register */ -#define USBD_BADDR (REG32(USBD + 0x50U)) /*!< buffer address register */ - -/* endpoint control and status register */ -#define USBD_EPxCS(ep_id) (REG32(USBD + (ep_id) * 4U)) /*!< endpoint x control and status register address */ - -/* LPM Registers */ -#define USBD_LPMCS (REG32(USBD + 0x54U)) /*!< USBD LPM control and status register */ - -/* bits definitions */ -/* USBD_CTL */ -#define CTL_STIE BIT(15) /*!< successful transfer interrupt enable mask */ -#define CTL_PMOUIE BIT(14) /*!< packet memory overrun/underrun interrupt enable mask */ -#define CTL_ERRIE BIT(13) /*!< error interrupt enable mask */ -#define CTL_WKUPIE BIT(12) /*!< wakeup interrupt enable mask */ -#define CTL_SPSIE BIT(11) /*!< suspend state interrupt enable mask */ -#define CTL_RSTIE BIT(10) /*!< reset interrupt enable mask */ -#define CTL_SOFIE BIT(9) /*!< start of frame interrupt enable mask */ -#define CTL_ESOFIE BIT(8) /*!< expected start of frame interrupt enable mask */ -#define CTL_L1REQIE BIT(7) /*!< LPM L1 state request interrupt enable */ -#define CTL_L1RSREQ BIT(5) /*!< LPM L1 resume request */ -#define CTL_RSREQ BIT(4) /*!< resume request */ -#define CTL_SETSPS BIT(3) /*!< set suspend state */ -#define CTL_LOWM BIT(2) /*!< low-power mode at suspend state */ -#define CTL_CLOSE BIT(1) /*!< goes to close state */ -#define CTL_SETRST BIT(0) /*!< set USB reset */ - -/* USBD_INTF */ -#define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */ -#define INTF_PMOUIF BIT(14) /*!< packet memory overrun/underrun interrupt flag (clear-only bit) */ -#define INTF_ERRIF BIT(13) /*!< error interrupt flag (clear-only bit) */ -#define INTF_WKUPIF BIT(12) /*!< wakeup interrupt flag (clear-only bit) */ -#define INTF_SPSIF BIT(11) /*!< suspend state interrupt flag (clear-only bit) */ -#define INTF_RSTIF BIT(10) /*!< reset interrupt flag (clear-only bit) */ -#define INTF_SOFIF BIT(9) /*!< start of frame interrupt flag (clear-only bit) */ -#define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */ -#define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */ -#define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */ -#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */ - -/* USBD_STAT */ -#define STAT_RXDP BIT(15) /*!< data plus line status */ -#define STAT_RXDM BIT(14) /*!< data minus line status */ -#define STAT_LOCK BIT(13) /*!< locked the USB */ -#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */ -#define STAT_FCNT BITS(0, 10) /*!< frame number count */ - -/* USBD_DADDR */ -#define DADDR_USBEN BIT(7) /*!< USB module enable */ -#define DADDR_USBDAR BITS(0, 6) /*!< USB device address */ - -/* USBD_EPxCS */ -#define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */ -#define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */ -#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */ -#define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */ -#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */ -#define EPxCS_KCTL BIT(8) /*!< endpoint kind control */ -#define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */ -#define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */ -#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */ -#define EPxCS_ADDR BITS(0, 3) /*!< endpoint address */ - -/* USBD_LPMCS */ -#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */ -#define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */ -#define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */ -#define LPMCS_LPMEN BIT(0) /*!< LPM support enable */ - -/* constants definitions */ -/* endpoint control and status register mask (no toggle fields) */ -#define EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR) - -/* EPxCS_CTL[1:0] endpoint type control */ -#define ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U)) - -#define EP_BULK ENDP_TYPE(0U) /* bulk transfers */ -#define EP_CONTROL ENDP_TYPE(1U) /* control transfers */ -#define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */ -#define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */ -#define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK) - -/* endpoint kind control mask */ -#define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK) - -/* EPxCS_TX_STA[1:0] status for tx transfer */ -#define ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U)) - -#define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */ -#define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */ -#define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */ -#define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */ -#define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK) - -/* EPxCS_RX_STA[1:0] status for rx transfer */ -#define ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U)) - -#define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */ -#define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */ -#define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */ -#define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */ -#define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK) - -/* endpoint receive/transmission counter register bit definitions */ -#define EPRCNT_BLKSIZ BIT(15) /* reception data block size */ -#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */ -#define EPRCNT_CNT BITS(0, 9) /* reception data count */ - -#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */ - -/* interrupt flag clear bits */ -#define CLR_STIF (~INTF_STIF) -#define CLR_PMOUIF (~INTF_PMOUIF) -#define CLR_ERRIF (~INTF_ERRIF) -#define CLR_WKUPIF (~INTF_WKUPIF) -#define CLR_SPSIF (~INTF_SPSIF) -#define CLR_RSTIF (~INTF_RSTIF) -#define CLR_SOFIF (~INTF_SOFIF) -#define CLR_ESOFIF (~INTF_ESOFIF) -#define CLR_L1REQ (~INTF_L1REQ) - -/* endpoint receive/transmission counter register bit offset */ -#define BLKSIZE_OFFSET (0x01U) -#define BLKNUM_OFFSET (0x05U) -#define RXCNT_OFFSET (0x0AU) - -#define TXCNT_OFFSET (0x0AU) - -#define BLKSIZE32_MASK (0x1fU) -#define BLKSIZE2_MASK (0x01U) - -#define BLKSIZE32_OFFSETMASK (0x05U) -#define BLKSIZE2_OFFSETMASK (0x01U) - -/* double buffer endpoint direction */ -typedef enum -{ - DBUF_EP_IN, /* double buffer IN direction */ - DBUF_EP_OUT, /* double buffer OUT direction */ - DBUF_EP_ERR, /* double buffer errer direction */ -}dbuf_ep_dir_enum; - -/* endpoints address */ -/* first bit is direction(0 for rx and 1 for tx) */ -#define EP0_OUT ((uint8_t)0x00) /* out endpoint 0 address */ -#define EP0_IN ((uint8_t)0x80) /* in endpoint 0 address */ -#define EP1_OUT ((uint8_t)0x01) /* out endpoint 1 address */ -#define EP1_IN ((uint8_t)0x81) /* in endpoint 1 address */ -#define EP2_OUT ((uint8_t)0x02) /* out endpoint 2 address */ -#define EP2_IN ((uint8_t)0x82) /* in endpoint 2 address */ -#define EP3_OUT ((uint8_t)0x03) /* out endpoint 3 address */ -#define EP3_IN ((uint8_t)0x83) /* in endpoint 3 address */ -#define EP4_OUT ((uint8_t)0x04) /* out endpoint 4 address */ -#define EP4_IN ((uint8_t)0x84) /* in endpoint 4 address */ -#define EP5_OUT ((uint8_t)0x05) /* out endpoint 5 address */ -#define EP5_IN ((uint8_t)0x85) /* in endpoint 5 address */ -#define EP6_OUT ((uint8_t)0x06) /* out endpoint 6 address */ -#define EP6_IN ((uint8_t)0x86) /* in endpoint 6 address */ -#define EP7_OUT ((uint8_t)0x07) /* out endpoint 7 address */ -#define EP7_IN ((uint8_t)0x87) /* in endpoint 7 address */ - -/* endpoints_identifier */ -#define EP0 ((uint8_t)0) /* endpoint 0 ID */ -#define EP1 ((uint8_t)1) /* endpoint 1 ID */ -#define EP2 ((uint8_t)2) /* endpoint 2 ID */ -#define EP3 ((uint8_t)3) /* endpoint 3 ID */ -#define EP4 ((uint8_t)4) /* endpoint 4 ID */ -#define EP5 ((uint8_t)5) /* endpoint 5 ID */ -#define EP6 ((uint8_t)6) /* endpoint 6 ID */ -#define EP7 ((uint8_t)7) /* endpoint 7 ID */ - -/* USBD operation macros */ - -/* set register value */ -#define USBD_REG_SET(reg, regvalue) ((reg) = (uint16_t)(regvalue)) - -/* get register value */ -#define USBD_REG_GET(reg) ((uint16_t)(reg)) - -#define _EP_ADDR_SET(ep_num, addr) USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr) - -/* tx or rx transfer status setting (bits EPTX_STA[1:0]) */ -#define USBD_ENDP_TX_STATUS_SET(ep_num, state) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPTX_DTGMASK;\ - USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ -} while(0) - -#define USBD_ENDP_RX_STATUS_SET(ep_num, state) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPRX_DTGMASK;\ - USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ -} while(0) - -/* tx or rx transfer status getting (bits EPxCS_RX_STA[1:0]) */ -#define USBD_ENDP_TX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA) -#define USBD_ENDP_RX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA) - -/* rx and tx transfer status setting (bits EPxCS_RX_STA[1:0] & EPxCS_TX_STA[1:0]) */ -#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)(EPRX_DTGMASK | EPxCS_TX_STA) ;\ - USBD_REG_SET(USBD_EPxCS(ep_num), (((_regval) ^ (state_rx)) ^ (state_tx))); \ -} while(0) - -/* set and clear endpoint kind (bit EPxCS_KCTL) */ -#define USBD_ENDP_KIND_SET(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK))) -#define USBD_ENDP_KIND_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK))) - -/* set and clear directly STATUS_OUT state of endpoint */ -#define USBD_STATUS_OUT_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) -#define USBD_STATUS_OUT_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) - -/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */ -#define USBD_ENDP_RX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK)) -#define USBD_ENDP_TX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK)) - -/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ -#define USBD_DTG_RX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) -#define USBD_DTG_TX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) - -/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ -#define USBD_DTG_RX_CLEAR(ep_num) do {\ - if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_DTG) != 0U) {\ - USBD_DTG_RX_TOGGLE(ep_num);\ - } else {\ - }\ -} while(0) - -#define USBD_DTG_TX_CLEAR(ep_num) do {\ - if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_DTG) != 0U) {\ - USBD_DTG_TX_TOGGLE(ep_num);\ - } else {\ - }\ -} while(0) - -/* set and clear directly double buffered feature of endpoint */ -#define USBD_ENDP_DOUBLE_BUF_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) -#define USBD_ENDP_DOUBLE_BUF_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) - -/* toggle SW_BUF bit in the double buffered endpoint */ -#define USBD_SWBUF_TX_TOGGLE(ep_num) USBD_DTG_RX_TOGGLE(ep_num) -#define USBD_SWBUF_RX_TOGGLE(ep_num) USBD_DTG_TX_TOGGLE(ep_num) - -#endif /* USBD_REGS_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h deleted file mode 100644 index 58a85d6cfc..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h +++ /dev/null @@ -1,221 +0,0 @@ -/*! - \file usbd_std.h - \brief USB standard definitions - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usbd_core.h" -#include - -#ifndef NULL -#define NULL 0U -#endif - -/* constants definitions */ -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */ - -#define USBD_LANGID_STR_IDX 0x00U /* language ID string index */ -#define USBD_MFC_STR_IDX 0x01U /* manufacturer string index */ -#define USBD_PRODUCT_STR_IDX 0x02U /* product string index */ -#define USBD_SERIAL_STR_IDX 0x03U /* serial string index */ -#define USBD_CONFIG_STR_IDX 0x04U /* configuration string index */ -#define USBD_INTERFACE_STR_IDX 0x05U /* interface string index */ - -#define USB_STANDARD_REQ 0x00U /* standard request */ -#define USB_CLASS_REQ 0x20U /* device class request */ -#define USB_VENDOR_REQ 0x40U /* vendor request */ -#define USB_REQ_MASK 0x60U /* request type mask */ - -#define USB_REQTYPE_DEVICE 0x00U /* request recipient is device */ -#define USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */ -#define USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */ -#define USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */ - -#define USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */ -#define USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */ -#define USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */ -#define USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */ -#define USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */ -#define USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */ -#define USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */ -#define USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */ -#define USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */ - -#define USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */ -#define USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */ -#define USB_DESCTYPE_STRING 0x03U /* string descriptor type */ -#define USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */ -#define USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */ -#define USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */ - -#define USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */ -#define USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */ - -#define USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */ -#define USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */ -#define USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */ - -#define ENG_LANGID 0x0409U /* english language ID */ -#define CHN_LANGID 0x0804U /* chinese language ID */ - -#define USB_EPTYPE_MASK 0x03U - -#define USB_DEVICE_DESC_SIZE 0x12U - -/* USB device exported macros */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -#pragma pack(1) - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -#pragma pack() - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -#pragma pack(1) - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -/* function declarations */ -/* USB setup transaction processing */ -uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev); -/* USB out transaction processing */ -uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); -/* USB in transaction processing */ -uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); - -/* handle USB standard device request */ -uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle device class request */ -uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle USB vendor request */ -uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -/* decode setup data packet */ -void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle USB enumeration error event */ -void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c deleted file mode 100644 index 4af7b03469..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c +++ /dev/null @@ -1,455 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -uint32_t g_interrupt_mask = 0U; -uint32_t g_free_buf_addr = ENDP_BUF_ADDR; - -usbd_ep_buf_struct *pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM; - -/*! - \brief device core register initialization - \param[in] none - \param[out] none - \retval none -*/ -void usbd_core_init (usbd_core_handle_struct *pudev) -{ - /* disable remote wakeup feature */ - pudev->remote_wakeup = 0U; - - /* just reset the CLOSE bit */ - USBD_REG_SET(USBD_CTL, CTL_SETRST); - - /* may be need wait some time(tSTARTUP) ... */ - - /* clear SETRST bit in USBD_CTL register */ - USBD_REG_SET(USBD_CTL, 0U); - - /* clear all pending interrupts */ - USBD_REG_SET(USBD_INTF, 0U); - - /* set allocation buffer address */ - USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U); - - g_interrupt_mask = IER_MASK; - -#ifdef LPM_ENABLED - /* enable L1REQ interrupt */ - USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN); -#endif /* LPM_ENABLED */ - - /* enable all interrupts mask bits */ - USBD_REG_SET(USBD_CTL, g_interrupt_mask); -} - -/*! - \brief free buffer used from application by toggling the SW_BUF byte - \param[in] ep_num: endpoint identifier (0..7) - \param[in] dir: endpoint direction which can be OUT(0) or IN(1) - \param[out] none - \retval None -*/ -void user_buffer_free (uint8_t ep_num, uint8_t dir) -{ - if (DBUF_EP_OUT == dir) { - USBD_SWBUF_RX_TOGGLE(ep_num); - } else if (DBUF_EP_IN == dir) { - USBD_SWBUF_TX_TOGGLE(ep_num); - } else { - /* no operation */ - } -} - -/*! - \brief device core register configure when stop device - \param[in] none - \param[out] none - \retval none -*/ -void usbd_core_deinit (void) -{ - /* disable all interrupts and set USB reset */ - USBD_REG_SET(USBD_CTL, CTL_SETRST); - - /* clear all interrupt flags */ - USBD_REG_SET(USBD_INTF, 0U); - - /* close device */ - USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to USB core instance - \param[in] buf_kind: kind of buffer - \param[in] pep_desc: pointer to endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *ep_desc) -{ - usb_descriptor_endpoint_struct *desc_ep = (usb_descriptor_endpoint_struct *)ep_desc; - - uint8_t ep_num = desc_ep->bEndpointAddress & 0x0FU; - uint32_t reg_value = 0; - - /* set the endpoint type */ - switch (desc_ep->bmAttributes & USB_EPTYPE_MASK) { - case ENDP_CONTROL: - reg_value = EP_CONTROL; - break; - case ENDP_BULK: - reg_value = EP_BULK; - break; - case ENDP_INT: - reg_value = EP_INTERRUPT; - break; - case ENDP_ISOC: - reg_value = EP_ISO; - break; - default: - break; - } - - USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num); - - reg_value = desc_ep->wMaxPacketSize; - - if (desc_ep->bEndpointAddress >> 7U) { - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - ep->maxpacket = reg_value; - - /* set the endpoint transmit buffer address */ - (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; - - reg_value = (reg_value + 1U) & ~1U; - - g_free_buf_addr += reg_value; - - if (ENDP_DBL_BUF == buf_kind) { - USBD_ENDP_DOUBLE_BUF_SET(ep_num); - - (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; - - g_free_buf_addr += reg_value; - - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); - } else { - /* configure the endpoint status as NAK status */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); - } - } else { - usb_ep_struct *ep = &pudev->out_ep[ep_num]; - - ep->maxpacket = reg_value; - - if (ENDP_DBL_BUF == buf_kind) { - USBD_ENDP_DOUBLE_BUF_SET(ep_num); - - USBD_DTG_TX_TOGGLE(ep_num); - - /* set the endpoint transmit buffer address */ - (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; - - if (reg_value > 62U) { - reg_value = (reg_value + 31U) & ~31U; - (pbuf_reg + ep_num)->tx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); - } else { - reg_value = (reg_value + 1U) & ~1U; - (pbuf_reg + ep_num)->tx_count = (uint16_t)(reg_value << 9U); - } - - g_free_buf_addr += reg_value; - } - - reg_value = desc_ep->wMaxPacketSize; - - /* set the endpoint receive buffer address */ - (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; - - if (reg_value > 62U) { - reg_value = (reg_value + 31U) & ~31U; - (pbuf_reg + ep_num)->rx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); - } else { - reg_value = (reg_value + 1U) & ~1U; - (pbuf_reg + ep_num)->rx_count = (uint16_t)(reg_value << 9U); - } - - if (ENDP_DBL_BUF == buf_kind) { - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); - } else { - /* configure the endpoint status as NAK status */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK); - } - } -} - -/*! - \brief configure the endpoint when it is disabled - \param[in] pudev: pointer to USB core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7F; - - if (ep_addr >> 7) { - USBD_DTG_TX_CLEAR(ep_num); - - /* configure the endpoint status as DISABLED */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED); - } else { - USBD_DTG_RX_CLEAR(ep_num); - - /* configure the endpoint status as DISABLED */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); - } -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[in] pbuf: user buffer address pointer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - - ep = &pudev->out_ep[ep_num]; - - /* configure the transaction level parameters */ - ep->trs_buf = pbuf; - ep->trs_len = buf_len; - - /* enable endpoint to receive */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to USB core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[in] pbuf: transmit buffer address pointer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - __IO uint32_t len = 0U; - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - /* configure the transaction level parameters */ - ep->trs_buf = pbuf; - ep->trs_len = buf_len; - ep->trs_count = 0U; - - /* transmit length is more than one packet */ - if (ep->trs_len > ep->maxpacket) { - len = ep->maxpacket; - } else { - len = ep->trs_len; - } - - usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len); - (pbuf_reg + ep_num)->tx_count = (uint16_t)len; - - /* enable endpoint to transmit */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); -} - -/*! - \brief set an endpoint to stall status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep; - - if (ep_addr >> 7U) { - ep = &pudev->in_ep[ep_num]; - - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL); - } else { - ep = &pudev->out_ep[ep_num]; - - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL); - } - - ep->stall = 1U; - - if (0U == ep_num) { - /* control endpoint need to be stalled in two directions */ - USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL); - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep; - - if (ep_addr >> 7U) { - ep = &pudev->in_ep[ep_num]; - - /* clear endpoint data toggle bit */ - USBD_DTG_TX_CLEAR(ep_num); - - /* clear endpoint stall status */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); - } else { - ep = &pudev->out_ep[ep_num]; - - /* clear endpoint data toggle bit */ - USBD_DTG_RX_CLEAR(ep_num); - - /* clear endpoint stall status */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); - } - - ep->stall = 0U; -} - -/*! - \brief get the endpoint status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval endpoint status -*/ -uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7U) { - return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU)); - } else { - return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr); - } -} - -/*! - \brief write datas from user fifo to USBRAM - \param[in] user_fifo: pointer to user fifo - \param[in] usbram_addr: the allocation buffer address of the endpoint - \param[in] bytes: the bytes count of the write datas - \param[out] none - \retval none -*/ -void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) -{ - uint32_t n; - uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); - - for (n = 0U; n < (bytes + 1U) / 2U; n++) { - *write_addr++ = *((__packed uint16_t*)user_fifo); - user_fifo += 2U; - } -} - -/*! - \brief read datas from USBRAM to user fifo - \param[in] user_fifo: pointer to user fifo - \param[in] usbram_addr: the allocation buffer address of the endpoint - \param[in] bytes: the bytes count of the read datas - \param[out] none - \retval none -*/ -void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) -{ - uint32_t n; - uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); - - for (n = 0U; n < (bytes + 1U) / 2U; n++) { - *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++; - user_fifo += 2U; - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to USB core instance - \param[in] ep_num: endpoint identifier which is in (0..7) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - return (uint16_t)pudev->out_ep[ep_num].trs_count; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c deleted file mode 100644 index f9e58fe3d9..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c +++ /dev/null @@ -1,458 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device power interrupt routines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_int.h" - -extern uint32_t g_interrupt_mask; -extern __IO uint8_t g_suspend_enabled; -extern __IO uint8_t g_remote_wakeup_on; -extern __IO uint8_t g_ESOF_count; - -#ifdef LPM_ENABLED -__IO uint32_t L1_remote_wakeup = 0U; -__IO uint32_t L1_resume = 0U; -__IO uint32_t besl = 0U; -#endif /* LPM_ENABLED */ - -static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev); - -/*! - \brief USB interrupt events service routine - \param[in] none - \param[out] none - \retval none -*/ -void usbd_isr (void) -{ - __IO uint16_t interrupt_flag = 0U; - __IO uint16_t ctlr = 0U; - - interrupt_flag = USBD_REG_GET(USBD_INTF); - - if (g_interrupt_mask & INTF_STIF & interrupt_flag) { - /* the endpoint successful transfer interrupt service */ - usbd_intf_lpst(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) { - /* clear wakeup interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF); - - /* USB wakeup interrupt handle */ - usbd_intf_wakeup(&usb_device_dev); - -#ifdef LPM_ENABLED - /* clear L1 remote wakeup flag */ - L1_remote_wakeup = 0; -#endif /* LPM_ENABLED */ - } - - if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) { - if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) { - /* process library core layer suspend routine*/ - usbd_intf_suspend(&usb_device_dev); - - /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF); - } - } - - if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) { - /* clear SOF interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF); - - /* USB SOF interrupt handle */ - usbd_intf_sof(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) { - /* clear ESOF interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF); - - /* USB ESOF interrupt handle */ - usbd_intf_esof(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) { - /* clear reset interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF); - - /* USB reset interrupt handle */ - usbd_intf_reset(&usb_device_dev); - } - -#ifdef LPM_ENABLED - if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) { - /* clear L1 ST bit in LPM INTF */ - USBD_REG_SET(USBD_INTF, CLR_L1REQ); - - /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */ - besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4; - - /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */ - L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8; - - /* process USB device core layer suspend routine */ - /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */ - usbd_intf_suspend(&usb_device_dev); - } -#endif /* LPM_ENABLED */ -} - -/*! - \brief handle USB high priority successful transfer event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev) -{ - uint8_t ep_num = 0U; - - __IO uint16_t int_status = 0U; - __IO uint16_t ep_value = 0U; - - usb_ep_struct *ep = NULL; - - /* wait till interrupts are not pending */ - while (0U != ((int_status = USBD_INTF) & (uint16_t)INTF_STIF)) { - /* get endpoint number and the value of control and state register */ - ep_num = (uint8_t)(int_status & INTF_EPNUM); - ep_value = USBD_EPxCS(ep_num); - - if (0U == (int_status & INTF_DIR)) { - /* handle the in direction transaction */ - - ep = &(pudev->in_ep[ep_num]); - - if (0U != (ep_value & EPxCS_TX_ST)) { - /* clear successful transmit interrupt flag */ - USBD_ENDP_TX_STAT_CLEAR(ep_num); - - if (ep_value & EPxCS_TX_DTG) { - /* just handle single buffer situation */ - ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; - } - - /* maybe mutiple packets */ - ep->trs_buf += ep->trs_count; - - usbd_in_transaction(pudev, ep_num); - } - } else { - /* handle the out direction transaction */ - - uint16_t count = 0U; - - ep = &(pudev->out_ep[ep_num]); - - if (0U != (ep_value & EPxCS_RX_ST)) { - /* clear successful receive interrupt flag */ - USBD_ENDP_RX_STAT_CLEAR(ep_num); - - if (ep_value & EPxCS_TX_DTG) { - count = (pbuf_reg + ep_num)->tx_count & (uint16_t)EPRCNT_CNT; - - if (0U != count) { - usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, count); - } - } else { - count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; - - if (0U != count) { - usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); - } - } - - user_buffer_free(ep_num, DBUF_EP_OUT); - - /* maybe mutiple packets */ - ep->trs_count += count; - ep->trs_buf += count; - ep->trs_len -= count; - - if ((0U == ep->trs_len) || (count < ep->maxpacket)) { - USBD_ENDP_TX_STATUS_SET(ep_num, EPRX_NAK); - - /* enter data OUT status */ - usbd_out_transaction(pudev, ep_num); - - ep->trs_count = 0U; - } - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB low priority successful transfer event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev) -{ - uint8_t ep_num = 0U; - - __IO uint16_t int_status = 0U; - __IO uint16_t ep_value = 0U; - - usb_ep_struct *ep = NULL; - - /* wait till interrupts are not pending */ - while (0U != ((int_status = USBD_REG_GET(USBD_INTF)) & (uint16_t)INTF_STIF)) { - /* get endpoint number and the value of control and state register */ - ep_num = (uint8_t)(int_status & INTF_EPNUM); - ep_value = USBD_REG_GET(USBD_EPxCS(ep_num)); - - if (0U == (int_status & INTF_DIR)) { - /* handle the in direction transaction */ - - ep = &(pudev->in_ep[ep_num]); - - if (0U != (ep_value & EPxCS_TX_ST)) { - /* clear successful transmit interrupt flag */ - USBD_ENDP_TX_STAT_CLEAR(ep_num); - - /* just handle single buffer situation */ - ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; - - /* maybe mutiple packets */ - ep->trs_buf += ep->trs_count; - - usbd_in_transaction(pudev, ep_num); - } - } else { - /* handle the out direction transaction */ - - uint16_t count = 0U; - - ep = &(pudev->out_ep[ep_num]); - - if (0U != (ep_value & EPxCS_RX_ST)) { - /* clear successful receive interrupt flag */ - USBD_ENDP_RX_STAT_CLEAR(ep_num); - - count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; - - if (0U != count) { - if (0U != (ep_value & EPxCS_SETUP)) { - /* handle setup packet */ - usbd_ep_data_read(&(pudev->setup_packet[0]), pbuf_reg->rx_addr, count); - - /* enter setup status */ - usbd_setup_transaction(pudev); - - return USBD_OK; - } else { - usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); - } - } - - /* maybe mutiple packets */ - ep->trs_count += count; - ep->trs_buf += count; - ep->trs_len -= count; - - if ((0U == ep->trs_len) || (count < ep->maxpacket)) { - /* enter data OUT status */ - usbd_out_transaction(pudev, ep_num); - - ep->trs_count = 0U; - } else { - usbd_ep_rx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); - } - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB SOF event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev) -{ - /* if necessary, user can add code here */ - if (NULL != usbd_int_fops) { - usbd_int_fops->SOF(pudev); - } - - return USBD_OK; -} - -/*! - \brief handle USB expect SOF event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev) -{ - /* control resume time by ESOFs */ - if (g_ESOF_count > 0U) { - g_ESOF_count--; - - if (0U == g_ESOF_count) { - if (1U == g_remote_wakeup_on) { - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_RSREQ); - - g_remote_wakeup_on = 0U; - } else { - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); - - g_ESOF_count = 3U; - g_remote_wakeup_on = 1U; - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB reset event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev) -{ - uint8_t i; - - g_free_buf_addr = ENDP_BUF_ADDR; - - /* configure endpoint 0 buffer */ - pbuf_reg->tx_addr = (uint16_t)g_free_buf_addr; - g_free_buf_addr += USBD_EP0_MAX_SIZE; - - pbuf_reg->rx_addr = (uint16_t)g_free_buf_addr; - g_free_buf_addr += USBD_EP0_MAX_SIZE; - - /* configure endpoint 0 Rx count */ - if (USBD_EP0_MAX_SIZE > 62U) { - pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE << 5U) - 1U) | 0x8000U; - } else { - pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE + 1U) & ~1U) << 9U; - } - - pudev->in_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; - pudev->out_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; - - /* set endpoints address */ - for (i = 0U; i < EP_COUNT; i++) - { - _EP_ADDR_SET(i, i); - } - - /* set device address as default address 0 */ - USBD_REG_SET(USBD_DADDR, DADDR_USBEN); - - /* clear endpoint 0 register */ - USBD_REG_SET(USBD_EPxCS(EP0), USBD_EPxCS(EP0)); - - USBD_REG_SET(USBD_EPxCS(EP0), EP_CONTROL | EPRX_VALID | EPTX_NAK); - - pudev->status = USBD_DEFAULT; - - return USBD_OK; -} - -/*! - \brief handle USB suspend event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev) -{ - /* store the device current status */ - pudev->prev_status = pudev->status; - - /* set device in suspended state */ - pudev->status = USBD_SUSPENDED; - - /* enter USB in suspend and mcu system in low power mode */ - if (g_suspend_enabled) { - usbd_suspend(); - } else { - /* if not possible then resume after xx ms */ - g_ESOF_count = 3U; - } - - return USBD_OK; -} - -/*! - \brief handle USB wakeup event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev) -{ - /* restore the old status */ - pudev->status = pudev->prev_status; - -#ifdef LPM_ENABLED - if ((0U == g_remote_wakeup_on) && (0U == L1_resume)) { - resume_mcu(); - } else if (1U == g_remote_wakeup_on) { - /* no operation */ - } else { - L1_resume = 0U; - } -#else - if (0U == g_remote_wakeup_on) { - resume_mcu(); - } -#endif /* LPM_ENABLED */ - - return USBD_OK; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c deleted file mode 100644 index febdd765f4..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c +++ /dev/null @@ -1,159 +0,0 @@ -/*! - \file usbd_pwr.c - \brief USB device power management driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_pwr.h" - -#ifdef USBD_LOWPWR_MODE_ENABLE -static void lowpower_mode_exit (void); -#endif /* USBD_LOWPWR_MODE_ENABLE */ - -__IO uint8_t g_ESOF_count = 0U; -__IO uint8_t g_suspend_enabled = 1U; -__IO uint8_t g_remote_wakeup_on = 0U; - -#ifdef LPM_ENABLED -extern __IO uint32_t L1_resume; -#endif /* LPM_ENABLED */ - -/*! - \brief USB wakeup first operation is to wakeup mcu - \param[in] none - \param[out] none - \retval none -*/ -void resume_mcu (void) -{ - /* clear low_power mode bit in USBD_CTL */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM)); - -#ifdef USBD_LOWPWR_MODE_ENABLE - - /* restore normal operations */ - lowpower_mode_exit(); - -#endif /* USBD_LOWPWR_MODE_ENABLE */ - - /* clear SETSPS bit */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS)); -} - -#ifdef USBD_LOWPWR_MODE_ENABLE - -/*! - \brief restore system clocks and power while exiting suspend mode - \param[in] none - \param[out] none - \retval none -*/ -static void lowpower_mode_exit (void) -{ - /* restore system clock */ - - /* enable HSE */ - rcu_osci_on(RCU_HXTAL); - - /* wait till HSE is ready */ - while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB)); - - /* enable PLL */ - rcu_osci_on(RCU_PLL_CK); - - /* wait till PLL is ready */ - while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB)); - - /* select PLL as system clock source */ - rcu_system_clock_source_config(RCU_CKSYSSRC_PLL); - - /* wait till PLL is used as system clock source */ - while(0x08 != rcu_system_clock_source_get()); - - /* low power sleep on exit disabled */ - system_lowpower_reset(SCB_LPM_DEEPSLEEP); -} - -#endif /* USBD_LOWPWR_MODE_ENABLE */ - -/*! - \brief set USB device to suspend mode - \param[in] none - \param[out] none - \retval none -*/ -void usbd_suspend (void) -{ - /* set usb module to suspend and low-power mode */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM); - -#ifdef USBD_LOWPWR_MODE_ENABLE - - /* check wakeup flag is set */ - if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) { - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } else { - /* clear wakeup interrupt flag */ - USBD_REG_SET(USBD_INTF, CLR_WKUPIF); - - /* clear set_suspend flag */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS); - } - -#endif /* USBD_LOWPWR_MODE_ENABLE */ -} - -/*! - \brief start to remote wakeup - \param[in] none - \param[out] none - \retval none -*/ -void usbd_remote_wakeup_active(void) -{ - resume_mcu(); - -#ifdef LPM_ENABLED - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ); - - L1_resume = 1U; -#else - g_remote_wakeup_on = 1U; - - g_ESOF_count = 15U; - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); -#endif /* LPM_ENABLED */ -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c deleted file mode 100644 index 582d614fac..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c +++ /dev/null @@ -1,868 +0,0 @@ -/*! - \file usbd_std.c - \brief USB device stand routines - \note about USB standard, please refer to the USB2.0 protocol - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_std.h" - -uint8_t g_device_address = 0U; - -/* USB enumeration handle functions */ -static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -#ifdef LPM_ENABLED -static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen); -#endif /* LPM_ENABLED */ - -/* standard device request handler */ -static void (*standard_device_request[])(usbd_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clearfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfiguration, - usbd_setconfiguration, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse (pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, 0x00U); - break; - } - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_num: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - usb_ep_struct *ep = &pudev->out_ep[ep_num]; - - if (0U == ep_num) { - if (0U != pudev->ctl_count) { - if (ep->trs_len > ep->maxpacket) { - /* one data packet has been received, update trs_len */ - ep->trs_len -= ep->maxpacket; - - /* continue to receive remain data */ - usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len); - } else { - if (USBD_CONFIGURED == pudev->status) { - /* device class handle */ - pudev->class_data_handler(pudev, USBD_RX, EP0); - } - - /* enter the control transaction status stage */ - USBD_CONTRL_STATUS_TX(); - - pudev->ctl_count = 0U; - } - } else { - /* clear endpoint status_out status */ - USBD_STATUS_OUT_CLEAR(EP0); - } - } else { - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_RX, ep_num); - } - } - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_num: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - if (0U == ep_num) { - if (0U != pudev->ctl_count) { - if (ep->trs_len > ep->maxpacket) { - /* one data packet has been transmited, update trs_len */ - ep->trs_len -= ep->maxpacket; - - /* continue to transmit remain data */ - usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len); - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { -#ifndef USB_DFU - /* transmit length is maxpacket multiple, so send zero length packet */ - if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) { - usbd_ep_tx (pudev, EP0_IN, NULL, 0U); - - pudev->ctl_count = 0U; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else -#endif /* USB_DFU */ - { - ep->trs_len = 0U; - - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_TX, EP0); - } - - USBD_CONTRL_STATUS_RX(); - - pudev->ctl_count = 0U; - } - } - } else { - if (0U != g_device_address) { - USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address); - g_device_address = 0U; - } - } - } else { - ep->trs_len -= ep->trs_count; - - if (0U == ep->trs_len) { - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_TX, ep_num); - } - } else { - usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); - } - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*standard_device_request[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret; - - switch (pudev->status) { - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* call device class handle function */ - ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - USBD_CONTRL_STATUS_TX(); - } - } else { - usbd_enum_error(pudev, req); - } - break; - default: - usbd_enum_error(pudev, req); - break; - } - - return USBD_OK; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation */ -} - -#ifdef LPM_ENABLED -/*! - \brief get BOS descriptor - \param[in] pudev: pointer to USB device instance - \param[in] pLen: data length pointer - \param[out] none - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen) -{ - *pLen = pudev->bos_desc[2] | ((uint16_t)pudev->bos_desc[3] << 8); - - return pudev->bos_desc; -} - -#endif /* LPM_ENABLED */ - -/*! - \brief get the device descriptor - \param[in] pudev: pointer to USB device instance - \param[in] index: no use - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev_desc[0]; - - return pudev->dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] pudev: pointer to USB device instance - \brief[in] index: no use - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->config_desc[2]; - - return pudev->config_desc; -} - -/*! - \brief get string descriptor - \param[in] pudev: pointer to USB device instance - \param[in] index: string descriptor index - \param[out] pLen: pointer to string length - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr; - uint16_t config_status = 0x0000U; - uint16_t endp_status = 0x0000U; - - switch(req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - -#ifdef USBD_SELF_POWERED - config_status = USB_STATUS_SELF_POWERED; -#endif /* USBD_SELF_POWERED */ - - if (pudev->remote_wakeup) { - config_status |= USB_STATUS_REMOTE_WAKEUP; - } - - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get enndpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - if ((ep_addr & 0x80U) == 0x80U) { - if(pudev->in_ep[ep_addr & 0x7FU].stall) { - endp_status = 0x0001U; - } - } else { - if (pudev->out_ep[ep_addr].stall) { - endp_status = 0x0001U; - } - } - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&endp_status, 2U); - break; - - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - /* clear device remote wakeup feature */ - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->remote_wakeup = 0U; - pudev->class_req_handler(pudev, req); - USBD_CONTRL_STATUS_TX(); - } else if (USB_FEATURE_TEST_MODE == req->wValue) { - /* can not clear test_mode feature */ - usbd_enum_error(pudev, req); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error (pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get endpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - /* clear endpoint halt feature */ - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - } - } - - pudev->class_req_handler(pudev, req); - - USBD_CONTRL_STATUS_TX(); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - /* set device remote wakeup feature */ - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->remote_wakeup = 1U; - - USBD_CONTRL_STATUS_TX(); - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get endpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - /* set endpoint halt feature */ - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - USBD_CONTRL_STATUS_TX(); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if ((0U == req->wIndex) && (0U == req->wLength)) { - g_device_address = (uint8_t)(req->wValue) & 0x7FU; - - if (USBD_CONFIGURED == pudev->status) { - usbd_enum_error(pudev, req); - } else { - USBD_CONTRL_STATUS_TX(); - - if (0U != g_device_address) { - pudev->status = USBD_ADDRESSED; - } else { - pudev->status = USBD_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { - uint8_t *pbuf = NULL; - uint8_t desc_type = (uint8_t)(req->wValue >> 8); - uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; - uint16_t len = 0U; - - if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); - } -#ifdef LPM_ENABLED - else if (USB_DESCTYPE_BOS == desc_type) { - pbuf = usbd_bos_descriptor_get(pudev, &len); - } -#endif /* LPM_ENABLED */ - else { - usbd_enum_error(pudev, req); - } - - if ((0U != len) && (0U != req->wLength)) { - len = MIN(len, req->wLength); - - usbd_ep_tx (pudev, EP0_IN, pbuf, len); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { - if (NULL != pudev->class_req_handler) { - /* get device class special descriptor */ - pudev->class_req_handler(pudev, req); - } - } else { - - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t usbd_default_config = 0U; - - if (req->wLength != 1U) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_ep_tx (pudev, EP0_IN, (uint8_t *)&usbd_default_config, 1U); - break; - case USBD_CONFIGURED: - usbd_ep_tx (pudev, EP0_IN, &pudev->config_num, 1U); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->status) { - case USBD_ADDRESSED: - if (cfgidx){ - pudev->config_num = cfgidx; - pudev->status = USBD_CONFIGURED; - pudev->class_init(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else { - USBD_CONTRL_STATUS_TX(); - } - break; - case USBD_CONFIGURED: - if (0U == cfgidx) { - pudev->status = USBD_ADDRESSED; - pudev->config_num = cfgidx; - pudev->class_deinit(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else if (cfgidx != pudev->config_num) { - /* clear old configuration */ - pudev->class_deinit(pudev, pudev->config_num); - - /* set new configuration */ - pudev->config_num = cfgidx; - pudev->class_init(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else { - USBD_CONTRL_STATUS_TX(); - } - break; - default: - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - if (NULL != pudev->class_req_handler) { - pudev->class_req_handler(pudev, req); - } - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - if (NULL != pudev->class_req_handler) { - pudev->class_req_handler(pudev, req); - } - - USBD_CONTRL_STATUS_TX(); - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *setup_data = pudev->setup_packet; - - req->bmRequestType = *setup_data; - req->bRequest = *(uint8_t *)(setup_data + 1U); - req->wValue = SWAPBYTE (setup_data + 2U); - req->wIndex = SWAPBYTE (setup_data + 4U); - req->wLength = SWAPBYTE (setup_data + 6U); - - pudev->ctl_count = req->wLength; -} - -/*! - \brief handle USB enumeration error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, EP0); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h deleted file mode 100644 index b50f903086..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h +++ /dev/null @@ -1,304 +0,0 @@ -/*! - \file usb_core.h - \brief USB core driver header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_CORE_H -#define USB_CORE_H - -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - -/* constants definitions */ -#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */ -#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ -#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ - -#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT -#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) - -/* USB core status */ -typedef enum -{ - USB_OK = 0, /* USB core OK status */ - USB_FAIL /* USB core fail status */ -}usb_status_enum; - -/* USB host channel status */ -typedef enum -{ - HC_IDLE = 0, /* USB host channel idle status */ - HC_XF, /* USB host channel transfer status */ - HC_HALTED, /* USB host channel halted status */ - HC_NAK, /* USB host channel nak status */ - HC_NYET, /* USB host channel nyet status */ - HC_STALL, /* USB host channel stall status */ - HC_TRACERR, /* USB host channel tracerr status */ - HC_BBERR, /* USB host channel bberr status */ - HC_DTGERR, /* USB host channel dtgerr status */ -}hc_status_enum; - -/* USB URB(USB request block) state */ -typedef enum -{ - URB_IDLE = 0, /* USB URB idle status */ - URB_DONE, /* USB URB done status */ - URB_NOTREADY, /* USB URB not ready status */ - URB_ERROR, /* USB URB error status */ - URB_STALL, /* USB URB stall status */ - URB_PING /* USB URB ping status */ -}urb_state_enum; - -/* USB core configuration */ -typedef struct -{ - uint8_t core_id; /* USB core id */ - uint8_t core_speed; /* USB core speed */ - uint8_t phy_interface; /* USB PHY interface */ - uint8_t host_channel_num; /* USB host channel number */ - uint8_t dev_endp_num; /* USB device endpoint number */ - uint8_t sof_output; /* USB SOF output */ - uint8_t low_power; /* USB low power */ - uint16_t max_packet_size; /* USB max packet size */ - uint16_t max_fifo_size; /* USB fifo size */ -}usb_core_cfgs_struct; - -typedef enum -{ - USBD_OK = 0, /* USB device ok status */ - USBD_BUSY, /* USB device busy status */ - USBD_FAIL, /* USB device fail stauts */ -}usbd_status_enum; - -/* USB control transfer state */ -typedef enum -{ - USB_CTRL_IDLE = 0, /* USB control transfer idle state */ - USB_CTRL_SETUP, /* USB control transfer setup state */ - USB_CTRL_DATA_IN, /* USB control transfer data in state */ - USB_CTRL_DATA_OUT, /* USB control transfer data out state */ - USB_CTRL_STATUS_IN, /* USB control transfer status in state*/ - USB_CTRL_STATUS_OUT, /* USB control transfer status out state */ - USB_CTRL_STALL /* USB control transfer stall state */ -}usbd_control_state_enum; - -/* USB transfer direction */ -typedef enum -{ - USB_RX = 0, /* receive direction type value */ - USB_TX /* transmit direction type value */ -}usb_dir_enum; - -/* USB endpoint in device mode */ -typedef struct -{ - uint8_t endp_type; /* USB endpoint type */ - uint8_t endp_frame; /* USB endpoint frame */ - uint32_t endp_mps; /* USB endpoint max packet size */ - - /* Transaction level variables */ - uint8_t *xfer_buff; /* USB transfer buffer */ - uint32_t xfer_len; /* USB transfer length */ - uint32_t xfer_count; /* USB transfer count */ - - uint32_t dma_addr; /* USBHS can use DMA */ -}usb_ep_struct; - -/* USB device standard request */ -typedef struct -{ - uint8_t bmRequestType; /* USB device request type */ - uint8_t bRequest; /* USB device request */ - uint16_t wValue; /* USB device request value */ - uint16_t wIndex; /* USB device request index */ - uint16_t wLength; /* USB device request length */ -}usb_device_req_struct; - -/* USB core device driver */ -typedef struct -{ - uint8_t config_num; /* USB configuration number */ - __IO uint8_t status; /* USB status */ - uint8_t ctl_status; /* USB control status */ - uint8_t prev_status; /* USB previous status */ - uint8_t connection_status; /* USB connection status */ - uint32_t remote_wakeup; /* USB remote wakeup */ - - /* transfer level variables */ - uint32_t remain_len; /* USB remain length */ - uint32_t sum_len; /* USB sum length */ - uint32_t ctl_len; /* USB control length */ - uint8_t setup_packet[8 * 3]; /* USB setup packet */ - - usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB in endpoint */ - usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB out endpoint */ - - uint8_t *dev_desc; /* device descriptor */ - uint8_t *config_desc; /* configuration descriptor */ - uint8_t* *strings; /* configuration strings */ - - /* device class handler */ - uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ - uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ - uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ - uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */ -}dcd_dev_struct; - -/* USB core host mode channel */ -typedef struct -{ - uint8_t dev_addr; /* device address */ - uint8_t dev_speed; /* device speed */ - uint8_t DPID; /* endpoint transfer data pid */ - uint8_t endp_id; /* endpoint number */ - uint8_t endp_in; /* endpoint in */ - uint8_t endp_type; /* endpoint type */ - uint16_t endp_mps; /* endpoint max pactet size */ - uint16_t info; /* channel information */ - - uint8_t *xfer_buff; /* transfer buffer */ - uint32_t xfer_len; /* transfer length */ - uint32_t xfer_count; /* trasnfer count */ - - uint32_t err_count; /* USB transfer error count */ - - hc_status_enum status; /* channel status */ - urb_state_enum urb_state; /* URB state */ - - uint8_t data_tg_in; /* data in toggle */ - uint8_t data_tg_out; /* data out toggle */ -}usb_hostchannel_struct; - -/* USB core host driver */ -typedef struct -{ - uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */ - uint8_t connect_status; /* device connect status */ - usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */ - void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */ -}hcd_dev_struct; - -#ifdef USE_OTG_MODE - -/* USB core OTG-mode driver */ -typedef struct -{ - uint8_t OTG_State; /* OTG state */ - uint8_t OTG_PrevState; /* OTG previous state */ - uint8_t OTG_Mode; /* OTG mode */ -}otg_dev_struct; - -#endif /* USE_OTG_MODE */ - -/* USB core driver */ -typedef struct -{ - usb_core_cfgs_struct cfg; - -#ifdef USE_DEVICE_MODE - dcd_dev_struct dev; -#endif /* USE_DEVICE_MODE */ - -#ifdef USE_HOST_MODE - hcd_dev_struct host; -#endif /* USE_HOST_MODE */ - -#ifdef USE_OTG_MODE - otg_dev_struct otg; -#endif /* USE_OTG_MODE */ - - void (*udelay) (const uint32_t usec); - void (*mdelay) (const uint32_t msec); -}usb_core_handle_struct; - -/* function declarations */ - -/* global APIs */ -/* initializes the USB controller registers and prepares the core device mode or host mode operation */ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev); -/* initialize core parameters */ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* read a packet from the rx fifo associated with the endpoint */ -void* usb_fifo_read (uint8_t *dest, uint16_t len); -/* write a packet into the tx fifo associated with the endpoint */ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len); -/* flush a tx fifo or all tx fifos */ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); -/* flush the entire rx fifo */ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev); -/* set operation mode (host or device) */ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode); - -/* host APIs */ -#ifdef USE_HOST_MODE - -/* initializes USB core for host mode */ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev); -/* enables the host mode interrupts */ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev); -/* initialize host channel */ -usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num); -/* halt channel */ -usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); -/* prepare host channel for transferring packets */ -usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); -/* reset host port */ -uint32_t usb_port_reset (usb_core_handle_struct *pudev); -/* control the VBUS to power */ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state); -/* stop the USB host and clean up fifos */ -void usb_host_stop (usb_core_handle_struct *pudev); - -#endif /* USE_HOST_MODE */ - -/* device APIs */ -#ifdef USE_DEVICE_MODE - -/* initialize USB core registers for device mode */ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev); -/* configures endpoint 0 to receive setup packets */ -void usb_ep0_startout (usb_core_handle_struct *pudev); -/* active remote wakeup signalling */ -void usb_remotewakeup_active (usb_core_handle_struct *pudev); -/* active USB core clock */ -void usb_clock_ungate (usb_core_handle_struct *pudev); -/* stop the device and clean up fifos */ -void usb_device_stop (usb_core_handle_struct *pudev); - -#endif /* USE_DEVICE_MODE */ - -#endif /* USB_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h deleted file mode 100644 index d9d1fd3c04..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h +++ /dev/null @@ -1,128 +0,0 @@ -/*! - \file usb_defines.h - \brief USB core defines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_DEFINES_H -#define USB_DEFINES_H - -#include "usb_conf.h" - -/* constants definitions */ -typedef enum -{ - USB_HS_CORE_ID = 0, - USB_FS_CORE_ID = 1 -}usb_core_id_enum; - -typedef enum -{ - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}usb_speed_enum; - -#ifndef NULL - #define NULL (void *)0 /*!< USB null marco value*/ -#endif /* NULL */ - -#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */ -#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */ - -#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */ -#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */ -#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */ -#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */ - -#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */ -#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */ -#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */ -#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */ - -#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */ -#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */ - -#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ -#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ - -#define GRSTATR_RPCKST_IN 2U /* in data packet received */ -#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* in transfer completed (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */ - -#define DEVICE_MODE 0U /* USB core in device mode */ -#define HOST_MODE 1U /* USB core in host mode */ -#define OTG_MODE 2U /* USB core in OTG mode */ - -#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */ -#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */ -#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */ -#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */ -#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */ - -#define RXSTAT_GOUT_NAK 1U /* global out NAK (triggers an interrupt) */ -#define RXSTAT_DATA_UPDT 2U /* out data packet received */ -#define RXSTAT_XFER_COMP 3U /* out transfer completed (triggers an interrupt) */ -#define RXSTAT_SETUP_COMP 4U /* setup transaction completed (triggers an interrupt) */ -#define RXSTAT_SETUP_UPDT 6U /* setup data packet received */ - -#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ -#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ -#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ -#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ - -#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */ -#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */ -#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */ -#define HC_PID_SETUP 3U /* host channel data PID is SETUP */ - -#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */ -#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */ -#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */ - -#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */ -#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */ -#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */ - -#define HCCHAR_CTRL 0U /* control channel type */ -#define HCCHAR_ISOC 1U /* synchronous channel type */ -#define HCCHAR_BULK 2U /* bulk channel type */ -#define HCCHAR_INTR 3U /* interrupt channel type */ - -#endif /* USB_DEFINES_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h deleted file mode 100644 index 2e7d444381..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h +++ /dev/null @@ -1,596 +0,0 @@ -/*! - \file usb_regs.h - \brief USB FS cell registers definition and handle macros - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_REGS_H -#define USB_REGS_H - -#include "usb_conf.h" - -#define USBFS USBFS_BASE /*!< base address of USBFS registers */ - -/* registers location definitions */ -#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device in endpoint-x (x = 1..3) transfer length registers */ -#define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ -#define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ -#define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ -#define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ -#define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device in endpoint-x control registers */ -#define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device out endpoint-x control registers */ -#define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device in endpoint-x interrupt flag registers */ -#define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device out endpoint-x interrupt flag registers */ -#define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device in endpoint-x transfer length registers */ -#define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device out endpoint-x transfer length registers */ -#define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device in endpoint-x transmit fifo status register */ -#define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ - -/* registers definitions */ -#define USB_GOTGCS REG32(((USBFS) + 0x0000U)) /*!< global OTG control and status register */ -#define USB_GOTGINTF REG32(((USBFS) + 0x0004U)) /*!< global OTG interrupt flag register */ -#define USB_GAHBCS REG32(((USBFS) + 0x0008U)) /*!< global AHB control and status register */ -#define USB_GUSBCS REG32(((USBFS) + 0x000CU)) /*!< global USB control and status register */ -#define USB_GRSTCTL REG32(((USBFS) + 0x0010U)) /*!< global reset control register */ -#define USB_GINTF REG32(((USBFS) + 0x0014U)) /*!< global interrupt flag register */ -#define USB_GINTEN REG32(((USBFS) + 0x0018U)) /*!< global interrupt enable register */ -#define USB_GRSTATR REG32(((USBFS) + 0x001CU)) /*!< global receive status read register */ -#define USB_GRSTATP REG32(((USBFS) + 0x0020U)) /*!< global receive status read and pop register */ -#define USB_GRFLEN REG32(((USBFS) + 0x0024U)) /*!< global receive fifo length register */ -#define USB_HNPTFLEN REG32(((USBFS) + 0x0028U)) /*!< host non-periodic transmit fifo length register */ -#define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U)) /*!< device in endpoint 0 transmit fifo length register */ -#define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU)) /*!< host non-periodic transmint fifo/queue status register */ -#define USB_GCCFG REG32(((USBFS) + 0x0038U)) /*!< global core configuration register */ -#define USB_CID REG32(((USBFS) + 0x003CU)) /*!< core id register */ -#define USB_HPTFLEN REG32(((USBFS) + 0x0100U)) /*!< host periodic transmit fifo length register */ -#define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x))) /*!< device in endpoint transmit fifo length register */ - -#define USB_HCTL REG32(((USBFS) + 0x0400U)) /*!< host control register */ -#define USB_HFT REG32(((USBFS) + 0x0404U)) /*!< host frame interval register */ -#define USB_HFINFR REG32(((USBFS) + 0x0408U)) /*!< host frame information remaining register */ -#define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U)) /*!< host periodic transmit fifo/queue status register */ -#define USB_HACHINT REG32(((USBFS) + 0x0414U)) /*!< host all channels interrupt register */ -#define USB_HACHINTEN REG32(((USBFS) + 0x0418U)) /*!< host all channels interrupt enable register */ -#define USB_HPCS REG32(((USBFS) + 0x0440U)) /*!< host port control and status register */ -#define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ -#define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ -#define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ -#define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ - -#define USB_DCFG REG32(((USBFS) + 0x0800U)) /*!< device configuration register */ -#define USB_DCTL REG32(((USBFS) + 0x0804U)) /*!< device control register */ -#define USB_DSTAT REG32(((USBFS) + 0x0808U)) /*!< device status register */ -#define USB_DIEPINTEN REG32(((USBFS) + 0x0810U)) /*!< device in endpoint common interrupt enable register */ -#define USB_DOEPINTEN REG32(((USBFS) + 0x0814U)) /*!< device out endpoint common interrupt enable register */ -#define USB_DAEPINT REG32(((USBFS) + 0x0818U)) /*!< device all endpoints interrupt register */ -#define USB_DAEPINTEN REG32(((USBFS) + 0x081CU)) /*!< device all endpoints interrupt enable register */ -#define USB_DVBUSDT REG32(((USBFS) + 0x0828U)) /*!< device vbus discharge time register */ -#define USB_DVBUSPT REG32(((USBFS) + 0x082CU)) /*!< device vbus pulsing time register */ -#define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U)) /*!< device in endpoint fifo empty interrupt enable register */ -#define USB_DEP1INT REG32(((USBFS) + 0x0838U)) /*!< device endpoint 1 interrupt register */ -#define USB_DEP1INTEN REG32(((USBFS) + 0x083CU)) /*!< device endpoint 1 interrupt enable register */ -#define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U)) /*!< device in endpoint 1 interrupt enable register */ -#define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U)) /*!< device out endpoint 1 interrupt enable register */ -#define USB_DIEP0CTL REG32(((USBFS) + 0x0900U)) /*!< device in endpoint 0 control register */ -#define USB_DIEP0LEN REG32(((USBFS) + 0x0910U)) /*!< device in endpoint 0 transfer length register */ -#define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U)) /*!< device out endpoint 0 control register */ -#define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U)) /*!< device out endpoint 0 transfer length register */ -#define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x))) /*!< device in endpoint-x control register */ -#define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x))) /*!< device out endpoint-x control register */ -#define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x))) /*!< device in endpoint-x interrupt flag register */ -#define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x))) /*!< device out endpoint-x interrupt flag register */ -#define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x))) /*!< device in endpoint-x transfer length register */ -#define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x))) /*!< device out endpoint-x transfer length register */ -#define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x))) /*!< device in endpoint-x transmit fifo status register */ - -#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U)) /*!< power and clock register */ - -#define USB_FIFO(x) (®32(((USBFS) + LOCATE_FIFO(x)))) /*!< fifo memory */ - -/* global OTG control and status register bits definitions */ -#define GOTGCS_BSV BIT(19) /*!< B-Session valid */ -#define GOTGCS_ASV BIT(18) /*!< A-session valid */ -#define GOTGCS_DI BIT(17) /*!< debounce interval */ -#define GOTGCS_IDPS BIT(16) /*!< id pin status */ -#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ -#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ -#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ -#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ -#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ -#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ - -/* global OTG interrupt flag register bits definitions */ -#define GOTGINTF_DF BIT(19) /*!< debounce finish */ -#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ -#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ -#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ -#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ -#define GOTGINTF_SESEND BIT(2) /*!< session end */ - -/* global AHB control and status register bits definitions */ -#define GAHBCS_PTXFTH BIT(8) /*!< periodic tx fifo threshold */ -#define GAHBCS_TXFTH BIT(7) /*!< tx fifo threshold */ -#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ - -/* global USB control and status register bits definitions */ -#define GUSBCS_FDM BIT(30) /*!< force device mode */ -#define GUSBCS_FHM BIT(29) /*!< force host mode */ -#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ -#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ -#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ -#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ - -/* global reset control register bits definitions */ -#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx fifo number */ -#define GRSTCTL_TXFF BIT(5) /*!< tx fifo flush */ -#define GRSTCTL_RXFF BIT(4) /*!< rx fifo flush */ -#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ -#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ -#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ - -/* global interrupt flag register bits definitions */ -#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ -#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ -#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ -#define GINTF_IDPSC BIT(28) /*!< id pin status change */ -#define GINTF_PTXFEIF BIT(26) /*!< periodic tx fifo empty interrupt flag */ -#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ -#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ -#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ -#define GINTF_ISOONCIF BIT(21) /*!< isochronous out transfer not complete interrupt flag */ -#define GINTF_ISOINCIF BIT(20) /*!< isochronous in transfer not complete interrupt flag */ -#define GINTF_OEPIF BIT(19) /*!< out endpoint interrupt flag */ -#define GINTF_IEPIF BIT(18) /*!< in endpoint interrupt flag */ -#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ -#define GINTF_ISOOPDIF BIT(14) /*!< isochronous out packet dropped interrupt flag */ -#define GINTF_ENUMF BIT(13) /*!< enumeration finished */ -#define GINTF_RST BIT(12) /*!< USB reset */ -#define GINTF_SP BIT(11) /*!< USB suspend */ -#define GINTF_ESP BIT(10) /*!< early suspend */ -#define GINTF_GONAK BIT(7) /*!< global out NAK effective */ -#define GINTF_GNPINAK BIT(6) /*!< global in non-periodic NAK effective */ -#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx fifo empty interrupt flag */ -#define GINTF_RXFNEIF BIT(4) /*!< rx fifo non-empty interrupt flag */ -#define GINTF_SOF BIT(3) /*!< start of frame */ -#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ -#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ -#define GINTF_COPM BIT(0) /*!< current operation mode */ - -/* global interrupt enable register bits definitions */ -#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ -#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ -#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ -#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ -#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx fifo empty interrupt enable */ -#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ -#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ -#define GINTEN_PXNCIE BIT(21) /*!< periodic transfer not complete interrupt enable */ -#define GINTEN_ISOONCIE BIT(21) /*!< isochronous out transfer not complete interrupt enable */ -#define GINTEN_ISOINCIE BIT(20) /*!< isochronous in transfer not complete interrupt enable */ -#define GINTEN_OEPIE BIT(19) /*!< out endpoints interrupt enable */ -#define GINTEN_IEPIE BIT(18) /*!< in endpoints interrupt enable */ -#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ -#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous out packet dropped interrupt enable */ -#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ -#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ -#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ -#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ -#define GINTEN_GONAKIE BIT(7) /*!< global out NAK effective interrupt enable */ -#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic in NAK effective interrupt enable */ -#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic tx fifo empty interrupt enable */ -#define GINTEN_RXFNEIE BIT(4) /*!< receive fifo non-empty interrupt enable */ -#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ -#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ -#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ - -/* global receive status read and pop register bits definitions */ -#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ -#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ - -/* global receive fifo length register bits definitions */ -#define GRFLEN_RXFD BITS(0, 15) /*!< rx fifo depth */ - -/* host non-periodic transmit fifo length register bits definitions */ -#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic tx fifo depth */ -#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic tx RAM start address */ - -/* IN endpoint 0 transmit fifo length register bits definitions */ -#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< in endpoint 0 tx fifo depth */ -#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< in endpoint 0 tx RAM start address */ - -/* host non-periodic transmit fifo/queue status register bits definitions */ -#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic tx request queue */ -#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic tx request queue space */ -#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic tx fifo space */ -#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ -#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* global core configuration register bits definitions */ -#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ -#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ -#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ -#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ -#define GCCFG_PWRON BIT(16) /*!< power on */ - -/* core ID register bits definitions */ -#define CID_CID BITS(0, 31) /*!< core ID */ - -/* host periodic transmit fifo length register bits definitions */ -#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic tx fifo depth */ -#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic tx RAM start address */ - -/* device in endpoint transmit fifo length register bits definitions */ -#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< in endpoint tx fifo x depth */ -#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< in endpoint fifox tx x RAM start address */ - -/* host control register bits definitions */ -#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ - -/* host frame interval register bits definitions */ -#define HFT_FRI BITS(0, 15) /*!< frame interval */ - -/* host frame information remaining register bits definitions */ -#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ -#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ - -/* host periodic transmit fifo/queue status register bits definitions */ -#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic tx request queue */ -#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic tx request queue space */ -#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic tx fifo space */ -#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ -#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ -#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* host all channels interrupt register bits definitions */ -#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ - -/* host all channels interrupt enable register bits definitions */ -#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ - -/* host port control and status register bits definitions */ -#define HPCS_PS BITS(17, 18) /*!< port speed */ -#define HPCS_PP BIT(12) /*!< port power */ -#define HPCS_PLST BITS(10, 11) /*!< port line status */ -#define HPCS_PRST BIT(8) /*!< port reset */ -#define HPCS_PSP BIT(7) /*!< port suspend */ -#define HPCS_PREM BIT(6) /*!< port resume */ -#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ -#define HPCS_PE BIT(2) /*!< port enable */ -#define HPCS_PCD BIT(1) /*!< port connect detected */ -#define HPCS_PCST BIT(0) /*!< port connect status */ - -/* host channel-x control register bits definitions */ -#define HCHCTL_CEN BIT(31) /*!< channel enable */ -#define HCHCTL_CDIS BIT(30) /*!< channel disable */ -#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ -#define HCHCTL_DAR BITS(22, 28) /*!< device address */ -#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ -#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define HCHCTL_LSD BIT(17) /*!< low-speed device */ -#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ -#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ -#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* host channel-x interrupt flag register bits definitions */ -#define HCHINTF_DTER BIT(10) /*!< data toggle error */ -#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ -#define HCHINTF_BBER BIT(8) /*!< babble error */ -#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ -#define HCHINTF_NYET BIT(6) /*!< NYET */ -#define HCHINTF_ACK BIT(5) /*!< ACK */ -#define HCHINTF_NAK BIT(4) /*!< NAK */ -#define HCHINTF_STALL BIT(3) /*!< STALL */ -#define HCHINTF_CH BIT(1) /*!< channel halted */ -#define HCHINTF_TF BIT(0) /*!< transfer finished */ - -/* host channel-x interrupt enable register bits definitions */ -#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ -#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ -#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ -#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ -#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ -#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ -#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ -#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ -#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ -#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ - -/* host channel-x transfer length register bits definitions */ -#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ -#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ -#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device control and status registers */ -/* device configuration registers bits definitions */ -#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ -#define DCFG_DAR BITS(4, 10) /*!< device address */ -#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status out handshake */ -#define DCFG_DS BITS(0, 1) /*!< device speed */ - -/* device control registers bits definitions */ -#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ -#define DCTL_CGONAK BIT(10) /*!< clear global out NAK */ -#define DCTL_SGONAK BIT(9) /*!< set global out NAK */ -#define DCTL_CGINAK BIT(8) /*!< clear global in NAK */ -#define DCTL_SGINAK BIT(7) /*!< set global in NAK */ -#define DCTL_GONS BIT(3) /*!< global out NAK status */ -#define DCTL_GINS BIT(2) /*!< global in NAK status */ -#define DCTL_SD BIT(1) /*!< soft disconnect */ -#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ - -/* device status registers bits definitions */ -#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ -#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ -#define DSTAT_SPST BIT(0) /*!< suspend status */ - -/* device in endpoint common interrupt enable registers bits definitions */ -#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit fifo empty interrupt enable bit */ -#define DIEPINTEN_IEPNEEN BIT(6) /*!< in endpoint NAK effective interrupt enable bit */ -#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint tx fifo underrun interrupt enable bit */ -#define DIEPINTEN_CITOEN BIT(3) /*!< control in timeout interrupt enable bit */ -#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device out endpoint common interrupt enable registers bits definitions */ -#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back setup packets interrupt enable bit */ -#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint rx fifo overrun interrupt enable bit */ -#define DOEPINTEN_STPFEN BIT(3) /*!< fifo phase finished interrupt enable bit */ -#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device all endpoints interrupt registers bits definitions */ -#define DAEPINT_OEPITB BITS(16, 21) /*!< device all out endpoint interrupt bits */ -#define DAEPINT_IEPITB BITS(0, 5) /*!< device all in endpoint interrupt bits */ - -/* device all endpoints interrupt enable registers bits definitions */ -#define DAEPINTEN_OEPIE BITS(16, 21) /*!< out endpoint interrupt enable */ -#define DAEPINTEN_IEPIE BITS(0, 3) /*!< in endpoint interrupt enable */ - -/* device Vbus discharge time registers bits definitions */ -#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ - -/* device Vbus pulsing time registers bits definitions */ -#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ - -/* device IN endpoint FIFO empty interrupt enable register bits definitions */ -#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< in endpoint tx FIFO empty interrupt enable bits */ - -/* device endpoint 0 control register bits definitions */ -#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ - -/* device endpoint x control register bits definitions */ -#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* device in endpoint-x interrupt flag register bits definitions */ -#define DIEPINTF_TXFE BIT(7) /*!< transmit fifo empty */ -#define DIEPINTF_IEPNE BIT(6) /*!< in endpoint NAK effective */ -#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint tx fifo underrun */ -#define DIEPINTF_CITO BIT(3) /*!< control in Timeout interrupt */ -#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DIEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device out endpoint-x interrupt flag register bits definitions */ -#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back setup packets */ -#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint rx fifo overrun */ -#define DOEPINTF_STPF BIT(3) /*!< setup phase finished */ -#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DOEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device in endpoint 0 transfer length register bits definitions */ -#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ -#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device out endpoint 0 transfer length register bits definitions */ -#define DOEP0LEN_STPCNT BITS(29, 30) /*!< setup packet count */ -#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ -#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device out endpoint-x transfer length register bits definitions */ -#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ -#define DOEPLEN_STPCNT BITS(29, 30) /*!< setup packet count */ -#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ -#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device in endpoint-x transmit fifo status register bits definitions */ -#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< in endpoint¡¯s tx fifo space remaining */ - -/* USB power and clock registers bits definition */ -#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ -#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ - -/* register options defines */ -#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ - -#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ -#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ -#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ - -#define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */ - -#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U) /*!< tx fifo half empty */ -#define TXFIFO_EMPTY GAHBCS_TFEL(1U) /*!< tx fifo completely empty */ - -#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ - -#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ -#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ -#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ -#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ -#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ - -#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ - -#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ -#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ -#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ -#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ - -#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ - -#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ -#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ -#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ -#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ - -/* endpoints address */ - -/* first bit is direction(0 for Rx and 1 for Tx) */ -#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */ -#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */ -#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */ -#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */ -#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */ -#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */ -#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */ -#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */ - -/* enable global interrupt */ -#define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN) - -/* disable global interrupt */ -#define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN) - -/* get current operation mode */ -#define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM) - -/* read global interrupt flag */ -#define USB_CORE_INTR_READ(x) \ -do { \ - uint32_t global_intf = USB_GINTF; \ - (x) = global_intf & USB_GINTEN; \ -} while(0) - -/* read global interrupt flag */ -#define USB_DAOEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t out_ep_intb = DAEPINT_OEPITB; \ - (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ -} while(0) - -/* read out endpoint-x interrupt flag */ -#define USB_DOEP_INTR_READ(x, EpID) \ -do { \ - uint32_t out_epintf = USB_DOEPxINTF(EpID); \ - (x) = out_epintf & USB_DOEPINTEN; \ -} while(0) - -/* read all in endpoint interrupt flag */ -#define USB_DAIEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t in_ep_intb = DAEPINT_IEPITB; \ - (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ -} while(0) - - -/* read in endpoint-x interrupt flag */ -#define USB_DIEP_INTR_READ(x, EpID) \ -do { \ - uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \ - uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \ - uint32_t dev_inep_inten = USB_DIEPINTEN; \ - (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \ -} while(0) - -/* generate remote wakup signal */ -#define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP) - -/* no remote wakup signal generate */ -#define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP) - -/* generate soft disconnect */ -#define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD) - -/* no soft disconnect generate */ -#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD) - -/* set device address */ -#define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U) - -/* check whether frame is even */ -#define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U)) - -/* read port status */ -#define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC)) - -/* usb clock initialize */ -#define USB_FSLSCLOCK_INIT(ClockFreq) \ -do { \ - USB_HCTL &= ~HCTL_CLKSEL; \ - USB_HCTL |= ClockFreq; \ -} while(0) - -/* get usb current speed */ -#define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17) - -/* get usb current frame */ -#define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU) - -#endif /* USB_REGS_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h deleted file mode 100644 index d82cb74f85..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h +++ /dev/null @@ -1,216 +0,0 @@ -/*! - \file usb_std.h - \brief USB 2.0 standard defines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_STD_H -#define USB_STD_H - -#include "usb_conf.h" - -/* constants definitions */ -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ -#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */ -#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */ -#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */ -#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ - -/* bit 7 of bmRequestType: data phase transfer direction */ -#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */ -#define USB_DIR_OUT 0x00U /*!< USB transfer out direction */ -#define USB_DIR_IN 0x80U /*!< USB transfer in direction */ - -/* bit 6..5 of bmRequestType: request type */ -#define USB_STANDARD_REQ 0x00U /*!< USB standard request */ -#define USB_CLASS_REQ 0x20U /*!< USB class request */ -#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */ -#define USB_REQ_MASK 0x60U /*!< USB request mask */ - -/* bit 4..0 of bmRequestType: recipient type */ -#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */ -#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/ -#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/ -#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/ - -/* bRequest value */ -#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/ -#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/ -#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/ -#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/ -#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/ -#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/ -#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/ -#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/ -#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/ -#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/ -#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/ - -/* descriptor types of usb specifications */ -#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/ -#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/ -#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/ -#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/ -#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/ -#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/ - -#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/ -#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/ - -#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/ -#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/ -#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/ -#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/ - -/* descriptor type and descriptor index */ -/* use the following values when USB host need to get descriptor */ -#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */ -#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */ -#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */ -#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */ -#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */ -#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */ -#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */ -#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */ -#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */ -#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */ - -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -/* supported classes */ -#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/ -#define USB_HID_CLASS 0x03U /*!< USB HID class*/ - -/* interface descriptor field values for hid boot protocol */ -#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/ -#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/ -#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/ - -/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec - standard request with no data stage timeout : 50ms */ -#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ -#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ - -#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \ - + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */ - -#pragma pack(1) - -typedef union -{ - uint8_t data[8]; - - struct _setup_packet_struct - { - uint8_t bmRequestType; /*!< type of request */ - uint8_t bRequest; /*!< request of setup packet */ - uint16_t wValue; /*!< value of setup packet */ - uint16_t wIndex; /*!< index of setup packet */ - uint16_t wLength; /*!< length of setup packet */ - } b; -}usb_setup_union; - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an interrupt or isochrnous type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -#endif /* USB_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h deleted file mode 100644 index 637f1b5654..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h +++ /dev/null @@ -1,81 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device mode core driver header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usb_core.h" -#include "usbd_std.h" - -/* constants definitions */ -/* device status */ -#define USB_STATUS_DEFAULT 1U /* default status */ -#define USB_STATUS_ADDRESSED 2U /* addressed status */ -#define USB_STATUS_CONFIGURED 3U /* configured status */ -#define USB_STATUS_SUSPENDED 4U /* suspended status */ - -/* function declarations */ -/* initailizes the USB device-mode handler stack */ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* endpoint initialization */ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc); -/* endpoint deinitialize */ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); -/* transmit data on the control channel */ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* receive data on the control channel */ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* transmit status on the control channel */ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev); -/* receive status on the control channel */ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev); -/* set an endpoint to stall status */ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* flushes the fifos */ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* get the received data length */ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h deleted file mode 100644 index 89f791d8d8..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h +++ /dev/null @@ -1,57 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device mode interrupt handler header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" - -/* constants definitions */ -typedef struct -{ - uint8_t (*SOF) (usb_core_handle_struct *pudev); -}usbd_int_cb_struct; - -extern usbd_int_cb_struct *usbd_int_fops; - -/* function declaration */ -/* USB device-mode interrupts global service routine handler */ -uint32_t usbd_isr (usb_core_handle_struct *pudev); - -#endif /* USBD_INT_H */ - diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h deleted file mode 100644 index d8ad1a61db..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h +++ /dev/null @@ -1,98 +0,0 @@ -/*! - \file usbd_std.h - \brief USB 2.0 standard defines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usb_std.h" -#include "usbd_core.h" -#include "usbd_conf.h" -#include - -/* constants definitions */ -#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/ -#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/ -#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/ -#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/ -#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/ -#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/ - -#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/ -#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/ - -#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/ -#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/ -#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/ - -#define ENG_LANGID 0x0409U /*!< USB english language id*/ -#define CHN_LANGID 0x0804U /*!< USB chinese language id*/ - -#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/ - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/ -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/ - -#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/ - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (uint8_t *)&(struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -/* function declarations */ -/* USB device setup transaction*/ -usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev); -/* USB device out transaction*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device in transaction*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device enum error handle*/ -void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h deleted file mode 100644 index 8137444b50..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h +++ /dev/null @@ -1,310 +0,0 @@ -/*! - \file usbh_core.h - \brief header file for usbh_core.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_CORE_H -#define USBH_CORE_H - -#include "usbh_conf.h" -#include "usb_std.h" -#include "usb_core.h" - -/* constants definitions */ -#define MSC_CLASS 0x08 /*!< the MSC class define */ -#define HID_CLASS 0x03 /*!< the HID class define */ -#define MSC_PROTOCOL 0x50 /*!< the MSC protocal define */ -#define CBI_PROTOCOL 0x01 /*!< the CBI protocal define */ - -#define USBH_DEVICE_ADDRESS_DEFAULT 0U /*!< the default device address define */ -#define USBH_DEVICE_ADDRESS 1U /*!< the device address define */ -#define USBH_MAX_ERROR_COUNT 2U /*!< the max error count define */ - -#define HOST_USER_SELECT_CONFIGURATION 1U /*!< the user select configuration define */ -#define HOST_USER_CLASS_ACTIVE 2U /*!< the user class active define */ -#define HOST_USER_CLASS_SELECTED 3U /*!< the user class selected define */ -#define HOST_USER_CONNECTION 4U /*!< the user connecttion define */ -#define HOST_USER_DISCONNECTION 5U /*!< the user disconnection define */ -#define HOST_USER_UNRECOVERED_ERROR 6U /*!< the user unrecovered error define */ - -#define MAX_USBH_STATE_STACK_DEEP 4 /*!< the max state stack deep define */ -#define MAX_USBH_STATE_TABLE_NUM 10U /*!< the max state table number */ - -#define HOST_FSM_ID 0U /*!< the host state table id */ -#define ENUM_FSM_ID 1U /*!< the enum state table id */ -#define CMD_FSM_ID 2U /*!< the cmd state table id */ -#define CTRL_FSM_ID 3U /*!< the ctrl state table id */ -#define CLASS_REQ_FSM_ID 4U /*!< the class req state table id */ -#define CLASS_FSM_ID 5U /*!< the class state table id */ - -#define UP_STATE 100U /*!< up state define */ -#define GO_TO_UP_STATE_EVENT 100U /*!< go to up state event define */ - -#define HOST_HANDLE_TABLE_SIZE 9U /*!< the host handle table size define */ -/* the enum of host state */ -typedef enum -{ - HOST_IDLE = 0, /* the host idle state definition */ - HOST_DEV_ATTACHED, /* the host device attached state definition */ - HOST_DEV_DETACHED, /* the host device detached state definition */ - HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */ - HOST_ENUMERATION, /* the host enumeration state definition */ - HOST_CLASS_REQUEST, /* the host class request state definition */ - HOST_CLASS, /* the host class state definition */ - HOST_USER_INPUT, /* the host user input state definition */ - HOST_SUSPENDED, /* the host suspended state definition */ - HOST_ERROR /* the host error state definition */ -}host_state_enum; - -/* the enum of host event */ -typedef enum -{ - HOST_EVENT_ATTACHED = 0, /* the host attached event */ - HOST_EVENT_ENUM, /* the host enum event */ - HOST_EVENT_USER_INPUT, /* the host user input event */ - HOST_EVENT_CLASS_REQ, /* the host class request event */ - HOST_EVENT_CLASS, /* the host class event */ - HOST_EVENT_ERROR, /* the host error event */ - HOST_EVENT_DEV_DETACHED, /* the host device detached event */ - HOST_EVENT_IDLE /* the host idle event */ -}host_event_enum; - -/* the enum of enum state */ -typedef enum -{ - ENUM_IDLE = 0, /* the enum idle state definition */ - ENUM_SET_ADDR, /* the enum set address state definition */ - ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */ - ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */ - ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */ - ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */ - ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */ - ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */ - ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */ - ENUM_DEV_CONFIGURED /* the enum device configuration state definition */ -}enum_state_enum; - -/* the enum of ctrl state */ -typedef enum -{ - CTRL_IDLE = 0, /* the ctrl idle state definition */ - CTRL_SETUP, /* the ctrl setup state definition */ - CTRL_DATA, /* the ctrl data state definition */ - CTRL_STATUS, /* the ctrl status state definition */ - CTRL_ERROR, /* the ctrl error state definition */ - CTRL_STALLED, /* the ctrl stalled state definition */ - CTRL_COMPLETE /* the ctrl complete state definition */ -}ctrl_state_enum; - -/* the enum of host status */ -typedef enum -{ - USBH_OK = 0, /* the usbh ok status definition */ - USBH_BUSY, /* the usbh busy status definition */ - USBH_FAIL, /* the usbh fail status definition */ - USBH_NOT_SUPPORTED, /* the usbh not supported status definition */ - USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */ - USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */ - USBH_APPLY_DEINIT /* the usbh apply deinit status definition */ -}usbh_status_enum; - -/* the state of user action */ -typedef enum -{ - USBH_USER_NO_RESP = 0, /* the user no response */ - USBH_USER_RESP_OK = 1, /* the user response ok */ -}usbh_user_status_enum; - -/* control transfer information */ -typedef struct -{ - uint8_t hc_in_num; /* the host in channel number */ - uint8_t hc_out_num; /* the host out channel number */ - uint8_t ep0_size; /* the endpoint 0 max packet size */ - uint8_t error_count; /* the error count */ - uint16_t length; /* the length */ - uint16_t timer; /* the timer */ - uint8_t *buff; /* the buffer */ - usb_setup_union setup; /* the setup packet */ -}usbh_ctrl_struct; - -/* device property */ -typedef struct -{ - uint8_t address; /* the device address */ - uint8_t speed; /* the device speed */ - usb_descriptor_device_struct dev_desc; /* the device descripter */ - usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */ - usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */ - usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */ -}usbh_device_struct; - -/* user callbacks */ -typedef struct -{ - void (*init) (void); /* the user callback init function */ - void (*deinit) (void); /* the user callback deinit function */ - void (*device_connected) (void); /* the user callback device connected function */ - void (*device_reset) (void); /* the user callback device reset function */ - void (*device_disconnected) (void); /* the user callback device disconnected function */ - void (*over_current_detected) (void); /* the user callback over current detected function */ - void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */ - void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */ - void (*device_address_set) (void); /* the user callback set device address function */ - - void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct *ep_desc); - /* the configuration descripter available function */ - - void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */ - void (*product_string) (void *prod_string); /* the user callback product string function */ - void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */ - void (*enumeration_finish) (void); /* the user callback enumeration finish function */ - usbh_user_status_enum (*user_input) (void); /* the user callback user input function */ - int (*user_application) (usb_core_handle_struct *pudev, uint8_t id); - /* the user callback user appliction function */ - void (*device_not_supported) (void); /* the user callback device not supported function */ - void (*unrecovered_error) (void); /* the user callback unrecovered error function */ -}usbh_user_callback_struct; - -/* the backup state struct */ -typedef struct -{ - host_state_enum host_backup_state; /* the host backup state */ - enum_state_enum enum_backup_state; /* the enum backup state */ - ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */ - uint8_t class_req_backup_state; /* the class request backup state */ - uint8_t class_backup_state; /* the class backup state */ -} backup_state_struct; - -/* host information */ -typedef struct -{ - backup_state_struct usbh_backup_state; /* the usbh backup state variable */ - usbh_ctrl_struct control; /* the control struct variable */ - usbh_device_struct device; /* the device struct variable */ - usbh_user_callback_struct *usr_cb; /* the user callback function */ - usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */ - void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */ -}usbh_host_struct; - -/* the action function definition */ -typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate); - -/* the state table struct */ -typedef struct -{ - uint8_t cur_state; /* the current state */ - uint8_t cur_event; /* the current event */ - uint8_t next_state; /* the next state */ - ACT_FUN event_action_fun; /* the event action function entry */ -} state_table_struct; - -/* the state stack struct */ -typedef struct -{ - uint8_t state; /* the state in state stack */ - state_table_struct* table; /* the table in state stack */ - uint8_t table_size; /* the table size in state stack */ -} usbh_state_stack_struct; - -/* the state regist table struct */ -typedef struct -{ - uint8_t id; /* the id of the state table */ - state_table_struct* table; /* the table entry to regist */ - uint8_t table_size; /* the table size to regist */ -} usbh_state_regist_table_struct; - -/* the state handle struct */ -typedef struct -{ - uint8_t usbh_current_state; /* current state */ - uint8_t usbh_current_state_table_size; /* current state table size */ - state_table_struct* usbh_current_state_table; /* current state table */ - - usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */ - int8_t usbh_current_state_stack_top; /* the current state top */ - - usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */ - uint8_t usbh_regist_state_table_num; /* the number of regist state table */ -} usbh_state_handle_struct; - -/* function declarations */ -/* the host core driver function */ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* initialize the host portion of the driver */ -uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* check if the device is connected */ -uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev); -/* this function returns the last URBstate */ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* this function returns the last URBstate */ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* de-initialize host */ -usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate); - -/* the state core driver function */ -/* state core driver init */ -void scd_init (usbh_state_handle_struct* pustate); -/* state core driver table regist */ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size); -/* state core driver begin */ -void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id); -/* state core driver move state */ -void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state); -/* state core driver event handle */ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state); -/* state core driver table push */ -void scd_table_push (usbh_state_handle_struct* pustate); -/* state core driver table pop */ -void scd_table_pop (usbh_state_handle_struct* pustate); -/* the function is only used to state move */ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* the function to the up state */ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -#endif /* USBH_CORE_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h deleted file mode 100644 index b9cf7c5f97..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h +++ /dev/null @@ -1,73 +0,0 @@ -/*! - \file usbh_ctrl.h - \brief header file for usbh_ctrl.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_CTRL_H -#define USBH_CTRL_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -/* constants definitions */ -/* the enum of CTRL event */ -typedef enum -{ - CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ - CTRL_EVENT_SETUP, /* the ctrl setup event */ - CTRL_EVENT_DATA, /* the ctrl data event */ - CTRL_EVENT_STATUS, /* the ctrl status event */ - CTRL_EVENT_COMPLETE, /* the ctrl complete event */ - CTRL_EVENT_ERROR, /* the ctrl error event */ - CTRL_EVENT_STALLED, /* the ctrl stalled event */ -}ctrl_event_enum; - -#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ - -extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; -extern uint8_t ctrl_polling_handle_flag; - -/* function declarations */ -/* the polling function of control transfer state handle */ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* send datas from the host channel */ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); -/* send the setup packet to the device */ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); -/* this function prepare a hc and start a transfer */ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); - -#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h deleted file mode 100644 index d387f15b76..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h +++ /dev/null @@ -1,73 +0,0 @@ -/*! - \file usbh_hcs.h - \brief header file for usbh_hcs.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_HCS_H -#define USBH_HCS_H - -#include "usbh_core.h" - -/* constants definitions */ -#define HC_MAX 8U -#define HC_OK 0x0000U -#define HC_USED 0x8000U -#define HC_ERROR 0xFFFFU -#define HC_USED_MASK 0x7FFFU - -/* function declarations */ -/* allocate a new channel for the pipe */ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* free all usb host channel */ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); -/* free the usb host channel */ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); -/* open a channel */ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); -/* modify a channel */ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); - -#endif /* USBH_HCS_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h deleted file mode 100644 index 468ebc37d7..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h +++ /dev/null @@ -1,58 +0,0 @@ -/*! - \file usbh_int.h - \brief USB host mode interrupt handler header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_INT_H -#define USBH_INT_H - -#include "usb_core.h" - -/* constants definitions */ -typedef struct -{ - uint8_t (*sof) (usb_core_handle_struct *pudev); - uint8_t (*device_connected) (usb_core_handle_struct *pudev); - uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); -}usbh_hcd_int_cb_struct; - -extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; - -/* function declarations */ -/* handle global host interrupt */ -uint32_t usbh_isr (usb_core_handle_struct *pudev); - -#endif /* USBH_INT_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h deleted file mode 100644 index c4bc6cd91b..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h +++ /dev/null @@ -1,101 +0,0 @@ -/*! - \file usbh_std.h - \brief header file for usbh_std.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_STD_H -#define USBH_STD_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -/* constants definitions */ -typedef enum -{ - ENUN_EVENT_IDLE = 0, /* the enum idle event */ - ENUM_EVENT_SET_ADDR, /* the enum set address event */ - ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */ - ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */ - ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */ - ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */ - ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */ - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */ - ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */ - ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */ -}enum_event_enum; -/* standard feature selector for clear feature command */ -#define FEATURE_SELECTOR_ENDPOINT 0x00U -#define FEATURE_SELECTOR_DEVICE 0x01U - -#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */ -#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */ - -extern uint8_t usbh_cfg_desc[512]; -extern uint8_t enum_polling_handle_flag; -extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]; - -/* function declarations */ -/* the polling function of enumeration state */ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* get descriptor in usb host enumeration stage */ -void usbh_enum_desc_get (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len); -/* set address in usb host enumeration stage */ -void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address); -/* set configuration in usb host enumeration stage */ -void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx); -/* parse the device descriptor */ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len); -/* parse the configuration descriptor */ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len); -/* parse the interface descriptor */ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf); -/* parse the endpoint descriptor */ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf); -/* parse the string descriptor */ -void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); -/* get the next descriptor header */ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr); - -#endif /* USBH_STD_H */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c deleted file mode 100644 index a2fa307efb..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c +++ /dev/null @@ -1,974 +0,0 @@ -/*! - \file usb_core.c - \brief USB core driver which can operate in host-mode and device-mode - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usb_core.h" - -static void usb_commonint_enable (usb_core_handle_struct *pudev); -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev); - -/*! - \brief enable the commmon interrupts which are used in both device and host modes - \param[in] pudev: pointer to selected usb device - \param[out] none - \retval none -*/ -static void usb_commonint_enable (usb_core_handle_struct *pudev) -{ -#ifndef USE_OTG_MODE - - /* clear any pending USB interrupts */ - USB_GOTGINTF = 0xFFFFFFFFU; - -#endif /* USE_OTG_MODE */ - - USB_GINTF = 0xBFFFFFFF; - - /* enable the usb wakeup and suspend interrupts */ - USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; - -#ifdef USE_OTG_MODE - - /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */ - USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; - -#endif /* USE_OTG_MODE */ -} - -/*! - \brief soft reset of the OTG_FS core - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - /* enable core soft reset */ - USB_GRSTCTL |= GRSTCTL_CSRST; - - /* wait for the core to be soft reset */ - do { - if (++count > 200000U) { - break; - } - } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST)); - - /* wait for addtional 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief write a packet into the tx fifo associated with the endpoint - \param[in] src: pointer to source buffer - \param[in] chep_num: channel or endpoint identifier which is in (0..3) - \param[in] len: packet length - \param[out] none - \retval operation status -*/ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len) -{ - uint32_t count32b = 0U, i = 0U; - __IO uint32_t *fifo = USB_FIFO(chep_num); - - count32b = (len + 3U) / 4U; - - for (i = 0U; i < count32b; i++) { - *fifo = *((__packed uint32_t *)src); - - src += 4U; - } - - return USB_OK; -} - -/*! - \brief read a packet from the rx fifo associated with the endpoint - \param[in] dest: pointer to destination buffer - \param[in] len: packet length - \param[out] none - \retval void type pointer -*/ -void *usb_fifo_read (uint8_t *dest, uint16_t len) -{ - uint32_t i = 0U; - uint32_t count32b = (len + 3U) / 4U; - - __IO uint32_t *fifo = USB_FIFO(0U); - - for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = *fifo; - - dest += 4U; - } - - return ((void *)dest); -} - -/*! - \brief initialize core parameters - \param[in] pudev: pointer to usb device - \param[in] core_id: USB core id - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* at startup the core is in FS mode */ - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - /* initialize the core parameters */ - if (USB_FS_CORE_ID == core_id) { - - pudev->cfg.core_id = USB_FS_CORE_ID; - - /* set the host channel numbers */ - pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT; - - /* set the device endpoint numbers */ - pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT; - - /* fifo size is in terms of DWORD */ - pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN; - - /* OTG_FS core use embedded physical layer */ - pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; - - #ifdef USBFS_SOF_OUTPUT_ENABLED - pudev->cfg.sof_output = 1U; - #endif /* USBFS_SOF_OUTPUT_ENABLED */ - - #ifdef USBFS_LOW_PWR_MGMT_SUPPORT - pudev->cfg.low_power = 1U; - #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ - } - - return USB_OK; -} - -/*! - \brief initializes the USB controller registers and - prepares the core device mode or host mode operation - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev) -{ - /* soft reset the core */ - usb_core_reset(pudev); - - /* active the transceiver and enable vbus sensing */ - USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - - /* set tx fifo empty level to half empty mode */ - USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; - -#ifndef VBUS_SENSING_ENABLED - USB_GCCFG |= GCCFG_VBUSIG; -#endif /* VBUS_SENSING_ENABLED */ - - if(pudev->cfg.sof_output){ - USB_GCCFG |= GCCFG_SOFOEN; - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - -#ifdef USE_OTG_MODE - /* enable OTG features */ - USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; - USB_OTG_EnableCommonInt(pudev); - -#endif /* USE_OTG_MODE */ - - return USB_OK; -} - -/*! - \brief flush a tx fifo or all tx fifos - \param[in] pudev: pointer to usb device - \param[in] fifo_num: fifo number which is in (0..3) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num) -{ - uint32_t count = 0U; - - USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; - - /* wait for tx fifo flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_TXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief flush the entire rx fifo - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - USB_GRSTCTL = GRSTCTL_RXFF; - - /* wait for rx fifo flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_RXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief set operation mode (host or device) - \param[in] pudev: pointer to usb device - \param[in] mode: operation mode which need to set - \arg HOST_MODE - \arg DEVICE_MODE - \param[out] none - \retval operation status -*/ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) -{ - if (HOST_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FDM; - USB_GUSBCS |= GUSBCS_FHM; - } else if (DEVICE_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FHM; - USB_GUSBCS |= GUSBCS_FDM; - } else { - /* no operation */ - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(50U); - } - - return USB_OK; -} - -#ifdef USE_HOST_MODE - -/*! - \brief initializes USB core for host mode - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i = 0U; - __IO uint32_t nptxfifolen = 0U; - __IO uint32_t ptxfifolen = 0U; - -#ifdef USE_OTG_MODE - __IO uint32_t otgctl = 0; -#endif /* USE_OTG_MODE */ - - /* restart the PHY clock */ - USB_PWRCLKCTL = 0U; - - /* initialize host configuration register */ - if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ); - } else { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - - /* reset USB port */ - usb_port_reset(pudev); - - /* configure data fifo sizes */ - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set rx fifo size */ - USB_GRFLEN = USBFS_RX_FIFO_SIZE; - - /* set non-periodic tx fifo size and address */ - nptxfifolen &= ~HNPTFLEN_HNPTXRSAR; - nptxfifolen |= USBFS_RX_FIFO_SIZE; - nptxfifolen &= ~HNPTFLEN_HNPTXFD; - nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = nptxfifolen; - - /* set periodic tx fifo size and address */ - ptxfifolen &= ~HPTFLEN_HPTXFSAR; - ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; - ptxfifolen &= ~HPTFLEN_HPTXFD; - ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = ptxfifolen; - } - -#ifdef USE_OTG_MODE - - /* clear host set HNP enable bit in the USB OTG control register */ - otgctl |= GOTGCS_HHNPEN; - USB_GOTGCS &= ~otgctl; - USB_GOTGCS |= 0; - -#endif /* USE_OTG_MODE */ - - /* make sure the fifos are flushed */ - - /* flush all tx fifos in device or host mode */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush the entire rx fifo */ - usb_rxfifo_flush(pudev); - - /* clear all pending host channel interrupts */ - USB_HACHINTEN &= ~HACHINTEN_CINTEN; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxINTEN(i) = 0U; - USB_HCHxINTF(i) = 0xFFFFFFFFU; - } - -#ifndef USE_OTG_MODE - usb_vbus_drive(pudev, 1U); -#endif /* USE_OTG_MODE */ - - usb_hostint_enable(pudev); - - return USB_OK; -} - -/*! - \brief control the VBUS to power - \param[in] pudev: pointer to selected usb host - \param[in] state: VBUS state - \param[out] none - \retval none -*/ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) -{ - __IO uint32_t host_port = 0U; - - /* enable or disable the external charge pump */ - if ((void *)0 != pudev->host.vbus_drive) { - pudev->host.vbus_drive(pudev, state); - } - - /* turn on the host port power. */ - host_port = USB_PORT_READ(); - - if ((0U == (host_port & HPCS_PP)) && (1U == state)) { - host_port |= HPCS_PP; - } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) { - host_port &= ~HPCS_PP; - } else { - /* no operation */ - } - - USB_HPCS = host_port; - - if (NULL != pudev->mdelay) { - pudev->mdelay(200U); - } -} - -/*! - \brief enables the host mode interrupts - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) -{ - uint32_t gintf = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xFFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - gintf |= GINTF_RXFNEIF; - - /* enable host_mode-related interrupts */ - gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF; - - USB_GINTEN &= ~gintf; - USB_GINTEN |= gintf; - - return USB_OK; -} - -/*! - \brief reset host port - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint32_t usb_port_reset (usb_core_handle_struct *pudev) -{ - __IO uint32_t hpcs; - - hpcs = USB_PORT_READ(); - - hpcs |= HPCS_PRST; - - USB_HPCS = hpcs; - - if (NULL != pudev->mdelay) { - pudev->mdelay(100U); - } - - hpcs &= ~HPCS_PRST; - - USB_HPCS = hpcs; - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - return USB_OK; -} - -/*! - \brief initialize host channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t is_low_speed = 0U; - __IO uint32_t chinten = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* clear old interrupt conditions for this host channel */ - USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; - - /* enable channel interrupts required for this transfer */ - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ - | HCHINTEN_DTERIE | HCHINTEN_NAKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } else { - chinten |= HCHINTEN_NYETIE; - } - break; - - case USB_EPTYPE_INTR: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ - | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } - break; - - case USB_EPTYPE_ISOC: - chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; - } - break; - - default: - break; - } - - USB_HCHxINTEN((uint16_t)hc_num) = chinten; - - /* enable the top level host channel interrupt */ - USB_HACHINTEN |= 1U << hc_num; - - /* make sure host channel interrupts are enabled */ - USB_GINTEN |= GINTEN_HCIE; - - /* program the hcctlr register */ - chctl = 0U; - - if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { - is_low_speed = 1U; - } - - chctl |= (uint32_t)puhc->dev_addr << 22U; - chctl |= (uint32_t)puhc->endp_type << 18U; - chctl |= (uint32_t)puhc->endp_id << 11U; - chctl |= (uint32_t)puhc->endp_in << 15U; - chctl |= (uint32_t)is_low_speed << 17U; - chctl |= puhc->endp_mps; - - if (HCCHAR_INTR == puhc->endp_type) { - chctl |= HCHCTL_ODDFRM; - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief prepare host channel for transferring packets - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint16_t dword_len = 0U; - uint16_t packet_num = 0U; - - __IO uint32_t chxlen = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* compute the expected number of packets associated to the transfer */ - if (puhc->xfer_len > 0U) { - packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps; - - if (packet_num > HC_MAX_PACKET_COUNT) { - packet_num = HC_MAX_PACKET_COUNT; - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - } else { - packet_num = 1U; - } - - if (puhc->endp_in) { - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - - /* initialize the host channel length register */ - chxlen &= ~HCHLEN_TLEN; - chxlen |= puhc->xfer_len; - chxlen &= ~HCHLEN_PCNT; - chxlen |= (uint32_t)packet_num << 19U; - chxlen &= ~HCHLEN_DPID; - chxlen |= (uint32_t)(puhc->DPID) << 29U; - USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen; - - /* set host channel enable */ - chctl = USB_HCHxCTL((uint16_t)hc_num); - - if (1U == USB_EVEN_FRAME()) { - chctl |= HCHCTL_ODDFRM; - } else { - chctl &= ~HCHCTL_ODDFRM; - } - - chctl |= HCHCTL_CEN; - chctl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { - dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; - - switch (puhc->endp_type) { - /* non-periodic transfer */ - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - /* check if there is enough space in fifo space */ - if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - /* need to process data in non-periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_NPTXFEIE; - } - break; - - /* periodic transfer */ - case USB_EPTYPE_INTR: - case USB_EPTYPE_ISOC: - /* check if there is enough space in FIFO space */ - if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - /* need to process data in periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_PTXFEIE; - } - break; - - default: - break; - } - - /* write packet into the Tx FIFO. */ - usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); - } - - return USB_OK; -} - -/*! - \brief halt channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t endp_type = 0U; - __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num); - - chctl |= HCHCTL_CEN | HCHCTL_CDIS; - - endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U); - - /* check for space in the request queue to issue the halt. */ - if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { - if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } else { - if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief stop the USB host and clean up fifos - \param[in] none - \param[out] none - \retval none -*/ -void usb_host_stop(usb_core_handle_struct *pudev) -{ - uint32_t i; - - /* disable all host channel interrupt */ - USB_HACHINTEN = 0U; - USB_HACHINT = 0xFFFFFFFFU; - - /* flush out any leftover queued requests */ - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR; - } - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} - -#endif /* USE_HOST_MODE */ - - -#ifdef USE_DEVICE_MODE - -/* USB endpoint Tx FIFO size */ -static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = -{ - (uint16_t)TX0_FIFO_FS_SIZE, - (uint16_t)TX1_FIFO_FS_SIZE, - (uint16_t)TX2_FIFO_FS_SIZE, - (uint16_t)TX3_FIFO_FS_SIZE -}; - -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); - -/*! - \brief initialize USB core registers for device mode - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i, ram_address = 0U; - __IO uint32_t devinep0intf = USB_DIEP0TFLEN; - __IO uint32_t devinepintf = 0U; - - /* restart the phy clock (maybe don't need to...) */ - USB_PWRCLKCTL = 0U; - - /* config periodic frmae interval to default */ - USB_DCFG &= ~DCFG_EOPFT; - USB_DCFG |= FRAME_INTERVAL_80; - - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set full speed PHY */ - USB_DCFG &= ~DCFG_DS; - USB_DCFG |= USB_SPEED_INP_FULL; - - /* set rx fifo size */ - USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 0 tx fifo length and RAM address */ - devinep0intf &= ~DIEP0TFLEN_IEP0TXFD; - devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16; - devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR; - devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE; - - USB_DIEP0TFLEN = devinep0intf; - - ram_address = (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 1 to 3's tx fifo length and RAM address */ - for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { - ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; - - devinepintf &= ~DIEPTFLEN_IEPTXFD; - devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; - devinepintf &= ~DIEPTFLEN_IEPTXRSAR; - devinepintf |= ram_address; - - USB_DIEPxTFLEN(i) = devinepintf; - } - } - - /* make sure all fifos are flushed */ - - /* flush all tx fifos */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush entire rx fifo */ - usb_rxfifo_flush(pudev); - - /* clear all pending device interrupts */ - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - USB_DAEPINTEN = 0U; - - /* configure all in/out endpoints */ - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - if (USB_DIEPxCTL(i) & DEPCTL_EPEN) { - USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DIEPxCTL(i) = 0U; - } - - if (USB_DOEPxCTL(i) & DEPCTL_EPEN) { - USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DOEPxCTL(i) = 0U; - } - - /* set in/out endpoint transfer length to 0 */ - USB_DIEPxLEN(i) = 0U; - USB_DOEPxLEN(i) = 0U; - - /* clear all pending in/out endpoints interrupts */ - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - usb_devint_enable(pudev); - - return USB_OK; -} - -/*! - \brief enable the device mode interrupts - \param[in] pudev: pointer to usb device - \param[out] none - \retval status -*/ -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) -{ - uint32_t int_mask = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xBFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - int_mask = GINTEN_RXFNEIE; - - /* enable device_mode-related interrupts */ - int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ - | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \ - | GINTEN_ISOINCIE; - -#ifdef VBUS_SENSING_ENABLED - int_mask |= GINTEN_SESIE | GINTEN_OTGIE; -#endif /* VBUS_SENSING_ENABLED */ - - USB_GINTEN &= ~int_mask; - USB_GINTEN |= int_mask; - - return USB_OK; -} - -/*! - \brief configures endpoint 0 to receive setup packets - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_ep0_startout(usb_core_handle_struct *pudev) -{ - __IO uint32_t ep0len = 0U; - - /* set out endpoint 0 receive length to 24 bytes */ - ep0len &= ~DOEP0LEN_TLEN; - ep0len |= 8U * 3U; - - /* set out endpoint 0 receive length to 1 packet */ - ep0len &= ~DOEP0LEN_PCNT; - ep0len |= 1U << 19; - - /* set setup packet count to 3 */ - ep0len &= ~DOEP0LEN_STPCNT; - ep0len |= 3U << 29; - - USB_DOEPxLEN(0U) = ep0len; -} - -/*! - \brief active remote wakeup signalling - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_remotewakeup_active(usb_core_handle_struct *pudev) -{ - __IO uint32_t power_clock; - - if (pudev->dev.remote_wakeup) { - if (1U == (USB_DSTAT & DSTAT_SPST)) { - if (pudev->cfg.low_power) { - /* ungate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - - /* active remote wakeup signaling */ - USB_DCTL |= DCTL_RWKUP; - - if (pudev->mdelay != (void *)0) { - pudev->mdelay(5U); - } - - USB_DCTL &= ~DCTL_RWKUP; - } - } -} - -/*! - \brief active USB core clock - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_clock_ungate(usb_core_handle_struct *pudev) -{ - if (pudev->cfg.low_power) { - __IO uint32_t power_clock; - - if (1U == (USB_DSTAT & DSTAT_SPST)) { - /* un-gate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - } -} - -/*! - \brief stop the device and clean up fifos - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_device_stop (usb_core_handle_struct *pudev) -{ - uint32_t i; - - pudev->dev.status = 1U; - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} -#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c deleted file mode 100644 index 366b1bbb3b..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c +++ /dev/null @@ -1,503 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device mode core driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -/*! - \brief initailizes the USB device-mode handler stack - \param[in] pudev: pointer to usb device instance - \param[in] core_id: USB core ID - \param[out] none - \retval none -*/ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* select USB core */ - usb_core_select (pudev, core_id); - - pudev->dev.status = USB_STATUS_DEFAULT; - - /* disable USB global interrupt */ - USB_GLOBAL_INT_DISABLE(); - - /* init the core (common init.) */ - usb_core_init(pudev); - - /* force device mode*/ - usb_mode_set(pudev, DEVICE_MODE); - - /* set device disconnect */ - USB_SOFT_DISCONNECT_ENABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* init device */ - usb_devcore_init(pudev); - - /* set device Connect */ - USB_SOFT_DISCONNECT_DISABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* enable USB global interrupt */ - USB_GLOBAL_INT_ENABLE(); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to usb device instance - \param[in] ep_desc: pointer to usb endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc) -{ - usb_ep_struct *ep; - usb_dir_enum ep_dir; - - uint32_t devepinten = 0U; - uint32_t devepctl = 0U; - - uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU; - uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK; - uint16_t ep_mps = ep_desc->wMaxPacketSize; - - if (ep_desc->bEndpointAddress >> 7U) { - ep = &pudev->dev.in_ep[ep_num]; - - devepinten |= 1U << ep_num; - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - ep_dir = USB_TX; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepinten |= (1U << ep_num) << 16U; - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - ep_dir = USB_RX; - } - - /* if the endpoint is not active, need change the endpoint control register */ - if (!(devepctl & DEPCTL_EPACT)) { - devepctl &= ~DEPCTL_MPL; - devepctl |= ep_mps; - - devepctl &= ~DEPCTL_EPTYPE; - devepctl |= (uint32_t)ep_type << 18U; - - if (USB_TX == ep_dir) { - devepctl &= ~DIEPCTL_TXFNUM; - devepctl |= (uint32_t)ep_num << 22U; - } - - devepctl |= DEPCTL_SD0PID; - devepctl |= DEPCTL_EPACT; - } - - if (USB_TX == ep_dir) { - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else if (USB_RX == ep_dir) { - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* no operation */ - } - - ep->endp_mps = ep_mps; - ep->endp_type = ep_type; - - /* enable the interrupts for this endpoint */ - USB_DAEPINTEN |= devepinten; -} - -/*! - \brief endpoint deinitialize - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint32_t devepinten = 0U; - uint8_t ep_num = ep_addr & 0x7FU; - - if (ep_addr >> 7U) { - devepinten |= 1U << ep_num; - - USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } else { - devepinten |= (1U << ep_num) << 16U; - - USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } - - /* disable the interrupts for this endpoint */ - USB_DAEPINTEN &= ~devepinten; -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - uint32_t devepctl = 0U, devepxlen = 0U; - - ep = &pudev->dev.out_ep[ep_num]; - - /* setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - devepxlen = USB_DOEPxLEN((uint16_t)ep_num); - - devepxlen &= ~DEPLEN_TLEN; - devepxlen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - - if (0U == ep_num) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - /* configure the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; - devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps; - } - } - - USB_DOEPxLEN((uint16_t)ep_num) = devepxlen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (ep->endp_frame) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - __IO uint32_t deveplen = 0U; - - ep = &pudev->dev.in_ep[ep_num]; - - /* setup and start the transfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - deveplen = USB_DIEPxLEN((uint16_t)ep_num); - - /* clear transfer length to 0 */ - deveplen &= ~DEPLEN_TLEN; - - /* clear transfer packet to 0 */ - deveplen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set transfer packet count to 1 */ - deveplen |= 1U << 19U; - } else { - if (0U == ep_num) { - if (ep->xfer_len > ep->endp_mps) { - ep->xfer_len = ep->endp_mps; - } - - deveplen |= 1U << 19U; - } else { - deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; - } - - /* configure the transfer size and packet count as follows: - * xfersize = N * maxpacket + short_packet - * pktcnt = N + (short_packet exist ? 1 : 0) - */ - deveplen |= ep->xfer_len; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - deveplen |= DIEPLEN_MCNT & (1U << 29U); - } - } - - USB_DIEPxLEN((uint16_t)ep_num) = deveplen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - - if (USB_EPTYPE_ISOC != ep->endp_type) { - /* enable the Tx FIFO empty interrupt for this endpoint */ - if (ep->xfer_len > 0U) { - USB_DIEPFEINTEN |= 1U << ep_num; - } - } else { - usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len); - } -} - -/*! - \brief transmit data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - usbd_status_enum ret = USBD_OK; - - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_IN; - - usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len); - - return ret; -} - -/*! - \brief receive data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_OUT; - - usbd_ep_rx (pudev, 0U, pbuf, len); - - return USBD_OK; -} - -/*! - \brief transmit status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_IN; - - usbd_ep_tx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief receive status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_OUT; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief set an endpoint to STALL status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if (ep_addr >> 7U) { - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* set the endpoint disable bit */ - if (devepctl & DEPCTL_EPEN) { - devepctl |= DEPCTL_EPD; - } - - /* set the endpoint stall bit */ - devepctl |= DEPCTL_STALL; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* set the endpoint stall bit */ - USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL; - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if(ep_addr >> 7U){ - ep = &pudev->dev.in_ep[ep_num]; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* clear the in endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - /* clear the out endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } -} - -/*! - \brief flushes the fifos - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7U) { - usb_txfifo_flush(pudev, ep_addr & 0x7FU); - } else { - usb_rxfifo_flush(pudev); - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to usb device instance - \param[in] ep_num: endpoint identifier which is in (0..3) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num) -{ - return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c deleted file mode 100644 index 668ef35cd7..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c +++ /dev/null @@ -1,663 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device mode interrupt routines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_int.h" -#include "usbd_std.h" - -/* interrupt handlers */ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev); - -static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num); - -#ifdef VBUS_SENSING_ENABLED - - static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); - static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); - -#endif /* VBUS_SENSING_ENABLED */ - -static usb_speed_enum USB_SPEED[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW -}; - -static const uint8_t EP0_MAXLEN[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 -}; - -/*! - \brief USB device-mode interrupts global service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbd_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN; - - /* ensure the core is in device mode */ - if (DEVICE_MODE == USB_CURRENT_MODE_GET()) { - int_status = gintf & ginten; - - /* there are no interrupts, avoid spurious interrupt */ - if (!int_status) { - return 0U; - } - - /* OUT endpoints interrupts */ - if (int_status & GINTF_OEPIF) { - retval |= usbd_intf_outep(pudev); - } - - /* IN endpoints interrupts */ - if (int_status & GINTF_IEPIF) { - retval |= usbd_intf_inep(pudev); - } - - /* mode mismatch interrupt */ - if (int_status & GINTF_MFIF) { - /* clear interrupt */ - USB_GINTF = GINTF_MFIF; - } - - /* early suspend interrupt */ - if (int_status & GINTF_ESP) { - retval |= usbd_intf_earlysuspend(pudev); - } - - /* suspend interrupt */ - if (int_status & GINTF_SP) { - retval |= usbd_intf_suspend(pudev); - } - - /* wakeup interrupt */ - if (int_status & GINTF_WKUPIF) { - retval |= usbd_intf_resume(pudev); - } - - /* start of frame interrupt */ - if (int_status & GINTF_SOF) { - retval |= usbd_intf_sof(pudev); - } - - /* reveive fifo not empty interrupt */ - if (int_status & GINTF_RXFNEIF) { - retval |= usbd_intf_rxfifo(pudev); - } - - /* USB reset interrupt */ - if (int_status & GINTF_RST) { - retval |= usbd_intf_reset(pudev); - } - - /* enumeration has been finished interrupt */ - if (int_status & GINTF_ENUMF) { - retval |= usbd_intf_enumfinish(pudev); - } - - /* incomplete synchronization in transfer interrupt*/ - if (int_status & GINTF_ISOINCIF) { - retval |= usbd_intf_isoinincomplete(pudev); - } - - /* incomplete synchronization out transfer interrupt*/ - if (int_status & GINTF_ISOONCIF) { - retval |= usbd_intf_isooutincomplete(pudev); - } - -#ifdef VBUS_SENSING_ENABLED - - /* session request interrupt */ - if (int_status & GINTF_SESIF) { - retval |= usbd_intf_sessionrequest(pudev); - } - - /* OTG mode interrupt */ - if (int_status & GINTF_OTGIF) { - retval |= usbd_intf_otg(pudev); - } -#endif /* VBUS_SENSING_ENABLED */ - } - - return retval; -} - -/*! - \brief indicates that an OUT endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t out_endp_intr = 0U; - - /* read in the device interrupt bits */ - USB_DAOEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num); - - /* transfer complete interrupt */ - if (out_endp_intr & DOEPINTF_TF) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; - - /* data receive is completed */ - usbd_out_transaction(pudev, endp_num); - } - - /* endpoint disable interrupt */ - if (out_endp_intr & DOEPINTF_EPDIS) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS; - } - - /* setup phase finished interrupt (just for control endpoints) */ - if (out_endp_intr & DOEPINTF_STPF) { - /* setup phase is completed */ - usbd_setup_transaction(pudev); - - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF; - } - - /* back to back setup packets received */ - if (out_endp_intr & DOEPINTF_BTBSTP) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that an in endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t in_endp_intr = 0U; - - /* get all in endpoints which have interrupts */ - USB_DAIEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num); - - if (in_endp_intr & DIEPINTF_TF) { - /* disable the fifo empty interrupt for the endpoint */ - USB_DIEPFEINTEN &= ~(0x1U << endp_num); - - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF; - - /* data transmittion is completed */ - usbd_in_transaction(pudev, endp_num); - } - - if (in_endp_intr & DIEPINTF_CITO) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO; - } - - if (in_endp_intr & DIEPINTF_IEPNE) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE; - } - - if (in_endp_intr & DIEPINTF_EPDIS) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS; - } - - if (in_endp_intr & DIEPINTF_TXFE) { - usbd_emptytxfifo_write(pudev, endp_num); - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that early suspend state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev) -{ - USB_GINTEN &= ~GINTEN_ESPIE; - USB_GINTF = GINTF_ESP; - - return 1U; -} - -/*! - \brief indicates that suspend state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev) -{ - __IO uint8_t low_power = pudev->cfg.low_power; - __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST); - __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U; - - pudev->dev.prev_status = pudev->dev.status; - pudev->dev.status = USB_STATUS_SUSPENDED; - - if (low_power && suspend && is_configured) { - /* switch-off the otg clocks */ - USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; - - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } - - /* clear interrupt */ - USB_GINTF = GINTF_SP; - - return 1U; -} - -/*! - \brief indicates that the USB controller has detected a resume or remote Wake-up sequence - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) -{ - pudev->dev.status = pudev->dev.prev_status; - pudev->dev.status = USB_STATUS_CONFIGURED; - - /* clear interrupt */ - USB_GINTF = GINTF_WKUPIF; - - return 1U; -} - -/*! - \brief handle the SOF interrupts - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) -{ - if (NULL != usbd_int_fops) { - usbd_int_fops->SOF(pudev); - } - - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle the rx status queue level interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) -{ - usb_ep_struct *ep; - uint8_t data_pid = 0U, endp_num = 0U; - uint32_t bcount = 0U, packet_num = 0U; - - /* get the status from the top of the fifo (must be read to a variable) */ - __IO uint32_t rx_status = USB_GRSTATP; - - /* disable the rx fifo non-empty interrupt */ - USB_GINTEN &= ~GINTEN_RXFNEIE; - - endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM); - bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U; - data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U); - - /* ensure no-DMA mode can work */ - packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT; - if ((1U == endp_num) && (0U == packet_num)) { - uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num); - - devepctl |= DEPCTL_SNAK; - devepctl &= ~DEPCTL_EPEN; - devepctl &= ~DEPCTL_EPD; - - USB_DOEPxCTL((uint16_t)endp_num) = devepctl; - } - - ep = &pudev->dev.out_ep[endp_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17U) { - case RXSTAT_GOUT_NAK: - break; - case RXSTAT_DATA_UPDT: - if (bcount > 0U) { - usb_fifo_read(ep->xfer_buff, (uint16_t)bcount); - ep->xfer_buff += bcount; - ep->xfer_count += bcount; - } - break; - case RXSTAT_XFER_COMP: - break; - case RXSTAT_SETUP_COMP: - break; - case RXSTAT_SETUP_UPDT: - *(uint32_t *)0x5000081CU |= 0x00020000U; - if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { - /* copy the setup packet received in fifo into the setup buffer in ram */ - usb_fifo_read(pudev->dev.setup_packet, 8U); - - ep->xfer_count += bcount; - } - break; - default: - break; - } - - /* enable the rx fifo non-empty interrupt */ - USB_GINTEN |= GINTEN_RXFNEIE; - - return 1U; -} - -/*! - \brief handle USB reset interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - usb_ep_struct *ep; - - /* clear the remote wakeup signaling */ - USB_DCTL &= ~DCTL_RWKUP; - - /* flush the tx fifo */ - usb_txfifo_flush(pudev, 0U); - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF((uint16_t)i) = 0xFFU; - USB_DOEPxINTF((uint16_t)i) = 0xFFU; - } - - /* clear all pending device endpoint interrupts */ - USB_DAEPINT = 0xFFFFFFFFU; - - /* enable endpoint 0 interrupts */ - USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; - USB_DAEPINTEN &= ~DAEPINTEN_IEPIE; - USB_DAEPINTEN = (1U << 16) | 1U; - - /* enable out endpoint interrupts */ - USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; - - /* enable in endpoint interrupts */ - USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; - - /* reset device address */ - USB_DCFG &= ~DCFG_DAR; - USB_DCFG |= 0U << 4U; - - /* configure endpoint 0 to receive setup packets */ - usb_ep0_startout(pudev); - - /* clear usb reset interrupt */ - USB_GINTF = GINTF_RST; - - /* open EP0 IN */ - ep = &pudev->dev.in_ep[0]; - - USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE; - USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; - - if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DIEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - /* open EP0 OUT */ - ep = &pudev->dev.out_ep[0]; - - USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE; - - if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DOEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - pudev->dev.status = USB_STATUS_DEFAULT; - - return 1U; -} - -/*! - \brief handle enumeration finish interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) -{ - uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U); - - /* set the max packet size of devie in endpoint based on the enumeration speed */ - USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed]; - - /* clear global in NAK */ - USB_DCTL &= ~DCTL_CGINAK; - USB_DCTL |= DCTL_CGINAK; - - /* set USB turn-around time based on device speed and PHY interface */ - if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) { - pudev->cfg.core_speed = USB_CORE_SPEED_HIGH; - pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x09U << 10; - } else { - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x05U << 10; - } - - /* clear interrupt */ - USB_GINTF = GINTF_ENUMF; - - return 1U; -} - -/*! - \brief handle the ISO in incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev) -{ - - /* clear interrupt */ - USB_GINTF = GINTF_ISOINCIF; - - return 1U; -} - -/*! - \brief handle the ISO OUT incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) -{ - /* clear interrupt */ - USB_GINTF = GINTF_ISOONCIF; - - return 1U; -} - -/*! - \brief check FIFO for the next packet to be loaded - \param[in] pudev: pointer to usb device instance - \param[in] ep_id: endpoint identifier which is in (0..3) - \param[out] none - \retval status -*/ -static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) -{ - uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U; - usb_ep_struct *ep; - - ep = &pudev->dev.in_ep[ep_num]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) && - (ep->xfer_count < ep->xfer_len)) { - /* write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - if(ep->xfer_len == ep->xfer_count) { - fifo_empty_mask = 0x1U << ep_num; - USB_DIEPFEINTEN &= ~fifo_empty_mask; - } - } - - return 1U; -} - -#ifdef VBUS_SENSING_ENABLED - -/*! - \brief indicates that the USB_OTG controller has detected a connection - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev) -{ - pudev->dev.connection_status = 1U; - - /* clear the interrupt bit */ - USB_GINTF = GINTF_SESIF; - - return 1; -} - -/*! - \brief indicates that the USB_OTG controller has detected an OTG event - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev) -{ - if (USB_GOTGINTF & GOTGINTF_SESEND) { - pudev->dev.class_deinit(pudev, 0); - pudev->dev.connection_status = 0; - } - - /* clear OTG interrupt */ - USB_GOTGINTF |= GOTGINTF_SESEND; - - return 1; -} - -#endif /* VBUS_SENSING_ENABLED */ diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c deleted file mode 100644 index 33ad7a94b6..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c +++ /dev/null @@ -1,727 +0,0 @@ -/*! - \file usbd_std.c - \brief USB 2.0 standard handler driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_std.h" -#include "usb_core.h" - -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); - -static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clrfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfig, - usbd_setconfig, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse(pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, req.bmRequestType & 0x80U); - break; - } - - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.out_ep[0]; - - if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_rx (pudev, - 0U, - ep->xfer_buff, - (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, 0U); - } - - usbd_ctlstatus_tx(pudev); - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.in_ep[0]; - - if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - /* last packet is MPS multiple, so send ZLP packet */ - if ((pudev->dev.sum_len % ep->endp_mps == 0U) && - (pudev->dev.sum_len >= ep->endp_mps) && - (pudev->dev.sum_len < pudev->dev.ctl_len)) { - usbd_ep_tx (pudev, 0U, NULL, 0U); - pudev->dev.ctl_len = 0U; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, 0U); - } - - usbd_ctlstatus_rx(pudev); - } - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*StandardDeviceRequest[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret = USBD_OK; - - switch (pudev->dev.status) { - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - usbd_ctlstatus_tx(pudev); - } - } else { - usbd_enum_error(pudev, req); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - - return ret; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user... */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation... */ -} - -/*! - \brief get the device descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.dev_desc[0]; - - return pudev->dev.dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.config_desc[2]; - - return pudev->dev.config_desc; -} - -/*! - \brief get string descriptor - \param[in] index: string descriptor index - \param[in] pLen: pointer to string length - \param[out] none - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->dev.strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQTYPE_MASK) { - /* process device feature */ - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 0U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - break; - /* process interface feature */ - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - /* process endpoint feature */ - case USB_REQTYPE_ENDPOINT: - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - - pudev->dev.class_req_handler(pudev, req); - } - } - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - __IO uint32_t DctlrStatus; - - switch (req->bmRequestType & USB_REQ_MASK) { - /* process device feature */ - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 1U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } else if ((req->wValue == USB_FEATURE_TEST_MODE) && - (0U == (req->wIndex & 0xFFU))) { - DctlrStatus = USB_DCTL; - - usbd_ctlstatus_tx(pudev); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - /* process interface feature */ - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - /* process endpoint feature */ - case USB_REQTYPE_ENDPOINT: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t DevAddr; - - if ((0U == req->wIndex) && (0U == req->wLength)) { - DevAddr = (uint8_t)(req->wValue) & 0x7FU; - - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - usbd_enum_error(pudev, req); - } else { - USB_SET_DEVADDR((uint32_t)DevAddr); - - usbd_ctlstatus_tx(pudev); - - if (0U != DevAddr) { - pudev->dev.status = USB_STATUS_ADDRESSED; - } else { - pudev->dev.status = USB_STATUS_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { - uint8_t desc_type = (uint8_t)(req->wValue >> 8); - uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; - - if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { - uint16_t len; - uint8_t *pbuf; - - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); - - if ((0U != len) && (0U != req->wLength)) { - len = USB_MIN(len, req->wLength); - - if ((1U == desc_type) && (64U == req->wLength)) { - len = 8U; - } - - usbd_ctltx(pudev, pbuf, len); - } - } else { - usbd_enum_error(pudev, req); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) { - pudev->dev.class_req_handler(pudev, req); - } else { - /* no operation */ - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t USBD_default_config = 0U; - - if (1U != req->wLength) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U); - break; - case USB_STATUS_CONFIGURED: - usbd_ctltx(pudev, &pudev->dev.config_num, 1U); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - /* if config index is more than configuration max number */ - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (cfgidx) { - pudev->dev.config_num = cfgidx; - pudev->dev.status = USB_STATUS_CONFIGURED; - pudev->dev.class_init(pudev, cfgidx); - } - - usbd_ctlstatus_tx(pudev); - break; - case USB_STATUS_CONFIGURED: - if (0U == cfgidx) { - pudev->dev.status = USB_STATUS_ADDRESSED; - pudev->dev.config_num = cfgidx; - pudev->dev.class_deinit(pudev, cfgidx); - } else if (cfgidx != pudev->dev.config_num) { - /* clear old configuration */ - pudev->dev.class_deinit(pudev, pudev->dev.config_num); - - /* set new configuration */ - pudev->dev.config_num = cfgidx; - pudev->dev.class_init(pudev, cfgidx); - } else { - /* no operation */ - } - - usbd_ctlstatus_tx(pudev); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *psetup = pudev->dev.setup_packet; - - req->bmRequestType = *psetup; - req->bRequest = *(uint8_t *)(psetup + 1U); - req->wValue = SWAPBYTE (psetup + 2U); - req->wIndex = SWAPBYTE (psetup + 4U); - req->wLength = SWAPBYTE (psetup + 6U); - - pudev->dev.ctl_len = req->wLength; -} - -/*! - \brief handle USB low level error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, 0x80U); - usbd_ep_stall(pudev, 0x00U); - usb_ep0_startout(pudev); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c deleted file mode 100644 index de41f72273..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c +++ /dev/null @@ -1,737 +0,0 @@ -/*! - \file usbh_core.c - \brief this file implements the functions for the core state machine process - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_hcs.h" -#include "usbh_core.h" -#include "usbh_int.h" -#include "stdio.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" -#include "usb_core.h" - -extern class_polling_fun_cb_struct class_polling_cb; - -uint8_t usbh_sof (usb_core_handle_struct *pudev); -uint8_t usbh_connected (usb_core_handle_struct *pudev); -uint8_t usbh_disconnected (usb_core_handle_struct *pudev); - -usbh_hcd_int_cb_struct usbh_hcd_int_cb = -{ - usbh_sof, - usbh_connected, - usbh_disconnected, -}; - -usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb; -extern usbh_state_handle_struct usbh_state_core; - -static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -/* the host state handle function array */ -void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - host_idle_handle, - host_dev_attached_handle, - host_dev_detached_handle, - host_detect_dev_speed_handle, - host_enum_handle, - host_class_request_handle, - host_class_handle, - host_user_input_handle, - host_suspended_handle, - host_error_handle, -}; - -/* the host state handle table */ -state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move }, - {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move }, - {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move }, - {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move }, - {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, - {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, -}; - -/*! - \brief the polling function of host state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate; - - scd_begin(p_state, HOST_FSM_ID); - - if (-1 == p_state->usbh_current_state_stack_top) { - uint8_t cur_state = p_state->usbh_current_state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) { - if (HOST_DEV_DETACHED != cur_state) { - p_state->usbh_current_state = HOST_DEV_DETACHED; - cur_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[cur_state](pudev, puhost, p_state); - } else { - uint8_t stack0_state = p_state->stack[0].state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) { - if (HOST_DEV_DETACHED != stack0_state) { - p_state->stack[0].state = HOST_DEV_DETACHED; - stack0_state = HOST_DEV_DETACHED; - p_state->usbh_current_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[stack0_state](pudev, puhost, p_state); - } - - return USBH_OK; -} - -/*! - \brief the handle function of HOST_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (hcd_is_device_connected(pudev)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } -} - -/*! - \brief the handle function of HOST_DEV_ATTACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_attached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usr_cb->device_connected(); - puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U); - puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U); - - /* reset usb device */ - if (0U == usb_port_reset(pudev)) { - puhost->usr_cb->device_reset(); - - /* wait for USB USBH_ISR_PrtEnDisableChange() - * host is now ready to start the enumeration - */ - puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET(); - puhost->usr_cb->device_speed_detected(puhost->device.speed); - - /* open in control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_in_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - /* open out control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_out_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_ENUMERATION state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_enum_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) { - puhost->usr_cb->enumeration_finish(); - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_USER_INPUT, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_USER_INPUT state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_user_input_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) { - if (USBH_OK == (puhost->class_init(pudev, puhost))) { - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_CLASS_REQ, - pustate->usbh_current_state); - } - } -} - -/*! - \brief the handle function of HOST_CLASS_REQUEST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_request_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_CLASS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - class_state_polling_fun(pudev, puhost, pustate); -} - -/*! - \brief the handle function of HOST_SUSPENDED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_suspended_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief the handle function of HOST_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* re-initilaize host for new enumeration */ - usbh_deinit (pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DEV_DETACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_detached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* manage user disconnect operations*/ - puhost->usr_cb->device_disconnected(); - - /* re-initilaize host for new enumeration */ - usbh_deinit(pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - usbh_allchannel_dealloc(pudev); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DETECT_DEV_SPEED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief usb connect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_connected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 1U; - - return 0U; -} - -/*! - \brief usb disconnect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_disconnected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 0U; - - return 0U; -} - -/*! - \brief usb sof callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_sof (usb_core_handle_struct *pudev) -{ - /* this callback could be used to implement a scheduler process */ - return 0U; -} - -/*! - \brief initialize the host portion of the driver. - \param[in] pudev: pointer to usb device - \param[in] core_id: usb otg core identifier(high-speed or full-speed) - \param[out] none - \retval operation status -*/ -uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - pudev->host.connect_status = 0U; - - pudev->host.host_channel[0].endp_mps = 8U; - - usb_core_select(pudev, core_id); - -#ifndef DUAL_ROLE_MODE_ENABLED - - USB_GLOBAL_INT_DISABLE(); - - usb_core_init(pudev); - - /* force host mode*/ - usb_mode_set(pudev, HOST_MODE); - - usb_hostcore_init(pudev); - - USB_GLOBAL_INT_ENABLE(); - -#endif - - return 0U; -} - -/*! - \brief check if the device is connected. - \param[in] pudev: pointer to usb device - \param[out] none - \retval device connection status. 1 -> connected and 0 -> disconnected -*/ -uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev) -{ - return (uint32_t)(pudev->host.connect_status); -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval urb_state_enum -*/ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].urb_state; -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval No. of data bytes transferred -*/ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].xfer_count; -} - -/*! - \brief de-initialize host - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[out] none - \retval host status -*/ -usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate) -{ - /* software init */ - - puhost->control.ep0_size = USB_MAX_EP0_SIZE; - - puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT; - puhost->device.speed = HPRT_PRTSPD_FULL_SPEED; - - usbh_channel_free(pudev, puhost->control.hc_in_num); - usbh_channel_free(pudev, puhost->control.hc_out_num); - - scd_init(pustate); - scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE); - - scd_begin(pustate,HOST_FSM_ID); - scd_state_move(pustate, HOST_IDLE); - - return USBH_OK; -} - -/*! - \brief state core driver init - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_init(usbh_state_handle_struct* pustate) -{ - /* init the state core */ - pustate->usbh_current_state = 0U; - pustate->usbh_current_state_table = NULL; - pustate->usbh_current_state_table_size = 0U; - - pustate->usbh_current_state_stack_top = -1; - pustate->stack->state = 0U; - pustate->stack->table_size = 0U; - pustate->stack->table = NULL; - - pustate->usbh_regist_state_table_num = 0U; - pustate->usbh_regist_state_table->table = NULL; - pustate->usbh_regist_state_table->table_size = 0U; - pustate->usbh_regist_state_table->id = 0U; - - /* init the control and the enumeration polling handle flag */ - ctrl_polling_handle_flag = 0U; - enum_polling_handle_flag = 0U; -} - -/*! - \brief state core driver table regist - \param[in] pustate: pointer to usb state driver - \param[in] pstate_table: pointer to the table to regist - \param[in] table_id: the id of the table to regist - \param[in] current_table_size: the size of the current table to regist - \param[out] none - \retval none -*/ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size) -{ - usbh_state_regist_table_struct *cur_state_reg_table; - - cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num]; - - cur_state_reg_table->id = table_id; - cur_state_reg_table->table = pstate_table; - cur_state_reg_table->table_size = current_table_size; - - pustate->usbh_regist_state_table_num++; -} - -/*! - \brief state core driver begin - \param[in] pustate: pointer to usb state driver - \param[in] table_id: the id of the table to begin - \param[out] none - \retval none -*/ -void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) -{ - uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num; - usbh_state_regist_table_struct *cur_state_reg_table; - - for (i = 0U; i < table_num; i++) { - cur_state_reg_table = &pustate->usbh_regist_state_table[i]; - - if (table_id == cur_state_reg_table->id) { - pustate->usbh_current_state_table = cur_state_reg_table->table; - pustate->usbh_current_state_table_size = cur_state_reg_table->table_size; - break; - } - } -} - -/*! - \brief state core driver move state - \param[in] pustate: pointer to usb state driver - \param[in] state: the state to move - \param[out] none - \retval none -*/ -void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state) -{ - pustate->usbh_current_state = state; -} - -/*! - \brief state core driver event handle - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[in] event: the current event - \param[in] state: the current state - \param[out] none - \retval host status -*/ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state) -{ - uint8_t i = 0U; - ACT_FUN event_act_fun = NULL; - state_table_struct *backup_state_t = pustate->usbh_current_state_table; - state_table_struct *executive_state_table = pustate->usbh_current_state_table; - - /* look up the table to find the action function */ - for (i = 0U; i < pustate->usbh_current_state_table_size; i++) { - if (state == executive_state_table->cur_state) { - if (event == executive_state_table->cur_event) { - state = executive_state_table->next_state; - event_act_fun = executive_state_table->event_action_fun; - break; - } else { - executive_state_table++; - } - } else { - executive_state_table++; - } - } - - pustate->usbh_current_state_table = backup_state_t; - - /* if the action function is not NULL, execute the action function */ - if (event_act_fun) { - if (event_act_fun == &only_state_move) { - pustate->usbh_current_state = state; - } else { - return event_act_fun(pudev, puhost, pustate); - } - } - - return USBH_BUSY; -} - -/*! - \brief state core driver table push - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_push(usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) { - pustate->usbh_current_state_stack_top++; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - /* put the current state table into the state stack */ - top_state_element->state = pustate->usbh_current_state; - top_state_element->table = pustate->usbh_current_state_table; - top_state_element->table_size = pustate->usbh_current_state_table_size; - } -} - -/*! - \brief state core driver table pop - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_pop (usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - if (pustate->usbh_current_state_stack_top > -1) { - /* get the current state table from the state stack */ - pustate->usbh_current_state = top_state_element->state; - pustate->usbh_current_state_table = top_state_element->table; - pustate->usbh_current_state_table_size = top_state_element->table_size; - pustate->usbh_current_state_stack_top--; - } -} -/*! - \brief the polling function of class req state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_req_polling(pudev, puhost, pustate); -} - -/*! - \brief the polling function of class state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_polling(pudev, puhost, pustate); -} - -/*! - \brief the function is only used to state move - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return USBH_OK; -} - -/*! - \brief the function to the up state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - scd_table_pop((usbh_state_handle_struct *)pustate); - - return USBH_OK; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c deleted file mode 100644 index 3f5277701f..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c +++ /dev/null @@ -1,639 +0,0 @@ -/*! - \file usbh_ctrl.c - \brief this file implements the functions for the control transmit process - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_core.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t ctrl_polling_handle_flag = 0U; -uint8_t ctrl_setup_wait_flag = 0U; -uint8_t ctrl_data_wait_flag = 0U; -uint8_t ctrl_status_wait_flag = 0U; - -static uint16_t timeout = 0U; - -static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the ctrl state handle function array */ -void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) = -{ - ctrl_idle_handle, - ctrl_setup_handle, - ctrl_data_handle, - ctrl_status_handle, - ctrl_error_handle, - ctrl_stalled_handle, - ctrl_complete_handle, -}; - -/* the ctrl state handle table */ -state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of CTRL state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - - p_state = (usbh_state_handle_struct *)pustate; - - /* if first enter this function, begin the ctrl state */ - if (0U == ctrl_polling_handle_flag) { - ctrl_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, CTRL_IDLE); - } - - /* base on the current state to handle the ctrl state */ - scd_begin(p_state, CTRL_FSM_ID); - ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - - /* determine the control transfer whether to complete */ - switch (puhost->usbh_backup_state.ctrl_backup_state) { - case CTRL_COMPLETE: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_OK; - break; - case CTRL_STALLED: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_NOT_SUPPORTED; - break; - case CTRL_ERROR: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_FAIL; - break; - default: - exe_state = USBH_BUSY; - break; - } - - return exe_state; -} - -/*! - \brief the handle function of CTRL_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_SETUP state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_setup_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP; - - if (0U == ctrl_setup_wait_flag) { - ctrl_setup_wait_flag = 1U; - - /* send a setup packet */ - usbh_ctltx_setup (pudev, - puhost->control.setup.data, - puhost->control.hc_out_num); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - /* case setup packet sent successfully */ - if (URB_DONE == urb_status) { - /* check if there is a data stage */ - if (0U != puhost->control.setup.b.wLength) { - ctrl_setup_wait_flag = 0U; - timeout = DATA_STAGE_TIMEOUT; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state); - /* no data stage */ - } else { - timeout = NODATA_STAGE_TIMEOUT; - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - } - - /* set the delay timer to enable timeout for data stage completion */ - puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET(); - } else if (URB_ERROR == urb_status) { - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state); - } else { - /* no operation */ - } - } -} - -/*! - \brief the handle function of CTRL_DATA state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_data_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA; - - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_IN == direction) { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* issue an IN token */ - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_in_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - /* check is data packet transfered successfully */ - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_data_wait_flag = 0U; - - /* timeout for in transfer */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* start data out transfer (only one data packet)*/ - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U; - - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_out_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - /* if the setup pkt is sent successful, then change the state */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* nack received from device */ - ctrl_data_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_STATUS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_status_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS; - - /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */ - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_OUT == direction) { - /* handle status in */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status*/ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_status_wait_flag = 0U; - - /* handle timeout */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - /* handle status out */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* handle URB_NOTREADY status */ - ctrl_status_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_ERROR status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR; - - if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { - /* do the transmission again, starting from setup packet */ - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); - } else { - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of CTRL_STALLED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_COMPLETE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_complete_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief send datas from the host channel - \param[in] pudev: pointer to usb device - \param[in] buf: data buffer address to send datas - \param[in] hc_num: the number of the host channel - \param[in] len: length of the send data - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, - uint8_t *buf, - uint8_t hc_num, - uint16_t len) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->xfer_buff = buf; - puhc->xfer_len = len; - - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - if (0U == puhc->endp_in) { - if (0U == len) { - /* for status out stage, length = 0, status out pid = 1 */ - puhc->data_tg_out = 1U; - } - - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - puhc->DPID = HC_PID_DATA1; - } - break; - - case USB_EPTYPE_ISOC: - puhc->DPID = HC_PID_DATA0; - break; - - case USB_EPTYPE_BULK: - if (0U == puhc->endp_in) { - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - } - break; - - case USB_EPTYPE_INTR: - if (0U == puhc->endp_in) { - if (0U == puhc->data_tg_out) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_out ^= 1U; - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_in ^= 1U; - } - break; - - default: - break; - } - - hcd_submit_request (pudev, hc_num); - - return USBH_OK; -} - -/*! - \brief send the setup packet to the device - \param[in] pudev: pointer to usb device - \param[in] buf: buffer pointer from which the data will be send to device - \param[in] hc_num: host channel number - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->DPID = HC_PID_SETUP; - puhc->xfer_buff = buf; - puhc->xfer_len = USBH_SETUP_PACKET_SIZE; - - return (usbh_status_enum)hcd_submit_request (pudev, hc_num); -} - -/*! - \brief this function prepare a hc and start a transfer - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - puhc->urb_state = URB_IDLE; - puhc->xfer_count = 0U; - - return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num); -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c deleted file mode 100644 index 33eecd62db..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c +++ /dev/null @@ -1,185 +0,0 @@ -/*! - \file usbh_hcs.c - \brief this file implements functions for opening and closing host channels - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_hcs.h" - -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev); - -/*! - \brief open a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - uint16_t channel_info = puhc->info; - - puhc->endp_id = (uint8_t)channel_info & 0x7FU; - puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7U; - puhc->endp_type = ep_type; - puhc->endp_mps = ep_mps; - puhc->dev_addr = dev_addr; - puhc->dev_speed = dev_speed; - - puhc->data_tg_in = 0U; - puhc->data_tg_out = 0U; - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief modify a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB Device address allocated to attached device - \param[in] dev_speed: USB device speed (full speed / low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - if (0U != dev_addr) { - puhc->dev_addr = dev_addr; - } - - if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) { - puhc->endp_mps = ep_mps; - } - - if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) { - puhc->dev_speed = dev_speed; - } - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief allocate a new channel for the pipe - \param[in] pudev: pointer to usb device - \param[in] ep_addr: endpoint for which the channel to be allocated - \param[out] none - \retval host channel number -*/ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint16_t hc_num = usbh_freechannel_get(pudev); - - if ((uint16_t)HC_ERROR != hc_num) { - pudev->host.host_channel[hc_num].info = HC_USED | ep_addr; - } - - return (uint8_t)hc_num; -} - -/*! - \brief free the usb host channel - \param[in] pudev: pointer to usb device - \param[in] index: channel number to be freed which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index) -{ - if (index < HC_MAX) { - pudev->host.host_channel[index].info &= HC_USED_MASK; - } - - return USBH_OK; -} - -/*! - \brief free all usb host channel - \param[in] pudev: pointer to usb device - \param[out] none - \retval host operation status -*/ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev) -{ - uint8_t index; - - for (index = 2U; index < HC_MAX; index ++) { - pudev->host.host_channel[index].info = 0U; - } - - return USBH_OK; -} - -/*! - \brief get a free channel number for allocation to a device endpoint - \param[in] pudev: pointer to usb device - \param[out] none - \retval free channel number -*/ -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev) -{ - uint8_t index = 0U; - - for (index = 0U; index < HC_MAX; index++) { - if (0U == (pudev->host.host_channel[index].info & HC_USED)) { - return (uint16_t)index; - } - } - - return HC_ERROR; -} - diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c deleted file mode 100644 index 5a652bcb88..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c +++ /dev/null @@ -1,612 +0,0 @@ -/*! - \file usbh_int.c - \brief USB host mode interrupt handler file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usb_core.h" -#include "usb_defines.h" -#include "usbh_int.h" - -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev); - -/*! - \brief handle global host interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbh_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - __IO uint32_t int_flag = 0U; - - /* check if host mode */ - if (USB_CURRENT_MODE_GET() == HOST_MODE) { - USB_CORE_INTR_READ(int_flag); - - if (!int_flag) { - return 0U; - } - - /* start of frame interrupt handle */ - if (int_flag & GINTF_SOF) { - retval |= usbh_intf_sof (pudev); - } - - /* rx fifo non-empty interrupt handle */ - if (int_flag & GINTF_RXFNEIF) { - retval |= usbh_intf_rxfifo_noempty (pudev); - } - - /* non-periodic tx fifo empty interrupt hanlde */ - if (int_flag & GINTF_NPTXFEIF) { - retval |= usbh_intf_nptxfifo_empty (pudev); - } - - /* periodic tx fifo empty interrupt handle */ - if (int_flag & GINTF_PTXFEIF) { - retval |= usbh_intf_ptxfifo_empty (pudev); - } - - /* host channels interrupt handle */ - if (int_flag & GINTF_HCIF) { - retval |= usbh_intf_hc (pudev); - } - - /* host port interrupt handle */ - if (int_flag & GINTF_HPIF) { - retval |= usbh_intf_port (pudev); - } - - /* disconnect interrupt handle */ - if (int_flag & GINTF_DISCIF) { - retval |= usbh_intf_disconnect (pudev); - } - - /* isochronous in transfer not complete interrupt handle */ - if (int_flag & GINTF_ISOONCIF) { - retval |= usbh_intf_iso_incomplete_xfer (pudev); - } - } - - return retval; -} - -/*! - \brief handle the start-of-frame interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->sof(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle all host channels interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - uint32_t retval = 0U; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) { - if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) { - retval |= usbh_intf_hc_in (pudev, i); - } else { - retval |= usbh_intf_hc_out (pudev, i); - } - } - } - - return retval; -} - -/*! - \brief handle the disconnect interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->device_disconnected(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_DISCIF; - - return 1U; -} - -/*! - \brief handle the non-periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U; - - if (len > puhc->xfer_len) { - /* last packet */ - len = (uint16_t)puhc->xfer_len; - - USB_GINTEN &= ~GINTF_NPTXFEIF; - - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U; - - if (len > puhc->xfer_len) { - len = puhc->xfer_len; - - /* last packet */ - USB_GINTEN &= ~GINTF_PTXFEIF; - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the host port interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) -{ - uint8_t port_speed = 0U; - uint8_t port_reset = 0U; - uint32_t retval = 0U; - __IO uint32_t hostportdup = USB_HPCS; - - /* clear the interrupt bits in gintsts */ - hostportdup &= ~HPCS_PE; - hostportdup &= ~HPCS_PCD; - hostportdup &= ~HPCS_PEDC; - - /* port connect detected */ - if (USB_HPCS & HPCS_PCD) { - hostportdup |= HPCS_PCD; - usbh_hcd_int_fops->device_connected(pudev); - retval |= 1U; - } - - /* port enable changed */ - if (USB_HPCS & HPCS_PEDC) { - hostportdup |= HPCS_PEDC; - - if (USB_HPCS & HPCS_PE) { - port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U); - - if (HPRT_PRTSPD_LOW_SPEED == port_speed) { - USB_HFT = 6000U; - - if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_6_MHZ); - } - port_reset = 1U; - } - } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) { - USB_HFT = 48000U; - - if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - port_reset = 1U; - } - } else { - /* for high speed device and others */ - port_reset = 1U; - } - } - } - - if (port_reset) { - usb_port_reset(pudev); - } - - /* clear port interrupts */ - USB_HPCS = hostportdup; - - return retval; -} - -/*! - \brief handle the out channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num); - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - channel_intr &= USB_HCHxINTEN((uint16_t)channel_num); - - if (channel_intr & HCHINTF_ACK) { - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channel_intr & HCHINTF_REQOVR) { - /* handle queue overrun interrupt */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channel_intr & HCHINTF_TF) { - /* handle transfer finished interrupt */ - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } else if (channel_intr & HCHINTF_STALL) { - /* handle stall */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_STALL; - } else if (channel_intr & HCHINTF_NAK) { - /* handle NAK */ - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_NAK; - } else if (channel_intr & HCHINTF_USBER) { - /* handle USB bus error */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_TRACERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channel_intr & HCHINTF_NYET) { - /* handle NYET */ - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_NYET; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET; - } else if (channel_intr & HCHINTF_DTER) { - /* handle data toggle error */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status= HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else if (channel_intr & HCHINTF_CH) { - /* handle channel halted */ - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - - if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18U)) { - puhc->data_tg_out ^= 1U; - } - break; - case HC_NAK: - puhc->urb_state = URB_NOTREADY; - break; - case HC_NYET: - puhc->urb_state = URB_NOTREADY; - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - case HC_TRACERR: - puhc->urb_state = URB_ERROR; - break; - default: - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the in channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint8_t endp_type = 0U; - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num); - __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num); - - channle_intf &= USB_HCHxINTEN((uint16_t)channel_num); - - endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U); - - if (channle_intf & HCHINTF_ACK) { - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channle_intf & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_STALL; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - - /* NOTE: When there is a 'stall', reset also nak, - else, the pudev->host.status = HC_STALL - will be overwritten by 'nak' in code below */ - channle_intf &= ~HCHINTF_NAK; - - usb_hostchannel_halt(pudev, channel_num); - } else if (channle_intf & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else { - /* no operation */ - } - /* handle queue overrun interrupt */ - if (channle_intf & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channle_intf & HCHINTF_TF) { - /* handle transfer finished interrupt */ - puhc->status = HC_XF; - puhc->err_count = 0U; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - - if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->data_tg_in ^= 1U; - } else if (USB_EPTYPE_INTR == endp_type) { - channel_ctrl |= HCHCTL_ODDFRM; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - puhc->urb_state = URB_DONE; - } else { - /* no operation */ - } - } else if (channle_intf & HCHINTF_CH) { - /* handle channel halted */ - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - break; - case HC_TRACERR: - case HC_DTGERR: - puhc->err_count = 0U; - puhc->urb_state = URB_ERROR; - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - default: - if (USB_EPTYPE_INTR == endp_type) { - puhc->data_tg_in ^= 1U; - } - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else if (channle_intf & HCHINTF_USBER) { - /* handle USB bus error */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_TRACERR; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channle_intf & HCHINTF_NAK) { - /* handle NAK */ - if (USB_EPTYPE_INTR == endp_type) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - } - - puhc->status = HC_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - - if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - /* re-activate the channel */ - channel_ctrl |= HCHCTL_CEN; - channel_ctrl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - } - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the rx fifo non-empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - __IO uint8_t channel_num = 0U; - __IO uint32_t rx_status = 0U; - uint32_t usbh_ch_ctl_reg = 0U; - usb_hostchannel_struct *puhc; - - /* disable the rx status queue level interrupt */ - USB_GINTEN &= ~GINTF_RXFNEIF; - - rx_status = USB_GRSTATP; - channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM); - puhc = &pudev->host.host_channel[channel_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17) { - case GRSTATR_RPCKST_IN: - count = (rx_status & GRSTATRP_BCOUNT) >> 4; - - /* read the data into the host buffer. */ - if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { - usb_fifo_read(puhc->xfer_buff, (uint16_t)count); - - /* manage multiple Xfer */ - puhc->xfer_buff += count; - puhc->xfer_count += count; - - if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) { - /* re-activate the channel when more packets are expected */ - usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num); - usbh_ch_ctl_reg |= HCHCTL_CEN; - usbh_ch_ctl_reg &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg; - } - } - break; - case GRSTATR_RPCKST_IN_XFER_COMP: - break; - case GRSTATR_RPCKST_DATA_TOGGLE_ERR: - count = (rx_status & GRSTATRP_BCOUNT) >> 4; - while (count > 0) { - rx_status = USB_GRSTATP; - count--; - } - break; - case GRSTATR_RPCKST_CH_HALTED: - default: - break; - } - - /* enable the rx status queue level interrupt */ - USB_GINTEN |= GINTF_RXFNEIF; - - return 1U; -} - -/*! - \brief handle the incomplete periodic transfer interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev) -{ - __IO uint32_t gint_flag = 0U; - - gint_flag = USB_HCHxCTL(0U); - USB_HCHxCTL(0U) = 0U; - - gint_flag = 0U; - - /* clear interrupt */ - gint_flag |= GINTF_ISOONCIF; - USB_GINTF = gint_flag; - - return 1U; -} diff --git a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c b/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c deleted file mode 100644 index 6052b906e4..0000000000 --- a/bsp/gd32105c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c +++ /dev/null @@ -1,834 +0,0 @@ -/*! - \file usbh_std.c - \brief USB 2.0 standard function definition - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_core.h" -#include "usbh_usr.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t local_buffer[64U]; -uint8_t usbh_cfg_desc[512U]; -uint8_t enum_polling_handle_flag = 0U; - -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the enumeration state handle function array */ -void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - enum_idle_handle, - enum_set_addr_handle, - enum_get_full_dev_desc_handle, - enum_get_cfg_desc_handle, - enum_get_full_cfg_desc_handle, - enum_get_mfc_string_desc_handle, - enum_get_product_string_desc_handle, - enum_get_serialnum_string_desc_handle, - enum_set_configuration_handle, - enum_dev_configured_handle, -}; - -/* the enumeration state handle table */ -state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move }, - {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move }, - {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move }, - {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move }, - {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move }, - {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move }, - {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move }, - {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move }, - {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move }, - {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of enumeration state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval usb host status -*/ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - p_state = (usbh_state_handle_struct *)pustate; - - if (0U == enum_polling_handle_flag) { - enum_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, ENUM_IDLE); - } - - /* start the enumeration state handle */ - scd_begin(p_state,ENUM_FSM_ID); - - if (0U == p_state->usbh_current_state_stack_top) { - enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - } else { - enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); - } - - /* determine the enumeration whether to complete */ - if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) { - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - enum_polling_handle_flag = 0U; - exe_state = USBH_OK; - } - - return exe_state; -} - -/*! - \brief the handle function of ENUM_IDLE state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - 8U); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U); - puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0; - - /* issue reset */ - usb_port_reset(pudev); - - /* modify control channels configuration for maxpacket size */ - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, - puhost, - pustate, - ENUM_EVENT_SET_ADDR, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_DEV_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - USB_DEVDESC_SIZE); - } - - if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE); - puhost->usr_cb->device_desc_available(&puhost->device.dev_desc); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_ADDR state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_addr_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(2U); - } - puhost->device.address = USBH_DEVICE_ADDRESS; - - /* user callback for device address assigned */ - puhost->usr_cb->device_address_set(); - - /* modify control channels to update device address */ - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - puhost->device.address, - 0U, - 0U, - 0U); - - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - puhost->device.address, - 0U, - 0U, - 0U); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_DEV_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, - USB_CFGDESC_SIZE); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < USB_CFGDESC_SIZE; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - USB_CFGDESC_SIZE); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, puhost->device.cfg_desc.wTotalLength); - } - - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < puhost->device.cfg_desc.wTotalLength; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - puhost->device.cfg_desc.wTotalLength); - - /* User callback for configuration descriptors available */ - puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc[0]); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_MFC_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_MFC_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC; - - if (0U != puhost->device.dev_desc.iManufacturer) { - if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iManufacturer, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - puhost->usr_cb->manufacturer_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_PRODUCT_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->manufacturer_string("N/A"); - scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC); - } -} - -/*! - \brief the handle function of ENUM_GET_PRODUCT_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC; - - if (0U != puhost->device.dev_desc.iProduct) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iProduct, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->product_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->product_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_SERIALNUM_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC; - - if (0U != puhost->device.dev_desc.iSerialNumber) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iSerialNumber, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->serial_num_string(local_buffer); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->serial_num_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_CONFIGURATION state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) { - usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_DEV_CONFIGURED, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_DEV_CONFIGURED state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief get descriptor in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] buf: buffer to store the descriptor - \param[in] ReqType: descriptor type - \param[in] ValueIdx: wValue for the GetDescriptr request - \param[in] Len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_enum_desc_get(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len) -{ - usb_setup_union *pSetup = &(puhost->control.setup); - - pSetup->b.bmRequestType = USB_DIR_IN | req_type; - pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR; - pSetup->b.wValue = value_idx; - - if (USB_STRDESC == (value_idx & 0xff00U)){ - pSetup->b.wIndex = 0x0409U; - } else { - pSetup->b.wIndex = 0U; - } - - pSetup->b.wLength = len; - - puhost->control.buff = buf; - puhost->control.length = len; - -} - -/*! - \brief set address in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] device_address: the device address - \param[out] none - \retval none -*/ -void usbh_enum_addr_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t device_address) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_ADDRESS; - p_setup->b.wValue = (uint16_t)device_address; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0U; - puhost->control.length = 0U; -} - -/*! - \brief set configuration in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] cfg_idx: the index of the configuration - \param[out] none - \retval none -*/ -void usbh_enum_cfg_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint16_t cfg_idx) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_CONFIGURATION; - p_setup->b.wValue = cfg_idx; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0; - puhost->control.length = 0U; -} - -/*! - \brief parse the device descriptor - \param[in] dev_desc: device_descriptor destinaton address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len) -{ - dev_desc->Header.bLength = *(uint8_t *)(buf + 0U); - dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - dev_desc->bcdUSB = SWAPBYTE(buf + 2U); - dev_desc->bDeviceClass = *(uint8_t *)(buf + 4U); - dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5U); - dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6U); - dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7U); - - if (len > 8U){ - /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ - dev_desc->idVendor = SWAPBYTE(buf + 8U); - dev_desc->idProduct = SWAPBYTE(buf + 10U); - dev_desc->bcdDevice = SWAPBYTE(buf + 12U); - dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); - dev_desc->iProduct = *(uint8_t *)(buf + 15U); - dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); - dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); - } -} - -/*! - \brief parse the configuration descriptor - \param[in] cfg_desc: configuration descriptor address - \param[in] itf_desc: interface descriptor address - \param[in] ep_desc: endpoint descriptor address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len) -{ - usb_descriptor_interface_struct *pitf = NULL; - usb_descriptor_interface_struct temp_pitf; - usb_descriptor_endpoint_struct *pep = NULL; - usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf; - - uint8_t itf_ix = 0U; - uint8_t ep_ix = 0U; - uint16_t ptr = 0U; - static uint8_t prev_itf = 0U; - static uint16_t prev_ep_size = 0U; - - /* parse configuration descriptor */ - cfg_desc->Header.bLength = *(uint8_t *)(buf + 0U); - cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - cfg_desc->wTotalLength = SWAPBYTE(buf + 2U); - cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4U); - cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5U); - cfg_desc->iConfiguration = *(uint8_t *)(buf + 6U); - cfg_desc->bmAttributes = *(uint8_t *)(buf + 7U); - cfg_desc->bMaxPower = *(uint8_t *)(buf + 8U); - - if (len > USB_CFGDESC_SIZE) { - ptr = USB_CFG_DESC_LEN; - - if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) { - pitf = (usb_descriptor_interface_struct *)0U; - - for (; ptr < cfg_desc->wTotalLength; ) { - pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr); - - if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) { - itf_ix = *((uint8_t *)pdesc + 2U); - pitf = &itf_desc[itf_ix]; - - if (*((uint8_t *)pdesc + 3U) < 3U) { - usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc); - - /* parse endpoint descriptors relative to the current interface */ - if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) { - for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) { - pdesc = usbh_next_desc_get((void* )pdesc, &ptr); - - if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) { - pep = &ep_desc[itf_ix][ep_ix]; - - if (prev_itf != itf_ix) { - prev_itf = itf_ix; - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } else { - if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) { - break; - } else { - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } - } - - usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc); - prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4); - ep_ix++; - } - } - } - } - } - } - } - - prev_ep_size = 0U; - prev_itf = 0U; - } -} - -/*! - \brief parse the interface descriptor - \param[in] itf_desc: interface descriptor destination - \param[in] buf: buffer where the descriptor data is available - \param[out] none - \retval none -*/ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf) -{ - itf_desc->Header.bLength = *(uint8_t *)(buf + 0U); - itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2U); - itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3U); - itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4U); - itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5U); - itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6U); - itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7U); - itf_desc->iInterface = *(uint8_t *)(buf + 8U); -} - -/*! - \brief parse the endpoint descriptor - \param[in] ep_desc: endpoint descriptor destination address - \param[in] buf: buffer where the parsed descriptor stored - \param[out] none - \retval none -*/ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf) -{ - ep_desc->Header.bLength = *(uint8_t *)(buf + 0U); - ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2U); - ep_desc->bmAttributes = *(uint8_t *)(buf + 3U); - ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4U); - ep_desc->bInterval = *(uint8_t *)(buf + 6U); -} - -/*! - \brief parse the string descriptor - \param[in] psrc: source pointer containing the descriptor data - \param[in] pdest: destination address pointer - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len) -{ - uint16_t strlength; - uint16_t idx; - - /* the unicode string descriptor is not null-terminated. the string length is - computed by substracting two from the value of the first byte of the descriptor. - */ - - /* check which is lower size, the size of string or the length of bytes read from the device */ - - if (USB_DESCTYPE_STRING == psrc[1]){ - /* make sure the descriptor is string type */ - - /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ - strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len); - psrc += 2; /* adjust the offset ignoring the string len and descriptor type */ - - for (idx = 0U; idx < strlength; idx += 2U) { - /* copy only the string and ignore the unicode id, hence add the src */ - *pdest = psrc[idx]; - pdest++; - } - - *pdest = 0U; /* mark end of string */ - } -} - -/*! - \brief get the next descriptor header - \param[in] pbuf: pointer to buffer where the cfg descriptor is available - \param[in] ptr: data popinter inside the configuration descriptor - \param[out] none - \retval next descriptor header -*/ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr) -{ - uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength; - - usb_descriptor_header_struct *pnext; - - *ptr += len; - - pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len); - - return(pnext); -} - diff --git a/bsp/gd32105c-eval/Libraries/SConscript b/bsp/gd32105c-eval/Libraries/SConscript deleted file mode 100644 index b77e069f46..0000000000 --- a/bsp/gd32105c-eval/Libraries/SConscript +++ /dev/null @@ -1,33 +0,0 @@ -import rtconfig -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. - -src = Glob('GD32F10x_standard_peripheral/Source/*.c') -src += [cwd + '/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c'] - -#add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += [cwd + '/CMSIS/GD/GD32F10x/Source/GCC/startup_gd32f10x_cl.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [cwd + '/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += [cwd + '/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s'] - -path = [ - cwd + '/CMSIS/GD/GD32F10x/Include', - cwd + '/CMSIS', - cwd + '/GD32F10x_standard_peripheral/Include',] - -if GetDepend(['RT_USING_BSP_USB']): - path += [cwd + '/GD32F10x_usbfs_driver/Include'] - src += [cwd + '/GD32F10x_usbfs_driver/Source'] - -CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F10X_CL'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/gd32105c-eval/README.md b/bsp/gd32105c-eval/README.md deleted file mode 100644 index 3ae69f8226..0000000000 --- a/bsp/gd32105c-eval/README.md +++ /dev/null @@ -1,93 +0,0 @@ -# GD32105C-EVAL # - -## 1. 简介 - -[GD32105C-EVAL](http://gd32mcu.21ic.com)是兆易科技æ供的开å‘æ¿ï¼Œä½¿ç”¨ GD32F105VCT6 作为主控制器。æä¾›åŒ…æ‹¬æ‰©å±•å¼•è„šåœ¨å†…çš„åŠ SWD, Reset, Boot, User button key, LED, CAN, I2C, I2S, USART, RTC, LCD, SPI, ADC, DAC, EXMC, CTC, SDIO,USBD, GD-Link 等外设资æºã€‚ - -æ¿è½½ä¸»è¦èµ„æºå¦‚下： - -| 硬件 | æè¿° | -| -- | -- | -|CPU| Cortex-M3| -|主频| 120MHz | -|SRAM| 96KB | -|Flash| 256KB | - -## 2. 编译说明 - -GD32105C-EVALæ¿çº§åŒ…支æŒMDK5ã€IARå¼€å‘环境和GCC编译器，以下是具体版本信æ¯ï¼š - -| IDE/编译器 | 已测试版本 | -| -- | -- | -| MDK5 | MDK5.25 | -| IAR | IAR8.20 | -| GCC | GCC 5.4.1 20160919 (release) | - -## 3. 烧写åŠæ‰§è¡Œ - -供电方å¼ï¼šå¼€å‘æ¿ä½¿ç”¨ Mini USB 接å£æˆ–者 DC-005 连接器æä¾› 5V 电æºã€‚ - -下载程åºï¼šä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿éœ€è¦ä¸€å¥— JLink 或者使用 GD-Link 工具。 - -解决IDE "Missing Device(s)"问题" -* MDK5: 安装GigaDevice.GD32F10x_DFP.2.0.1.pack，在 Folder Selection 中的 Destination Folder 那一æ é€‰æ‹© Keil uVision5 软件的安装目录，如 C:\Keil_v5，然åŽåœ¨ Option for Target çš„ Device 选择对应的器件，åŒæ—¶åœ¨ Option forTarget çš„ C/C++中添加路径 C:\Keil_v5\ARM\Pack\ARM\CMSIS\4.2.0\CMSIS\Include。 - -* IAR：安装 IAR_GD32F10x_ADDON.2.0.0.exe - -### 3.1 é…置和仿真 - -工程已ç»é»˜è®¤ä½¿èƒ½äº†RT-Thread UART驱动ã€GPIO驱动ã€SPI驱动ã€I2C驱动。若想进一步é…置工程请 -使用ENV工具。 - -### 3.2 è¿è¡Œç»“æžœ - -打开MDK或者IAR工程，进入仿真åŽå…¨é€Ÿè¿è¡Œï¼Œå°†ä¼šåœ¨ä¸²å£0上看到RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š - -``` - \ | / -- RT - Thread Operating System - / | \ 4.0.4 build Aug 23 2021 - 2006 - 2021 Copyright by rt-thread team -msh > - -``` - -## 4. 驱动支æŒæƒ…况åŠè®¡åˆ’ - -| 驱动 | 支æŒæƒ…况 | 备注 | -| ------ | ---- | :------: | -| UART | æ”¯æŒ | UART0/1/2/3 | -| GPIO | æ”¯æŒ | | -| SPI | æ”¯æŒ | SPI0/1/2 | -| I2C | æ”¯æŒ | I2C0/1| - -### 4.1 IO在æ¿çº§æ”¯æŒåŒ…中的映射情况 - -| IOå· | æ¿çº§åŒ…中的定义 | -| -- | -- | -| PA9 | USART0 TX | -| PA10 | USART0 RX | -| PA2 | USART1 TX | -| PA3 | USART1 RX | -| PA5| SPI0 SCK | -| PA6 | SPI0 MISO | -| PA6 | SPI0 MOSI | -| PB13| SPI1 SCK | -| PB14 | SPI1 MISO | -| PB15 | SPI1 MOSI | -| PB6| I2C0 SCL | -| PB7 | I2C0 SDA | -| PB10| I2C1 SCL | -| PB11 | I2C1 SDA | - -## 5. è”ç³»äººä¿¡æ¯ - -维护人： - -- [lianzhian](https://gitee.com/qidiyun) - -## 6. å‚考 - -* [GD32105C-EVAL](http://gd32mcu.21ic.com/site) - - diff --git a/bsp/gd32105c-eval/SConscript b/bsp/gd32105c-eval/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/gd32105c-eval/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32105c-eval/SConstruct b/bsp/gd32105c-eval/SConstruct deleted file mode 100644 index 6712d0169f..0000000000 --- a/bsp/gd32105c-eval/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32105c-eval/applications/SConscript b/bsp/gd32105c-eval/applications/SConscript deleted file mode 100644 index 9bb9abae89..0000000000 --- a/bsp/gd32105c-eval/applications/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -from building import * -import os - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -list = os.listdir(cwd) -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - group = group + SConscript(os.path.join(item, 'SConscript')) - -Return('group') diff --git a/bsp/gd32105c-eval/applications/main.c b/bsp/gd32105c-eval/applications/main.c deleted file mode 100644 index 83b68664a3..0000000000 --- a/bsp/gd32105c-eval/applications/main.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-24 lianzhian first implementation - */ -#include -#include -#include - - -/* defined the LED0 pin: PF0 */ -#define LED0_PIN GET_PIN(C, 0) - -int main(void) -{ - int count = 1; - /* set LED0 pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - - while (count++) - { - rt_pin_write(LED0_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED0_PIN, PIN_LOW); - rt_thread_mdelay(500); - } - - return RT_EOK; -} - diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf deleted file mode 100644 index 27790e4197..0000000000 --- a/bsp/gd32105c-eval/board/linker_script/gd32_rom.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807ffff; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -export symbol __ICFEDIT_region_RAM_end__; - -define symbol __region_RAM1_start__ = 0x10000000; -define symbol __region_RAM1_end__ = 0x1000FFFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.ld b/bsp/gd32105c-eval/board/linker_script/gd32_rom.ld deleted file mode 100644 index 4af47d1dcb..0000000000 --- a/bsp/gd32105c-eval/board/linker_script/gd32_rom.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linker script for GD32F30x with GNU ld - * bernard.xiong 2009-10-14 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 512KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 64KB sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/gd32105c-eval/board/linker_script/gd32_rom.sct b/bsp/gd32105c-eval/board/linker_script/gd32_rom.sct deleted file mode 100644 index b3144a70e0..0000000000 --- a/bsp/gd32105c-eval/board/linker_script/gd32_rom.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x000040000 { ; load region size_region - ER_IROM1 0x08000000 0x000040000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00018000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/gd32105c-eval/drivers/Kconfig b/bsp/gd32105c-eval/drivers/Kconfig deleted file mode 100644 index 333a49bc25..0000000000 --- a/bsp/gd32105c-eval/drivers/Kconfig +++ /dev/null @@ -1,69 +0,0 @@ -menu "Hardware Drivers Config" - -menu "Onboard Peripheral Drivers" - -endmenu - -menu "On-chip Peripheral Drivers" - - config SOC_SERIES_GD32F1 - bool - default y - config SOC_GD32105C - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - select SOC_SERIES_GD32F1 - default y - - config RT_USING_USART0 - bool "Using USART0" - select RT_USING_SERIAL - default y - - config RT_USING_USART1 - bool "Using USART1" - select RT_USING_SERIAL - default n - - config RT_USING_USART2 - bool "Using USART2" - select RT_USING_SERIAL - default n - - config RT_USING_UART3 - bool "Using UART3" - select RT_USING_SERIAL - default n - - config RT_USING_SPI0 - bool "Using SPI0" - select RT_USING_SPI - default y - - config RT_USING_SPI1 - bool "Using SPI1" - select RT_USING_SPI - default n - - config RT_USING_SPI2 - bool "Using SPI2" - select RT_USING_SPI - default n - - config RT_USING_I2C0 - bool "Using I2C0" - select RT_USING_I2C - default n - - config RT_USING_I2C1 - bool "Using I2C1" - select RT_USING_I2C - default n -endmenu - -menu "Board extended module Drivers" - -endmenu - -endmenu diff --git a/bsp/gd32105c-eval/drivers/SConscript b/bsp/gd32105c-eval/drivers/SConscript deleted file mode 100644 index 77badf9a32..0000000000 --- a/bsp/gd32105c-eval/drivers/SConscript +++ /dev/null @@ -1,33 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drivers. -src = Split(""" -board.c -drv_usart.c -""") - -CPPPATH = [cwd] - -# add spi drivers. -if GetDepend('RT_USING_SPI'): - src += ['drv_spi.c'] - -# add i2c drivers. -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -# add pin drivers. -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -# add spi flash drivers. -if GetDepend('RT_USING_SFUD'): - src += ['drv_spi_flash.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32105c-eval/drivers/board.c b/bsp/gd32105c-eval/drivers/board.c deleted file mode 100644 index 528c166884..0000000000 --- a/bsp/gd32105c-eval/drivers/board.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include -#include - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while (1) - { - } - /* USER CODE END Error_Handler */ -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This function will initial GD32 board. - */ -void rt_hw_board_init() -{ - /* NVIC Configuration */ -#define NVIC_VTOR_MASK 0x3FFFFF80 -#ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); -#else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); -#endif - - SystemClock_Config(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/gd32105c-eval/drivers/board.h b/bsp/gd32105c-eval/drivers/board.h deleted file mode 100644 index 7b791f25c9..0000000000 --- a/bsp/gd32105c-eval/drivers/board.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include -#include "drv_gpio.h" - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#ifdef __ICCARM__ -// Use *.icf ram symbal, to avoid hardcode. -extern char __ICFEDIT_region_RAM_end__; -#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ -#else -#define GD32_SRAM_SIZE 96 -#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) -#endif - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif - -#define HEAP_END GD32_SRAM_END - -#endif - -//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32105c-eval/drivers/drv_comm.h b/bsp/gd32105c-eval/drivers/drv_comm.h deleted file mode 100644 index 0881776e60..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_comm.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __DRV_COMM_H__ -#define __DRV_COMM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_HWTIMER_H__ */ - diff --git a/bsp/gd32105c-eval/drivers/drv_gpio.c b/bsp/gd32105c-eval/drivers/drv_gpio.c deleted file mode 100644 index a4dd68ee17..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_gpio.c +++ /dev/null @@ -1,552 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include "drv_gpio.h" -#include -#include -#include "gd32f10x.h" -#include "gd32f10x_exti.h" - -#ifdef RT_USING_PIN - -#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \ - GPIO_PIN_##pin, GPIO_PORT_SOURCE_GPIO##port, GPIO_PIN_SOURCE_##pin} -#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} - -/* GD32 GPIO driver */ -struct pin_index -{ - rt_int16_t index; - rcu_periph_enum clk; - rt_uint32_t gpio_periph; - rt_uint32_t pin; - rt_uint8_t port_src; - rt_uint8_t pin_src; -}; - -static const struct pin_index pins[] = -{ - __GD32_PIN(0 , A, 0 ), - __GD32_PIN(1 , A, 1 ), - __GD32_PIN(2 , A, 2 ), - __GD32_PIN(3 , A, 3 ), - __GD32_PIN(4 , A, 4 ), - __GD32_PIN(5 , A, 5 ), - __GD32_PIN(6 , A, 6 ), - __GD32_PIN(7 , A, 7 ), - __GD32_PIN(8 , A, 8 ), - __GD32_PIN(9 , A, 9 ), - __GD32_PIN(10, A, 10), - __GD32_PIN(11, A, 11), - __GD32_PIN(12, A, 12), - __GD32_PIN(13, A, 13), - __GD32_PIN(14, A, 14), - __GD32_PIN(15, A, 15), - - __GD32_PIN(16, B, 0), - __GD32_PIN(17, B, 1), - __GD32_PIN(18, B, 2), - __GD32_PIN(19, B, 3), - __GD32_PIN(20, B, 4), - __GD32_PIN(21, B, 5), - __GD32_PIN(22, B, 6), - __GD32_PIN(23, B, 7), - __GD32_PIN(24, B, 8), - __GD32_PIN(25, B, 9), - __GD32_PIN(26, B, 10), - __GD32_PIN(27, B, 11), - __GD32_PIN(28, B, 12), - __GD32_PIN(29, B, 13), - __GD32_PIN(30, B, 14), - __GD32_PIN(31, B, 15), - - __GD32_PIN(32, C, 0), - __GD32_PIN(33, C, 1), - __GD32_PIN(34, C, 2), - __GD32_PIN(35, C, 3), - __GD32_PIN(36, C, 4), - __GD32_PIN(37, C, 5), - __GD32_PIN(38, C, 6), - __GD32_PIN(39, C, 7), - __GD32_PIN(40, C, 8), - __GD32_PIN(41, C, 9), - __GD32_PIN(42, C, 10), - __GD32_PIN(43, C, 11), - __GD32_PIN(44, C, 12), - __GD32_PIN(45, C, 13), - __GD32_PIN(46, C, 14), - __GD32_PIN(47, C, 15), - - __GD32_PIN(48, D, 0), - __GD32_PIN(49, D, 1), - __GD32_PIN(50, D, 2), - __GD32_PIN(51, D, 3), - __GD32_PIN(52, D, 4), - __GD32_PIN(53, D, 5), - __GD32_PIN(54, D, 6), - __GD32_PIN(55, D, 7), - __GD32_PIN(56, D, 8), - __GD32_PIN(57, D, 9), - __GD32_PIN(58, D, 10), - __GD32_PIN(59, D, 11), - __GD32_PIN(60, D, 12), - __GD32_PIN(61, D, 13), - __GD32_PIN(62, D, 14), - __GD32_PIN(63, D, 15), - - __GD32_PIN(64, E, 0), - __GD32_PIN(65, E, 1), - __GD32_PIN(66, E, 2), - __GD32_PIN(67, E, 3), - __GD32_PIN(68, E, 4), - __GD32_PIN(69, E, 5), - __GD32_PIN(70, E, 6), - __GD32_PIN(71, E, 7), - __GD32_PIN(72, E, 8), - __GD32_PIN(73, E, 9), - __GD32_PIN(74, E, 10), - __GD32_PIN(75, E, 11), - __GD32_PIN(76, E, 12), - __GD32_PIN(77, E, 13), - __GD32_PIN(78, E, 14), - __GD32_PIN(79, E, 15), - - __GD32_PIN(80, F, 0), - __GD32_PIN(81, F, 1), - __GD32_PIN(82, F, 2), - __GD32_PIN(83, F, 3), - __GD32_PIN(84, F, 4), - __GD32_PIN(85, F, 5), - __GD32_PIN(86, F, 6), - __GD32_PIN(87, F, 7), - __GD32_PIN(88, F, 8), - __GD32_PIN(89, F, 9), - __GD32_PIN(90, F, 10), - __GD32_PIN(91, F, 11), - __GD32_PIN(92, F, 12), - __GD32_PIN(93, F, 13), - __GD32_PIN(94, F, 14), - __GD32_PIN(95, F, 15), - - __GD32_PIN(96, G, 0), - __GD32_PIN(97, G, 1), - __GD32_PIN(98, G, 2), - __GD32_PIN(99, G, 3), - __GD32_PIN(100, G, 4), - __GD32_PIN(101, G, 5), - __GD32_PIN(102, G, 6), - __GD32_PIN(103, G, 7), - __GD32_PIN(104, G, 8), - __GD32_PIN(105, G, 9), - __GD32_PIN(106, G, 10), - __GD32_PIN(107, G, 11), - __GD32_PIN(108, G, 12), - __GD32_PIN(109, G, 13), - __GD32_PIN(110, G, 14), - __GD32_PIN(111, G, 15), - - -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI5_9_IRQn}, - {GPIO_PIN_6, EXTI5_9_IRQn}, - {GPIO_PIN_7, EXTI5_9_IRQn}, - {GPIO_PIN_8, EXTI5_9_IRQn}, - {GPIO_PIN_9, EXTI5_9_IRQn}, - {GPIO_PIN_10, EXTI10_15_IRQn}, - {GPIO_PIN_11, EXTI10_15_IRQn}, - {GPIO_PIN_12, EXTI10_15_IRQn}, - {GPIO_PIN_13, EXTI10_15_IRQn}, - {GPIO_PIN_14, EXTI10_15_IRQn}, - {GPIO_PIN_15, EXTI10_15_IRQn}, -}; -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(rt_uint8_t pin) -{ - const struct pin_index *index; - - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - - return index; -}; - -static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) -{ - const struct pin_index *index; - rt_uint32_t pin_mode; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* GPIO Periph clock enable */ - rcu_periph_clock_enable(index->clk); - pin_mode = GPIO_MODE_OUT_PP; - - switch(mode) - { - case PIN_MODE_OUTPUT: - /* output setting */ - pin_mode = GPIO_MODE_OUT_PP; - break; - case PIN_MODE_OUTPUT_OD: - /* output setting: od. */ - pin_mode = GPIO_MODE_OUT_OD; - break; - case PIN_MODE_INPUT: - /* input setting: not pull. */ - pin_mode = GPIO_MODE_IN_FLOATING; - break; - case PIN_MODE_INPUT_PULLUP: - /* input setting: pull up. */ - pin_mode = GPIO_MODE_IPU; - break; - case PIN_MODE_INPUT_PULLDOWN: - /* input setting: pull down. */ - pin_mode = GPIO_MODE_IPD; - break; - default: - break; - } - - gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); -} - -static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) -{ - const struct pin_index *index; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); -} - -static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) -{ - rt_int8_t value; - const struct pin_index *index; - - value = PIN_LOW; - - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - - value = gpio_input_bit_get(index->gpio_periph, index->pin); - - return value; -} - - -rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) -{ - rt_uint8_t i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { - return i; - } - } - return -1; -} -rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) -{ - rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; -static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == pin && - pin_irq_hdr_tab[hdr_index].hdr == hdr && - pin_irq_hdr_tab[hdr_index].mode == mode && - pin_irq_hdr_tab[hdr_index].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[hdr_index].pin != -1) - { - rt_hw_interrupt_enable(level); - return -RT_EFULL; - } - pin_irq_hdr_tab[hdr_index].pin = pin; - pin_irq_hdr_tab[hdr_index].hdr = hdr; - pin_irq_hdr_tab[hdr_index].mode = mode; - pin_irq_hdr_tab[hdr_index].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[hdr_index].pin = -1; - pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; - pin_irq_hdr_tab[hdr_index].mode = 0; - pin_irq_hdr_tab[hdr_index].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t hdr_index = -1; - exti_trig_type_enum trigger_mode; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - if (enabled == PIN_IRQ_ENABLE) - { - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - irqmap = &pin_irq_map[hdr_index]; - - switch (pin_irq_hdr_tab[hdr_index].mode) - { - case PIN_IRQ_MODE_RISING: - trigger_mode = EXTI_TRIG_RISING; - break; - case PIN_IRQ_MODE_FALLING: - trigger_mode = EXTI_TRIG_FALLING; - break; - case PIN_IRQ_MODE_RISING_FALLING: - trigger_mode = EXTI_TRIG_BOTH; - break; - default: - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - - rcu_periph_clock_enable(RCU_AF); - - /* enable and set interrupt priority */ - nvic_irq_enable(irqmap->irqno, 5U, 0U); - - /* connect EXTI line to GPIO pin */ - gpio_exti_source_select(index->port_src, index->pin_src); - - /* configure EXTI line */ - exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); - exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return -RT_EINVAL; - } - nvic_irq_disable(irqmap->irqno); - } - else - { - return -RT_EINVAL; - } - - return RT_EOK; -} -const static struct rt_pin_ops _gd32_pin_ops = -{ - _pin_mode, - _pin_write, - _pin_read, - _pin_attach_irq, - _pin_detach_irq, - _pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - - result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -rt_inline void pin_irq_hdr(int irqno) -{ - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) -{ - if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) - { - pin_irq_hdr(exti_line); - exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } -} -void EXTI0_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(0); - rt_interrupt_leave(); -} -void EXTI1_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(1); - rt_interrupt_leave(); -} -void EXTI2_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(2); - rt_interrupt_leave(); -} -void EXTI3_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(3); - rt_interrupt_leave(); -} -void EXTI4_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(4); - rt_interrupt_leave(); -} -void EXTI5_9_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(5); - GD32_GPIO_EXTI_IRQHandler(6); - GD32_GPIO_EXTI_IRQHandler(7); - GD32_GPIO_EXTI_IRQHandler(8); - GD32_GPIO_EXTI_IRQHandler(9); - rt_interrupt_leave(); -} -void EXTI10_15_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(10); - GD32_GPIO_EXTI_IRQHandler(11); - GD32_GPIO_EXTI_IRQHandler(12); - GD32_GPIO_EXTI_IRQHandler(13); - GD32_GPIO_EXTI_IRQHandler(14); - GD32_GPIO_EXTI_IRQHandler(15); - rt_interrupt_leave(); -} - -#endif diff --git a/bsp/gd32105c-eval/drivers/drv_gpio.h b/bsp/gd32105c-eval/drivers/drv_gpio.h deleted file mode 100644 index 0cdedb9acb..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_gpio.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __DRV_GPIO_H__ -#define __DRV_GPIO_H__ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define __GD32_PORT(port) GPIO##port - -#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN) - -#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) -#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) -#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) - -#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) - - - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/gd32105c-eval/drivers/drv_i2c.c b/bsp/gd32105c-eval/drivers/drv_i2c.c deleted file mode 100644 index a4216651cf..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_i2c.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#include "drv_i2c.h" -#include -#include "gd32f10x.h" - -#ifdef RT_USING_I2C - -#include - -#define DBG_TAG "drv.I2C" -#ifdef RT_I2C_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif -#include - -#ifdef RT_USING_I2C_BITOPS - -/*user can change this*/ -#define I2C_BUS_NAME "i2c2" - -/*user should change this to adapt specific board*/ -#define I2C_SCL_PIN GPIO_PIN_4 -#define I2C_SCL_PORT GPIOE -#define I2C_SCL_CLK RCU_GPIOE -#define I2C_SDA_PIN GPIO_PIN_5 -#define I2C_SDA_PORT GPIOE -#define I2C_SDA_CLK RCU_GPIOE - -struct gd32_i2c_bit_data -{ - struct - { - rcu_periph_enum clk; - rt_uint32_t port; - rt_uint32_t pin; - }scl, sda; -}; - -static void gpio_set_sda(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - - if (state) - { - gpio_bit_set(bd->sda.port, bd->sda.pin); - } - else - { - gpio_bit_reset(bd->sda.port, bd->sda.pin); - } -} - -static void gpio_set_scl(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - if (state) - { - gpio_bit_set(bd->scl.port, bd->scl.pin); - } - else - { - gpio_bit_reset(bd->scl.port, bd->scl.pin); - } -} - -static rt_int32_t gpio_get_sda(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->sda.port, bd->sda.pin); -} - -static rt_int32_t gpio_get_scl(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->scl.port, bd->scl.pin); -} - -static void gpio_udelay(rt_uint32_t us) -{ - int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us); - while(i) - { - i--; - } -} - -static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd) -{ - rcu_periph_clock_enable(bd->sda.clk); - rcu_periph_clock_enable(bd->scl.clk); - gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin); - gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin); - - gpio_bit_set(bd->sda.port, bd->sda.pin); - gpio_bit_set(bd->scl.port, bd->scl.pin); -} - -#else /* use hardware i2c */ - -struct gd32_i2c_bus -{ - struct rt_i2c_bus_device parent; - rt_uint32_t i2c_periph; -}; - -static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - if(1 == data_byte){ - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - - /* while there is data to be read */ - while(data_byte) - { - /* wait until the RBNE bit is set and clear it */ - if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) - { - /* read a byte from the EEPROM */ - *p_buffer = i2c_data_receive(i2c_periph); - - /* point to the next location where the byte read will be saved */ - p_buffer++; - - /* decrement the read bytes counter */ - data_byte--; - if(1 == data_byte) - { - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - } - } - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - /* enable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_ENABLE); - - i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT); - - return 0; -} - -static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - /* wait until the transmit data buffer is empty */ - while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE)); - - /* while there is data to be read */ - while(data_byte) - { - i2c_data_transmit(i2c_periph, *p_buffer); - - /* point to the next byte to be written */ - p_buffer++; - - /* decrement the write bytes counter */ - data_byte --; - - /* wait until BTC bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC)); - } - - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - return 0; -} - -static rt_ssize_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) -{ - struct rt_i2c_msg *msg; - rt_uint32_t i; - rt_err_t ret = -RT_ERROR; - - struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus; - - for (i = 0; i < num; i++) - { - msg = &msgs[i]; - - if (msg->flags & RT_I2C_ADDR_10BIT) - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0); - } - else - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0); - } - if (msg->flags & RT_I2C_RD) - { - if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - else - { - if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - } - - ret = i; - -out: - LOG_E("send stop condition\n"); - - return ret; -} - -static const struct rt_i2c_bus_device_ops i2c_ops = -{ - gd32_i2c_xfer, - RT_NULL, - RT_NULL -}; - -#endif /* RT_USING_I2C_BITOPS */ - -int rt_hw_i2c_init(void) -{ -#ifdef RT_USING_I2C_BITOPS - { - static struct rt_i2c_bus_device i2c_device; - static const struct gd32_i2c_bit_data _i2c_bdata = - { - /* SCL */ - { I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN}, - /* SDA */ - { I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN}, - }; - - static const struct rt_i2c_bit_ops _i2c_bit_ops = - { - (void*)&_i2c_bdata, - gpio_set_sda, - gpio_set_scl, - gpio_get_sda, - gpio_get_scl, - gpio_udelay, - 1, - 100 - }; - - drv_i2c_gpio_init(&_i2c_bdata); - - i2c_device.priv = (void *)&_i2c_bit_ops; - rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); - } - -#else /* register hardware I2C */ - -#ifdef RT_USING_I2C0 -#define I2C0_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c0; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */ - gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C0); - /* configure I2C clock */ - i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2); - - i2c_enable(I2C0); - /* enable acknowledge */ - i2c_ack_config(I2C0,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c0.parent.ops = &i2c_ops; - gd32_i2c0.i2c_periph = I2C0; - rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0"); -#endif - -#ifdef RT_USING_I2C1 -#define I2C1_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c1; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */ - gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C1); - /* configure I2C clock */ - i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2); - - i2c_enable(I2C1); - /* enable acknowledge */ - i2c_ack_config(I2C1,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c1.parent.ops = &i2c_ops; - gd32_i2c1.i2c_periph = I2C1; - rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1"); -#endif - -#endif /* RT_USING_I2C_BITOPS */ - - return 0; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); - -#endif -/* end of i2c driver */ diff --git a/bsp/gd32105c-eval/drivers/drv_i2c.h b/bsp/gd32105c-eval/drivers/drv_i2c.h deleted file mode 100644 index fb34ff2b09..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_i2c.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __DRV_I2C__ -#define __DRV_I2C__ - - -#endif diff --git a/bsp/gd32105c-eval/drivers/drv_spi.c b/bsp/gd32105c-eval/drivers/drv_spi.c deleted file mode 100644 index 7c52c37961..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_spi.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#include "drv_spi.h" -#include "gd32f10x.h" -#include - -#if defined(RT_USING_SPI) && defined(RT_USING_PIN) -#include - -#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \ - !defined(RT_USING_SPI2) -#error "Please define at least one SPIx" -#endif - -/* #define DEBUG */ -#ifdef DEBUG -#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) -#else -#define DEBUG_PRINTF(...) -#endif - -/* private rt-thread spi ops function */ -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); - -static struct rt_spi_ops gd32_spi_ops = -{ - configure, - xfer -}; - -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) -{ - spi_parameter_struct spi_init_struct; - - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); - - if(configuration->data_width <= 8) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; - } - else if(configuration->data_width <= 16) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; - } - else - { - return -RT_EIO; - } - - { - rcu_clock_freq_enum spi_src; - rt_uint32_t spi_apb_clock; - rt_uint32_t max_hz; - - max_hz = configuration->max_hz; - - DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS)); - DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2)); - DEBUG_PRINTF("max freq: %d\n", max_hz); - - if (spi_periph == SPI1 || spi_periph == SPI2) - { - spi_src = CK_APB1; - } - else - { - spi_src = CK_APB2; - } - spi_apb_clock = rcu_clock_freq_get(spi_src); - - if(max_hz >= spi_apb_clock/2) - { - spi_init_struct.prescale = SPI_PSC_2; - } - else if (max_hz >= spi_apb_clock/4) - { - spi_init_struct.prescale = SPI_PSC_4; - } - else if (max_hz >= spi_apb_clock/8) - { - spi_init_struct.prescale = SPI_PSC_8; - } - else if (max_hz >= spi_apb_clock/16) - { - spi_init_struct.prescale = SPI_PSC_16; - } - else if (max_hz >= spi_apb_clock/32) - { - spi_init_struct.prescale = SPI_PSC_32; - } - else if (max_hz >= spi_apb_clock/64) - { - spi_init_struct.prescale = SPI_PSC_64; - } - else if (max_hz >= spi_apb_clock/128) - { - spi_init_struct.prescale = SPI_PSC_128; - } - else - { - /* min prescaler 256 */ - spi_init_struct.prescale = SPI_PSC_256; - } - } /* baudrate */ - - switch(configuration->mode & RT_SPI_MODE_3) - { - case RT_SPI_MODE_0: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - break; - case RT_SPI_MODE_1: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; - case RT_SPI_MODE_2: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; - case RT_SPI_MODE_3: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; - break; - } - - /* MSB or LSB */ - if(configuration->mode & RT_SPI_MSB) - { - spi_init_struct.endian = SPI_ENDIAN_MSB; - } - else - { - spi_init_struct.endian = SPI_ENDIAN_LSB; - } - - spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_init_struct.device_mode = SPI_MASTER; - spi_init_struct.nss = SPI_NSS_SOFT; - - spi_init(spi_periph, &spi_init_struct); - - spi_crc_off(spi_periph); - - spi_enable(spi_periph); - - return RT_EOK; -}; - -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) -{ - rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data; - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - struct rt_spi_configuration * config = &device->config; - - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - - /* take CS */ - if(message->cs_take) - { - rt_pin_write(gd32_cs_pin, PIN_LOW); - DEBUG_PRINTF("spi take cs\n"); - } - - { - if(config->data_width <= 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - DEBUG_PRINTF("spi poll transfer start: %d\n", size); - - while(size--) - { - rt_uint8_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /* Todo: replace register read/write by gd32f3 lib */ - /* Wait until the transmit buffer is empty */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - /* Send the byte */ - spi_i2s_data_transmit(spi_periph, data); - - /* Wait until a data is received */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - /* Get the received data */ - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - DEBUG_PRINTF("spi poll transfer finsh\n"); - } - else if(config->data_width <= 16) - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - while(size--) - { - rt_uint16_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /*Wait until the transmit buffer is empty */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - /* Send the byte */ - spi_i2s_data_transmit(spi_periph, data); - - /*Wait until a data is received */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - /* Get the received data */ - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - } - } - - /* release CS */ - if(message->cs_release) - { - rt_pin_write(gd32_cs_pin, PIN_HIGH); - DEBUG_PRINTF("spi release cs\n"); - } - - return message->length; -}; - -int gd32_hw_spi_init(void) -{ - int result = 0; -#ifdef RT_USING_SPI0 - static struct rt_spi_bus spi_bus0; - spi_bus0.parent.user_data = (void *)SPI0; - - result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_SPI0); - /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */ - gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); - gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); - -#endif -#ifdef RT_USING_SPI1 - static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; - - result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_SPI1); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15); - gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14); -#endif -#ifdef RT_USING_SPI2 - static struct rt_spi_bus spi_bus2; - spi_bus2.parent.user_data = (void *)SPI2; - - result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_SPI2); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5); - gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); -#endif - return result; -} -INIT_BOARD_EXPORT(gd32_hw_spi_init); -#endif diff --git a/bsp/gd32105c-eval/drivers/drv_spi.h b/bsp/gd32105c-eval/drivers/drv_spi.h deleted file mode 100644 index b4d768c5f5..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_spi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef gd32F30X_SPI_H_INCLUDED -#define gd32F30X_SPI_H_INCLUDED - - -#endif /* gd32F30X_SPI_H_INCLUDED */ diff --git a/bsp/gd32105c-eval/drivers/drv_spi_flash.c b/bsp/gd32105c-eval/drivers/drv_spi_flash.c deleted file mode 100644 index 21a8b1c1d0..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_spi_flash.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include -#include "spi_flash.h" -#include "spi_flash_sfud.h" - -#define SPI_BUS_NAME "spi0" -#define SPI_DEVICE_NAME "spi01" -#define SPI_FLASH_DEVICE_NAME "gd25q" -#define GD25Q_SPI_CS_PIN 67 /* PE3，在 drv_gpio.c 文件 pin_index pins[]中查到 PE3 ç¼–å·ä¸º 67 */ - -static int rt_hw_gd25q40_init(void) -{ - rt_err_t res; - static struct rt_spi_device spi_dev_gd25q; /* SPI设备对象 */ - static rt_base_t gd25q_cs_pin; /* SPI设备CS片选引脚 */ - - gd25q_cs_pin = GD25Q_SPI_CS_PIN; - - rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP); - - res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin); - if (res != RT_EOK) - { - rt_kprintf("rt_spi_bus_attach_device() run failed!\n"); - return res; - } - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_gd25q40_init); - -static int rt_hw_spi_flash_with_sfud_init(void) -{ - if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_DEVICE_NAME, SPI_DEVICE_NAME)) - { - return -RT_ERROR; - } - - return RT_EOK; -} -INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); - -#ifdef RT_USING_DFS -#include - -int mnt_init(void) -{ - if (dfs_mount(SPI_FLASH_DEVICE_NAME, "/", "elm", 0, 0) == 0) - { - rt_kprintf("spi flash mount success !\n"); - } - else - { - rt_kprintf("spi flash mount failed!\n"); - } - - return 0; -} -MSH_CMD_EXPORT(mnt_init, mount spi flash to file system); -#endif diff --git a/bsp/gd32105c-eval/drivers/drv_usart.c b/bsp/gd32105c-eval/drivers/drv_usart.c deleted file mode 100644 index 6dbe467ab8..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_usart.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include -#include - -#ifdef RT_USING_SERIAL - -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \ - !defined(RT_USING_USART2) && !defined(RT_USING_UART3) && \ - !defined(RT_USING_UART4) -#error "Please define at least one UARTx" - -#endif - -#include - -/* GD32 uart driver */ -/* Todo: compress uart info */ -struct gd32_uart -{ - uint32_t uart_periph; - IRQn_Type irqn; - rcu_periph_enum per_clk; - rcu_periph_enum tx_gpio_clk; - rcu_periph_enum rx_gpio_clk; - uint32_t tx_port; - uint16_t tx_pin; - uint32_t rx_port; - uint16_t rx_pin; - - struct rt_serial_device * serial; - char *device_name; -}; - -static void uart_isr(struct rt_serial_device *serial); - -#if defined(RT_USING_USART0) -struct rt_serial_device serial0; - -void USART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial0); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_USART0 */ - -#if defined(RT_USING_USART1) -struct rt_serial_device serial1; - -void USART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial1); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART1 */ - -#if defined(RT_USING_USART2) -struct rt_serial_device serial2; - -void USART2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial2); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART2 */ - -#if defined(RT_USING_UART3) -struct rt_serial_device serial3; - -void UART3_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial3); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART3 */ - -#if defined(RT_USING_UART4) -struct rt_serial_device serial4; - -void UART4_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial4); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* RT_USING_UART4 */ - -static const struct gd32_uart uarts[] = { - #ifdef RT_USING_USART0 - { - USART0, /* uart peripheral index */ - USART0_IRQn, /* uart iqrn */ - RCU_USART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIO_PIN_9, /* tx port, tx pin */ - GPIOA, GPIO_PIN_10, /* rx port, rx pin */ - &serial0, - "uart0", - }, - #endif - - #ifdef RT_USING_USART1 - { - USART1, /* uart peripheral index */ - USART1_IRQn, /* uart iqrn */ - RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIO_PIN_2, /* tx port, tx pin */ - GPIOA, GPIO_PIN_3, /* rx port, rx pin */ - &serial1, - "uart1", - }, - #endif - - #ifdef RT_USING_USART2 - { - USART2, /* uart peripheral index */ - USART2_IRQn, /* uart iqrn */ - RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOB, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOB, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - &serial2, - "uart2", - }, - #endif - - #ifdef RT_USING_UART3 - { - UART3, /* uart peripheral index */ - UART3_IRQn, /* uart iqrn */ - RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOC, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOC, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - &serial3, - "uart3", - }, - #endif - - #ifdef RT_USING_UART4 - { - UART4, /* uart peripheral index */ - UART4_IRQn, /* uart iqrn */ - RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOC, GPIO_PIN_12, /* tx port, tx alternate, tx pin */ - GPIOD, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ - &serial4, - "uart4", - }, - #endif -}; - - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example: -* - Peripheral's clock enable -* - Peripheral's GPIO Configuration -* - NVIC configuration for UART interrupt request enable -* @param uart: UART handle pointer -* @retval None -*/ -void gd32_uart_gpio_init(struct gd32_uart *uart) -{ - /* enable USART clock */ - rcu_periph_clock_enable(uart->tx_gpio_clk); - rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); - - /* connect port to USARTx_Tx */ - gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ - gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); - - NVIC_SetPriority(uart->irqn, 0); - NVIC_EnableIRQ(uart->irqn); -} - -static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = (struct gd32_uart *)serial->parent.user_data; - - gd32_uart_gpio_init(uart); - - usart_baudrate_set(uart->uart_periph, cfg->baud_rate); - - switch (cfg->data_bits) - { - case DATA_BITS_9: - usart_word_length_set(uart->uart_periph, USART_WL_9BIT); - break; - - default: - usart_word_length_set(uart->uart_periph, USART_WL_8BIT); - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT); - break; - default: - usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT); - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - usart_parity_config(uart->uart_periph, USART_PM_ODD); - break; - case PARITY_EVEN: - usart_parity_config(uart->uart_periph, USART_PM_EVEN); - break; - default: - usart_parity_config(uart->uart_periph, USART_PM_NONE); - break; - } - - usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE); - usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE); - usart_enable(uart->uart_periph); - - return RT_EOK; -} - -static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irqn); - /* disable interrupt */ - usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); - - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irqn); - /* enable interrupt */ - usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); - break; - } - - return RT_EOK; -} - -static int _uart_putc(struct rt_serial_device *serial, char ch) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - usart_data_transmit(uart->uart_periph, ch); - while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - - return 1; -} - -static int _uart_getc(struct rt_serial_device *serial) -{ - int ch; - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - ch = -1; - if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET) - ch = usart_data_receive(uart->uart_periph); - return ch; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) -{ - struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; - - RT_ASSERT(uart != RT_NULL); - - /* UART in mode Receiver */ - if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && - (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - /* Clear RXNE interrupt flag */ - usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE); - } -} - -static const struct rt_uart_ops gd32_uart_ops = -{ - _uart_configure, - _uart_control, - _uart_putc, - _uart_getc -}; - -int gd32_hw_usart_init(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - int i; - - for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) - { - uarts[i].serial->ops = &gd32_uart_ops; - uarts[i].serial->config = config; - - /* register UART device */ - rt_hw_serial_register(uarts[i].serial, - uarts[i].device_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&uarts[i]); - } - - return 0; -} -INIT_BOARD_EXPORT(gd32_hw_usart_init); -#endif diff --git a/bsp/gd32105c-eval/drivers/drv_usart.h b/bsp/gd32105c-eval/drivers/drv_usart.h deleted file mode 100644 index f575ad3810..0000000000 --- a/bsp/gd32105c-eval/drivers/drv_usart.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __USART_H__ -#define __USART_H__ - - -#endif diff --git a/bsp/gd32105c-eval/drivers/gd32f10x_libopt.h b/bsp/gd32105c-eval/drivers/gd32f10x_libopt.h deleted file mode 100644 index a4dd11b017..0000000000 --- a/bsp/gd32105c-eval/drivers/gd32f10x_libopt.h +++ /dev/null @@ -1,67 +0,0 @@ -/*! - \file gd32f10x_libopt.h - \brief library optional for gd32f10x - \version 2014-12-26, V1.0.0, demo for GD32F10x - \version 2017-06-30, V2.0.0, demo for GD32F10x - \version 2018-07-31, V2.1.0, demo for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_LIBOPT_H -#define GD32F10X_LIBOPT_H - -#include "gd32f10x_rcu.h" -#include "gd32f10x_adc.h" -#include "gd32f10x_can.h" -#include "gd32f10x_crc.h" -#include "gd32f10x_dac.h" -#include "gd32f10x_dbg.h" -#include "gd32f10x_dma.h" -#include "gd32f10x_exti.h" -#include "gd32f10x_fmc.h" -#include "gd32f10x_fwdgt.h" -#include "gd32f10x_gpio.h" -#include "gd32f10x_i2c.h" -#include "gd32f10x_pmu.h" -#include "gd32f10x_bkp.h" -#include "gd32f10x_rtc.h" -#include "gd32f10x_sdio.h" -#include "gd32f10x_spi.h" -#include "gd32f10x_timer.h" -#include "gd32f10x_usart.h" -#include "gd32f10x_wwdgt.h" -#include "gd32f10x_misc.h" -#include "gd32f10x_exmc.h" -#ifdef GD32F10X_CL -#include "gd32f10x_enet.h" -#endif /* GD32F10X_CL */ - -#endif /* GD32F10X_LIBOPT_H */ diff --git a/bsp/gd32105c-eval/list/context_rvds.lst b/bsp/gd32105c-eval/list/context_rvds.lst deleted file mode 100644 index 2993bc3ddf..0000000000 --- a/bsp/gd32105c-eval/list/context_rvds.lst +++ /dev/null @@ -1,520 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;/* - 2 00000000 ; * Copyright (c) 2006-2022, RT-Thread Development Team - 3 00000000 ; * - 4 00000000 ; * SPDX-License-Identifier: Apache-2.0 - 5 00000000 ; * - 6 00000000 ; * Change Logs: - 7 00000000 ; * Date Author Notes - 8 00000000 ; * 2009-01-17 Bernard first version - 9 00000000 ; * 2013-06-18 aozima add restore MSP feature. - - 10 00000000 ; * 2013-07-09 aozima enhancement hard fault e - xception handler. - 11 00000000 ; */ - 12 00000000 - 13 00000000 ;/** - 14 00000000 ; * @addtogroup CORTEX-M3 - 15 00000000 ; */ - 16 00000000 ;/*@{*/ - 17 00000000 - 18 00000000 E000ED08 - SCB_VTOR - EQU 0xE000ED08 ; Vector Table Offs - et Register - 19 00000000 E000ED04 - NVIC_INT_CTRL - EQU 0xE000ED04 ; interrupt control - state register - 20 00000000 E000ED20 - NVIC_SYSPRI2 - EQU 0xE000ED20 ; system priority r - egister (2) - 21 00000000 FFFF0000 - NVIC_PENDSV_PRI - EQU 0xFFFF0000 ; PendSV and SysTic - k priority value (l - owest) - 22 00000000 10000000 - NVIC_PENDSVSET - EQU 0x10000000 ; value to trigger - PendSV exception - 23 00000000 - 24 00000000 AREA |.text|, CODE, READONLY, ALIGN= -2 - 25 00000000 THUMB - 26 00000000 REQUIRE8 - 27 00000000 PRESERVE8 - 28 00000000 - 29 00000000 IMPORT rt_thread_switch_interrupt_flag - 30 00000000 IMPORT rt_interrupt_from_thread - 31 00000000 IMPORT rt_interrupt_to_thread - 32 00000000 - 33 00000000 ;/* - 34 00000000 ; * rt_base_t rt_hw_interrupt_disable(); - 35 00000000 ; */ - 36 00000000 rt_hw_interrupt_disable - PROC - 37 00000000 EXPORT rt_hw_interrupt_disable - 38 00000000 F3EF 8010 MRS r0, PRIMASK - 39 00000004 B672 CPSID I - - - -ARM Macro Assembler Page 2 - - - 40 00000006 4770 BX LR - 41 00000008 ENDP - 42 00000008 - 43 00000008 ;/* - 44 00000008 ; * void rt_hw_interrupt_enable(rt_base_t level); - 45 00000008 ; */ - 46 00000008 rt_hw_interrupt_enable - PROC - 47 00000008 EXPORT rt_hw_interrupt_enable - 48 00000008 F380 8810 MSR PRIMASK, r0 - 49 0000000C 4770 BX LR - 50 0000000E ENDP - 51 0000000E - 52 0000000E ;/* - 53 0000000E ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 - to); - 54 0000000E ; * r0 --> from - 55 0000000E ; * r1 --> to - 56 0000000E ; */ - 57 0000000E rt_hw_context_switch_interrupt - 58 0000000E EXPORT rt_hw_context_switch_interrupt - 59 0000000E rt_hw_context_switch - PROC - 60 0000000E EXPORT rt_hw_context_switch - 61 0000000E - 62 0000000E ; set rt_thread_switch_interrupt_flag to 1 - 63 0000000E 4A34 LDR r2, =rt_thread_switch_interrupt -_flag - 64 00000010 6813 LDR r3, [r2] - 65 00000012 2B01 CMP r3, #1 - 66 00000014 D004 BEQ _reswitch - 67 00000016 F04F 0301 MOV r3, #1 - 68 0000001A 6013 STR r3, [r2] - 69 0000001C - 70 0000001C 4A31 LDR r2, =rt_interrupt_from_thread ; - set rt_interrupt_f - rom_thread - 71 0000001E 6010 STR r0, [r2] - 72 00000020 - 73 00000020 _reswitch - 74 00000020 4A31 LDR r2, =rt_interrupt_to_thread ; s - et rt_interrupt_to_ - thread - 75 00000022 6011 STR r1, [r2] - 76 00000024 - 77 00000024 4831 LDR r0, =NVIC_INT_CTRL ; trigger th - e PendSV exception - (causes context swi - tch) - 78 00000026 F04F 5180 LDR r1, =NVIC_PENDSVSET - 79 0000002A 6001 STR r1, [r0] - 80 0000002C 4770 BX LR - 81 0000002E ENDP - 82 0000002E - 83 0000002E ; r0 --> switch from thread stack - 84 0000002E ; r1 --> switch to thread stack - 85 0000002E ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from - ] stack - 86 0000002E PendSV_Handler - - - -ARM Macro Assembler Page 3 - - - PROC - 87 0000002E EXPORT PendSV_Handler - 88 0000002E - 89 0000002E ; disable interrupt to protect context switch - 90 0000002E F3EF 8210 MRS r2, PRIMASK - 91 00000032 B672 CPSID I - 92 00000034 - 93 00000034 ; get rt_thread_switch_interrupt_flag - 94 00000034 482A LDR r0, =rt_thread_switch_interrupt -_flag - 95 00000036 6801 LDR r1, [r0] - 96 00000038 B191 CBZ r1, pendsv_exit ; pendsv alread - y handled - 97 0000003A - 98 0000003A ; clear rt_thread_switch_interrupt_flag to 0 - 99 0000003A F04F 0100 MOV r1, #0x00 - 100 0000003E 6001 STR r1, [r0] - 101 00000040 - 102 00000040 4828 LDR r0, =rt_interrupt_from_thread - 103 00000042 6801 LDR r1, [r0] - 104 00000044 B129 CBZ r1, switch_to_thread ; skip reg - ister save at the f - irst time - 105 00000046 - 106 00000046 F3EF 8109 MRS r1, psp ; get from thread s - tack pointer - 107 0000004A E921 0FF0 STMFD r1!, {r4 - r11} ; push r4 - r11 - register - 108 0000004E 6800 LDR r0, [r0] - 109 00000050 6001 STR r1, [r0] ; update from threa - d stack pointer - 110 00000052 - 111 00000052 switch_to_thread - 112 00000052 4925 LDR r1, =rt_interrupt_to_thread - 113 00000054 6809 LDR r1, [r1] - 114 00000056 6809 LDR r1, [r1] ; load thread stack - pointer - 115 00000058 - 116 00000058 E8B1 0FF0 LDMFD r1!, {r4 - r11} ; pop r4 - r11 - register - 117 0000005C F381 8809 MSR psp, r1 ; update stack poin - ter - 118 00000060 - 119 00000060 pendsv_exit - 120 00000060 ; restore interrupt - 121 00000060 F382 8810 MSR PRIMASK, r2 - 122 00000064 - 123 00000064 F04E 0E04 ORR lr, lr, #0x04 - 124 00000068 4770 BX lr - 125 0000006A ENDP - 126 0000006A - 127 0000006A ;/* - 128 0000006A ; * void rt_hw_context_switch_to(rt_uint32 to); - 129 0000006A ; * r0 --> to - 130 0000006A ; * this fucntion is used to perform the first thread sw - itch - 131 0000006A ; */ - 132 0000006A rt_hw_context_switch_to - PROC - - - -ARM Macro Assembler Page 4 - - - 133 0000006A EXPORT rt_hw_context_switch_to - 134 0000006A ; set to thread - 135 0000006A 491F LDR r1, =rt_interrupt_to_thread - 136 0000006C 6008 STR r0, [r1] - 137 0000006E - 138 0000006E ; set from thread to 0 - 139 0000006E 491D LDR r1, =rt_interrupt_from_thread - 140 00000070 F04F 0000 MOV r0, #0x0 - 141 00000074 6008 STR r0, [r1] - 142 00000076 - 143 00000076 ; set interrupt flag to 1 - 144 00000076 491A LDR r1, =rt_thread_switch_interrupt -_flag - 145 00000078 F04F 0001 MOV r0, #1 - 146 0000007C 6008 STR r0, [r1] - 147 0000007E - 148 0000007E ; set the PendSV and SysTick exception priority - 149 0000007E 481C LDR r0, =NVIC_SYSPRI2 - 150 00000080 491C LDR r1, =NVIC_PENDSV_PRI - 151 00000082 F8D0 2000 LDR.W r2, [r0,#0x00] ; read - 152 00000086 EA41 0102 ORR r1,r1,r2 ; modify - 153 0000008A 6001 STR r1, [r0] ; write-back - 154 0000008C - 155 0000008C ; trigger the PendSV exception (causes context switch) - 156 0000008C 4817 LDR r0, =NVIC_INT_CTRL - 157 0000008E F04F 5180 LDR r1, =NVIC_PENDSVSET - 158 00000092 6001 STR r1, [r0] - 159 00000094 - 160 00000094 ; restore MSP - 161 00000094 4818 LDR r0, =SCB_VTOR - 162 00000096 6800 LDR r0, [r0] - 163 00000098 6800 LDR r0, [r0] - 164 0000009A F380 8808 MSR msp, r0 - 165 0000009E - 166 0000009E ; enable interrupts at processor level - 167 0000009E B661 CPSIE F - 168 000000A0 B662 CPSIE I - 169 000000A2 - 170 000000A2 ; ensure PendSV exception taken place before subsequent - operation - 171 000000A2 F3BF 8F4F DSB - 172 000000A6 F3BF 8F6F ISB - 173 000000AA - 174 000000AA ; never reach here! - 175 000000AA ENDP - 176 000000AA - 177 000000AA ; compatible with old version - 178 000000AA rt_hw_interrupt_thread_switch - PROC - 179 000000AA EXPORT rt_hw_interrupt_thread_switch - 180 000000AA 4770 BX lr - 181 000000AC ENDP - 182 000000AC - 183 000000AC IMPORT rt_hw_hard_fault_exception - 184 000000AC EXPORT HardFault_Handler - 185 000000AC HardFault_Handler - PROC - 186 000000AC - 187 000000AC ; get current context - - - -ARM Macro Assembler Page 5 - - - 188 000000AC F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] - ) - 189 000000B0 BF0C ITE EQ - 190 000000B2 F3EF 8008 MRSEQ r0, msp ; [2]=0 ==> Z=1, ge - t fault context fro - m handler. - 191 000000B6 F3EF 8009 MRSNE r0, psp ; [2]=1 ==> Z=0, ge - t fault context fro - m thread. - 192 000000BA - 193 000000BA E920 0FF0 STMFD r0!, {r4 - r11} ; push r4 - r11 - register - 194 000000BE F840 ED04 STMFD r0!, {lr} ; push exec_return - register - 195 000000C2 - 196 000000C2 F01E 0F04 TST lr, #0x04 ; if(!EXC_RETURN[2] - ) - 197 000000C6 BF0C ITE EQ - 198 000000C8 F380 8808 MSREQ msp, r0 ; [2]=0 ==> Z=1, up - date stack pointer - to MSP. - 199 000000CC F380 8809 MSRNE psp, r0 ; [2]=1 ==> Z=0, up - date stack pointer - to PSP. - 200 000000D0 - 201 000000D0 B500 PUSH {lr} - 202 000000D2 F7FF FFFE BL rt_hw_hard_fault_exception - 203 000000D6 F85D EB04 POP {lr} - 204 000000DA - 205 000000DA F04E 0E04 ORR lr, lr, #0x04 - 206 000000DE 4770 BX lr - 207 000000E0 ENDP - 208 000000E0 - 209 000000E0 ALIGN 4 - 210 000000E0 - 211 000000E0 END - 00000000 - 00000000 - 00000000 - E000ED04 - E000ED20 - FFFF0000 - E000ED08 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=.\output\context_rvds.d -o.\output\context_rvds.o -I.\RTE\_rt-thre -ad_gd32f105 -ID:\software\KEIL_V5_ArmPacks\GigaDevice\GD32F10x_DFP\2.0.3\Device -\Include -ID:\software\KEIL_V5\ARM\CMSIS\Include --predefine="__MICROLIB SETA 1 -" --predefine="__UVISION_VERSION SETA 530" --predefine="GD32F10X_CL SETA 1" --p -redefine="USE_STDPERIPH_DRIVER SETA 1" --predefine="_RTE_ SETA 1" --list=.\list -\context_rvds.lst ..\..\libcpu\arm\cortex-m3\context_rvds.S - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 24 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - None -Comment: .text unused -HardFault_Handler 000000AC - -Symbol: HardFault_Handler - Definitions - At line 185 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 184 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: HardFault_Handler used once -PendSV_Handler 0000002E - -Symbol: PendSV_Handler - Definitions - At line 86 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 87 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: PendSV_Handler used once -_reswitch 00000020 - -Symbol: _reswitch - Definitions - At line 73 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 66 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: _reswitch used once -pendsv_exit 00000060 - -Symbol: pendsv_exit - Definitions - At line 119 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 96 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: pendsv_exit used once -rt_hw_context_switch 0000000E - -Symbol: rt_hw_context_switch - Definitions - At line 59 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 60 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: rt_hw_context_switch used once -rt_hw_context_switch_interrupt 0000000E - -Symbol: rt_hw_context_switch_interrupt - Definitions - At line 57 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 58 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: rt_hw_context_switch_interrupt used once -rt_hw_context_switch_to 0000006A - -Symbol: rt_hw_context_switch_to - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - - Definitions - At line 132 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 133 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: rt_hw_context_switch_to used once -rt_hw_interrupt_disable 00000000 - -Symbol: rt_hw_interrupt_disable - Definitions - At line 36 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 37 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: rt_hw_interrupt_disable used once -rt_hw_interrupt_enable 00000008 - -Symbol: rt_hw_interrupt_enable - Definitions - At line 46 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 47 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: rt_hw_interrupt_enable used once -rt_hw_interrupt_thread_switch 000000AA - -Symbol: rt_hw_interrupt_thread_switch - Definitions - At line 178 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 179 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: rt_hw_interrupt_thread_switch used once -switch_to_thread 00000052 - -Symbol: switch_to_thread - Definitions - At line 111 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 104 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: switch_to_thread used once -12 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -NVIC_INT_CTRL E000ED04 - -Symbol: NVIC_INT_CTRL - Definitions - At line 19 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 77 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 156 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - -NVIC_PENDSVSET 10000000 - -Symbol: NVIC_PENDSVSET - Definitions - At line 22 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 78 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 157 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - -NVIC_PENDSV_PRI FFFF0000 - -Symbol: NVIC_PENDSV_PRI - Definitions - At line 21 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 150 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: NVIC_PENDSV_PRI used once -NVIC_SYSPRI2 E000ED20 - -Symbol: NVIC_SYSPRI2 - Definitions - At line 20 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 149 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: NVIC_SYSPRI2 used once -SCB_VTOR E000ED08 - -Symbol: SCB_VTOR - Definitions - At line 18 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 161 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: SCB_VTOR used once -5 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -rt_hw_hard_fault_exception 00000000 - -Symbol: rt_hw_hard_fault_exception - Definitions - At line 183 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 202 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S -Comment: rt_hw_hard_fault_exception used once -rt_interrupt_from_thread 00000000 - -Symbol: rt_interrupt_from_thread - Definitions - At line 30 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 70 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 102 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 139 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - -rt_interrupt_to_thread 00000000 - -Symbol: rt_interrupt_to_thread - Definitions - At line 31 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 74 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 112 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 135 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - -rt_thread_switch_interrupt_flag 00000000 - -Symbol: rt_thread_switch_interrupt_flag - Definitions - At line 29 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - Uses - At line 63 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 94 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - At line 144 in file ..\..\libcpu\arm\cortex-m3\context_rvds.S - -4 symbols -358 symbols in table diff --git a/bsp/gd32105c-eval/list/startup_gd32f10x_cl.lst b/bsp/gd32105c-eval/list/startup_gd32f10x_cl.lst deleted file mode 100644 index 739f2b33d1..0000000000 --- a/bsp/gd32105c-eval/list/startup_gd32f10x_cl.lst +++ /dev/null @@ -1,1851 +0,0 @@ - - - -ARM Macro Assembler Page 1 - - - 1 00000000 ;/*! - 2 00000000 ; \file startup_gd32f10x_cl.s - 3 00000000 ; \brief start up file - 4 00000000 ; - 5 00000000 ; \version 2014-12-26, V1.0.0, firmware for GD32F10x - 6 00000000 ; \version 2017-06-20, V2.0.0, firmware for GD32F10x - 7 00000000 ; \version 2018-07-31, V2.1.0, firmware for GD32F10x - 8 00000000 ;*/ - 9 00000000 ; - 10 00000000 ;/* - 11 00000000 ; Copyright (c) 2018, GigaDevice Semiconductor Inc. - 12 00000000 ; - 13 00000000 ; All rights reserved. - 14 00000000 ; - 15 00000000 ; Redistribution and use in source and binary forms, - with or without modification, - 16 00000000 ;are permitted provided that the following conditions ar - e met: - 17 00000000 ; - 18 00000000 ; 1. Redistributions of source code must retain the a - bove copyright notice, this - 19 00000000 ; list of conditions and the following disclaimer. - - 20 00000000 ; 2. Redistributions in binary form must reproduce th - e above copyright notice, - 21 00000000 ; this list of conditions and the following discla - imer in the documentation - 22 00000000 ; and/or other materials provided with the distrib - ution. - 23 00000000 ; 3. Neither the name of the copyright holder nor the - names of its contributors - 24 00000000 ; may be used to endorse or promote products deriv - ed from this software without - 25 00000000 ; specific prior written permission. - 26 00000000 ; - 27 00000000 ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS - AND CONTRIBUTORS "AS IS" - 28 00000000 ;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT N - OT LIMITED TO, THE IMPLIED - 29 00000000 ;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICU - LAR PURPOSE ARE DISCLAIMED. - 30 00000000 ;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS - BE LIABLE FOR ANY DIRECT, - 31 00000000 ;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENT - IAL DAMAGES (INCLUDING, BUT - 32 00000000 ;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERV - ICES; LOSS OF USE, DATA, OR - 33 00000000 ;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND O - N ANY THEORY OF LIABILITY, - 34 00000000 ;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDI - NG NEGLIGENCE OR OTHERWISE) - 35 00000000 ;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVE - N IF ADVISED OF THE POSSIBILITY - 36 00000000 ;OF SUCH DAMAGE. - 37 00000000 ;*/ - 38 00000000 - 39 00000000 ; Stack Configuration - 40 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> - 41 00000000 ; - - - -ARM Macro Assembler Page 2 - - - 42 00000000 - 43 00000000 00002000 - Stack_Size - EQU 0x00002000 - 44 00000000 - 45 00000000 AREA STACK, NOINIT, READWRITE, ALIGN - = 3 - 46 00000000 Stack_Mem - SPACE Stack_Size - 47 00002000 __initial_sp - 48 00002000 - 49 00002000 - 50 00002000 ; Heap Configuration - 51 00002000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> - 52 00002000 ; - 53 00002000 - 54 00002000 00002000 - Heap_Size - EQU 0x00002000 - 55 00002000 - 56 00002000 AREA HEAP, NOINIT, READWRITE, ALIGN -= 3 - 57 00000000 __heap_base - 58 00000000 Heap_Mem - SPACE Heap_Size - 59 00002000 __heap_limit - 60 00002000 - 61 00002000 - 62 00002000 PRESERVE8 - 63 00002000 THUMB - 64 00002000 - 65 00002000 ; /* reset Vector Mapped to at Address - 0 */ - 66 00002000 AREA RESET, DATA, READONLY - 67 00000000 EXPORT __Vectors - 68 00000000 EXPORT __Vectors_End - 69 00000000 EXPORT __Vectors_Size - 70 00000000 - 71 00000000 00000000 - __Vectors - DCD __initial_sp ; Top of Stack - 72 00000004 00000000 DCD Reset_Handler ; Reset Handler - 73 00000008 00000000 DCD NMI_Handler ; NMI Handler - 74 0000000C 00000000 DCD HardFault_Handler ; Hard Fault - Handler - 75 00000010 00000000 DCD MemManage_Handler - ; MPU Fault Handler - - 76 00000014 00000000 DCD BusFault_Handler - ; Bus Fault Handler - - 77 00000018 00000000 DCD UsageFault_Handler ; Usage Faul - t Handler - 78 0000001C 00000000 DCD 0 ; Reserved - 79 00000020 00000000 DCD 0 ; Reserved - 80 00000024 00000000 DCD 0 ; Reserved - 81 00000028 00000000 DCD 0 ; Reserved - 82 0000002C 00000000 DCD SVC_Handler ; SVCall Handler - 83 00000030 00000000 DCD DebugMon_Handler ; Debug Monito - - - -ARM Macro Assembler Page 3 - - - r Handler - 84 00000034 00000000 DCD 0 ; Reserved - 85 00000038 00000000 DCD PendSV_Handler ; PendSV Handler - - 86 0000003C 00000000 DCD SysTick_Handler - ; SysTick Handler - 87 00000040 - 88 00000040 ; /* external interrupts handler */ - 89 00000040 00000000 DCD WWDGT_IRQHandler ; 16:Window Wa - tchdog Timer - 90 00000044 00000000 DCD LVD_IRQHandler ; 17:LVD through - EXTI Line detect - 91 00000048 00000000 DCD TAMPER_IRQHandler ; 18:Tamper I - nterrupt - 92 0000004C 00000000 DCD RTC_IRQHandler ; 19:RTC through - EXTI Line - 93 00000050 00000000 DCD FMC_IRQHandler ; 20:FMC - 94 00000054 00000000 DCD RCU_IRQHandler ; 21:RCU - 95 00000058 00000000 DCD EXTI0_IRQHandler - ; 22:EXTI Line 0 - 96 0000005C 00000000 DCD EXTI1_IRQHandler - ; 23:EXTI Line 1 - 97 00000060 00000000 DCD EXTI2_IRQHandler - ; 24:EXTI Line 2 - 98 00000064 00000000 DCD EXTI3_IRQHandler - ; 25:EXTI Line 3 - 99 00000068 00000000 DCD EXTI4_IRQHandler - ; 26:EXTI Line 4 - 100 0000006C 00000000 DCD DMA0_Channel0_IRQHandler - ; 27:DMA0 Channel 0 - - 101 00000070 00000000 DCD DMA0_Channel1_IRQHandler - ; 28:DMA0 Channel 1 - - 102 00000074 00000000 DCD DMA0_Channel2_IRQHandler - ; 29:DMA0 Channel 2 - - 103 00000078 00000000 DCD DMA0_Channel3_IRQHandler - ; 30:DMA0 Channel 3 - - 104 0000007C 00000000 DCD DMA0_Channel4_IRQHandler - ; 31:DMA0 Channel 4 - - 105 00000080 00000000 DCD DMA0_Channel5_IRQHandler ; 32:D - MA0 Channel 5 - 106 00000084 00000000 DCD DMA0_Channel6_IRQHandler - ; 33:DMA0 Channel 6 - - 107 00000088 00000000 DCD ADC0_1_IRQHandler - ; 34:ADC0 and ADC1 - 108 0000008C 00000000 DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - - 109 00000090 00000000 DCD CAN0_RX0_IRQHandler - ; 36:CAN0 RX0 - 110 00000094 00000000 DCD CAN0_RX1_IRQHandler - ; 37:CAN0 RX1 - 111 00000098 00000000 DCD CAN0_EWMC_IRQHandler - ; 38:CAN0 EWMC - 112 0000009C 00000000 DCD EXTI5_9_IRQHandler ; 39:EXTI Li - - - -ARM Macro Assembler Page 4 - - - ne 5 to EXTI Line 9 - - 113 000000A0 00000000 DCD TIMER0_BRK_IRQHandler - ; 40:TIMER0 Break - 114 000000A4 00000000 DCD TIMER0_UP_IRQHandler - ; 41:TIMER0 Update - 115 000000A8 00000000 DCD TIMER0_TRG_CMT_IRQHandler ; 42: - TIMER0 Trigger and - Commutation - 116 000000AC 00000000 DCD TIMER0_Channel_IRQHandler ; 43: - TIMER0 Channel Capt - ure Compare - 117 000000B0 00000000 DCD TIMER1_IRQHandler ; 44:TIMER1 - 118 000000B4 00000000 DCD TIMER2_IRQHandler ; 45:TIMER2 - 119 000000B8 00000000 DCD TIMER3_IRQHandler ; 46:TIMER3 - 120 000000BC 00000000 DCD I2C0_EV_IRQHandler - ; 47:I2C0 Event - 121 000000C0 00000000 DCD I2C0_ER_IRQHandler - ; 48:I2C0 Error - 122 000000C4 00000000 DCD I2C1_EV_IRQHandler - ; 49:I2C1 Event - 123 000000C8 00000000 DCD I2C1_ER_IRQHandler - ; 50:I2C1 Error - 124 000000CC 00000000 DCD SPI0_IRQHandler ; 51:SPI0 - 125 000000D0 00000000 DCD SPI1_IRQHandler ; 52:SPI1 - 126 000000D4 00000000 DCD USART0_IRQHandler ; 53:USART0 - 127 000000D8 00000000 DCD USART1_IRQHandler ; 54:USART1 - 128 000000DC 00000000 DCD USART2_IRQHandler ; 55:USART2 - 129 000000E0 00000000 DCD EXTI10_15_IRQHandler ; 56:EXTI - Line 10 to EXTI Lin - e 15 - 130 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; 57:RTC A - larm through EXTI L - ine - 131 000000E8 00000000 DCD USBFS_WKUP_IRQHandler ; 58:USBF - S WakeUp from suspe - nd through EXTI Lin - e - 132 000000EC 00000000 DCD TIMER7_BRK_IRQHandler ; 59:TIME - R7 Break Interrupt - 133 000000F0 00000000 DCD TIMER7_UP_IRQHandler ; 60:TIMER - 7 Update Interrupt - 134 000000F4 00000000 DCD TIMER7_TRG_CMT_IRQHandler - ; 61:TIMER7 Trigger - - 135 000000F8 00000000 DCD TIMER7_Channel_IRQHandler ; 62: - TIMER7 Channel Capt - ure Compare - 136 000000FC 00000000 DCD 0 ; Reserved - 137 00000100 00000000 DCD EXMC_IRQHandler ; 64:EXMC - 138 00000104 00000000 DCD 0 ; Reserved - 139 00000108 00000000 DCD TIMER4_IRQHandler ; 66:TIMER4 - 140 0000010C 00000000 DCD SPI2_IRQHandler ; 67:SPI2 - 141 00000110 00000000 DCD UART3_IRQHandler ; 68:UART3 - 142 00000114 00000000 DCD UART4_IRQHandler ; 69:UART4 - 143 00000118 00000000 DCD TIMER5_IRQHandler ; 70:TIMER5 - 144 0000011C 00000000 DCD TIMER6_IRQHandler ; 71:TIMER6 - 145 00000120 00000000 DCD DMA1_Channel0_IRQHandler - ; 72:DMA1 Channel0 - - - -ARM Macro Assembler Page 5 - - - 146 00000124 00000000 DCD DMA1_Channel1_IRQHandler - ; 73:DMA1 Channel1 - 147 00000128 00000000 DCD DMA1_Channel2_IRQHandler - ; 74:DMA1 Channel2 - 148 0000012C 00000000 DCD DMA1_Channel3_IRQHandler - ; 75:DMA1 Channel3 - 149 00000130 00000000 DCD DMA1_Channel4_IRQHandler - ; 76:DMA1 Channel4 - 150 00000134 00000000 DCD ENET_IRQHandler ; 77:Ethernet - 151 00000138 00000000 DCD ENET_WKUP_IRQHandler ; 78:Ether - net Wakeup through - EXTI line - 152 0000013C 00000000 DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - - 153 00000140 00000000 DCD CAN1_RX0_IRQHandler - ; 80:CAN1 RX0 - 154 00000144 00000000 DCD CAN1_RX1_IRQHandler - ; 81:CAN1 RX1 - 155 00000148 00000000 DCD CAN1_EWMC_IRQHandler - ; 82:CAN1 EWMC - 156 0000014C 00000000 DCD USBFS_IRQHandler ; 83:USBFS - 157 00000150 - 158 00000150 __Vectors_End - 159 00000150 - 160 00000150 00000150 - __Vectors_Size - EQU __Vectors_End - __Vectors - 161 00000150 - 162 00000150 AREA |.text|, CODE, READONLY - 163 00000000 - 164 00000000 ;/* reset Handler */ - 165 00000000 Reset_Handler - PROC - 166 00000000 EXPORT Reset_Handler - [WEAK] - 167 00000000 IMPORT __main - 168 00000000 IMPORT SystemInit - 169 00000000 4806 LDR R0, =SystemInit - 170 00000002 4780 BLX R0 - 171 00000004 4806 LDR R0, =__main - 172 00000006 4700 BX R0 - 173 00000008 ENDP - 174 00000008 - 175 00000008 ;/* dummy Exception Handlers */ - 176 00000008 NMI_Handler - PROC - 177 00000008 EXPORT NMI_Handler - [WEAK] - 178 00000008 E7FE B . - 179 0000000A ENDP - 180 0000000A - 181 0000000A HardFault_Handler - PROC - 182 0000000A EXPORT HardFault_Handler - [WEAK] - 183 0000000A E7FE B . - 184 0000000C ENDP - 185 0000000C - 186 0000000C MemManage_Handler - - - -ARM Macro Assembler Page 6 - - - PROC - 187 0000000C EXPORT MemManage_Handler - [WEAK] - 188 0000000C E7FE B . - 189 0000000E ENDP - 190 0000000E - 191 0000000E BusFault_Handler - PROC - 192 0000000E EXPORT BusFault_Handler - [WEAK] - 193 0000000E E7FE B . - 194 00000010 ENDP - 195 00000010 - 196 00000010 UsageFault_Handler - PROC - 197 00000010 EXPORT UsageFault_Handler - [WEAK] - 198 00000010 E7FE B . - 199 00000012 ENDP - 200 00000012 - 201 00000012 SVC_Handler - PROC - 202 00000012 EXPORT SVC_Handler - [WEAK] - 203 00000012 E7FE B . - 204 00000014 ENDP - 205 00000014 - 206 00000014 DebugMon_Handler - PROC - 207 00000014 EXPORT DebugMon_Handler - [WEAK] - 208 00000014 E7FE B . - 209 00000016 ENDP - 210 00000016 - 211 00000016 PendSV_Handler - PROC - 212 00000016 EXPORT PendSV_Handler - [WEAK] - 213 00000016 E7FE B . - 214 00000018 ENDP - 215 00000018 - 216 00000018 SysTick_Handler - PROC - 217 00000018 EXPORT SysTick_Handler - [WEAK] - 218 00000018 E7FE B . - 219 0000001A ENDP - 220 0000001A - 221 0000001A Default_Handler - PROC - 222 0000001A ; /* external interrupts handler */ - - 223 0000001A EXPORT WWDGT_IRQHandler - [WEAK] - 224 0000001A EXPORT LVD_IRQHandler - [WEAK] - 225 0000001A EXPORT TAMPER_IRQHandler - [WEAK] - 226 0000001A EXPORT RTC_IRQHandler - - - -ARM Macro Assembler Page 7 - - - [WEAK] - 227 0000001A EXPORT FMC_IRQHandler - [WEAK] - 228 0000001A EXPORT RCU_IRQHandler - [WEAK] - 229 0000001A EXPORT EXTI0_IRQHandler - [WEAK] - 230 0000001A EXPORT EXTI1_IRQHandler - [WEAK] - 231 0000001A EXPORT EXTI2_IRQHandler - [WEAK] - 232 0000001A EXPORT EXTI3_IRQHandler - [WEAK] - 233 0000001A EXPORT EXTI4_IRQHandler - [WEAK] - 234 0000001A EXPORT DMA0_Channel0_IRQHandler - [WEAK] - 235 0000001A EXPORT DMA0_Channel1_IRQHandler - [WEAK] - 236 0000001A EXPORT DMA0_Channel2_IRQHandler - [WEAK] - 237 0000001A EXPORT DMA0_Channel3_IRQHandler - [WEAK] - 238 0000001A EXPORT DMA0_Channel4_IRQHandler - [WEAK] - 239 0000001A EXPORT DMA0_Channel5_IRQHandler - [WEAK] - 240 0000001A EXPORT DMA0_Channel6_IRQHandler - [WEAK] - 241 0000001A EXPORT ADC0_1_IRQHandler - [WEAK] - 242 0000001A EXPORT CAN0_TX_IRQHandler - [WEAK] - 243 0000001A EXPORT CAN0_RX0_IRQHandler - [WEAK] - 244 0000001A EXPORT CAN0_RX1_IRQHandler - [WEAK] - 245 0000001A EXPORT CAN0_EWMC_IRQHandler - [WEAK] - 246 0000001A EXPORT EXTI5_9_IRQHandler - [WEAK] - 247 0000001A EXPORT TIMER0_BRK_IRQHandler - [WEAK] - 248 0000001A EXPORT TIMER0_UP_IRQHandler - [WEAK] - 249 0000001A EXPORT TIMER0_TRG_CMT_IRQHandler - [WEAK] - 250 0000001A EXPORT TIMER0_Channel_IRQHandler - [WEAK] - 251 0000001A EXPORT TIMER1_IRQHandler - [WEAK] - 252 0000001A EXPORT TIMER2_IRQHandler - [WEAK] - 253 0000001A EXPORT TIMER3_IRQHandler - [WEAK] - 254 0000001A EXPORT I2C0_EV_IRQHandler - [WEAK] - 255 0000001A EXPORT I2C0_ER_IRQHandler - [WEAK] - - - -ARM Macro Assembler Page 8 - - - 256 0000001A EXPORT I2C1_EV_IRQHandler - [WEAK] - 257 0000001A EXPORT I2C1_ER_IRQHandler - [WEAK] - 258 0000001A EXPORT SPI0_IRQHandler - [WEAK] - 259 0000001A EXPORT SPI1_IRQHandler - [WEAK] - 260 0000001A EXPORT USART0_IRQHandler - [WEAK] - 261 0000001A EXPORT USART1_IRQHandler - [WEAK] - 262 0000001A EXPORT USART2_IRQHandler - [WEAK] - 263 0000001A EXPORT EXTI10_15_IRQHandler - [WEAK] - 264 0000001A EXPORT RTC_Alarm_IRQHandler - [WEAK] - 265 0000001A EXPORT USBFS_WKUP_IRQHandler - [WEAK] - 266 0000001A EXPORT TIMER7_BRK_IRQHandler - [WEAK] - 267 0000001A EXPORT TIMER7_UP_IRQHandler - [WEAK] - 268 0000001A EXPORT TIMER7_TRG_CMT_IRQHandler - [WEAK] - 269 0000001A EXPORT TIMER7_Channel_IRQHandler - [WEAK] - 270 0000001A EXPORT EXMC_IRQHandler - [WEAK] - 271 0000001A EXPORT TIMER4_IRQHandler - [WEAK] - 272 0000001A EXPORT SPI2_IRQHandler - [WEAK] - 273 0000001A EXPORT UART3_IRQHandler - [WEAK] - 274 0000001A EXPORT UART4_IRQHandler - [WEAK] - 275 0000001A EXPORT TIMER5_IRQHandler - [WEAK] - 276 0000001A EXPORT TIMER6_IRQHandler - [WEAK] - 277 0000001A EXPORT DMA1_Channel0_IRQHandler - [WEAK] - 278 0000001A EXPORT DMA1_Channel1_IRQHandler - [WEAK] - 279 0000001A EXPORT DMA1_Channel2_IRQHandler - [WEAK] - 280 0000001A EXPORT DMA1_Channel3_IRQHandler - [WEAK] - 281 0000001A EXPORT DMA1_Channel4_IRQHandler - [WEAK] - 282 0000001A EXPORT ENET_IRQHandler - [WEAK] - 283 0000001A EXPORT ENET_WKUP_IRQHandler - [WEAK] - 284 0000001A EXPORT CAN1_TX_IRQHandler - [WEAK] - 285 0000001A EXPORT CAN1_RX0_IRQHandler - - - -ARM Macro Assembler Page 9 - - - [WEAK] - 286 0000001A EXPORT CAN1_RX1_IRQHandler - [WEAK] - 287 0000001A EXPORT CAN1_EWMC_IRQHandler - [WEAK] - 288 0000001A EXPORT USBFS_IRQHandler - [WEAK] - 289 0000001A - 290 0000001A - 291 0000001A ;/* external interrupts handler */ - 292 0000001A WWDGT_IRQHandler - 293 0000001A LVD_IRQHandler - 294 0000001A TAMPER_IRQHandler - 295 0000001A RTC_IRQHandler - 296 0000001A FMC_IRQHandler - 297 0000001A RCU_IRQHandler - 298 0000001A EXTI0_IRQHandler - 299 0000001A EXTI1_IRQHandler - 300 0000001A EXTI2_IRQHandler - 301 0000001A EXTI3_IRQHandler - 302 0000001A EXTI4_IRQHandler - 303 0000001A DMA0_Channel0_IRQHandler - 304 0000001A DMA0_Channel1_IRQHandler - 305 0000001A DMA0_Channel2_IRQHandler - 306 0000001A DMA0_Channel3_IRQHandler - 307 0000001A DMA0_Channel4_IRQHandler - 308 0000001A DMA0_Channel5_IRQHandler - 309 0000001A DMA0_Channel6_IRQHandler - 310 0000001A ADC0_1_IRQHandler - 311 0000001A CAN0_TX_IRQHandler - 312 0000001A CAN0_RX0_IRQHandler - 313 0000001A CAN0_RX1_IRQHandler - 314 0000001A CAN0_EWMC_IRQHandler - 315 0000001A EXTI5_9_IRQHandler - 316 0000001A TIMER0_BRK_IRQHandler - 317 0000001A TIMER0_UP_IRQHandler - 318 0000001A TIMER0_TRG_CMT_IRQHandler - 319 0000001A TIMER0_Channel_IRQHandler - 320 0000001A TIMER1_IRQHandler - 321 0000001A TIMER2_IRQHandler - 322 0000001A TIMER3_IRQHandler - 323 0000001A I2C0_EV_IRQHandler - 324 0000001A I2C0_ER_IRQHandler - 325 0000001A I2C1_EV_IRQHandler - 326 0000001A I2C1_ER_IRQHandler - 327 0000001A SPI0_IRQHandler - 328 0000001A SPI1_IRQHandler - 329 0000001A USART0_IRQHandler - 330 0000001A USART1_IRQHandler - 331 0000001A USART2_IRQHandler - 332 0000001A EXTI10_15_IRQHandler - 333 0000001A RTC_Alarm_IRQHandler - 334 0000001A USBFS_WKUP_IRQHandler - 335 0000001A TIMER7_BRK_IRQHandler - 336 0000001A TIMER7_UP_IRQHandler - 337 0000001A TIMER7_TRG_CMT_IRQHandler - 338 0000001A TIMER7_Channel_IRQHandler - 339 0000001A EXMC_IRQHandler - 340 0000001A TIMER4_IRQHandler - - - -ARM Macro Assembler Page 10 - - - 341 0000001A SPI2_IRQHandler - 342 0000001A UART3_IRQHandler - 343 0000001A UART4_IRQHandler - 344 0000001A TIMER5_IRQHandler - 345 0000001A TIMER6_IRQHandler - 346 0000001A DMA1_Channel0_IRQHandler - 347 0000001A DMA1_Channel1_IRQHandler - 348 0000001A DMA1_Channel2_IRQHandler - 349 0000001A DMA1_Channel3_IRQHandler - 350 0000001A DMA1_Channel4_IRQHandler - 351 0000001A ENET_IRQHandler - 352 0000001A ENET_WKUP_IRQHandler - 353 0000001A CAN1_TX_IRQHandler - 354 0000001A CAN1_RX0_IRQHandler - 355 0000001A CAN1_RX1_IRQHandler - 356 0000001A CAN1_EWMC_IRQHandler - 357 0000001A USBFS_IRQHandler - 358 0000001A - 359 0000001A - 360 0000001A E7FE B . - 361 0000001C ENDP - 362 0000001C - 363 0000001C ALIGN - 364 0000001C - 365 0000001C ; user Initial Stack & Heap - 366 0000001C - 367 0000001C IF :DEF:__MICROLIB - 368 0000001C - 369 0000001C EXPORT __initial_sp - 370 0000001C EXPORT __heap_base - 371 0000001C EXPORT __heap_limit - 372 0000001C - 373 0000001C ELSE - 388 ENDIF - 389 0000001C - 390 0000001C END - 00000000 - 00000000 -Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw -ork --depend=.\output\startup_gd32f10x_cl.d -o.\output\startup_gd32f10x_cl.o -I -.\RTE\_rt-thread_gd32f105 -ID:\software\KEIL_V5_ArmPacks\GigaDevice\GD32F10x_DF -P\2.0.3\Device\Include -ID:\software\KEIL_V5\ARM\CMSIS\Include --predefine="__M -ICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 530" --predefine="GD32F10X_ -CL SETA 1" --predefine="USE_STDPERIPH_DRIVER SETA 1" --predefine="_RTE_ SETA 1" - --list=.\list\startup_gd32f10x_cl.lst Libraries\CMSIS\GD\GD32F10x\Source\ARM\s -tartup_gd32f10x_cl.s - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -STACK 00000000 - -Symbol: STACK - Definitions - At line 45 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - None -Comment: STACK unused -Stack_Mem 00000000 - -Symbol: Stack_Mem - Definitions - At line 46 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - None -Comment: Stack_Mem unused -__initial_sp 00002000 - -Symbol: __initial_sp - Definitions - At line 47 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - At line 71 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 369 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -HEAP 00000000 - -Symbol: HEAP - Definitions - At line 56 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - None -Comment: HEAP unused -Heap_Mem 00000000 - -Symbol: Heap_Mem - Definitions - At line 58 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - None -Comment: Heap_Mem unused -__heap_base 00000000 - -Symbol: __heap_base - Definitions - At line 57 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - At line 370 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s -Comment: __heap_base used once -__heap_limit 00002000 - -Symbol: __heap_limit - Definitions - At line 59 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - At line 371 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s -Comment: __heap_limit used once -4 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -RESET 00000000 - -Symbol: RESET - Definitions - At line 66 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - None -Comment: RESET unused -__Vectors 00000000 - -Symbol: __Vectors - Definitions - At line 71 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - At line 67 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -__Vectors_End 00000150 - -Symbol: __Vectors_End - Definitions - At line 158 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 68 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Relocatable symbols - -.text 00000000 - -Symbol: .text - Definitions - At line 162 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - None -Comment: .text unused -ADC0_1_IRQHandler 0000001A - -Symbol: ADC0_1_IRQHandler - Definitions - At line 310 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 107 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 241 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -BusFault_Handler 0000000E - -Symbol: BusFault_Handler - Definitions - At line 191 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 76 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 192 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN0_EWMC_IRQHandler 0000001A - -Symbol: CAN0_EWMC_IRQHandler - Definitions - At line 314 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 111 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 245 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN0_RX0_IRQHandler 0000001A - -Symbol: CAN0_RX0_IRQHandler - Definitions - At line 312 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 109 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 243 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN0_RX1_IRQHandler 0000001A - - - - -ARM Macro Assembler Page 2 Alphabetic symbol ordering -Relocatable symbols - -Symbol: CAN0_RX1_IRQHandler - Definitions - At line 313 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 110 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 244 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN0_TX_IRQHandler 0000001A - -Symbol: CAN0_TX_IRQHandler - Definitions - At line 311 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 108 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 242 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN1_EWMC_IRQHandler 0000001A - -Symbol: CAN1_EWMC_IRQHandler - Definitions - At line 356 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 155 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 287 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN1_RX0_IRQHandler 0000001A - -Symbol: CAN1_RX0_IRQHandler - Definitions - At line 354 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 153 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 285 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN1_RX1_IRQHandler 0000001A - -Symbol: CAN1_RX1_IRQHandler - Definitions - At line 355 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 154 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 286 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -CAN1_TX_IRQHandler 0000001A - - - -ARM Macro Assembler Page 3 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: CAN1_TX_IRQHandler - Definitions - At line 353 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 152 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 284 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA0_Channel0_IRQHandler 0000001A - -Symbol: DMA0_Channel0_IRQHandler - Definitions - At line 303 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 100 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 234 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA0_Channel1_IRQHandler 0000001A - -Symbol: DMA0_Channel1_IRQHandler - Definitions - At line 304 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 101 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 235 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA0_Channel2_IRQHandler 0000001A - -Symbol: DMA0_Channel2_IRQHandler - Definitions - At line 305 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 102 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 236 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA0_Channel3_IRQHandler 0000001A - -Symbol: DMA0_Channel3_IRQHandler - Definitions - At line 306 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 103 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 237 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - - - - -ARM Macro Assembler Page 4 Alphabetic symbol ordering -Relocatable symbols - -DMA0_Channel4_IRQHandler 0000001A - -Symbol: DMA0_Channel4_IRQHandler - Definitions - At line 307 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 104 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 238 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA0_Channel5_IRQHandler 0000001A - -Symbol: DMA0_Channel5_IRQHandler - Definitions - At line 308 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 105 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 239 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA0_Channel6_IRQHandler 0000001A - -Symbol: DMA0_Channel6_IRQHandler - Definitions - At line 309 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 106 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 240 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA1_Channel0_IRQHandler 0000001A - -Symbol: DMA1_Channel0_IRQHandler - Definitions - At line 346 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 145 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 277 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA1_Channel1_IRQHandler 0000001A - -Symbol: DMA1_Channel1_IRQHandler - Definitions - At line 347 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 146 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 278 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - - - -ARM Macro Assembler Page 5 Alphabetic symbol ordering -Relocatable symbols - - -DMA1_Channel2_IRQHandler 0000001A - -Symbol: DMA1_Channel2_IRQHandler - Definitions - At line 348 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 147 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 279 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA1_Channel3_IRQHandler 0000001A - -Symbol: DMA1_Channel3_IRQHandler - Definitions - At line 349 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 148 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 280 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DMA1_Channel4_IRQHandler 0000001A - -Symbol: DMA1_Channel4_IRQHandler - Definitions - At line 350 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 149 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 281 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -DebugMon_Handler 00000014 - -Symbol: DebugMon_Handler - Definitions - At line 206 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 83 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 207 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -Default_Handler 0000001A - -Symbol: Default_Handler - Definitions - At line 221 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - None -Comment: Default_Handler unused -ENET_IRQHandler 0000001A - - - -ARM Macro Assembler Page 6 Alphabetic symbol ordering -Relocatable symbols - - -Symbol: ENET_IRQHandler - Definitions - At line 351 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 150 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 282 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -ENET_WKUP_IRQHandler 0000001A - -Symbol: ENET_WKUP_IRQHandler - Definitions - At line 352 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 151 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 283 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -EXMC_IRQHandler 0000001A - -Symbol: EXMC_IRQHandler - Definitions - At line 339 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 137 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 270 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -EXTI0_IRQHandler 0000001A - -Symbol: EXTI0_IRQHandler - Definitions - At line 298 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 95 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 229 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -EXTI10_15_IRQHandler 0000001A - -Symbol: EXTI10_15_IRQHandler - Definitions - At line 332 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 129 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 263 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - - - - -ARM Macro Assembler Page 7 Alphabetic symbol ordering -Relocatable symbols - -EXTI1_IRQHandler 0000001A - -Symbol: EXTI1_IRQHandler - Definitions - At line 299 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 96 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 230 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -EXTI2_IRQHandler 0000001A - -Symbol: EXTI2_IRQHandler - Definitions - At line 300 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 97 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 231 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -EXTI3_IRQHandler 0000001A - -Symbol: EXTI3_IRQHandler - Definitions - At line 301 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 98 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 232 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -EXTI4_IRQHandler 0000001A - -Symbol: EXTI4_IRQHandler - Definitions - At line 302 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 99 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 233 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -EXTI5_9_IRQHandler 0000001A - -Symbol: EXTI5_9_IRQHandler - Definitions - At line 315 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 112 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 246 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - - - -ARM Macro Assembler Page 8 Alphabetic symbol ordering -Relocatable symbols - - -FMC_IRQHandler 0000001A - -Symbol: FMC_IRQHandler - Definitions - At line 296 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 93 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 227 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -HardFault_Handler 0000000A - -Symbol: HardFault_Handler - Definitions - At line 181 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 74 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 182 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -I2C0_ER_IRQHandler 0000001A - -Symbol: I2C0_ER_IRQHandler - Definitions - At line 324 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 121 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 255 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -I2C0_EV_IRQHandler 0000001A - -Symbol: I2C0_EV_IRQHandler - Definitions - At line 323 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 120 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 254 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -I2C1_ER_IRQHandler 0000001A - -Symbol: I2C1_ER_IRQHandler - Definitions - At line 326 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 123 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 257 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 - - - -ARM Macro Assembler Page 9 Alphabetic symbol ordering -Relocatable symbols - -0x_cl.s - -I2C1_EV_IRQHandler 0000001A - -Symbol: I2C1_EV_IRQHandler - Definitions - At line 325 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 122 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 256 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -LVD_IRQHandler 0000001A - -Symbol: LVD_IRQHandler - Definitions - At line 293 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 90 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 224 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -MemManage_Handler 0000000C - -Symbol: MemManage_Handler - Definitions - At line 186 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 75 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 187 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -NMI_Handler 00000008 - -Symbol: NMI_Handler - Definitions - At line 176 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 73 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 177 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -PendSV_Handler 00000016 - -Symbol: PendSV_Handler - Definitions - At line 211 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 85 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - - - -ARM Macro Assembler Page 10 Alphabetic symbol ordering -Relocatable symbols - - At line 212 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -RCU_IRQHandler 0000001A - -Symbol: RCU_IRQHandler - Definitions - At line 297 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 94 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 228 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -RTC_Alarm_IRQHandler 0000001A - -Symbol: RTC_Alarm_IRQHandler - Definitions - At line 333 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 130 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 264 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -RTC_IRQHandler 0000001A - -Symbol: RTC_IRQHandler - Definitions - At line 295 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 92 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 226 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -Reset_Handler 00000000 - -Symbol: Reset_Handler - Definitions - At line 165 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 72 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 166 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -SPI0_IRQHandler 0000001A - -Symbol: SPI0_IRQHandler - Definitions - At line 327 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 124 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 - - - -ARM Macro Assembler Page 11 Alphabetic symbol ordering -Relocatable symbols - -0x_cl.s - At line 258 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -SPI1_IRQHandler 0000001A - -Symbol: SPI1_IRQHandler - Definitions - At line 328 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 125 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 259 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -SPI2_IRQHandler 0000001A - -Symbol: SPI2_IRQHandler - Definitions - At line 341 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 140 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 272 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -SVC_Handler 00000012 - -Symbol: SVC_Handler - Definitions - At line 201 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 82 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 202 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -SysTick_Handler 00000018 - -Symbol: SysTick_Handler - Definitions - At line 216 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 86 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 217 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TAMPER_IRQHandler 0000001A - -Symbol: TAMPER_IRQHandler - Definitions - At line 294 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - - - -ARM Macro Assembler Page 12 Alphabetic symbol ordering -Relocatable symbols - - At line 91 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 225 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER0_BRK_IRQHandler 0000001A - -Symbol: TIMER0_BRK_IRQHandler - Definitions - At line 316 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 113 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 247 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER0_Channel_IRQHandler 0000001A - -Symbol: TIMER0_Channel_IRQHandler - Definitions - At line 319 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 116 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 250 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER0_TRG_CMT_IRQHandler 0000001A - -Symbol: TIMER0_TRG_CMT_IRQHandler - Definitions - At line 318 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 115 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 249 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER0_UP_IRQHandler 0000001A - -Symbol: TIMER0_UP_IRQHandler - Definitions - At line 317 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 114 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 248 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER1_IRQHandler 0000001A - -Symbol: TIMER1_IRQHandler - Definitions - At line 320 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - - - -ARM Macro Assembler Page 13 Alphabetic symbol ordering -Relocatable symbols - - Uses - At line 117 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 251 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER2_IRQHandler 0000001A - -Symbol: TIMER2_IRQHandler - Definitions - At line 321 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 118 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 252 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER3_IRQHandler 0000001A - -Symbol: TIMER3_IRQHandler - Definitions - At line 322 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 119 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 253 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER4_IRQHandler 0000001A - -Symbol: TIMER4_IRQHandler - Definitions - At line 340 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 139 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 271 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER5_IRQHandler 0000001A - -Symbol: TIMER5_IRQHandler - Definitions - At line 344 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 143 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 275 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER6_IRQHandler 0000001A - -Symbol: TIMER6_IRQHandler - Definitions - At line 345 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 - - - -ARM Macro Assembler Page 14 Alphabetic symbol ordering -Relocatable symbols - -0x_cl.s - Uses - At line 144 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 276 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER7_BRK_IRQHandler 0000001A - -Symbol: TIMER7_BRK_IRQHandler - Definitions - At line 335 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 132 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 266 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER7_Channel_IRQHandler 0000001A - -Symbol: TIMER7_Channel_IRQHandler - Definitions - At line 338 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 135 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 269 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER7_TRG_CMT_IRQHandler 0000001A - -Symbol: TIMER7_TRG_CMT_IRQHandler - Definitions - At line 337 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 134 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 268 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -TIMER7_UP_IRQHandler 0000001A - -Symbol: TIMER7_UP_IRQHandler - Definitions - At line 336 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 133 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 267 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -UART3_IRQHandler 0000001A - -Symbol: UART3_IRQHandler - Definitions - - - -ARM Macro Assembler Page 15 Alphabetic symbol ordering -Relocatable symbols - - At line 342 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 141 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 273 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -UART4_IRQHandler 0000001A - -Symbol: UART4_IRQHandler - Definitions - At line 343 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 142 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 274 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -USART0_IRQHandler 0000001A - -Symbol: USART0_IRQHandler - Definitions - At line 329 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 126 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 260 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -USART1_IRQHandler 0000001A - -Symbol: USART1_IRQHandler - Definitions - At line 330 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 127 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 261 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -USART2_IRQHandler 0000001A - -Symbol: USART2_IRQHandler - Definitions - At line 331 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 128 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 262 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -USBFS_IRQHandler 0000001A - -Symbol: USBFS_IRQHandler - - - -ARM Macro Assembler Page 16 Alphabetic symbol ordering -Relocatable symbols - - Definitions - At line 357 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 156 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 288 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -USBFS_WKUP_IRQHandler 0000001A - -Symbol: USBFS_WKUP_IRQHandler - Definitions - At line 334 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 131 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - At line 265 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -UsageFault_Handler 00000010 - -Symbol: UsageFault_Handler - Definitions - At line 196 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 77 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 197 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -WWDGT_IRQHandler 0000001A - -Symbol: WWDGT_IRQHandler - Definitions - At line 292 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 89 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - At line 223 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - -78 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -Absolute symbols - -Heap_Size 00002000 - -Symbol: Heap_Size - Definitions - At line 54 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - At line 58 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s -Comment: Heap_Size used once -Stack_Size 00002000 - -Symbol: Stack_Size - Definitions - At line 43 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s - Uses - At line 46 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s -Comment: Stack_Size used once -__Vectors_Size 00000150 - -Symbol: __Vectors_Size - Definitions - At line 160 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 69 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10 -x_cl.s -Comment: __Vectors_Size used once -3 symbols - - - -ARM Macro Assembler Page 1 Alphabetic symbol ordering -External symbols - -SystemInit 00000000 - -Symbol: SystemInit - Definitions - At line 168 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - Uses - At line 169 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s -Comment: SystemInit used once -__main 00000000 - -Symbol: __main - Definitions - At line 167 in file Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f1 -0x_cl.s - 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- - - - $WS_DIR$\project.ewp - - - - - diff --git a/bsp/gd32105c-eval/project.uvoptx b/bsp/gd32105c-eval/project.uvoptx deleted file mode 100644 index 36f7f0050c..0000000000 --- a/bsp/gd32105c-eval/project.uvoptx +++ /dev/null @@ -1,177 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f105 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\list\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U58001139 -O14 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(790007A3) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL0300000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - diff --git a/bsp/gd32105c-eval/project.uvprojx b/bsp/gd32105c-eval/project.uvprojx deleted file mode 100644 index 3c11aff459..0000000000 --- a/bsp/gd32105c-eval/project.uvprojx +++ /dev/null @@ -1,1234 +0,0 @@ - - - 2.1 -
### uVision Project, (C) Keil Software
- - - rt-thread_gd32f105 - 0x4 - ARM-ADS - 0 - - - GD32F105VC - GigaDevice - GigaDevice.GD32F10x_DFP.2.0.3 - https://gd32mcu.com/data/documents/pack/ - IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM)) - 0 - $$Device:GD32F105VC$Device\Include\gd32f10x.h - - - - - - - - - - $$Device:GD32F105VC$SVD\GD32F10x\GD32F10x_CL.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\output\ - Project - 1 - 0 - 1 - 1 - 1 - .\list\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x18000 - - - 1 - 0x8000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x18000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - GD32F10X_CL, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__ - - ..\..\components\drivers\include;applications;..\..\components\libc\posix\io\poll;..\..\components\libc\compilers\common\extension;Libraries\CMSIS;..\..\components\libc\compilers\common\include;Libraries\CMSIS\GD\GD32F10x\Include;..\..\include;..\..\components\drivers\spi;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\spi\sfud\inc;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\dfs\dfs_v1\include;..\..\components\drivers\include;..\..\components\drivers\include;.;..\..\components\libc\posix\ipc;..\..\components\libc\posix\io\eventfd;..\..\components\drivers\include;..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\libcpu\arm\common;..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\components\dfs\dfs_v1\filesystems\devfs;Libraries\GD32F10x_standard_peripheral\Include;..\..\components\libc\posix\io\epoll;..\..\components\finsh - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Applications - - - main.c - 1 - applications\main.c - - - - - Compiler - - - syscall_mem.c - 1 - ..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\components\libc\compilers\common\cctype.c - - - - - cstdlib.c - 1 - ..\..\components\libc\compilers\common\cstdlib.c - - - - - cstring.c - 1 - ..\..\components\libc\compilers\common\cstring.c - - - - - ctime.c - 1 - ..\..\components\libc\compilers\common\ctime.c - - - - - cunistd.c - 1 - ..\..\components\libc\compilers\common\cunistd.c - - - - - cwchar.c - 1 - ..\..\components\libc\compilers\common\cwchar.c - - - - - CPU - - - div0.c - 1 - ..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\libcpu\arm\common\showmem.c - - - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S - - - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c - - - - - DeviceDrivers - - - device.c - 1 - ..\..\components\drivers\core\device.c - - - - - --c99 - - - - - - - - - - - - i2c_core.c - 1 - ..\..\components\drivers\i2c\i2c_core.c - - - - - --c99 - - - - - - - - - - - - i2c_dev.c - 1 - ..\..\components\drivers\i2c\i2c_dev.c - - - - - --c99 - - - - - - - - - - - - completion.c - 1 - ..\..\components\drivers\ipc\completion.c - - - - - --c99 - - - - - - - - - - - - dataqueue.c - 1 - ..\..\components\drivers\ipc\dataqueue.c - - - - - --c99 - - - - - - - - - - - - pipe.c - 1 - ..\..\components\drivers\ipc\pipe.c - - - - - --c99 - - - - - - - - - - - - ringblk_buf.c - 1 - ..\..\components\drivers\ipc\ringblk_buf.c - - - - - --c99 - - - - - - - - - - - - ringbuffer.c - 1 - ..\..\components\drivers\ipc\ringbuffer.c - - - - - --c99 - - - - - - - - - - - - waitqueue.c - 1 - ..\..\components\drivers\ipc\waitqueue.c - - - - - --c99 - - - - - - - - - - - - workqueue.c - 1 - ..\..\components\drivers\ipc\workqueue.c - - - - - --c99 - - - - - - - - - - - - pin.c - 1 - ..\..\components\drivers\misc\pin.c - - - - - --c99 - - - - - - - - - - - - serial.c - 1 - ..\..\components\drivers\serial\serial.c - - - - - --c99 - - - - - - - - - - - - sfud.c - 1 - ..\..\components\drivers\spi\sfud\src\sfud.c - - - - - --c99 - - - - - - - - - - - - sfud_sfdp.c - 1 - ..\..\components\drivers\spi\sfud\src\sfud_sfdp.c - - - - - --c99 - - - - - - - - - - - - spi_core.c - 1 - ..\..\components\drivers\spi\spi_core.c - - - - - --c99 - - - - - - - - - - - - spi_dev.c - 1 - ..\..\components\drivers\spi\spi_dev.c - - - - - --c99 - - - - - - - - - - - - spi_flash_sfud.c - 1 - ..\..\components\drivers\spi\spi_flash_sfud.c - - - - - --c99 - - - - - - - - - - - - Drivers - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_spi.c - 1 - drivers\drv_spi.c - - - - - drv_i2c.c - 1 - drivers\drv_i2c.c - - - - - drv_spi_flash.c - 1 - drivers\drv_spi_flash.c - - - - - drv_usart.c - 1 - drivers\drv_usart.c - - - - - board.c - 1 - drivers\board.c - - - - - Filesystem - - - devfs.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c - - - - - dfs_elm.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c - - - - - ff.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c - - - - - ffunicode.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c - - - - - dfs.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs.c - - - - - dfs_file.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_file.c - - - - - dfs_fs.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_fs.c - - - - - dfs_posix.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_posix.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - msh_parse.c - 1 - ..\..\components\finsh\msh_parse.c - - - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - msh_file.c - 1 - ..\..\components\finsh\msh_file.c - - - - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler_up.c - 1 - ..\..\src\scheduler_up.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - Libraries - - - gd32f10x_rcu.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c - - - - - gd32f10x_crc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_crc.c - - - - - gd32f10x_dbg.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dbg.c - - - - - gd32f10x_exti.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c - - - - - gd32f10x_bkp.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_bkp.c - - - - - gd32f10x_fmc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fmc.c - - - - - gd32f10x_enet.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_enet.c - - - - - gd32f10x_dac.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dac.c - - - - - gd32f10x_misc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c - - - - - gd32f10x_sdio.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_sdio.c - - - - - startup_gd32f10x_cl.s - 2 - Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s - - - - - gd32f10x_can.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_can.c - - - - - gd32f10x_timer.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_timer.c - - - - - gd32f10x_fwdgt.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fwdgt.c - - - - - gd32f10x_exmc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exmc.c - - - - - gd32f10x_spi.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c - - - - - gd32f10x_wwdgt.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_wwdgt.c - - - - - gd32f10x_rtc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rtc.c - - - - - gd32f10x_pmu.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_pmu.c - - - - - system_gd32f10x.c - 1 - Libraries\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c - - - - - gd32f10x_i2c.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_i2c.c - - - - - gd32f10x_adc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_adc.c - - - - - gd32f10x_gpio.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c - - - - - gd32f10x_usart.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c - - - - - gd32f10x_dma.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dma.c - - - - - - - - - - - - - - - <Project Info> - - - - - - 0 - 1 - - - - diff --git a/bsp/gd32105c-eval/rtconfig.h b/bsp/gd32105c-eval/rtconfig.h deleted file mode 100644 index 28b06046d9..0000000000 --- a/bsp/gd32105c-eval/rtconfig.h +++ /dev/null @@ -1,273 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 - -/* kservice optimization */ - -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FD_MAX 16 -#define RT_USING_DFS_V1 -#define DFS_FILESYSTEMS_MAX 4 -#define DFS_FILESYSTEM_TYPES_MAX 4 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_3 -#define RT_DFS_ELM_USE_LFN 3 -#define RT_DFS_ELM_LFN_UNICODE_0 -#define RT_DFS_ELM_LFN_UNICODE 0 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 2 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 -#define RT_DFS_ELM_REENTRANT -#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_I2C -#define RT_USING_PIN -#define RT_USING_SPI -#define RT_USING_SFUD -#define RT_SFUD_USING_SFDP -#define RT_SFUD_USING_FLASH_INFO_TABLE -#define RT_SFUD_SPI_MAX_HZ 50000000 - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* sensors drivers */ - - -/* touch drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -/* Hardware Drivers Config */ - -/* Onboard Peripheral Drivers */ - -/* On-chip Peripheral Drivers */ - -#define SOC_SERIES_GD32F1 -#define SOC_GD32105C -#define RT_USING_USART0 -#define RT_USING_SPI0 -#define RT_USING_I2C0 - -/* Board extended module Drivers */ - - -#endif diff --git a/bsp/gd32105c-eval/rtconfig.py b/bsp/gd32105c-eval/rtconfig.py deleted file mode 100644 index 253e258b37..0000000000 --- a/bsp/gd32105c-eval/rtconfig.py +++ /dev/null @@ -1,126 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' - - LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - - EXEC_PATH += '/ARM/ARMCC/bin' - print(EXEC_PATH) - - CFLAGS += ' --c99' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config gd32_rom.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH += '/arm/bin/' - POST_ACTION = '' - diff --git a/bsp/gd32105c-eval/template.ewp b/bsp/gd32105c-eval/template.ewp deleted file mode 100644 index 716042958e..0000000000 --- a/bsp/gd32105c-eval/template.ewp +++ /dev/null @@ -1,1889 +0,0 @@ - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/gd32105c-eval/template.uvoptx b/bsp/gd32105c-eval/template.uvoptx deleted file mode 100644 index 36f7f0050c..0000000000 --- a/bsp/gd32105c-eval/template.uvoptx +++ /dev/null @@ -1,177 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f105 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\list\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U58001139 -O14 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(790007A3) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL0300000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - diff --git a/bsp/gd32105c-eval/template.uvprojx b/bsp/gd32105c-eval/template.uvprojx deleted file mode 100644 index 3e21481087..0000000000 --- a/bsp/gd32105c-eval/template.uvprojx +++ /dev/null @@ -1,405 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread_gd32f105 - 0x4 - ARM-ADS - 0 - - - GD32F105VC - GigaDevice - GigaDevice.GD32F10x_DFP.2.0.3 - https://gd32mcu.com/data/documents/pack/ - IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F105VC$Flash\GD32F10x_CL.FLM)) - 0 - $$Device:GD32F105VC$Device\Include\gd32f10x.h - - - - - - - - - - $$Device:GD32F105VC$SVD\GD32F10x\GD32F10x_CL.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\output\ - Project - 1 - 0 - 1 - 1 - 1 - .\list\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x18000 - - - 1 - 0x8000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x18000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - ..\..\..\..\GD32F10x_Firmware_Library\CMSIS;..\..\..\..\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\..\..\..\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\Utilities;..\ - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - - - - - - - - - - - <Project Info> - - - - - - 0 - 1 - - - - - diff --git a/bsp/gd32107c-eval/.config b/bsp/gd32107c-eval/.config deleted file mode 100644 index 3e011de8be..0000000000 --- a/bsp/gd32107c-eval/.config +++ /dev/null @@ -1,1063 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_INIT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50002 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=16 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=4 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_MQUEUE is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -# CONFIG_RT_USING_I2C_BITOPS is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -CONFIG_RT_USING_SFUD=y -CONFIG_RT_SFUD_USING_SFDP=y -CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y -# CONFIG_RT_SFUD_USING_QSPI is not set -CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 -# CONFIG_RT_DEBUG_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_KTIME is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# - -# -# Hardware Drivers Config -# - -# -# Onboard Peripheral Drivers -# - -# -# On-chip Peripheral Drivers -# -CONFIG_SOC_SERIES_GD32F1=y -CONFIG_SOC_GD32107C=y -CONFIG_RT_USING_USART0=y -# CONFIG_RT_USING_USART1 is not set -# CONFIG_RT_USING_USART2 is not set -# CONFIG_RT_USING_UART3 is not set -CONFIG_RT_USING_SPI0=y -# CONFIG_RT_USING_SPI1 is not set -# CONFIG_RT_USING_SPI2 is not set -CONFIG_RT_USING_I2C0=y -# CONFIG_RT_USING_I2C1 is not set - -# -# Board extended module Drivers -# diff --git a/bsp/gd32107c-eval/.ignore_format.yml b/bsp/gd32107c-eval/.ignore_format.yml deleted file mode 100644 index d570c52faf..0000000000 --- a/bsp/gd32107c-eval/.ignore_format.yml +++ /dev/null @@ -1,8 +0,0 @@ -# files format check exclude path, please follow the instructions below to modify; -# If you need to exclude an entire folder, add the folder path in dir_path; -# If you need to exclude a file, add the path to the file in file_path. - -file_path: - -dir_path: -- Libraries diff --git a/bsp/gd32107c-eval/Kconfig b/bsp/gd32107c-eval/Kconfig deleted file mode 100644 index bead9b5eea..0000000000 --- a/bsp/gd32107c-eval/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "drivers/Kconfig" - - - - - diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h deleted file mode 100644 index e525f3c0c6..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/gd32f10x.h +++ /dev/null @@ -1,381 +0,0 @@ -/*! - \file gd32f10x.h - \brief general definitions for GD32F10x - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_H -#define GD32F10X_H - -#ifdef cplusplus - extern "C" { -#endif - -/* define GD32F10x */ -#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) - /* #define GD32F10X_MD */ /*!< GD32F10X_MD: GD32 Medium density devices */ - /* #define GD32F10X_HD */ /*!< GD32F10X_HD: GD32 High density Value Line devices */ - /* #define GD32F10X_XD */ /*!< GD32F10X_XD: GD32 Extra density devices */ - /* #define GD32F10X_CL */ /*!< GD32F10X_CL: GD32 Connectivity line devices */ -#endif /* define GD32F10x */ - -#if !defined (GD32F10X_MD) && !defined (GD32F10X_HD) && !defined (GD32F10X_XD) && !defined (GD32F10X_CL) - #error "Please select the target GD32F10x device in gd32f10x.h file" -#endif /* undefine GD32F10x tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined HXTAL_VALUE -#ifdef GD32F10X_CL -#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ -#else -#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ -#endif /* HXTAL_VALUE */ -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* GD32F10x firmware library version number V2.0 */ -#define __GD32F10x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __GD32F10x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32F10x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F10x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32F10x_STDPERIPH_VERSION ((__GD32F10x_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32F10x_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32F10x_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32F10x_STDPERIPH_VERSION_RC)) - -/* configuration of the Cortex-M3 processor and core peripherals */ -#define __MPU_PRESENT 0 /*!< GD32F10x do not provide MPU */ -#define __NVIC_PRIO_BITS 4 /*!< GD32F10x uses 4 bits for the priority levels */ -#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ -/* define interrupt number */ -typedef enum IRQn -{ - /* Cortex-M3 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 system tick interrupt */ - - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ - RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ - FMC_IRQn = 4, /*!< FMC interrupt */ - RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ - EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ - EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ - EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ - EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ - EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ - DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ - DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ - DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ - DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ - DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ - DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ - -#ifdef GD32F10X_MD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ -#endif /* GD32F10X_MD */ - -#ifdef GD32F10X_HD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ - TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ - TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ - TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - ADC2_IRQn = 47, /*!< ADC2 global interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - SDIO_IRQn = 49, /*!< SDIO global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ -#endif /* GD32F10X_HD */ - -#ifdef GD32F10X_XD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - ADC2_IRQn = 47, /*!< ADC2 global interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - SDIO_IRQn = 49, /*!< SDIO global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ -#endif /* GD32F10X_XD */ - -#ifdef GD32F10X_CL - CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ - USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ - TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ - TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ - TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ - ENET_IRQn = 61, /*!< ENET global interrupt */ - ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS global interrupt */ -#endif /* GD32F10X_CL */ - -} IRQn_Type; - -/* includes */ -#include "core_cm3.h" -#include "system_gd32f10x.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ -#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ - -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ -#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ - -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ -#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */ -#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ -#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ - -/* advanced peripheral bus 2 memory map */ -#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ - -/* advanced high performance bus 1 memory map */ -#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ -#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ -#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - -/* define marco USE_STDPERIPH_DRIVER */ -#if !defined USE_STDPERIPH_DRIVER -#define USE_STDPERIPH_DRIVER -#endif -#ifdef USE_STDPERIPH_DRIVER -#include "gd32f10x_libopt.h" -#endif /* USE_STDPERIPH_DRIVER */ - -#ifdef cplusplus -} -#endif -#endif diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h deleted file mode 100644 index 6bd00fb99d..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Include/system_gd32f10x.h +++ /dev/null @@ -1,60 +0,0 @@ -/*! - \file system_gd32f10x.h - \brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for - GD32F10x Device Series -*/ - -/* - Copyright (c) 2012 ARM LIMITED - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32F10X_H -#define SYSTEM_GD32F10X_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit(void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32F10X_H */ diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s deleted file mode 100644 index a3ffa4c752..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s +++ /dev/null @@ -1,390 +0,0 @@ -;/*! -; \file startup_gd32f10x_cl.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBFS_WKUP_IRQHandler ; 58:USBFS WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; 64:EXMC - DCD 0 ; Reserved - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD ENET_IRQHandler ; 77:Ethernet - DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI line - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT CAN0_TX_IRQHandler [WEAK] - EXPORT CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_IRQHandler [WEAK] - EXPORT TIMER0_UP_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBFS_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_IRQHandler [WEAK] - EXPORT TIMER7_UP_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT ENET_WKUP_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_EWMC_IRQHandler [WEAK] - EXPORT USBFS_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -CAN0_TX_IRQHandler -CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_IRQHandler -TIMER0_UP_IRQHandler -TIMER0_TRG_CMT_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBFS_WKUP_IRQHandler -TIMER7_BRK_IRQHandler -TIMER7_UP_IRQHandler -TIMER7_TRG_CMT_IRQHandler -TIMER7_Channel_IRQHandler -EXMC_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -ENET_IRQHandler -ENET_WKUP_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_EWMC_IRQHandler -USBFS_IRQHandler - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s deleted file mode 100644 index fe768cc3a9..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_hd.s +++ /dev/null @@ -1,371 +0,0 @@ -;/*! -; \file startup_gd32f10x_hd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_IRQHandler [WEAK] - EXPORT TIMER0_UP_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_IRQHandler [WEAK] - EXPORT TIMER7_UP_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_4_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_IRQHandler -TIMER0_UP_IRQHandler -TIMER0_TRG_CMT_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -TIMER7_BRK_IRQHandler -TIMER7_UP_IRQHandler -TIMER7_TRG_CMT_IRQHandler -TIMER7_Channel_IRQHandler -ADC2_IRQHandler -EXMC_IRQHandler -SDIO_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_4_IRQHandler - - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s deleted file mode 100644 index c567fee5c1..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_md.s +++ /dev/null @@ -1,328 +0,0 @@ -;/*! -; \file startup_gd32f10x_md.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; 64:EXMC - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_IRQHandler [WEAK] - EXPORT TIMER0_UP_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_IRQHandler -TIMER0_UP_IRQHandler -TIMER0_TRG_CMT_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -EXMC_IRQHandler - - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s deleted file mode 100644 index 3db249b8e5..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_xd.s +++ /dev/null @@ -1,371 +0,0 @@ -;/*! -; \file startup_gd32f10x_xd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN = 3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00002000 - - AREA HEAP, NOINIT, READWRITE, ALIGN = 3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper Interrupt - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_IRQHandler ; 21:RCU - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 global - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 global - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 global - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break Interrupt and TIMER11 global - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update Interrupt and TIMER12 global - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt and TIMER13 global - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] - EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] - EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_4_IRQHandler [WEAK] - - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_TIMER8_IRQHandler -TIMER0_UP_TIMER9_IRQHandler -TIMER0_TRG_CMT_TIMER10_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -TIMER7_BRK_TIMER11_IRQHandler -TIMER7_UP_TIMER12_IRQHandler -TIMER7_TRG_CMT_TIMER13_IRQHandler -TIMER7_Channel_IRQHandler -ADC2_IRQHandler -EXMC_IRQHandler -SDIO_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_4_IRQHandler - - - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s deleted file mode 100644 index 8d614ecf3e..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s +++ /dev/null @@ -1,529 +0,0 @@ -;/*! -; \file startup_gd32f10x_cl.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; Vector Number 35,CAN0 TX - DCD CAN0_RX0_IRQHandler ; Vector Number 36,CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break - DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt - DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; Vector Number 64,EXMC - DCD 0 ; Reserved - DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 - DCD SPI2_IRQHandler ; Vector Number 67,SPI2 - DCD UART3_IRQHandler ; Vector Number 68,UART3 - DCD UART4_IRQHandler ; Vector Number 69,UART4 - DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 - DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 - DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; Vector Number 75,DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; Vector Number 76,DMA1 Channel4 - DCD ENET_IRQHandler ; Vector Number 77,Ethernet - DCD ENET_WKUP_IRQHandler ; Vector Number 78,Ethernet Wakeup through EXTI line - DCD CAN1_TX_IRQHandler ; Vector Number 79,CAN1 TX - DCD CAN1_RX0_IRQHandler ; Vector Number 80,CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; Vector Number 81,CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; Vector Number 82,CAN1 EWMC - DCD USBFS_IRQHandler ; Vector Number 83,USBFS -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_TX_IRQHandler - B CAN0_TX_IRQHandler - - PUBWEAK CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX0_IRQHandler - B CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_IRQHandler - B TIMER0_BRK_IRQHandler - - PUBWEAK TIMER0_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_IRQHandler - B TIMER0_UP_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_IRQHandler - B TIMER0_TRG_CMT_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBFS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_WKUP_IRQHandler - B USBFS_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_IRQHandler - B TIMER7_BRK_IRQHandler - - PUBWEAK TIMER7_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_IRQHandler - B TIMER7_UP_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_IRQHandler - B TIMER7_TRG_CMT_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK ENET_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_WKUP_IRQHandler - B ENET_WKUP_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_EWMC_IRQHandler - B CAN1_EWMC_IRQHandler - - PUBWEAK USBFS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_IRQHandler - B USBFS_IRQHandler - - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s deleted file mode 100644 index 0cd9ade897..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_hd.s +++ /dev/null @@ -1,491 +0,0 @@ -;/*! -; \file startup_gd32f10x_hd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break - DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt - DCD TIMER7_UP_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt - DCD TIMER7_TRG_CMT_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt - DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; Vector Number 63,ADC2 - DCD EXMC_IRQHandler ; Vector Number 64,EXMC - DCD SDIO_IRQHandler ; Vector Number 65,SDIO - DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 - DCD SPI2_IRQHandler ; Vector Number 67,SPI2 - DCD UART3_IRQHandler ; Vector Number 68,UART3 - DCD UART4_IRQHandler ; Vector Number 69,UART4 - DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 - DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 - DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_IRQHandler - B TIMER0_BRK_IRQHandler - - PUBWEAK TIMER0_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_IRQHandler - B TIMER0_UP_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_IRQHandler - B TIMER0_TRG_CMT_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_IRQHandler - B TIMER7_BRK_IRQHandler - - PUBWEAK TIMER7_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_IRQHandler - B TIMER7_UP_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_IRQHandler - B TIMER7_TRG_CMT_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_4_IRQHandler - B DMA1_Channel3_4_IRQHandler - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s deleted file mode 100644 index bc0d386613..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_md.s +++ /dev/null @@ -1,400 +0,0 @@ -;/*! -; \file startup_gd32f10x_md.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_IRQHandler ; Vector Number 40,TIMER0 Break - DCD TIMER0_UP_IRQHandler ; Vector Number 41,TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; Vector Number 64,EXMC -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_IRQHandler - B TIMER0_BRK_IRQHandler - - PUBWEAK TIMER0_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_IRQHandler - B TIMER0_UP_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_IRQHandler - B TIMER0_TRG_CMT_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s deleted file mode 100644 index 4f52b7d5fa..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_xd.s +++ /dev/null @@ -1,491 +0,0 @@ -;/*! -; \file startup_gd32f10x_xd.s -; \brief start up file -; -; \version 2014-12-26, V1.0.0, firmware for GD32F10x -; \version 2017-06-20, V2.0.0, firmware for GD32F10x -; \version 2018-07-31, V2.1.0, firmware for GD32F10x -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window Watchdog Timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; Vector Number 18,Tamper Interrupt - DCD RTC_IRQHandler ; Vector Number 19,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 20,FMC - DCD RCU_IRQHandler ; Vector Number 21,RCU - DCD EXTI0_IRQHandler ; Vector Number 22,EXTI Line 0 - DCD EXTI1_IRQHandler ; Vector Number 23,EXTI Line 1 - DCD EXTI2_IRQHandler ; Vector Number 24,EXTI Line 2 - DCD EXTI3_IRQHandler ; Vector Number 25,EXTI Line 3 - DCD EXTI4_IRQHandler ; Vector Number 26,EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; Vector Number 27,DMA0 Channel 0 - DCD DMA0_Channel1_IRQHandler ; Vector Number 28,DMA0 Channel 1 - DCD DMA0_Channel2_IRQHandler ; Vector Number 29,DMA0 Channel 2 - DCD DMA0_Channel3_IRQHandler ; Vector Number 30,DMA0 Channel 3 - DCD DMA0_Channel4_IRQHandler ; Vector Number 31,DMA0 Channel 4 - DCD DMA0_Channel5_IRQHandler ; Vector Number 32,DMA0 Channel 5 - DCD DMA0_Channel6_IRQHandler ; Vector Number 33,DMA0 Channel 6 - DCD ADC0_1_IRQHandler ; Vector Number 34,ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; Vector Number 35,USBD and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; Vector Number 36,USBD and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; Vector Number 37,CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; Vector Number 38,CAN0 EWMC - DCD EXTI5_9_IRQHandler ; Vector Number 39,EXTI Line 5 to EXTI Line 9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; Vector Number 40,TIMER0 Break and TIMER8 global - DCD TIMER0_UP_TIMER9_IRQHandler ; Vector Number 41,TIMER0 Update and TIMER9 global - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 global - DCD TIMER0_Channel_IRQHandler ; Vector Number 43,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 44,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 45,TIMER2 - DCD TIMER3_IRQHandler ; Vector Number 46,TIMER3 - DCD I2C0_EV_IRQHandler ; Vector Number 47,I2C0 Event - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD I2C1_EV_IRQHandler ; Vector Number 49,I2C1 Event - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD SPI0_IRQHandler ; Vector Number 51,SPI0 - DCD SPI1_IRQHandler ; Vector Number 52,SPI1 - DCD USART0_IRQHandler ; Vector Number 53,USART0 - DCD USART1_IRQHandler ; Vector Number 54,USART1 - DCD USART2_IRQHandler ; Vector Number 55,USART2 - DCD EXTI10_15_IRQHandler ; Vector Number 56,EXTI Line 10 to EXTI Line 15 - DCD RTC_Alarm_IRQHandler ; Vector Number 57,RTC Alarm through EXTI Line - DCD USBD_WKUP_IRQHandler ; Vector Number 58,USBD WakeUp from suspend through EXTI Line - DCD TIMER7_BRK_TIMER11_IRQHandler ; Vector Number 59,TIMER7 Break Interrupt and TIMER11 global - DCD TIMER7_UP_TIMER12_IRQHandler ; Vector Number 60,TIMER7 Update Interrupt and TIMER12 global - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; Vector Number 61,TIMER7 Trigger and Commutation Interrupt and TIMER13 global - DCD TIMER7_Channel_IRQHandler ; Vector Number 62,TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; Vector Number 63,ADC2 - DCD EXMC_IRQHandler ; Vector Number 64,EXMC - DCD SDIO_IRQHandler ; Vector Number 65,SDIO - DCD TIMER4_IRQHandler ; Vector Number 66,TIMER4 - DCD SPI2_IRQHandler ; Vector Number 67,SPI2 - DCD UART3_IRQHandler ; Vector Number 68,UART3 - DCD UART4_IRQHandler ; Vector Number 69,UART4 - DCD TIMER5_IRQHandler ; Vector Number 70,TIMER5 - DCD TIMER6_IRQHandler ; Vector Number 71,TIMER6 - DCD DMA1_Channel0_IRQHandler ; Vector Number 72,DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; Vector Number 73,DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; Vector Number 74,DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; Vector Number 75,DMA1 Channel4 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, = SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_TIMER8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_TIMER8_IRQHandler - B TIMER0_BRK_TIMER8_IRQHandler - - PUBWEAK TIMER0_UP_TIMER9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_TIMER9_IRQHandler - B TIMER0_UP_TIMER9_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_TIMER10_IRQHandler - B TIMER0_TRG_CMT_TIMER10_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_TIMER11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_TIMER11_IRQHandler - B TIMER7_BRK_TIMER11_IRQHandler - - PUBWEAK TIMER7_UP_TIMER12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_TIMER12_IRQHandler - B TIMER7_UP_TIMER12_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_TIMER13_IRQHandler - B TIMER7_TRG_CMT_TIMER13_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_4_IRQHandler - B DMA1_Channel3_4_IRQHandler - - END diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c b/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c deleted file mode 100644 index 699179711a..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c +++ /dev/null @@ -1,1028 +0,0 @@ -/*! - \file system_gd32f10x.c - \brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for - GD32F10x Device Series -*/ - -/* - Copyright (c) 2012 ARM LIMITED - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32f10x.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -/* select a system clock by uncommenting the following line */ -/* use IRC8M */ -//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) - -/* use HXTAL (XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */ -//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) -//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) -//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) -//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) -#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) - -#define SEL_IRC8M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLL 0x02U - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; -static void system_clock_48m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; -static void system_clock_72m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; -static void system_clock_108m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; -static void system_clock_hxtal(void); -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; -static void system_clock_24m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; -static void system_clock_36m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; -static void system_clock_48m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; -static void system_clock_56m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; -static void system_clock_96m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; -static void system_clock_108m_hxtal(void); -#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_HXTAL - system_clock_hxtal(); -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) - system_clock_24m_hxtal(); -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) - system_clock_36m_hxtal(); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) - system_clock_48m_hxtal(); -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) - system_clock_56m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) - system_clock_96m_hxtal(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) - system_clock_108m_hxtal(); - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) - system_clock_48m_irc8m(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) - system_clock_108m_irc8m(); -#endif /* __SYSTEM_CLOCK_HXTAL */ -} - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit(void) -{ - /* reset the RCC clock configuration to the default reset state */ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); - - /* reset HXTALEN, CKMEN, PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - - /* Reset HXTALBPS bit */ - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - - /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ - -#ifdef GD32F10X_CL - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); - - RCU_CFG1 = 0x00000000U; -#else - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | - RCU_CFG0_USBDPSC | RCU_CFG0_PLLMF_4); -#endif /* GD32F10X_CL */ - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* reset HXTALEN, CKMEN and PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x009F0000U; -#elif defined(GD32F10X_CL) - /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x00FF0000U; -#endif - - /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ - system_clock_config(); -} - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate(void) -{ - uint32_t scss; - uint32_t pllsel, predv0sel, pllmf, ck_src; -#ifdef GD32F10X_CL - uint32_t predv0, predv1, pll1mf; -#endif /* GD32F10X_CL */ - - scss = GET_BITS(RCU_CFG0, 2, 3); - - switch (scss) - { - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - - if(RCU_PLLSRC_IRC8M_DIV2 == pllsel){ - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE / 2U; - }else{ - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); - - /* PREDV0 input source clock divided by 2 */ - if(RCU_CFG0_PREDV0 == predv0sel){ - ck_src = HXTAL_VALUE / 2U; - } -#elif defined(GD32F10X_CL) - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - - /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ - pllmf |= 0x10U; - } - - if(pllmf >= 15U){ - pllmf += 1U; - }else{ - pllmf += 2U; - } - - SystemCoreClock = ck_src * pllmf; - -#ifdef GD32F10X_CL - if(15U == pllmf){ - /* PLL source clock multiply by 6.5 */ - SystemCoreClock = ck_src * 6U + ck_src / 2U; - } -#endif /* GD32F10X_CL */ - - break; - - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } -} - -#ifdef __SYSTEM_CLOCK_HXTAL -/*! - \brief configure the system clock to HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) -/*! - \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_24m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 6 = 24 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL6; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) -/*! - \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_36m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 9 = 36 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL9; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -/*! - \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL12; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) -/*! - \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_56m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 14 = 56 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL14; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL18; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -/*! - \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL24; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -/*! - \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL27; - -#elif defined(GD32F10X_CL) - /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while(0U == (RCU_CTL & RCU_CTL_PLL1STB)){ - } -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) -/*! - \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL12; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL18; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -/*! - \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL27; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#endif diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/core_cm3.h b/bsp/gd32107c-eval/Libraries/CMSIS/core_cm3.h deleted file mode 100644 index 1b661b4421..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/core_cm3.h +++ /dev/null @@ -1,1638 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32107c-eval/Libraries/CMSIS/core_cmFunc.h deleted file mode 100644 index 01089f1333..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,637 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32107c-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32107c-eval/Libraries/CMSIS/core_cmInstr.h deleted file mode 100644 index 856b4c3c61..0000000000 --- a/bsp/gd32107c-eval/Libraries/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,880 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h deleted file mode 100644 index bb61cd73b5..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_adc.h +++ /dev/null @@ -1,368 +0,0 @@ -/*! - \file gd32f10x_adc.h - \brief definitions for the ADC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_ADC_H -#define GD32F10x_ADC_H - -#include "gd32f10x.h" - -/* ADC definitions */ -#define ADC0 ADC_BASE -#define ADC1 (ADC_BASE + 0x400U) -#define ADC2 (ADC_BASE + 0x1800U) - -/* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - -/* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx x=0..2 */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ -#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ - -/* constants definitions */ -/* adc_stat register value */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - -/* scan mode */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ - -/* inserted channel group convert automatically */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ - -/* ADC sync mode */ -#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ -#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ -#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ -#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ - -/* adc_ctl1 register value */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ - -/* continuous mode */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -/* for ADC0 and ADC1 regular channel */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ -/* for ADC2 regular channel */ -#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */ -#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */ -#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */ - -/* external trigger mode for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -/* for ADC0 and ADC1 inserted channel */ -#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */ -#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ -/* for ADC2 inserted channel */ -#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */ -#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */ -#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */ -#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */ -#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - -/* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - -/* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - -/* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - -/* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ - -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ - -/* ADC interrupt */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* function declarations */ -/* initialization config */ -/* reset ADC */ -void adc_deinit(uint32_t adc_periph); -/* configure the ADC sync mode */ -void adc_mode_config(uint32_t mode); -/* enable or disable ADC special function */ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); -/* enable ADC interface */ -void adc_enable(uint32_t adc_periph); -/* disable ADC interface */ -void adc_disable(uint32_t adc_periph); -/* ADC calibration and reset calibration */ -void adc_calibration_enable(uint32_t adc_periph); -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); - -/* DMA config */ -/* enable DMA request */ -void adc_dma_mode_enable(uint32_t adc_periph); -/* disable DMA request */ -void adc_dma_mode_disable(uint32_t adc_periph); - -/* regular group and inserted group config */ -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); - -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); - -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); -/* configure ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); - -/* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); -/* read the last ADC0 and ADC1 conversion result data in sync mode */ -uint32_t adc_sync_mode_convert_value_read(void); - -/* watchdog config */ -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); - -/* interrupt & flag functions */ -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); -/* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); -/* get the bit state of ADCx software inserted channel start conversion */ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); - -#endif /* GD32F10x_ADC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h deleted file mode 100644 index 73f93252fe..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_bkp.h +++ /dev/null @@ -1,230 +0,0 @@ -/*! - \file gd32f10x_bkp.h - \brief definitions for the BKP - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_BKP_H -#define GD32F10X_BKP_H - -#include "gd32f10x.h" - -/* BKP definitions */ -#define BKP BKP_BASE /*!< BKP base address */ - -/* registers definitions */ -#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ -#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ -#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ -#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ -#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ -#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ -#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ -#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ -#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ -#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ -#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ -#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ -#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ -#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ -#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ -#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ -#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ -#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ -#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ -#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ -#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ -#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ -#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ -#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ -#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ -#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ -#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ -#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ -#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ -#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ -#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ -#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ -#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ -#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ -#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ -#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ -#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ -#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ -#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ -#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ -#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ -#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ -#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ -#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ -#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ - -/* bits definitions */ -/* BKP_DATA */ -#define BKP_DATA BITS(0,15) /*!< backup data */ - -/* BKP_OCTL */ -#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ -#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ -#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ - -/* BKP_TPCTL */ -#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ -#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ - -/* BKP_TPCS */ -#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ -#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ -#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ -#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ -#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ - -/* constants definitions */ -/* BKP data register number */ -typedef enum -{ - BKP_DATA_0 = 1, /*!< BKP data register 0 */ - BKP_DATA_1, /*!< BKP data register 1 */ - BKP_DATA_2, /*!< BKP data register 2 */ - BKP_DATA_3, /*!< BKP data register 3 */ - BKP_DATA_4, /*!< BKP data register 4 */ - BKP_DATA_5, /*!< BKP data register 5 */ - BKP_DATA_6, /*!< BKP data register 6 */ - BKP_DATA_7, /*!< BKP data register 7 */ - BKP_DATA_8, /*!< BKP data register 8 */ - BKP_DATA_9, /*!< BKP data register 9 */ - BKP_DATA_10, /*!< BKP data register 10 */ - BKP_DATA_11, /*!< BKP data register 11 */ - BKP_DATA_12, /*!< BKP data register 12 */ - BKP_DATA_13, /*!< BKP data register 13 */ - BKP_DATA_14, /*!< BKP data register 14 */ - BKP_DATA_15, /*!< BKP data register 15 */ - BKP_DATA_16, /*!< BKP data register 16 */ - BKP_DATA_17, /*!< BKP data register 17 */ - BKP_DATA_18, /*!< BKP data register 18 */ - BKP_DATA_19, /*!< BKP data register 19 */ - BKP_DATA_20, /*!< BKP data register 20 */ - BKP_DATA_21, /*!< BKP data register 21 */ - BKP_DATA_22, /*!< BKP data register 22 */ - BKP_DATA_23, /*!< BKP data register 23 */ - BKP_DATA_24, /*!< BKP data register 24 */ - BKP_DATA_25, /*!< BKP data register 25 */ - BKP_DATA_26, /*!< BKP data register 26 */ - BKP_DATA_27, /*!< BKP data register 27 */ - BKP_DATA_28, /*!< BKP data register 28 */ - BKP_DATA_29, /*!< BKP data register 29 */ - BKP_DATA_30, /*!< BKP data register 30 */ - BKP_DATA_31, /*!< BKP data register 31 */ - BKP_DATA_32, /*!< BKP data register 32 */ - BKP_DATA_33, /*!< BKP data register 33 */ - BKP_DATA_34, /*!< BKP data register 34 */ - BKP_DATA_35, /*!< BKP data register 35 */ - BKP_DATA_36, /*!< BKP data register 36 */ - BKP_DATA_37, /*!< BKP data register 37 */ - BKP_DATA_38, /*!< BKP data register 38 */ - BKP_DATA_39, /*!< BKP data register 39 */ - BKP_DATA_40, /*!< BKP data register 40 */ - BKP_DATA_41, /*!< BKP data register 41 */ -}bkp_data_register_enum; - -/* BKP register */ -#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) -#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) - -/* get data of BKP data register */ -#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - -/* RTC clock calibration value */ -#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/* RTC output selection */ -#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ -#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ - -/* tamper pin active level */ -#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ -#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ - -/* tamper flag */ -#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ - -/* tamper interrupt flag */ -#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ -/* function declarations */ -/* reset BKP registers */ -void bkp_deinit(void); -/* write BKP data register */ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); -/* read BKP data register */ -uint16_t bkp_data_read(bkp_data_register_enum register_number); - -/* RTC related functions */ -/* enable RTC clock calibration output */ -void bkp_rtc_calibration_output_enable(void); -/* disable RTC clock calibration output */ -void bkp_rtc_calibration_output_disable(void); -/* enable RTC alarm or second signal output */ -void bkp_rtc_signal_output_enable(void); -/* disable RTC alarm or second signal output */ -void bkp_rtc_signal_output_disable(void); -/* select RTC output */ -void bkp_rtc_output_select(uint16_t outputsel); -/* set RTC clock calibration value */ -void bkp_rtc_calibration_value_set(uint8_t value); - -/* tamper pin related functions */ -/* enable tamper pin detection */ -void bkp_tamper_detection_enable(void); -/* disable tamper pin detection */ -void bkp_tamper_detection_disable(void); -/* set tamper pin active level */ -void bkp_tamper_active_level_set(uint16_t level); - -/* interrupt & flag functions */ -/* enable tamper interrupt */ -void bkp_interrupt_enable(void); -/* disable tamper interrupt */ -void bkp_interrupt_disable(void); -/* get tamper flag state */ -FlagStatus bkp_flag_get(void); -/* clear tamper flag state */ -void bkp_flag_clear(void); -/* get tamper interrupt flag state */ -FlagStatus bkp_interrupt_flag_get(void); -/* clear tamper interrupt flag state */ -void bkp_interrupt_flag_clear(void); - -#endif /* GD32F10X_BKP_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h deleted file mode 100644 index 0e5ae1f251..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_can.h +++ /dev/null @@ -1,725 +0,0 @@ -/*! - \file gd32f10x_can.h - \brief definitions for the CAN - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_CAN_H -#define GD32F10x_CAN_H - -#include "gd32f10x.h" - -/* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ - -/* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ - -/* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ - -/* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ - -/* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ - -/* bits definitions */ -/* CAN_CTL */ -#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ -#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ -#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ -#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ -#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ -#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ -#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ -#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ -#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ -#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ - -/* CAN_STAT */ -#define CAN_STAT_IWS BIT(0) /*!< initial working state */ -#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ -#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ -#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ -#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ -#define CAN_STAT_TS BIT(8) /*!< transmitting state */ -#define CAN_STAT_RS BIT(9) /*!< receiving state */ -#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ -#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ - -/* CAN_TSTAT */ -#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ -#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ -#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ -#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ -#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ -#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ -#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ -#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ -#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ -#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ -#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ -#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ -#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ -#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ -#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ -#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ -#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ -#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ -#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ -#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ -#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - -/* CAN_RFIFO0 */ -#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ -#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ -#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - -/* CAN_RFIFO1 */ -#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ -#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ -#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ - -/* CAN_INTEN */ -#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ -#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ -#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ -#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ -#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ -#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ -#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ -#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ -#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ - -/* CAN_ERR */ -#define CAN_ERR_WERR BIT(0) /*!< warning error */ -#define CAN_ERR_PERR BIT(1) /*!< passive error */ -#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ -#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ -#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ -#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ - -/* CAN_BT */ -#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ -#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ -#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ -#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ -#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ -#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - -/* CAN_TMIx */ -#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ -#define CAN_TMI_FT BIT(1) /*!< frame type */ -#define CAN_TMI_FF BIT(2) /*!< frame format */ -#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_TMPx */ -#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ -#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_TMDATA0x */ -#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ -#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ -#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ -#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ - -/* CAN_TMDATA1x */ -#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ -#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ -#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ -#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ - -/* CAN_RFIFOMIx */ -#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ -#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ -#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_RFIFOMPx */ -#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ -#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ -#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_RFIFOMDATA0x */ -#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ -#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ -#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ -#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ - -/* CAN_RFIFOMDATA1x */ -#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ -#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ -#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ -#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ - -/* CAN_FCTL */ -#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ -#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ - -/* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ - -/* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ - -/* CAN_FAFIFO */ -#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ - -/* CAN_FW */ -#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ - -/* CAN_FxDATAy */ -#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ - -/* consts definitions */ -/* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) -#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ -#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ -#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ -#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ -#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ - -/* CAN flags */ -typedef enum -{ - /* flags in TSTAT register */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ - /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ - /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ - /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -}can_flag_enum; - -/* CAN interrupt flags */ -typedef enum -{ - /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ - /* interrupt flags in TSTAT register */ - CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ - CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ - CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ -}can_interrupt_flag_enum; - -/* CAN initiliaze parameters struct */ -typedef struct -{ - uint8_t working_mode; /*!< CAN working mode */ - uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ - uint8_t time_segment_1; /*!< time segment 1 */ - uint8_t time_segment_2; /*!< time segment 2 */ - ControlStatus time_triggered; /*!< time triggered communication mode */ - ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ - ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ - ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ - ControlStatus trans_fifo_order; /*!< transmit FIFO order */ - uint16_t prescaler; /*!< baudrate prescaler */ -}can_parameter_struct; - -/* CAN transmit message struct */ -typedef struct -{ - uint32_t tx_sfid; /*!< standard format frame identifier */ - uint32_t tx_efid; /*!< extended format frame identifier */ - uint8_t tx_ff; /*!< format of frame, standard or extended format */ - uint8_t tx_ft; /*!< type of frame, data or remote */ - uint8_t tx_dlen; /*!< data length */ - uint8_t tx_data[8]; /*!< transmit data */ -}can_trasnmit_message_struct; - -/* CAN receive message struct */ -typedef struct -{ - uint32_t rx_sfid; /*!< standard format frame identifier */ - uint32_t rx_efid; /*!< extended format frame identifier */ - uint8_t rx_ff; /*!< format of frame, standard or extended format */ - uint8_t rx_ft; /*!< type of frame, data or remote */ - uint8_t rx_dlen; /*!< data length */ - uint8_t rx_data[8]; /*!< receive data */ - uint8_t rx_fi; /*!< filtering index */ -} can_receive_message_struct; - -/* CAN filter parameters struct */ -typedef struct -{ - uint16_t filter_list_high; /*!< filter list number high bits*/ - uint16_t filter_list_low; /*!< filter list number low bits */ - uint16_t filter_mask_high; /*!< filter mask number high bits */ - uint16_t filter_mask_low; /*!< filter mask number low bits */ - uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ - uint16_t filter_number; /*!< filter number */ - uint16_t filter_mode; /*!< filter mode, list or mask */ - uint16_t filter_bits; /*!< filter scale */ - ControlStatus filter_enable; /*!< filter work or not */ -}can_filter_parameter_struct; - -/* CAN errors */ -typedef enum -{ - CAN_ERROR_NONE = 0, /*!< no error */ - CAN_ERROR_FILL, /*!< fill error */ - CAN_ERROR_FORMATE, /*!< format error */ - CAN_ERROR_ACK, /*!< ACK error */ - CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ - CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ - CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG, /*!< software configure */ -}can_error_enum; - -/* transmit states */ -typedef enum -{ - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ -}can_transmit_state_enum; - -typedef enum -{ - CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ - CAN_FILTER_STRUCT, /* CAN filter parameters struct */ - CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ - CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -}can_struct_type_enum; - -/* CAN baudrate prescaler*/ -#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) - -/* CAN bit segment 1*/ -#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) - -/* CAN bit segment 2*/ -#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) - -/* CAN resynchronization jump width*/ -#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) - -/* CAN communication mode*/ -#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) - -/* CAN FDATA high 16 bits */ -#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) - -/* CAN FDATA low 16 bits */ -#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) - -/* CAN1 filter start bank_number*/ -#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) - -/* CAN transmit mailbox extended identifier*/ -#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) - -/* CAN transmit mailbox standard identifier*/ -#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) - -/* transmit data byte 0 */ -#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 1 */ -#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 2 */ -#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 3 */ -#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* transmit data byte 4 */ -#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 5 */ -#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 6 */ -#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 7 */ -#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* receive mailbox extended identifier*/ -#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) - -/* receive mailbox standrad identifier*/ -#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) - -/* receive data length */ -#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) - -/* the index of the filter by which the frame is passed */ -#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 0 */ -#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 1 */ -#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 2 */ -#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 3 */ -#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* receive data byte 4 */ -#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 5 */ -#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 6 */ -#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 7 */ -#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* error number */ -#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) - -/* transmit error count */ -#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive error count */ -#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* CAN errors */ -#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ - -#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ - -/* CAN communication mode */ -#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ -#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ -#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ -#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ - -/* CAN resynchronisation jump width */ -#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ - -/* CAN time segment 1 */ -#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ -#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ -#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ -#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ -#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ -#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ -#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ -#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ -#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ - -/* CAN time segment 2 */ -#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ - -/* CAN mailbox number */ -#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ -#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ -#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ -#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ - -/* CAN frame format */ -#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ -#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ - -/* CAN receive fifo */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ - -/* frame number of receive fifo */ -#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ - -#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ -#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ - -/* CAN working mode */ -#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ -#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ -#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ - -/* filter bits */ -#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ -#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ - -/* filter mode */ -#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ -#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ - -/* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ - -/* frame type */ -#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ -#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ - -/* CAN timeout */ -#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ - -/* interrupt enable bits */ -#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ -#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ -#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ -#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ -#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ -#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ -#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ -#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ -#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ -#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ - -/* function declarations */ -/* deinitialize CAN */ -void can_deinit(uint32_t can_periph); -/* initialize CAN struct */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct); -/* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); -/* set can1 fliter start bank number */ -void can1_filter_start_bank(uint8_t start_bank); -/* enable functions */ -/* CAN debug freeze enable */ -void can_debug_freeze_enable(uint32_t can_periph); -/* CAN debug freeze disable */ -void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time trigger mode enable */ -void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time trigger mode disable */ -void can_time_trigger_mode_disable(uint32_t can_periph); - -/* transmit functions */ -/* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); -/* get CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); -/* stop CAN transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); -/* CAN release fifo */ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive message length */ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); -/* CAN working mode */ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); -/* CAN wakeup from sleep mode */ -ErrStatus can_wakeup(uint32_t can_periph); - -/* CAN get error */ -can_error_enum can_error_get(uint32_t can_periph); -/* get CAN receive error number */ -uint8_t can_receive_error_number_get(uint32_t can_periph); -/* get CAN transmit error number */ -uint8_t can_transmit_error_number_get(uint32_t can_periph); - -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* CAN get flag state */ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); -/* CAN clear flag state */ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag); -/* CAN get interrupt flag state */ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); -/* CAN clear interrupt flag state */ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); - -#endif /* GD32F10x_CAN_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h deleted file mode 100644 index 9f2781ff26..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_crc.h +++ /dev/null @@ -1,81 +0,0 @@ -/*! - \file gd32f10x_crc.h - \brief definitions for the CRC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_CRC_H -#define GD32F10X_CRC_H - -#include "gd32f10x.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* reset data register to the value of initializaiton data register */ -void crc_data_register_reset(void); -/* read the value of the data register */ -uint32_t crc_data_register_read(void); - -/* read the value of the free data register */ -uint8_t crc_free_data_register_read(void); -/* write data to the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* calculate the CRC value of a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* calculate the CRC value of an array of 32-bit values */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32F10X_CRC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h deleted file mode 100644 index aa9e70bbf8..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dac.h +++ /dev/null @@ -1,250 +0,0 @@ -/*! - \file gd32f10x_dac.h - \brief definitions for the DAC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_DAC_H -#define GD32F10X_DAC_H - -#include "gd32f10x.h" - -/* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 0U -#define DAC1 1U - -/* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ - -/* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - -/* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - -/* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - -/* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - -/* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - -/* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - -/* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - -/* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - -/* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - -/* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - -/* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - -/* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ - -/* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ - -/* constants definitions */ -/* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ -#elif defined(GD32F10X_CL) -#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - -/* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - -/* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ - -/* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ - -/* function declarations */ -/* initialization functions */ -/* deinitialize DAC */ -void dac_deinit(void); -/* enable DAC */ -void dac_enable(uint32_t dac_periph); -/* disable DAC */ -void dac_disable(uint32_t dac_periph); -/* enable DAC DMA */ -void dac_dma_enable(uint32_t dac_periph); -/* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); -/* enable DAC output buffer */ -void dac_output_buffer_enable(uint32_t dac_periph); -/* disable DAC output buffer */ -void dac_output_buffer_disable(uint32_t dac_periph); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); - -/* DAC trigger configuration */ -/* enable DAC trigger */ -void dac_trigger_enable(uint32_t dac_periph); -/* disable DAC trigger */ -void dac_trigger_disable(uint32_t dac_periph); -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); -/* enable DAC software trigger */ -void dac_software_trigger_enable(uint32_t dac_periph); -/* disable DAC software trigger */ -void dac_software_trigger_disable(uint32_t dac_periph); - -/* DAC wave mode configuration */ -/* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); -/* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); -/* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); - -/* DAC concurrent mode configuration */ -/* enable DAC concurrent mode */ -void dac_concurrent_enable(void); -/* disable DAC concurrent mode */ -void dac_concurrent_disable(void); -/* enable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_enable(void); -/* disable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_disable(void); -/* enable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_enable(void); -/* disable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_disable(void); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); - -#endif /* GD32F10X_DAC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h deleted file mode 100644 index d9248414b8..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dbg.h +++ /dev/null @@ -1,152 +0,0 @@ -/*! - \file gd32f10x_dbg.h - \brief definitions for the DBG - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_DBG_H -#define GD32F10X_DBG_H - -#include "gd32f10x.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL */ -#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ -#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ -#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ -#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ -#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ -#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ -#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ -#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ -#define DBG_CTL_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ -#define DBG_CTL_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ -#ifdef GD32F10x_CL -#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ -#endif /* GD32F10x_CL */ -#ifdef GD32F10X_XD -#define DBG_CTL_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ -#define DBG_CTL_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ -#define DBG_CTL_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ -#define DBG_CTL_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ -#define DBG_CTL_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ -#define DBG_CTL_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ -#endif /* GD32F10x_XD */ - -/* constants definitions */ -/* debug hold when core is halted */ -typedef enum -{ - DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ - DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ - DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ - DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ - DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ - DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ - DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ -#ifdef GD32F10x_CL - DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ -#endif /* GD32F10x_CL */ -#if (defined(GD32F10x_XD) || defined(GD32F10x_CL)) - DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ - DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ -#endif /* GD32F10x_XD || GD32F10x_CL*/ -}dbg_periph_enum; - -/* DBG low power mode configurations */ -#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* DBG_CTL0_TRACE_MODE configurations */ -#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) -#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */ -#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ -#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ -#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ - -/* function declarations */ -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* low power behavior configuration */ -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* peripheral behavior configuration */ -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -/* trace pin assignment configuration */ -/* enable trace pin assignment */ -void dbg_trace_pin_enable(void); -/* disable trace pin assignment */ -void dbg_trace_pin_disable(void); -/* set trace pin mode */ -void dbg_trace_pin_mode_set(uint32_t trace_mode); - -#endif /* GD32F10x_DBG_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h deleted file mode 100644 index 3a90e8d690..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_dma.h +++ /dev/null @@ -1,289 +0,0 @@ -/*! - \file gd32f10x_dma.h - \brief definitions for the DMA - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_DMA_H -#define GD32F10X_DMA_H - -#include "gd32f10x.h" - -/* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ - -/* registers definitions */ -#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ - -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ - -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ - -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ - -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ - -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ - -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ - -#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL, x=0..6 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT, x=0..6 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR, x=0..6 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR, x=0..6 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA channel 0 */ - DMA_CH1, /*!< DMA channel 1 */ - DMA_CH2, /*!< DMA channel 2 */ - DMA_CH3, /*!< DMA channel 3 */ - DMA_CH4, /*!< DMA channel 4 */ - DMA_CH5, /*!< DMA channel 5 */ - DMA_CH6 /*!< DMA channel 6 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ - -} dma_parameter_struct; - -#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_register address */ -#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ -/* circular mode */ -#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */ -#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ - -/* memory to memory mode */ -#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ -#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ - -/* function declarations */ -/* DMA deinitialization and initialization functions */ -/* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); -/* initialize the parameters of DMA struct with the default values */ -void dma_struct_para_init(dma_parameter_struct* init_struct); -/* initialize DMA channel */ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); -/* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); - -/* DMA configuration functions */ -/* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set DMA memory base address */ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); - -/* flag and interrupt functions */ -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the flag of a DMA channel */ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the interrupt flag of a DMA channel */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); - -#endif /* GD32F10X_DMA_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h deleted file mode 100644 index 310fb2f8d8..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_enet.h +++ /dev/null @@ -1,1498 +0,0 @@ -/*! - \file gd32f10x_enet.h - \brief definitions for the ENET - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_ENET_H -#define GD32F10x_ENET_H - -#include "gd32f10x.h" -#include - -#define IF_USE_EXTERNPHY_LIB 0 -#if (1 == IF_USE_EXTERNPHY_LIB) -#include "phy.h" -#endif - -#ifndef ENET_RXBUF_NUM -#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ -#endif - -#ifndef ENET_TXBUF_NUM -#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ -#endif - -#ifndef ENET_RXBUF_SIZE -#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ -#endif - -#ifndef ENET_TXBUF_SIZE -#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ -#endif - -/* #define USE_DELAY */ - -#ifndef _PHY_H_ -#define DP83848 0 -#define LAN8700 1 -#define PHY_TYPE DP83848 - -#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ - -/* PHY read write timeouts */ -#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ -#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ - -/* PHY delay */ -#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ -#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ - -/* PHY register address */ -#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ -#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ - -/* PHY basic control register */ -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ - -/* PHY basic status register */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ - -#if(PHY_TYPE == LAN8700) -#define PHY_SR 31U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ -#elif(PHY_TYPE == DP83848) -#define PHY_SR 16U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ -#endif /* PHY_TYPE */ - -#endif /* _PHY_H_ */ - - -/* ENET definitions */ -#define ENET ENET_BASE - -/* registers definitions */ -#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ -#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ -#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ -#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ -#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ -#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ -#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ -#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ -#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ -#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ -#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ -#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ -#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ -#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ -#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ -#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ -#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ -#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ -#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ -#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ - -#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ -#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ -#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ -#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ -#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ -#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ -#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ -#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ -#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ -#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ -#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ - -#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ -#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ -#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ -#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ -#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ -#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ -#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ -#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ - -#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ -#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ -#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ -#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ -#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ -#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ -#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ -#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ -#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ -#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ -#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ - -/* bits definitions */ -/* ENET_MAC_CFG */ -#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ -#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ -#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ -#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ -#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ -#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ -#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ -#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ -#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ -#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ -#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ -#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ -#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ -#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ - -/* ENET_MAC_FRMF */ -#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ -#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - -/* ENET_MAC_HLH */ -#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - -/* ENET_MAC_HLL */ -#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - -/* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - -/* ENET_MAC_PHY_DATA */ -#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - -/* ENET_MAC_FCTL */ -#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ -#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ -#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ -#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ -#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ -#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - -/* ENET_MAC_FCTH */ -#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ -#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - -/* ENET_MAC_VLT */ -#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ -#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - -/* ENET_MAC_RWFF */ -#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ -#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ -#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ -#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ -#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ -#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ -#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ -#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ - -/* ENET_MAC_INTF */ -#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ -#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ -#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ -#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ -#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ - -/* ENET_MAC_INTMSK */ -#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ -#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ - -/* ENET_MAC_ADDR0H */ -#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ -#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - -/* ENET_MAC_ADDR0L */ -#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - -/* ENET_MAC_ADDR1H */ -#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR1L */ -#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - -/* ENET_MAC_ADDR2H */ -#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ -#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR2L */ -#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - -/* ENET_MAC_ADDR3H */ -#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ -#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR3L */ -#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - -/* ENET_MSC_CTL */ -#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ -#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ -#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ -#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ - -/* ENET_MSC_RINTF */ -#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ -#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ -#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - -/* ENET_MSC_TINTF */ -#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ -#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ -#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ - -/* ENET_MSC_RINTMSK */ -#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ -#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ -#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - -/* ENET_MSC_TINTMSK */ -#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - -/* ENET_MSC_SCCNT */ -#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - -/* ENET_MSC_MSCCNT */ -#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - -/* ENET_MSC_TGFCNT */ -#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - -/* ENET_MSC_RFCECNT */ -#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - -/* ENET_MSC_RFAECNT */ -#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - -/* ENET_MSC_RGUFCNT */ -#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - -/* ENET_PTP_TSCTL */ -#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ -#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ -#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ -#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ -#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ -#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ - -/* ENET_PTP_SSINC */ -#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - -/* ENET_PTP_TSH */ -#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - -/* ENET_PTP_TSL */ -#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ -#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - -/* ENET_PTP_TSUH */ -#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - -/* ENET_PTP_TSUL */ -#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ -#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ - -/* ENET_PTP_TSADDEND */ -#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ - -/* ENET_PTP_ETH */ -#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - -/* ENET_PTP_ETL */ -#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - -/* ENET_DMA_BCTL */ -#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ -#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ -#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ -#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ -#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ -#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ -#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ -#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ -#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ -#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ - -/* ENET_DMA_TPEN */ -#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - -/* ENET_DMA_RPEN */ -#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ - -/* ENET_DMA_RDTADDR */ -#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - -/* ENET_DMA_TDTADDR */ -#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - -/* ENET_DMA_STAT */ -#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ -#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ -#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ -#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ -#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ -#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ -#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ -#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ -#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ -#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ -#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ -#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ -#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ -#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ -#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ -#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ -#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ -#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ -#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ -#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ -#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - -/* ENET_DMA_CTL */ -#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ -#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ -#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ -#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ -#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ -#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ -#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ -#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ -#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ -#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ -#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ -#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - -/* ENET_DMA_INTEN */ -#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ -#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ -#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ -#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ -#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ -#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ -#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ -#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ -#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ -#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ -#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ -#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ -#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - -/* ENET_DMA_MFBOCNT */ -#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ -#define ENET_DMA_MFBOCNT_OBMFC BIT(16) /* Overflow bit for missed frame counter */ -#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ -#define ENET_DMA_MFBOCNT_OBFOC BIT(28) /*!< Overflow bit for FIFO overflow counter */ - -/* ENET_DMA_CTDADDR */ -#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ - -/* ENET_DMA_CRDADDR */ -#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - -/* ENET_DMA_CTBADDR */ -#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - -/* ENET_DMA_CRBADDR */ -#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ - -/* ENET DMA Tx descriptor TDES0 */ -#define ENET_TDES0_DB BIT(0) /*!< deferred */ -#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ -#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ -#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ -#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ -#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ -#define ENET_TDES0_LCO BIT(9) /*!< late collision */ -#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ -#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ -#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ -#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ -#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ -#define ENET_TDES0_ES BIT(15) /*!< error summary */ -#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ -#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ -#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ -#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ -#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ -#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ -#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ -#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ -#define ENET_TDES0_FSG BIT(28) /*!< first segment */ -#define ENET_TDES0_LSG BIT(29) /*!< last segment */ -#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ -#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ - -/* ENET DMA Tx descriptor TDES1 */ -#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ -#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ - -/* ENET DMA Tx descriptor TDES2 */ -#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ - -/* ENET DMA Tx descriptor TDES3 */ -#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ - -/* ENET DMA Rx descriptor RDES0 */ -#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ -#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ -#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ -#define ENET_RDES0_RERR BIT(3) /*!< receive error */ -#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ -#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ -#define ENET_RDES0_LCO BIT(6) /*!< late collision */ -#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ -#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ -#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ -#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ -#define ENET_RDES0_LERR BIT(12) /*!< length error */ -#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ -#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ -#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ -#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ -#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ -#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ - -/* ENET DMA Rx descriptor RDES1 */ -#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ -#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ -#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ -#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ -#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ - -/* ENET DMA Rx descriptor RDES2 */ -#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ - -/* ENET DMA Rx descriptor RDES3 */ -#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ - -/* constants definitions */ -/* define bit position and its register index offset */ -#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) -#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* ENET clock range judgement */ -#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) - -/* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) -#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) -#define ENET_ADDRH_BASE ((ENET) + 0x40U) -#define ENET_ADDRL_BASE ((ENET) + 0x44U) -#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) - -/* register offset */ -#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ -#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ -#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ -#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ - -#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ -#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ -#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ -#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ -#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ -#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ -#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ -#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ -#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ -#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ - -#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ -#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ -#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ -#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ -#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ -#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ -#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ -#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ - -/* ENET status flag get */ -typedef enum -{ - /* ENET_MAC_WUM register */ - ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ - /* ENET_MAC_FCTL register */ - ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ - /* ENET_MAC_INTF register */ - ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ - ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ - ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ - ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_flag_enum; - -/* ENET stutus flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_flag_clear_enum; - -/* ENET interrupt enable/disable */ -typedef enum -{ - /* ENET_MAC_INTMSK register */ - ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ - ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ - ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ - ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ - ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ - ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ - ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ - ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ - ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ - ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ - ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ - ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ - ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ - ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ - ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ - ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ - ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ - ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ - ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ - ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ - ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ - ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ - ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ -}enet_int_enum; - -/* ENET interrupt flag get */ -typedef enum -{ - /* ENET_MAC_INTF register */ - ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_int_flag_enum; - -/* ENET interrupt flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_int_flag_clear_enum; - -/* current RX/TX descriptor/buffer/descriptor table address get */ -typedef enum -{ - ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ - ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ - ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ - ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ - ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ - ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ -}enet_desc_reg_enum; - -/* MAC statistics counter get */ -typedef enum -{ - ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ - ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ - ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ - ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ - ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ - ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; - -/* function option, used for ENET initialization */ -typedef enum -{ - FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ - DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ - DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ - DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ - STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ - DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ - VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ - FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ - HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ - HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ - FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ - HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ - TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ - INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ -}enet_option_enum; - -/* phy mode and mac loopback configurations */ -typedef enum -{ - ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ - ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ - ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ - ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ - ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ - ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ -}enet_mediamode_enum; - -/* IP frame checksum function */ -typedef enum -{ - ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ - ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ - ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped */ -}enet_chksumconf_enum; - -/* received frame filter function */ -typedef enum -{ - ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ - ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ - ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ - ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ -}enet_frmrecept_enum; - -/* register group value get */ -typedef enum -{ - ALL_MAC_REG = 0, /*!< MAC register group */ - ALL_MSC_REG = 22, /*!< MSC register group */ - ALL_PTP_REG = 33, /*!< PTP register group */ - ALL_DMA_REG = 44, /*!< DMA register group */ -}enet_registers_type_enum; - -/* dma direction select */ -typedef enum -{ - ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ - ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ -}enet_dmadirection_enum; - -/* PHY operation direction select */ -typedef enum -{ - ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ - ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ -}enet_phydirection_enum; - -/* register operation direction select */ -typedef enum -{ - ENET_REG_READ, /*!< read register */ - ENET_REG_WRITE /*!< write register */ -}enet_regdirection_enum; - -/* ENET MAC addresses */ -typedef enum -{ - ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ - ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ - ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ - ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ -}enet_macaddress_enum; - -/* descriptor information */ -typedef enum -{ - TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ - TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ - RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ - RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ - RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ - RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ -}enet_descstate_enum; - -/* structure for initialization of the ENET */ -typedef struct -{ - uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ - uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ - uint32_t dma_maxburst; /*!< DMA max burst related parameters */ - uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ - uint32_t store_forward_mode; /*!< store forward mode related parameters */ - uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ - uint32_t flow_control; /*!< flow control related parameters */ - uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ - uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ - uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ - uint32_t timer_config; /*!< frame timer related parameters */ - uint32_t interframegap; /*!< inter frame gap related parameters */ -}enet_initpara_struct; - -/* structure for ENET DMA desciptors */ -typedef struct -{ - uint32_t status; /*!< status */ - uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ - uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ - uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ -} enet_descriptors_struct; - -/* structure of PTP system time */ -typedef struct -{ - uint32_t second; /*!< second of system time */ - uint32_t nanosecond; /*!< nanosecond of system time */ - uint32_t sign; /*!< sign of system time */ -}enet_ptp_systime_struct; - -/* mac_cfg register value */ -#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ -#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ -#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ -#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ - -#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ -#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ -#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ -#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ -#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ -#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ -#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ -#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ - -#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ -#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - -#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ -#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ - -#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ -#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - -#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ -#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ - -#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ -#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ - -#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ -#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ - -#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ -#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ - -#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ -#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ - -#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ -#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ - -#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ -#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ -#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ - -#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ -#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ - -/* mac_frmf register value */ -#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ -#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ -#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ -#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ -#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - -#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ -#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - -#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ -#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ -#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ -#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ -#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ - -#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ -#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - -#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ - -#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ -#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - -#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ -#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ -#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ -#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ -#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ -#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ -#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ - -#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ -#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ -#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ -#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ - -/* mac_phy_ctl register value */ -#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ -#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ -#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ -#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ -#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ - -#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ - -#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ - -/* mac_phy_data register value */ -#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ - -/* mac_fctl register value */ -#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ -#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ -#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ -#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ - -#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ - -#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ -#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - -#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ -#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ -#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ - -#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ - -#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - -#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ -/* mac_vlt register value */ -#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - -#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ -#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ - -/* mac_wum register value */ -#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ -#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ -#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ -#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ - -/* mac_addr0h register value */ -#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ - -/* mac_addrxh register value, x = 1,2,3 */ -#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ - -#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ -#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ -#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ -#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ - -#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ -#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - -/* mac_fcth register value */ -#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ -#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ -#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ -#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ -#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ -#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ -#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ -#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ - -#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ -#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ -#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ -#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ - -/* msc_ctl register value */ -#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ -#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ -#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ - -/* ptp_tsctl register value */ -#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ -#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ - -/* ptp_ssinc register value */ -#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ - -/* ptp_tsl register value */ -#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - -#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ -#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ - -#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ - -/* ptp_tsul register value */ -#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ - -#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ -#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ - -/* dma_bctl register value */ -#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ -#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ - -#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ -#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ -#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ -#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ -#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ - -#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ -#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ -#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ -#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ -#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ - -#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ -#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ - -#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ -#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ -#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ -#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ -#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ -#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ -#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ -#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ -#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ - -#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ -#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ - -#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ -#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ - -/* dma_stat register value */ -#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ -#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ -#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ -#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ -#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ -#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ -#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ - -#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ -#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ -#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ -#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ -#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ -#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ -#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ - -#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ -#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ -#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ -#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ - -/* dma_ctl register value */ -#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ -#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ -#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ -#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ - -#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ -#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ -#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ -#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ -#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ -#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ -#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ -#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ - -#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ -#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ - -#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ -#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ - -#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ -#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ -#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ - -#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ -#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ - -#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ -#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ -#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ - -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ - -#define ENET_SECONDFRAME_OPT_ENABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode enable*/ -#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ -#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ - -/* dma_mfbocnt register value */ -#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ - -#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ - -/* dma tx descriptor tdes0 register value */ -#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ -#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ - -#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ - -/* dma tx descriptor tdes1 register value */ -#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ - -#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ - -/* dma rx descriptor rdes0 register value */ -#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ -#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ - -/* dma rx descriptor rdes1 register value */ -#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ -#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ - -#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ - -#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ - -/* dma rx descriptor rdes4 register value */ -#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ -#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ - -#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ -#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ - -/* ENET register mask value */ -#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ -#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ -#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ -#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ - -#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ -#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ - -typedef enum{ - ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ - ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ - ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ - ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ -}enet_ptp_function_enum; - - -/* ENET remote wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ - -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ - -/* ENET delay timeout */ -#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ -#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ - -/* function declarations */ -/* main function */ -/* deinitialize the ENET, and reset structure parameters for ENET initialization */ -void enet_deinit(void); -/* configure the parameters which are usually less cared for initialization */ -void enet_initpara_config(enet_option_enum option, uint32_t para); -/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); -/* reset all core internal registers located in CLK_TX and CLK_RX */ -ErrStatus enet_software_reset(void); -/* check receive frame valid and return frame size */ -uint32_t enet_rxframe_size_get(void); -/* initialize the dma tx/rx descriptors's parameters in chain mode */ -void enet_descriptors_chain_init(enet_dmadirection_enum direction); -/* initialize the dma tx/rx descriptors's parameters in ring mode */ -void enet_descriptors_ring_init(enet_dmadirection_enum direction); -/* handle current received frame data to application buffer */ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); -/* handle current received frame but without data copy to application buffer */ -#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) -/* handle application buffer data to transmit it */ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); -/* handle current transmit frame but without data copy from application buffer */ -#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) -/* configure the transmit IP frame checksum offload calculation and insertion */ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); -/* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); -/* ENET Tx and Rx function disable (include MAC and DMA module) */ -void enet_disable(void); -/* configure MAC address */ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); - -/* get the ENET MAC/MSC/PTP/DMA status flag */ -FlagStatus enet_flag_get(enet_flag_enum enet_flag); -/* clear the ENET DMA status flag */ -void enet_flag_clear(enet_flag_clear_enum enet_flag); -/* enable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_enable(enet_int_enum enet_int); -/* disable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_disable(enet_int_enum enet_int); -/* get ENET MAC/MSC/DMA interrupt flag */ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); -/* clear ENET DMA interrupt flag */ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); - -/* MAC function */ -/* ENET Tx function enable (include MAC and DMA module) */ -void enet_tx_enable(void); -/* ENET Tx function disable (include MAC and DMA module) */ -void enet_tx_disable(void); -/* ENET Rx function enable (include MAC and DMA module) */ -void enet_rx_enable(void); -/* ENET Rx function disable (include MAC and DMA module) */ -void enet_rx_disable(void); -/* put registers value into the application buffer */ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); -/* enable the MAC address filter */ -void enet_address_filter_enable(enet_macaddress_enum mac_addr); -/* disable the MAC address filter */ -void enet_address_filter_disable(enet_macaddress_enum mac_addr); -/* configure the MAC address filter */ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); -/* PHY interface configuration (configure SMI clock and reset PHY chip) */ -ErrStatus enet_phy_config(void); -/* write to/read from a PHY register */ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); -/* enable the loopback function of phy chip */ -ErrStatus enet_phyloopback_enable(void); -/* disable the loopback function of phy chip */ -ErrStatus enet_phyloopback_disable(void); -/* enable ENET forward feature */ -void enet_forward_feature_enable(uint32_t feature); -/* disable ENET forward feature */ -void enet_forward_feature_disable(uint32_t feature); -/* enable ENET fliter feature */ -void enet_fliter_feature_enable(uint32_t feature); -/* disable ENET fliter feature */ -void enet_fliter_feature_disable(uint32_t feature); - -/* flow control function */ -/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ -ErrStatus enet_pauseframe_generate(void); -/* configure the pause frame detect type */ -void enet_pauseframe_detect_config(uint32_t detect); -/* configure the pause frame parameters */ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); -/* configure the threshold of the flow control(deactive and active threshold) */ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); -/* enable ENET flow control feature */ -void enet_flowcontrol_feature_enable(uint32_t feature); -/* disable ENET flow control feature */ -void enet_flowcontrol_feature_disable(uint32_t feature); - -/* DMA function */ -/* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); -/* poll the dma transmission/reception enable */ -void enet_dmaprocess_resume(enet_dmadirection_enum direction); -/* check and recover the Rx process */ -void enet_rxprocess_check_recovery(void); -/* flush the ENET transmit fifo, and wait until the flush operation completes */ -ErrStatus enet_txfifo_flush(void); -/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); -/* get the Tx or Rx descriptor information */ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); -/* get the number of missed frames during receiving */ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); - -/* descriptor function */ -/* get the bit flag of ENET dma descriptor */ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); -/* set the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); -/* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will set */ -void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will not set */ -void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc); -/* drop current receive frame */ -void enet_rxframe_drop(void); -/* enable DMA feature */ -void enet_dma_feature_enable(uint32_t feature); -/* disable DMA feature */ -void enet_dma_feature_disable(uint32_t feature); - -/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); -/* handle current received frame but without data copy to application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) -/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); -/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) - -/* WUM function */ -/* wakeup frame filter register pointer reset */ -void enet_wum_filter_register_pointer_reset(void); -/* set the remote wakeup frame registers */ -void enet_wum_filter_config(uint32_t pdata[]); -/* enable wakeup management features */ -void enet_wum_feature_enable(uint32_t feature); -/* disable wakeup management features */ -void enet_wum_feature_disable(uint32_t feature); - -/* MSC function */ -/* reset the MAC statistics counters */ -void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ -void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ -void enet_msc_feature_disable(uint32_t feature); -/* get MAC statistics counter */ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); - -/* PTP function */ -/* change subsecond to nanosecond */ -uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond); -/* change nanosecond to subsecond */ -uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond); -/* enable the PTP features */ -void enet_ptp_feature_enable(uint32_t feature); -/* disable the PTP features */ -void enet_ptp_feature_disable(uint32_t feature); -/* configure the PTP timestamp function */ -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); -/* configure the PTP system time subsecond increment value */ -void enet_ptp_subsecond_increment_config(uint32_t subsecond); -/* adjusting the PTP clock frequency only in fine update mode */ -void enet_ptp_timestamp_addend_config(uint32_t add); -/* initializing or adding/subtracting to second of the PTP system time */ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); -/* configure the PTP expected target time */ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); -/* get the PTP current system time */ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); -/* configure and start PTP timestamp counter */ -void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg); -/* adjust frequency in fine method by configure addend register */ -void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); -/* update system time in coarse method */ -void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); -/* set system time in fine method */ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); -/* get the ptp flag status */ -FlagStatus enet_ptp_flag_get(uint32_t flag); - -/* internal function */ -/* reset the ENET initpara struct, call it before using enet_initpara_config() */ -void enet_initpara_reset(void); -/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ -static void enet_default_init(void); -#ifdef USE_DELAY -/* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms -#else -/* insert a delay time */ -static void enet_delay(uint32_t ncount); -/* default _ENET_DELAY_ function with less precise timing */ -#define _ENET_DELAY_ enet_delay -#endif - -#endif /* GD32F10X_ENET_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h deleted file mode 100644 index b9b1478a04..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exmc.h +++ /dev/null @@ -1,432 +0,0 @@ -/*! - \file gd32f10x_exmc.h - \brief definitions for the EXMC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_EXMC_H -#define GD32F10X_EXMC_H - -#include "gd32f10x.h" - -/* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ - -/* registers definitions */ -/* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ - -#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */ -#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */ -#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */ - -#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */ -#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */ -#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */ - -#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */ -#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */ -#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */ - -/* NAND/PC card */ -#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */ -#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */ -#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */ -#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */ -#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */ - -#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */ -#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */ -#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */ -#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */ -#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */ - -#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */ -#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */ -#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */ -#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */ -#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ - -/* bits definitions */ -/* NOR/PSRAM */ -/* EXMC_SNCTLx,x=0..3 */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ -#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ - -/* EXMC_SNTCFGx,x=0..3 */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* EXMC_SNWTCFGx,x=0..3 */ -#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNWTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNWTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* NAND/PC card */ -/* EXMC_NPCTLx,x=1..3 */ -#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ -#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ -#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ -#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ -#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ -#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ -#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ -#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ - -/* EXMC_NPINTENx,x=1..3 */ -#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ -#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ -#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ -#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ -#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ -#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ -#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ - -/* EXMC_NPCTCFGx,x=1..3 */ -#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ -#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ -#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ -#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ - -/* EXMC_NPATCFGx,x=1..3 */ -#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ -#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ -#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ -#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ - -/* EXMC_PIOTCFG3 */ -#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ -#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ -#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ -#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ - -/* EXMC_NECCx,x=1,2 */ -#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ - -/* constants definitions */ -/* EXMC NOR/SRAM timing initialize struct */ -typedef struct -{ - uint32_t asyn_access_mode; /*!< asynchronous access mode */ - uint32_t syn_data_latency; /*!< configure the data latency */ - uint32_t syn_clk_division; /*!< configure the clock divide ratio */ - uint32_t bus_latency; /*!< configure the bus latency */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ - uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ -}exmc_norsram_timing_parameter_struct; - -/* EXMC NOR/SRAM initialize struct */ -typedef struct -{ - uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ - uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ - uint32_t extended_mode; /*!< enable or disable the extended mode */ - uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ - uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ - uint32_t memory_write; /*!< enable or disable the write operation */ - uint32_t nwait_config; /*!< NWAIT signal configuration */ - uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ - uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ - uint32_t burst_mode; /*!< enable or disable the burst mode */ - uint32_t databus_width; /*!< specifies the databus width of external memory */ - uint32_t memory_type; /*!< specifies the type of external memory */ - uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing - parameters for read if the extended mode is used */ - exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ -}exmc_norsram_parameter_struct; - -/* EXMC NAND/PC card timing initialize struct */ -typedef struct -{ - uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ - uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ - uint32_t waittime; /*!< configure the minimum wait time */ - uint32_t setuptime; /*!< configure the address setup time */ -}exmc_nand_pccard_timing_parameter_struct; - -/* EXMC NAND initialize struct */ -typedef struct -{ - uint32_t nand_bank; /*!< select the bank of NAND */ - uint32_t ecc_size; /*!< the page size for the ECC calculation */ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ - uint32_t databus_width; /*!< the NAND flash databus width */ - uint32_t wait_feature; /*!< enables or disables the wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ -}exmc_nand_parameter_struct; - -/* EXMC PC card initialize struct */ -typedef struct -{ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t wait_feature; /*!< enables or disables the Wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ - exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ -}exmc_pccard_parameter_struct;; - -/* EXMC register address */ -#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */ - -#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */ - -/* NOR bank memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ - -/* NOR bank memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - -/* asynchronous access mode */ -#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ -#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ -#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ -#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ - -/* data latency for NOR flash */ -#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ -#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ -#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ -#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ -#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ -#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ -#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ -#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ -#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ -#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ -#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ -#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ -#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ -#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ -#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ -#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ - -/* synchronous clock divide ratio */ -#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ - -/* ECC size */ -#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ -#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ -#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ -#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ -#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ -#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ - -/* ALE to RE delay */ -#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ -#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ -#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ -#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ -#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ -#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ -#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ -#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ -#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ -#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ -#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ -#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ -#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ -#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ -#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ -#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ - -/* CLE to RE delay */ -#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ -#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ -#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ -#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ -#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ -#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ -#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ -#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ -#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ -#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ -#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ -#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ -#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ -#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ -#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ -#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ - -/* NAND bank memory data bus width */ -#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ -#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ - -/* EXMC NOR/SRAM bank region definition */ -#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ -#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ -#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ -#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ - -/* EXMC NOR/SRAM write mode */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ -#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */ - -/* EXMC NWAIT signal configuration */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ -#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ - -/* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ - -/* EXMC NAND/PC card bank definition */ -#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ -#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ -#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ - -/* EXMC flag bits */ -#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ -#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ -#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ -#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ - -/* EXMC interrupt flag bits */ -#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ -#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ -#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ - -/* function declarations */ -/* deinitialize EXMC NOR/SRAM region */ -void exmc_norsram_deinit(uint32_t norsram_region); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* initialize EXMC NOR/SRAM region */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* EXMC NOR/SRAM bank enable */ -void exmc_norsram_enable(uint32_t norsram_region); -/* EXMC NOR/SRAM bank disable */ -void exmc_norsram_disable(uint32_t norsram_region); - -/* deinitialize EXMC NAND bank */ -void exmc_nand_deinit(uint32_t nand_bank); -/* initialize EXMC NAND bank */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* exmc_nand_init_struct parameter initialize */ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* EXMC NAND bank enable */ -void exmc_nand_enable(uint32_t nand_bank); -/* EXMC NAND bank disable */ -void exmc_nand_disable(uint32_t nand_bank); -/* enable or disable the EXMC NAND ECC function */ -void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue); -/* get the EXMC ECC value */ -uint32_t exmc_ecc_get(uint32_t nand_bank); - -/* deinitialize EXMC PC card bank */ -void exmc_pccard_deinit(void); -/* initialize EXMC PC card bank */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* exmc_pccard_parameter_struct parameter initialize */ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* EXMC PC card bank enable */ -void exmc_pccard_enable(void); -/* EXMC PC card bank disable */ -void exmc_pccard_disable(void); - -/* enable EXMC interrupt */ -void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source); -/* disable EXMC interrupt */ -void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source); -/* check EXMC flag is set or not */ -FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag); -/* clear EXMC flag */ -void exmc_flag_clear(uint32_t bank, uint32_t flag); -/* check EXMC flag is set or not */ -FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source); -/* clear EXMC flag */ -void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source); - -#endif /* GD32F10X_EXMC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h deleted file mode 100644 index 9822671976..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_exti.h +++ /dev/null @@ -1,258 +0,0 @@ -/*! - \file gd32f10x_exti.h - \brief definitions for the EXTI - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_EXTI_H -#define GD32F10X_EXTI_H - -#include "gd32f10x.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ -#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ -#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ -#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ -#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ -#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum -{ - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ -}exti_line_enum; - -/* external interrupt and event */ -typedef enum -{ - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum -{ - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising edge and falling edge trigger */ -}exti_trig_type_enum; - -/* function declarations */ -/* initialization, EXTI lines configuration functions */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - -/* interrupt & flag functions */ -/* get EXTI lines pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); -/* enable the EXTI software interrupt event */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable the EXTI software interrupt event */ -void exti_software_interrupt_disable(exti_line_enum linex); - -#endif /* GD32F10X_EXTI_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h deleted file mode 100644 index f5969b6436..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fmc.h +++ /dev/null @@ -1,370 +0,0 @@ -/*! - \file gd32f10x_fmc.h - \brief definitions for the FMC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_FMC_H -#define GD32F10X_FMC_H - -#include "gd32f10x.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option bytes base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ -#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ -#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ -#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ -#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ -#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ -#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ -#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ -#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ -#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ -#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ -#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ -#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ - -/* FMC_KEY0 */ -#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT0 */ -#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL0 */ -#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ -#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ -#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ -#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ -#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR0 */ -#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ -#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ -#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ -#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - -/* FMC_WP */ -#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ - -/* FMC_KEY1 */ -#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ - -/* FMC_STAT1 */ -#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL1 */ -#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ -#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ -#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ -#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ -#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR1 */ -#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */ - -/* FMC_WSEN */ -#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* define the FMC bit position and its register index offset */ -#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) -#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) -#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) - -/* configuration register */ -#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ -#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ -#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ -#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ -#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ - -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ -}fmc_state_enum; - -/* FMC interrupt enable */ -typedef enum -{ - FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ - FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ - FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ - FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ -}fmc_int_enum; - -/* FMC flags */ -typedef enum -{ - FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ - FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ - FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ - FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ - FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ - FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ - FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ - FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ - FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ -}fmc_flag_enum; - -/* FMC interrupt flags */ -typedef enum -{ - FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ - FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ - FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ - FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ -}fmc_interrupt_flag_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* FMC wait state counter */ -#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ -#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ -#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ - -/* option bytes software/hardware free watch dog timer */ -#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ -#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ - -/* option bytes reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ - -/* option bytes reset or not entering standby mode */ -#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ -#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ - -/* option bytes boot bank value */ -#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ -#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ - -#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ - -/* read protect configure */ -#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ -#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ - -/* OB_SPC */ -#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ -#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ - -/* OB_USER */ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ -#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ - -/* OB_WP0 */ -#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ - -/* OB_WP1 */ -#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ - -/* OB_WP2 */ -#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ - -/* OB_WP3 */ -#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ - -/* option bytes write protection */ -#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ -#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ -#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ -#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ -#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ -#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ -#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ -#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ -#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ -#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ -#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ -#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ -#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ -#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ -#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ -#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ -#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ -#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ -#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ -#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ -#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ - -/* FMC timeout */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ - -/* FMC BANK address */ -#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ -#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ -#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* set the FMC wait state counter */ -void fmc_wscnt_set(uint32_t wscnt); -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* unlock the FMC bank0 operation */ -void fmc_bank0_unlock(void); -/* unlock the FMC bank1 operation */ -void fmc_bank1_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* lock the bank0 FMC operation */ -void fmc_bank0_lock(void); -/* lock the bank1 FMC operation */ -void fmc_bank1_lock(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC erase whole bank0 */ -fmc_state_enum fmc_bank0_erase(void); -/* FMC erase whole bank1 */ -fmc_state_enum fmc_bank1_erase(void); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* erase the option byte */ -fmc_state_enum ob_erase(void); -/* enable write protect */ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); -/* configure the option byte security protection */ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte */ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); -/* program option bytes data */ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data); -/* get the FMC option byte user */ -uint8_t ob_user_get(void); -/* get OB_DATA in register FMC_OBSTAT */ -uint16_t ob_data_get(void); -/* get the FMC option byte write protection */ -uint32_t ob_write_protection_get(void); -/* get option byte security protection code value */ -FlagStatus ob_spc_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* check flag is set or not */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC flag */ -void fmc_flag_clear(uint32_t flag); -/* get FMC interrupt flag state */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); -/* clear FMC interrupt flag state */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); -/* return the FMC bank0 state */ -fmc_state_enum fmc_bank0_state_get(void); -/* return the FMC bank1 state */ -fmc_state_enum fmc_bank1_state_get(void); -/* check FMC bank0 ready or not */ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); -/* check FMC bank1 ready or not */ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); - -#endif /* GD32F10X_FMC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h deleted file mode 100644 index 2d22177e1e..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_fwdgt.h +++ /dev/null @@ -1,108 +0,0 @@ -/*! - \file gd32f10x_fwdgt.h - \brief definitions for the FWDGT - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_FWDGT_H -#define GD32F10X_FWDGT_H - -#include "gd32f10x.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE /*!< FWDGT base address */ - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ - -/* constants definitions */ -/* psc register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32F10X_FWDGT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h deleted file mode 100644 index 3b6b53a36d..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_gpio.h +++ /dev/null @@ -1,497 +0,0 @@ -/*! - \file gd32f10x_gpio.h - \brief definitions for the GPIO - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10x_GPIO_H -#define GD32F10x_GPIO_H - -#include "gd32f10x.h" - -/* GPIOx(x=A,B,C,D,E,F,G) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOE (GPIO_BASE + 0x00001000U) -#define GPIOF (GPIO_BASE + 0x00001400U) -#define GPIOG (GPIO_BASE + 0x00001800U) - -/* AFIO definitions */ -#define AFIO AFIO_BASE - -/* registers definitions */ - -/* GPIO registers definitions */ -#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ -#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ - -/* AFIO registers definitions */ -#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ -#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ -#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ -#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ -#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ -#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ -#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ - -/* bits definitions */ -/* GPIO_CTL0 */ -#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ -#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ -#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ -#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ -#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ -#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ -#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ -#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ -#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ -#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ -#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ -#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ -#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ -#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ -#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ -#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ - -/* GPIO_CTL1 */ -#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ -#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ -#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ -#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ -#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ -#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ -#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ -#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ -#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ -#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ -#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ -#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ -#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ -#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ -#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ -#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* AFIO_EC */ -#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ -#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ -#define AFIO_EC_EOE BIT(7) /*!< event output enable */ - -/* AFIO_PCF0 */ -#ifdef GD32F10X_CL -/* memory map and bit definitions for GD32F10X_CL devices */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ -#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ -#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ -#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ -#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ -#define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ -#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ - -#else -/* memory map and bit definitions for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_REMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ -#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ -#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -#endif /* GD32F10X_CL */ - -/* AFIO_EXTISS0 */ -#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ -#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ -#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ -#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ - -/* AFIO_EXTISS1 */ -#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ -#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ -#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ -#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ - -/* AFIO_EXTISS2 */ -#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ -#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ -#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ -#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ - -/* AFIO_EXTISS3 */ -#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ -#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ -#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ -#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ - -/* AFIO_PCF1 */ -#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ -#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ -#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ -#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ -#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ -#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* GPIO mode values set */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) -#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) - -/* GPIO mode definitions */ -#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ -#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ -#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ -#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ -#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ -#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ -#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ -#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ - -/* GPIO output max speed value */ -#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ - -/* GPIO event output port definitions */ -#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ -#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ -#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ -#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ -#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ - -/* GPIO output port source definitions */ -#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ -#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ -#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ -#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ -#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ -#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ -#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ - -/* GPIO event output pin definitions */ -#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ -#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ -#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ -#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ -#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ -#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ -#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ -#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ -#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ -#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ -#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ -#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ -#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ -#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ -#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ -#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ - -/* GPIO output pin source definitions */ -#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ -#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ -#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ -#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ -#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ -#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ -#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ -#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ -#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ -#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ -#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ -#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ -#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ -#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ -#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ -#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* GPIO remap definitions */ -#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ -#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ -#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ -#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ -#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ -#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ -#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ -#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ -#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ -#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ -#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ -#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN partial remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN full remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ -#if (defined(GD32F10X_CL) || defined(GD32F10X_HD)) -#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) */ -#endif /* GD32F10X_CL||GD32F10X_HD */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U) /*!< ADC0 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U) /*!< ADC1 external trigger regular conversion remapping(only for GD32F10X_MD devices, GD32F10X_HD devices and GD32F10X_XD devices) */ -#endif /* GD32F10X_MD||GD32F10X_HD||GD32F10X_XD */ -#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ -#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled and SW-DP enabled */ -#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled and SW-DP disabled */ -#ifdef GD32F10X_CL -#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping(only for GD32F10X_CL devices) */ -#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping(only for GD32F10X_CL devices) */ -#define GPIO_ENET_REMAP ((uint32_t)0x00200020U) /*!< ENET remapping(only for GD32F10X_CL devices) */ -#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping(only for GD32F10X_CL devices) */ -#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping(only for GD32F10X_CL devices) */ -#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) */ -#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U) /*!< ethernet PTP PPS remapping(only for GD32F10X_CL devices) */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD -#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U) /*!< TIMER8 remapping */ -#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U) /*!< TIMER9 remapping */ -#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U) /*!< TIMER10 remapping */ -#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U) /*!< TIMER12 remapping */ -#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U) /*!< TIMER13 remapping */ -#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ -#endif /* GD32F10X_XD */ - -#ifdef GD32F10X_CL -/* ethernet MII or RMII PHY selection */ -#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ -#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ -#endif /* GD32F10X_CL */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* reset alternate function I/O(AFIO) */ -void gpio_afio_deinit(void); -/* GPIO parameter initialization */ -void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* configure GPIO pin remap */ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); - -/* select GPIO pin exti sources */ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); -/* configure GPIO pin event output */ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); -/* enable GPIO pin event output */ -void gpio_event_output_enable(void); -/* disable GPIO pin event output */ -void gpio_event_output_disable(void); - -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -#ifdef GD32F10X_CL -/* select ethernet MII or RMII PHY */ -void gpio_ethernet_phy_select(uint32_t gpio_enetsel); -#endif /* GD32F10X_CL */ - - -#endif /* GD32F10x_GPIO_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h deleted file mode 100644 index ab884837dc..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_i2c.h +++ /dev/null @@ -1,346 +0,0 @@ -/*! - \file gd32f10x_i2c.h - \brief definitions for the I2C - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_I2C_H -#define GD32F10X_I2C_H - -#include "gd32f10x.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking register */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ - -/* I2C flags */ -typedef enum -{ - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ -}i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ -}i2c_interrupt_flag_enum; - -/* I2C interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ -}i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* dual-address mode switch */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); - -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); - -#endif /* GD32E10X_I2C_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h deleted file mode 100644 index 1c692733c8..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_misc.h +++ /dev/null @@ -1,95 +0,0 @@ -/*! - \file gd32f10x_misc.h - \brief definitions for the MISC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_MISC_H -#define GD32F10X_MISC_H - -#include "gd32f10x.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ -/* set the priority group */ -void nvic_priority_group_set(uint32_t nvic_prigroup); - -/* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); -/* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32F10X_MISC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h deleted file mode 100644 index 3805d75ad5..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_pmu.h +++ /dev/null @@ -1,129 +0,0 @@ -/*! - \file gd32f10x_pmu.h - \brief definitions for the PMU - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_PMU_H -#define GD32F10X_PMU_H - -#include "gd32f10x.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU registers */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* set PMU mode */ -/* PMU work at sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(void); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(void); - -/* backup related functions */ -/* enable write access to the registers in backup domain */ -void pmu_backup_write_enable(void); -/* disable write access to the registers in backup domain */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag_reset); - -#endif /* GD32F10X_PMU_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h deleted file mode 100644 index 7053c053f4..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rcu.h +++ /dev/null @@ -1,924 +0,0 @@ -/*! - \file gd32f10x_rcu.h - \brief definitions for the RCU - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_RCU_H -#define GD32F10X_RCU_H - -#include "gd32f10x.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ -#elif defined(GD32F10X_CL) -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* bits definitions */ -/* RCU_CTL */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#elif defined(GD32F10X_CL) -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ -#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ -#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ -#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_CFG0 */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#elif defined(GD32F10X_CL) -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_INT */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#elif defined(GD32F10X_CL) -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ -#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ -#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ -#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ -#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ -#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ -#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ -#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ -#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ -#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ -#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ -#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ -#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#ifndef GD32F10X_CL -#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD -#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ -#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ -#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ -#endif /* GD32F10X_XD */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ -#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ -#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ -#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ -#ifdef GD32F10X_XD -#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ -#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ -#endif /* GD32F10X_XD */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ -#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ -#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ -#ifdef GD32F10X_CL -#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ -#endif /* GD32F10X_CL */ -#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ -#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ -#elif defined(GD32F10X_CL) -#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ -#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ -#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ -#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ -#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ -#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ -#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ -#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ -#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ -#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ -#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ -#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ -#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#ifndef GD32F10X_CL -#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD -#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ -#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ -#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ -#endif /* GD32F10X_XD */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ -#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ -#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ -#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ -#ifdef GD32F10X_XD -#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ -#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ -#endif /* GD32F10X_XD */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ -#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ -#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ -#ifdef GD32F10X_CL -#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ -#endif /* GD32F10X_CL */ -#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -#ifdef GD32F10X_CL -/* RCU_AHBRST */ -#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ -#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ -#endif /* GD32F10X_CL */ - -#if defined(GD32F10X_CL) -/* RCU_CFG1 */ -#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ -#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ -#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ -#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ -#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ -#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ -#endif /* GD32F10X_CL */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -/* peripherals enable */ -#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ -#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ -#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ - -/* peripherals reset */ -#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ -#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ -#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ -#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ - -/* clock control */ -#define CTL_REG_OFFSET 0x00U /*!< control register offset */ -#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ - -/* clock stabilization and stuck interrupt */ -#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ - -/* configuration register */ -#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ -#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ - -/* peripheral clock enable */ -typedef enum -{ - /* AHB peripherals */ - RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ - RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ - RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ - RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ -#elif defined(GD32F10X_CL) - RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ - RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ - RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ - RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ -#if defined(GD32F10X_XD) - RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ - RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ -#endif /* GD32F10X_XD */ - RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ -#ifdef GD32F10X_CL - RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ -#endif /* GD32F10X_CL */ - RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ - RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - - /* APB2 peripherals */ - RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ - RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ - RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ - RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ - RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ - RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ - RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ - RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ -#ifndef GD32F10X_CL - RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD - RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ - RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ - RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ -#endif /* GD32F10X_XD */ -}rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum -{ - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ -}rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum -{ - /* AHB peripherals */ -#ifdef GD32F10X_CL - RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ -#endif /* GD32F10X_CL */ - - /* APB1 peripherals */ - RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ - RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ - RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ - RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ -#ifdef GD32F10X_XD - RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ - RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ -#endif /* GD32F10X_XD */ - RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ - RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ - RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ - RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ - RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ - RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ -#ifdef GD32F10X_CL - RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ -#endif /* GD32F10X_CL */ - RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ - RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ - RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - - /* APB2 peripherals */ - RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ - RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ - RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ - RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ - RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ - RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ - RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ -#ifndef GD32F10X_CL - RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ -#endif /* GD32F10X_CL */ -#ifdef GD32F10X_XD - RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ - RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ - RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ -#endif /* GD32F10X_XD */ -}rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum -{ - /* clock stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ -#ifdef GD32F10X_CL - RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ - RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ -#endif /* GD32F10X_CL */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ - /* reset source flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ -}rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ -#ifdef GD32F10X_CL - RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ - RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ -#endif /* GD32F10X_CL */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ -}rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ -#ifdef GD32F10X_CL - RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ -#endif /* GD32F10X_CL */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ -}rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum -{ - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ -#ifdef GD32F10X_CL - RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ - RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ -#endif /* GD32F10X_CL */ -}rcu_int_enum; - -/* oscillator types */ -typedef enum -{ - RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ - RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ -#ifdef GD32F10X_CL - RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ - RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ -#endif /* GD32F10X_CL */ -}rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum -{ - CK_SYS = 0, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ -}rcu_clock_freq_enum; - -/* RCU_CFG0 register bit define */ -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC prescaler select */ -#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ -#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ -#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ -#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ -#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ -#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ -#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ - -/* PLL clock multiplication factor */ -#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ - -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ -#elif defined(GD32F10X_CL) -#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ - -/* USBD/USBFS prescaler select */ -#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ -#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ -#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ -#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ - -/* CKOUT0 clock source selection */ -#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ -#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ -#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ -#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ -#ifdef GD32F10X_CL -#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ -#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ -#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ -#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ -#endif /* GD32F10X_CL */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ -#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - -/* PREDV0 division factor */ -#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ -#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ -#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ -#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ -#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ -#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ -#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ -#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ -#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ -#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ -#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ -#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ -#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ -#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ -#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ -#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - -/* PREDV1 division factor */ -#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ -#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ -#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ -#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ -#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ -#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ -#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ -#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ -#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ -#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ -#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ -#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ -#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ -#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ -#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ -#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - -/* PLL1 clock multiplication factor */ -#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ -#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ -#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ -#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ -#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ -#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ -#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ -#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ -#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ -#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - -/* PLL2 clock multiplication factor */ -#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ -#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ -#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ -#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ -#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ -#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ -#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ -#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ -#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ -#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ - -#ifdef GD32F10X_CL -/* PREDV0 input clock source selection */ -#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ -#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ - -/* I2S1 clock source selection */ -#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ -#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ - -/* I2S2 clock source selection */ -#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ -#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ -#endif /* GD32F10X_CL */ - -/* deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ - -/* function declarations */ -/* initialization, peripheral clock enable/disable functions */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP domain */ -void rcu_bkp_reset_enable(void); -/* disable the BKP domain reset */ -void rcu_bkp_reset_disable(void); - -/* clock configuration functions */ -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the CK_OUT0 clock source and divider */ -void rcu_ckout0_config(uint32_t ckout0_src); -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_div); -#elif defined(GD32F10X_CL) -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); -/* configure the PREDV1 division factor */ -void rcu_predv1_config(uint32_t predv1_div); -/* configure the PLL1 clock */ -void rcu_pll1_config(uint32_t pll_mul); -/* configure the PLL2 clock */ -void rcu_pll2_config(uint32_t pll_mul); -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/* peripheral clock configuration functions */ -/* configure the ADC division factor */ -void rcu_adc_clock_config(uint32_t adc_psc); -/* configure the USBD/USBFS prescaler factor */ -void rcu_usb_clock_config(uint32_t usb_psc); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -#ifdef GD32F10X_CL -/* configure the I2S1 clock source selection */ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source); -/* configure the I2S2 clock source selection */ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source); -#endif /* GD32F10X_CL */ - -/* interrupt & flag functions */ -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* oscillator configuration functions */ -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32F10X_RCU_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h deleted file mode 100644 index 580617014f..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_rtc.h +++ /dev/null @@ -1,152 +0,0 @@ -/*! - \file gd32f10x_rtc.h - \brief definitions for the RTC - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_RTC_H -#define GD32F10X_RTC_H - -#include "gd32f10x.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ -#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ -#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ -#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ -#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ -#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ -#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ -#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ -#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ -#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ - -/* bits definitions */ -/* RTC_INTEN */ -#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ -#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ -#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ - -/* RTC_CTL */ -#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ -#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ -#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ -#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ -#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ -#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - -/* RTC_PSCH */ -#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ - -/* RTC_PSCL */ -#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ - -/* RTC_DIVH */ -#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ - -/* RTC_DIVL */ -#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ - -/* RTC_CNTH */ -#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ - -/* RTC_CNTL */ -#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ - -/* RTC_ALRMH */ -#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ - -/* RTC_ALRML */ -#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ - -/* constants definitions */ -/* RTC interrupt enable or disable definitions */ -#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ -#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ -#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ - -/* RTC interrupt flag definitions */ -#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ - -/* RTC flag definitions */ -#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ -#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ - -/* function declarations */ -/* initialization functions */ -/* enter RTC configuration mode */ -void rtc_configuration_mode_enter(void); -/* exit RTC configuration mode */ -void rtc_configuration_mode_exit(void); -/* set RTC counter value */ -void rtc_counter_set(uint32_t cnt); -/* set RTC prescaler value */ -void rtc_prescaler_set(uint32_t psc); - -/* operation functions */ -/* wait RTC last write operation finished flag set */ -void rtc_lwoff_wait(void); -/* wait RTC registers synchronized flag set */ -void rtc_register_sync_wait(void); -/* set RTC alarm value */ -void rtc_alarm_config(uint32_t alarm); -/* get RTC counter value */ -uint32_t rtc_counter_get(void); -/* get RTC divider value */ -uint32_t rtc_divider_get(void); - -/* flag & interrupt functions */ -/* get RTC flag status */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear RTC flag status */ -void rtc_flag_clear(uint32_t flag); -/* get RTC interrupt flag status */ -FlagStatus rtc_interrupt_flag_get(uint32_t flag); -/* clear RTC interrupt flag status */ -void rtc_interrupt_flag_clear(uint32_t flag); -/* enable RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disable RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); - -#endif /* GD32F10X_RTC_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h deleted file mode 100644 index c905e10200..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_sdio.h +++ /dev/null @@ -1,430 +0,0 @@ -/*! - \file gd32f10x_sdio.h - \brief definitions for the SDIO - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_SDIO_H -#define GD32F10X_SDIO_H - -#include "gd32f10x.h" - -/* SDIO definitions */ -#define SDIO SDIO_BASE - -/* registers definitions */ -#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ -#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ -#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ -#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ -#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ -#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ -#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ -#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ -#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ -#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ -#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ -#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ -#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ -#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ -#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ -#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ -#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ -#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ - -/* bits definitions */ -/* SDIO_PWRCTL */ -#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ - -/* SDIO_CLKCTL */ -#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ -#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ -#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ -#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ -#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ -#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ - -/* SDIO_CMDAGMT */ -#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ - -/* SDIO_CMDCTL */ -#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ -#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ -#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ -#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ -#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ -#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ -#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ -#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ -#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ - -/* SDIO_DATATO */ -#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ - -/* SDIO_DATALEN */ -#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ - -/* SDIO_DATACTL */ -#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ -#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ -#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ -#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ -#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ -#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ -#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ -#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ -#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ - -/* SDIO_STAT */ -#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ -#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ -#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ -#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ -#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ -#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ -#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ -#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ -#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ -#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ -#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ -#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ -#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ -#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ -#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ -#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ -#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ -#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ -#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ -#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ -#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ -#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ -#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ -#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ - -/* SDIO_INTC */ -#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ -#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ -#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ -#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ -#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ -#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ -#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ -#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ -#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ -#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ -#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ -#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ -#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ - -/* SDIO_INTEN */ -#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ -#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ -#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ -#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ -#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ -#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ -#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ -#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ -#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ -#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ -#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ -#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ -#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ -#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ -#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ -#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ -#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ -#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ -#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ -#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ -#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ -#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ -#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ -#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ - -/* SDIO_FIFO */ -#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ - -/* constants definitions */ -/* SDIO flags */ -#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ -#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ -#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ -#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ -#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ -#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ -#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ -#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ -#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ -#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ -#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ -#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ -#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ -#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ -#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ -#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ -#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ -#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ -#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ -#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ -#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ -#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ -#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ -#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ - -/* SDIO interrupt enable or disable */ -#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ -#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ -#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ -#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ -#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ -#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ -#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ -#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ -#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ -#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ -#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ -#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ -#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ -#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ -#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ -#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ -#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ -#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ -#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ -#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ -#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ -#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ -#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ -#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ - -/* SDIO interrupt flags */ -#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ -#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ -#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ -#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ -#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */ -#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */ -#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ -#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ -#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */ -#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */ -#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ -#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ -#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ -#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ -#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */ -#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */ -#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */ -#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */ -#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */ -#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */ -#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ -#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ -#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ -#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ - -/* SDIO power control */ -#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ -#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ - -/* SDIO card bus mode control */ -#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ -#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ -#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ - -/* SDIO_CLK clock edge selection */ -#define SDIO_SDIOCLKEDGE_RISING ((uint32_t)0x00000000U)/*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ -#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ - -/* clock bypass enable or disable */ -#define SDIO_CLOCKBYPASS_DISABLE ((uint32_t)0x00000000U)/*!< no bypass */ -#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ - -/* SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLOCKPWRSAVE_DISABLE ((uint32_t)0x00000000U)/*!< SDIO_CLK clock is always on */ -#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ - -/* SDIO command response type */ -#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ -#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ -#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ - -/* command state machine wait type */ -#define SDIO_WAITTYPE_NO ((uint32_t)0x00000000U)/*!< not wait interrupt */ -#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ -#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ - -#define SDIO_RESPONSE0 ((uint32_t)0x00000000U)/*!< card response[31:0]/card response[127:96] */ -#define SDIO_RESPONSE1 ((uint32_t)0x00000001U)/*!< card response[95:64] */ -#define SDIO_RESPONSE2 ((uint32_t)0x00000002U)/*!< card response[63:32] */ -#define SDIO_RESPONSE3 ((uint32_t)0x00000003U)/*!< card response[31:1], plus bit 0 */ - -/* SDIO data block size */ -#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ -#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ -#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ -#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ -#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ -#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ -#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ -#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ -#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ -#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ -#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ -#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ -#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ -#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ -#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ - -/* SDIO data transfer mode */ -#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000U)/*!< block transfer */ -#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ - -/* SDIO data transfer direction */ -#define SDIO_TRANSDIRECTION_TOCARD ((uint32_t)0x00000000U)/*!< write data to card */ -#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ - -/* SDIO read wait type */ -#define SDIO_READWAITTYPE_DAT2 ((uint32_t)0x00000000U)/*!< read wait control using SDIO_DAT[2] */ -#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ - -/* function declarations */ -/* deinitialize the SDIO */ -void sdio_deinit(void); -/* configure the SDIO clock */ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); -/* enable hardware clock control */ -void sdio_hardware_clock_enable(void); -/* disable hardware clock control */ -void sdio_hardware_clock_disable(void); -/* set different SDIO card bus mode */ -void sdio_bus_mode_set(uint32_t bus_mode); -/* set the SDIO power state */ -void sdio_power_state_set(uint32_t power_state); -/* get the SDIO power state */ -uint32_t sdio_power_state_get(void); -/* enable SDIO_CLK clock output */ -void sdio_clock_enable(void); -/* disable SDIO_CLK clock output */ -void sdio_clock_disable(void); - -/* configure the command index, argument, response type, wait type and CSM to send command */ -/* configure the command and response */ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); -/* set the command state machine wait type */ -void sdio_wait_type_set(uint32_t wait_type); -/* enable the CSM(command state machine) */ -void sdio_csm_enable(void); -/* disable the CSM(command state machine) */ -void sdio_csm_disable(void); -/* get the last response command index */ -uint8_t sdio_command_index_get(void); -/* get the response for the last received command */ -uint32_t sdio_response_get(uint32_t responsex); - -/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ -/* configure the data timeout, data length and data block size */ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); -/* configure the data transfer mode and direction */ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); -/* enable the DSM(data state machine) for data transfer */ -void sdio_dsm_enable(void); -/* disable the DSM(data state machine) */ -void sdio_dsm_disable(void); -/* write data(one word) to the transmit FIFO */ -void sdio_data_write(uint32_t data); -/* read data(one word) from the receive FIFO */ -uint32_t sdio_data_read(void); -/* get the number of remaining data bytes to be transferred to card */ -uint32_t sdio_data_counter_get(void); -/* get the number of words remaining to be written or read from FIFO */ -uint32_t sdio_fifo_counter_get(void); -/* enable the DMA request for SDIO */ -void sdio_dma_enable(void); -/* disable the DMA request for SDIO */ -void sdio_dma_disable(void); - -/* get the flags state of SDIO */ -FlagStatus sdio_flag_get(uint32_t flag); -/* clear the pending flags of SDIO */ -void sdio_flag_clear(uint32_t flag); -/* enable the SDIO interrupt */ -void sdio_interrupt_enable(uint32_t int_flag); -/* disable the SDIO interrupt */ -void sdio_interrupt_disable(uint32_t int_flag); -/* get the interrupt flags state of SDIO */ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); -/* clear the interrupt pending flags of SDIO */ -void sdio_interrupt_flag_clear(uint32_t int_flag); - -/* enable the read wait mode(SD I/O only) */ -void sdio_readwait_enable(void); -/* disable the read wait mode(SD I/O only) */ -void sdio_readwait_disable(void); -/* enable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_enable(void); -/* disable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_disable(void); -/* set the read wait type(SD I/O only) */ -void sdio_readwait_type_set(uint32_t readwait_type); -/* enable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_enable(void); -/* disable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_disable(void); -/* enable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_enable(void); -/* disable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_disable(void); - -/* enable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_enable(void); -/* disable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_disable(void); -/* enable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_enable(void); -/* disable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_disable(void); -/* enable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_enable(void); -/* disable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_disable(void); - -#endif /* GD32F10X_SDIO_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h deleted file mode 100644 index 0cd8c26786..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_spi.h +++ /dev/null @@ -1,328 +0,0 @@ -/*! - \file gd32f10x_spi.h - \brief definitions for the SPI - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_SPI_H -#define GD32F10X_SPI_H - -#include "gd32f10x.h" - -/* SPIx(x=0,1,2) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE -#define SPI2 (SPI_BASE + 0x00000400U) - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial value */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC value */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC value */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct -{ - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI frame size */ -#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ -#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ - -/* function declarations */ -/* SPI/I2S deinitialization and initialization functions */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); -/* initialize SPI parameter */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph,uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* NSS functions */ -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* DMA communication */ -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); - -/* normal mode communication */ -/* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); - -/* flag and interrupt functions */ -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -#endif /* GD32F10X_SPI_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h deleted file mode 100644 index 01af9b655c..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_timer.h +++ /dev/null @@ -1,730 +0,0 @@ -/*! - \file gd32f10x_timer.h - \brief definitions for the TIMER - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_TIMER_H -#define GD32F10X_TIMER_H - -#include "gd32f10x.h" - -/* TIMERx(x=0..13) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER1 (TIMER_BASE + 0x00000000U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER3 (TIMER_BASE + 0x00000800U) -#define TIMER4 (TIMER_BASE + 0x00000C00U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER6 (TIMER_BASE + 0x00001400U) -#define TIMER7 (TIMER_BASE + 0x00013400U) -#define TIMER8 (TIMER_BASE + 0x00014C00U) -#define TIMER9 (TIMER_BASE + 0x00015000U) -#define TIMER10 (TIMER_BASE + 0x00015400U) -#define TIMER11 (TIMER_BASE + 0x00001800U) -#define TIMER12 (TIMER_BASE + 0x00001C00U) -#define TIMER13 (TIMER_BASE + 0x00002000U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* constants definitions */ -/* TIMER init parameter struct definitions */ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint32_t period; /*!< period value */ - uint16_t clockdivision; /*!< clock division value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions*/ -typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint16_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint16_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ -#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ -#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ -#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ -#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ -#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ -#define TIMER_INT_FLAG_BRK TIMER_INT_BRK - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ - -/* channel enable state */ -#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ - -/* channel complementary output enable state */ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< frozen mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< set the channel output */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< clear the channel output */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle on match */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ - -/* timer input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ - -/* TIMERx(x=0..4,7..13) write CHxVAL register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ - -/* function declarations */ -/* TIMER timebase */ -/* deinit a TIMER */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct* initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a TIMER */ -void timer_enable(uint32_t timer_periph); -/* disable a TIMER */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint32_t update); - -/* timer DMA and event */ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); - -/* TIMER master and slave */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); - -/* TIMER interrupt and flag */ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flag */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flag */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -#endif /* GD32E10X_TIMER_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h deleted file mode 100644 index b0af23732f..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_usart.h +++ /dev/null @@ -1,378 +0,0 @@ -/*! - \file gd32f10x_usart.h - \brief definitions for the USART - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.1, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_USART_H -#define GD32F10X_USART_H - -#include "gd32f10x.h" - -/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ -#define USART1 USART_BASE /*!< USART1 base address */ -#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ -#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ -#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ -#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ - -/* registers definitions */ -#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ -#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ -#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ -#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ -#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ - -/* bits definitions */ -/* USARTx_STAT */ -#define USART_STAT_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT_TC BIT(6) /*!< transmission complete */ -#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ - -/* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ - -/* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* constants definitions */ -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) - -/* register offset */ -#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ -#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ - -/* USART flags */ -typedef enum -{ - /* flags in STAT register */ - USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ -}usart_interrupt_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ - -/* USART CK length */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART DMA request for receive configure */ -#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ - -/* USART DMA request for transmission configure */ -#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ - -/* USART RTS configure */ -#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ - -/* USART CTS configure */ -#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); - -/* USART normal mode communication */ -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* LIN mode enable */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* LIN mode disable */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); -/* send break frame */ -void usart_send_break(uint32_t usart_periph); - -/* half-duplex communication */ -/* half-duplex enable */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* half-duplex disable */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* clock enable */ -void usart_synchronous_clock_enable(uint32_t usart_periph); -/* clock disable */ -void usart_synchronous_clock_disable(uint32_t usart_periph); -/* configure usart synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* guard time value configure in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut); -/* smartcard mode enable */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* smartcard mode disable */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* NACK enable in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* NACK disable in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); - -/* flag functions */ -/* get flag in STAT register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT register */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); - -/* interrupt functions */ -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); -/* clear interrupt flag in STAT register */ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); -#endif /* GD32F10X_USART_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h deleted file mode 100644 index c548139baa..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Include/gd32f10x_wwdgt.h +++ /dev/null @@ -1,90 +0,0 @@ -/*! - \file gd32f10x_wwdgt.h - \brief definitions for the WWDGT - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_WWDGT_H -#define GD32F10X_WWDGT_H - -#include "gd32f10x.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE /*!< WWDGT base address */ - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32F10X_WWDGT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c deleted file mode 100644 index ab628288bf..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_adc.c +++ /dev/null @@ -1,933 +0,0 @@ -/*! - \file gd32f10x_adc.c - \brief ADC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_adc.h" - -/* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) - -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) - -/* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) - -/* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) - -/* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) - -/*! - \brief reset ADC - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_deinit(uint32_t adc_periph) -{ - switch(adc_periph){ - case ADC0: - /* reset ADC0 */ - rcu_periph_reset_enable(RCU_ADC0RST); - rcu_periph_reset_disable(RCU_ADC0RST); - break; - case ADC1: - /* reset ADC1 */ - rcu_periph_reset_enable(RCU_ADC1RST); - rcu_periph_reset_disable(RCU_ADC1RST); - break; -#ifndef GD32F10X_CL - case ADC2: - rcu_periph_reset_enable(RCU_ADC2RST); - rcu_periph_reset_disable(RCU_ADC2RST); - break; -#endif /* GD32F10X_CL */ - default: - break; - } -} - -/*! - \brief configure the ADC sync mode - \param[in] mode: ADC mode - only one parameter can be selected which is shown as below: - \arg ADC_MODE_FREE: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only - \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only - \param[out] none - \retval none -*/ -void adc_mode_config(uint32_t mode) -{ - ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); - ADC_CTL0(ADC0) |= mode; -} - -/*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] function: the function to config - only one parameter can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (function & ADC_SCAN_MODE)){ - /* enable scan mode */ - ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* enable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* enable continuous mode */ - ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ - /* disable scan mode */ - ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* disable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* disable continuous mode */ - ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment){ - /* MSB alignment */ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ - /* LSB alignment */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief enable ADC interface - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_enable(uint32_t adc_periph) -{ - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ - /* enable ADC */ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_disable(uint32_t adc_periph) -{ - /* disable ADC */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_calibration_enable(uint32_t adc_periph) -{ - /* reset the selected ADC1 calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ - } -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief enable DMA request - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - /* enable DMA request */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - /* disable DMA request */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel, the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) -{ - /* disable discontinuous mode of regular & inserted channel */ - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* config the number of conversions in discontinuous mode */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - /* enable regular channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ - default: - break; - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure the length of regular channel group */ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - case ADC_INSERTED_CHANNEL: - /* configure the length of inserted channel group */ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ - /* the regular group sequence rank is smaller than six */ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); - ADC_RSQ2(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ - /* the regular group sequence rank is smaller than twelve */ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); - ADC_RSQ1(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ - /* the regular group sequence rank is smaller than sixteen */ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); - ADC_RSQ0(adc_periph) = rsq; - }else{ - } - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the regular group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the regular group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - /* get inserted channel group length */ - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); - isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); - ADC_ISQ(adc_periph) = isq; - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the inserted group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the inserted group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] inserted_channel: insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset: the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - - if(num <= ADC_OFFSET_LENGTH){ - /* calculate the offset of the register */ - num = num * ADC_OFFSET_SHIFT_LENGTH; - /* config the offset of the selected channels */ - REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief configure ADC external trigger source - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected - for regular channel: - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select - \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 - \arg ADC2_EXTTRIG_REGULAR_T2_CH0: TIMER2 CH0 event select - \arg ADC2_EXTTRIG_REGULAR_T1_CH2: TIMER1 CH2 event select - \arg ADC2_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC2_EXTTRIG_REGULAR_T7_CH0: TIMER7 CH0 event select - \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: TIMER7 TRGO event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH0: TIMER4 CH0 event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH2: TIMER4 CH2 event select - \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select - \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select - \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC2_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC2_EXTTRIG_INSERTED_T3_CH2: TIMER3 CH2 event select - \arg ADC2_EXTTRIG_INSERTED_T7_CH1: TIMER7 CH1 event select - \arg ADC2_EXTTRIG_INSERTED_T7_CH3: TIMER7 CH3 event select - \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: TIMER4 TRGO event select - \arg ADC2_EXTTRIG_INSERTED_T4_CH3: TIMER4 CH3 event select - \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief configure ADC external trigger - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* enable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* enable ADC inserted channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; - } - }else{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief enable ADC software trigger - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* enable ADC regular channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* enable ADC inserted channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(uint32_t adc_periph) -{ - return (uint16_t)(ADC_RDATA(adc_periph)); -} - -/*! - \brief read ADC inserted group data register - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] inserted_channel: insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - /* read the data of channel 0 */ - idata = ADC_IDATA0(adc_periph); - break; - case ADC_INSERTED_CHANNEL_1: - /* read the data of channel 1 */ - idata = ADC_IDATA1(adc_periph); - break; - case ADC_INSERTED_CHANNEL_2: - /* read the data of channel 2 */ - idata = ADC_IDATA2(adc_periph); - break; - case ADC_INSERTED_CHANNEL_3: - /* read the data of channel 3 */ - idata = ADC_IDATA3(adc_periph); - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief read the last ADC0 and ADC1 conversion result data in sync mode - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint32_t adc_sync_mode_convert_value_read(void) -{ - /* return conversion value */ - return ADC_RDATA(ADC0); -} - - -/*! - \brief configure ADC analog watchdog single channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - /* analog watchdog channel select */ - ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - /* inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] adc_periph: ADCx, x=0,1,2 - \param[out] none - \retval none -*/ -void adc_watchdog_disable(uint32_t adc_periph) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] low_threshold: analog watchdog low threshold, 0..4095 - \param[in] high_threshold: analog watchdog high threshold, 0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) -{ - ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); -} - -/*! - \brief get the ADC flag bits - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) -{ - FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag bits - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_flag: the adc flag bits - one or more parameters can be selected which are shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); -} - -/*! - \brief get the bit state of ADCx software start conversion - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the bit state of ADCx software inserted channel start conversion - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the ADC interrupt bits - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc interrupt bits - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch(adc_interrupt){ - case ADC_INT_FLAG_WDE: - /* get the ADC analog watchdog interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear the ADC flag - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc status flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief enable ADC interrupt - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc interrupt - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* enable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - } - /* enable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - } - /* enable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] adc_periph: ADCx, x=0,1,2 - \param[in] adc_interrupt: the adc interrupt flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* disable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; - } - /* disable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; - } - /* disable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; - } -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c deleted file mode 100644 index 69e0c6a93b..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_bkp.c +++ /dev/null @@ -1,296 +0,0 @@ -/*! - \file gd32f10x_bkp.c - \brief BKP driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_bkp.h" - -/* BKP register bits offset */ -#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) - -/*! - \brief reset BKP registers - \param[in] none - \param[out] none - \retval none -*/ -void bkp_deinit(void) -{ - /* reset BKP domain register*/ - rcu_bkp_reset_enable(); - rcu_bkp_reset_disable(); -} - -/*! - \brief write BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[in] data: the data to be write in BKP data register - \param[out] none - \retval none -*/ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) -{ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - BKP_DATA10_41(register_number - 1U) = data; - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - BKP_DATA0_9(register_number - 1U) = data; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief read BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[out] none - \retval data of BKP data register -*/ -uint16_t bkp_data_read(bkp_data_register_enum register_number) -{ - uint16_t data = 0U; - - /* get the data from the BKP data register */ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - data = BKP_DATA10_41(register_number - 1U); - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - data = BKP_DATA0_9(register_number - 1U); - }else{ - /* illegal parameters */ - } - return data; -} - -/*! - \brief enable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; -} - -/*! - \brief disable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; -} - -/*! - \brief enable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; -} - -/*! - \brief disable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; -} - -/*! - \brief select RTC output - \param[in] outputsel: RTC output selection - only one parameter can be selected which is shown as below: - \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output - \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output - \param[out] none - \retval none -*/ -void bkp_rtc_output_select(uint16_t outputsel) -{ - uint16_t ctl = 0U; - - /* configure BKP_OCTL_ROSEL with outputsel */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_ROSEL; - ctl |= outputsel; - BKP_OCTL = ctl; -} - -/*! - \brief set RTC clock calibration value - \param[in] value: RTC clock calibration value - \arg 0x00 - 0x7F - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_value_set(uint8_t value) -{ - uint16_t ctl; - - /* configure BKP_OCTL_RCCV with value */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_RCCV; - ctl |= (uint16_t)OCTL_RCCV(value); - BKP_OCTL = ctl; -} - -/*! - \brief enable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_enable(void) -{ - BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; -} - -/*! - \brief disable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_disable(void) -{ - BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; -} - -/*! - \brief set tamper pin active level - \param[in] level: tamper active level - only one parameter can be selected which is shown as below: - \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high - \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low - \param[out] none - \retval none -*/ -void bkp_tamper_active_level_set(uint16_t level) -{ - uint16_t ctl = 0U; - - /* configure BKP_TPCTL_TPAL with level */ - ctl = BKP_TPCTL; - ctl &= (uint16_t)~BKP_TPCTL_TPAL; - ctl |= level; - BKP_TPCTL = ctl; -} - -/*! - \brief enable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_enable(void) -{ - BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; -} - -/*! - \brief disable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_disable(void) -{ - BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; -} - -/*! - \brief get tamper flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_flag_get(void) -{ - if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear tamper flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} - -/*! - \brief get tamper interrupt flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_interrupt_flag_get(void) -{ - if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear tamper interrupt flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c deleted file mode 100644 index 95ca2dd050..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_can.c +++ /dev/null @@ -1,993 +0,0 @@ -/*! - \file gd32f10x_can.c - \brief CAN driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_can.h" - -#define CAN_ERROR_HANDLE(s) do{}while(1) - -/*! - \brief deinitialize CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_deinit(uint32_t can_periph) -{ -#ifdef GD32F10x_CL - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - }else{ - rcu_periph_reset_enable(RCU_CAN1RST); - rcu_periph_reset_disable(RCU_CAN1RST); - } -#else - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - } -#endif -} - -/*! - \brief initialize CAN parameter struct with a default value - \param[in] type: the type of CAN parameter struct - only one parameter can be selected which is shown as below: - \arg CAN_INIT_STRUCT: the CAN initial struct - \arg CAN_FILTER_STRUCT: the CAN filter struct - \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct - \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct - \param[in] p_struct: the pointer of the specific struct - \param[out] none - \retval none -*/ -void can_struct_para_init(can_struct_type_enum type, void* p_struct) -{ - uint8_t i; - - /* get type of the struct */ - switch(type){ - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE; - ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; - - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; - - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; - } - - ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; - - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; - } - - ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct*)p_struct)->rx_efid = 0U; - ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct*)p_struct)->rx_fi = 0U; - ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; - - break; - - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); - } -} - -/*! - \brief initialize CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] can_parameter_init: parameters for CAN initializtion - \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) - \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) - \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) - \arg time_triggered: ENABLE or DISABLE - \arg auto_bus_off_recovery: ENABLE or DISABLE - \arg auto_wake_up: ENABLE or DISABLE - \arg auto_retrans: ENABLE or DISABLE - \arg rec_fifo_overwrite: ENABLE or DISABLE - \arg trans_fifo_order: ENABLE or DISABLE - \arg prescaler: 0x0000 - 0x03FF - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) -{ - uint32_t timeout = CAN_TIMEOUT; - ErrStatus flag = ERROR; - - /* disable sleep mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - /* enable initialize mode */ - CAN_CTL(can_periph) |= CAN_CTL_IWMOD; - /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - /* set the bit timing register */ - CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ - BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ - BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ - BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ - BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); - - /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ - CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; - } - /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ - CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_AWU; - } - /* automatic retransmission mode disable*/ - if(ENABLE == can_parameter_init->auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ARD; - } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } - /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ - CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } - /* disable initialize mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; - timeout = CAN_TIMEOUT; - /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check exit initialize mode */ - if(0U != timeout){ - flag = SUCCESS; - } - } - return flag; -} - -/*! - \brief initialize CAN filter - \param[in] can_filter_parameter_init: struct for CAN filter initialization - \arg filter_list_high: 0x0000 - 0xFFFF - \arg filter_list_low: 0x0000 - 0xFFFF - \arg filter_mask_high: 0x0000 - 0xFFFF - \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - \arg filter_number: 0 - 27 - \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - \arg filter_enable: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) -{ - uint32_t val = 0U; - - val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* disable filter */ - CAN_FW(CAN0) &= ~(uint32_t)val; - - /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ - /* set filter 16 bits */ - CAN_FSCFG(CAN0) &= ~(uint32_t)val; - /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); - } - /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ - /* set filter 32 bits */ - CAN_FSCFG(CAN0) |= (uint32_t)val; - /* 32 bits list or first 32 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* 32 bits mask or second 32 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); - } - - /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ - /* mask mode */ - CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ - /* list mode */ - CAN_FMCFG(CAN0) |= (uint32_t)val; - } - - /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ - /* FIFO0 */ - CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - }else{ - /* FIFO1 */ - CAN_FAFIFO(CAN0) |= (uint32_t)val; - } - - /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ - - CAN_FW(CAN0) |= (uint32_t)val; - } - - /* filter lock enable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief set CAN1 fliter start bank number - \param[in] start_bank: CAN1 start bank number - only one parameter can be selected which is shown as below: - \arg (1..27) - \param[out] none - \retval none -*/ -void can1_filter_start_bank(uint8_t start_bank) -{ - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* set CAN1 filter start number */ - CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; - CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief enable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_debug_freeze_enable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) |= CAN_CTL_DFZ; -#ifdef GD32F10x_CL - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - }else{ - dbg_periph_enable(DBG_CAN1_HOLD); - } -#else - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - } -#endif -} - -/*! - \brief disable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_debug_freeze_disable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; -#ifdef GD32F10x_CL - if(CAN0 == can_periph){ - dbg_periph_disable(DBG_CAN0_HOLD); - }else{ - dbg_periph_disable(DBG_CAN1_HOLD); - } -#else - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - } -#endif -} - -/*! - \brief enable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_time_trigger_mode_enable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* enable the tcc mode */ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - /* enable time stamp */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; - } -} - -/*! - \brief disable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval none -*/ -void can_time_trigger_mode_disable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* disable the TCC mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - /* reset TSEN bits */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; - } -} - -/*! - \brief transmit CAN message - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] transmit_message: struct for CAN transmit message - \arg tx_sfid: 0x00000000 - 0x000007FF - \arg tx_efid: 0x00000000 - 0x1FFFFFFF - \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg tx_dlenc: 1 - 7 - \arg tx_data[]: 0x00 - 0xFF - \param[out] none - \retval mailbox_number -*/ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) -{ - uint8_t mailbox_number = CAN_MAILBOX0; - - /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ - mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ - mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ - mailbox_number = CAN_MAILBOX2; - }else{ - mailbox_number = CAN_NOMAILBOX; - } - /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number){ - return CAN_NOMAILBOX; - } - - CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ - /* set transmit mailbox standard identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ - /* set transmit mailbox extended identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); - } - /* set the data length */ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; - CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; - /* set the data */ - CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); - CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); - /* enable transmission */ - CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; - - return mailbox_number; -} - -/*! - \brief get CAN transmit state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOX(x=0,1,2) - \param[out] none - \retval can_transmit_state_enum -*/ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) -{ - can_transmit_state_enum state = CAN_TRANSMIT_FAILED; - uint32_t val = 0U; - - /* check selected mailbox state */ - switch(mailbox_number){ - /* mailbox0 */ - case CAN_MAILBOX0: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); - break; - /* mailbox1 */ - case CAN_MAILBOX1: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); - break; - /* mailbox2 */ - case CAN_MAILBOX2: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); - break; - default: - val = CAN_TRANSMIT_FAILED; - break; - } - - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): - state = CAN_TRANSMIT_PENDING; - break; - /* mailbox0 transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_OK; - break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_OK; - break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_OK; - break; - /* transmit failed */ - default: - state = CAN_TRANSMIT_FAILED; - break; - } - return state; -} - -/*! - \brief stop CAN transmission - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOXx(x=0,1,2) - \param[out] none - \retval none -*/ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) -{ - if(CAN_MAILBOX0 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ - } - }else if(CAN_MAILBOX1 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ - } - }else if(CAN_MAILBOX2 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ - } - }else{ - /* illegal parameters */ - } -} - -/*! - \brief CAN receive message - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] receive_message: struct for CAN receive message - \arg rx_sfid: 0x00000000 - 0x000007FF - \arg rx_efid: 0x00000000 - 0x1FFFFFFF - \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg rx_dlenc: 1 - 7 - \arg rx_data[]: 0x00 - 0xFF - \arg rx_fi: 0 - 27 - \retval none -*/ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) -{ - /* get the frame format */ - receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ - /* get standard identifier */ - receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ - /* get extended identifier */ - receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); - } - - /* get frame type */ - receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* filtering index */ - receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - /* get recevie data length */ - receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - - /* receive data */ - receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - - /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - } -} - -/*! - \brief release FIFO0 - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval none -*/ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) -{ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ - /* illegal parameters */ - CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); - } -} - -/*! - \brief CAN receive message length - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval message length -*/ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) -{ - uint8_t val = 0U; - - if(CAN_FIFO0 == fifo_number){ - /* FIFO0 */ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ - /* FIFO1 */ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ - /* illegal parameters */ - } - return val; -} - -/*! - \brief set CAN working mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] can_working_mode - only one parameter can be selected which is shown as below: - \arg CAN_MODE_INITIALIZE - \arg CAN_MODE_NORMAL - \arg CAN_MODE_SLEEP - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) -{ - ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if(CAN_MODE_INITIALIZE == working_mode){ - /* disable sleep mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); - /* set initialize mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_NORMAL == working_mode){ - /* enter normal mode */ - CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ - timeout--; - } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_SLEEP == working_mode){ - /* disable initialize mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); - /* set sleep mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; - /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else{ - flag = ERROR; - } - return flag; -} - -/*! - \brief wake up CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_wakeup(uint32_t can_periph) -{ - ErrStatus flag = ERROR; - uint32_t timeout = CAN_TIMEOUT; - - /* wakeup */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ - timeout--; - } - /* check state */ - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - return flag; -} - -/*! - \brief get CAN error type - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval can_error_enum - \arg CAN_ERROR_NONE: no error - \arg CAN_ERROR_FILL: fill error - \arg CAN_ERROR_FORMATE: format error - \arg CAN_ERROR_ACK: ACK error - \arg CAN_ERROR_BITRECESSIVE: bit recessive - \arg CAN_ERROR_BITDOMINANTER: bit dominant error - \arg CAN_ERROR_CRC: CRC error - \arg CAN_ERROR_SOFTWARECFG: software configure -*/ -can_error_enum can_error_get(uint32_t can_periph) -{ - can_error_enum error; - error = CAN_ERROR_NONE; - - /* get error type */ - error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); - return error; -} - -/*! - \brief get CAN receive error number - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval error number -*/ -uint8_t can_receive_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - /* get error count */ - val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief get CAN transmit error number - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[out] none - \retval error number -*/ -uint8_t can_transmit_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - -/*! - \brief get CAN flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ - /* get flag and interrupt enable state */ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \param[out] none - \retval none -*/ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag) -{ - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); -} - -/*! - \brief get CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F10x_CL - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval none -*/ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c deleted file mode 100644 index 0173e9f507..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_crc.c +++ /dev/null @@ -1,131 +0,0 @@ -/*! - \file gd32f10x_crc.c - \brief CRC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_crc.h" - -#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) -#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_DATA = CRC_DATA_RESET_VALUE; - CRC_FDATA = CRC_FDATA_RESET_VALUE; - CRC_CTL = (uint32_t)CRC_CTL_RST; -} - -/*! - \brief reset data register to the value of initializaiton data register - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the value of the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the value of the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write data to the free data register - \param[in] free_data: specify 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief calculate the CRC value of a 32-bit data - \param[in] sdata: specified 32-bit data - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return (CRC_DATA); -} - -/*! - \brief calculate the CRC value of an array of 32-bit values - \param[in] array: pointer to an array of 32-bit values - \param[in] size: size of the array - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for(index = 0U; index < size; index++){ - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c deleted file mode 100644 index b5114a2739..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dac.c +++ /dev/null @@ -1,559 +0,0 @@ -/*! - \file gd32f10x_dac.c - \brief DAC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_dac.h" - -/* DAC register bit offset */ -#define DAC1_REG_OFFSET ((uint32_t)16U) -#define DH_12BIT_OFFSET ((uint32_t)16U) -#define DH_8BIT_OFFSET ((uint32_t)8U) - -/*! - \brief deinitialize DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_deinit(void) -{ - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); -} - -/*! - \brief enable DAC - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DEN0; - }else{ - DAC_CTL |= DAC_CTL_DEN1; - } -} - -/*! - \brief disable DAC - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DEN1; - } -} - -/*! - \brief enable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ - DAC_CTL |= DAC_CTL_DDMAEN1; - } -} - -/*! - \brief disable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DDMAEN1; - } -} - -/*! - \brief enable DAC output buffer - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ - DAC_CTL &= ~DAC_CTL_DBOFF1; - } -} - -/*! - \brief disable DAC output buffer - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DBOFF0; - }else{ - DAC_CTL |= DAC_CTL_DBOFF1; - } -} - -/*! - \brief get DAC output value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if(DAC0 == dac_periph){ - /* store the DAC0 output value */ - data = (uint16_t)DAC0_DO; - }else{ - /* store the DAC1 output value */ - data = (uint16_t)DAC1_DO; - } - return data; -} - -/*! - \brief set the DAC specified data holding register value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] dac_align - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data: data to be loaded - \param[out] none - \retval none -*/ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) -{ - if(DAC0 == dac_periph){ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } - }else{ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } - } -} - -/*! - \brief enable DAC trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DTEN0; - }else{ - DAC_CTL |= DAC_CTL_DTEN1; - } -} - -/*! - \brief disable DAC trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DTEN1; - } -} - -/*! - \brief set DAC trigger source - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] triggersource: external triggers of DAC - only one parameter can be selected which is shown as below: - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F10X_CL) - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO - \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO - \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F10X_MD and GD32F10X_HD and GD32F10X_XD) - \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger - \param[out] none - \retval none -*/ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; - }else{ - /* configure DAC1 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC software trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \retval none -*/ -void dac_software_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; - }else{ - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; - } -} - -/*! - \brief configure DAC wave mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] wave_mode - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_DISABLE: wave disable - \arg DAC_WAVE_MODE_LFSR: LFSR noise mode - \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode - \param[out] none - \retval none -*/ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM0; - DAC_CTL |= wave_mode; - }else{ - /* configure DAC1 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC wave bit width - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] bit_width - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= bit_width; - }else{ - /* configure DAC1 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (bit_width << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC LFSR noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] unmask_bits - only one parameter can be selected which is shown as below: - \arg DAC_LFSR_BIT0: unmask the LFSR bit0 - \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] - \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] - \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] - \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] - \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] - \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] - \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] - \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] - \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] - \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] - \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] - \param[out] none - \retval none -*/ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= unmask_bits; - }else{ - /* configure DAC1 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC triangle noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] amplitude - only one parameter can be selected which is shown as below: - \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 - \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 - \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 - \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 - \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 - \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 - \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 - \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 - \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 - \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 - \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 - \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 - \param[out] none - \retval none -*/ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= amplitude; - }else{ - /* configure DAC1 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (amplitude << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL |= (ctl); -} - -/*! - \brief disable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL &= (~ctl); -} - -/*! - \brief enable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_enable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); -} - -/*! - \brief disable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_disable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT &= (~swt); -} - -/*! - \brief enable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL &= (~ctl); -} - -/*! - \brief disable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL |= (ctl); -} - -/*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded - \param[out] none - \retval none -*/ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) -{ - uint32_t data = 0U; - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; - DACC_R8DH = data; - break; - default: - break; - } -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c deleted file mode 100644 index f8b74c727f..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dbg.c +++ /dev/null @@ -1,153 +0,0 @@ -/*! - \file gd32f10x_dbg.c - \brief DBG driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_dbg.h" - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_CTL |= (uint32_t)dbg_periph; -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD and CL series): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_CTL &= ~(uint32_t)dbg_periph; -} - -/*! - \brief enable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_enable(void) -{ - DBG_CTL |= DBG_CTL_TRACE_IOEN; -} - -/*! - \brief disable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_disable(void) -{ - DBG_CTL &= ~DBG_CTL_TRACE_IOEN; -} - -/*! - \brief trace pin mode selection - \param[in] trace_mode: - only one parameter can be selected which is shown as below: - \arg TRACE_MODE_ASYNC: trace pin used for async mode - \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 - \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 - \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 - \param[out] none - \retval none -*/ -void dbg_trace_pin_mode_set(uint32_t trace_mode) -{ - DBG_CTL &= ~DBG_CTL_TRACE_MODE; - DBG_CTL |= trace_mode; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c deleted file mode 100644 index 801d69130d..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_dma.c +++ /dev/null @@ -1,737 +0,0 @@ -/*! - \file gd32f10x_dma.c - \brief DMA driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_dma.h" - -#define DMA_WRONG_HANDLE while(1){} - - /* check whether peripheral matches channels or not */ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); - -/*! - \brief deinitialize DMA a channel registers - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is deinitialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* disable DMA a channel */ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_struct_para_init(dma_parameter_struct* init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; - init_struct->number = 0U; - init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; - init_struct->priority = DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is initialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* configure peripheral base address */ - DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width, */ - ctl = DMA_CHCTL(dma_periph, channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); - DMA_CHCTL(dma_periph, channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - }else{ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set peripheral base address - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHPADDR(dma_periph, channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set memory base address - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHMADDR(dma_periph, channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] number: the number of remaining data to be transferred by the DMA - \arg 0x0000-0xFFFF - \param[out] none - \retval none -*/ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - return (uint32_t)DMA_CHCNT(dma_periph, channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] priority: priority Level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] mwidth: transfer data width of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] pwidth: transfer data width of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - if(DMA_PERIPHERAL_TO_MEMORY == direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - /* check whether the flag is set or not */ - if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ - reval = SET; - }else{ - reval = RESET; - } - - return reval; -} - -/*! - \brief clear the flag of a DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch(flag){ - case DMA_INT_FLAG_FTF: - /* check whether the full transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - /* check whether the half transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - /* check whether the error interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; - break; - default: - DMA_WRONG_HANDLE - } - - /* when the interrupt flag is set and enabled, return SET */ - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~source; -} - -/*! - \brief check whether peripheral and channels match - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) -{ - ErrStatus val = SUCCESS; - - if(DMA1 == dma_periph){ - /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ - if(channelx > DMA_CH4){ - val = ERROR; - } - } - - return val; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c deleted file mode 100644 index e614de1670..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_enet.c +++ /dev/null @@ -1,3074 +0,0 @@ -/*! - \file gd32f10x_enet.c - \brief ENET driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_enet.h" - -#ifdef GD32F10X_CL - -#if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#elif defined ( __ICCARM__ ) /*!< IAR compiler */ -#pragma data_alignment=4 -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -#pragma data_alignment=4 -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -#pragma data_alignment=4 -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -#pragma data_alignment=4 -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#endif /* __CC_ARM */ - -/* global transmit and receive descriptors pointers */ -enet_descriptors_struct *dma_current_txdesc; -enet_descriptors_struct *dma_current_rxdesc; - -/* structure pointer of ptp descriptor for normal mode */ -enet_descriptors_struct *dma_current_ptp_txdesc = NULL; -enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; - -/* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; - -static uint32_t enet_unknow_err = 0U; - -/* array of register offset for debug information get */ -static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x1080, 0x001C, 0x0028, 0x002C, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, - -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1048, 0x104C, -0x1050, 0x1054}; - - -/*! - \brief deinitialize the ENET, and reset structure parameters for ENET initialization - \param[in] none - \param[out] none - \retval none -*/ -void enet_deinit(void) -{ - rcu_periph_reset_enable(RCU_ENETRST); - rcu_periph_reset_disable(RCU_ENETRST); - enet_initpara_reset(); -} - -/*! - \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise - configuration will be no effect - \param[in] option: different function option, which is related to several parameters, - only one parameter can be selected which is shown as below, refer to enet_option_enum - \arg FORWARD_OPTION: choose to configure the frame forward related parameters - \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters - \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters - \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters - \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters - \arg VLAN_OPTION: choose to configure vlan related parameters - \arg FLOWCTL_OPTION: choose to configure flow control related parameters - \arg HASHH_OPTION: choose to configure hash high - \arg HASHL_OPTION: choose to configure hash low - \arg FILTER_OPTION: choose to configure frame filter related parameters - \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters - \arg TIMER_OPTION: choose to configure time counter related parameters - \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option - all the related parameters should be configured which are shown as below - FORWARD_OPTION related parameters: - - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; - - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; - - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . - DMABUS_OPTION related parameters: - - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; - - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; - DMA_MAXBURST_OPTION related parameters: - - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ - ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ - ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ - ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ - ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; - - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ - ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ - ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ - ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ - ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; - - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; - DMA_ARBITRATION_OPTION related parameters: - - ENET_ARBITRATION_RXPRIORTX / ENET_ARBITRATION_RXTX_1_1 - / ENET_ARBITRATION_RXTX_2_1/ ENET_ARBITRATION_RXTX_3_1 - / ENET_ARBITRATION_RXTX_4_1. - STORE_OPTION related parameters: - - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; - - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; - - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ - ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; - - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ - ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ - ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ - ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . - DMA_OPTION related parameters: - - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; - - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE . - VLAN_OPTION related parameters: - - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; - - MAC_VLT_VLTI(regval) . - FLOWCTL_OPTION related parameters: - - MAC_FCTL_PTM(regval) ; - - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ - ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; - - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . - HASHH_OPTION related parameters: - - 0x0~0xFFFF FFFFU - HASHL_OPTION related parameters: - - 0x0~0xFFFF FFFFU - FILTER_OPTION related parameters: - - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ - ENET_SRC_FILTER_DISABLE ; - - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; - - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ - ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; - - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ - ENET_UNICAST_FILTER_PERFECT ; - - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ - ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . - HALFDUPLEX_OPTION related parameters: - - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; - - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; - - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; - - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ - ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; - - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . - TIMER_OPTION related parameters: - - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; - - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; - INTERFRAMEGAP_OPTION related parameters: - - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ - ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ - ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ - ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . - \param[out] none - \retval none -*/ -void enet_initpara_config(enet_option_enum option, uint32_t para) -{ - switch(option){ - case FORWARD_OPTION: - /* choose to configure forward_frame, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; - enet_initpara.forward_frame = para; - break; - case DMABUS_OPTION: - /* choose to configure dmabus_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; - enet_initpara.dmabus_mode = para; - break; - case DMA_MAXBURST_OPTION: - /* choose to configure dma_maxburst, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; - enet_initpara.dma_maxburst = para; - break; - case DMA_ARBITRATION_OPTION: - /* choose to configure dma_arbitration, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; - enet_initpara.dma_arbitration = para; - break; - case STORE_OPTION: - /* choose to configure store_forward_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)STORE_OPTION; - enet_initpara.store_forward_mode = para; - break; - case DMA_OPTION: - /* choose to configure dma_function, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - enet_initpara.dma_function = para; - break; - case VLAN_OPTION: - /* choose to configure vlan_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; - enet_initpara.vlan_config = para; - break; - case FLOWCTL_OPTION: - /* choose to configure flow_control, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; - enet_initpara.flow_control = para; - break; - case HASHH_OPTION: - /* choose to configure hashtable_high, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; - enet_initpara.hashtable_high = para; - break; - case HASHL_OPTION: - /* choose to configure hashtable_low, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; - enet_initpara.hashtable_low = para; - break; - case FILTER_OPTION: - /* choose to configure framesfilter_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; - enet_initpara.framesfilter_mode = para; - break; - case HALFDUPLEX_OPTION: - /* choose to configure halfduplex_param, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; - enet_initpara.halfduplex_param = para; - break; - case TIMER_OPTION: - /* choose to configure timer_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; - break; - case INTERFRAMEGAP_OPTION: - /* choose to configure interframegap, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; - enet_initpara.interframegap = para; - break; - default: - break; - } -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared - parameters - \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum - \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation - \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex - \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex - \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex - \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex - \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII - \param[in] checksum: IP frame checksum offload function, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum - \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function - \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function - \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped - \param[in] recept: frame filter function, only one parameter can be selected - which is shown as below, refer to enet_frmrecept_enum - \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled - \arg ENET_RECEIVEALL: all received frame are forwarded to application - \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames - \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) -{ - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; - uint32_t media_temp = 0U; - uint32_t timeout = 0U; - uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; - - /* PHY interface configuration, configure SMI clock and reset PHY chip */ - if(ERROR == enet_phy_config()){ - _ENET_DELAY_(PHY_RESETDELAY); - if(ERROR == enet_phy_config()){ - return enet_state; - } - } - /* initialize ENET peripheral with generally concerned parameters */ - enet_default_init(); - - /* 1st, configure mediamode */ - media_temp = (uint32_t)mediamode; - /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ - /* wait for PHY_LINKED_STATUS bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; - timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* enable auto-negotiation */ - phy_value = PHY_AUTONEGOTIATION; - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - - /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_AUTONEGO_COMPLETE; - timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); - /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ - media_temp = ENET_MODE_FULLDUPLEX; - }else{ - media_temp = ENET_MODE_HALFDUPLEX; - } - /* configure the communication speed of MAC following the auto-negotiation result */ - if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ - media_temp |= ENET_SPEEDMODE_10M; - }else{ - media_temp |= ENET_SPEEDMODE_100M; - } - }else{ - phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); - phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - /* PHY configuration need some time */ - _ENET_DELAY_(PHY_CONFIGDELAY); - } - /* after configuring the PHY, use mediamode to configure registers */ - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); - reg_value |= media_temp; - ENET_MAC_CFG = reg_value; - - - /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ - ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~ENET_DMA_CTL_DTCERFD; - reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); - ENET_DMA_CTL = reg_value; - } - - /* 3rd, configure recept */ - ENET_MAC_FRMF |= (uint32_t)recept; - - /* 4th, configure different function options */ - /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ - reg_temp = enet_initpara.forward_frame; - - reg_value = ENET_MAC_CFG; - temp = reg_temp; - /* configure ENET_MAC_CFG register */ - reg_value &= (~ENET_MAC_CFG_APCD); - temp &= ENET_MAC_CFG_APCD; - reg_value |= temp; - ENET_MAC_CFG = reg_value; - - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); - temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); - reg_value |= (temp >> 2); - ENET_DMA_CTL = reg_value; - } - - /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ - temp = enet_initpara.dmabus_mode; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ - temp = enet_initpara.dma_maxburst; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ - temp = enet_initpara.dma_arbitration; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ - temp = enet_initpara.store_forward_mode; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - } - - /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ - reg_temp = enet_initpara.dma_function; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); - reg_value |= reg_temp; - ENET_DMA_CTL = reg_value; - } - - /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ - reg_temp = enet_initpara.vlan_config; - - reg_value = ENET_MAC_VLT; - /* configure ENET_MAC_VLT register */ - reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); - reg_value |= reg_temp; - ENET_MAC_VLT = reg_value; - } - - /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ - reg_temp = enet_initpara.flow_control; - - reg_value = ENET_MAC_FCTL; - temp = reg_temp; - /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - reg_value |= temp; - ENET_MAC_FCTL = reg_value; - - reg_value = ENET_MAC_FCTH; - temp = reg_temp; - /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); - reg_value |= (temp >> 8); - ENET_MAC_FCTH = reg_value; - } - - /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ - ENET_MAC_HLH = enet_initpara.hashtable_high; - } - - /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ - ENET_MAC_HLL = enet_initpara.hashtable_low; - } - - /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ - reg_temp = enet_initpara.framesfilter_mode; - - reg_value = ENET_MAC_FRMF; - /* configure ENET_MAC_FRMF register */ - reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); - reg_value |= reg_temp; - ENET_MAC_FRMF = reg_value; - } - - /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ - reg_temp = enet_initpara.halfduplex_param; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ - reg_temp = enet_initpara.timer_config; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ - reg_temp = enet_initpara.interframegap; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~ENET_MAC_CFG_IGBS; - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - enet_state = SUCCESS; - return enet_state; -} - -/*! - \brief reset all core internal registers located in CLK_TX and CLK_RX - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_software_reset(void) -{ - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - uint32_t dma_flag; - - /* reset all core internal registers located in CLK_TX and CLK_RX */ - ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - - /* wait for reset operation complete */ - do{ - dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); - timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - - /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief check receive frame valid and return frame size - \param[in] none - \param[out] none - \retval size of received frame: 0x0 - 0x3FFF -*/ -uint32_t enet_rxframe_size_get(void) -{ - uint32_t size = 0U; - uint32_t status; - - /* get rdes0 information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - - /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ - return 0U; - } - - /* if has any error, or the frame uses two or more descriptors */ - if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; - } - - /* if is an ethernet-type frame, and IP frame payload error occurred */ - if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; - } - - /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ - if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ - /* get the size of the received data including CRC */ - size = GET_RDES0_FRML(status); - /* substract the CRC size */ - size = size - 4U; - }else{ - enet_unknow_err++; - enet_rxframe_drop(); - - return 1U; - } - - /* return packet size */ - return size; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_chain_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode */ - desc_status = ENET_TDES0_TCHM; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; - } - } -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_ring_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc; - enet_descriptors_struct *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* set buffer1 size */ - desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - } -} - -/*! - \brief handle current received frame data to application buffer - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] buffer: pointer to the received frame data - note -- if the input is NULL, user should copy data in application by himself - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status); - size = size - 4U; - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); - } - - }else{ - /* return ERROR */ - return ERROR; - } - } - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief handle application buffer data to transmit it - \param[in] buffer: pointer to the frame data to be transmitted, - note -- if the input is NULL, user should handle the data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) -{ - uint32_t offset = 0U; - uint32_t dma_tbu_flag, dma_tu_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief configure the transmit IP frame checksum offload calculation and insertion - \param[in] desc: the descriptor pointer which users want to configure - \param[in] checksum: IP frame checksum configuration - only one parameter can be selected which is shown as below - \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled - \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled - \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header - \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated - \param[out] none - \retval none -*/ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) -{ - desc->status &= ~ENET_TDES0_CM; - desc->status |= checksum; -} - -/*! - \brief ENET Tx and Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_enable(void) -{ - enet_tx_enable(); - enet_rx_enable(); -} - -/*! - \brief ENET Tx and Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_disable(void) -{ - enet_tx_disable(); - enet_rx_disable(); -} - -/*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: set MAC address 0 filter - \arg ENET_MAC_ADDRESS1: set MAC address 1 filter - \arg ENET_MAC_ADDRESS2: set MAC address 2 filter - \arg ENET_MAC_ADDRESS3: set MAC address 3 filter - \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \param[out] none - \retval none -*/ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); - REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); -} - -/*! - \brief get MAC address - \param[in] mac_addr: select which MAC address will be get, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: get MAC address 0 filter - \arg ENET_MAC_ADDRESS1: get MAC address 1 filter - \arg ENET_MAC_ADDRESS2: get MAC address 2 filter - \arg ENET_MAC_ADDRESS3: get MAC address 3 filter - \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \retval none -*/ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); - paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); - paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); - paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); - paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); - paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); -} - -/*! - \brief get the ENET MAC/MSC/PTP/DMA status flag - \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, - only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag - \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag - \arg ENET_MAC_FLAG_WUM: WUM status flag - \arg ENET_MAC_FLAG_MSC: MSC status flag - \arg ENET_MAC_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag - \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag - \arg ENET_PTP_FLAG_TTM: target time match flag - \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_FLAG_TS: transmit status flag - \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_FLAG_RO: receive overflow status flag - \arg ENET_DMA_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_FLAG_RS: receive status flag - \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_FLAG_ET: early transmit status flag - \arg ENET_DMA_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_FLAG_ER: early receive status flag - \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag - \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag - \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag - \arg ENET_DMA_FLAG_MSC: MSC status flag - \arg ENET_DMA_FLAG_WUM: WUM status flag - \arg ENET_DMA_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_flag_get(enet_flag_enum enet_flag) -{ - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the ENET DMA status flag - \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear - \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear - \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear - \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear - \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear - \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear - \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear - \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear - \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear - \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear - \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear - \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear - \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear - \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear - \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear - \param[out] none - \retval none -*/ -void enet_flag_clear(enet_flag_clear_enum enet_flag) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); -} - -/*! - \brief enable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_enable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief disable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_disable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief get ENET MAC/MSC/DMA interrupt flag - \param[in] int_flag: ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_FLAG_WUM: WUM status flag - \arg ENET_MAC_INT_FLAG_MSC: MSC status flag - \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag - \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_INT_FLAG_TS: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS: receive status flag - \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER: early receive status flag - \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_INT_FLAG_MSC: MSC status flag - \arg ENET_DMA_INT_FLAG_WUM: WUM status flag - \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) -{ - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear ENET DMA interrupt flag - \param[in] int_flag_clear: clear ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag - \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag - \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag - \param[out] none - \retval none -*/ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); -} - -/*! - \brief ENET Tx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_TEN; - enet_txfifo_flush(); - ENET_DMA_CTL |= ENET_DMA_CTL_STE; -} - -/*! - \brief ENET Tx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; - enet_txfifo_flush(); - ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; -} - -/*! - \brief ENET Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_REN; - ENET_DMA_CTL |= ENET_DMA_CTL_SRE; -} - -/*! - \brief ENET Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; - ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; -} - -/*! - \brief put registers value into the application buffer - \param[in] type: register type which will be get, refer to enet_registers_type_enum, - only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH - \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT - \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL - \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR - \param[in] num: the number of registers that the user want to get - \param[out] preg: the application buffer pointer for storing the register value - \retval none -*/ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) -{ - uint32_t offset = 0U, max = 0U, limit = 0U; - - offset = (uint32_t)type; - max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - - /* prevent element in this array is out of range */ - if(max > limit){ - max = limit; - } - - for(; offset < max; offset++){ - /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); - preg++; - } -} - -/*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable - \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_enable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief disable the MAC address filter - \param[in] mac_addr: select which MAC address will be disable, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_disable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief configure the MAC address filter - \param[in] mac_addr: select which MAC address will be configured, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter - \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter - \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter - \param[in] addr_mask: select which MAC address bytes will be mask, - one or more parameters can be selected which are shown as below - \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits - \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits - \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits - \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits - \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits - \param[in] filter_type: select which MAC address filter type will be selected, - only one parameter can be selected which is shown as below - \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame - \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame - \param[out] none - \retval none -*/ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) -{ - uint32_t reg; - - /* get the address filter register value which is to be configured */ - reg = REG32(ENET_ADDRH_BASE + mac_addr); - - /* clear and configure the address filter register */ - reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); - reg |= (addr_mask | filter_type); - REG32(ENET_ADDRH_BASE + mac_addr) = reg; -} - -/*! - \brief PHY interface configuration (configure SMI clock and reset PHY chip) - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_config(void) -{ - uint32_t ahbclk; - uint32_t reg; - uint16_t phy_value; - ErrStatus enet_state = ERROR; - - /* clear the previous MDC clock */ - reg = ENET_MAC_PHY_CTL; - reg &= ~ENET_MAC_PHY_CTL_CLR; - - /* get the HCLK frequency */ - ahbclk = rcu_clock_freq_get(CK_AHB); - - /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ - reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ - reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 90000000U)){ - reg |= ENET_MDC_HCLK_DIV42; - }else if((ENET_RANGE(ahbclk, 90000000U, 108000000U))||(108000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV62; - }else{ - return enet_state; - } - ENET_MAC_PHY_CTL = reg; - - /* reset PHY */ - phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - /* PHY reset need some time */ - _ENET_DELAY_(ENET_DELAY_TO); - - /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - - /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief write to / read from a PHY register - \param[in] direction: only one parameter can be selected which is shown as below - \arg ENET_PHY_WRITE: write data to phy register - \arg ENET_PHY_READ: read data from phy register - \param[in] phy_address: 0x0 - 0x1F - \param[in] phy_reg: 0x0 - 0x1F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction - \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) -{ - uint32_t reg, phy_flag; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* configure ENET_MAC_PHY_CTL with write/read operation */ - reg = ENET_MAC_PHY_CTL; - reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); - - /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; - } - - /* do PHY write/read operation, and wait the operation complete */ - ENET_MAC_PHY_CTL = reg; - do{ - phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); - timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - - /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ - enet_state = SUCCESS; - } - - /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; - } - - return enet_state; -} - -/*! - \brief enable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_enable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* enable the PHY loopback mode */ - temp_phy |= PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief disable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_disable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* disable the PHY loopback mode */ - temp_phy &= (uint16_t)~PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief enable ENET forward feature - \param[in] feature: the feature of ENET forward mode, - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames - \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames - \param[out] none - \retval none -*/ -void enet_forward_feature_enable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG |= mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); - ENET_DMA_CTL |= (mask >> 2); -} - -/*! - \brief disable ENET forward feature - \param[in] feature: the feature of ENET forward mode, - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function - \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_forward_feature_disable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG &= ~mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP))); - ENET_DMA_CTL &= ~(mask >> 2); -} - -/*! - \brief enable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_enable(uint32_t feature) -{ - ENET_MAC_FRMF |= feature; -} - -/*! - \brief disable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_disable(uint32_t feature) -{ - ENET_MAC_FRMF &= ~feature; -} - -/*! - \brief generate the pause frame, ENET will send pause frame after enable transmit flow control - this function only use in full-dulex mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_pauseframe_generate(void) -{ - ErrStatus enet_state =ERROR; - uint32_t temp = 0U; - - /* in full-duplex mode, must make sure this bit is 0 before writing register */ - temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ - ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; - enet_state = SUCCESS; - } - return enet_state; -} - -/*! - \brief configure the pause frame detect type - \param[in] detect: pause frame detect type, - only one parameter can be selected which is shown as below - \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also - use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified - in IEEE802.3 can be detected - \param[out] none - \retval none -*/ -void enet_pauseframe_detect_config(uint32_t detect) -{ - ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; - ENET_MAC_FCTL |= detect; -} - -/*! - \brief configure the pause frame parameters - \param[in] pausetime: pause time in transmit pause control frame - \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, - this value must make sure to be less than configured pause time, only one parameter can be - selected which is shown as below - \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times - \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times - \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times - \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times - \param[out] none - \retval none -*/ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) -{ - ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); - ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); -} - -/*! - \brief configure the threshold of the flow control(deactive and active threshold) - \param[in] deactive: the threshold of the deactive flow control, this value - should always be less than active flow control value, only one - parameter can be selected which is shown as below - \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[in] active: the threshold of the active flow control, only one parameter - can be selected which is shown as below - \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[out] none - \retval none -*/ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) -{ - ENET_MAC_FCTH = ((deactive | active) >> 8); -} - -/*! - \brief enable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_enable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL |= feature; -} - -/*! - \brief disable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_disable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL &= ~feature; -} - -/*! - \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: dma transmit process - \arg ENET_DMA_RX: dma receive process - \param[out] none - \retval state of dma process, the value range shows below: - ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, - ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, - ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, - ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING -*/ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) -{ - uint32_t reval; - reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); - return reval; -} - -/*! - \brief poll the DMA transmission/reception enable by writing any value to the - ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA transmit process - \arg ENET_DMA_RX: DMA receive process - \param[out] none - \retval none -*/ -void enet_dmaprocess_resume(enet_dmadirection_enum direction) -{ - if(ENET_DMA_TX == direction){ - ENET_DMA_TPEN = 0U; - }else{ - ENET_DMA_RPEN = 0U; - } -} - -/*! - \brief check and recover the Rx process - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxprocess_check_recovery(void) -{ - uint32_t status; - - /* get DAV information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with - receive descriptor address pointer updated by RxDMA controller */ - if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; - } -} - -/*! - \brief flush the ENET transmit FIFO, and wait until the flush operation completes - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_txfifo_flush(void) -{ - uint32_t flush_state; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; - /* wait until the flush operation completes */ - do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; - timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(RESET == flush_state){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table - \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, - only one parameter can be selected which is shown as below - \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table - \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by - the RxDMA controller - \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller - \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table - \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by - the TxDMA controller - \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none - \retval address value -*/ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) -{ - uint32_t reval = 0U; - - reval = REG32((ENET) +(uint32_t)addr_get); - return reval; -} - -/*! - \brief get the Tx or Rx descriptor information - \param[in] desc: the descriptor pointer which users want to get information - \param[in] info_get: the descriptor information type which is selected, - only one parameter can be selected which is shown as below - \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size - \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size - \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer - \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted - \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame - \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame - \param[out] none - \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter -*/ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) -{ - uint32_t reval = 0xFFFFFFFFU; - - switch(info_get){ - case RXDESC_BUFFER_1_SIZE: - reval = GET_RDES1_RB1S(desc->control_buffer_size); - break; - case RXDESC_BUFFER_2_SIZE: - reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: - reval = GET_RDES0_FRML(desc->status); - if(reval > 4U){ - reval = reval - 4U; - }else{ - reval = 0U; - } - break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_COLLISION_COUNT: - reval = GET_TDES0_COCNT(desc->status); - break; - default: - break; - } - return reval; -} - -/*! - \brief get the number of missed frames during receiving - \param[in] none - \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO - \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller - \retval none -*/ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) -{ - uint32_t temp_counter = 0U; - - temp_counter = ENET_DMA_MFBOCNT; - *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); - *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); -} - -/*! - \brief get the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to get flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred - \arg ENET_TDES0_UFE: underflow error - \arg ENET_TDES0_EXD: excessive deferral - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_ECO: excessive collision - \arg ENET_TDES0_LCO: late collision - \arg ENET_TDES0_NCA: no carrier - \arg ENET_TDES0_LCA: loss of carrier - \arg ENET_TDES0_IPPE: IP payload error - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_JT: jabber timeout - \arg ENET_TDES0_ES: error summary - \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error - \arg ENET_RDES0_CERR: CRC error - \arg ENET_RDES0_DBERR: dribble bit error - \arg ENET_RDES0_RERR: receive error - \arg ENET_RDES0_RWDT: receive watchdog timeout - \arg ENET_RDES0_FRMT: frame type - \arg ENET_RDES0_LCO: late collision - \arg ENET_RDES0_IPHERR: IP frame header error - \arg ENET_RDES0_LDES: last descriptor - \arg ENET_RDES0_FDES: first descriptor - \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error - \arg ENET_RDES0_LERR: length error - \arg ENET_RDES0_SAFF: SA filter fail - \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary - \arg ENET_RDES0_DAFF: destination address filter fail - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - FlagStatus enet_flag = RESET; - - if ((uint32_t)RESET != (desc->status & desc_flag)){ - enet_flag = SET; - } - - return enet_flag; -} - -/*! - \brief set the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to set flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status |= desc_flag; -} - -/*! - \brief clear the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to clear flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status &= ~desc_flag; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will set - \param[in] desc: the descriptor pointer which users want to configure - \param[out] none - \retval none -*/ -void enet_desc_receive_complete_bit_enable(enet_descriptors_struct *desc) -{ - desc->control_buffer_size &= ~ENET_RDES1_DINTC; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will not set - \param[in] desc: the descriptor pointer which users want to configure - \param[out] none - \retval none -*/ -void enet_desc_receive_complete_bit_disable(enet_descriptors_struct *desc) -{ - desc->control_buffer_size |= ENET_RDES1_DINTC; -} - -/*! - \brief drop current receive frame - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxframe_drop(void) -{ - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - } - - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - } - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc++; - } - } - } -} - -/*! - \brief enable DMA feature - \param[in] feature: the feature of DMA mode, - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_enable(uint32_t feature) -{ - ENET_DMA_CTL |= feature; -} - -/*! - \brief disable DMA feature - \param[in] feature: the feature of DMA mode, - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_disable(uint32_t feature) -{ - ENET_DMA_CTL &= ~feature; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select ring mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive ring mode and set buffer1 size */ - desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] timestamp: pointer to the table which stores the timestamp high and low - \param[out] buffer: pointer to the application buffer - note -- if the input is NULL, user should copy data in application by himself - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); - } - - }else{ - return ERROR; - } - } - /* copy timestamp value from Rx descriptor to application array */ - timestamp[0] = dma_current_rxdesc->buffer1_addr; - timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; - - dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; - dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_rxdesc ++; - } - } - - return SUCCESS; -} - -/*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode - \param[in] buffer: pointer on the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) -{ - uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->buffer1_addr; - timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; - } - dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; - dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_txdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; - } - } - return SUCCESS; -} - -/*! - \brief wakeup frame filter register pointer reset - \param[in] none - \param[out] none - \retval none -*/ -void enet_wum_filter_register_pointer_reset(void) -{ - ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; -} - -/*! - \brief set the remote wakeup frame registers - \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) - \param[out] none - \retval none -*/ -void enet_wum_filter_config(uint32_t pdata[]) -{ - uint32_t num = 0U; - - /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ - ENET_MAC_RWFF = pdata[num]; - } -} - -/*! - \brief enable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_WUM_POWER_DOWN: power down mode - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_enable(uint32_t feature) -{ - ENET_MAC_WUM |= feature; -} - -/*! - \brief disable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_disable(uint32_t feature) -{ - ENET_MAC_WUM &= (~feature); -} - -/*! - \brief reset the MAC statistics counters - \param[in] none - \param[out] none - \retval none -*/ -void enet_msc_counters_reset(void) -{ - /* reset all counters */ - ENET_MSC_CTL |= ENET_MSC_CTL_CTR; -} - -/*! - \brief enable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_enable(uint32_t feature) -{ - ENET_MSC_CTL |= feature; -} - -/*! - \brief disable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_disable(uint32_t feature) -{ - ENET_MSC_CTL &= (~feature); -} - -/*! - \brief get MAC statistics counter - \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, - only one parameter can be selected which is shown as below - \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter - \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter - \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter - \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter - \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter - \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter - \param[out] none - \retval the MSC counter value -*/ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) -{ - uint32_t reval; - - reval = REG32((ENET + (uint32_t)counter)); - - return reval; -} - -/*! - \brief change subsecond to nanosecond - \param[in] subsecond: subsecond value - \param[out] none - \retval the nanosecond value -*/ -uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) -{ - uint64_t val = subsecond * 1000000000Ull; - val >>= 31; - return (uint32_t)val; -} - -/*! - \brief change nanosecond to subsecond - \param[in] nanosecond: nanosecond value - \param[out] none - \retval the subsecond value -*/ -uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond) -{ - uint64_t val = nanosecond * 0x80000000Ull; - val /= 1000000000U; - return (uint32_t)val; -} - -/*! - \brief enable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \param[out] none - \retval none -*/ -void enet_ptp_feature_enable(uint32_t feature) -{ - ENET_PTP_TSCTL |= feature; -} - -/*! - \brief disable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \param[out] none - \retval none -*/ -void enet_ptp_feature_disable(uint32_t feature) -{ - ENET_PTP_TSCTL &= ~feature; -} - -/*! - \brief configure the PTP timestamp function - \param[in] func: only one parameter can be selected which is shown as below - \arg ENET_PTP_ADDEND_UPDATE: addend register update - \arg ENET_PTP_SYSTIME_UPDATE: timestamp update - \arg ENET_PTP_SYSTIME_INIT: timestamp initialize - \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating - \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ - -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) -{ - uint32_t temp_config = 0U, temp_state = 0U; - uint32_t timeout = 0U; - ErrStatus enet_state = SUCCESS; - - switch(func){ - case ENET_PTP_ADDEND_UPDATE: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } - break; - case ENET_PTP_SYSTIME_UPDATE: - /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; - case ENET_PTP_SYSTIME_INIT: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; - default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; - } - break; - } - - return enet_state; -} - -/*! - \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time, - this value must be between 0 and 0xFF - \param[out] none - \retval none -*/ -void enet_ptp_subsecond_increment_config(uint32_t subsecond) -{ - ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); -} - -/*! - \brief adjusting the clock frequency only in fine update mode - \param[in] add: the value will be added to the accumulator register to achieve time synchronization - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_addend_config(uint32_t add) -{ - ENET_PTP_TSADDEND = add; -} - -/*! - \brief initialize or add/subtract to second of the system time - \param[in] sign: timestamp update positive or negative sign, - only one parameter can be selected which is shown as below - \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time - \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time - \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time - with 0.46 ns accuracy if required accuracy is 20 ns - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) -{ - ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); -} - -/*! - \brief configure the expected target time - \param[in] second: the expected target second time - \param[in] nanosecond: the expected target nanosecond time (signed) - \param[out] none - \retval none -*/ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) -{ - ENET_PTP_ETH = second; - ENET_PTP_ETL = nanosecond; -} - -/*! - \brief get the current system time - \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \retval none -*/ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) -{ - uint32_t temp_sec = 0U, temp_subs = 0U; - - /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; - temp_subs = (uint32_t)ENET_PTP_TSL; - - /* get sysytem time and construct the enet_ptp_systime_struct structure */ - systime_struct->second = temp_sec; - systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); - systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); - systime_struct->sign = GET_PTP_TSL_STS(temp_subs); -} - -/*! - \brief configure and start PTP timestamp counter - \param[in] updatemethod: method for updating - \arg ENET_PTP_FINEMODE: fine correction method - \arg ENET_PTP_COARSEMODE: coarse correction method - \param[in] init_sec: second value for initializing system time - \param[in] init_subsec: subsecond value for initializing system time - \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used) - \param[in] accuracy_cfg: the value to be added to the subsecond value of system time - \param[out] none - \retval none -*/ -void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) -{ - /* mask the timestamp trigger interrupt */ - enet_interrupt_disable(ENET_MAC_INT_TMSTIM); - - /* enable timestamp */ - enet_ptp_feature_enable(ENET_RXTX_TIMESTAMP); - - /* configure system time subsecond increment based on the PTP clock frequency */ - enet_ptp_subsecond_increment_config(accuracy_cfg); - - if(ENET_PTP_FINEMODE == updatemethod){ - /* fine correction method: configure the timestamp addend, then update */ - enet_ptp_timestamp_addend_config(carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); - /* wait until update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ - } - } - - /* choose the fine correction method */ - enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod); - - /* initialize the system time */ - enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); -} - -/*! - \brief adjust frequency in fine method by configure addend register - \param[in] carry_cfg: the value to be added to the accumulator register - \param[out] none - \retval none -*/ -void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) -{ - /* re-configure the timestamp addend, then update */ - enet_ptp_timestamp_addend_config((uint32_t)carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); -} - -/*! - \brief update system time in coarse method - \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \param[out] none - \retval none -*/ -void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct) -{ - uint32_t subsecond_val; - uint32_t carry_cfg; - - subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); - - /* save the carry_cfg value */ - carry_cfg = ENET_PTP_TSADDEND_TMSA; - - /* update the system time */ - enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); - - /* wait until the update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ - } - - /* write back the carry_cfg value, then update */ - enet_ptp_timestamp_addend_config(carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); -} - -/*! - \brief set system time in fine method - \param[in] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \param[out] none - \retval none -*/ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) -{ - uint32_t subsecond_val; - - subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); - - /* initialize the system time */ - enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); - - /* wait until the system time initialzation finished */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ - } -} - -/*! - \brief get the ptp flag status - \param[in] flag: ptp flag status to be checked - \arg ENET_PTP_ADDEND_UPDATE: addend register update - \arg ENET_PTP_SYSTIME_UPDATE: timestamp update - \arg ENET_PTP_SYSTIME_INIT: timestamp initialize - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_ptp_flag_get(uint32_t flag) -{ - FlagStatus bitstatus = RESET; - - if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ - bitstatus = SET; - } - - return bitstatus; -} - -/*! - \brief reset the ENET initpara struct, call it before using enet_initpara_config() - \param[in] none - \param[out] none - \retval none -*/ -void enet_initpara_reset(void) -{ - enet_initpara.option_enable = 0U; - enet_initpara.forward_frame = 0U; - enet_initpara.dmabus_mode = 0U; - enet_initpara.dma_maxburst = 0U; - enet_initpara.dma_arbitration = 0U; - enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; - enet_initpara.vlan_config = 0U; - enet_initpara.flow_control = 0U; - enet_initpara.hashtable_high = 0U; - enet_initpara.hashtable_low = 0U; - enet_initpara.framesfilter_mode = 0U; - enet_initpara.halfduplex_param = 0U; - enet_initpara.timer_config = 0U; - enet_initpara.interframegap = 0U; -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() - \param[in] none - \param[out] none - \retval none -*/ -static void enet_default_init(void) -{ - uint32_t reg_value = 0U; - - /* MAC */ - /* configure ENET_MAC_CFG register */ - reg_value = ENET_MAC_CFG; - reg_value &= MAC_CFG_MASK; - reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; - ENET_MAC_CFG = reg_value; - - /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; - - /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ - ENET_MAC_HLH = 0x0U; - - ENET_MAC_HLL = 0x0U; - - /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ - reg_value = ENET_MAC_FCTL; - reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; - ENET_MAC_FCTL = reg_value; - - ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - - /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); - - /* DMA */ - /* configure ENET_DMA_CTL register */ - reg_value = ENET_DMA_CTL; - reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; - ENET_DMA_CTL = reg_value; - - /* configure ENET_DMA_BCTL register */ - reg_value = ENET_DMA_BCTL; - reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE; - ENET_DMA_BCTL = reg_value; -} - -#ifndef USE_DELAY -/*! - \brief insert a delay time - \param[in] ncount: specifies the delay time length - \param[out] none - \param[out] none -*/ -static void enet_delay(uint32_t ncount) -{ - uint32_t delay_time = 0U; - - for(delay_time = ncount; delay_time != 0U; delay_time--){ - } -} -#endif /* USE_DELAY */ - -#endif /* GD32F10X_CL */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c deleted file mode 100644 index 641e716ca1..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exmc.c +++ /dev/null @@ -1,646 +0,0 @@ -/*! - \file gd32f10x_exmc.c - \brief EXMC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_exmc.h" - -/* EXMC bank0 register reset value */ -#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DBU) -#define BANK0_SNCTL1_2_3_REGION_RESET ((uint32_t)0x000030D2U) -#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) -#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) - -/* EXMC bank1/2 register reset mask*/ -#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) - -/* EXMC bank3 register reset mask*/ -#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) - -/* EXMC register bit offset */ -#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) -#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) -#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) -#define SNCTL_WREN_OFFSET ((uint32_t)12U) -#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) -#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) -#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) - -#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) -#define SNTCFG_DSET_OFFSET ((uint32_t)8U) -#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) - -#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) -#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) -#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) - -#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) -#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) - -#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) -#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) - -#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) -#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) -#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) - -#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) -#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) -#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) - -#define INTEN_INTS_OFFSET ((uint32_t)3U) - -/*! - \brief deinitialize EXMC NOR/SRAM region - \param[in] norsram_region: select the region of bank0 - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_deinit(uint32_t norsram_region) -{ - /* reset the registers */ - if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){ - EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; - }else{ - EXMC_SNCTL(norsram_region) = BANK0_SNCTL1_2_3_REGION_RESET; - } - - EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET; - EXMC_SNWTCFG(norsram_region) = BANK0_SNWTCFG_RESET; -} - -/*! - \brief initialize EXMC NOR/SRAM region - \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 - write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE - asyn_wait: ENABLE or DISABLE - nwait_signal: ENABLE or DISABLE - memory_write: ENABLE or DISABLE - nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING - wrap_burst_mode: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH - burst_mode: ENABLE or DISABLE - databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR - address_data_mux: ENABLE or DISABLE - read_write_timing: struct exmc_norsram_timing_parameter_struct set the time - write_timing: struct exmc_norsram_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U; - - /* get the register value */ - snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); - - /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRMUX )); - - snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - - sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| - (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | - (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | - (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )| - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ - snctl |= (uint32_t)EXMC_SNCTL_NREN; - } - - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode){ - snwtcfg = (uint32_t)(((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET) | - (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime - 1U) << SNTCFG_AHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD)| - (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime - 1U) << SNTCFG_DSET_OFFSET) & EXMC_SNWTCFG_WDSET) | - exmc_norsram_init_struct->write_timing->asyn_access_mode); - }else{ - snwtcfg = BANK0_SNWTCFG_RESET; - } - - /* configure the registers */ - EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; - EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; - EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; -} - -/*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - /* configure the structure with default value */ - exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; - exmc_norsram_init_struct->address_data_mux = ENABLE; - exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; - exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; - exmc_norsram_init_struct->burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - exmc_norsram_init_struct->wrap_burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; - exmc_norsram_init_struct->memory_write = ENABLE; - exmc_norsram_init_struct->nwait_signal = ENABLE; - exmc_norsram_init_struct->extended_mode = DISABLE; - exmc_norsram_init_struct->asyn_wait = DISABLE; - exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - - /* read/write timing configure */ - exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; - exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; - exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - - /* write timing configure, when extended mode is used */ - exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; -} - -/*! - \brief enable EXMC NOR/PSRAM bank region - \param[in] norsram_region: specifie the region of NOR/PSRAM bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_enable(uint32_t norsram_region) -{ - EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief disable EXMC NOR/PSRAM bank region - \param[in] norsram_region: specifie the region of NOR/PSRAM Bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_disable(uint32_t norsram_region) -{ - EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief deinitialize EXMC NAND bank - \param[in] nand_bank: select the bank of NAND - \arg EXMC_BANKx_NAND(x=1..2) - \param[out] none - \retval none -*/ -void exmc_nand_deinit(uint32_t nand_bank) -{ - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ - EXMC_NPCTL(nand_bank) = BANK1_2_NPCTL_RESET; - EXMC_NPINTEN(nand_bank) = BANK1_2_NPINTEN_RESET; - EXMC_NPCTCFG(nand_bank) = BANK1_2_NPCTCFG_RESET; - EXMC_NPATCFG(nand_bank) = BANK1_2_NPATCFG_RESET; -} - -/*! - \brief initialize EXMC NAND bank - \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter - nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND - ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - ecc_logic: ENABLE or DISABLE - databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - - npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| - EXMC_NPCTL_NDTP | - exmc_nand_init_struct->databus_width | - (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| - exmc_nand_init_struct->ecc_size | - exmc_nand_init_struct->ctr_latency | - exmc_nand_init_struct->atr_latency; - - npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ - EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; - EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; - EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; -} - -/*! - \brief initialize the struct exmc_nand_init_struct - \param[in] none - \param[out] the initialized struct exmc_nand_init_struct pointer - \retval none -*/ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - /* configure the structure with default value */ - exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; - exmc_nand_init_struct->wait_feature = DISABLE; - exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; - exmc_nand_init_struct->ecc_logic = DISABLE; - exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; - exmc_nand_init_struct->ctr_latency = 0x0U; - exmc_nand_init_struct->atr_latency = 0x0U; - exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; - exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief enable NAND bank - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_enable(uint32_t nand_bank) -{ - EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable NAND bank - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_disable(uint32_t nand_bank) -{ - EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_NDBKEN; -} - -/*! - \brief enable or disable the EXMC NAND ECC function - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_nand_ecc_config(uint32_t nand_bank, ControlStatus newvalue) -{ - if (ENABLE == newvalue){ - /* enable the selected NAND bank ECC function */ - EXMC_NPCTL(nand_bank) |= EXMC_NPCTL_ECCEN; - }else{ - /* disable the selected NAND bank ECC function */ - EXMC_NPCTL(nand_bank) &= ~EXMC_NPCTL_ECCEN; - } -} - -/*! - \brief get the EXMC ECC value - \param[in] nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval the error correction code(ECC) value -*/ -uint32_t exmc_ecc_get(uint32_t nand_bank) -{ - return (EXMC_NECC(nand_bank)); -} - -/*! - \brief deinitialize EXMC PC card bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_deinit(void) -{ - /* EXMC_BANK3_PCCARD */ - EXMC_NPCTL3 = BANK3_NPCTL_RESET; - EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; - EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; - EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; - EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; -} - -/*! - \brief initialize EXMC PC card bank - \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the EXMC bank3 PC card control register */ - EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; - - /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) | - (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )| - (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | - (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | - ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )| - ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); -} - -/*! - \brief initialize the struct exmc_pccard_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer - \retval none -*/ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the structure with default value */ - exmc_pccard_init_struct->wait_feature = DISABLE; - exmc_pccard_init_struct->ctr_latency = 0x0U; - exmc_pccard_init_struct->atr_latency = 0x0U; - exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief enable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_enable(void) -{ - EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_disable(void) -{ - EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; -} - -/*! - \brief enable EXMC interrupt - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_enable(uint32_t bank, uint32_t interrupt_source) -{ - /* NAND bank1, bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) |= interrupt_source; -} - -/*! - \brief disable EXMC interrupt - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_disable(uint32_t bank, uint32_t interrupt_source) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~interrupt_source; -} - -/*! - \brief check EXMC flag is set or not - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC Card bank - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_flag_get(uint32_t bank, uint32_t flag) -{ - uint32_t status = 0x00000000U; - - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(bank); - - if ((status & flag) != (uint32_t)flag ){ - /* flag is reset */ - return RESET; - }else{ - /* flag is set */ - return SET; - } -} - -/*! - \brief clear EXMC flag - \param[in] bank: specifie the NAND bank, PCCARD bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] flag: specify get which flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \param[out] none - \retval none -*/ -void exmc_flag_clear(uint32_t bank, uint32_t flag) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~flag; -} - -/*! - \brief check EXMC interrupt flag is set or not - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_interrupt_flag_get(uint32_t bank, uint32_t interrupt_source) -{ - uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; - - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(bank); - interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); - - interrupt_enable = (status & interrupt_source); - - if ((interrupt_enable) && (interrupt_state)){ - /* interrupt flag is set */ - return SET; - }else{ - /* interrupt flag is reset */ - return RESET; - } -} - -/*! - \brief clear EXMC interrupt flag - \param[in] bank: specifies the NAND bank, PC card bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - one or more parameters can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_flag_clear(uint32_t bank, uint32_t interrupt_source) -{ - /* NAND bank1, bank2 or PC card bank3 */ - EXMC_NPINTEN(bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c deleted file mode 100644 index dcda291314..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_exti.c +++ /dev/null @@ -1,256 +0,0 @@ -/*! - \file gd32f10x_exti.c - \brief EXTI driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_exti.h" - -#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = EXTI_REG_RESET_VALUE; - EXTI_EVEN = EXTI_REG_RESET_VALUE; - EXTI_RTEN = EXTI_REG_RESET_VALUE; - EXTI_FTEN = EXTI_REG_RESET_VALUE; - EXTI_SWIEV = EXTI_REG_RESET_VALUE; -} - -/*! - \brief initialize the EXTI - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling edge trigger - \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch(trig_type){ - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI lines flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c deleted file mode 100644 index 83da3519e0..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fmc.c +++ /dev/null @@ -1,965 +0,0 @@ -/*! - \file gd32f10x_fmc.c - \brief FMC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_fmc.h" - -/*! - \brief set the wait state counter value - \param[in] wscnt£ºwait state counter value - \arg WS_WSCNT_0: FMC 0 wait state - \arg WS_WSCNT_1: FMC 1 wait state - \arg WS_WSCNT_2: FMC 2 wait state - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint32_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief unlock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ - /* write the FMC unlock key */ - FMC_KEY0 = UNLOCK_KEY0; - FMC_KEY0 = UNLOCK_KEY1; - } - - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* write the FMC unlock key */ - if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ - FMC_KEY1 = UNLOCK_KEY0; - FMC_KEY1 = UNLOCK_KEY1; - } - } -} - -/*! - \brief unlock the FMC bank0 operation - this function can be used for all GD32F10x devices. - for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. - for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank0_unlock(void) -{ - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ - /* write the FMC unlock key */ - FMC_KEY0 = UNLOCK_KEY0; - FMC_KEY0 = UNLOCK_KEY1; - } -} - -/*! - \brief unlock the FMC bank1 operation - this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank1_unlock(void) -{ - if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ - /* write the FMC unlock key */ - FMC_KEY1 = UNLOCK_KEY0; - FMC_KEY1 = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit */ - FMC_CTL0 |= FMC_CTL0_LK; - - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* set the LK bit */ - FMC_CTL1 |= FMC_CTL1_LK; - } -} - -/*! - \brief lock the FMC bank0 operation - this function can be used for all GD32F10X devices. - for GD32F10x_MD and GD32F10x_HD, this function unlocks bank0. - for GD32F10x_XD and GD32F10x_CL with flash no more than 512KB, it is equivalent to fmc_unlock function. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank0_lock(void) -{ - /* set the LK bit*/ - FMC_CTL0 |= FMC_CTL0_LK; -} - -/*! - \brief lock the FMC bank1 operation - this function can be used for GD32F10x_XD and GD32F10x_CL with flash more than 512KB. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank1_lock(void) -{ - /* set the LK bit*/ - FMC_CTL1 |= FMC_CTL1_LK; -} - -/*! - \brief erase page - \param[in] page_address: the page address to be erased. - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state; - - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > page_address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_PER; - FMC_ADDR0 = page_address; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL0 &= ~FMC_CTL0_PER; - } - }else{ - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL1 |= FMC_CTL1_PER; - FMC_ADDR1 = page_address; - if(FMC_OBSTAT & FMC_OBSTAT_SPC){ - FMC_ADDR0 = page_address; - } - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL1 &= ~FMC_CTL1_PER; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_PER; - FMC_ADDR0 = page_address; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL0 &= ~FMC_CTL0_PER; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state; - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL1 |= FMC_CTL1_MER; - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL1 &= ~FMC_CTL1_MER; - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase bank0 - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start FMC bank0 erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief erase bank1 - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start FMC bank1 erase */ - FMC_CTL1 |= FMC_CTL1_MER; - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL1 &= ~FMC_CTL1_MER; - } - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL1 |= FMC_CTL1_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL1 &= ~FMC_CTL1_PG; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a half word at the corresponding address - \param[in] address: address to program - \param[in] data: halfword to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - if(FMC_BANK0_SIZE > FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL1 |= FMC_CTL1_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL1 &= ~FMC_CTL1_PG; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } - - /* wait until OBWEN bit is set by hardware */ - while(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ - } -} - -/*! - \brief lock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWEN bit */ - FMC_CTL0 &= ~FMC_CTL0_OBWEN; -} - -/*! - \brief erase the FMC option byte - unlock the FMC_CTL0 and option byte before calling this function - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_erase(void) -{ - uint16_t temp_spc = FMC_NSPC; - - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - /* check the option byte security protection value */ - if(RESET != ob_spc_get()){ - temp_spc = FMC_USPC; - } - - if(FMC_READY == fmc_state){ - - /* start erase the option byte */ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - /* no security protection */ - OB_SPC = (uint16_t)temp_spc; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if - you want to protect the corresponding pages. meanwhile, sector - macro could used to set specific sector write protected. - one or more parameters can be selected which are shown as below: - \arg OB_WPx(x = 0..31): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) -{ - uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; - - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - ob_wp = (uint32_t)(~ob_wp); - temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); - temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); - temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); - temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); - - if(FMC_READY == fmc_state){ - - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - if(0xFFU != temp_wp0){ - OB_WP0 = temp_wp0; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ - OB_WP1 = temp_wp1; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ - OB_WP2 = temp_wp2; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ - OB_WP3 = temp_wp3; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection - only one parameter can be selected which is shown as below: - \arg FMC_NSPC: no security protection - \arg FMC_USPC: under security protection - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc) -{ - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - - /* start the option byte program */ - FMC_CTL0 |= FMC_CTL0_OBPG; - - OB_SPC = (uint16_t)ob_spc; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option byte - \param[in] ob_fwdgt: option byte watchdog value - \arg OB_FWDGT_SW: software free watchdog - \arg OB_FWDGT_HW: hardware free watchdog - \param[in] ob_deepsleep: option byte deepsleep reset value - \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \param[in] ob_stdby:option byte standby reset value - \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \param[in] ob_boot: specifies the option byte boot bank value - \arg OB_BOOT_B0: boot from bank0 - \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) -{ - fmc_state_enum fmc_state = FMC_READY; - uint8_t temp; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); - OB_USER = (uint16_t)temp; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program option bytes data - \param[in] address: the option bytes address to be programmed - \param[in] data: the byte to be programmed - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data) -{ - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - REG16(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC user option byte - \param[in] none - \param[out] none - \retval the FMC user option byte values -*/ -uint8_t ob_user_get(void) -{ - /* return the FMC user option byte value */ - return (uint8_t)(FMC_OBSTAT >> 2U); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> 10U); -} - -/*! - \brief get the FMC option byte write protection - \param[in] none - \param[out] none - \retval the FMC write protection option byte value -*/ -uint32_t ob_write_protection_get(void) -{ - /* return the FMC write protection option byte value */ - return FMC_WP; -} - -/*! - \brief get the FMC option byte security protection - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ob_spc_get(void) -{ - FlagStatus spc_state = RESET; - - if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ - spc_state = SET; - }else{ - spc_state = RESET; - } - return spc_state; -} - -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief check flag is set or not - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit - \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit - \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit - \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit - \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit - \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit - \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit - \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit - \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the FMC flag - \param[in] flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit - \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit - \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit - \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit - \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit - \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); -} - -/*! - \brief get FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit - \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); - }else{ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); - } - - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit - \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) -{ - FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); -} - -/*! - \brief get the FMC bank0 state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ - fmc_state = FMC_PGERR; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC bank1 state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ - fmc_state = FMC_PGERR; - } - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC bank0 is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_bank0_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC bank1 is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_bank1_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c deleted file mode 100644 index 0025c9a572..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_fwdgt.c +++ /dev/null @@ -1,155 +0,0 @@ -/*! - \file gd32f10x_fwdgt.c - \brief FWDGT driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_fwdgt.h" - -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status){ - return ERROR; - } - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status){ - return ERROR; - } - FWDGT_RLD = RLD_RLD(reload_value); - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(FWDGT_STAT & flag){ - return SET; - } - - return RESET; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c deleted file mode 100644 index d8bdd709bb..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_gpio.c +++ /dev/null @@ -1,539 +0,0 @@ -/*! - \file gd32f10x_gpio.c - \brief GPIO driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_gpio.h" - -#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ -#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ -#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ -#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ -#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ -#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ -#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ -#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ -#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch(gpio_periph){ - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOD: - /* reset GPIOD */ - rcu_periph_reset_enable(RCU_GPIODRST); - rcu_periph_reset_disable(RCU_GPIODRST); - break; - case GPIOE: - /* reset GPIOE */ - rcu_periph_reset_enable(RCU_GPIOERST); - rcu_periph_reset_disable(RCU_GPIOERST); - break; - case GPIOF: - /* reset GPIOF */ - rcu_periph_reset_enable(RCU_GPIOFRST); - rcu_periph_reset_disable(RCU_GPIOFRST); - break; - case GPIOG: - /* reset GPIOG */ - rcu_periph_reset_enable(RCU_GPIOGRST); - rcu_periph_reset_disable(RCU_GPIOGRST); - break; - default: - break; - } -} - -/*! - \brief reset alternate function I/O(AFIO) - \param[in] none - \param[out] none - \retval none -*/ -void gpio_afio_deinit(void) -{ - rcu_periph_reset_enable(RCU_AFRST); - rcu_periph_reset_disable(RCU_AFRST); -} - -/*! - \brief GPIO parameter initialization - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] mode: gpio pin mode - only one parameter can be selected which is shown as below: - \arg GPIO_MODE_AIN: analog input mode - \arg GPIO_MODE_IN_FLOATING: floating input mode - \arg GPIO_MODE_IPD: pull-down input mode - \arg GPIO_MODE_IPU: pull-up input mode - \arg GPIO_MODE_OUT_OD: GPIO output with open-drain - \arg GPIO_MODE_OUT_PP: GPIO output with push-pull - \arg GPIO_MODE_AF_OD: AFIO output with open-drain - \arg GPIO_MODE_AF_PP: AFIO output with push-pull - \param[in] speed: gpio output max speed value - only one parameter can be selected which is shown as below: - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - - \param[out] none - \retval none -*/ -void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t temp_mode = 0U; - uint32_t reg = 0U; - - /* GPIO mode configuration */ - temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); - - /* GPIO speed configuration */ - if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ - /* output mode max speed:10MHz,2MHz,50MHz */ - temp_mode |= (uint32_t)speed; - } - - /* configure the eight low port pins with GPIO_CTL0 */ - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL0(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL0 register */ - GPIO_CTL0(gpio_periph) = reg; - } - } - /* configure the eight high port pins with GPIO_CTL1 */ - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL1(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i - 8U); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i - 8U, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL1 register */ - GPIO_CTL1(gpio_periph) = reg; - } - } -} - -/*! - \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if(RESET != bit_value){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] data: specify the value to be written to the port output data register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph,uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval input status of gpio pin: SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO port input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval input status of gpio all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t)(GPIO_ISTAT(gpio_periph)); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval output status of gpio pin: SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO port output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval output status of gpio all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return ((uint16_t)GPIO_OCTL(gpio_periph)); -} - -/*! - \brief configure GPIO pin remap - \param[in] gpio_remap: select the pin to remap - \arg GPIO_SPI0_REMAP: SPI0 remapping - \arg GPIO_I2C0_REMAP: I2C0 remapping - \arg GPIO_USART0_REMAP: USART0 remapping - \arg GPIO_USART1_REMAP: USART1 remapping - \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping - \arg GPIO_USART2_FULL_REMAP: USART2 full remapping - \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping - \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping - \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping - \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping - \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping - \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping - \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping - \arg GPIO_TIMER3_REMAP: TIMER3 remapping - \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F10X_CL devices) - \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F10X_CL devices) - \arg GPIO_PD01_REMAP: PD01 remapping - \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F10X_CL devices and GD32F10X_HD devices) - \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F10X_MD, GD32F10X_HD devices and GD32F10X_XD devices) - \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F10X_CL devices) - \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F10X_CL devices) - \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST - \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled - \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled - \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F10X_CL devices) - \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F10X_CL devices) - \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F10X_CL devices) - \arg GPIO_TIMER8_REMAP: TIMER8 remapping - \arg GPIO_TIMER9_REMAP: TIMER9 remapping - \arg GPIO_TIMER10_REMAP: TIMER10 remapping - \arg GPIO_TIMER12_REMAP: TIMER12 remapping - \arg GPIO_TIMER13_REMAP: TIMER13 remapping - \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) -{ - uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; - - if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ - /* get AFIO_PCF1 regiter value */ - temp_reg = AFIO_PCF1; - }else{ - /* get AFIO_PCF0 regiter value */ - temp_reg = AFIO_PCF0; - } - - temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; - remap1 = remap & LSB_16BIT_MASK; - - /* judge pin remap type */ - if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ - temp_reg &= PCF_SWJCFG_MASK; - AFIO_PCF0 &= PCF_SWJCFG_MASK; - }else if(PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)){ - remap2 = ((uint32_t)0x03U) << temp_mask; - temp_reg &= ~remap2; - temp_reg |= ~PCF_SWJCFG_MASK; - }else{ - temp_reg &= ~(remap1 << ((remap >> 0x15U)*0x10U)); - temp_reg |= ~PCF_SWJCFG_MASK; - } - - /* set pin remap value */ - if(DISABLE != newvalue){ - temp_reg |= (remap1 << ((remap >> 0x15U)*0x10U)); - } - - if(AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)){ - /* set AFIO_PCF1 regiter value */ - AFIO_PCF1 = temp_reg; - }else{ - /* set AFIO_PCF0 regiter value */ - AFIO_PCF0 = temp_reg; - } -} - -/*! - \brief select GPIO pin exti sources - \param[in] gpio_outputport: gpio event output port - \arg GPIO_PORT_SOURCE_GPIOA: output port source A - \arg GPIO_PORT_SOURCE_GPIOB: output port source B - \arg GPIO_PORT_SOURCE_GPIOC: output port source C - \arg GPIO_PORT_SOURCE_GPIOD: output port source D - \arg GPIO_PORT_SOURCE_GPIOE: output port source E - \arg GPIO_PORT_SOURCE_GPIOF: output port source F - \arg GPIO_PORT_SOURCE_GPIOG: output port source G - \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) -{ - uint32_t source = 0U; - source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); - - /* select EXTI sources */ - if(GPIO_PIN_SOURCE_4 > output_pin){ - /* select EXTI0/EXTI1/EXTI2/EXTI3 */ - AFIO_EXTISS0 &= ~source; - AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else if(GPIO_PIN_SOURCE_8 > output_pin){ - /* select EXTI4/EXTI5/EXTI6/EXTI7 */ - AFIO_EXTISS1 &= ~source; - AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else if(GPIO_PIN_SOURCE_12 > output_pin){ - /* select EXTI8/EXTI9/EXTI10/EXTI11 */ - AFIO_EXTISS2 &= ~source; - AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - }else{ - /* select EXTI12/EXTI13/EXTI14/EXTI15 */ - AFIO_EXTISS3 &= ~source; - AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } -} - -/*! - \brief configure GPIO pin event output - \param[in] output_port: gpio event output port - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PORT_GPIOA: event output port A - \arg GPIO_EVENT_PORT_GPIOB: event output port B - \arg GPIO_EVENT_PORT_GPIOC: event output port C - \arg GPIO_EVENT_PORT_GPIOD: event output port D - \arg GPIO_EVENT_PORT_GPIOE: event output port E - \arg GPIO_EVENT_PORT_GPIOE: event output port F - \arg GPIO_EVENT_PORT_GPIOE: event output port G - \param[in] output_pin: - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PIN_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) -{ - uint32_t reg = 0U; - reg = AFIO_EC; - - /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ - reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); - - reg |= (uint32_t)((uint32_t)output_port << GPIO_OUTPUT_PORT_OFFSET); - reg |= (uint32_t)output_pin; - - AFIO_EC = reg; -} - -/*! - \brief enable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_enable(void) -{ - AFIO_EC |= AFIO_EC_EOE; -} - -/*! - \brief disable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_disable(void) -{ - AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); -} - -/*! - \brief lock GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -#ifdef GD32F10X_CL -/*! - \brief select ethernet MII or RMII PHY - \param[in] gpio_enetsel: ethernet MII or RMII PHY selection - \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY - \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY - \param[out] none - \retval none -*/ -void gpio_ethernet_phy_select(uint32_t gpio_enetsel) -{ - /* clear AFIO_PCF0_ENET_PHY_SEL bit */ - AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); - - /* select MII or RMII PHY */ - AFIO_PCF0 |= (uint32_t)gpio_enetsel; -} -#endif diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c deleted file mode 100644 index fa1ae96d23..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_i2c.c +++ /dev/null @@ -1,707 +0,0 @@ -/*! - \file gd32f10x_i2c.c - \brief I2C driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch(i2c_periph){ - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - \param[in] dutycyc: duty cycle in fast mode - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) = I2CCLK_MAX; - }else if(risetime <= I2CCLK_MIN){ - I2C_RT(i2c_periph) = I2CCLK_MIN; - }else{ - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - }else if(400000U >= clkspeed){ - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if(0U == (clkc & I2C_CKCFG_CLKC)){ - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - }else{ - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief configure I2C POAP position - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ - addr = addr & I2C_TRANSMITTER; - }else{ - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief dual-address mode switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dualaddr: - only one parameter can be selected which is shown as below: - \arg I2C_DUADEN_DISABLE: disable dual-address mode - \arg I2C_DUADEN_ENABLE: enable dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) -{ - if(I2C_DUADEN_ENABLE == dualaddr){ - I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; - }else{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); - } -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none -*/ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_DISSTRC); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C PEC calculation on or off - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none -*/ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) &I2C_STAT1_ECV)>>STAT1_PECV_OFFSET); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable or disable I2C ARP protocol in SMBus switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] arpstate: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(I2C_FLAG_ADDSEND == flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ - intenable = 1U; - }else{ - intenable = 0U; - } - } - if((0U != flagstatus) && (0U != intenable)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - if(I2C_INT_FLAG_ADDSEND == int_flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c deleted file mode 100644 index 1a96627b3a..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_misc.c +++ /dev/null @@ -1,187 +0,0 @@ -/*! - \file gd32f10x_misc.c - \brief MISC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_misc.h" - -/*! - \brief set the priority group - \param[in] nvic_prigroup: the NVIC priority group - \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority - \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority - \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority - \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority - \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority - \param[out] none - \retval none -*/ -void nvic_priority_group_set(uint32_t nvic_prigroup) -{ - /* set the priority group value */ - SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; -} - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set - \param[in] nvic_irq_sub_priority: the subpriority needed to set - \param[out] none - \retval none -*/ -void nvic_irq_enable(uint8_t nvic_irq, - uint8_t nvic_irq_pre_priority, - uint8_t nvic_irq_sub_priority) -{ - uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; - - /* use the priority group value to get the temp_pre and the temp_sub */ - switch ((SCB->AIRCR) & (uint32_t)0x700U) { - case NVIC_PRIGROUP_PRE0_SUB4: - temp_pre = 0U; - temp_sub = 0x4U; - break; - case NVIC_PRIGROUP_PRE1_SUB3: - temp_pre = 1U; - temp_sub = 0x3U; - break; - case NVIC_PRIGROUP_PRE2_SUB2: - temp_pre = 2U; - temp_sub = 0x2U; - break; - case NVIC_PRIGROUP_PRE3_SUB1: - temp_pre = 3U; - temp_sub = 0x1U; - break; - case NVIC_PRIGROUP_PRE4_SUB0: - temp_pre = 4U; - temp_sub = 0x0U; - break; - default: - nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre = 2U; - temp_sub = 0x2U; - break; - } - - /* get the temp_priority to fill the NVIC->IP register */ - temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); - temp_priority = temp_priority << 0x04U; - NVIC->IP[nvic_irq] = (uint8_t)temp_priority; - - /* enable the selected IRQ */ - NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(uint8_t nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - \arg NVIC_VECTTAB_RAM: RAM base address - \are NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c deleted file mode 100644 index 33052db8d1..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c +++ /dev/null @@ -1,265 +0,0 @@ -/*! - \file gd32f10x_pmu.c - \brief PMU driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_pmu.h" - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - only one parameter can be selected which is shown as below: - \arg PMU_LVDT_0: voltage threshold is 2.2V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.5V - \arg PMU_LVDT_4: voltage threshold is 2.6V - \arg PMU_LVDT_5: voltage threshold is 2.7V - \arg PMU_LVDT_6: voltage threshold is 2.8V - \arg PMU_LVDT_7: voltage threshold is 2.9V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo: - only one parameter can be selected which is shown as below: - \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) -{ - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ - __WFI(); - }else{ - __SEV(); - __WFE(); - __WFE(); - } - /* reset sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set sleepdeep bit of Cortex-M3 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief enable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(void) -{ - PMU_CS |= PMU_CS_WUPEN; -} - -/*! - \brief disable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(void) -{ - PMU_CS &= ~PMU_CS_WUPEN; -} - -/*! - \brief enable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief get flag state - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \param[out] none - \retval FlagStatus SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - if(PMU_CS & flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag bit - \param[in] flag_reset: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag_reset) -{ - switch(flag_reset){ - case PMU_FLAG_RESET_WAKEUP: - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - break; - case PMU_FLAG_RESET_STANDBY: - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - break; - default : - break; - } -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c deleted file mode 100644 index 579831ccaf..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rcu.c +++ /dev/null @@ -1,1193 +0,0 @@ -/*! - \file gd32f10x_rcu.c - \brief RCU driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_rcu.h" - -/* define clock source */ -#define SEL_IRC8M ((uint16_t)0U) -#define SEL_HXTAL ((uint16_t)1U) -#define SEL_PLL ((uint16_t)2U) - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - rcu_osci_stab_wait(RCU_IRC8M); - - /* reset CFG0 register */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | - RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2); -#elif defined(GD32F10X_CL) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4); -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - RCU_CTL &= ~RCU_CTL_HXTALBPS; -#ifdef GD32F10X_CL - RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); -#endif /* GD32F10X_CL */ - - /* reset INT and CFG1 register */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - RCU_INT = 0x009f0000U; -#elif defined(GD32F10X_CL) - RCU_INT = 0x00ff0000U; - RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | - RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL); -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF : alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF: alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are only available for XD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1,2, ADC2 is not available for CL series): reset ADC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP domain - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP domain reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - reg &= ~RCU_CFG0_SCS; - RCU_CFG0 = (reg | ck_sys); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source - \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source - \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the AHBPSC bits and set according to ck_ahb */ - reg &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (reg | ck_ahb); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB1PSC and set according to ck_apb1 */ - reg &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (reg | ck_apb1); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB2PSC and set according to ck_apb2 */ - reg &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (reg | ck_apb2); -} - -/*! - \brief configure the CK_OUT0 clock source - \param[in] ckout0_src: CK_OUT0 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT0SRC_NONE: no clock selected - \arg RCU_CKOUT0SRC_CKSYS: system clock selected - \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected - \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected - \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected - \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected - \arg RCU_CKOUT0SRC_EXT1: EXT1 selected - \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected - \param[out] none - \retval none -*/ -void rcu_ckout0_config(uint32_t ckout0_src) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the CKOUT0SRC, set according to ckout0_src */ - reg &= ~RCU_CFG0_CKOUT0SEL; - RCU_CFG0 = (reg | ckout0_src); -} - -/*! - \brief configure the main PLL clock - \param[in] pll_src: PLL clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL - \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL_MULx (XD series x = 2..32, CL series x = 2..14, 6.5, 16..32) - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - - /* PLL clock source and multiplication factor configuration */ - reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - reg |= (pll_src | pll_mul); - - RCU_CFG0 = reg; -} - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) -/*! - \brief configure the PREDV0 division factor - \param[in] predv0_div: PREDV0 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0_DIVx, x = 1,2 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - /* reset PREDV0 bit */ - reg &= ~RCU_CFG0_PREDV0; - if(RCU_PREDV0_DIV2 == predv0_div){ - /* set the PREDV0 bit */ - reg |= RCU_CFG0_PREDV0; - } - - RCU_CFG0 = reg; -} -#elif defined(GD32F10X_CL) -/*! - \brief configure the PREDV0 division factor and clock source - \param[in] predv0_source: PREDV0 input clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock - \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock - \param[in] predv0_div: PREDV0 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset PREDV0SEL and PREDV0 bits */ - reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); - /* set the PREDV0SEL and PREDV0 division factor */ - reg |= (predv0_source | predv0_div); - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PREDV1 division factor - \param[in] predv1_div: PREDV1 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV1_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv1_config(uint32_t predv1_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset the PREDV1 bits */ - reg &= ~RCU_CFG1_PREDV1; - /* set the PREDV1 division factor */ - reg |= predv1_div; - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PLL1 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL1_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll1_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL1MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the PLL2 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL2_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll2_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL2MF; - RCU_CFG1 |= pll_mul; -} -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - -/*! - \brief configure the ADC prescaler factor - \param[in] adc_psc: ADC prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 - \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 - \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 - \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 - \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 - \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(uint32_t adc_psc) -{ - uint32_t reg0; - - /* reset the ADCPSC bits */ - reg0 = RCU_CFG0; - reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); - - /* set the ADC prescaler factor */ - switch(adc_psc){ - case RCU_CKADC_CKAPB2_DIV2: - case RCU_CKADC_CKAPB2_DIV4: - case RCU_CKADC_CKAPB2_DIV6: - case RCU_CKADC_CKAPB2_DIV8: - reg0 |= (adc_psc << 14); - break; - - case RCU_CKADC_CKAPB2_DIV12: - case RCU_CKADC_CKAPB2_DIV16: - adc_psc &= ~BIT(2); - reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); - break; - - default: - break; - } - - /* set the register */ - RCU_CFG0 = reg0; -} - -/*! - \brief configure the USBD/USBFS prescaler factor - \param[in] usb_psc: USB prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 - \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 - \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 - \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 - \param[out] none - \retval none -*/ -void rcu_usb_clock_config(uint32_t usb_psc) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* configure the USBD/USBFS prescaler factor */ -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - reg &= ~RCU_CFG0_USBDPSC; -#elif defined(GD32F10X_CL) - reg &= ~RCU_CFG0_USBFSPSC; -#endif /* GD32F10X_MD and GD32F10X_HD and GD32F10X_XD */ - - RCU_CFG0 = (reg | usb_psc); -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - uint32_t reg; - - reg = RCU_BDCTL; - /* reset the RTCSRC bits and set according to rtc_clock_source */ - reg &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL = (reg | rtc_clock_source); -} - -#ifdef GD32F10X_CL -/*! - \brief configure the I2S1 clock source selection - \param[in] i2s_clock_source: I2S1 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock - \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock - \param[out] none - \retval none -*/ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S1SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S1SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief configure the I2S2 clock source selection - \param[in] i2s_clock_source: I2S2 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock - \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock - \param[out] none - \retval none -*/ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S2SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S2SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} -#endif /* GD32F10X_CL */ - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) - \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - - switch(osci){ - /* wait HXTAL stable */ - case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ - reval = SUCCESS; - } - break; - -#ifdef GD32F10X_CL - /* wait PLL1 stable */ - case RCU_PLL1_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ - reval = SUCCESS; - } - break; - /* wait PLL2 stable */ - case RCU_PLL2_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ - reval = SUCCESS; - } - break; -#endif /* GD32F10X_CL */ - - default: - break; - } - - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* enable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg | RCU_CTL_HXTALBPS); - break; - /* enable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F10X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F10X_CL */ - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* disable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); - break; - /* disable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F10X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F10X_CL */ - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) -{ - uint32_t reg; - - reg = RCU_CTL; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - reg &= ~RCU_CTL_IRC8MADJ; - RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws, ck_freq = 0U; - uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp; -#ifdef GD32F10X_CL - uint32_t predv0, predv1, pll1mf; -#endif /* GD32F10X_CL */ - - /* exponent of AHB, APB1 and APB2 clock divider */ - uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if(RCU_PLLSRC_HXTAL == pllsel) { - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - -#if (defined(GD32F10X_MD) || defined(GD32F10X_HD) || defined(GD32F10X_XD)) - predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); - /* PREDV0 input source clock divided by 2 */ - if(RCU_CFG0_PREDV0 == predv0sel){ - ck_src = HXTAL_VALUE/2U; - } -#elif defined(GD32F10X_CL) - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ - predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; -#endif /* GD32F10X_HD and GD32F10X_XD */ - }else{ - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE/2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ - pllmf |= 0x10U; - } - if(pllmf < 15U){ - pllmf += 2U; - }else{ - pllmf += 1U; - } - - cksys_freq = ck_src * pllmf; - - #ifdef GD32F10X_CL - if(15U == pllmf){ - /* PLL source clock multiply by 6.5 */ - cksys_freq = ck_src * 6U + ck_src / 2U; - } - #endif /* GD32F10X_CL */ - - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock){ - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c deleted file mode 100644 index 27fe2cfe70..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c +++ /dev/null @@ -1,277 +0,0 @@ -/*! - \file gd32f10x_rtc.c - \brief RTC driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_rtc.h" - -/* RTC register high / low bits mask */ -#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ -#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ - -/* RTC register high bits offset */ -#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) - -/*! - \brief enter RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_enter(void) -{ - RTC_CTL |= RTC_CTL_CMF; -} - -/*! - \brief exit RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_exit(void) -{ - RTC_CTL &= ~RTC_CTL_CMF; -} - -/*! - \brief set RTC counter value - \param[in] cnt: RTC counter value - \param[out] none - \retval none -*/ -void rtc_counter_set(uint32_t cnt) -{ - rtc_configuration_mode_enter(); - /* set the RTC counter high bits */ - RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); - /* set the RTC counter low bits */ - RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief set RTC prescaler value - \param[in] psc: RTC prescaler value - \param[out] none - \retval none -*/ -void rtc_prescaler_set(uint32_t psc) -{ - rtc_configuration_mode_enter(); - /* set the RTC prescaler high bits */ - RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); - /* set the RTC prescaler low bits */ - RTC_PSCL = (psc & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief wait RTC last write operation finished flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_lwoff_wait(void) -{ - /* loop until LWOFF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ - } -} - -/*! - \brief wait RTC registers synchronized flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_register_sync_wait(void) -{ - /* clear RSYNF flag */ - RTC_CTL &= ~RTC_CTL_RSYNF; - /* loop until RSYNF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ - } -} - -/*! - \brief set RTC alarm value - \param[in] alarm: RTC alarm value - \param[out] none - \retval none -*/ -void rtc_alarm_config(uint32_t alarm) -{ - rtc_configuration_mode_enter(); - /* set the alarm high bits */ - RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); - /* set the alarm low bits */ - RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief get RTC counter value - \param[in] none - \param[out] none - \retval RTC counter value -*/ -uint32_t rtc_counter_get(void) -{ - uint32_t temp = 0x0U; - - temp = RTC_CNTL; - temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); - return temp; -} - -/*! - \brief get RTC divider value - \param[in] none - \param[out] none - \retval RTC divider value -*/ -uint32_t rtc_divider_get(void) -{ - uint32_t temp = 0x00U; - - temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); - temp |= RTC_DIVL; - return temp; -} - -/*! - \brief get RTC flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \arg RTC_FLAG_LWOF: last write operation finished flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear RTC flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - /* clear RTC flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief get RTC interrupt flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_interrupt_flag_get(uint32_t flag) -{ - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear RTC interrupt flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval none -*/ -void rtc_interrupt_flag_clear(uint32_t flag) -{ - /* clear RTC interrupt flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief enable RTC interrupt - \param[in] interrupt: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - RTC_INTEN |= interrupt; -} - -/*! - \brief disable RTC interrupt - \param[in] interrupt: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - RTC_INTEN &= ~interrupt; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c deleted file mode 100644 index d609f282ed..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_sdio.c +++ /dev/null @@ -1,814 +0,0 @@ -/*! - \file gd32f10x_sdio.c - \brief SDIO driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_sdio.h" - -#define DEFAULT_RESET_VALUE 0x00000000U - -/*! - \brief deinitialize the SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_deinit(void) -{ - SDIO_PWRCTL = DEFAULT_RESET_VALUE; - SDIO_CLKCTL = DEFAULT_RESET_VALUE; - SDIO_CMDAGMT = DEFAULT_RESET_VALUE; - SDIO_CMDCTL = DEFAULT_RESET_VALUE; - SDIO_DATATO = DEFAULT_RESET_VALUE; - SDIO_DATALEN = DEFAULT_RESET_VALUE; - SDIO_DATACTL = DEFAULT_RESET_VALUE; - SDIO_INTC = DEFAULT_RESET_VALUE; - SDIO_INTEN = DEFAULT_RESET_VALUE; -} - -/*! - \brief configure the SDIO clock - \param[in] clock_edge: SDIO_CLK clock edge - only one parameter can be selected which is shown as below: - \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK - \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK - \param[in] clock_bypass: clock bypass - only one parameter can be selected which is shown as below: - \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass - \arg SDIO_CLOCKBYPASS_DISABLE: no bypass - \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving - only one parameter can be selected which is shown as below: - \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle - \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on - \param[in] clock_division: clock division, less than 256 - \param[out] none - \retval none -*/ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) -{ - uint32_t clock_config = 0U; - clock_config = SDIO_CLKCTL; - /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ - clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV); - - /* configure the SDIO_CLKCTL according to the parameters */ - clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); - SDIO_CLKCTL = clock_config; -} - -/*! - \brief enable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief disable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief set different SDIO card bus mode - \param[in] bus_mode: SDIO card bus mode - only one parameter can be selected which is shown as below: - \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode - \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode - \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode - \param[out] none - \retval none -*/ -void sdio_bus_mode_set(uint32_t bus_mode) -{ - /* reset the SDIO card bus mode bits and set according to bus_mode */ - SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; - SDIO_CLKCTL |= bus_mode; -} - -/*! - \brief set the SDIO power state - \param[in] power_state: SDIO power state - only one parameter can be selected which is shown as below: - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off - \param[out] none - \retval none -*/ -void sdio_power_state_set(uint32_t power_state) -{ - SDIO_PWRCTL = power_state; -} - -/*! - \brief get the SDIO power state - \param[in] none - \param[out] none - \retval SDIO power state - only one parameter can be selected which is shown as below: - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off -*/ -uint32_t sdio_power_state_get(void) -{ - return SDIO_PWRCTL; -} - -/*! - \brief enable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; -} - -/*! - \brief disable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; -} - -/*! - \brief configure the command and response - \param[in] cmd_index: command index, refer to the related specifications - \param[in] cmd_argument: command argument, refer to the related specifications - \param[in] response_type: response type - only one parameter can be selected which is shown as below: - \arg SDIO_RESPONSETYPE_NO: no response - \arg SDIO_RESPONSETYPE_SHORT: short response - \arg SDIO_RESPONSETYPE_LONG: long response - \param[out] none - \retval none -*/ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) -{ - uint32_t cmd_config = 0U; - /* reset the command index, command argument and response type */ - SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; - SDIO_CMDAGMT = cmd_argument; - cmd_config = SDIO_CMDCTL; - cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); - /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ - cmd_config |= (cmd_index | response_type); - SDIO_CMDCTL = cmd_config; -} - -/*! - \brief set the command state machine wait type - \param[in] wait_type: wait type - only one parameter can be selected which is shown as below: - \arg SDIO_WAITTYPE_NO: not wait interrupt - \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt - \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer - \param[out] none - \retval none -*/ -void sdio_wait_type_set(uint32_t wait_type) -{ - /* reset INTWAIT and WAITDEND */ - SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); - /* set the wait type according to wait_type */ - SDIO_CMDCTL |= wait_type; -} - -/*! - \brief enable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; -} - -/*! - \brief disable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; -} - -/*! - \brief get the last response command index - \param[in] none - \param[out] none - \retval last response command index -*/ -uint8_t sdio_command_index_get(void) -{ - return (uint8_t)SDIO_RSPCMDIDX; -} - -/*! - \brief get the response for the last received command - \param[in] responsex: SDIO response - only one parameter can be selected which is shown as below: - \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] - \arg SDIO_RESPONSE1: card response[95:64] - \arg SDIO_RESPONSE2: card response[63:32] - \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 - \param[out] none - \retval response for the last received command -*/ -uint32_t sdio_response_get(uint32_t responsex) -{ - uint32_t resp_content = 0U; - switch(responsex){ - case SDIO_RESPONSE0: - resp_content = SDIO_RESP0; - break; - case SDIO_RESPONSE1: - resp_content = SDIO_RESP1; - break; - case SDIO_RESPONSE2: - resp_content = SDIO_RESP2; - break; - case SDIO_RESPONSE3: - resp_content = SDIO_RESP3; - break; - default: - break; - } - return resp_content; -} - -/*! - \brief configure the data timeout, data length and data block size - \param[in] data_timeout: data timeout period in card bus clock periods - \param[in] data_length: number of data bytes to be transferred - \param[in] data_blocksize: size of data block for block transfer - only one parameter can be selected which is shown as below: - \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte - \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes - \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes - \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes - \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes - \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes - \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes - \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes - \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes - \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes - \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes - \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes - \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes - \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes - \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes - \param[out] none - \retval none -*/ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) -{ - /* reset data timeout, data length and data block size */ - SDIO_DATATO &= ~SDIO_DATATO_DATATO; - SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; - SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; - /* configure the related parameters of data */ - SDIO_DATATO = data_timeout; - SDIO_DATALEN = data_length; - SDIO_DATACTL |= data_blocksize; -} - -/*! - \brief configure the data transfer mode and direction - \param[in] transfer_mode: mode of data transfer - only one parameter can be selected which is shown as below: - \arg SDIO_TRANSMODE_BLOCK: block transfer - \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer - \param[in] transfer_direction: data transfer direction, read or write - only one parameter can be selected which is shown as below: - \arg SDIO_TRANSDIRECTION_TOCARD: write data to card - \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card - \param[out] none - \retval none -*/ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) -{ - uint32_t data_trans = 0U; - /* reset the data transfer mode, transfer direction and set according to the parameters */ - data_trans = SDIO_DATACTL; - data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); - data_trans |= (transfer_mode | transfer_direction); - SDIO_DATACTL = data_trans; -} - -/*! - \brief enable the DSM(data state machine) for data transfer - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DATAEN; -} - -/*! - \brief disable the DSM(data state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; -} - -/*! - \brief write data(one word) to the transmit FIFO - \param[in] data: 32-bit data write to card - \param[out] none - \retval none -*/ -void sdio_data_write(uint32_t data) -{ - SDIO_FIFO = data; -} - -/*! - \brief read data(one word) from the receive FIFO - \param[in] none - \param[out] none - \retval received data -*/ -uint32_t sdio_data_read(void) -{ - return SDIO_FIFO; -} - -/*! - \brief get the number of remaining data bytes to be transferred to card - \param[in] none - \param[out] none - \retval number of remaining data bytes to be transferred -*/ -uint32_t sdio_data_counter_get(void) -{ - return SDIO_DATACNT; -} - -/*! - \brief get the number of words remaining to be written or read from FIFO - \param[in] none - \param[out] none - \retval remaining number of words -*/ -uint32_t sdio_fifo_counter_get(void) -{ - return SDIO_FIFOCNT; -} - -/*! - \brief enable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DMAEN; -} - -/*! - \brief disable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; -} - -/*! - \brief get the flags state of SDIO - \param[in] flag: flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_CMDRUN: command transmission in progress flag - \arg SDIO_FLAG_TXRUN: data transmission in progress flag - \arg SDIO_FLAG_RXRUN: data reception in progress flag - \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO - \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO - \arg SDIO_FLAG_TFF: transmit FIFO is full flag - \arg SDIO_FLAG_RFF: receive FIFO is full flag - \arg SDIO_FLAG_TFE: transmit FIFO is empty flag - \arg SDIO_FLAG_RFE: receive FIFO is empty flag - \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag - \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_flag_get(uint32_t flag) -{ - FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & flag)){ - temp_flag = SET; - } - return temp_flag; -} - -/*! - \brief clear the pending flags of SDIO - \param[in] flag: flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_flag_clear(uint32_t flag) -{ - SDIO_INTC = flag; -} - -/*! - \brief enable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_enable(uint32_t int_flag) -{ - SDIO_INTEN |= int_flag; -} - -/*! - \brief disable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_disable(uint32_t int_flag) -{ - SDIO_INTEN &= ~int_flag; -} - -/*! - \brief get the interrupt flags state of SDIO - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt - \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt - \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt - \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt - \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt - \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt - \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) -{ - uint32_t state = 0U; - state = SDIO_STAT; - if(state & int_flag){ - state = SDIO_INTEN; - /* check whether the corresponding bit in SDIO_INTEN is set or not */ - if(state & int_flag){ - return SET; - } - } - return RESET; -} - -/*! - \brief clear the interrupt pending flags of SDIO - \param[in] int_flag: interrupt flags state of SDIO - only one parameter can be selected which is shown as below: - \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag - \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_interrupt_flag_clear(uint32_t int_flag) -{ - SDIO_INTC = int_flag; -} - -/*! - \brief enable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWEN; -} - -/*! - \brief disable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; -} - -/*! - \brief enable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; -} - -/*! - \brief disable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; -} - -/*! - \brief set the read wait type(SD I/O only) - \param[in] readwait_type: SD I/O read wait type - only one parameter can be selected which is shown as below: - \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK - \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] - \param[out] none - \retval none -*/ -void sdio_readwait_type_set(uint32_t readwait_type) -{ - if(SDIO_READWAITTYPE_CLK == readwait_type){ - SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; - }else{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; - } -} - -/*! - \brief enable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_IOEN; -} - -/*! - \brief disable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; -} - -/*! - \brief enable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief disable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief enable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; -} - -/*! - \brief disable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; -} - -/*! - \brief enable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_enable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; -} - -/*! - \brief disable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_disable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; -} - -/*! - \brief enable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; -} - -/*! - \brief disable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c deleted file mode 100644 index c0fb893ccc..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_spi.c +++ /dev/null @@ -1,718 +0,0 @@ -/*! - \file gd32f10x_spi.c - \brief SPI driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_spi.h" - -/* SPI/I2S parameter initialization mask */ -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -/* I2S clock source selection, multiplication and division mask */ -#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ -#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ -#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ -#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ - -/* default value and offset */ -#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ -#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ -#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph){ - case SPI0: - /* reset SPI0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 and I2S1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - case SPI2: - /* reset SPI2 and I2S2 */ - rcu_periph_reset_enable(RCU_SPI2RST); - rcu_periph_reset_disable(RCU_SPI2RST); - break; - default : - break; - } -} - -/*! - \brief initialize the parameters of SPI struct with the default values - \param[in] spi_struct: SPI parameter stuct - \param[out] none - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct* spi_struct) -{ - /* set the SPI struct with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; -} - -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval none -*/ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ - uint32_t reg = 0U; - reg = SPI_CTL0(spi_periph); - reg &= SPI_INIT_MASK; - - /* select SPI as master or slave */ - reg |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg |= spi_struct->trans_mode; - /* select SPI frame size */ - reg |= spi_struct->frame_size; - /* select SPI NSS use hardware or software */ - reg |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg |= spi_struct->endian; - /* select SPI polarity and phase */ - reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg |= spi_struct->prescale; - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg; - - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPIx(x=1,2) - \param[in] mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg = 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPIx(x=1,2) - \param[in] audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; - -#ifdef GD32F10X_CL - /* get the I2S clock source */ - if(SPI1 == ((uint32_t)spi_periph)){ - /* I2S1 clock source selection */ - clks = I2S1_CLOCK_SEL; - }else{ - /* I2S2 clock source selection */ - clks = I2S2_CLOCK_SEL; - } - - if(0U != (RCU_CFG1 & clks)){ - /* get RCU PLL2 clock multiplication factor */ - clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); - - if((clks > 5U) && (clks < 15U)){ - /* multiplier is between 8 and 14 */ - clks += 2U; - }else{ - if(15U == clks){ - /* multiplier is 20 */ - clks = 20U; - } - } - - /* get the PREDV1 value */ - i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); - /* calculate I2S clock based on PLL2 and PREDV1 */ - i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); - }else{ - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - } -#else - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); -#endif /* GD32F10X_CL */ - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout){ - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)){ - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \param[out] none - \retval none -*/ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* configure SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= (uint32_t)frame_format; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - SPI_DATA(spi_periph) = (uint32_t)data; -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - return ((uint16_t)SPI_DATA(spi_periph)); -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) -{ - if(SPI_CRC_TX == crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt flag status - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - /*get SPI/I2S interrupt flag status */ - if((0U != reg1) && (0U != reg2)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] flag: SPI/I2S flag status - one or more parameters can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(RESET != (SPI_STAT(spi_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c deleted file mode 100644 index 236eedf9be..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_timer.c +++ /dev/null @@ -1,2004 +0,0 @@ -/*! - \file gd32f10x_timer.c - \brief TIMER driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_timer.h" - -/* TIMER init parameter mask */ -#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ -#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ -#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ - -/*! - \brief deinit a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph){ - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER1: - /* reset TIMER1 */ - rcu_periph_reset_enable(RCU_TIMER1RST); - rcu_periph_reset_disable(RCU_TIMER1RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER3: - /* reset TIMER3 */ - rcu_periph_reset_enable(RCU_TIMER3RST); - rcu_periph_reset_disable(RCU_TIMER3RST); - break; - case TIMER4: - /* reset TIMER4 */ - rcu_periph_reset_enable(RCU_TIMER4RST); - rcu_periph_reset_disable(RCU_TIMER4RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER6: - /* reset TIMER6 */ - rcu_periph_reset_enable(RCU_TIMER6RST); - rcu_periph_reset_disable(RCU_TIMER6RST); - break; - case TIMER7: - /* reset TIMER7 */ - rcu_periph_reset_enable(RCU_TIMER7RST); - rcu_periph_reset_disable(RCU_TIMER7RST); - break; -#ifdef GD32F10X_XD - case TIMER8: - /* reset TIMER8 */ - rcu_periph_reset_enable(RCU_TIMER8RST); - rcu_periph_reset_disable(RCU_TIMER8RST); - break; - case TIMER9: - /* reset TIMER9 */ - rcu_periph_reset_enable(RCU_TIMER9RST); - rcu_periph_reset_disable(RCU_TIMER9RST); - break; - case TIMER10: - /* reset TIMER10 */ - rcu_periph_reset_enable(RCU_TIMER10RST); - rcu_periph_reset_disable(RCU_TIMER10RST); - break; - case TIMER11: - /* reset TIMER11 */ - rcu_periph_reset_enable(RCU_TIMER11RST); - rcu_periph_reset_disable(RCU_TIMER11RST); - break; - case TIMER12: - /* reset TIMER12 */ - rcu_periph_reset_enable(RCU_TIMER12RST); - rcu_periph_reset_disable(RCU_TIMER12RST); - break; - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; -#endif /* GD32F10X_XD */ - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct* initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock,0~65535 - alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP, - TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN - period: counter auto reload value,0~65535 - clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER3 == timer_periph) || - (TIMER4 == timer_periph) || (TIMER7 == timer_periph) || (TIMER8 == timer_periph) || (TIMER9 == timer_periph) || - (TIMER10 == timer_periph) || (TIMER11 == timer_periph) || (TIMER12 == timer_periph) || (TIMER13 == timer_periph)){ - TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); - } - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0..4,7..13) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] prescaler: prescaler value - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] repetition: the counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] autoreload: the counter auto-reload value - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] counter: the counter value - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0..8,11) - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, - or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint32_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: timer DMA source enable - only one parameter can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: timer DMA source disable - only one parameter can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA disable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA disable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request disable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA disable,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: please refer to the following parameters - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: please refer to the following parameters - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4,7..13) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,7) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | - ((uint32_t)(breakpara->ideloffstate)) | - ((uint32_t)(breakpara->deadtime)) | - ((uint32_t)(breakpara->breakpolarity)) | - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode)) | - ((uint32_t)(breakpara->breakstate))) ; -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief enable or disable TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl){ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U); - } - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U); - } - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U); - } - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] pulse: channel output pulse value - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \arg TIMER_CH_3: TIMER channel3 - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, - TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) - icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, - TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, - TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel){ - case TIMER_CH_0: - /* read TIMER channel 0 capture compare register value */ - count_value = TIMER_CH0CV(timer_periph); - break; - case TIMER_CH_1: - /* read TIMER channel 1 capture compare register value */ - count_value = TIMER_CH1CV(timer_periph); - break; - case TIMER_CH_2: - /* read TIMER channel 2 capture compare register value */ - count_value = TIMER_CH2CV(timer_periph); - break; - case TIMER_CH_3: - /* read TIMER channel 3 capture compare register value */ - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ - icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ - icpolarity = TIMER_IC_POLARITY_RISING; - } - /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ - icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel){ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: please refer to the following parameters - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1,TIMERx(x=0..4,7,8,11) - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0..7) - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7)) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) -{ - /* configure the quadrature decoder mode */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - /* configure input capture selection */ - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - /* configure channel input capture polarity */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph,intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] expolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active high or rising edge active - \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source disable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel commutation flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)flag); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c deleted file mode 100644 index 3e6c97ee6f..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_usart.c +++ /dev/null @@ -1,767 +0,0 @@ -/*! - \file gd32f10x_usart.c - \brief USART driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.1, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_usart.h" - -/*! - \brief reset USART/UART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph){ - case USART0: - /* reset USART0 */ - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - /* reset USART1 */ - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - case USART2: - /* reset USART2 */ - rcu_periph_reset_enable(RCU_USART2RST); - rcu_periph_reset_disable(RCU_USART2RST); - break; - case UART3: - /* reset UART3 */ - rcu_periph_reset_enable(RCU_UART3RST); - rcu_periph_reset_disable(RCU_UART3RST); - break; - case UART4: - /* reset UART4 */ - rcu_periph_reset_enable(RCU_UART4RST); - rcu_periph_reset_disable(RCU_UART4RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ - case USART0: - /* get USART0 clock */ - uclk=rcu_clock_freq_get(CK_APB2); - break; - case USART1: - /* get USART1 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case USART2: - /* get USART2 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART3: - /* get UART3 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART4: - /* get UART4 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; - intdiv = udiv & (0x0000fff0U); - fradiv = udiv & (0x0000000fU); - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] paritycfg: configure USART parity - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg ; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - /* configure USART stop bits */ - USART_CTL1(usart_periph) |= stblen; -} -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_TEN; - ctl |= txconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_REN; - ctl |= rxconfig; - /* configure receiver mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_DATA(usart_periph) = USART_DATA_DATA & data; -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); -} - -/*! - \brief configure the address of the USART in wake up by address match mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] addr: address of USART/UART - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); -} - -/*! - \brief receiver in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_RWU; -} - -/*! - \brief receiver in active mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wmethod: two methods be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mask - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief configure lin break frame length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] lblen: lin break frame length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits - \arg USART_LBLEN_11B: 11 bits - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); -} - -/*! - \brief send break frame - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_send_break(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; -} - -/*! - \brief enable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] clen: CK length - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame - \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] gaut: guard time value - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) -{ - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] psc: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) -{ - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] irlp: IrDA low-power or normal - only one parameter can be selected which is shown as below: - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] hardwareflow: enable or disable RTS - only one parameter can be selected which is shown as below: - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_RTSEN; - ctl |= rtsconfig; - /* configure RTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] hardwareflow: enable or disable CTS - only one parameter can be selected which is shown as below: - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_CTSEN; - ctl |= ctsconfig; - /* configure CTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for reception - only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENR; - ctl |= dmacmd; - /* configure DMA reception */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for transmission - only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENT; - ctl |= dmacmd; - /* configure DMA transmission */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief get flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag - \arg USART_FLAG_TBE: transmit data buffer empty - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_IDLEF: IDLE frame detected flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_PERR: parity error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_PERR: parity error interrupt and flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag - \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag - \param[out] none - \retval FlagStatus -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if(flagstatus && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART interrupt flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART interrupt flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_CTS: CTS change flag - \arg USART_INT_FLAG_LBD: LIN break detected flag - \arg USART_INT_FLAG_TC: transmission complete - \arg USART_INT_FLAG_RBNE: read data buffer not empty - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) -{ - USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c b/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c deleted file mode 100644 index 633b50423b..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c +++ /dev/null @@ -1,150 +0,0 @@ -/*! - \file gd32f10x_wwdgt.c - \brief WWDGT driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f10x_wwdgt.h" - -/* write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -/* write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00 - 0x7F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F - \param[in] window: 0x00 - 0x7F - \param[in] prescaler: wwdgt prescaler value - only one parameter can be selected which is shown as below: - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - uint32_t reg_cfg = 0U, reg_ctl = 0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); - reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= CFG_WIN(window); - reg_cfg |= prescaler; - reg_ctl |= CTL_CNT(counter); - - WWDGT_CTL = reg_ctl; - WWDGT_CFG = reg_cfg; -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if(WWDGT_STAT & WWDGT_STAT_EWIF){ - return SET; - } - - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (~WWDGT_STAT_EWIF); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h deleted file mode 100644 index 189be18bae..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_core.h +++ /dev/null @@ -1,217 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device driver core - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usbd_regs.h" - -/* interrupt flag mask which decide what event should be handled by application */ -#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ - | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE) - -#ifdef LPM_ENABLED -#undef IER_MASK - -#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ - | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE | CTL_L1REQIE) -#endif /* LPM_ENABLED */ - -/* USB device endpoint0 max packet size */ -#define USBD_EP0_MAX_SIZE 64U - -#define USBD_CONTRL_STATUS_TX() do \ -{ \ - pbuf_reg->tx_count = 0U; \ - USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \ -} while(0) - -#define USBD_CONTRL_STATUS_RX() do \ -{ \ - USBD_STATUS_OUT_SET(EP0); \ - USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \ -} while(0) - -#define ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT) - -/* USB device endpoint type */ -typedef enum -{ - ENDP_CONTROL = 0, /*!< control endpoint type value */ - ENDP_ISOC, /*!< isochronous endpoint type value */ - ENDP_BULK, /*!< bulk endpoint type value */ - ENDP_INT /*!< interupt endpoint type value */ -}usbd_eptype_enum; - -/* USB device endpoint kind */ -typedef enum -{ - ENDP_SNG_BUF = 0, /*!< single buffer endpoint type value */ - ENDP_DBL_BUF /*!< double buffer endpoint type value */ -}usbd_epkind_enum; - -/* transfer direction */ -typedef enum -{ - USBD_RX = 0, /*!< receive direction type value */ - USBD_TX /*!< transmit direction type value */ -}usbd_dir_enum; - -/* USB device status */ -typedef enum -{ - USBD_UNCONNECTED = 0, /*!< USB device unconnected status */ - USBD_DEFAULT, /*!< USB device default status */ - USBD_ADDRESSED, /*!< USB device addressed status */ - USBD_CONFIGURED, /*!< USB device configured status */ - USBD_SUSPENDED, /*!< USB device suspended status */ - USBD_CONNECTED /*!< USB device connected status */ -}usbd_run_status_enum; - -/* USB device operation state */ -typedef enum -{ - USBD_OK = 0, /*!< USB device ok */ - USBD_BUSY, /*!< USB device busy */ - USBD_FAIL /*!< USB device fail */ -}usbd_status_enum; - -typedef struct -{ - uint16_t tx_addr; /*!< transmission address */ - uint16_t reserved0; - uint16_t tx_count; /*!< transmission count */ - uint16_t reserved1; - uint16_t rx_addr; /*!< reception address */ - uint16_t reserved2; - uint16_t rx_count; /*!< reception count */ - uint16_t reserved3; -}usbd_ep_buf_struct; - -/* USB endpoint structure */ -typedef struct -{ - /* basic parameters */ - uint8_t stall; /*!< endpoint stall status */ - uint32_t maxpacket; /*!< the maxpacket of the endpoint */ - - /* transaction level parameters */ - uint8_t *trs_buf; /*!< transaction buffer address */ - uint32_t trs_len; /*!< transaction buffer length */ - uint32_t trs_count; /*!< transaction data counts */ -}usb_ep_struct; - -/* USB standard device request structure */ -typedef struct -{ - uint8_t bmRequestType; /*!< the property of the request */ - uint8_t bRequest; /*!< the code of the request */ - uint16_t wValue; /*!< the value of the request which used to choose the different request in the same code request */ - uint16_t wIndex; /*!< USB standard device request index */ - uint16_t wLength; /*!< the return datas length that the host wants to get */ -}usb_device_req_struct; - -/* USB core driver struct */ -typedef struct -{ - /* basic parameters */ - uint8_t config_num; /*!< the number of the USB device configuration */ - __IO uint8_t status; /*!< USB device status */ - uint8_t prev_status; /*!< the previous USB device status */ - uint8_t remote_wakeup; /*!< the flag that point out the device whether support the remote wakeup function */ - - /* the parameters which needs in control transfer */ - uint8_t setup_packet[8]; /*!< the buffer used to store the setup packet */ - uint32_t ctl_count; /*!< the datas length of control transfer request */ - - /* device endpoints */ - usb_ep_struct in_ep[EP_COUNT]; /*!< the in direction endpoints */ - usb_ep_struct out_ep[EP_COUNT]; /*!< the out direction endpoints */ - -#ifdef LPM_ENABLED - uint8_t *bos_desc; /*!< BOS descriptor */ -#endif /* LPM_ENABLED */ - - uint8_t *dev_desc; /*!< device descriptor */ - uint8_t *config_desc; /*!< configuration descriptor */ - void* const *strings; /*!< configuration strings */ - - /* device class handler */ - usbd_status_enum (*class_init) (void *pudev, uint8_t config_index); - usbd_status_enum (*class_deinit) (void *pudev, uint8_t config_index); - usbd_status_enum (*class_req_handler) (void *pudev, usb_device_req_struct *req); - usbd_status_enum (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num); -}usbd_core_handle_struct; - -extern uint32_t g_free_buf_addr; -extern usbd_ep_buf_struct *pbuf_reg; - -/* function declarations */ -/* device core register initialization */ -void usbd_core_init (usbd_core_handle_struct *pudev); -/* device core register configure when stop device */ -void usbd_core_deinit (void); - -/* free buffer used from application by toggling the SW_BUF byte */ -void user_buffer_free (uint8_t ep_num, uint8_t dir); - -/* endpoint initialization */ -void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *pep_desc); -/* configure the endpoint when it is disabled */ -void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* set an endpoint to stall status */ -void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* write datas from user fifo to USBRAM */ -void usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); -/* read datas from USBRAM to user fifo */ -void usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); - -/* get the endpoint status */ -uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr); - -/* get the received data length */ -uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h deleted file mode 100644 index a524ea615f..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_int.h +++ /dev/null @@ -1,62 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device interrupt handler header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" -#include "usbd_std.h" -#include "usbd_pwr.h" - -/* constants definitions */ -extern usbd_core_handle_struct usb_device_dev; - -typedef struct -{ - uint8_t (*SOF) (usbd_core_handle_struct *pudev); /*!< SOF ISR callback */ -}usbd_int_cb_struct; - -extern usbd_int_cb_struct *usbd_int_fops; - -/* function declarations */ -/* USB device interrupt service routine */ -void usbd_isr (void); -/* handle USB high priority successful transfer event */ -uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev); - -#endif /* USBD_INT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h deleted file mode 100644 index c0e6a21a19..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_pwr.h +++ /dev/null @@ -1,52 +0,0 @@ -/*! - \file usbd_pwr.h - \brief USB device power management functions prototype - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_PWR_H -#define USBD_PWR_H - -#include "usbd_core.h" - -/* function declarations */ -/* USB wakeup first operation is to wakeup mcu */ -void resume_mcu (void); -/* set USB device to suspend mode */ -void usbd_suspend (void); -/* start to remote wakeup */ -void usbd_remote_wakeup_active (void); - -#endif /* USBD_PWR_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h deleted file mode 100644 index ef3c5c8fcc..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_regs.h +++ /dev/null @@ -1,297 +0,0 @@ -/*! - \file usbd_regs.h - \brief USB device registers - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_REGS_H -#define USBD_REGS_H - -#include "usbd_conf.h" - -/* USB device registers base address */ -#define USBD USBD_BASE -#define USBD_RAM (APB1_BUS_BASE + 0x00006000U) - -/* registers definitions */ -/* common registers */ -#define USBD_CTL (REG32(USBD + 0x40U)) /*!< control register */ -#define USBD_INTF (REG32(USBD + 0x44U)) /*!< interrupt flag register */ -#define USBD_STAT (REG32(USBD + 0x48U)) /*!< status register */ -#define USBD_DADDR (REG32(USBD + 0x4CU)) /*!< device address register */ -#define USBD_BADDR (REG32(USBD + 0x50U)) /*!< buffer address register */ - -/* endpoint control and status register */ -#define USBD_EPxCS(ep_id) (REG32(USBD + (ep_id) * 4U)) /*!< endpoint x control and status register address */ - -/* LPM Registers */ -#define USBD_LPMCS (REG32(USBD + 0x54U)) /*!< USBD LPM control and status register */ - -/* bits definitions */ -/* USBD_CTL */ -#define CTL_STIE BIT(15) /*!< successful transfer interrupt enable mask */ -#define CTL_PMOUIE BIT(14) /*!< packet memory overrun/underrun interrupt enable mask */ -#define CTL_ERRIE BIT(13) /*!< error interrupt enable mask */ -#define CTL_WKUPIE BIT(12) /*!< wakeup interrupt enable mask */ -#define CTL_SPSIE BIT(11) /*!< suspend state interrupt enable mask */ -#define CTL_RSTIE BIT(10) /*!< reset interrupt enable mask */ -#define CTL_SOFIE BIT(9) /*!< start of frame interrupt enable mask */ -#define CTL_ESOFIE BIT(8) /*!< expected start of frame interrupt enable mask */ -#define CTL_L1REQIE BIT(7) /*!< LPM L1 state request interrupt enable */ -#define CTL_L1RSREQ BIT(5) /*!< LPM L1 resume request */ -#define CTL_RSREQ BIT(4) /*!< resume request */ -#define CTL_SETSPS BIT(3) /*!< set suspend state */ -#define CTL_LOWM BIT(2) /*!< low-power mode at suspend state */ -#define CTL_CLOSE BIT(1) /*!< goes to close state */ -#define CTL_SETRST BIT(0) /*!< set USB reset */ - -/* USBD_INTF */ -#define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */ -#define INTF_PMOUIF BIT(14) /*!< packet memory overrun/underrun interrupt flag (clear-only bit) */ -#define INTF_ERRIF BIT(13) /*!< error interrupt flag (clear-only bit) */ -#define INTF_WKUPIF BIT(12) /*!< wakeup interrupt flag (clear-only bit) */ -#define INTF_SPSIF BIT(11) /*!< suspend state interrupt flag (clear-only bit) */ -#define INTF_RSTIF BIT(10) /*!< reset interrupt flag (clear-only bit) */ -#define INTF_SOFIF BIT(9) /*!< start of frame interrupt flag (clear-only bit) */ -#define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */ -#define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */ -#define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */ -#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */ - -/* USBD_STAT */ -#define STAT_RXDP BIT(15) /*!< data plus line status */ -#define STAT_RXDM BIT(14) /*!< data minus line status */ -#define STAT_LOCK BIT(13) /*!< locked the USB */ -#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */ -#define STAT_FCNT BITS(0, 10) /*!< frame number count */ - -/* USBD_DADDR */ -#define DADDR_USBEN BIT(7) /*!< USB module enable */ -#define DADDR_USBDAR BITS(0, 6) /*!< USB device address */ - -/* USBD_EPxCS */ -#define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */ -#define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */ -#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */ -#define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */ -#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */ -#define EPxCS_KCTL BIT(8) /*!< endpoint kind control */ -#define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */ -#define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */ -#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */ -#define EPxCS_ADDR BITS(0, 3) /*!< endpoint address */ - -/* USBD_LPMCS */ -#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */ -#define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */ -#define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */ -#define LPMCS_LPMEN BIT(0) /*!< LPM support enable */ - -/* constants definitions */ -/* endpoint control and status register mask (no toggle fields) */ -#define EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR) - -/* EPxCS_CTL[1:0] endpoint type control */ -#define ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U)) - -#define EP_BULK ENDP_TYPE(0U) /* bulk transfers */ -#define EP_CONTROL ENDP_TYPE(1U) /* control transfers */ -#define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */ -#define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */ -#define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK) - -/* endpoint kind control mask */ -#define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK) - -/* EPxCS_TX_STA[1:0] status for tx transfer */ -#define ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U)) - -#define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */ -#define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */ -#define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */ -#define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */ -#define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK) - -/* EPxCS_RX_STA[1:0] status for rx transfer */ -#define ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U)) - -#define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */ -#define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */ -#define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */ -#define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */ -#define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK) - -/* endpoint receive/transmission counter register bit definitions */ -#define EPRCNT_BLKSIZ BIT(15) /* reception data block size */ -#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */ -#define EPRCNT_CNT BITS(0, 9) /* reception data count */ - -#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */ - -/* interrupt flag clear bits */ -#define CLR_STIF (~INTF_STIF) -#define CLR_PMOUIF (~INTF_PMOUIF) -#define CLR_ERRIF (~INTF_ERRIF) -#define CLR_WKUPIF (~INTF_WKUPIF) -#define CLR_SPSIF (~INTF_SPSIF) -#define CLR_RSTIF (~INTF_RSTIF) -#define CLR_SOFIF (~INTF_SOFIF) -#define CLR_ESOFIF (~INTF_ESOFIF) -#define CLR_L1REQ (~INTF_L1REQ) - -/* endpoint receive/transmission counter register bit offset */ -#define BLKSIZE_OFFSET (0x01U) -#define BLKNUM_OFFSET (0x05U) -#define RXCNT_OFFSET (0x0AU) - -#define TXCNT_OFFSET (0x0AU) - -#define BLKSIZE32_MASK (0x1fU) -#define BLKSIZE2_MASK (0x01U) - -#define BLKSIZE32_OFFSETMASK (0x05U) -#define BLKSIZE2_OFFSETMASK (0x01U) - -/* double buffer endpoint direction */ -typedef enum -{ - DBUF_EP_IN, /* double buffer IN direction */ - DBUF_EP_OUT, /* double buffer OUT direction */ - DBUF_EP_ERR, /* double buffer errer direction */ -}dbuf_ep_dir_enum; - -/* endpoints address */ -/* first bit is direction(0 for rx and 1 for tx) */ -#define EP0_OUT ((uint8_t)0x00) /* out endpoint 0 address */ -#define EP0_IN ((uint8_t)0x80) /* in endpoint 0 address */ -#define EP1_OUT ((uint8_t)0x01) /* out endpoint 1 address */ -#define EP1_IN ((uint8_t)0x81) /* in endpoint 1 address */ -#define EP2_OUT ((uint8_t)0x02) /* out endpoint 2 address */ -#define EP2_IN ((uint8_t)0x82) /* in endpoint 2 address */ -#define EP3_OUT ((uint8_t)0x03) /* out endpoint 3 address */ -#define EP3_IN ((uint8_t)0x83) /* in endpoint 3 address */ -#define EP4_OUT ((uint8_t)0x04) /* out endpoint 4 address */ -#define EP4_IN ((uint8_t)0x84) /* in endpoint 4 address */ -#define EP5_OUT ((uint8_t)0x05) /* out endpoint 5 address */ -#define EP5_IN ((uint8_t)0x85) /* in endpoint 5 address */ -#define EP6_OUT ((uint8_t)0x06) /* out endpoint 6 address */ -#define EP6_IN ((uint8_t)0x86) /* in endpoint 6 address */ -#define EP7_OUT ((uint8_t)0x07) /* out endpoint 7 address */ -#define EP7_IN ((uint8_t)0x87) /* in endpoint 7 address */ - -/* endpoints_identifier */ -#define EP0 ((uint8_t)0) /* endpoint 0 ID */ -#define EP1 ((uint8_t)1) /* endpoint 1 ID */ -#define EP2 ((uint8_t)2) /* endpoint 2 ID */ -#define EP3 ((uint8_t)3) /* endpoint 3 ID */ -#define EP4 ((uint8_t)4) /* endpoint 4 ID */ -#define EP5 ((uint8_t)5) /* endpoint 5 ID */ -#define EP6 ((uint8_t)6) /* endpoint 6 ID */ -#define EP7 ((uint8_t)7) /* endpoint 7 ID */ - -/* USBD operation macros */ - -/* set register value */ -#define USBD_REG_SET(reg, regvalue) ((reg) = (uint16_t)(regvalue)) - -/* get register value */ -#define USBD_REG_GET(reg) ((uint16_t)(reg)) - -#define _EP_ADDR_SET(ep_num, addr) USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr) - -/* tx or rx transfer status setting (bits EPTX_STA[1:0]) */ -#define USBD_ENDP_TX_STATUS_SET(ep_num, state) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPTX_DTGMASK;\ - USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ -} while(0) - -#define USBD_ENDP_RX_STATUS_SET(ep_num, state) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPRX_DTGMASK;\ - USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ -} while(0) - -/* tx or rx transfer status getting (bits EPxCS_RX_STA[1:0]) */ -#define USBD_ENDP_TX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA) -#define USBD_ENDP_RX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA) - -/* rx and tx transfer status setting (bits EPxCS_RX_STA[1:0] & EPxCS_TX_STA[1:0]) */ -#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)(EPRX_DTGMASK | EPxCS_TX_STA) ;\ - USBD_REG_SET(USBD_EPxCS(ep_num), (((_regval) ^ (state_rx)) ^ (state_tx))); \ -} while(0) - -/* set and clear endpoint kind (bit EPxCS_KCTL) */ -#define USBD_ENDP_KIND_SET(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK))) -#define USBD_ENDP_KIND_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK))) - -/* set and clear directly STATUS_OUT state of endpoint */ -#define USBD_STATUS_OUT_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) -#define USBD_STATUS_OUT_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) - -/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */ -#define USBD_ENDP_RX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK)) -#define USBD_ENDP_TX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK)) - -/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ -#define USBD_DTG_RX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) -#define USBD_DTG_TX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) - -/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ -#define USBD_DTG_RX_CLEAR(ep_num) do {\ - if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_DTG) != 0U) {\ - USBD_DTG_RX_TOGGLE(ep_num);\ - } else {\ - }\ -} while(0) - -#define USBD_DTG_TX_CLEAR(ep_num) do {\ - if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_DTG) != 0U) {\ - USBD_DTG_TX_TOGGLE(ep_num);\ - } else {\ - }\ -} while(0) - -/* set and clear directly double buffered feature of endpoint */ -#define USBD_ENDP_DOUBLE_BUF_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) -#define USBD_ENDP_DOUBLE_BUF_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) - -/* toggle SW_BUF bit in the double buffered endpoint */ -#define USBD_SWBUF_TX_TOGGLE(ep_num) USBD_DTG_RX_TOGGLE(ep_num) -#define USBD_SWBUF_RX_TOGGLE(ep_num) USBD_DTG_TX_TOGGLE(ep_num) - -#endif /* USBD_REGS_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h deleted file mode 100644 index 58a85d6cfc..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Include/usbd_std.h +++ /dev/null @@ -1,221 +0,0 @@ -/*! - \file usbd_std.h - \brief USB standard definitions - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usbd_core.h" -#include - -#ifndef NULL -#define NULL 0U -#endif - -/* constants definitions */ -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */ - -#define USBD_LANGID_STR_IDX 0x00U /* language ID string index */ -#define USBD_MFC_STR_IDX 0x01U /* manufacturer string index */ -#define USBD_PRODUCT_STR_IDX 0x02U /* product string index */ -#define USBD_SERIAL_STR_IDX 0x03U /* serial string index */ -#define USBD_CONFIG_STR_IDX 0x04U /* configuration string index */ -#define USBD_INTERFACE_STR_IDX 0x05U /* interface string index */ - -#define USB_STANDARD_REQ 0x00U /* standard request */ -#define USB_CLASS_REQ 0x20U /* device class request */ -#define USB_VENDOR_REQ 0x40U /* vendor request */ -#define USB_REQ_MASK 0x60U /* request type mask */ - -#define USB_REQTYPE_DEVICE 0x00U /* request recipient is device */ -#define USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */ -#define USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */ -#define USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */ - -#define USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */ -#define USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */ -#define USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */ -#define USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */ -#define USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */ -#define USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */ -#define USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */ -#define USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */ -#define USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */ - -#define USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */ -#define USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */ -#define USB_DESCTYPE_STRING 0x03U /* string descriptor type */ -#define USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */ -#define USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */ -#define USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */ - -#define USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */ -#define USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */ - -#define USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */ -#define USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */ -#define USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */ - -#define ENG_LANGID 0x0409U /* english language ID */ -#define CHN_LANGID 0x0804U /* chinese language ID */ - -#define USB_EPTYPE_MASK 0x03U - -#define USB_DEVICE_DESC_SIZE 0x12U - -/* USB device exported macros */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -#pragma pack(1) - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -#pragma pack() - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -#pragma pack(1) - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -/* function declarations */ -/* USB setup transaction processing */ -uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev); -/* USB out transaction processing */ -uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); -/* USB in transaction processing */ -uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); - -/* handle USB standard device request */ -uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle device class request */ -uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle USB vendor request */ -uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -/* decode setup data packet */ -void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle USB enumeration error event */ -void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c deleted file mode 100644 index 4af7b03469..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_core.c +++ /dev/null @@ -1,455 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -uint32_t g_interrupt_mask = 0U; -uint32_t g_free_buf_addr = ENDP_BUF_ADDR; - -usbd_ep_buf_struct *pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM; - -/*! - \brief device core register initialization - \param[in] none - \param[out] none - \retval none -*/ -void usbd_core_init (usbd_core_handle_struct *pudev) -{ - /* disable remote wakeup feature */ - pudev->remote_wakeup = 0U; - - /* just reset the CLOSE bit */ - USBD_REG_SET(USBD_CTL, CTL_SETRST); - - /* may be need wait some time(tSTARTUP) ... */ - - /* clear SETRST bit in USBD_CTL register */ - USBD_REG_SET(USBD_CTL, 0U); - - /* clear all pending interrupts */ - USBD_REG_SET(USBD_INTF, 0U); - - /* set allocation buffer address */ - USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U); - - g_interrupt_mask = IER_MASK; - -#ifdef LPM_ENABLED - /* enable L1REQ interrupt */ - USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN); -#endif /* LPM_ENABLED */ - - /* enable all interrupts mask bits */ - USBD_REG_SET(USBD_CTL, g_interrupt_mask); -} - -/*! - \brief free buffer used from application by toggling the SW_BUF byte - \param[in] ep_num: endpoint identifier (0..7) - \param[in] dir: endpoint direction which can be OUT(0) or IN(1) - \param[out] none - \retval None -*/ -void user_buffer_free (uint8_t ep_num, uint8_t dir) -{ - if (DBUF_EP_OUT == dir) { - USBD_SWBUF_RX_TOGGLE(ep_num); - } else if (DBUF_EP_IN == dir) { - USBD_SWBUF_TX_TOGGLE(ep_num); - } else { - /* no operation */ - } -} - -/*! - \brief device core register configure when stop device - \param[in] none - \param[out] none - \retval none -*/ -void usbd_core_deinit (void) -{ - /* disable all interrupts and set USB reset */ - USBD_REG_SET(USBD_CTL, CTL_SETRST); - - /* clear all interrupt flags */ - USBD_REG_SET(USBD_INTF, 0U); - - /* close device */ - USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to USB core instance - \param[in] buf_kind: kind of buffer - \param[in] pep_desc: pointer to endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usbd_core_handle_struct *pudev, usbd_epkind_enum buf_kind, void *ep_desc) -{ - usb_descriptor_endpoint_struct *desc_ep = (usb_descriptor_endpoint_struct *)ep_desc; - - uint8_t ep_num = desc_ep->bEndpointAddress & 0x0FU; - uint32_t reg_value = 0; - - /* set the endpoint type */ - switch (desc_ep->bmAttributes & USB_EPTYPE_MASK) { - case ENDP_CONTROL: - reg_value = EP_CONTROL; - break; - case ENDP_BULK: - reg_value = EP_BULK; - break; - case ENDP_INT: - reg_value = EP_INTERRUPT; - break; - case ENDP_ISOC: - reg_value = EP_ISO; - break; - default: - break; - } - - USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num); - - reg_value = desc_ep->wMaxPacketSize; - - if (desc_ep->bEndpointAddress >> 7U) { - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - ep->maxpacket = reg_value; - - /* set the endpoint transmit buffer address */ - (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; - - reg_value = (reg_value + 1U) & ~1U; - - g_free_buf_addr += reg_value; - - if (ENDP_DBL_BUF == buf_kind) { - USBD_ENDP_DOUBLE_BUF_SET(ep_num); - - (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; - - g_free_buf_addr += reg_value; - - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); - } else { - /* configure the endpoint status as NAK status */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); - } - } else { - usb_ep_struct *ep = &pudev->out_ep[ep_num]; - - ep->maxpacket = reg_value; - - if (ENDP_DBL_BUF == buf_kind) { - USBD_ENDP_DOUBLE_BUF_SET(ep_num); - - USBD_DTG_TX_TOGGLE(ep_num); - - /* set the endpoint transmit buffer address */ - (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; - - if (reg_value > 62U) { - reg_value = (reg_value + 31U) & ~31U; - (pbuf_reg + ep_num)->tx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); - } else { - reg_value = (reg_value + 1U) & ~1U; - (pbuf_reg + ep_num)->tx_count = (uint16_t)(reg_value << 9U); - } - - g_free_buf_addr += reg_value; - } - - reg_value = desc_ep->wMaxPacketSize; - - /* set the endpoint receive buffer address */ - (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; - - if (reg_value > 62U) { - reg_value = (reg_value + 31U) & ~31U; - (pbuf_reg + ep_num)->rx_count = (uint16_t)(((reg_value << 5U) - 1U) | 0x8000U); - } else { - reg_value = (reg_value + 1U) & ~1U; - (pbuf_reg + ep_num)->rx_count = (uint16_t)(reg_value << 9U); - } - - if (ENDP_DBL_BUF == buf_kind) { - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); - } else { - /* configure the endpoint status as NAK status */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK); - } - } -} - -/*! - \brief configure the endpoint when it is disabled - \param[in] pudev: pointer to USB core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7F; - - if (ep_addr >> 7) { - USBD_DTG_TX_CLEAR(ep_num); - - /* configure the endpoint status as DISABLED */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED); - } else { - USBD_DTG_RX_CLEAR(ep_num); - - /* configure the endpoint status as DISABLED */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); - } -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[in] pbuf: user buffer address pointer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - - ep = &pudev->out_ep[ep_num]; - - /* configure the transaction level parameters */ - ep->trs_buf = pbuf; - ep->trs_len = buf_len; - - /* enable endpoint to receive */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to USB core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[in] pbuf: transmit buffer address pointer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - __IO uint32_t len = 0U; - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - /* configure the transaction level parameters */ - ep->trs_buf = pbuf; - ep->trs_len = buf_len; - ep->trs_count = 0U; - - /* transmit length is more than one packet */ - if (ep->trs_len > ep->maxpacket) { - len = ep->maxpacket; - } else { - len = ep->trs_len; - } - - usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len); - (pbuf_reg + ep_num)->tx_count = (uint16_t)len; - - /* enable endpoint to transmit */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); -} - -/*! - \brief set an endpoint to stall status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep; - - if (ep_addr >> 7U) { - ep = &pudev->in_ep[ep_num]; - - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL); - } else { - ep = &pudev->out_ep[ep_num]; - - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL); - } - - ep->stall = 1U; - - if (0U == ep_num) { - /* control endpoint need to be stalled in two directions */ - USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL); - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep; - - if (ep_addr >> 7U) { - ep = &pudev->in_ep[ep_num]; - - /* clear endpoint data toggle bit */ - USBD_DTG_TX_CLEAR(ep_num); - - /* clear endpoint stall status */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); - } else { - ep = &pudev->out_ep[ep_num]; - - /* clear endpoint data toggle bit */ - USBD_DTG_RX_CLEAR(ep_num); - - /* clear endpoint stall status */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); - } - - ep->stall = 0U; -} - -/*! - \brief get the endpoint status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval endpoint status -*/ -uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7U) { - return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU)); - } else { - return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr); - } -} - -/*! - \brief write datas from user fifo to USBRAM - \param[in] user_fifo: pointer to user fifo - \param[in] usbram_addr: the allocation buffer address of the endpoint - \param[in] bytes: the bytes count of the write datas - \param[out] none - \retval none -*/ -void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) -{ - uint32_t n; - uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); - - for (n = 0U; n < (bytes + 1U) / 2U; n++) { - *write_addr++ = *((__packed uint16_t*)user_fifo); - user_fifo += 2U; - } -} - -/*! - \brief read datas from USBRAM to user fifo - \param[in] user_fifo: pointer to user fifo - \param[in] usbram_addr: the allocation buffer address of the endpoint - \param[in] bytes: the bytes count of the read datas - \param[out] none - \retval none -*/ -void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) -{ - uint32_t n; - uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); - - for (n = 0U; n < (bytes + 1U) / 2U; n++) { - *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++; - user_fifo += 2U; - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to USB core instance - \param[in] ep_num: endpoint identifier which is in (0..7) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - return (uint16_t)pudev->out_ep[ep_num].trs_count; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c deleted file mode 100644 index f9e58fe3d9..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_int.c +++ /dev/null @@ -1,458 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device power interrupt routines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_int.h" - -extern uint32_t g_interrupt_mask; -extern __IO uint8_t g_suspend_enabled; -extern __IO uint8_t g_remote_wakeup_on; -extern __IO uint8_t g_ESOF_count; - -#ifdef LPM_ENABLED -__IO uint32_t L1_remote_wakeup = 0U; -__IO uint32_t L1_resume = 0U; -__IO uint32_t besl = 0U; -#endif /* LPM_ENABLED */ - -static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev); - -/*! - \brief USB interrupt events service routine - \param[in] none - \param[out] none - \retval none -*/ -void usbd_isr (void) -{ - __IO uint16_t interrupt_flag = 0U; - __IO uint16_t ctlr = 0U; - - interrupt_flag = USBD_REG_GET(USBD_INTF); - - if (g_interrupt_mask & INTF_STIF & interrupt_flag) { - /* the endpoint successful transfer interrupt service */ - usbd_intf_lpst(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) { - /* clear wakeup interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF); - - /* USB wakeup interrupt handle */ - usbd_intf_wakeup(&usb_device_dev); - -#ifdef LPM_ENABLED - /* clear L1 remote wakeup flag */ - L1_remote_wakeup = 0; -#endif /* LPM_ENABLED */ - } - - if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) { - if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) { - /* process library core layer suspend routine*/ - usbd_intf_suspend(&usb_device_dev); - - /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF); - } - } - - if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) { - /* clear SOF interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF); - - /* USB SOF interrupt handle */ - usbd_intf_sof(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) { - /* clear ESOF interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF); - - /* USB ESOF interrupt handle */ - usbd_intf_esof(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) { - /* clear reset interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF); - - /* USB reset interrupt handle */ - usbd_intf_reset(&usb_device_dev); - } - -#ifdef LPM_ENABLED - if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) { - /* clear L1 ST bit in LPM INTF */ - USBD_REG_SET(USBD_INTF, CLR_L1REQ); - - /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */ - besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4; - - /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */ - L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8; - - /* process USB device core layer suspend routine */ - /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */ - usbd_intf_suspend(&usb_device_dev); - } -#endif /* LPM_ENABLED */ -} - -/*! - \brief handle USB high priority successful transfer event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_intf_hpst (usbd_core_handle_struct *pudev) -{ - uint8_t ep_num = 0U; - - __IO uint16_t int_status = 0U; - __IO uint16_t ep_value = 0U; - - usb_ep_struct *ep = NULL; - - /* wait till interrupts are not pending */ - while (0U != ((int_status = USBD_INTF) & (uint16_t)INTF_STIF)) { - /* get endpoint number and the value of control and state register */ - ep_num = (uint8_t)(int_status & INTF_EPNUM); - ep_value = USBD_EPxCS(ep_num); - - if (0U == (int_status & INTF_DIR)) { - /* handle the in direction transaction */ - - ep = &(pudev->in_ep[ep_num]); - - if (0U != (ep_value & EPxCS_TX_ST)) { - /* clear successful transmit interrupt flag */ - USBD_ENDP_TX_STAT_CLEAR(ep_num); - - if (ep_value & EPxCS_TX_DTG) { - /* just handle single buffer situation */ - ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; - } - - /* maybe mutiple packets */ - ep->trs_buf += ep->trs_count; - - usbd_in_transaction(pudev, ep_num); - } - } else { - /* handle the out direction transaction */ - - uint16_t count = 0U; - - ep = &(pudev->out_ep[ep_num]); - - if (0U != (ep_value & EPxCS_RX_ST)) { - /* clear successful receive interrupt flag */ - USBD_ENDP_RX_STAT_CLEAR(ep_num); - - if (ep_value & EPxCS_TX_DTG) { - count = (pbuf_reg + ep_num)->tx_count & (uint16_t)EPRCNT_CNT; - - if (0U != count) { - usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, count); - } - } else { - count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; - - if (0U != count) { - usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); - } - } - - user_buffer_free(ep_num, DBUF_EP_OUT); - - /* maybe mutiple packets */ - ep->trs_count += count; - ep->trs_buf += count; - ep->trs_len -= count; - - if ((0U == ep->trs_len) || (count < ep->maxpacket)) { - USBD_ENDP_TX_STATUS_SET(ep_num, EPRX_NAK); - - /* enter data OUT status */ - usbd_out_transaction(pudev, ep_num); - - ep->trs_count = 0U; - } - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB low priority successful transfer event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev) -{ - uint8_t ep_num = 0U; - - __IO uint16_t int_status = 0U; - __IO uint16_t ep_value = 0U; - - usb_ep_struct *ep = NULL; - - /* wait till interrupts are not pending */ - while (0U != ((int_status = USBD_REG_GET(USBD_INTF)) & (uint16_t)INTF_STIF)) { - /* get endpoint number and the value of control and state register */ - ep_num = (uint8_t)(int_status & INTF_EPNUM); - ep_value = USBD_REG_GET(USBD_EPxCS(ep_num)); - - if (0U == (int_status & INTF_DIR)) { - /* handle the in direction transaction */ - - ep = &(pudev->in_ep[ep_num]); - - if (0U != (ep_value & EPxCS_TX_ST)) { - /* clear successful transmit interrupt flag */ - USBD_ENDP_TX_STAT_CLEAR(ep_num); - - /* just handle single buffer situation */ - ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; - - /* maybe mutiple packets */ - ep->trs_buf += ep->trs_count; - - usbd_in_transaction(pudev, ep_num); - } - } else { - /* handle the out direction transaction */ - - uint16_t count = 0U; - - ep = &(pudev->out_ep[ep_num]); - - if (0U != (ep_value & EPxCS_RX_ST)) { - /* clear successful receive interrupt flag */ - USBD_ENDP_RX_STAT_CLEAR(ep_num); - - count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; - - if (0U != count) { - if (0U != (ep_value & EPxCS_SETUP)) { - /* handle setup packet */ - usbd_ep_data_read(&(pudev->setup_packet[0]), pbuf_reg->rx_addr, count); - - /* enter setup status */ - usbd_setup_transaction(pudev); - - return USBD_OK; - } else { - usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); - } - } - - /* maybe mutiple packets */ - ep->trs_count += count; - ep->trs_buf += count; - ep->trs_len -= count; - - if ((0U == ep->trs_len) || (count < ep->maxpacket)) { - /* enter data OUT status */ - usbd_out_transaction(pudev, ep_num); - - ep->trs_count = 0U; - } else { - usbd_ep_rx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); - } - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB SOF event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev) -{ - /* if necessary, user can add code here */ - if (NULL != usbd_int_fops) { - usbd_int_fops->SOF(pudev); - } - - return USBD_OK; -} - -/*! - \brief handle USB expect SOF event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev) -{ - /* control resume time by ESOFs */ - if (g_ESOF_count > 0U) { - g_ESOF_count--; - - if (0U == g_ESOF_count) { - if (1U == g_remote_wakeup_on) { - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_RSREQ); - - g_remote_wakeup_on = 0U; - } else { - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); - - g_ESOF_count = 3U; - g_remote_wakeup_on = 1U; - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB reset event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev) -{ - uint8_t i; - - g_free_buf_addr = ENDP_BUF_ADDR; - - /* configure endpoint 0 buffer */ - pbuf_reg->tx_addr = (uint16_t)g_free_buf_addr; - g_free_buf_addr += USBD_EP0_MAX_SIZE; - - pbuf_reg->rx_addr = (uint16_t)g_free_buf_addr; - g_free_buf_addr += USBD_EP0_MAX_SIZE; - - /* configure endpoint 0 Rx count */ - if (USBD_EP0_MAX_SIZE > 62U) { - pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE << 5U) - 1U) | 0x8000U; - } else { - pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE + 1U) & ~1U) << 9U; - } - - pudev->in_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; - pudev->out_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; - - /* set endpoints address */ - for (i = 0U; i < EP_COUNT; i++) - { - _EP_ADDR_SET(i, i); - } - - /* set device address as default address 0 */ - USBD_REG_SET(USBD_DADDR, DADDR_USBEN); - - /* clear endpoint 0 register */ - USBD_REG_SET(USBD_EPxCS(EP0), USBD_EPxCS(EP0)); - - USBD_REG_SET(USBD_EPxCS(EP0), EP_CONTROL | EPRX_VALID | EPTX_NAK); - - pudev->status = USBD_DEFAULT; - - return USBD_OK; -} - -/*! - \brief handle USB suspend event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev) -{ - /* store the device current status */ - pudev->prev_status = pudev->status; - - /* set device in suspended state */ - pudev->status = USBD_SUSPENDED; - - /* enter USB in suspend and mcu system in low power mode */ - if (g_suspend_enabled) { - usbd_suspend(); - } else { - /* if not possible then resume after xx ms */ - g_ESOF_count = 3U; - } - - return USBD_OK; -} - -/*! - \brief handle USB wakeup event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev) -{ - /* restore the old status */ - pudev->status = pudev->prev_status; - -#ifdef LPM_ENABLED - if ((0U == g_remote_wakeup_on) && (0U == L1_resume)) { - resume_mcu(); - } else if (1U == g_remote_wakeup_on) { - /* no operation */ - } else { - L1_resume = 0U; - } -#else - if (0U == g_remote_wakeup_on) { - resume_mcu(); - } -#endif /* LPM_ENABLED */ - - return USBD_OK; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c deleted file mode 100644 index febdd765f4..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_pwr.c +++ /dev/null @@ -1,159 +0,0 @@ -/*! - \file usbd_pwr.c - \brief USB device power management driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_pwr.h" - -#ifdef USBD_LOWPWR_MODE_ENABLE -static void lowpower_mode_exit (void); -#endif /* USBD_LOWPWR_MODE_ENABLE */ - -__IO uint8_t g_ESOF_count = 0U; -__IO uint8_t g_suspend_enabled = 1U; -__IO uint8_t g_remote_wakeup_on = 0U; - -#ifdef LPM_ENABLED -extern __IO uint32_t L1_resume; -#endif /* LPM_ENABLED */ - -/*! - \brief USB wakeup first operation is to wakeup mcu - \param[in] none - \param[out] none - \retval none -*/ -void resume_mcu (void) -{ - /* clear low_power mode bit in USBD_CTL */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM)); - -#ifdef USBD_LOWPWR_MODE_ENABLE - - /* restore normal operations */ - lowpower_mode_exit(); - -#endif /* USBD_LOWPWR_MODE_ENABLE */ - - /* clear SETSPS bit */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS)); -} - -#ifdef USBD_LOWPWR_MODE_ENABLE - -/*! - \brief restore system clocks and power while exiting suspend mode - \param[in] none - \param[out] none - \retval none -*/ -static void lowpower_mode_exit (void) -{ - /* restore system clock */ - - /* enable HSE */ - rcu_osci_on(RCU_HXTAL); - - /* wait till HSE is ready */ - while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB)); - - /* enable PLL */ - rcu_osci_on(RCU_PLL_CK); - - /* wait till PLL is ready */ - while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB)); - - /* select PLL as system clock source */ - rcu_system_clock_source_config(RCU_CKSYSSRC_PLL); - - /* wait till PLL is used as system clock source */ - while(0x08 != rcu_system_clock_source_get()); - - /* low power sleep on exit disabled */ - system_lowpower_reset(SCB_LPM_DEEPSLEEP); -} - -#endif /* USBD_LOWPWR_MODE_ENABLE */ - -/*! - \brief set USB device to suspend mode - \param[in] none - \param[out] none - \retval none -*/ -void usbd_suspend (void) -{ - /* set usb module to suspend and low-power mode */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM); - -#ifdef USBD_LOWPWR_MODE_ENABLE - - /* check wakeup flag is set */ - if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) { - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } else { - /* clear wakeup interrupt flag */ - USBD_REG_SET(USBD_INTF, CLR_WKUPIF); - - /* clear set_suspend flag */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS); - } - -#endif /* USBD_LOWPWR_MODE_ENABLE */ -} - -/*! - \brief start to remote wakeup - \param[in] none - \param[out] none - \retval none -*/ -void usbd_remote_wakeup_active(void) -{ - resume_mcu(); - -#ifdef LPM_ENABLED - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ); - - L1_resume = 1U; -#else - g_remote_wakeup_on = 1U; - - g_ESOF_count = 15U; - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); -#endif /* LPM_ENABLED */ -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c deleted file mode 100644 index 582d614fac..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbd_driver/Source/usbd_std.c +++ /dev/null @@ -1,868 +0,0 @@ -/*! - \file usbd_std.c - \brief USB device stand routines - \note about USB standard, please refer to the USB2.0 protocol - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_std.h" - -uint8_t g_device_address = 0U; - -/* USB enumeration handle functions */ -static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -#ifdef LPM_ENABLED -static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen); -#endif /* LPM_ENABLED */ - -/* standard device request handler */ -static void (*standard_device_request[])(usbd_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clearfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfiguration, - usbd_setconfiguration, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse (pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, 0x00U); - break; - } - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_num: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - usb_ep_struct *ep = &pudev->out_ep[ep_num]; - - if (0U == ep_num) { - if (0U != pudev->ctl_count) { - if (ep->trs_len > ep->maxpacket) { - /* one data packet has been received, update trs_len */ - ep->trs_len -= ep->maxpacket; - - /* continue to receive remain data */ - usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len); - } else { - if (USBD_CONFIGURED == pudev->status) { - /* device class handle */ - pudev->class_data_handler(pudev, USBD_RX, EP0); - } - - /* enter the control transaction status stage */ - USBD_CONTRL_STATUS_TX(); - - pudev->ctl_count = 0U; - } - } else { - /* clear endpoint status_out status */ - USBD_STATUS_OUT_CLEAR(EP0); - } - } else { - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_RX, ep_num); - } - } - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_num: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - if (0U == ep_num) { - if (0U != pudev->ctl_count) { - if (ep->trs_len > ep->maxpacket) { - /* one data packet has been transmited, update trs_len */ - ep->trs_len -= ep->maxpacket; - - /* continue to transmit remain data */ - usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len); - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { -#ifndef USB_DFU - /* transmit length is maxpacket multiple, so send zero length packet */ - if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) { - usbd_ep_tx (pudev, EP0_IN, NULL, 0U); - - pudev->ctl_count = 0U; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else -#endif /* USB_DFU */ - { - ep->trs_len = 0U; - - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_TX, EP0); - } - - USBD_CONTRL_STATUS_RX(); - - pudev->ctl_count = 0U; - } - } - } else { - if (0U != g_device_address) { - USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address); - g_device_address = 0U; - } - } - } else { - ep->trs_len -= ep->trs_count; - - if (0U == ep->trs_len) { - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_TX, ep_num); - } - } else { - usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); - } - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*standard_device_request[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret; - - switch (pudev->status) { - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* call device class handle function */ - ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - USBD_CONTRL_STATUS_TX(); - } - } else { - usbd_enum_error(pudev, req); - } - break; - default: - usbd_enum_error(pudev, req); - break; - } - - return USBD_OK; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation */ -} - -#ifdef LPM_ENABLED -/*! - \brief get BOS descriptor - \param[in] pudev: pointer to USB device instance - \param[in] pLen: data length pointer - \param[out] none - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen) -{ - *pLen = pudev->bos_desc[2] | ((uint16_t)pudev->bos_desc[3] << 8); - - return pudev->bos_desc; -} - -#endif /* LPM_ENABLED */ - -/*! - \brief get the device descriptor - \param[in] pudev: pointer to USB device instance - \param[in] index: no use - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev_desc[0]; - - return pudev->dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] pudev: pointer to USB device instance - \brief[in] index: no use - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->config_desc[2]; - - return pudev->config_desc; -} - -/*! - \brief get string descriptor - \param[in] pudev: pointer to USB device instance - \param[in] index: string descriptor index - \param[out] pLen: pointer to string length - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr; - uint16_t config_status = 0x0000U; - uint16_t endp_status = 0x0000U; - - switch(req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - -#ifdef USBD_SELF_POWERED - config_status = USB_STATUS_SELF_POWERED; -#endif /* USBD_SELF_POWERED */ - - if (pudev->remote_wakeup) { - config_status |= USB_STATUS_REMOTE_WAKEUP; - } - - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get enndpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - if ((ep_addr & 0x80U) == 0x80U) { - if(pudev->in_ep[ep_addr & 0x7FU].stall) { - endp_status = 0x0001U; - } - } else { - if (pudev->out_ep[ep_addr].stall) { - endp_status = 0x0001U; - } - } - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&endp_status, 2U); - break; - - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - /* clear device remote wakeup feature */ - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->remote_wakeup = 0U; - pudev->class_req_handler(pudev, req); - USBD_CONTRL_STATUS_TX(); - } else if (USB_FEATURE_TEST_MODE == req->wValue) { - /* can not clear test_mode feature */ - usbd_enum_error(pudev, req); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error (pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get endpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - /* clear endpoint halt feature */ - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - } - } - - pudev->class_req_handler(pudev, req); - - USBD_CONTRL_STATUS_TX(); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - /* set device remote wakeup feature */ - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->remote_wakeup = 1U; - - USBD_CONTRL_STATUS_TX(); - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get endpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - /* set endpoint halt feature */ - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - USBD_CONTRL_STATUS_TX(); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if ((0U == req->wIndex) && (0U == req->wLength)) { - g_device_address = (uint8_t)(req->wValue) & 0x7FU; - - if (USBD_CONFIGURED == pudev->status) { - usbd_enum_error(pudev, req); - } else { - USBD_CONTRL_STATUS_TX(); - - if (0U != g_device_address) { - pudev->status = USBD_ADDRESSED; - } else { - pudev->status = USBD_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { - uint8_t *pbuf = NULL; - uint8_t desc_type = (uint8_t)(req->wValue >> 8); - uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; - uint16_t len = 0U; - - if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); - } -#ifdef LPM_ENABLED - else if (USB_DESCTYPE_BOS == desc_type) { - pbuf = usbd_bos_descriptor_get(pudev, &len); - } -#endif /* LPM_ENABLED */ - else { - usbd_enum_error(pudev, req); - } - - if ((0U != len) && (0U != req->wLength)) { - len = MIN(len, req->wLength); - - usbd_ep_tx (pudev, EP0_IN, pbuf, len); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { - if (NULL != pudev->class_req_handler) { - /* get device class special descriptor */ - pudev->class_req_handler(pudev, req); - } - } else { - - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t usbd_default_config = 0U; - - if (req->wLength != 1U) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_ep_tx (pudev, EP0_IN, (uint8_t *)&usbd_default_config, 1U); - break; - case USBD_CONFIGURED: - usbd_ep_tx (pudev, EP0_IN, &pudev->config_num, 1U); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->status) { - case USBD_ADDRESSED: - if (cfgidx){ - pudev->config_num = cfgidx; - pudev->status = USBD_CONFIGURED; - pudev->class_init(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else { - USBD_CONTRL_STATUS_TX(); - } - break; - case USBD_CONFIGURED: - if (0U == cfgidx) { - pudev->status = USBD_ADDRESSED; - pudev->config_num = cfgidx; - pudev->class_deinit(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else if (cfgidx != pudev->config_num) { - /* clear old configuration */ - pudev->class_deinit(pudev, pudev->config_num); - - /* set new configuration */ - pudev->config_num = cfgidx; - pudev->class_init(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else { - USBD_CONTRL_STATUS_TX(); - } - break; - default: - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - if (NULL != pudev->class_req_handler) { - pudev->class_req_handler(pudev, req); - } - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - if (NULL != pudev->class_req_handler) { - pudev->class_req_handler(pudev, req); - } - - USBD_CONTRL_STATUS_TX(); - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *setup_data = pudev->setup_packet; - - req->bmRequestType = *setup_data; - req->bRequest = *(uint8_t *)(setup_data + 1U); - req->wValue = SWAPBYTE (setup_data + 2U); - req->wIndex = SWAPBYTE (setup_data + 4U); - req->wLength = SWAPBYTE (setup_data + 6U); - - pudev->ctl_count = req->wLength; -} - -/*! - \brief handle USB enumeration error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, EP0); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h deleted file mode 100644 index b50f903086..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_core.h +++ /dev/null @@ -1,304 +0,0 @@ -/*! - \file usb_core.h - \brief USB core driver header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_CORE_H -#define USB_CORE_H - -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - -/* constants definitions */ -#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */ -#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ -#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ - -#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT -#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) - -/* USB core status */ -typedef enum -{ - USB_OK = 0, /* USB core OK status */ - USB_FAIL /* USB core fail status */ -}usb_status_enum; - -/* USB host channel status */ -typedef enum -{ - HC_IDLE = 0, /* USB host channel idle status */ - HC_XF, /* USB host channel transfer status */ - HC_HALTED, /* USB host channel halted status */ - HC_NAK, /* USB host channel nak status */ - HC_NYET, /* USB host channel nyet status */ - HC_STALL, /* USB host channel stall status */ - HC_TRACERR, /* USB host channel tracerr status */ - HC_BBERR, /* USB host channel bberr status */ - HC_DTGERR, /* USB host channel dtgerr status */ -}hc_status_enum; - -/* USB URB(USB request block) state */ -typedef enum -{ - URB_IDLE = 0, /* USB URB idle status */ - URB_DONE, /* USB URB done status */ - URB_NOTREADY, /* USB URB not ready status */ - URB_ERROR, /* USB URB error status */ - URB_STALL, /* USB URB stall status */ - URB_PING /* USB URB ping status */ -}urb_state_enum; - -/* USB core configuration */ -typedef struct -{ - uint8_t core_id; /* USB core id */ - uint8_t core_speed; /* USB core speed */ - uint8_t phy_interface; /* USB PHY interface */ - uint8_t host_channel_num; /* USB host channel number */ - uint8_t dev_endp_num; /* USB device endpoint number */ - uint8_t sof_output; /* USB SOF output */ - uint8_t low_power; /* USB low power */ - uint16_t max_packet_size; /* USB max packet size */ - uint16_t max_fifo_size; /* USB fifo size */ -}usb_core_cfgs_struct; - -typedef enum -{ - USBD_OK = 0, /* USB device ok status */ - USBD_BUSY, /* USB device busy status */ - USBD_FAIL, /* USB device fail stauts */ -}usbd_status_enum; - -/* USB control transfer state */ -typedef enum -{ - USB_CTRL_IDLE = 0, /* USB control transfer idle state */ - USB_CTRL_SETUP, /* USB control transfer setup state */ - USB_CTRL_DATA_IN, /* USB control transfer data in state */ - USB_CTRL_DATA_OUT, /* USB control transfer data out state */ - USB_CTRL_STATUS_IN, /* USB control transfer status in state*/ - USB_CTRL_STATUS_OUT, /* USB control transfer status out state */ - USB_CTRL_STALL /* USB control transfer stall state */ -}usbd_control_state_enum; - -/* USB transfer direction */ -typedef enum -{ - USB_RX = 0, /* receive direction type value */ - USB_TX /* transmit direction type value */ -}usb_dir_enum; - -/* USB endpoint in device mode */ -typedef struct -{ - uint8_t endp_type; /* USB endpoint type */ - uint8_t endp_frame; /* USB endpoint frame */ - uint32_t endp_mps; /* USB endpoint max packet size */ - - /* Transaction level variables */ - uint8_t *xfer_buff; /* USB transfer buffer */ - uint32_t xfer_len; /* USB transfer length */ - uint32_t xfer_count; /* USB transfer count */ - - uint32_t dma_addr; /* USBHS can use DMA */ -}usb_ep_struct; - -/* USB device standard request */ -typedef struct -{ - uint8_t bmRequestType; /* USB device request type */ - uint8_t bRequest; /* USB device request */ - uint16_t wValue; /* USB device request value */ - uint16_t wIndex; /* USB device request index */ - uint16_t wLength; /* USB device request length */ -}usb_device_req_struct; - -/* USB core device driver */ -typedef struct -{ - uint8_t config_num; /* USB configuration number */ - __IO uint8_t status; /* USB status */ - uint8_t ctl_status; /* USB control status */ - uint8_t prev_status; /* USB previous status */ - uint8_t connection_status; /* USB connection status */ - uint32_t remote_wakeup; /* USB remote wakeup */ - - /* transfer level variables */ - uint32_t remain_len; /* USB remain length */ - uint32_t sum_len; /* USB sum length */ - uint32_t ctl_len; /* USB control length */ - uint8_t setup_packet[8 * 3]; /* USB setup packet */ - - usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB in endpoint */ - usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB out endpoint */ - - uint8_t *dev_desc; /* device descriptor */ - uint8_t *config_desc; /* configuration descriptor */ - uint8_t* *strings; /* configuration strings */ - - /* device class handler */ - uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ - uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ - uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ - uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */ -}dcd_dev_struct; - -/* USB core host mode channel */ -typedef struct -{ - uint8_t dev_addr; /* device address */ - uint8_t dev_speed; /* device speed */ - uint8_t DPID; /* endpoint transfer data pid */ - uint8_t endp_id; /* endpoint number */ - uint8_t endp_in; /* endpoint in */ - uint8_t endp_type; /* endpoint type */ - uint16_t endp_mps; /* endpoint max pactet size */ - uint16_t info; /* channel information */ - - uint8_t *xfer_buff; /* transfer buffer */ - uint32_t xfer_len; /* transfer length */ - uint32_t xfer_count; /* trasnfer count */ - - uint32_t err_count; /* USB transfer error count */ - - hc_status_enum status; /* channel status */ - urb_state_enum urb_state; /* URB state */ - - uint8_t data_tg_in; /* data in toggle */ - uint8_t data_tg_out; /* data out toggle */ -}usb_hostchannel_struct; - -/* USB core host driver */ -typedef struct -{ - uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */ - uint8_t connect_status; /* device connect status */ - usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */ - void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */ -}hcd_dev_struct; - -#ifdef USE_OTG_MODE - -/* USB core OTG-mode driver */ -typedef struct -{ - uint8_t OTG_State; /* OTG state */ - uint8_t OTG_PrevState; /* OTG previous state */ - uint8_t OTG_Mode; /* OTG mode */ -}otg_dev_struct; - -#endif /* USE_OTG_MODE */ - -/* USB core driver */ -typedef struct -{ - usb_core_cfgs_struct cfg; - -#ifdef USE_DEVICE_MODE - dcd_dev_struct dev; -#endif /* USE_DEVICE_MODE */ - -#ifdef USE_HOST_MODE - hcd_dev_struct host; -#endif /* USE_HOST_MODE */ - -#ifdef USE_OTG_MODE - otg_dev_struct otg; -#endif /* USE_OTG_MODE */ - - void (*udelay) (const uint32_t usec); - void (*mdelay) (const uint32_t msec); -}usb_core_handle_struct; - -/* function declarations */ - -/* global APIs */ -/* initializes the USB controller registers and prepares the core device mode or host mode operation */ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev); -/* initialize core parameters */ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* read a packet from the rx fifo associated with the endpoint */ -void* usb_fifo_read (uint8_t *dest, uint16_t len); -/* write a packet into the tx fifo associated with the endpoint */ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len); -/* flush a tx fifo or all tx fifos */ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); -/* flush the entire rx fifo */ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev); -/* set operation mode (host or device) */ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode); - -/* host APIs */ -#ifdef USE_HOST_MODE - -/* initializes USB core for host mode */ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev); -/* enables the host mode interrupts */ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev); -/* initialize host channel */ -usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num); -/* halt channel */ -usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); -/* prepare host channel for transferring packets */ -usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); -/* reset host port */ -uint32_t usb_port_reset (usb_core_handle_struct *pudev); -/* control the VBUS to power */ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state); -/* stop the USB host and clean up fifos */ -void usb_host_stop (usb_core_handle_struct *pudev); - -#endif /* USE_HOST_MODE */ - -/* device APIs */ -#ifdef USE_DEVICE_MODE - -/* initialize USB core registers for device mode */ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev); -/* configures endpoint 0 to receive setup packets */ -void usb_ep0_startout (usb_core_handle_struct *pudev); -/* active remote wakeup signalling */ -void usb_remotewakeup_active (usb_core_handle_struct *pudev); -/* active USB core clock */ -void usb_clock_ungate (usb_core_handle_struct *pudev); -/* stop the device and clean up fifos */ -void usb_device_stop (usb_core_handle_struct *pudev); - -#endif /* USE_DEVICE_MODE */ - -#endif /* USB_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h deleted file mode 100644 index d9d1fd3c04..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_defines.h +++ /dev/null @@ -1,128 +0,0 @@ -/*! - \file usb_defines.h - \brief USB core defines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_DEFINES_H -#define USB_DEFINES_H - -#include "usb_conf.h" - -/* constants definitions */ -typedef enum -{ - USB_HS_CORE_ID = 0, - USB_FS_CORE_ID = 1 -}usb_core_id_enum; - -typedef enum -{ - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}usb_speed_enum; - -#ifndef NULL - #define NULL (void *)0 /*!< USB null marco value*/ -#endif /* NULL */ - -#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */ -#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */ - -#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */ -#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */ -#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */ -#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */ - -#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */ -#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */ -#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */ -#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */ - -#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */ -#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */ - -#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ -#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ - -#define GRSTATR_RPCKST_IN 2U /* in data packet received */ -#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* in transfer completed (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */ - -#define DEVICE_MODE 0U /* USB core in device mode */ -#define HOST_MODE 1U /* USB core in host mode */ -#define OTG_MODE 2U /* USB core in OTG mode */ - -#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */ -#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */ -#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */ -#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */ -#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */ - -#define RXSTAT_GOUT_NAK 1U /* global out NAK (triggers an interrupt) */ -#define RXSTAT_DATA_UPDT 2U /* out data packet received */ -#define RXSTAT_XFER_COMP 3U /* out transfer completed (triggers an interrupt) */ -#define RXSTAT_SETUP_COMP 4U /* setup transaction completed (triggers an interrupt) */ -#define RXSTAT_SETUP_UPDT 6U /* setup data packet received */ - -#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ -#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ -#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ -#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ - -#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */ -#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */ -#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */ -#define HC_PID_SETUP 3U /* host channel data PID is SETUP */ - -#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */ -#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */ -#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */ - -#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */ -#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */ -#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */ - -#define HCCHAR_CTRL 0U /* control channel type */ -#define HCCHAR_ISOC 1U /* synchronous channel type */ -#define HCCHAR_BULK 2U /* bulk channel type */ -#define HCCHAR_INTR 3U /* interrupt channel type */ - -#endif /* USB_DEFINES_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h deleted file mode 100644 index 2e7d444381..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_regs.h +++ /dev/null @@ -1,596 +0,0 @@ -/*! - \file usb_regs.h - \brief USB FS cell registers definition and handle macros - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_REGS_H -#define USB_REGS_H - -#include "usb_conf.h" - -#define USBFS USBFS_BASE /*!< base address of USBFS registers */ - -/* registers location definitions */ -#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device in endpoint-x (x = 1..3) transfer length registers */ -#define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ -#define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ -#define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ -#define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ -#define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device in endpoint-x control registers */ -#define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device out endpoint-x control registers */ -#define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device in endpoint-x interrupt flag registers */ -#define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device out endpoint-x interrupt flag registers */ -#define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device in endpoint-x transfer length registers */ -#define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device out endpoint-x transfer length registers */ -#define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device in endpoint-x transmit fifo status register */ -#define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ - -/* registers definitions */ -#define USB_GOTGCS REG32(((USBFS) + 0x0000U)) /*!< global OTG control and status register */ -#define USB_GOTGINTF REG32(((USBFS) + 0x0004U)) /*!< global OTG interrupt flag register */ -#define USB_GAHBCS REG32(((USBFS) + 0x0008U)) /*!< global AHB control and status register */ -#define USB_GUSBCS REG32(((USBFS) + 0x000CU)) /*!< global USB control and status register */ -#define USB_GRSTCTL REG32(((USBFS) + 0x0010U)) /*!< global reset control register */ -#define USB_GINTF REG32(((USBFS) + 0x0014U)) /*!< global interrupt flag register */ -#define USB_GINTEN REG32(((USBFS) + 0x0018U)) /*!< global interrupt enable register */ -#define USB_GRSTATR REG32(((USBFS) + 0x001CU)) /*!< global receive status read register */ -#define USB_GRSTATP REG32(((USBFS) + 0x0020U)) /*!< global receive status read and pop register */ -#define USB_GRFLEN REG32(((USBFS) + 0x0024U)) /*!< global receive fifo length register */ -#define USB_HNPTFLEN REG32(((USBFS) + 0x0028U)) /*!< host non-periodic transmit fifo length register */ -#define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U)) /*!< device in endpoint 0 transmit fifo length register */ -#define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU)) /*!< host non-periodic transmint fifo/queue status register */ -#define USB_GCCFG REG32(((USBFS) + 0x0038U)) /*!< global core configuration register */ -#define USB_CID REG32(((USBFS) + 0x003CU)) /*!< core id register */ -#define USB_HPTFLEN REG32(((USBFS) + 0x0100U)) /*!< host periodic transmit fifo length register */ -#define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x))) /*!< device in endpoint transmit fifo length register */ - -#define USB_HCTL REG32(((USBFS) + 0x0400U)) /*!< host control register */ -#define USB_HFT REG32(((USBFS) + 0x0404U)) /*!< host frame interval register */ -#define USB_HFINFR REG32(((USBFS) + 0x0408U)) /*!< host frame information remaining register */ -#define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U)) /*!< host periodic transmit fifo/queue status register */ -#define USB_HACHINT REG32(((USBFS) + 0x0414U)) /*!< host all channels interrupt register */ -#define USB_HACHINTEN REG32(((USBFS) + 0x0418U)) /*!< host all channels interrupt enable register */ -#define USB_HPCS REG32(((USBFS) + 0x0440U)) /*!< host port control and status register */ -#define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ -#define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ -#define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ -#define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ - -#define USB_DCFG REG32(((USBFS) + 0x0800U)) /*!< device configuration register */ -#define USB_DCTL REG32(((USBFS) + 0x0804U)) /*!< device control register */ -#define USB_DSTAT REG32(((USBFS) + 0x0808U)) /*!< device status register */ -#define USB_DIEPINTEN REG32(((USBFS) + 0x0810U)) /*!< device in endpoint common interrupt enable register */ -#define USB_DOEPINTEN REG32(((USBFS) + 0x0814U)) /*!< device out endpoint common interrupt enable register */ -#define USB_DAEPINT REG32(((USBFS) + 0x0818U)) /*!< device all endpoints interrupt register */ -#define USB_DAEPINTEN REG32(((USBFS) + 0x081CU)) /*!< device all endpoints interrupt enable register */ -#define USB_DVBUSDT REG32(((USBFS) + 0x0828U)) /*!< device vbus discharge time register */ -#define USB_DVBUSPT REG32(((USBFS) + 0x082CU)) /*!< device vbus pulsing time register */ -#define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U)) /*!< device in endpoint fifo empty interrupt enable register */ -#define USB_DEP1INT REG32(((USBFS) + 0x0838U)) /*!< device endpoint 1 interrupt register */ -#define USB_DEP1INTEN REG32(((USBFS) + 0x083CU)) /*!< device endpoint 1 interrupt enable register */ -#define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U)) /*!< device in endpoint 1 interrupt enable register */ -#define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U)) /*!< device out endpoint 1 interrupt enable register */ -#define USB_DIEP0CTL REG32(((USBFS) + 0x0900U)) /*!< device in endpoint 0 control register */ -#define USB_DIEP0LEN REG32(((USBFS) + 0x0910U)) /*!< device in endpoint 0 transfer length register */ -#define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U)) /*!< device out endpoint 0 control register */ -#define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U)) /*!< device out endpoint 0 transfer length register */ -#define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x))) /*!< device in endpoint-x control register */ -#define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x))) /*!< device out endpoint-x control register */ -#define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x))) /*!< device in endpoint-x interrupt flag register */ -#define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x))) /*!< device out endpoint-x interrupt flag register */ -#define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x))) /*!< device in endpoint-x transfer length register */ -#define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x))) /*!< device out endpoint-x transfer length register */ -#define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x))) /*!< device in endpoint-x transmit fifo status register */ - -#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U)) /*!< power and clock register */ - -#define USB_FIFO(x) (®32(((USBFS) + LOCATE_FIFO(x)))) /*!< fifo memory */ - -/* global OTG control and status register bits definitions */ -#define GOTGCS_BSV BIT(19) /*!< B-Session valid */ -#define GOTGCS_ASV BIT(18) /*!< A-session valid */ -#define GOTGCS_DI BIT(17) /*!< debounce interval */ -#define GOTGCS_IDPS BIT(16) /*!< id pin status */ -#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ -#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ -#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ -#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ -#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ -#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ - -/* global OTG interrupt flag register bits definitions */ -#define GOTGINTF_DF BIT(19) /*!< debounce finish */ -#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ -#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ -#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ -#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ -#define GOTGINTF_SESEND BIT(2) /*!< session end */ - -/* global AHB control and status register bits definitions */ -#define GAHBCS_PTXFTH BIT(8) /*!< periodic tx fifo threshold */ -#define GAHBCS_TXFTH BIT(7) /*!< tx fifo threshold */ -#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ - -/* global USB control and status register bits definitions */ -#define GUSBCS_FDM BIT(30) /*!< force device mode */ -#define GUSBCS_FHM BIT(29) /*!< force host mode */ -#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ -#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ -#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ -#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ - -/* global reset control register bits definitions */ -#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx fifo number */ -#define GRSTCTL_TXFF BIT(5) /*!< tx fifo flush */ -#define GRSTCTL_RXFF BIT(4) /*!< rx fifo flush */ -#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ -#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ -#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ - -/* global interrupt flag register bits definitions */ -#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ -#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ -#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ -#define GINTF_IDPSC BIT(28) /*!< id pin status change */ -#define GINTF_PTXFEIF BIT(26) /*!< periodic tx fifo empty interrupt flag */ -#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ -#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ -#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ -#define GINTF_ISOONCIF BIT(21) /*!< isochronous out transfer not complete interrupt flag */ -#define GINTF_ISOINCIF BIT(20) /*!< isochronous in transfer not complete interrupt flag */ -#define GINTF_OEPIF BIT(19) /*!< out endpoint interrupt flag */ -#define GINTF_IEPIF BIT(18) /*!< in endpoint interrupt flag */ -#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ -#define GINTF_ISOOPDIF BIT(14) /*!< isochronous out packet dropped interrupt flag */ -#define GINTF_ENUMF BIT(13) /*!< enumeration finished */ -#define GINTF_RST BIT(12) /*!< USB reset */ -#define GINTF_SP BIT(11) /*!< USB suspend */ -#define GINTF_ESP BIT(10) /*!< early suspend */ -#define GINTF_GONAK BIT(7) /*!< global out NAK effective */ -#define GINTF_GNPINAK BIT(6) /*!< global in non-periodic NAK effective */ -#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx fifo empty interrupt flag */ -#define GINTF_RXFNEIF BIT(4) /*!< rx fifo non-empty interrupt flag */ -#define GINTF_SOF BIT(3) /*!< start of frame */ -#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ -#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ -#define GINTF_COPM BIT(0) /*!< current operation mode */ - -/* global interrupt enable register bits definitions */ -#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ -#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ -#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ -#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ -#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx fifo empty interrupt enable */ -#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ -#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ -#define GINTEN_PXNCIE BIT(21) /*!< periodic transfer not complete interrupt enable */ -#define GINTEN_ISOONCIE BIT(21) /*!< isochronous out transfer not complete interrupt enable */ -#define GINTEN_ISOINCIE BIT(20) /*!< isochronous in transfer not complete interrupt enable */ -#define GINTEN_OEPIE BIT(19) /*!< out endpoints interrupt enable */ -#define GINTEN_IEPIE BIT(18) /*!< in endpoints interrupt enable */ -#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ -#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous out packet dropped interrupt enable */ -#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ -#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ -#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ -#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ -#define GINTEN_GONAKIE BIT(7) /*!< global out NAK effective interrupt enable */ -#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic in NAK effective interrupt enable */ -#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic tx fifo empty interrupt enable */ -#define GINTEN_RXFNEIE BIT(4) /*!< receive fifo non-empty interrupt enable */ -#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ -#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ -#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ - -/* global receive status read and pop register bits definitions */ -#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ -#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ - -/* global receive fifo length register bits definitions */ -#define GRFLEN_RXFD BITS(0, 15) /*!< rx fifo depth */ - -/* host non-periodic transmit fifo length register bits definitions */ -#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic tx fifo depth */ -#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic tx RAM start address */ - -/* IN endpoint 0 transmit fifo length register bits definitions */ -#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< in endpoint 0 tx fifo depth */ -#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< in endpoint 0 tx RAM start address */ - -/* host non-periodic transmit fifo/queue status register bits definitions */ -#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic tx request queue */ -#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic tx request queue space */ -#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic tx fifo space */ -#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ -#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* global core configuration register bits definitions */ -#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ -#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ -#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ -#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ -#define GCCFG_PWRON BIT(16) /*!< power on */ - -/* core ID register bits definitions */ -#define CID_CID BITS(0, 31) /*!< core ID */ - -/* host periodic transmit fifo length register bits definitions */ -#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic tx fifo depth */ -#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic tx RAM start address */ - -/* device in endpoint transmit fifo length register bits definitions */ -#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< in endpoint tx fifo x depth */ -#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< in endpoint fifox tx x RAM start address */ - -/* host control register bits definitions */ -#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ - -/* host frame interval register bits definitions */ -#define HFT_FRI BITS(0, 15) /*!< frame interval */ - -/* host frame information remaining register bits definitions */ -#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ -#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ - -/* host periodic transmit fifo/queue status register bits definitions */ -#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic tx request queue */ -#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic tx request queue space */ -#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic tx fifo space */ -#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ -#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ -#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* host all channels interrupt register bits definitions */ -#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ - -/* host all channels interrupt enable register bits definitions */ -#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ - -/* host port control and status register bits definitions */ -#define HPCS_PS BITS(17, 18) /*!< port speed */ -#define HPCS_PP BIT(12) /*!< port power */ -#define HPCS_PLST BITS(10, 11) /*!< port line status */ -#define HPCS_PRST BIT(8) /*!< port reset */ -#define HPCS_PSP BIT(7) /*!< port suspend */ -#define HPCS_PREM BIT(6) /*!< port resume */ -#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ -#define HPCS_PE BIT(2) /*!< port enable */ -#define HPCS_PCD BIT(1) /*!< port connect detected */ -#define HPCS_PCST BIT(0) /*!< port connect status */ - -/* host channel-x control register bits definitions */ -#define HCHCTL_CEN BIT(31) /*!< channel enable */ -#define HCHCTL_CDIS BIT(30) /*!< channel disable */ -#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ -#define HCHCTL_DAR BITS(22, 28) /*!< device address */ -#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ -#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define HCHCTL_LSD BIT(17) /*!< low-speed device */ -#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ -#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ -#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* host channel-x interrupt flag register bits definitions */ -#define HCHINTF_DTER BIT(10) /*!< data toggle error */ -#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ -#define HCHINTF_BBER BIT(8) /*!< babble error */ -#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ -#define HCHINTF_NYET BIT(6) /*!< NYET */ -#define HCHINTF_ACK BIT(5) /*!< ACK */ -#define HCHINTF_NAK BIT(4) /*!< NAK */ -#define HCHINTF_STALL BIT(3) /*!< STALL */ -#define HCHINTF_CH BIT(1) /*!< channel halted */ -#define HCHINTF_TF BIT(0) /*!< transfer finished */ - -/* host channel-x interrupt enable register bits definitions */ -#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ -#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ -#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ -#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ -#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ -#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ -#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ -#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ -#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ -#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ - -/* host channel-x transfer length register bits definitions */ -#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ -#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ -#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device control and status registers */ -/* device configuration registers bits definitions */ -#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ -#define DCFG_DAR BITS(4, 10) /*!< device address */ -#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status out handshake */ -#define DCFG_DS BITS(0, 1) /*!< device speed */ - -/* device control registers bits definitions */ -#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ -#define DCTL_CGONAK BIT(10) /*!< clear global out NAK */ -#define DCTL_SGONAK BIT(9) /*!< set global out NAK */ -#define DCTL_CGINAK BIT(8) /*!< clear global in NAK */ -#define DCTL_SGINAK BIT(7) /*!< set global in NAK */ -#define DCTL_GONS BIT(3) /*!< global out NAK status */ -#define DCTL_GINS BIT(2) /*!< global in NAK status */ -#define DCTL_SD BIT(1) /*!< soft disconnect */ -#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ - -/* device status registers bits definitions */ -#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ -#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ -#define DSTAT_SPST BIT(0) /*!< suspend status */ - -/* device in endpoint common interrupt enable registers bits definitions */ -#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit fifo empty interrupt enable bit */ -#define DIEPINTEN_IEPNEEN BIT(6) /*!< in endpoint NAK effective interrupt enable bit */ -#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint tx fifo underrun interrupt enable bit */ -#define DIEPINTEN_CITOEN BIT(3) /*!< control in timeout interrupt enable bit */ -#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device out endpoint common interrupt enable registers bits definitions */ -#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back setup packets interrupt enable bit */ -#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint rx fifo overrun interrupt enable bit */ -#define DOEPINTEN_STPFEN BIT(3) /*!< fifo phase finished interrupt enable bit */ -#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device all endpoints interrupt registers bits definitions */ -#define DAEPINT_OEPITB BITS(16, 21) /*!< device all out endpoint interrupt bits */ -#define DAEPINT_IEPITB BITS(0, 5) /*!< device all in endpoint interrupt bits */ - -/* device all endpoints interrupt enable registers bits definitions */ -#define DAEPINTEN_OEPIE BITS(16, 21) /*!< out endpoint interrupt enable */ -#define DAEPINTEN_IEPIE BITS(0, 3) /*!< in endpoint interrupt enable */ - -/* device Vbus discharge time registers bits definitions */ -#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ - -/* device Vbus pulsing time registers bits definitions */ -#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ - -/* device IN endpoint FIFO empty interrupt enable register bits definitions */ -#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< in endpoint tx FIFO empty interrupt enable bits */ - -/* device endpoint 0 control register bits definitions */ -#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ - -/* device endpoint x control register bits definitions */ -#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* device in endpoint-x interrupt flag register bits definitions */ -#define DIEPINTF_TXFE BIT(7) /*!< transmit fifo empty */ -#define DIEPINTF_IEPNE BIT(6) /*!< in endpoint NAK effective */ -#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint tx fifo underrun */ -#define DIEPINTF_CITO BIT(3) /*!< control in Timeout interrupt */ -#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DIEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device out endpoint-x interrupt flag register bits definitions */ -#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back setup packets */ -#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint rx fifo overrun */ -#define DOEPINTF_STPF BIT(3) /*!< setup phase finished */ -#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DOEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device in endpoint 0 transfer length register bits definitions */ -#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ -#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device out endpoint 0 transfer length register bits definitions */ -#define DOEP0LEN_STPCNT BITS(29, 30) /*!< setup packet count */ -#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ -#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device out endpoint-x transfer length register bits definitions */ -#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ -#define DOEPLEN_STPCNT BITS(29, 30) /*!< setup packet count */ -#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ -#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device in endpoint-x transmit fifo status register bits definitions */ -#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< in endpoint¡¯s tx fifo space remaining */ - -/* USB power and clock registers bits definition */ -#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ -#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ - -/* register options defines */ -#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ - -#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ -#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ -#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ - -#define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */ - -#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U) /*!< tx fifo half empty */ -#define TXFIFO_EMPTY GAHBCS_TFEL(1U) /*!< tx fifo completely empty */ - -#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ - -#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ -#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ -#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ -#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ -#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ - -#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ - -#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ -#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ -#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ -#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ - -#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ - -#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ -#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ -#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ -#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ - -/* endpoints address */ - -/* first bit is direction(0 for Rx and 1 for Tx) */ -#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */ -#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */ -#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */ -#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */ -#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */ -#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */ -#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */ -#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */ - -/* enable global interrupt */ -#define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN) - -/* disable global interrupt */ -#define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN) - -/* get current operation mode */ -#define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM) - -/* read global interrupt flag */ -#define USB_CORE_INTR_READ(x) \ -do { \ - uint32_t global_intf = USB_GINTF; \ - (x) = global_intf & USB_GINTEN; \ -} while(0) - -/* read global interrupt flag */ -#define USB_DAOEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t out_ep_intb = DAEPINT_OEPITB; \ - (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ -} while(0) - -/* read out endpoint-x interrupt flag */ -#define USB_DOEP_INTR_READ(x, EpID) \ -do { \ - uint32_t out_epintf = USB_DOEPxINTF(EpID); \ - (x) = out_epintf & USB_DOEPINTEN; \ -} while(0) - -/* read all in endpoint interrupt flag */ -#define USB_DAIEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t in_ep_intb = DAEPINT_IEPITB; \ - (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ -} while(0) - - -/* read in endpoint-x interrupt flag */ -#define USB_DIEP_INTR_READ(x, EpID) \ -do { \ - uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \ - uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \ - uint32_t dev_inep_inten = USB_DIEPINTEN; \ - (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \ -} while(0) - -/* generate remote wakup signal */ -#define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP) - -/* no remote wakup signal generate */ -#define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP) - -/* generate soft disconnect */ -#define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD) - -/* no soft disconnect generate */ -#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD) - -/* set device address */ -#define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U) - -/* check whether frame is even */ -#define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U)) - -/* read port status */ -#define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC)) - -/* usb clock initialize */ -#define USB_FSLSCLOCK_INIT(ClockFreq) \ -do { \ - USB_HCTL &= ~HCTL_CLKSEL; \ - USB_HCTL |= ClockFreq; \ -} while(0) - -/* get usb current speed */ -#define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17) - -/* get usb current frame */ -#define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU) - -#endif /* USB_REGS_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h deleted file mode 100644 index d82cb74f85..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usb_std.h +++ /dev/null @@ -1,216 +0,0 @@ -/*! - \file usb_std.h - \brief USB 2.0 standard defines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_STD_H -#define USB_STD_H - -#include "usb_conf.h" - -/* constants definitions */ -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ -#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */ -#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */ -#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */ -#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ - -/* bit 7 of bmRequestType: data phase transfer direction */ -#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */ -#define USB_DIR_OUT 0x00U /*!< USB transfer out direction */ -#define USB_DIR_IN 0x80U /*!< USB transfer in direction */ - -/* bit 6..5 of bmRequestType: request type */ -#define USB_STANDARD_REQ 0x00U /*!< USB standard request */ -#define USB_CLASS_REQ 0x20U /*!< USB class request */ -#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */ -#define USB_REQ_MASK 0x60U /*!< USB request mask */ - -/* bit 4..0 of bmRequestType: recipient type */ -#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */ -#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/ -#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/ -#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/ - -/* bRequest value */ -#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/ -#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/ -#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/ -#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/ -#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/ -#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/ -#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/ -#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/ -#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/ -#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/ -#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/ - -/* descriptor types of usb specifications */ -#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/ -#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/ -#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/ -#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/ -#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/ -#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/ - -#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/ -#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/ - -#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/ -#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/ -#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/ -#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/ - -/* descriptor type and descriptor index */ -/* use the following values when USB host need to get descriptor */ -#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */ -#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */ -#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */ -#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */ -#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */ -#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */ -#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */ -#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */ -#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */ -#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */ - -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -/* supported classes */ -#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/ -#define USB_HID_CLASS 0x03U /*!< USB HID class*/ - -/* interface descriptor field values for hid boot protocol */ -#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/ -#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/ -#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/ - -/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec - standard request with no data stage timeout : 50ms */ -#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ -#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ - -#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \ - + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */ - -#pragma pack(1) - -typedef union -{ - uint8_t data[8]; - - struct _setup_packet_struct - { - uint8_t bmRequestType; /*!< type of request */ - uint8_t bRequest; /*!< request of setup packet */ - uint16_t wValue; /*!< value of setup packet */ - uint16_t wIndex; /*!< index of setup packet */ - uint16_t wLength; /*!< length of setup packet */ - } b; -}usb_setup_union; - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an interrupt or isochrnous type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -#endif /* USB_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h deleted file mode 100644 index 637f1b5654..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_core.h +++ /dev/null @@ -1,81 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device mode core driver header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usb_core.h" -#include "usbd_std.h" - -/* constants definitions */ -/* device status */ -#define USB_STATUS_DEFAULT 1U /* default status */ -#define USB_STATUS_ADDRESSED 2U /* addressed status */ -#define USB_STATUS_CONFIGURED 3U /* configured status */ -#define USB_STATUS_SUSPENDED 4U /* suspended status */ - -/* function declarations */ -/* initailizes the USB device-mode handler stack */ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* endpoint initialization */ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc); -/* endpoint deinitialize */ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); -/* transmit data on the control channel */ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* receive data on the control channel */ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* transmit status on the control channel */ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev); -/* receive status on the control channel */ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev); -/* set an endpoint to stall status */ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* flushes the fifos */ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* get the received data length */ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h deleted file mode 100644 index 89f791d8d8..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_int.h +++ /dev/null @@ -1,57 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device mode interrupt handler header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" - -/* constants definitions */ -typedef struct -{ - uint8_t (*SOF) (usb_core_handle_struct *pudev); -}usbd_int_cb_struct; - -extern usbd_int_cb_struct *usbd_int_fops; - -/* function declaration */ -/* USB device-mode interrupts global service routine handler */ -uint32_t usbd_isr (usb_core_handle_struct *pudev); - -#endif /* USBD_INT_H */ - diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h deleted file mode 100644 index d8ad1a61db..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbd_std.h +++ /dev/null @@ -1,98 +0,0 @@ -/*! - \file usbd_std.h - \brief USB 2.0 standard defines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usb_std.h" -#include "usbd_core.h" -#include "usbd_conf.h" -#include - -/* constants definitions */ -#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/ -#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/ -#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/ -#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/ -#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/ -#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/ - -#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/ -#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/ - -#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/ -#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/ -#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/ - -#define ENG_LANGID 0x0409U /*!< USB english language id*/ -#define CHN_LANGID 0x0804U /*!< USB chinese language id*/ - -#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/ - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/ -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/ - -#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/ - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (uint8_t *)&(struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -/* function declarations */ -/* USB device setup transaction*/ -usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev); -/* USB device out transaction*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device in transaction*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device enum error handle*/ -void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h deleted file mode 100644 index 8137444b50..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_core.h +++ /dev/null @@ -1,310 +0,0 @@ -/*! - \file usbh_core.h - \brief header file for usbh_core.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_CORE_H -#define USBH_CORE_H - -#include "usbh_conf.h" -#include "usb_std.h" -#include "usb_core.h" - -/* constants definitions */ -#define MSC_CLASS 0x08 /*!< the MSC class define */ -#define HID_CLASS 0x03 /*!< the HID class define */ -#define MSC_PROTOCOL 0x50 /*!< the MSC protocal define */ -#define CBI_PROTOCOL 0x01 /*!< the CBI protocal define */ - -#define USBH_DEVICE_ADDRESS_DEFAULT 0U /*!< the default device address define */ -#define USBH_DEVICE_ADDRESS 1U /*!< the device address define */ -#define USBH_MAX_ERROR_COUNT 2U /*!< the max error count define */ - -#define HOST_USER_SELECT_CONFIGURATION 1U /*!< the user select configuration define */ -#define HOST_USER_CLASS_ACTIVE 2U /*!< the user class active define */ -#define HOST_USER_CLASS_SELECTED 3U /*!< the user class selected define */ -#define HOST_USER_CONNECTION 4U /*!< the user connecttion define */ -#define HOST_USER_DISCONNECTION 5U /*!< the user disconnection define */ -#define HOST_USER_UNRECOVERED_ERROR 6U /*!< the user unrecovered error define */ - -#define MAX_USBH_STATE_STACK_DEEP 4 /*!< the max state stack deep define */ -#define MAX_USBH_STATE_TABLE_NUM 10U /*!< the max state table number */ - -#define HOST_FSM_ID 0U /*!< the host state table id */ -#define ENUM_FSM_ID 1U /*!< the enum state table id */ -#define CMD_FSM_ID 2U /*!< the cmd state table id */ -#define CTRL_FSM_ID 3U /*!< the ctrl state table id */ -#define CLASS_REQ_FSM_ID 4U /*!< the class req state table id */ -#define CLASS_FSM_ID 5U /*!< the class state table id */ - -#define UP_STATE 100U /*!< up state define */ -#define GO_TO_UP_STATE_EVENT 100U /*!< go to up state event define */ - -#define HOST_HANDLE_TABLE_SIZE 9U /*!< the host handle table size define */ -/* the enum of host state */ -typedef enum -{ - HOST_IDLE = 0, /* the host idle state definition */ - HOST_DEV_ATTACHED, /* the host device attached state definition */ - HOST_DEV_DETACHED, /* the host device detached state definition */ - HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */ - HOST_ENUMERATION, /* the host enumeration state definition */ - HOST_CLASS_REQUEST, /* the host class request state definition */ - HOST_CLASS, /* the host class state definition */ - HOST_USER_INPUT, /* the host user input state definition */ - HOST_SUSPENDED, /* the host suspended state definition */ - HOST_ERROR /* the host error state definition */ -}host_state_enum; - -/* the enum of host event */ -typedef enum -{ - HOST_EVENT_ATTACHED = 0, /* the host attached event */ - HOST_EVENT_ENUM, /* the host enum event */ - HOST_EVENT_USER_INPUT, /* the host user input event */ - HOST_EVENT_CLASS_REQ, /* the host class request event */ - HOST_EVENT_CLASS, /* the host class event */ - HOST_EVENT_ERROR, /* the host error event */ - HOST_EVENT_DEV_DETACHED, /* the host device detached event */ - HOST_EVENT_IDLE /* the host idle event */ -}host_event_enum; - -/* the enum of enum state */ -typedef enum -{ - ENUM_IDLE = 0, /* the enum idle state definition */ - ENUM_SET_ADDR, /* the enum set address state definition */ - ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */ - ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */ - ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */ - ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */ - ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */ - ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */ - ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */ - ENUM_DEV_CONFIGURED /* the enum device configuration state definition */ -}enum_state_enum; - -/* the enum of ctrl state */ -typedef enum -{ - CTRL_IDLE = 0, /* the ctrl idle state definition */ - CTRL_SETUP, /* the ctrl setup state definition */ - CTRL_DATA, /* the ctrl data state definition */ - CTRL_STATUS, /* the ctrl status state definition */ - CTRL_ERROR, /* the ctrl error state definition */ - CTRL_STALLED, /* the ctrl stalled state definition */ - CTRL_COMPLETE /* the ctrl complete state definition */ -}ctrl_state_enum; - -/* the enum of host status */ -typedef enum -{ - USBH_OK = 0, /* the usbh ok status definition */ - USBH_BUSY, /* the usbh busy status definition */ - USBH_FAIL, /* the usbh fail status definition */ - USBH_NOT_SUPPORTED, /* the usbh not supported status definition */ - USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */ - USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */ - USBH_APPLY_DEINIT /* the usbh apply deinit status definition */ -}usbh_status_enum; - -/* the state of user action */ -typedef enum -{ - USBH_USER_NO_RESP = 0, /* the user no response */ - USBH_USER_RESP_OK = 1, /* the user response ok */ -}usbh_user_status_enum; - -/* control transfer information */ -typedef struct -{ - uint8_t hc_in_num; /* the host in channel number */ - uint8_t hc_out_num; /* the host out channel number */ - uint8_t ep0_size; /* the endpoint 0 max packet size */ - uint8_t error_count; /* the error count */ - uint16_t length; /* the length */ - uint16_t timer; /* the timer */ - uint8_t *buff; /* the buffer */ - usb_setup_union setup; /* the setup packet */ -}usbh_ctrl_struct; - -/* device property */ -typedef struct -{ - uint8_t address; /* the device address */ - uint8_t speed; /* the device speed */ - usb_descriptor_device_struct dev_desc; /* the device descripter */ - usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */ - usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */ - usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */ -}usbh_device_struct; - -/* user callbacks */ -typedef struct -{ - void (*init) (void); /* the user callback init function */ - void (*deinit) (void); /* the user callback deinit function */ - void (*device_connected) (void); /* the user callback device connected function */ - void (*device_reset) (void); /* the user callback device reset function */ - void (*device_disconnected) (void); /* the user callback device disconnected function */ - void (*over_current_detected) (void); /* the user callback over current detected function */ - void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */ - void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */ - void (*device_address_set) (void); /* the user callback set device address function */ - - void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct *ep_desc); - /* the configuration descripter available function */ - - void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */ - void (*product_string) (void *prod_string); /* the user callback product string function */ - void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */ - void (*enumeration_finish) (void); /* the user callback enumeration finish function */ - usbh_user_status_enum (*user_input) (void); /* the user callback user input function */ - int (*user_application) (usb_core_handle_struct *pudev, uint8_t id); - /* the user callback user appliction function */ - void (*device_not_supported) (void); /* the user callback device not supported function */ - void (*unrecovered_error) (void); /* the user callback unrecovered error function */ -}usbh_user_callback_struct; - -/* the backup state struct */ -typedef struct -{ - host_state_enum host_backup_state; /* the host backup state */ - enum_state_enum enum_backup_state; /* the enum backup state */ - ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */ - uint8_t class_req_backup_state; /* the class request backup state */ - uint8_t class_backup_state; /* the class backup state */ -} backup_state_struct; - -/* host information */ -typedef struct -{ - backup_state_struct usbh_backup_state; /* the usbh backup state variable */ - usbh_ctrl_struct control; /* the control struct variable */ - usbh_device_struct device; /* the device struct variable */ - usbh_user_callback_struct *usr_cb; /* the user callback function */ - usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */ - void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */ -}usbh_host_struct; - -/* the action function definition */ -typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate); - -/* the state table struct */ -typedef struct -{ - uint8_t cur_state; /* the current state */ - uint8_t cur_event; /* the current event */ - uint8_t next_state; /* the next state */ - ACT_FUN event_action_fun; /* the event action function entry */ -} state_table_struct; - -/* the state stack struct */ -typedef struct -{ - uint8_t state; /* the state in state stack */ - state_table_struct* table; /* the table in state stack */ - uint8_t table_size; /* the table size in state stack */ -} usbh_state_stack_struct; - -/* the state regist table struct */ -typedef struct -{ - uint8_t id; /* the id of the state table */ - state_table_struct* table; /* the table entry to regist */ - uint8_t table_size; /* the table size to regist */ -} usbh_state_regist_table_struct; - -/* the state handle struct */ -typedef struct -{ - uint8_t usbh_current_state; /* current state */ - uint8_t usbh_current_state_table_size; /* current state table size */ - state_table_struct* usbh_current_state_table; /* current state table */ - - usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */ - int8_t usbh_current_state_stack_top; /* the current state top */ - - usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */ - uint8_t usbh_regist_state_table_num; /* the number of regist state table */ -} usbh_state_handle_struct; - -/* function declarations */ -/* the host core driver function */ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* initialize the host portion of the driver */ -uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* check if the device is connected */ -uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev); -/* this function returns the last URBstate */ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* this function returns the last URBstate */ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* de-initialize host */ -usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate); - -/* the state core driver function */ -/* state core driver init */ -void scd_init (usbh_state_handle_struct* pustate); -/* state core driver table regist */ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size); -/* state core driver begin */ -void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id); -/* state core driver move state */ -void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state); -/* state core driver event handle */ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state); -/* state core driver table push */ -void scd_table_push (usbh_state_handle_struct* pustate); -/* state core driver table pop */ -void scd_table_pop (usbh_state_handle_struct* pustate); -/* the function is only used to state move */ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* the function to the up state */ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -#endif /* USBH_CORE_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h deleted file mode 100644 index b9cf7c5f97..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_ctrl.h +++ /dev/null @@ -1,73 +0,0 @@ -/*! - \file usbh_ctrl.h - \brief header file for usbh_ctrl.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_CTRL_H -#define USBH_CTRL_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -/* constants definitions */ -/* the enum of CTRL event */ -typedef enum -{ - CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ - CTRL_EVENT_SETUP, /* the ctrl setup event */ - CTRL_EVENT_DATA, /* the ctrl data event */ - CTRL_EVENT_STATUS, /* the ctrl status event */ - CTRL_EVENT_COMPLETE, /* the ctrl complete event */ - CTRL_EVENT_ERROR, /* the ctrl error event */ - CTRL_EVENT_STALLED, /* the ctrl stalled event */ -}ctrl_event_enum; - -#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ - -extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; -extern uint8_t ctrl_polling_handle_flag; - -/* function declarations */ -/* the polling function of control transfer state handle */ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* send datas from the host channel */ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); -/* send the setup packet to the device */ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); -/* this function prepare a hc and start a transfer */ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); - -#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h deleted file mode 100644 index d387f15b76..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_hcs.h +++ /dev/null @@ -1,73 +0,0 @@ -/*! - \file usbh_hcs.h - \brief header file for usbh_hcs.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_HCS_H -#define USBH_HCS_H - -#include "usbh_core.h" - -/* constants definitions */ -#define HC_MAX 8U -#define HC_OK 0x0000U -#define HC_USED 0x8000U -#define HC_ERROR 0xFFFFU -#define HC_USED_MASK 0x7FFFU - -/* function declarations */ -/* allocate a new channel for the pipe */ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* free all usb host channel */ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); -/* free the usb host channel */ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); -/* open a channel */ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); -/* modify a channel */ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); - -#endif /* USBH_HCS_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h deleted file mode 100644 index 468ebc37d7..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_int.h +++ /dev/null @@ -1,58 +0,0 @@ -/*! - \file usbh_int.h - \brief USB host mode interrupt handler header file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_INT_H -#define USBH_INT_H - -#include "usb_core.h" - -/* constants definitions */ -typedef struct -{ - uint8_t (*sof) (usb_core_handle_struct *pudev); - uint8_t (*device_connected) (usb_core_handle_struct *pudev); - uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); -}usbh_hcd_int_cb_struct; - -extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; - -/* function declarations */ -/* handle global host interrupt */ -uint32_t usbh_isr (usb_core_handle_struct *pudev); - -#endif /* USBH_INT_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h deleted file mode 100644 index c4bc6cd91b..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Include/usbh_std.h +++ /dev/null @@ -1,101 +0,0 @@ -/*! - \file usbh_std.h - \brief header file for usbh_std.c - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_STD_H -#define USBH_STD_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -/* constants definitions */ -typedef enum -{ - ENUN_EVENT_IDLE = 0, /* the enum idle event */ - ENUM_EVENT_SET_ADDR, /* the enum set address event */ - ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */ - ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */ - ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */ - ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */ - ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */ - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */ - ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */ - ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */ -}enum_event_enum; -/* standard feature selector for clear feature command */ -#define FEATURE_SELECTOR_ENDPOINT 0x00U -#define FEATURE_SELECTOR_DEVICE 0x01U - -#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */ -#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */ - -extern uint8_t usbh_cfg_desc[512]; -extern uint8_t enum_polling_handle_flag; -extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]; - -/* function declarations */ -/* the polling function of enumeration state */ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* get descriptor in usb host enumeration stage */ -void usbh_enum_desc_get (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len); -/* set address in usb host enumeration stage */ -void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address); -/* set configuration in usb host enumeration stage */ -void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx); -/* parse the device descriptor */ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len); -/* parse the configuration descriptor */ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len); -/* parse the interface descriptor */ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf); -/* parse the endpoint descriptor */ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf); -/* parse the string descriptor */ -void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); -/* get the next descriptor header */ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr); - -#endif /* USBH_STD_H */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c deleted file mode 100644 index a2fa307efb..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usb_core.c +++ /dev/null @@ -1,974 +0,0 @@ -/*! - \file usb_core.c - \brief USB core driver which can operate in host-mode and device-mode - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usb_core.h" - -static void usb_commonint_enable (usb_core_handle_struct *pudev); -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev); - -/*! - \brief enable the commmon interrupts which are used in both device and host modes - \param[in] pudev: pointer to selected usb device - \param[out] none - \retval none -*/ -static void usb_commonint_enable (usb_core_handle_struct *pudev) -{ -#ifndef USE_OTG_MODE - - /* clear any pending USB interrupts */ - USB_GOTGINTF = 0xFFFFFFFFU; - -#endif /* USE_OTG_MODE */ - - USB_GINTF = 0xBFFFFFFF; - - /* enable the usb wakeup and suspend interrupts */ - USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; - -#ifdef USE_OTG_MODE - - /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */ - USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; - -#endif /* USE_OTG_MODE */ -} - -/*! - \brief soft reset of the OTG_FS core - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - /* enable core soft reset */ - USB_GRSTCTL |= GRSTCTL_CSRST; - - /* wait for the core to be soft reset */ - do { - if (++count > 200000U) { - break; - } - } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST)); - - /* wait for addtional 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief write a packet into the tx fifo associated with the endpoint - \param[in] src: pointer to source buffer - \param[in] chep_num: channel or endpoint identifier which is in (0..3) - \param[in] len: packet length - \param[out] none - \retval operation status -*/ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len) -{ - uint32_t count32b = 0U, i = 0U; - __IO uint32_t *fifo = USB_FIFO(chep_num); - - count32b = (len + 3U) / 4U; - - for (i = 0U; i < count32b; i++) { - *fifo = *((__packed uint32_t *)src); - - src += 4U; - } - - return USB_OK; -} - -/*! - \brief read a packet from the rx fifo associated with the endpoint - \param[in] dest: pointer to destination buffer - \param[in] len: packet length - \param[out] none - \retval void type pointer -*/ -void *usb_fifo_read (uint8_t *dest, uint16_t len) -{ - uint32_t i = 0U; - uint32_t count32b = (len + 3U) / 4U; - - __IO uint32_t *fifo = USB_FIFO(0U); - - for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = *fifo; - - dest += 4U; - } - - return ((void *)dest); -} - -/*! - \brief initialize core parameters - \param[in] pudev: pointer to usb device - \param[in] core_id: USB core id - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* at startup the core is in FS mode */ - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - /* initialize the core parameters */ - if (USB_FS_CORE_ID == core_id) { - - pudev->cfg.core_id = USB_FS_CORE_ID; - - /* set the host channel numbers */ - pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT; - - /* set the device endpoint numbers */ - pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT; - - /* fifo size is in terms of DWORD */ - pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN; - - /* OTG_FS core use embedded physical layer */ - pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; - - #ifdef USBFS_SOF_OUTPUT_ENABLED - pudev->cfg.sof_output = 1U; - #endif /* USBFS_SOF_OUTPUT_ENABLED */ - - #ifdef USBFS_LOW_PWR_MGMT_SUPPORT - pudev->cfg.low_power = 1U; - #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ - } - - return USB_OK; -} - -/*! - \brief initializes the USB controller registers and - prepares the core device mode or host mode operation - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev) -{ - /* soft reset the core */ - usb_core_reset(pudev); - - /* active the transceiver and enable vbus sensing */ - USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - - /* set tx fifo empty level to half empty mode */ - USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; - -#ifndef VBUS_SENSING_ENABLED - USB_GCCFG |= GCCFG_VBUSIG; -#endif /* VBUS_SENSING_ENABLED */ - - if(pudev->cfg.sof_output){ - USB_GCCFG |= GCCFG_SOFOEN; - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - -#ifdef USE_OTG_MODE - /* enable OTG features */ - USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; - USB_OTG_EnableCommonInt(pudev); - -#endif /* USE_OTG_MODE */ - - return USB_OK; -} - -/*! - \brief flush a tx fifo or all tx fifos - \param[in] pudev: pointer to usb device - \param[in] fifo_num: fifo number which is in (0..3) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num) -{ - uint32_t count = 0U; - - USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; - - /* wait for tx fifo flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_TXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief flush the entire rx fifo - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - USB_GRSTCTL = GRSTCTL_RXFF; - - /* wait for rx fifo flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_RXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief set operation mode (host or device) - \param[in] pudev: pointer to usb device - \param[in] mode: operation mode which need to set - \arg HOST_MODE - \arg DEVICE_MODE - \param[out] none - \retval operation status -*/ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) -{ - if (HOST_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FDM; - USB_GUSBCS |= GUSBCS_FHM; - } else if (DEVICE_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FHM; - USB_GUSBCS |= GUSBCS_FDM; - } else { - /* no operation */ - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(50U); - } - - return USB_OK; -} - -#ifdef USE_HOST_MODE - -/*! - \brief initializes USB core for host mode - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i = 0U; - __IO uint32_t nptxfifolen = 0U; - __IO uint32_t ptxfifolen = 0U; - -#ifdef USE_OTG_MODE - __IO uint32_t otgctl = 0; -#endif /* USE_OTG_MODE */ - - /* restart the PHY clock */ - USB_PWRCLKCTL = 0U; - - /* initialize host configuration register */ - if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ); - } else { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - - /* reset USB port */ - usb_port_reset(pudev); - - /* configure data fifo sizes */ - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set rx fifo size */ - USB_GRFLEN = USBFS_RX_FIFO_SIZE; - - /* set non-periodic tx fifo size and address */ - nptxfifolen &= ~HNPTFLEN_HNPTXRSAR; - nptxfifolen |= USBFS_RX_FIFO_SIZE; - nptxfifolen &= ~HNPTFLEN_HNPTXFD; - nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = nptxfifolen; - - /* set periodic tx fifo size and address */ - ptxfifolen &= ~HPTFLEN_HPTXFSAR; - ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; - ptxfifolen &= ~HPTFLEN_HPTXFD; - ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = ptxfifolen; - } - -#ifdef USE_OTG_MODE - - /* clear host set HNP enable bit in the USB OTG control register */ - otgctl |= GOTGCS_HHNPEN; - USB_GOTGCS &= ~otgctl; - USB_GOTGCS |= 0; - -#endif /* USE_OTG_MODE */ - - /* make sure the fifos are flushed */ - - /* flush all tx fifos in device or host mode */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush the entire rx fifo */ - usb_rxfifo_flush(pudev); - - /* clear all pending host channel interrupts */ - USB_HACHINTEN &= ~HACHINTEN_CINTEN; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxINTEN(i) = 0U; - USB_HCHxINTF(i) = 0xFFFFFFFFU; - } - -#ifndef USE_OTG_MODE - usb_vbus_drive(pudev, 1U); -#endif /* USE_OTG_MODE */ - - usb_hostint_enable(pudev); - - return USB_OK; -} - -/*! - \brief control the VBUS to power - \param[in] pudev: pointer to selected usb host - \param[in] state: VBUS state - \param[out] none - \retval none -*/ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) -{ - __IO uint32_t host_port = 0U; - - /* enable or disable the external charge pump */ - if ((void *)0 != pudev->host.vbus_drive) { - pudev->host.vbus_drive(pudev, state); - } - - /* turn on the host port power. */ - host_port = USB_PORT_READ(); - - if ((0U == (host_port & HPCS_PP)) && (1U == state)) { - host_port |= HPCS_PP; - } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) { - host_port &= ~HPCS_PP; - } else { - /* no operation */ - } - - USB_HPCS = host_port; - - if (NULL != pudev->mdelay) { - pudev->mdelay(200U); - } -} - -/*! - \brief enables the host mode interrupts - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) -{ - uint32_t gintf = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xFFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - gintf |= GINTF_RXFNEIF; - - /* enable host_mode-related interrupts */ - gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF; - - USB_GINTEN &= ~gintf; - USB_GINTEN |= gintf; - - return USB_OK; -} - -/*! - \brief reset host port - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint32_t usb_port_reset (usb_core_handle_struct *pudev) -{ - __IO uint32_t hpcs; - - hpcs = USB_PORT_READ(); - - hpcs |= HPCS_PRST; - - USB_HPCS = hpcs; - - if (NULL != pudev->mdelay) { - pudev->mdelay(100U); - } - - hpcs &= ~HPCS_PRST; - - USB_HPCS = hpcs; - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - return USB_OK; -} - -/*! - \brief initialize host channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t is_low_speed = 0U; - __IO uint32_t chinten = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* clear old interrupt conditions for this host channel */ - USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; - - /* enable channel interrupts required for this transfer */ - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ - | HCHINTEN_DTERIE | HCHINTEN_NAKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } else { - chinten |= HCHINTEN_NYETIE; - } - break; - - case USB_EPTYPE_INTR: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ - | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } - break; - - case USB_EPTYPE_ISOC: - chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; - } - break; - - default: - break; - } - - USB_HCHxINTEN((uint16_t)hc_num) = chinten; - - /* enable the top level host channel interrupt */ - USB_HACHINTEN |= 1U << hc_num; - - /* make sure host channel interrupts are enabled */ - USB_GINTEN |= GINTEN_HCIE; - - /* program the hcctlr register */ - chctl = 0U; - - if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { - is_low_speed = 1U; - } - - chctl |= (uint32_t)puhc->dev_addr << 22U; - chctl |= (uint32_t)puhc->endp_type << 18U; - chctl |= (uint32_t)puhc->endp_id << 11U; - chctl |= (uint32_t)puhc->endp_in << 15U; - chctl |= (uint32_t)is_low_speed << 17U; - chctl |= puhc->endp_mps; - - if (HCCHAR_INTR == puhc->endp_type) { - chctl |= HCHCTL_ODDFRM; - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief prepare host channel for transferring packets - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint16_t dword_len = 0U; - uint16_t packet_num = 0U; - - __IO uint32_t chxlen = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* compute the expected number of packets associated to the transfer */ - if (puhc->xfer_len > 0U) { - packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps; - - if (packet_num > HC_MAX_PACKET_COUNT) { - packet_num = HC_MAX_PACKET_COUNT; - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - } else { - packet_num = 1U; - } - - if (puhc->endp_in) { - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - - /* initialize the host channel length register */ - chxlen &= ~HCHLEN_TLEN; - chxlen |= puhc->xfer_len; - chxlen &= ~HCHLEN_PCNT; - chxlen |= (uint32_t)packet_num << 19U; - chxlen &= ~HCHLEN_DPID; - chxlen |= (uint32_t)(puhc->DPID) << 29U; - USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen; - - /* set host channel enable */ - chctl = USB_HCHxCTL((uint16_t)hc_num); - - if (1U == USB_EVEN_FRAME()) { - chctl |= HCHCTL_ODDFRM; - } else { - chctl &= ~HCHCTL_ODDFRM; - } - - chctl |= HCHCTL_CEN; - chctl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { - dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; - - switch (puhc->endp_type) { - /* non-periodic transfer */ - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - /* check if there is enough space in fifo space */ - if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - /* need to process data in non-periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_NPTXFEIE; - } - break; - - /* periodic transfer */ - case USB_EPTYPE_INTR: - case USB_EPTYPE_ISOC: - /* check if there is enough space in FIFO space */ - if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - /* need to process data in periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_PTXFEIE; - } - break; - - default: - break; - } - - /* write packet into the Tx FIFO. */ - usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); - } - - return USB_OK; -} - -/*! - \brief halt channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t endp_type = 0U; - __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num); - - chctl |= HCHCTL_CEN | HCHCTL_CDIS; - - endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U); - - /* check for space in the request queue to issue the halt. */ - if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { - if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } else { - if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief stop the USB host and clean up fifos - \param[in] none - \param[out] none - \retval none -*/ -void usb_host_stop(usb_core_handle_struct *pudev) -{ - uint32_t i; - - /* disable all host channel interrupt */ - USB_HACHINTEN = 0U; - USB_HACHINT = 0xFFFFFFFFU; - - /* flush out any leftover queued requests */ - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR; - } - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} - -#endif /* USE_HOST_MODE */ - - -#ifdef USE_DEVICE_MODE - -/* USB endpoint Tx FIFO size */ -static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = -{ - (uint16_t)TX0_FIFO_FS_SIZE, - (uint16_t)TX1_FIFO_FS_SIZE, - (uint16_t)TX2_FIFO_FS_SIZE, - (uint16_t)TX3_FIFO_FS_SIZE -}; - -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); - -/*! - \brief initialize USB core registers for device mode - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i, ram_address = 0U; - __IO uint32_t devinep0intf = USB_DIEP0TFLEN; - __IO uint32_t devinepintf = 0U; - - /* restart the phy clock (maybe don't need to...) */ - USB_PWRCLKCTL = 0U; - - /* config periodic frmae interval to default */ - USB_DCFG &= ~DCFG_EOPFT; - USB_DCFG |= FRAME_INTERVAL_80; - - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set full speed PHY */ - USB_DCFG &= ~DCFG_DS; - USB_DCFG |= USB_SPEED_INP_FULL; - - /* set rx fifo size */ - USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 0 tx fifo length and RAM address */ - devinep0intf &= ~DIEP0TFLEN_IEP0TXFD; - devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16; - devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR; - devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE; - - USB_DIEP0TFLEN = devinep0intf; - - ram_address = (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 1 to 3's tx fifo length and RAM address */ - for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { - ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; - - devinepintf &= ~DIEPTFLEN_IEPTXFD; - devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; - devinepintf &= ~DIEPTFLEN_IEPTXRSAR; - devinepintf |= ram_address; - - USB_DIEPxTFLEN(i) = devinepintf; - } - } - - /* make sure all fifos are flushed */ - - /* flush all tx fifos */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush entire rx fifo */ - usb_rxfifo_flush(pudev); - - /* clear all pending device interrupts */ - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - USB_DAEPINTEN = 0U; - - /* configure all in/out endpoints */ - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - if (USB_DIEPxCTL(i) & DEPCTL_EPEN) { - USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DIEPxCTL(i) = 0U; - } - - if (USB_DOEPxCTL(i) & DEPCTL_EPEN) { - USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DOEPxCTL(i) = 0U; - } - - /* set in/out endpoint transfer length to 0 */ - USB_DIEPxLEN(i) = 0U; - USB_DOEPxLEN(i) = 0U; - - /* clear all pending in/out endpoints interrupts */ - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - usb_devint_enable(pudev); - - return USB_OK; -} - -/*! - \brief enable the device mode interrupts - \param[in] pudev: pointer to usb device - \param[out] none - \retval status -*/ -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) -{ - uint32_t int_mask = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xBFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - int_mask = GINTEN_RXFNEIE; - - /* enable device_mode-related interrupts */ - int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ - | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \ - | GINTEN_ISOINCIE; - -#ifdef VBUS_SENSING_ENABLED - int_mask |= GINTEN_SESIE | GINTEN_OTGIE; -#endif /* VBUS_SENSING_ENABLED */ - - USB_GINTEN &= ~int_mask; - USB_GINTEN |= int_mask; - - return USB_OK; -} - -/*! - \brief configures endpoint 0 to receive setup packets - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_ep0_startout(usb_core_handle_struct *pudev) -{ - __IO uint32_t ep0len = 0U; - - /* set out endpoint 0 receive length to 24 bytes */ - ep0len &= ~DOEP0LEN_TLEN; - ep0len |= 8U * 3U; - - /* set out endpoint 0 receive length to 1 packet */ - ep0len &= ~DOEP0LEN_PCNT; - ep0len |= 1U << 19; - - /* set setup packet count to 3 */ - ep0len &= ~DOEP0LEN_STPCNT; - ep0len |= 3U << 29; - - USB_DOEPxLEN(0U) = ep0len; -} - -/*! - \brief active remote wakeup signalling - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_remotewakeup_active(usb_core_handle_struct *pudev) -{ - __IO uint32_t power_clock; - - if (pudev->dev.remote_wakeup) { - if (1U == (USB_DSTAT & DSTAT_SPST)) { - if (pudev->cfg.low_power) { - /* ungate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - - /* active remote wakeup signaling */ - USB_DCTL |= DCTL_RWKUP; - - if (pudev->mdelay != (void *)0) { - pudev->mdelay(5U); - } - - USB_DCTL &= ~DCTL_RWKUP; - } - } -} - -/*! - \brief active USB core clock - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_clock_ungate(usb_core_handle_struct *pudev) -{ - if (pudev->cfg.low_power) { - __IO uint32_t power_clock; - - if (1U == (USB_DSTAT & DSTAT_SPST)) { - /* un-gate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - } -} - -/*! - \brief stop the device and clean up fifos - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_device_stop (usb_core_handle_struct *pudev) -{ - uint32_t i; - - pudev->dev.status = 1U; - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} -#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c deleted file mode 100644 index 366b1bbb3b..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_core.c +++ /dev/null @@ -1,503 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device mode core driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -/*! - \brief initailizes the USB device-mode handler stack - \param[in] pudev: pointer to usb device instance - \param[in] core_id: USB core ID - \param[out] none - \retval none -*/ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* select USB core */ - usb_core_select (pudev, core_id); - - pudev->dev.status = USB_STATUS_DEFAULT; - - /* disable USB global interrupt */ - USB_GLOBAL_INT_DISABLE(); - - /* init the core (common init.) */ - usb_core_init(pudev); - - /* force device mode*/ - usb_mode_set(pudev, DEVICE_MODE); - - /* set device disconnect */ - USB_SOFT_DISCONNECT_ENABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* init device */ - usb_devcore_init(pudev); - - /* set device Connect */ - USB_SOFT_DISCONNECT_DISABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* enable USB global interrupt */ - USB_GLOBAL_INT_ENABLE(); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to usb device instance - \param[in] ep_desc: pointer to usb endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc) -{ - usb_ep_struct *ep; - usb_dir_enum ep_dir; - - uint32_t devepinten = 0U; - uint32_t devepctl = 0U; - - uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU; - uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK; - uint16_t ep_mps = ep_desc->wMaxPacketSize; - - if (ep_desc->bEndpointAddress >> 7U) { - ep = &pudev->dev.in_ep[ep_num]; - - devepinten |= 1U << ep_num; - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - ep_dir = USB_TX; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepinten |= (1U << ep_num) << 16U; - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - ep_dir = USB_RX; - } - - /* if the endpoint is not active, need change the endpoint control register */ - if (!(devepctl & DEPCTL_EPACT)) { - devepctl &= ~DEPCTL_MPL; - devepctl |= ep_mps; - - devepctl &= ~DEPCTL_EPTYPE; - devepctl |= (uint32_t)ep_type << 18U; - - if (USB_TX == ep_dir) { - devepctl &= ~DIEPCTL_TXFNUM; - devepctl |= (uint32_t)ep_num << 22U; - } - - devepctl |= DEPCTL_SD0PID; - devepctl |= DEPCTL_EPACT; - } - - if (USB_TX == ep_dir) { - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else if (USB_RX == ep_dir) { - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* no operation */ - } - - ep->endp_mps = ep_mps; - ep->endp_type = ep_type; - - /* enable the interrupts for this endpoint */ - USB_DAEPINTEN |= devepinten; -} - -/*! - \brief endpoint deinitialize - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint32_t devepinten = 0U; - uint8_t ep_num = ep_addr & 0x7FU; - - if (ep_addr >> 7U) { - devepinten |= 1U << ep_num; - - USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } else { - devepinten |= (1U << ep_num) << 16U; - - USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } - - /* disable the interrupts for this endpoint */ - USB_DAEPINTEN &= ~devepinten; -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - uint32_t devepctl = 0U, devepxlen = 0U; - - ep = &pudev->dev.out_ep[ep_num]; - - /* setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - devepxlen = USB_DOEPxLEN((uint16_t)ep_num); - - devepxlen &= ~DEPLEN_TLEN; - devepxlen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - - if (0U == ep_num) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - /* configure the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; - devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps; - } - } - - USB_DOEPxLEN((uint16_t)ep_num) = devepxlen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (ep->endp_frame) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - __IO uint32_t deveplen = 0U; - - ep = &pudev->dev.in_ep[ep_num]; - - /* setup and start the transfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - deveplen = USB_DIEPxLEN((uint16_t)ep_num); - - /* clear transfer length to 0 */ - deveplen &= ~DEPLEN_TLEN; - - /* clear transfer packet to 0 */ - deveplen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set transfer packet count to 1 */ - deveplen |= 1U << 19U; - } else { - if (0U == ep_num) { - if (ep->xfer_len > ep->endp_mps) { - ep->xfer_len = ep->endp_mps; - } - - deveplen |= 1U << 19U; - } else { - deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; - } - - /* configure the transfer size and packet count as follows: - * xfersize = N * maxpacket + short_packet - * pktcnt = N + (short_packet exist ? 1 : 0) - */ - deveplen |= ep->xfer_len; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - deveplen |= DIEPLEN_MCNT & (1U << 29U); - } - } - - USB_DIEPxLEN((uint16_t)ep_num) = deveplen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - - if (USB_EPTYPE_ISOC != ep->endp_type) { - /* enable the Tx FIFO empty interrupt for this endpoint */ - if (ep->xfer_len > 0U) { - USB_DIEPFEINTEN |= 1U << ep_num; - } - } else { - usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len); - } -} - -/*! - \brief transmit data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - usbd_status_enum ret = USBD_OK; - - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_IN; - - usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len); - - return ret; -} - -/*! - \brief receive data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_OUT; - - usbd_ep_rx (pudev, 0U, pbuf, len); - - return USBD_OK; -} - -/*! - \brief transmit status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_IN; - - usbd_ep_tx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief receive status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_OUT; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief set an endpoint to STALL status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if (ep_addr >> 7U) { - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* set the endpoint disable bit */ - if (devepctl & DEPCTL_EPEN) { - devepctl |= DEPCTL_EPD; - } - - /* set the endpoint stall bit */ - devepctl |= DEPCTL_STALL; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* set the endpoint stall bit */ - USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL; - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if(ep_addr >> 7U){ - ep = &pudev->dev.in_ep[ep_num]; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* clear the in endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - /* clear the out endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } -} - -/*! - \brief flushes the fifos - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7U) { - usb_txfifo_flush(pudev, ep_addr & 0x7FU); - } else { - usb_rxfifo_flush(pudev); - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to usb device instance - \param[in] ep_num: endpoint identifier which is in (0..3) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num) -{ - return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c deleted file mode 100644 index 668ef35cd7..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_int.c +++ /dev/null @@ -1,663 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device mode interrupt routines - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_int.h" -#include "usbd_std.h" - -/* interrupt handlers */ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev); - -static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num); - -#ifdef VBUS_SENSING_ENABLED - - static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); - static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); - -#endif /* VBUS_SENSING_ENABLED */ - -static usb_speed_enum USB_SPEED[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW -}; - -static const uint8_t EP0_MAXLEN[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 -}; - -/*! - \brief USB device-mode interrupts global service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbd_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN; - - /* ensure the core is in device mode */ - if (DEVICE_MODE == USB_CURRENT_MODE_GET()) { - int_status = gintf & ginten; - - /* there are no interrupts, avoid spurious interrupt */ - if (!int_status) { - return 0U; - } - - /* OUT endpoints interrupts */ - if (int_status & GINTF_OEPIF) { - retval |= usbd_intf_outep(pudev); - } - - /* IN endpoints interrupts */ - if (int_status & GINTF_IEPIF) { - retval |= usbd_intf_inep(pudev); - } - - /* mode mismatch interrupt */ - if (int_status & GINTF_MFIF) { - /* clear interrupt */ - USB_GINTF = GINTF_MFIF; - } - - /* early suspend interrupt */ - if (int_status & GINTF_ESP) { - retval |= usbd_intf_earlysuspend(pudev); - } - - /* suspend interrupt */ - if (int_status & GINTF_SP) { - retval |= usbd_intf_suspend(pudev); - } - - /* wakeup interrupt */ - if (int_status & GINTF_WKUPIF) { - retval |= usbd_intf_resume(pudev); - } - - /* start of frame interrupt */ - if (int_status & GINTF_SOF) { - retval |= usbd_intf_sof(pudev); - } - - /* reveive fifo not empty interrupt */ - if (int_status & GINTF_RXFNEIF) { - retval |= usbd_intf_rxfifo(pudev); - } - - /* USB reset interrupt */ - if (int_status & GINTF_RST) { - retval |= usbd_intf_reset(pudev); - } - - /* enumeration has been finished interrupt */ - if (int_status & GINTF_ENUMF) { - retval |= usbd_intf_enumfinish(pudev); - } - - /* incomplete synchronization in transfer interrupt*/ - if (int_status & GINTF_ISOINCIF) { - retval |= usbd_intf_isoinincomplete(pudev); - } - - /* incomplete synchronization out transfer interrupt*/ - if (int_status & GINTF_ISOONCIF) { - retval |= usbd_intf_isooutincomplete(pudev); - } - -#ifdef VBUS_SENSING_ENABLED - - /* session request interrupt */ - if (int_status & GINTF_SESIF) { - retval |= usbd_intf_sessionrequest(pudev); - } - - /* OTG mode interrupt */ - if (int_status & GINTF_OTGIF) { - retval |= usbd_intf_otg(pudev); - } -#endif /* VBUS_SENSING_ENABLED */ - } - - return retval; -} - -/*! - \brief indicates that an OUT endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t out_endp_intr = 0U; - - /* read in the device interrupt bits */ - USB_DAOEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num); - - /* transfer complete interrupt */ - if (out_endp_intr & DOEPINTF_TF) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; - - /* data receive is completed */ - usbd_out_transaction(pudev, endp_num); - } - - /* endpoint disable interrupt */ - if (out_endp_intr & DOEPINTF_EPDIS) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS; - } - - /* setup phase finished interrupt (just for control endpoints) */ - if (out_endp_intr & DOEPINTF_STPF) { - /* setup phase is completed */ - usbd_setup_transaction(pudev); - - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF; - } - - /* back to back setup packets received */ - if (out_endp_intr & DOEPINTF_BTBSTP) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that an in endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t in_endp_intr = 0U; - - /* get all in endpoints which have interrupts */ - USB_DAIEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num); - - if (in_endp_intr & DIEPINTF_TF) { - /* disable the fifo empty interrupt for the endpoint */ - USB_DIEPFEINTEN &= ~(0x1U << endp_num); - - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF; - - /* data transmittion is completed */ - usbd_in_transaction(pudev, endp_num); - } - - if (in_endp_intr & DIEPINTF_CITO) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO; - } - - if (in_endp_intr & DIEPINTF_IEPNE) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE; - } - - if (in_endp_intr & DIEPINTF_EPDIS) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS; - } - - if (in_endp_intr & DIEPINTF_TXFE) { - usbd_emptytxfifo_write(pudev, endp_num); - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that early suspend state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev) -{ - USB_GINTEN &= ~GINTEN_ESPIE; - USB_GINTF = GINTF_ESP; - - return 1U; -} - -/*! - \brief indicates that suspend state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev) -{ - __IO uint8_t low_power = pudev->cfg.low_power; - __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST); - __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U; - - pudev->dev.prev_status = pudev->dev.status; - pudev->dev.status = USB_STATUS_SUSPENDED; - - if (low_power && suspend && is_configured) { - /* switch-off the otg clocks */ - USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; - - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } - - /* clear interrupt */ - USB_GINTF = GINTF_SP; - - return 1U; -} - -/*! - \brief indicates that the USB controller has detected a resume or remote Wake-up sequence - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) -{ - pudev->dev.status = pudev->dev.prev_status; - pudev->dev.status = USB_STATUS_CONFIGURED; - - /* clear interrupt */ - USB_GINTF = GINTF_WKUPIF; - - return 1U; -} - -/*! - \brief handle the SOF interrupts - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) -{ - if (NULL != usbd_int_fops) { - usbd_int_fops->SOF(pudev); - } - - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle the rx status queue level interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) -{ - usb_ep_struct *ep; - uint8_t data_pid = 0U, endp_num = 0U; - uint32_t bcount = 0U, packet_num = 0U; - - /* get the status from the top of the fifo (must be read to a variable) */ - __IO uint32_t rx_status = USB_GRSTATP; - - /* disable the rx fifo non-empty interrupt */ - USB_GINTEN &= ~GINTEN_RXFNEIE; - - endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM); - bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U; - data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U); - - /* ensure no-DMA mode can work */ - packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT; - if ((1U == endp_num) && (0U == packet_num)) { - uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num); - - devepctl |= DEPCTL_SNAK; - devepctl &= ~DEPCTL_EPEN; - devepctl &= ~DEPCTL_EPD; - - USB_DOEPxCTL((uint16_t)endp_num) = devepctl; - } - - ep = &pudev->dev.out_ep[endp_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17U) { - case RXSTAT_GOUT_NAK: - break; - case RXSTAT_DATA_UPDT: - if (bcount > 0U) { - usb_fifo_read(ep->xfer_buff, (uint16_t)bcount); - ep->xfer_buff += bcount; - ep->xfer_count += bcount; - } - break; - case RXSTAT_XFER_COMP: - break; - case RXSTAT_SETUP_COMP: - break; - case RXSTAT_SETUP_UPDT: - *(uint32_t *)0x5000081CU |= 0x00020000U; - if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { - /* copy the setup packet received in fifo into the setup buffer in ram */ - usb_fifo_read(pudev->dev.setup_packet, 8U); - - ep->xfer_count += bcount; - } - break; - default: - break; - } - - /* enable the rx fifo non-empty interrupt */ - USB_GINTEN |= GINTEN_RXFNEIE; - - return 1U; -} - -/*! - \brief handle USB reset interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - usb_ep_struct *ep; - - /* clear the remote wakeup signaling */ - USB_DCTL &= ~DCTL_RWKUP; - - /* flush the tx fifo */ - usb_txfifo_flush(pudev, 0U); - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF((uint16_t)i) = 0xFFU; - USB_DOEPxINTF((uint16_t)i) = 0xFFU; - } - - /* clear all pending device endpoint interrupts */ - USB_DAEPINT = 0xFFFFFFFFU; - - /* enable endpoint 0 interrupts */ - USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; - USB_DAEPINTEN &= ~DAEPINTEN_IEPIE; - USB_DAEPINTEN = (1U << 16) | 1U; - - /* enable out endpoint interrupts */ - USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; - - /* enable in endpoint interrupts */ - USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; - - /* reset device address */ - USB_DCFG &= ~DCFG_DAR; - USB_DCFG |= 0U << 4U; - - /* configure endpoint 0 to receive setup packets */ - usb_ep0_startout(pudev); - - /* clear usb reset interrupt */ - USB_GINTF = GINTF_RST; - - /* open EP0 IN */ - ep = &pudev->dev.in_ep[0]; - - USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE; - USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; - - if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DIEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - /* open EP0 OUT */ - ep = &pudev->dev.out_ep[0]; - - USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE; - - if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DOEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - pudev->dev.status = USB_STATUS_DEFAULT; - - return 1U; -} - -/*! - \brief handle enumeration finish interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) -{ - uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U); - - /* set the max packet size of devie in endpoint based on the enumeration speed */ - USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed]; - - /* clear global in NAK */ - USB_DCTL &= ~DCTL_CGINAK; - USB_DCTL |= DCTL_CGINAK; - - /* set USB turn-around time based on device speed and PHY interface */ - if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) { - pudev->cfg.core_speed = USB_CORE_SPEED_HIGH; - pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x09U << 10; - } else { - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x05U << 10; - } - - /* clear interrupt */ - USB_GINTF = GINTF_ENUMF; - - return 1U; -} - -/*! - \brief handle the ISO in incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev) -{ - - /* clear interrupt */ - USB_GINTF = GINTF_ISOINCIF; - - return 1U; -} - -/*! - \brief handle the ISO OUT incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) -{ - /* clear interrupt */ - USB_GINTF = GINTF_ISOONCIF; - - return 1U; -} - -/*! - \brief check FIFO for the next packet to be loaded - \param[in] pudev: pointer to usb device instance - \param[in] ep_id: endpoint identifier which is in (0..3) - \param[out] none - \retval status -*/ -static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) -{ - uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U; - usb_ep_struct *ep; - - ep = &pudev->dev.in_ep[ep_num]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) && - (ep->xfer_count < ep->xfer_len)) { - /* write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - if(ep->xfer_len == ep->xfer_count) { - fifo_empty_mask = 0x1U << ep_num; - USB_DIEPFEINTEN &= ~fifo_empty_mask; - } - } - - return 1U; -} - -#ifdef VBUS_SENSING_ENABLED - -/*! - \brief indicates that the USB_OTG controller has detected a connection - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev) -{ - pudev->dev.connection_status = 1U; - - /* clear the interrupt bit */ - USB_GINTF = GINTF_SESIF; - - return 1; -} - -/*! - \brief indicates that the USB_OTG controller has detected an OTG event - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev) -{ - if (USB_GOTGINTF & GOTGINTF_SESEND) { - pudev->dev.class_deinit(pudev, 0); - pudev->dev.connection_status = 0; - } - - /* clear OTG interrupt */ - USB_GOTGINTF |= GOTGINTF_SESEND; - - return 1; -} - -#endif /* VBUS_SENSING_ENABLED */ diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c deleted file mode 100644 index 33ad7a94b6..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbd_std.c +++ /dev/null @@ -1,727 +0,0 @@ -/*! - \file usbd_std.c - \brief USB 2.0 standard handler driver - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_std.h" -#include "usb_core.h" - -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); - -static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clrfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfig, - usbd_setconfig, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse(pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, req.bmRequestType & 0x80U); - break; - } - - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.out_ep[0]; - - if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_rx (pudev, - 0U, - ep->xfer_buff, - (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, 0U); - } - - usbd_ctlstatus_tx(pudev); - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.in_ep[0]; - - if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - /* last packet is MPS multiple, so send ZLP packet */ - if ((pudev->dev.sum_len % ep->endp_mps == 0U) && - (pudev->dev.sum_len >= ep->endp_mps) && - (pudev->dev.sum_len < pudev->dev.ctl_len)) { - usbd_ep_tx (pudev, 0U, NULL, 0U); - pudev->dev.ctl_len = 0U; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, 0U); - } - - usbd_ctlstatus_rx(pudev); - } - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*StandardDeviceRequest[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret = USBD_OK; - - switch (pudev->dev.status) { - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - usbd_ctlstatus_tx(pudev); - } - } else { - usbd_enum_error(pudev, req); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - - return ret; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user... */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation... */ -} - -/*! - \brief get the device descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.dev_desc[0]; - - return pudev->dev.dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.config_desc[2]; - - return pudev->dev.config_desc; -} - -/*! - \brief get string descriptor - \param[in] index: string descriptor index - \param[in] pLen: pointer to string length - \param[out] none - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->dev.strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQTYPE_MASK) { - /* process device feature */ - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 0U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - break; - /* process interface feature */ - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - /* process endpoint feature */ - case USB_REQTYPE_ENDPOINT: - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - - pudev->dev.class_req_handler(pudev, req); - } - } - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - __IO uint32_t DctlrStatus; - - switch (req->bmRequestType & USB_REQ_MASK) { - /* process device feature */ - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 1U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } else if ((req->wValue == USB_FEATURE_TEST_MODE) && - (0U == (req->wIndex & 0xFFU))) { - DctlrStatus = USB_DCTL; - - usbd_ctlstatus_tx(pudev); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - /* process interface feature */ - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - /* process endpoint feature */ - case USB_REQTYPE_ENDPOINT: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t DevAddr; - - if ((0U == req->wIndex) && (0U == req->wLength)) { - DevAddr = (uint8_t)(req->wValue) & 0x7FU; - - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - usbd_enum_error(pudev, req); - } else { - USB_SET_DEVADDR((uint32_t)DevAddr); - - usbd_ctlstatus_tx(pudev); - - if (0U != DevAddr) { - pudev->dev.status = USB_STATUS_ADDRESSED; - } else { - pudev->dev.status = USB_STATUS_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { - uint8_t desc_type = (uint8_t)(req->wValue >> 8); - uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; - - if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { - uint16_t len; - uint8_t *pbuf; - - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); - - if ((0U != len) && (0U != req->wLength)) { - len = USB_MIN(len, req->wLength); - - if ((1U == desc_type) && (64U == req->wLength)) { - len = 8U; - } - - usbd_ctltx(pudev, pbuf, len); - } - } else { - usbd_enum_error(pudev, req); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) { - pudev->dev.class_req_handler(pudev, req); - } else { - /* no operation */ - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t USBD_default_config = 0U; - - if (1U != req->wLength) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U); - break; - case USB_STATUS_CONFIGURED: - usbd_ctltx(pudev, &pudev->dev.config_num, 1U); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - /* if config index is more than configuration max number */ - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (cfgidx) { - pudev->dev.config_num = cfgidx; - pudev->dev.status = USB_STATUS_CONFIGURED; - pudev->dev.class_init(pudev, cfgidx); - } - - usbd_ctlstatus_tx(pudev); - break; - case USB_STATUS_CONFIGURED: - if (0U == cfgidx) { - pudev->dev.status = USB_STATUS_ADDRESSED; - pudev->dev.config_num = cfgidx; - pudev->dev.class_deinit(pudev, cfgidx); - } else if (cfgidx != pudev->dev.config_num) { - /* clear old configuration */ - pudev->dev.class_deinit(pudev, pudev->dev.config_num); - - /* set new configuration */ - pudev->dev.config_num = cfgidx; - pudev->dev.class_init(pudev, cfgidx); - } else { - /* no operation */ - } - - usbd_ctlstatus_tx(pudev); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *psetup = pudev->dev.setup_packet; - - req->bmRequestType = *psetup; - req->bRequest = *(uint8_t *)(psetup + 1U); - req->wValue = SWAPBYTE (psetup + 2U); - req->wIndex = SWAPBYTE (psetup + 4U); - req->wLength = SWAPBYTE (psetup + 6U); - - pudev->dev.ctl_len = req->wLength; -} - -/*! - \brief handle USB low level error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, 0x80U); - usbd_ep_stall(pudev, 0x00U); - usb_ep0_startout(pudev); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c deleted file mode 100644 index de41f72273..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_core.c +++ /dev/null @@ -1,737 +0,0 @@ -/*! - \file usbh_core.c - \brief this file implements the functions for the core state machine process - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_hcs.h" -#include "usbh_core.h" -#include "usbh_int.h" -#include "stdio.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" -#include "usb_core.h" - -extern class_polling_fun_cb_struct class_polling_cb; - -uint8_t usbh_sof (usb_core_handle_struct *pudev); -uint8_t usbh_connected (usb_core_handle_struct *pudev); -uint8_t usbh_disconnected (usb_core_handle_struct *pudev); - -usbh_hcd_int_cb_struct usbh_hcd_int_cb = -{ - usbh_sof, - usbh_connected, - usbh_disconnected, -}; - -usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb; -extern usbh_state_handle_struct usbh_state_core; - -static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -/* the host state handle function array */ -void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - host_idle_handle, - host_dev_attached_handle, - host_dev_detached_handle, - host_detect_dev_speed_handle, - host_enum_handle, - host_class_request_handle, - host_class_handle, - host_user_input_handle, - host_suspended_handle, - host_error_handle, -}; - -/* the host state handle table */ -state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move }, - {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move }, - {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move }, - {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move }, - {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, - {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, -}; - -/*! - \brief the polling function of host state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate; - - scd_begin(p_state, HOST_FSM_ID); - - if (-1 == p_state->usbh_current_state_stack_top) { - uint8_t cur_state = p_state->usbh_current_state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) { - if (HOST_DEV_DETACHED != cur_state) { - p_state->usbh_current_state = HOST_DEV_DETACHED; - cur_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[cur_state](pudev, puhost, p_state); - } else { - uint8_t stack0_state = p_state->stack[0].state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) { - if (HOST_DEV_DETACHED != stack0_state) { - p_state->stack[0].state = HOST_DEV_DETACHED; - stack0_state = HOST_DEV_DETACHED; - p_state->usbh_current_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[stack0_state](pudev, puhost, p_state); - } - - return USBH_OK; -} - -/*! - \brief the handle function of HOST_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (hcd_is_device_connected(pudev)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } -} - -/*! - \brief the handle function of HOST_DEV_ATTACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_attached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usr_cb->device_connected(); - puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U); - puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U); - - /* reset usb device */ - if (0U == usb_port_reset(pudev)) { - puhost->usr_cb->device_reset(); - - /* wait for USB USBH_ISR_PrtEnDisableChange() - * host is now ready to start the enumeration - */ - puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET(); - puhost->usr_cb->device_speed_detected(puhost->device.speed); - - /* open in control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_in_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - /* open out control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_out_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_ENUMERATION state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_enum_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) { - puhost->usr_cb->enumeration_finish(); - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_USER_INPUT, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_USER_INPUT state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_user_input_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) { - if (USBH_OK == (puhost->class_init(pudev, puhost))) { - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_CLASS_REQ, - pustate->usbh_current_state); - } - } -} - -/*! - \brief the handle function of HOST_CLASS_REQUEST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_request_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_CLASS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - class_state_polling_fun(pudev, puhost, pustate); -} - -/*! - \brief the handle function of HOST_SUSPENDED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_suspended_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief the handle function of HOST_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* re-initilaize host for new enumeration */ - usbh_deinit (pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DEV_DETACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_detached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* manage user disconnect operations*/ - puhost->usr_cb->device_disconnected(); - - /* re-initilaize host for new enumeration */ - usbh_deinit(pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - usbh_allchannel_dealloc(pudev); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DETECT_DEV_SPEED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief usb connect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_connected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 1U; - - return 0U; -} - -/*! - \brief usb disconnect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_disconnected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 0U; - - return 0U; -} - -/*! - \brief usb sof callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_sof (usb_core_handle_struct *pudev) -{ - /* this callback could be used to implement a scheduler process */ - return 0U; -} - -/*! - \brief initialize the host portion of the driver. - \param[in] pudev: pointer to usb device - \param[in] core_id: usb otg core identifier(high-speed or full-speed) - \param[out] none - \retval operation status -*/ -uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - pudev->host.connect_status = 0U; - - pudev->host.host_channel[0].endp_mps = 8U; - - usb_core_select(pudev, core_id); - -#ifndef DUAL_ROLE_MODE_ENABLED - - USB_GLOBAL_INT_DISABLE(); - - usb_core_init(pudev); - - /* force host mode*/ - usb_mode_set(pudev, HOST_MODE); - - usb_hostcore_init(pudev); - - USB_GLOBAL_INT_ENABLE(); - -#endif - - return 0U; -} - -/*! - \brief check if the device is connected. - \param[in] pudev: pointer to usb device - \param[out] none - \retval device connection status. 1 -> connected and 0 -> disconnected -*/ -uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev) -{ - return (uint32_t)(pudev->host.connect_status); -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval urb_state_enum -*/ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].urb_state; -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval No. of data bytes transferred -*/ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].xfer_count; -} - -/*! - \brief de-initialize host - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[out] none - \retval host status -*/ -usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate) -{ - /* software init */ - - puhost->control.ep0_size = USB_MAX_EP0_SIZE; - - puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT; - puhost->device.speed = HPRT_PRTSPD_FULL_SPEED; - - usbh_channel_free(pudev, puhost->control.hc_in_num); - usbh_channel_free(pudev, puhost->control.hc_out_num); - - scd_init(pustate); - scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE); - - scd_begin(pustate,HOST_FSM_ID); - scd_state_move(pustate, HOST_IDLE); - - return USBH_OK; -} - -/*! - \brief state core driver init - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_init(usbh_state_handle_struct* pustate) -{ - /* init the state core */ - pustate->usbh_current_state = 0U; - pustate->usbh_current_state_table = NULL; - pustate->usbh_current_state_table_size = 0U; - - pustate->usbh_current_state_stack_top = -1; - pustate->stack->state = 0U; - pustate->stack->table_size = 0U; - pustate->stack->table = NULL; - - pustate->usbh_regist_state_table_num = 0U; - pustate->usbh_regist_state_table->table = NULL; - pustate->usbh_regist_state_table->table_size = 0U; - pustate->usbh_regist_state_table->id = 0U; - - /* init the control and the enumeration polling handle flag */ - ctrl_polling_handle_flag = 0U; - enum_polling_handle_flag = 0U; -} - -/*! - \brief state core driver table regist - \param[in] pustate: pointer to usb state driver - \param[in] pstate_table: pointer to the table to regist - \param[in] table_id: the id of the table to regist - \param[in] current_table_size: the size of the current table to regist - \param[out] none - \retval none -*/ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size) -{ - usbh_state_regist_table_struct *cur_state_reg_table; - - cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num]; - - cur_state_reg_table->id = table_id; - cur_state_reg_table->table = pstate_table; - cur_state_reg_table->table_size = current_table_size; - - pustate->usbh_regist_state_table_num++; -} - -/*! - \brief state core driver begin - \param[in] pustate: pointer to usb state driver - \param[in] table_id: the id of the table to begin - \param[out] none - \retval none -*/ -void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) -{ - uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num; - usbh_state_regist_table_struct *cur_state_reg_table; - - for (i = 0U; i < table_num; i++) { - cur_state_reg_table = &pustate->usbh_regist_state_table[i]; - - if (table_id == cur_state_reg_table->id) { - pustate->usbh_current_state_table = cur_state_reg_table->table; - pustate->usbh_current_state_table_size = cur_state_reg_table->table_size; - break; - } - } -} - -/*! - \brief state core driver move state - \param[in] pustate: pointer to usb state driver - \param[in] state: the state to move - \param[out] none - \retval none -*/ -void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state) -{ - pustate->usbh_current_state = state; -} - -/*! - \brief state core driver event handle - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[in] event: the current event - \param[in] state: the current state - \param[out] none - \retval host status -*/ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state) -{ - uint8_t i = 0U; - ACT_FUN event_act_fun = NULL; - state_table_struct *backup_state_t = pustate->usbh_current_state_table; - state_table_struct *executive_state_table = pustate->usbh_current_state_table; - - /* look up the table to find the action function */ - for (i = 0U; i < pustate->usbh_current_state_table_size; i++) { - if (state == executive_state_table->cur_state) { - if (event == executive_state_table->cur_event) { - state = executive_state_table->next_state; - event_act_fun = executive_state_table->event_action_fun; - break; - } else { - executive_state_table++; - } - } else { - executive_state_table++; - } - } - - pustate->usbh_current_state_table = backup_state_t; - - /* if the action function is not NULL, execute the action function */ - if (event_act_fun) { - if (event_act_fun == &only_state_move) { - pustate->usbh_current_state = state; - } else { - return event_act_fun(pudev, puhost, pustate); - } - } - - return USBH_BUSY; -} - -/*! - \brief state core driver table push - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_push(usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) { - pustate->usbh_current_state_stack_top++; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - /* put the current state table into the state stack */ - top_state_element->state = pustate->usbh_current_state; - top_state_element->table = pustate->usbh_current_state_table; - top_state_element->table_size = pustate->usbh_current_state_table_size; - } -} - -/*! - \brief state core driver table pop - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_pop (usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - if (pustate->usbh_current_state_stack_top > -1) { - /* get the current state table from the state stack */ - pustate->usbh_current_state = top_state_element->state; - pustate->usbh_current_state_table = top_state_element->table; - pustate->usbh_current_state_table_size = top_state_element->table_size; - pustate->usbh_current_state_stack_top--; - } -} -/*! - \brief the polling function of class req state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_req_polling(pudev, puhost, pustate); -} - -/*! - \brief the polling function of class state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_polling(pudev, puhost, pustate); -} - -/*! - \brief the function is only used to state move - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return USBH_OK; -} - -/*! - \brief the function to the up state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - scd_table_pop((usbh_state_handle_struct *)pustate); - - return USBH_OK; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c deleted file mode 100644 index 3f5277701f..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_ctrl.c +++ /dev/null @@ -1,639 +0,0 @@ -/*! - \file usbh_ctrl.c - \brief this file implements the functions for the control transmit process - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_core.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t ctrl_polling_handle_flag = 0U; -uint8_t ctrl_setup_wait_flag = 0U; -uint8_t ctrl_data_wait_flag = 0U; -uint8_t ctrl_status_wait_flag = 0U; - -static uint16_t timeout = 0U; - -static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the ctrl state handle function array */ -void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) = -{ - ctrl_idle_handle, - ctrl_setup_handle, - ctrl_data_handle, - ctrl_status_handle, - ctrl_error_handle, - ctrl_stalled_handle, - ctrl_complete_handle, -}; - -/* the ctrl state handle table */ -state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of CTRL state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - - p_state = (usbh_state_handle_struct *)pustate; - - /* if first enter this function, begin the ctrl state */ - if (0U == ctrl_polling_handle_flag) { - ctrl_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, CTRL_IDLE); - } - - /* base on the current state to handle the ctrl state */ - scd_begin(p_state, CTRL_FSM_ID); - ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - - /* determine the control transfer whether to complete */ - switch (puhost->usbh_backup_state.ctrl_backup_state) { - case CTRL_COMPLETE: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_OK; - break; - case CTRL_STALLED: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_NOT_SUPPORTED; - break; - case CTRL_ERROR: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_FAIL; - break; - default: - exe_state = USBH_BUSY; - break; - } - - return exe_state; -} - -/*! - \brief the handle function of CTRL_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_SETUP state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_setup_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP; - - if (0U == ctrl_setup_wait_flag) { - ctrl_setup_wait_flag = 1U; - - /* send a setup packet */ - usbh_ctltx_setup (pudev, - puhost->control.setup.data, - puhost->control.hc_out_num); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - /* case setup packet sent successfully */ - if (URB_DONE == urb_status) { - /* check if there is a data stage */ - if (0U != puhost->control.setup.b.wLength) { - ctrl_setup_wait_flag = 0U; - timeout = DATA_STAGE_TIMEOUT; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state); - /* no data stage */ - } else { - timeout = NODATA_STAGE_TIMEOUT; - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - } - - /* set the delay timer to enable timeout for data stage completion */ - puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET(); - } else if (URB_ERROR == urb_status) { - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state); - } else { - /* no operation */ - } - } -} - -/*! - \brief the handle function of CTRL_DATA state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_data_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA; - - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_IN == direction) { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* issue an IN token */ - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_in_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - /* check is data packet transfered successfully */ - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_data_wait_flag = 0U; - - /* timeout for in transfer */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* start data out transfer (only one data packet)*/ - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U; - - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_out_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - /* if the setup pkt is sent successful, then change the state */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* nack received from device */ - ctrl_data_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_STATUS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_status_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS; - - /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */ - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_OUT == direction) { - /* handle status in */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status*/ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_status_wait_flag = 0U; - - /* handle timeout */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - /* handle status out */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* handle URB_NOTREADY status */ - ctrl_status_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_ERROR status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR; - - if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { - /* do the transmission again, starting from setup packet */ - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); - } else { - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of CTRL_STALLED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_COMPLETE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_complete_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief send datas from the host channel - \param[in] pudev: pointer to usb device - \param[in] buf: data buffer address to send datas - \param[in] hc_num: the number of the host channel - \param[in] len: length of the send data - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, - uint8_t *buf, - uint8_t hc_num, - uint16_t len) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->xfer_buff = buf; - puhc->xfer_len = len; - - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - if (0U == puhc->endp_in) { - if (0U == len) { - /* for status out stage, length = 0, status out pid = 1 */ - puhc->data_tg_out = 1U; - } - - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - puhc->DPID = HC_PID_DATA1; - } - break; - - case USB_EPTYPE_ISOC: - puhc->DPID = HC_PID_DATA0; - break; - - case USB_EPTYPE_BULK: - if (0U == puhc->endp_in) { - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - } - break; - - case USB_EPTYPE_INTR: - if (0U == puhc->endp_in) { - if (0U == puhc->data_tg_out) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_out ^= 1U; - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_in ^= 1U; - } - break; - - default: - break; - } - - hcd_submit_request (pudev, hc_num); - - return USBH_OK; -} - -/*! - \brief send the setup packet to the device - \param[in] pudev: pointer to usb device - \param[in] buf: buffer pointer from which the data will be send to device - \param[in] hc_num: host channel number - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->DPID = HC_PID_SETUP; - puhc->xfer_buff = buf; - puhc->xfer_len = USBH_SETUP_PACKET_SIZE; - - return (usbh_status_enum)hcd_submit_request (pudev, hc_num); -} - -/*! - \brief this function prepare a hc and start a transfer - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - puhc->urb_state = URB_IDLE; - puhc->xfer_count = 0U; - - return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num); -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c deleted file mode 100644 index 33eecd62db..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_hcs.c +++ /dev/null @@ -1,185 +0,0 @@ -/*! - \file usbh_hcs.c - \brief this file implements functions for opening and closing host channels - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_hcs.h" - -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev); - -/*! - \brief open a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - uint16_t channel_info = puhc->info; - - puhc->endp_id = (uint8_t)channel_info & 0x7FU; - puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7U; - puhc->endp_type = ep_type; - puhc->endp_mps = ep_mps; - puhc->dev_addr = dev_addr; - puhc->dev_speed = dev_speed; - - puhc->data_tg_in = 0U; - puhc->data_tg_out = 0U; - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief modify a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB Device address allocated to attached device - \param[in] dev_speed: USB device speed (full speed / low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - if (0U != dev_addr) { - puhc->dev_addr = dev_addr; - } - - if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) { - puhc->endp_mps = ep_mps; - } - - if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) { - puhc->dev_speed = dev_speed; - } - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief allocate a new channel for the pipe - \param[in] pudev: pointer to usb device - \param[in] ep_addr: endpoint for which the channel to be allocated - \param[out] none - \retval host channel number -*/ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint16_t hc_num = usbh_freechannel_get(pudev); - - if ((uint16_t)HC_ERROR != hc_num) { - pudev->host.host_channel[hc_num].info = HC_USED | ep_addr; - } - - return (uint8_t)hc_num; -} - -/*! - \brief free the usb host channel - \param[in] pudev: pointer to usb device - \param[in] index: channel number to be freed which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index) -{ - if (index < HC_MAX) { - pudev->host.host_channel[index].info &= HC_USED_MASK; - } - - return USBH_OK; -} - -/*! - \brief free all usb host channel - \param[in] pudev: pointer to usb device - \param[out] none - \retval host operation status -*/ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev) -{ - uint8_t index; - - for (index = 2U; index < HC_MAX; index ++) { - pudev->host.host_channel[index].info = 0U; - } - - return USBH_OK; -} - -/*! - \brief get a free channel number for allocation to a device endpoint - \param[in] pudev: pointer to usb device - \param[out] none - \retval free channel number -*/ -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev) -{ - uint8_t index = 0U; - - for (index = 0U; index < HC_MAX; index++) { - if (0U == (pudev->host.host_channel[index].info & HC_USED)) { - return (uint16_t)index; - } - } - - return HC_ERROR; -} - diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c deleted file mode 100644 index 5a652bcb88..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_int.c +++ /dev/null @@ -1,612 +0,0 @@ -/*! - \file usbh_int.c - \brief USB host mode interrupt handler file - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usb_core.h" -#include "usb_defines.h" -#include "usbh_int.h" - -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev); - -/*! - \brief handle global host interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbh_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - __IO uint32_t int_flag = 0U; - - /* check if host mode */ - if (USB_CURRENT_MODE_GET() == HOST_MODE) { - USB_CORE_INTR_READ(int_flag); - - if (!int_flag) { - return 0U; - } - - /* start of frame interrupt handle */ - if (int_flag & GINTF_SOF) { - retval |= usbh_intf_sof (pudev); - } - - /* rx fifo non-empty interrupt handle */ - if (int_flag & GINTF_RXFNEIF) { - retval |= usbh_intf_rxfifo_noempty (pudev); - } - - /* non-periodic tx fifo empty interrupt hanlde */ - if (int_flag & GINTF_NPTXFEIF) { - retval |= usbh_intf_nptxfifo_empty (pudev); - } - - /* periodic tx fifo empty interrupt handle */ - if (int_flag & GINTF_PTXFEIF) { - retval |= usbh_intf_ptxfifo_empty (pudev); - } - - /* host channels interrupt handle */ - if (int_flag & GINTF_HCIF) { - retval |= usbh_intf_hc (pudev); - } - - /* host port interrupt handle */ - if (int_flag & GINTF_HPIF) { - retval |= usbh_intf_port (pudev); - } - - /* disconnect interrupt handle */ - if (int_flag & GINTF_DISCIF) { - retval |= usbh_intf_disconnect (pudev); - } - - /* isochronous in transfer not complete interrupt handle */ - if (int_flag & GINTF_ISOONCIF) { - retval |= usbh_intf_iso_incomplete_xfer (pudev); - } - } - - return retval; -} - -/*! - \brief handle the start-of-frame interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->sof(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle all host channels interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - uint32_t retval = 0U; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) { - if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) { - retval |= usbh_intf_hc_in (pudev, i); - } else { - retval |= usbh_intf_hc_out (pudev, i); - } - } - } - - return retval; -} - -/*! - \brief handle the disconnect interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->device_disconnected(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_DISCIF; - - return 1U; -} - -/*! - \brief handle the non-periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U; - - if (len > puhc->xfer_len) { - /* last packet */ - len = (uint16_t)puhc->xfer_len; - - USB_GINTEN &= ~GINTF_NPTXFEIF; - - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U; - - if (len > puhc->xfer_len) { - len = puhc->xfer_len; - - /* last packet */ - USB_GINTEN &= ~GINTF_PTXFEIF; - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the host port interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) -{ - uint8_t port_speed = 0U; - uint8_t port_reset = 0U; - uint32_t retval = 0U; - __IO uint32_t hostportdup = USB_HPCS; - - /* clear the interrupt bits in gintsts */ - hostportdup &= ~HPCS_PE; - hostportdup &= ~HPCS_PCD; - hostportdup &= ~HPCS_PEDC; - - /* port connect detected */ - if (USB_HPCS & HPCS_PCD) { - hostportdup |= HPCS_PCD; - usbh_hcd_int_fops->device_connected(pudev); - retval |= 1U; - } - - /* port enable changed */ - if (USB_HPCS & HPCS_PEDC) { - hostportdup |= HPCS_PEDC; - - if (USB_HPCS & HPCS_PE) { - port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U); - - if (HPRT_PRTSPD_LOW_SPEED == port_speed) { - USB_HFT = 6000U; - - if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_6_MHZ); - } - port_reset = 1U; - } - } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) { - USB_HFT = 48000U; - - if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - port_reset = 1U; - } - } else { - /* for high speed device and others */ - port_reset = 1U; - } - } - } - - if (port_reset) { - usb_port_reset(pudev); - } - - /* clear port interrupts */ - USB_HPCS = hostportdup; - - return retval; -} - -/*! - \brief handle the out channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num); - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - channel_intr &= USB_HCHxINTEN((uint16_t)channel_num); - - if (channel_intr & HCHINTF_ACK) { - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channel_intr & HCHINTF_REQOVR) { - /* handle queue overrun interrupt */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channel_intr & HCHINTF_TF) { - /* handle transfer finished interrupt */ - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } else if (channel_intr & HCHINTF_STALL) { - /* handle stall */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_STALL; - } else if (channel_intr & HCHINTF_NAK) { - /* handle NAK */ - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_NAK; - } else if (channel_intr & HCHINTF_USBER) { - /* handle USB bus error */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_TRACERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channel_intr & HCHINTF_NYET) { - /* handle NYET */ - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_NYET; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET; - } else if (channel_intr & HCHINTF_DTER) { - /* handle data toggle error */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status= HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else if (channel_intr & HCHINTF_CH) { - /* handle channel halted */ - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - - if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18U)) { - puhc->data_tg_out ^= 1U; - } - break; - case HC_NAK: - puhc->urb_state = URB_NOTREADY; - break; - case HC_NYET: - puhc->urb_state = URB_NOTREADY; - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - case HC_TRACERR: - puhc->urb_state = URB_ERROR; - break; - default: - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the in channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint8_t endp_type = 0U; - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num); - __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num); - - channle_intf &= USB_HCHxINTEN((uint16_t)channel_num); - - endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U); - - if (channle_intf & HCHINTF_ACK) { - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channle_intf & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_STALL; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - - /* NOTE: When there is a 'stall', reset also nak, - else, the pudev->host.status = HC_STALL - will be overwritten by 'nak' in code below */ - channle_intf &= ~HCHINTF_NAK; - - usb_hostchannel_halt(pudev, channel_num); - } else if (channle_intf & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else { - /* no operation */ - } - /* handle queue overrun interrupt */ - if (channle_intf & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channle_intf & HCHINTF_TF) { - /* handle transfer finished interrupt */ - puhc->status = HC_XF; - puhc->err_count = 0U; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - - if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->data_tg_in ^= 1U; - } else if (USB_EPTYPE_INTR == endp_type) { - channel_ctrl |= HCHCTL_ODDFRM; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - puhc->urb_state = URB_DONE; - } else { - /* no operation */ - } - } else if (channle_intf & HCHINTF_CH) { - /* handle channel halted */ - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - break; - case HC_TRACERR: - case HC_DTGERR: - puhc->err_count = 0U; - puhc->urb_state = URB_ERROR; - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - default: - if (USB_EPTYPE_INTR == endp_type) { - puhc->data_tg_in ^= 1U; - } - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else if (channle_intf & HCHINTF_USBER) { - /* handle USB bus error */ - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_TRACERR; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channle_intf & HCHINTF_NAK) { - /* handle NAK */ - if (USB_EPTYPE_INTR == endp_type) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - } - - puhc->status = HC_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - - if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - /* re-activate the channel */ - channel_ctrl |= HCHCTL_CEN; - channel_ctrl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - } - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the rx fifo non-empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - __IO uint8_t channel_num = 0U; - __IO uint32_t rx_status = 0U; - uint32_t usbh_ch_ctl_reg = 0U; - usb_hostchannel_struct *puhc; - - /* disable the rx status queue level interrupt */ - USB_GINTEN &= ~GINTF_RXFNEIF; - - rx_status = USB_GRSTATP; - channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM); - puhc = &pudev->host.host_channel[channel_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17) { - case GRSTATR_RPCKST_IN: - count = (rx_status & GRSTATRP_BCOUNT) >> 4; - - /* read the data into the host buffer. */ - if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { - usb_fifo_read(puhc->xfer_buff, (uint16_t)count); - - /* manage multiple Xfer */ - puhc->xfer_buff += count; - puhc->xfer_count += count; - - if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) { - /* re-activate the channel when more packets are expected */ - usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num); - usbh_ch_ctl_reg |= HCHCTL_CEN; - usbh_ch_ctl_reg &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg; - } - } - break; - case GRSTATR_RPCKST_IN_XFER_COMP: - break; - case GRSTATR_RPCKST_DATA_TOGGLE_ERR: - count = (rx_status & GRSTATRP_BCOUNT) >> 4; - while (count > 0) { - rx_status = USB_GRSTATP; - count--; - } - break; - case GRSTATR_RPCKST_CH_HALTED: - default: - break; - } - - /* enable the rx status queue level interrupt */ - USB_GINTEN |= GINTF_RXFNEIF; - - return 1U; -} - -/*! - \brief handle the incomplete periodic transfer interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev) -{ - __IO uint32_t gint_flag = 0U; - - gint_flag = USB_HCHxCTL(0U); - USB_HCHxCTL(0U) = 0U; - - gint_flag = 0U; - - /* clear interrupt */ - gint_flag |= GINTF_ISOONCIF; - USB_GINTF = gint_flag; - - return 1U; -} diff --git a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c b/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c deleted file mode 100644 index 6052b906e4..0000000000 --- a/bsp/gd32107c-eval/Libraries/GD32F10x_usbfs_driver/Source/usbh_std.c +++ /dev/null @@ -1,834 +0,0 @@ -/*! - \file usbh_std.c - \brief USB 2.0 standard function definition - - \version 2014-12-26, V1.0.0, firmware for GD32F10x - \version 2017-06-20, V2.0.0, firmware for GD32F10x - \version 2018-07-31, V2.1.0, firmware for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_core.h" -#include "usbh_usr.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t local_buffer[64U]; -uint8_t usbh_cfg_desc[512U]; -uint8_t enum_polling_handle_flag = 0U; - -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the enumeration state handle function array */ -void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - enum_idle_handle, - enum_set_addr_handle, - enum_get_full_dev_desc_handle, - enum_get_cfg_desc_handle, - enum_get_full_cfg_desc_handle, - enum_get_mfc_string_desc_handle, - enum_get_product_string_desc_handle, - enum_get_serialnum_string_desc_handle, - enum_set_configuration_handle, - enum_dev_configured_handle, -}; - -/* the enumeration state handle table */ -state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move }, - {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move }, - {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move }, - {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move }, - {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move }, - {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move }, - {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move }, - {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move }, - {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move }, - {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of enumeration state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval usb host status -*/ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - p_state = (usbh_state_handle_struct *)pustate; - - if (0U == enum_polling_handle_flag) { - enum_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, ENUM_IDLE); - } - - /* start the enumeration state handle */ - scd_begin(p_state,ENUM_FSM_ID); - - if (0U == p_state->usbh_current_state_stack_top) { - enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - } else { - enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); - } - - /* determine the enumeration whether to complete */ - if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) { - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - enum_polling_handle_flag = 0U; - exe_state = USBH_OK; - } - - return exe_state; -} - -/*! - \brief the handle function of ENUM_IDLE state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - 8U); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U); - puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0; - - /* issue reset */ - usb_port_reset(pudev); - - /* modify control channels configuration for maxpacket size */ - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, - puhost, - pustate, - ENUM_EVENT_SET_ADDR, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_DEV_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - USB_DEVDESC_SIZE); - } - - if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE); - puhost->usr_cb->device_desc_available(&puhost->device.dev_desc); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_ADDR state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_addr_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(2U); - } - puhost->device.address = USBH_DEVICE_ADDRESS; - - /* user callback for device address assigned */ - puhost->usr_cb->device_address_set(); - - /* modify control channels to update device address */ - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - puhost->device.address, - 0U, - 0U, - 0U); - - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - puhost->device.address, - 0U, - 0U, - 0U); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_DEV_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, - USB_CFGDESC_SIZE); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < USB_CFGDESC_SIZE; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - USB_CFGDESC_SIZE); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, puhost->device.cfg_desc.wTotalLength); - } - - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < puhost->device.cfg_desc.wTotalLength; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - puhost->device.cfg_desc.wTotalLength); - - /* User callback for configuration descriptors available */ - puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc[0]); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_MFC_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_MFC_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC; - - if (0U != puhost->device.dev_desc.iManufacturer) { - if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iManufacturer, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - puhost->usr_cb->manufacturer_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_PRODUCT_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->manufacturer_string("N/A"); - scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC); - } -} - -/*! - \brief the handle function of ENUM_GET_PRODUCT_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC; - - if (0U != puhost->device.dev_desc.iProduct) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iProduct, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->product_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->product_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_SERIALNUM_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC; - - if (0U != puhost->device.dev_desc.iSerialNumber) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iSerialNumber, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->serial_num_string(local_buffer); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->serial_num_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_CONFIGURATION state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) { - usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_DEV_CONFIGURED, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_DEV_CONFIGURED state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief get descriptor in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] buf: buffer to store the descriptor - \param[in] ReqType: descriptor type - \param[in] ValueIdx: wValue for the GetDescriptr request - \param[in] Len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_enum_desc_get(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len) -{ - usb_setup_union *pSetup = &(puhost->control.setup); - - pSetup->b.bmRequestType = USB_DIR_IN | req_type; - pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR; - pSetup->b.wValue = value_idx; - - if (USB_STRDESC == (value_idx & 0xff00U)){ - pSetup->b.wIndex = 0x0409U; - } else { - pSetup->b.wIndex = 0U; - } - - pSetup->b.wLength = len; - - puhost->control.buff = buf; - puhost->control.length = len; - -} - -/*! - \brief set address in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] device_address: the device address - \param[out] none - \retval none -*/ -void usbh_enum_addr_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t device_address) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_ADDRESS; - p_setup->b.wValue = (uint16_t)device_address; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0U; - puhost->control.length = 0U; -} - -/*! - \brief set configuration in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] cfg_idx: the index of the configuration - \param[out] none - \retval none -*/ -void usbh_enum_cfg_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint16_t cfg_idx) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_CONFIGURATION; - p_setup->b.wValue = cfg_idx; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0; - puhost->control.length = 0U; -} - -/*! - \brief parse the device descriptor - \param[in] dev_desc: device_descriptor destinaton address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len) -{ - dev_desc->Header.bLength = *(uint8_t *)(buf + 0U); - dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - dev_desc->bcdUSB = SWAPBYTE(buf + 2U); - dev_desc->bDeviceClass = *(uint8_t *)(buf + 4U); - dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5U); - dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6U); - dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7U); - - if (len > 8U){ - /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ - dev_desc->idVendor = SWAPBYTE(buf + 8U); - dev_desc->idProduct = SWAPBYTE(buf + 10U); - dev_desc->bcdDevice = SWAPBYTE(buf + 12U); - dev_desc->iManufacturer = *(uint8_t *)(buf + 14U); - dev_desc->iProduct = *(uint8_t *)(buf + 15U); - dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U); - dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17U); - } -} - -/*! - \brief parse the configuration descriptor - \param[in] cfg_desc: configuration descriptor address - \param[in] itf_desc: interface descriptor address - \param[in] ep_desc: endpoint descriptor address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len) -{ - usb_descriptor_interface_struct *pitf = NULL; - usb_descriptor_interface_struct temp_pitf; - usb_descriptor_endpoint_struct *pep = NULL; - usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf; - - uint8_t itf_ix = 0U; - uint8_t ep_ix = 0U; - uint16_t ptr = 0U; - static uint8_t prev_itf = 0U; - static uint16_t prev_ep_size = 0U; - - /* parse configuration descriptor */ - cfg_desc->Header.bLength = *(uint8_t *)(buf + 0U); - cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - cfg_desc->wTotalLength = SWAPBYTE(buf + 2U); - cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4U); - cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5U); - cfg_desc->iConfiguration = *(uint8_t *)(buf + 6U); - cfg_desc->bmAttributes = *(uint8_t *)(buf + 7U); - cfg_desc->bMaxPower = *(uint8_t *)(buf + 8U); - - if (len > USB_CFGDESC_SIZE) { - ptr = USB_CFG_DESC_LEN; - - if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) { - pitf = (usb_descriptor_interface_struct *)0U; - - for (; ptr < cfg_desc->wTotalLength; ) { - pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr); - - if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) { - itf_ix = *((uint8_t *)pdesc + 2U); - pitf = &itf_desc[itf_ix]; - - if (*((uint8_t *)pdesc + 3U) < 3U) { - usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc); - - /* parse endpoint descriptors relative to the current interface */ - if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) { - for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) { - pdesc = usbh_next_desc_get((void* )pdesc, &ptr); - - if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) { - pep = &ep_desc[itf_ix][ep_ix]; - - if (prev_itf != itf_ix) { - prev_itf = itf_ix; - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } else { - if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) { - break; - } else { - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } - } - - usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc); - prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4); - ep_ix++; - } - } - } - } - } - } - } - - prev_ep_size = 0U; - prev_itf = 0U; - } -} - -/*! - \brief parse the interface descriptor - \param[in] itf_desc: interface descriptor destination - \param[in] buf: buffer where the descriptor data is available - \param[out] none - \retval none -*/ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf) -{ - itf_desc->Header.bLength = *(uint8_t *)(buf + 0U); - itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2U); - itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3U); - itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4U); - itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5U); - itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6U); - itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7U); - itf_desc->iInterface = *(uint8_t *)(buf + 8U); -} - -/*! - \brief parse the endpoint descriptor - \param[in] ep_desc: endpoint descriptor destination address - \param[in] buf: buffer where the parsed descriptor stored - \param[out] none - \retval none -*/ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf) -{ - ep_desc->Header.bLength = *(uint8_t *)(buf + 0U); - ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1U); - ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2U); - ep_desc->bmAttributes = *(uint8_t *)(buf + 3U); - ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4U); - ep_desc->bInterval = *(uint8_t *)(buf + 6U); -} - -/*! - \brief parse the string descriptor - \param[in] psrc: source pointer containing the descriptor data - \param[in] pdest: destination address pointer - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len) -{ - uint16_t strlength; - uint16_t idx; - - /* the unicode string descriptor is not null-terminated. the string length is - computed by substracting two from the value of the first byte of the descriptor. - */ - - /* check which is lower size, the size of string or the length of bytes read from the device */ - - if (USB_DESCTYPE_STRING == psrc[1]){ - /* make sure the descriptor is string type */ - - /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ - strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len); - psrc += 2; /* adjust the offset ignoring the string len and descriptor type */ - - for (idx = 0U; idx < strlength; idx += 2U) { - /* copy only the string and ignore the unicode id, hence add the src */ - *pdest = psrc[idx]; - pdest++; - } - - *pdest = 0U; /* mark end of string */ - } -} - -/*! - \brief get the next descriptor header - \param[in] pbuf: pointer to buffer where the cfg descriptor is available - \param[in] ptr: data popinter inside the configuration descriptor - \param[out] none - \retval next descriptor header -*/ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr) -{ - uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength; - - usb_descriptor_header_struct *pnext; - - *ptr += len; - - pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len); - - return(pnext); -} - diff --git a/bsp/gd32107c-eval/Libraries/SConscript b/bsp/gd32107c-eval/Libraries/SConscript deleted file mode 100644 index b77e069f46..0000000000 --- a/bsp/gd32107c-eval/Libraries/SConscript +++ /dev/null @@ -1,33 +0,0 @@ -import rtconfig -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. - -src = Glob('GD32F10x_standard_peripheral/Source/*.c') -src += [cwd + '/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c'] - -#add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += [cwd + '/CMSIS/GD/GD32F10x/Source/GCC/startup_gd32f10x_cl.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [cwd + '/CMSIS/GD/GD32F10x/Source/ARM/startup_gd32f10x_cl.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += [cwd + '/CMSIS/GD/GD32F10x/Source/IAR/startup_gd32f10x_cl.s'] - -path = [ - cwd + '/CMSIS/GD/GD32F10x/Include', - cwd + '/CMSIS', - cwd + '/GD32F10x_standard_peripheral/Include',] - -if GetDepend(['RT_USING_BSP_USB']): - path += [cwd + '/GD32F10x_usbfs_driver/Include'] - src += [cwd + '/GD32F10x_usbfs_driver/Source'] - -CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F10X_CL'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/gd32107c-eval/README.md b/bsp/gd32107c-eval/README.md deleted file mode 100644 index 3ae69f8226..0000000000 --- a/bsp/gd32107c-eval/README.md +++ /dev/null @@ -1,93 +0,0 @@ -# GD32105C-EVAL # - -## 1. 简介 - -[GD32105C-EVAL](http://gd32mcu.21ic.com)是兆易科技æ供的开å‘æ¿ï¼Œä½¿ç”¨ GD32F105VCT6 作为主控制器。æä¾›åŒ…æ‹¬æ‰©å±•å¼•è„šåœ¨å†…çš„åŠ SWD, Reset, Boot, User button key, LED, CAN, I2C, I2S, USART, RTC, LCD, SPI, ADC, DAC, EXMC, CTC, SDIO,USBD, GD-Link 等外设资æºã€‚ - -æ¿è½½ä¸»è¦èµ„æºå¦‚下： - -| 硬件 | æè¿° | -| -- | -- | -|CPU| Cortex-M3| -|主频| 120MHz | -|SRAM| 96KB | -|Flash| 256KB | - -## 2. 编译说明 - -GD32105C-EVALæ¿çº§åŒ…支æŒMDK5ã€IARå¼€å‘环境和GCC编译器，以下是具体版本信æ¯ï¼š - -| IDE/编译器 | 已测试版本 | -| -- | -- | -| MDK5 | MDK5.25 | -| IAR | IAR8.20 | -| GCC | GCC 5.4.1 20160919 (release) | - -## 3. 烧写åŠæ‰§è¡Œ - -供电方å¼ï¼šå¼€å‘æ¿ä½¿ç”¨ Mini USB 接å£æˆ–者 DC-005 连接器æä¾› 5V 电æºã€‚ - -下载程åºï¼šä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿éœ€è¦ä¸€å¥— JLink 或者使用 GD-Link 工具。 - -解决IDE "Missing Device(s)"问题" -* MDK5: 安装GigaDevice.GD32F10x_DFP.2.0.1.pack，在 Folder Selection 中的 Destination Folder 那一æ é€‰æ‹© Keil uVision5 软件的安装目录，如 C:\Keil_v5，然åŽåœ¨ Option for Target çš„ Device 选择对应的器件，åŒæ—¶åœ¨ Option forTarget çš„ C/C++中添加路径 C:\Keil_v5\ARM\Pack\ARM\CMSIS\4.2.0\CMSIS\Include。 - -* IAR：安装 IAR_GD32F10x_ADDON.2.0.0.exe - -### 3.1 é…置和仿真 - -工程已ç»é»˜è®¤ä½¿èƒ½äº†RT-Thread UART驱动ã€GPIO驱动ã€SPI驱动ã€I2C驱动。若想进一步é…置工程请 -使用ENV工具。 - -### 3.2 è¿è¡Œç»“æžœ - -打开MDK或者IAR工程，进入仿真åŽå…¨é€Ÿè¿è¡Œï¼Œå°†ä¼šåœ¨ä¸²å£0上看到RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š - -``` - \ | / -- RT - Thread Operating System - / | \ 4.0.4 build Aug 23 2021 - 2006 - 2021 Copyright by rt-thread team -msh > - -``` - -## 4. 驱动支æŒæƒ…况åŠè®¡åˆ’ - -| 驱动 | 支æŒæƒ…况 | 备注 | -| ------ | ---- | :------: | -| UART | æ”¯æŒ | UART0/1/2/3 | -| GPIO | æ”¯æŒ | | -| SPI | æ”¯æŒ | SPI0/1/2 | -| I2C | æ”¯æŒ | I2C0/1| - -### 4.1 IO在æ¿çº§æ”¯æŒåŒ…中的映射情况 - -| IOå· | æ¿çº§åŒ…中的定义 | -| -- | -- | -| PA9 | USART0 TX | -| PA10 | USART0 RX | -| PA2 | USART1 TX | -| PA3 | USART1 RX | -| PA5| SPI0 SCK | -| PA6 | SPI0 MISO | -| PA6 | SPI0 MOSI | -| PB13| SPI1 SCK | -| PB14 | SPI1 MISO | -| PB15 | SPI1 MOSI | -| PB6| I2C0 SCL | -| PB7 | I2C0 SDA | -| PB10| I2C1 SCL | -| PB11 | I2C1 SDA | - -## 5. è”ç³»äººä¿¡æ¯ - -维护人： - -- [lianzhian](https://gitee.com/qidiyun) - -## 6. å‚考 - -* [GD32105C-EVAL](http://gd32mcu.21ic.com/site) - - diff --git a/bsp/gd32107c-eval/SConscript b/bsp/gd32107c-eval/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/gd32107c-eval/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32107c-eval/SConstruct b/bsp/gd32107c-eval/SConstruct deleted file mode 100644 index 6712d0169f..0000000000 --- a/bsp/gd32107c-eval/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32107c-eval/applications/SConscript b/bsp/gd32107c-eval/applications/SConscript deleted file mode 100644 index 9bb9abae89..0000000000 --- a/bsp/gd32107c-eval/applications/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -from building import * -import os - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -list = os.listdir(cwd) -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - group = group + SConscript(os.path.join(item, 'SConscript')) - -Return('group') diff --git a/bsp/gd32107c-eval/applications/main.c b/bsp/gd32107c-eval/applications/main.c deleted file mode 100644 index 83b68664a3..0000000000 --- a/bsp/gd32107c-eval/applications/main.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-24 lianzhian first implementation - */ -#include -#include -#include - - -/* defined the LED0 pin: PF0 */ -#define LED0_PIN GET_PIN(C, 0) - -int main(void) -{ - int count = 1; - /* set LED0 pin mode to output */ - rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); - - while (count++) - { - rt_pin_write(LED0_PIN, PIN_HIGH); - rt_thread_mdelay(500); - rt_pin_write(LED0_PIN, PIN_LOW); - rt_thread_mdelay(500); - } - - return RT_EOK; -} - diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf b/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf deleted file mode 100644 index 27790e4197..0000000000 --- a/bsp/gd32107c-eval/board/linker_script/gd32_rom.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807ffff; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -export symbol __ICFEDIT_region_RAM_end__; - -define symbol __region_RAM1_start__ = 0x10000000; -define symbol __region_RAM1_end__ = 0x1000FFFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.ld b/bsp/gd32107c-eval/board/linker_script/gd32_rom.ld deleted file mode 100644 index 4af47d1dcb..0000000000 --- a/bsp/gd32107c-eval/board/linker_script/gd32_rom.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linker script for GD32F30x with GNU ld - * bernard.xiong 2009-10-14 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 512KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 96k /* 64KB sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/gd32107c-eval/board/linker_script/gd32_rom.sct b/bsp/gd32107c-eval/board/linker_script/gd32_rom.sct deleted file mode 100644 index b3144a70e0..0000000000 --- a/bsp/gd32107c-eval/board/linker_script/gd32_rom.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x000040000 { ; load region size_region - ER_IROM1 0x08000000 0x000040000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00018000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/gd32107c-eval/drivers/Kconfig b/bsp/gd32107c-eval/drivers/Kconfig deleted file mode 100644 index d6ee12a61c..0000000000 --- a/bsp/gd32107c-eval/drivers/Kconfig +++ /dev/null @@ -1,69 +0,0 @@ -menu "Hardware Drivers Config" - -menu "Onboard Peripheral Drivers" - -endmenu - -menu "On-chip Peripheral Drivers" - - config SOC_SERIES_GD32F1 - bool - default y - config SOC_GD32107C - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - select SOC_SERIES_GD32F1 - default y - - config RT_USING_USART0 - bool "Using USART0" - select RT_USING_SERIAL - default y - - config RT_USING_USART1 - bool "Using USART1" - select RT_USING_SERIAL - default n - - config RT_USING_USART2 - bool "Using USART2" - select RT_USING_SERIAL - default n - - config RT_USING_UART3 - bool "Using UART3" - select RT_USING_SERIAL - default n - - config RT_USING_SPI0 - bool "Using SPI0" - select RT_USING_SPI - default y - - config RT_USING_SPI1 - bool "Using SPI1" - select RT_USING_SPI - default n - - config RT_USING_SPI2 - bool "Using SPI2" - select RT_USING_SPI - default n - - config RT_USING_I2C0 - bool "Using I2C0" - select RT_USING_I2C - default n - - config RT_USING_I2C1 - bool "Using I2C1" - select RT_USING_I2C - default n -endmenu - -menu "Board extended module Drivers" - -endmenu - -endmenu diff --git a/bsp/gd32107c-eval/drivers/SConscript b/bsp/gd32107c-eval/drivers/SConscript deleted file mode 100644 index 77badf9a32..0000000000 --- a/bsp/gd32107c-eval/drivers/SConscript +++ /dev/null @@ -1,33 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drivers. -src = Split(""" -board.c -drv_usart.c -""") - -CPPPATH = [cwd] - -# add spi drivers. -if GetDepend('RT_USING_SPI'): - src += ['drv_spi.c'] - -# add i2c drivers. -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -# add pin drivers. -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -# add spi flash drivers. -if GetDepend('RT_USING_SFUD'): - src += ['drv_spi_flash.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32107c-eval/drivers/board.c b/bsp/gd32107c-eval/drivers/board.c deleted file mode 100644 index 528c166884..0000000000 --- a/bsp/gd32107c-eval/drivers/board.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include -#include - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while (1) - { - } - /* USER CODE END Error_Handler */ -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This function will initial GD32 board. - */ -void rt_hw_board_init() -{ - /* NVIC Configuration */ -#define NVIC_VTOR_MASK 0x3FFFFF80 -#ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); -#else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); -#endif - - SystemClock_Config(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/gd32107c-eval/drivers/board.h b/bsp/gd32107c-eval/drivers/board.h deleted file mode 100644 index 7b791f25c9..0000000000 --- a/bsp/gd32107c-eval/drivers/board.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include -#include "drv_gpio.h" - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#ifdef __ICCARM__ -// Use *.icf ram symbal, to avoid hardcode. -extern char __ICFEDIT_region_RAM_end__; -#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ -#else -#define GD32_SRAM_SIZE 96 -#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) -#endif - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif - -#define HEAP_END GD32_SRAM_END - -#endif - -//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32107c-eval/drivers/drv_comm.h b/bsp/gd32107c-eval/drivers/drv_comm.h deleted file mode 100644 index 0881776e60..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_comm.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __DRV_COMM_H__ -#define __DRV_COMM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_HWTIMER_H__ */ - diff --git a/bsp/gd32107c-eval/drivers/drv_gpio.c b/bsp/gd32107c-eval/drivers/drv_gpio.c deleted file mode 100644 index a4dd68ee17..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_gpio.c +++ /dev/null @@ -1,552 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include "drv_gpio.h" -#include -#include -#include "gd32f10x.h" -#include "gd32f10x_exti.h" - -#ifdef RT_USING_PIN - -#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \ - GPIO_PIN_##pin, GPIO_PORT_SOURCE_GPIO##port, GPIO_PIN_SOURCE_##pin} -#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} - -/* GD32 GPIO driver */ -struct pin_index -{ - rt_int16_t index; - rcu_periph_enum clk; - rt_uint32_t gpio_periph; - rt_uint32_t pin; - rt_uint8_t port_src; - rt_uint8_t pin_src; -}; - -static const struct pin_index pins[] = -{ - __GD32_PIN(0 , A, 0 ), - __GD32_PIN(1 , A, 1 ), - __GD32_PIN(2 , A, 2 ), - __GD32_PIN(3 , A, 3 ), - __GD32_PIN(4 , A, 4 ), - __GD32_PIN(5 , A, 5 ), - __GD32_PIN(6 , A, 6 ), - __GD32_PIN(7 , A, 7 ), - __GD32_PIN(8 , A, 8 ), - __GD32_PIN(9 , A, 9 ), - __GD32_PIN(10, A, 10), - __GD32_PIN(11, A, 11), - __GD32_PIN(12, A, 12), - __GD32_PIN(13, A, 13), - __GD32_PIN(14, A, 14), - __GD32_PIN(15, A, 15), - - __GD32_PIN(16, B, 0), - __GD32_PIN(17, B, 1), - __GD32_PIN(18, B, 2), - __GD32_PIN(19, B, 3), - __GD32_PIN(20, B, 4), - __GD32_PIN(21, B, 5), - __GD32_PIN(22, B, 6), - __GD32_PIN(23, B, 7), - __GD32_PIN(24, B, 8), - __GD32_PIN(25, B, 9), - __GD32_PIN(26, B, 10), - __GD32_PIN(27, B, 11), - __GD32_PIN(28, B, 12), - __GD32_PIN(29, B, 13), - __GD32_PIN(30, B, 14), - __GD32_PIN(31, B, 15), - - __GD32_PIN(32, C, 0), - __GD32_PIN(33, C, 1), - __GD32_PIN(34, C, 2), - __GD32_PIN(35, C, 3), - __GD32_PIN(36, C, 4), - __GD32_PIN(37, C, 5), - __GD32_PIN(38, C, 6), - __GD32_PIN(39, C, 7), - __GD32_PIN(40, C, 8), - __GD32_PIN(41, C, 9), - __GD32_PIN(42, C, 10), - __GD32_PIN(43, C, 11), - __GD32_PIN(44, C, 12), - __GD32_PIN(45, C, 13), - __GD32_PIN(46, C, 14), - __GD32_PIN(47, C, 15), - - __GD32_PIN(48, D, 0), - __GD32_PIN(49, D, 1), - __GD32_PIN(50, D, 2), - __GD32_PIN(51, D, 3), - __GD32_PIN(52, D, 4), - __GD32_PIN(53, D, 5), - __GD32_PIN(54, D, 6), - __GD32_PIN(55, D, 7), - __GD32_PIN(56, D, 8), - __GD32_PIN(57, D, 9), - __GD32_PIN(58, D, 10), - __GD32_PIN(59, D, 11), - __GD32_PIN(60, D, 12), - __GD32_PIN(61, D, 13), - __GD32_PIN(62, D, 14), - __GD32_PIN(63, D, 15), - - __GD32_PIN(64, E, 0), - __GD32_PIN(65, E, 1), - __GD32_PIN(66, E, 2), - __GD32_PIN(67, E, 3), - __GD32_PIN(68, E, 4), - __GD32_PIN(69, E, 5), - __GD32_PIN(70, E, 6), - __GD32_PIN(71, E, 7), - __GD32_PIN(72, E, 8), - __GD32_PIN(73, E, 9), - __GD32_PIN(74, E, 10), - __GD32_PIN(75, E, 11), - __GD32_PIN(76, E, 12), - __GD32_PIN(77, E, 13), - __GD32_PIN(78, E, 14), - __GD32_PIN(79, E, 15), - - __GD32_PIN(80, F, 0), - __GD32_PIN(81, F, 1), - __GD32_PIN(82, F, 2), - __GD32_PIN(83, F, 3), - __GD32_PIN(84, F, 4), - __GD32_PIN(85, F, 5), - __GD32_PIN(86, F, 6), - __GD32_PIN(87, F, 7), - __GD32_PIN(88, F, 8), - __GD32_PIN(89, F, 9), - __GD32_PIN(90, F, 10), - __GD32_PIN(91, F, 11), - __GD32_PIN(92, F, 12), - __GD32_PIN(93, F, 13), - __GD32_PIN(94, F, 14), - __GD32_PIN(95, F, 15), - - __GD32_PIN(96, G, 0), - __GD32_PIN(97, G, 1), - __GD32_PIN(98, G, 2), - __GD32_PIN(99, G, 3), - __GD32_PIN(100, G, 4), - __GD32_PIN(101, G, 5), - __GD32_PIN(102, G, 6), - __GD32_PIN(103, G, 7), - __GD32_PIN(104, G, 8), - __GD32_PIN(105, G, 9), - __GD32_PIN(106, G, 10), - __GD32_PIN(107, G, 11), - __GD32_PIN(108, G, 12), - __GD32_PIN(109, G, 13), - __GD32_PIN(110, G, 14), - __GD32_PIN(111, G, 15), - - -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI5_9_IRQn}, - {GPIO_PIN_6, EXTI5_9_IRQn}, - {GPIO_PIN_7, EXTI5_9_IRQn}, - {GPIO_PIN_8, EXTI5_9_IRQn}, - {GPIO_PIN_9, EXTI5_9_IRQn}, - {GPIO_PIN_10, EXTI10_15_IRQn}, - {GPIO_PIN_11, EXTI10_15_IRQn}, - {GPIO_PIN_12, EXTI10_15_IRQn}, - {GPIO_PIN_13, EXTI10_15_IRQn}, - {GPIO_PIN_14, EXTI10_15_IRQn}, - {GPIO_PIN_15, EXTI10_15_IRQn}, -}; -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(rt_uint8_t pin) -{ - const struct pin_index *index; - - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - - return index; -}; - -static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) -{ - const struct pin_index *index; - rt_uint32_t pin_mode; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* GPIO Periph clock enable */ - rcu_periph_clock_enable(index->clk); - pin_mode = GPIO_MODE_OUT_PP; - - switch(mode) - { - case PIN_MODE_OUTPUT: - /* output setting */ - pin_mode = GPIO_MODE_OUT_PP; - break; - case PIN_MODE_OUTPUT_OD: - /* output setting: od. */ - pin_mode = GPIO_MODE_OUT_OD; - break; - case PIN_MODE_INPUT: - /* input setting: not pull. */ - pin_mode = GPIO_MODE_IN_FLOATING; - break; - case PIN_MODE_INPUT_PULLUP: - /* input setting: pull up. */ - pin_mode = GPIO_MODE_IPU; - break; - case PIN_MODE_INPUT_PULLDOWN: - /* input setting: pull down. */ - pin_mode = GPIO_MODE_IPD; - break; - default: - break; - } - - gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); -} - -static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) -{ - const struct pin_index *index; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); -} - -static rt_int8_t _pin_read(rt_device_t dev, rt_base_t pin) -{ - rt_int8_t value; - const struct pin_index *index; - - value = PIN_LOW; - - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - - value = gpio_input_bit_get(index->gpio_periph, index->pin); - - return value; -} - - -rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) -{ - rt_uint8_t i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { - return i; - } - } - return -1; -} -rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) -{ - rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; -static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == pin && - pin_irq_hdr_tab[hdr_index].hdr == hdr && - pin_irq_hdr_tab[hdr_index].mode == mode && - pin_irq_hdr_tab[hdr_index].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[hdr_index].pin != -1) - { - rt_hw_interrupt_enable(level); - return -RT_EFULL; - } - pin_irq_hdr_tab[hdr_index].pin = pin; - pin_irq_hdr_tab[hdr_index].hdr = hdr; - pin_irq_hdr_tab[hdr_index].mode = mode; - pin_irq_hdr_tab[hdr_index].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[hdr_index].pin = -1; - pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; - pin_irq_hdr_tab[hdr_index].mode = 0; - pin_irq_hdr_tab[hdr_index].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t hdr_index = -1; - exti_trig_type_enum trigger_mode; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - if (enabled == PIN_IRQ_ENABLE) - { - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - irqmap = &pin_irq_map[hdr_index]; - - switch (pin_irq_hdr_tab[hdr_index].mode) - { - case PIN_IRQ_MODE_RISING: - trigger_mode = EXTI_TRIG_RISING; - break; - case PIN_IRQ_MODE_FALLING: - trigger_mode = EXTI_TRIG_FALLING; - break; - case PIN_IRQ_MODE_RISING_FALLING: - trigger_mode = EXTI_TRIG_BOTH; - break; - default: - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - - rcu_periph_clock_enable(RCU_AF); - - /* enable and set interrupt priority */ - nvic_irq_enable(irqmap->irqno, 5U, 0U); - - /* connect EXTI line to GPIO pin */ - gpio_exti_source_select(index->port_src, index->pin_src); - - /* configure EXTI line */ - exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); - exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return -RT_EINVAL; - } - nvic_irq_disable(irqmap->irqno); - } - else - { - return -RT_EINVAL; - } - - return RT_EOK; -} -const static struct rt_pin_ops _gd32_pin_ops = -{ - _pin_mode, - _pin_write, - _pin_read, - _pin_attach_irq, - _pin_detach_irq, - _pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - - result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -rt_inline void pin_irq_hdr(int irqno) -{ - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) -{ - if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) - { - pin_irq_hdr(exti_line); - exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } -} -void EXTI0_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(0); - rt_interrupt_leave(); -} -void EXTI1_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(1); - rt_interrupt_leave(); -} -void EXTI2_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(2); - rt_interrupt_leave(); -} -void EXTI3_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(3); - rt_interrupt_leave(); -} -void EXTI4_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(4); - rt_interrupt_leave(); -} -void EXTI5_9_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(5); - GD32_GPIO_EXTI_IRQHandler(6); - GD32_GPIO_EXTI_IRQHandler(7); - GD32_GPIO_EXTI_IRQHandler(8); - GD32_GPIO_EXTI_IRQHandler(9); - rt_interrupt_leave(); -} -void EXTI10_15_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(10); - GD32_GPIO_EXTI_IRQHandler(11); - GD32_GPIO_EXTI_IRQHandler(12); - GD32_GPIO_EXTI_IRQHandler(13); - GD32_GPIO_EXTI_IRQHandler(14); - GD32_GPIO_EXTI_IRQHandler(15); - rt_interrupt_leave(); -} - -#endif diff --git a/bsp/gd32107c-eval/drivers/drv_gpio.h b/bsp/gd32107c-eval/drivers/drv_gpio.h deleted file mode 100644 index 0cdedb9acb..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_gpio.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __DRV_GPIO_H__ -#define __DRV_GPIO_H__ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#define __GD32_PORT(port) GPIO##port - -#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN) - -#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) -#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) -#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) - -#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) - - - -#ifdef __cplusplus -} -#endif - -#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/gd32107c-eval/drivers/drv_i2c.c b/bsp/gd32107c-eval/drivers/drv_i2c.c deleted file mode 100644 index a4216651cf..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_i2c.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#include "drv_i2c.h" -#include -#include "gd32f10x.h" - -#ifdef RT_USING_I2C - -#include - -#define DBG_TAG "drv.I2C" -#ifdef RT_I2C_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif -#include - -#ifdef RT_USING_I2C_BITOPS - -/*user can change this*/ -#define I2C_BUS_NAME "i2c2" - -/*user should change this to adapt specific board*/ -#define I2C_SCL_PIN GPIO_PIN_4 -#define I2C_SCL_PORT GPIOE -#define I2C_SCL_CLK RCU_GPIOE -#define I2C_SDA_PIN GPIO_PIN_5 -#define I2C_SDA_PORT GPIOE -#define I2C_SDA_CLK RCU_GPIOE - -struct gd32_i2c_bit_data -{ - struct - { - rcu_periph_enum clk; - rt_uint32_t port; - rt_uint32_t pin; - }scl, sda; -}; - -static void gpio_set_sda(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - - if (state) - { - gpio_bit_set(bd->sda.port, bd->sda.pin); - } - else - { - gpio_bit_reset(bd->sda.port, bd->sda.pin); - } -} - -static void gpio_set_scl(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - if (state) - { - gpio_bit_set(bd->scl.port, bd->scl.pin); - } - else - { - gpio_bit_reset(bd->scl.port, bd->scl.pin); - } -} - -static rt_int32_t gpio_get_sda(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->sda.port, bd->sda.pin); -} - -static rt_int32_t gpio_get_scl(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->scl.port, bd->scl.pin); -} - -static void gpio_udelay(rt_uint32_t us) -{ - int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us); - while(i) - { - i--; - } -} - -static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd) -{ - rcu_periph_clock_enable(bd->sda.clk); - rcu_periph_clock_enable(bd->scl.clk); - gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin); - gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin); - - gpio_bit_set(bd->sda.port, bd->sda.pin); - gpio_bit_set(bd->scl.port, bd->scl.pin); -} - -#else /* use hardware i2c */ - -struct gd32_i2c_bus -{ - struct rt_i2c_bus_device parent; - rt_uint32_t i2c_periph; -}; - -static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - if(1 == data_byte){ - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - - /* while there is data to be read */ - while(data_byte) - { - /* wait until the RBNE bit is set and clear it */ - if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) - { - /* read a byte from the EEPROM */ - *p_buffer = i2c_data_receive(i2c_periph); - - /* point to the next location where the byte read will be saved */ - p_buffer++; - - /* decrement the read bytes counter */ - data_byte--; - if(1 == data_byte) - { - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - } - } - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - /* enable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_ENABLE); - - i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT); - - return 0; -} - -static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - /* wait until the transmit data buffer is empty */ - while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE)); - - /* while there is data to be read */ - while(data_byte) - { - i2c_data_transmit(i2c_periph, *p_buffer); - - /* point to the next byte to be written */ - p_buffer++; - - /* decrement the write bytes counter */ - data_byte --; - - /* wait until BTC bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC)); - } - - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - return 0; -} - -static rt_ssize_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) -{ - struct rt_i2c_msg *msg; - rt_uint32_t i; - rt_err_t ret = -RT_ERROR; - - struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus; - - for (i = 0; i < num; i++) - { - msg = &msgs[i]; - - if (msg->flags & RT_I2C_ADDR_10BIT) - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0); - } - else - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0); - } - if (msg->flags & RT_I2C_RD) - { - if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - else - { - if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - } - - ret = i; - -out: - LOG_E("send stop condition\n"); - - return ret; -} - -static const struct rt_i2c_bus_device_ops i2c_ops = -{ - gd32_i2c_xfer, - RT_NULL, - RT_NULL -}; - -#endif /* RT_USING_I2C_BITOPS */ - -int rt_hw_i2c_init(void) -{ -#ifdef RT_USING_I2C_BITOPS - { - static struct rt_i2c_bus_device i2c_device; - static const struct gd32_i2c_bit_data _i2c_bdata = - { - /* SCL */ - { I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN}, - /* SDA */ - { I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN}, - }; - - static const struct rt_i2c_bit_ops _i2c_bit_ops = - { - (void*)&_i2c_bdata, - gpio_set_sda, - gpio_set_scl, - gpio_get_sda, - gpio_get_scl, - gpio_udelay, - 1, - 100 - }; - - drv_i2c_gpio_init(&_i2c_bdata); - - i2c_device.priv = (void *)&_i2c_bit_ops; - rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); - } - -#else /* register hardware I2C */ - -#ifdef RT_USING_I2C0 -#define I2C0_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c0; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */ - gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C0); - /* configure I2C clock */ - i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2); - - i2c_enable(I2C0); - /* enable acknowledge */ - i2c_ack_config(I2C0,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c0.parent.ops = &i2c_ops; - gd32_i2c0.i2c_periph = I2C0; - rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0"); -#endif - -#ifdef RT_USING_I2C1 -#define I2C1_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c1; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */ - gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C1); - /* configure I2C clock */ - i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2); - - i2c_enable(I2C1); - /* enable acknowledge */ - i2c_ack_config(I2C1,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c1.parent.ops = &i2c_ops; - gd32_i2c1.i2c_periph = I2C1; - rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1"); -#endif - -#endif /* RT_USING_I2C_BITOPS */ - - return 0; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); - -#endif -/* end of i2c driver */ diff --git a/bsp/gd32107c-eval/drivers/drv_i2c.h b/bsp/gd32107c-eval/drivers/drv_i2c.h deleted file mode 100644 index fb34ff2b09..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_i2c.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __DRV_I2C__ -#define __DRV_I2C__ - - -#endif diff --git a/bsp/gd32107c-eval/drivers/drv_spi.c b/bsp/gd32107c-eval/drivers/drv_spi.c deleted file mode 100644 index 7c52c37961..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_spi.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#include "drv_spi.h" -#include "gd32f10x.h" -#include - -#if defined(RT_USING_SPI) && defined(RT_USING_PIN) -#include - -#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \ - !defined(RT_USING_SPI2) -#error "Please define at least one SPIx" -#endif - -/* #define DEBUG */ -#ifdef DEBUG -#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) -#else -#define DEBUG_PRINTF(...) -#endif - -/* private rt-thread spi ops function */ -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); - -static struct rt_spi_ops gd32_spi_ops = -{ - configure, - xfer -}; - -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) -{ - spi_parameter_struct spi_init_struct; - - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); - - if(configuration->data_width <= 8) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; - } - else if(configuration->data_width <= 16) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; - } - else - { - return -RT_EIO; - } - - { - rcu_clock_freq_enum spi_src; - rt_uint32_t spi_apb_clock; - rt_uint32_t max_hz; - - max_hz = configuration->max_hz; - - DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS)); - DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2)); - DEBUG_PRINTF("max freq: %d\n", max_hz); - - if (spi_periph == SPI1 || spi_periph == SPI2) - { - spi_src = CK_APB1; - } - else - { - spi_src = CK_APB2; - } - spi_apb_clock = rcu_clock_freq_get(spi_src); - - if(max_hz >= spi_apb_clock/2) - { - spi_init_struct.prescale = SPI_PSC_2; - } - else if (max_hz >= spi_apb_clock/4) - { - spi_init_struct.prescale = SPI_PSC_4; - } - else if (max_hz >= spi_apb_clock/8) - { - spi_init_struct.prescale = SPI_PSC_8; - } - else if (max_hz >= spi_apb_clock/16) - { - spi_init_struct.prescale = SPI_PSC_16; - } - else if (max_hz >= spi_apb_clock/32) - { - spi_init_struct.prescale = SPI_PSC_32; - } - else if (max_hz >= spi_apb_clock/64) - { - spi_init_struct.prescale = SPI_PSC_64; - } - else if (max_hz >= spi_apb_clock/128) - { - spi_init_struct.prescale = SPI_PSC_128; - } - else - { - /* min prescaler 256 */ - spi_init_struct.prescale = SPI_PSC_256; - } - } /* baudrate */ - - switch(configuration->mode & RT_SPI_MODE_3) - { - case RT_SPI_MODE_0: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - break; - case RT_SPI_MODE_1: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; - case RT_SPI_MODE_2: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; - case RT_SPI_MODE_3: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; - break; - } - - /* MSB or LSB */ - if(configuration->mode & RT_SPI_MSB) - { - spi_init_struct.endian = SPI_ENDIAN_MSB; - } - else - { - spi_init_struct.endian = SPI_ENDIAN_LSB; - } - - spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_init_struct.device_mode = SPI_MASTER; - spi_init_struct.nss = SPI_NSS_SOFT; - - spi_init(spi_periph, &spi_init_struct); - - spi_crc_off(spi_periph); - - spi_enable(spi_periph); - - return RT_EOK; -}; - -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) -{ - rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data; - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - struct rt_spi_configuration * config = &device->config; - - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - - /* take CS */ - if(message->cs_take) - { - rt_pin_write(gd32_cs_pin, PIN_LOW); - DEBUG_PRINTF("spi take cs\n"); - } - - { - if(config->data_width <= 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - DEBUG_PRINTF("spi poll transfer start: %d\n", size); - - while(size--) - { - rt_uint8_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /* Todo: replace register read/write by gd32f3 lib */ - /* Wait until the transmit buffer is empty */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - /* Send the byte */ - spi_i2s_data_transmit(spi_periph, data); - - /* Wait until a data is received */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - /* Get the received data */ - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - DEBUG_PRINTF("spi poll transfer finsh\n"); - } - else if(config->data_width <= 16) - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - while(size--) - { - rt_uint16_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - /*Wait until the transmit buffer is empty */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - /* Send the byte */ - spi_i2s_data_transmit(spi_periph, data); - - /*Wait until a data is received */ - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - /* Get the received data */ - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - } - } - - /* release CS */ - if(message->cs_release) - { - rt_pin_write(gd32_cs_pin, PIN_HIGH); - DEBUG_PRINTF("spi release cs\n"); - } - - return message->length; -}; - -int gd32_hw_spi_init(void) -{ - int result = 0; -#ifdef RT_USING_SPI0 - static struct rt_spi_bus spi_bus0; - spi_bus0.parent.user_data = (void *)SPI0; - - result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_SPI0); - /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */ - gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); - gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); - -#endif -#ifdef RT_USING_SPI1 - static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; - - result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_SPI1); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15); - gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14); -#endif -#ifdef RT_USING_SPI2 - static struct rt_spi_bus spi_bus2; - spi_bus2.parent.user_data = (void *)SPI2; - - result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_SPI2); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5); - gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); -#endif - return result; -} -INIT_BOARD_EXPORT(gd32_hw_spi_init); -#endif diff --git a/bsp/gd32107c-eval/drivers/drv_spi.h b/bsp/gd32107c-eval/drivers/drv_spi.h deleted file mode 100644 index 6616fd88eb..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_spi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __DRV_SPI_H__ -#define __DRV_SPI_H__ - - -#endif /* __DRV_SPI_H__ */ diff --git a/bsp/gd32107c-eval/drivers/drv_spi_flash.c b/bsp/gd32107c-eval/drivers/drv_spi_flash.c deleted file mode 100644 index 21a8b1c1d0..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_spi_flash.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include -#include "spi_flash.h" -#include "spi_flash_sfud.h" - -#define SPI_BUS_NAME "spi0" -#define SPI_DEVICE_NAME "spi01" -#define SPI_FLASH_DEVICE_NAME "gd25q" -#define GD25Q_SPI_CS_PIN 67 /* PE3，在 drv_gpio.c 文件 pin_index pins[]中查到 PE3 ç¼–å·ä¸º 67 */ - -static int rt_hw_gd25q40_init(void) -{ - rt_err_t res; - static struct rt_spi_device spi_dev_gd25q; /* SPI设备对象 */ - static rt_base_t gd25q_cs_pin; /* SPI设备CS片选引脚 */ - - gd25q_cs_pin = GD25Q_SPI_CS_PIN; - - rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP); - - res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin); - if (res != RT_EOK) - { - rt_kprintf("rt_spi_bus_attach_device() run failed!\n"); - return res; - } - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_gd25q40_init); - -static int rt_hw_spi_flash_with_sfud_init(void) -{ - if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_DEVICE_NAME, SPI_DEVICE_NAME)) - { - return -RT_ERROR; - } - - return RT_EOK; -} -INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); - -#ifdef RT_USING_DFS -#include - -int mnt_init(void) -{ - if (dfs_mount(SPI_FLASH_DEVICE_NAME, "/", "elm", 0, 0) == 0) - { - rt_kprintf("spi flash mount success !\n"); - } - else - { - rt_kprintf("spi flash mount failed!\n"); - } - - return 0; -} -MSH_CMD_EXPORT(mnt_init, mount spi flash to file system); -#endif diff --git a/bsp/gd32107c-eval/drivers/drv_usart.c b/bsp/gd32107c-eval/drivers/drv_usart.c deleted file mode 100644 index 6dbe467ab8..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_usart.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ -#include -#include -#include -#include - -#ifdef RT_USING_SERIAL - -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \ - !defined(RT_USING_USART2) && !defined(RT_USING_UART3) && \ - !defined(RT_USING_UART4) -#error "Please define at least one UARTx" - -#endif - -#include - -/* GD32 uart driver */ -/* Todo: compress uart info */ -struct gd32_uart -{ - uint32_t uart_periph; - IRQn_Type irqn; - rcu_periph_enum per_clk; - rcu_periph_enum tx_gpio_clk; - rcu_periph_enum rx_gpio_clk; - uint32_t tx_port; - uint16_t tx_pin; - uint32_t rx_port; - uint16_t rx_pin; - - struct rt_serial_device * serial; - char *device_name; -}; - -static void uart_isr(struct rt_serial_device *serial); - -#if defined(RT_USING_USART0) -struct rt_serial_device serial0; - -void USART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial0); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_USART0 */ - -#if defined(RT_USING_USART1) -struct rt_serial_device serial1; - -void USART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial1); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART1 */ - -#if defined(RT_USING_USART2) -struct rt_serial_device serial2; - -void USART2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial2); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART2 */ - -#if defined(RT_USING_UART3) -struct rt_serial_device serial3; - -void UART3_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial3); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART3 */ - -#if defined(RT_USING_UART4) -struct rt_serial_device serial4; - -void UART4_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial4); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* RT_USING_UART4 */ - -static const struct gd32_uart uarts[] = { - #ifdef RT_USING_USART0 - { - USART0, /* uart peripheral index */ - USART0_IRQn, /* uart iqrn */ - RCU_USART0, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIO_PIN_9, /* tx port, tx pin */ - GPIOA, GPIO_PIN_10, /* rx port, rx pin */ - &serial0, - "uart0", - }, - #endif - - #ifdef RT_USING_USART1 - { - USART1, /* uart peripheral index */ - USART1_IRQn, /* uart iqrn */ - RCU_USART1, RCU_GPIOA, RCU_GPIOA, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOA, GPIO_PIN_2, /* tx port, tx pin */ - GPIOA, GPIO_PIN_3, /* rx port, rx pin */ - &serial1, - "uart1", - }, - #endif - - #ifdef RT_USING_USART2 - { - USART2, /* uart peripheral index */ - USART2_IRQn, /* uart iqrn */ - RCU_USART2, RCU_GPIOB, RCU_GPIOB, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOB, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOB, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - &serial2, - "uart2", - }, - #endif - - #ifdef RT_USING_UART3 - { - UART3, /* uart peripheral index */ - UART3_IRQn, /* uart iqrn */ - RCU_UART3, RCU_GPIOC, RCU_GPIOC, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOC, GPIO_PIN_10, /* tx port, tx alternate, tx pin */ - GPIOC, GPIO_PIN_11, /* rx port, rx alternate, rx pin */ - &serial3, - "uart3", - }, - #endif - - #ifdef RT_USING_UART4 - { - UART4, /* uart peripheral index */ - UART4_IRQn, /* uart iqrn */ - RCU_UART4, RCU_GPIOC, RCU_GPIOD, /* periph clock, tx gpio clock, rt gpio clock */ - GPIOC, GPIO_PIN_12, /* tx port, tx alternate, tx pin */ - GPIOD, GPIO_PIN_2, /* rx port, rx alternate, rx pin */ - &serial4, - "uart4", - }, - #endif -}; - - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example: -* - Peripheral's clock enable -* - Peripheral's GPIO Configuration -* - NVIC configuration for UART interrupt request enable -* @param uart: UART handle pointer -* @retval None -*/ -void gd32_uart_gpio_init(struct gd32_uart *uart) -{ - /* enable USART clock */ - rcu_periph_clock_enable(uart->tx_gpio_clk); - rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); - - /* connect port to USARTx_Tx */ - gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ - gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); - - NVIC_SetPriority(uart->irqn, 0); - NVIC_EnableIRQ(uart->irqn); -} - -static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = (struct gd32_uart *)serial->parent.user_data; - - gd32_uart_gpio_init(uart); - - usart_baudrate_set(uart->uart_periph, cfg->baud_rate); - - switch (cfg->data_bits) - { - case DATA_BITS_9: - usart_word_length_set(uart->uart_periph, USART_WL_9BIT); - break; - - default: - usart_word_length_set(uart->uart_periph, USART_WL_8BIT); - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT); - break; - default: - usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT); - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - usart_parity_config(uart->uart_periph, USART_PM_ODD); - break; - case PARITY_EVEN: - usart_parity_config(uart->uart_periph, USART_PM_EVEN); - break; - default: - usart_parity_config(uart->uart_periph, USART_PM_NONE); - break; - } - - usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE); - usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE); - usart_enable(uart->uart_periph); - - return RT_EOK; -} - -static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irqn); - /* disable interrupt */ - usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); - - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irqn); - /* enable interrupt */ - usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); - break; - } - - return RT_EOK; -} - -static int _uart_putc(struct rt_serial_device *serial, char ch) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - usart_data_transmit(uart->uart_periph, ch); - while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - - return 1; -} - -static int _uart_getc(struct rt_serial_device *serial) -{ - int ch; - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - ch = -1; - if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET) - ch = usart_data_receive(uart->uart_periph); - return ch; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) -{ - struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; - - RT_ASSERT(uart != RT_NULL); - - /* UART in mode Receiver */ - if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && - (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - /* Clear RXNE interrupt flag */ - usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE); - } -} - -static const struct rt_uart_ops gd32_uart_ops = -{ - _uart_configure, - _uart_control, - _uart_putc, - _uart_getc -}; - -int gd32_hw_usart_init(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - int i; - - for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) - { - uarts[i].serial->ops = &gd32_uart_ops; - uarts[i].serial->config = config; - - /* register UART device */ - rt_hw_serial_register(uarts[i].serial, - uarts[i].device_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&uarts[i]); - } - - return 0; -} -INIT_BOARD_EXPORT(gd32_hw_usart_init); -#endif diff --git a/bsp/gd32107c-eval/drivers/drv_usart.h b/bsp/gd32107c-eval/drivers/drv_usart.h deleted file mode 100644 index f575ad3810..0000000000 --- a/bsp/gd32107c-eval/drivers/drv_usart.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-08-23 lianzhian first implementation. - */ - -#ifndef __USART_H__ -#define __USART_H__ - - -#endif diff --git a/bsp/gd32107c-eval/drivers/gd32f10x_libopt.h b/bsp/gd32107c-eval/drivers/gd32f10x_libopt.h deleted file mode 100644 index a4dd11b017..0000000000 --- a/bsp/gd32107c-eval/drivers/gd32f10x_libopt.h +++ /dev/null @@ -1,67 +0,0 @@ -/*! - \file gd32f10x_libopt.h - \brief library optional for gd32f10x - \version 2014-12-26, V1.0.0, demo for GD32F10x - \version 2017-06-30, V2.0.0, demo for GD32F10x - \version 2018-07-31, V2.1.0, demo for GD32F10x -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F10X_LIBOPT_H -#define GD32F10X_LIBOPT_H - -#include "gd32f10x_rcu.h" -#include "gd32f10x_adc.h" -#include "gd32f10x_can.h" -#include "gd32f10x_crc.h" -#include "gd32f10x_dac.h" -#include "gd32f10x_dbg.h" -#include "gd32f10x_dma.h" -#include "gd32f10x_exti.h" -#include "gd32f10x_fmc.h" -#include "gd32f10x_fwdgt.h" -#include "gd32f10x_gpio.h" -#include "gd32f10x_i2c.h" -#include "gd32f10x_pmu.h" -#include "gd32f10x_bkp.h" -#include "gd32f10x_rtc.h" -#include "gd32f10x_sdio.h" -#include "gd32f10x_spi.h" -#include "gd32f10x_timer.h" -#include "gd32f10x_usart.h" -#include "gd32f10x_wwdgt.h" -#include "gd32f10x_misc.h" -#include "gd32f10x_exmc.h" -#ifdef GD32F10X_CL -#include "gd32f10x_enet.h" -#endif /* GD32F10X_CL */ - -#endif /* GD32F10X_LIBOPT_H */ diff --git a/bsp/gd32107c-eval/project.ewd b/bsp/gd32107c-eval/project.ewd deleted file mode 100644 index 03d1b7efb8..0000000000 --- a/bsp/gd32107c-eval/project.ewd +++ /dev/null @@ -1,2966 +0,0 @@ - - - 3 - - Debug - - ARM - - 1 - - C-SPY - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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- - - - Filesystem - - - devfs.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c - - - - - dfs_elm.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c - - - - - ff.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c - - - - - ffunicode.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c - - - - - dfs.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs.c - - - - - dfs_file.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_file.c - - - - - dfs_fs.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_fs.c - - - - - dfs_posix.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_posix.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - msh_parse.c - 1 - ..\..\components\finsh\msh_parse.c - - - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - msh_file.c - 1 - ..\..\components\finsh\msh_file.c - - - - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler_up.c - 1 - ..\..\src\scheduler_up.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - Libraries - - - system_gd32f10x.c - 1 - Libraries\CMSIS\GD\GD32F10x\Source\system_gd32f10x.c - - - - - gd32f10x_pmu.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_pmu.c - - - - - gd32f10x_exti.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exti.c - - - - - gd32f10x_wwdgt.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_wwdgt.c - - - - - gd32f10x_can.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_can.c - - - - - gd32f10x_fwdgt.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fwdgt.c - - - - - gd32f10x_crc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_crc.c - - - - - gd32f10x_i2c.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_i2c.c - - - - - gd32f10x_rtc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rtc.c - - - - - gd32f10x_fmc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_fmc.c - - - - - startup_gd32f10x_cl.s - 2 - Libraries\CMSIS\GD\GD32F10x\Source\ARM\startup_gd32f10x_cl.s - - - - - gd32f10x_adc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_adc.c - - - - - gd32f10x_timer.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_timer.c - - - - - gd32f10x_exmc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_exmc.c - - - - - gd32f10x_usart.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_usart.c - - - - - gd32f10x_dac.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dac.c - - - - - gd32f10x_bkp.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_bkp.c - - - - - gd32f10x_sdio.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_sdio.c - - - - - gd32f10x_rcu.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_rcu.c - - - - - gd32f10x_gpio.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_gpio.c - - - - - gd32f10x_dbg.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dbg.c - - - - - gd32f10x_dma.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_dma.c - - - - - gd32f10x_misc.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_misc.c - - - - - gd32f10x_spi.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_spi.c - - - - - gd32f10x_enet.c - 1 - Libraries\GD32F10x_standard_peripheral\Source\gd32f10x_enet.c - - - - - - - - - - - - - - - <Project Info> - - - - - - 0 - 1 - - - - diff --git a/bsp/gd32107c-eval/rtconfig.h b/bsp/gd32107c-eval/rtconfig.h deleted file mode 100644 index 8ec1e6353d..0000000000 --- a/bsp/gd32107c-eval/rtconfig.h +++ /dev/null @@ -1,273 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 - -/* kservice optimization */ - -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FD_MAX 16 -#define RT_USING_DFS_V1 -#define DFS_FILESYSTEMS_MAX 4 -#define DFS_FILESYSTEM_TYPES_MAX 4 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_3 -#define RT_DFS_ELM_USE_LFN 3 -#define RT_DFS_ELM_LFN_UNICODE_0 -#define RT_DFS_ELM_LFN_UNICODE 0 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 2 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 -#define RT_DFS_ELM_REENTRANT -#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_I2C -#define RT_USING_PIN -#define RT_USING_SPI -#define RT_USING_SFUD -#define RT_SFUD_USING_SFDP -#define RT_SFUD_USING_FLASH_INFO_TABLE -#define RT_SFUD_SPI_MAX_HZ 50000000 - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* sensors drivers */ - - -/* touch drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -/* Hardware Drivers Config */ - -/* Onboard Peripheral Drivers */ - -/* On-chip Peripheral Drivers */ - -#define SOC_SERIES_GD32F1 -#define SOC_GD32107C -#define RT_USING_USART0 -#define RT_USING_SPI0 -#define RT_USING_I2C0 - -/* Board extended module Drivers */ - - -#endif diff --git a/bsp/gd32107c-eval/rtconfig.py b/bsp/gd32107c-eval/rtconfig.py deleted file mode 100644 index ade1471bec..0000000000 --- a/bsp/gd32107c-eval/rtconfig.py +++ /dev/null @@ -1,126 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' - - LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - - EXEC_PATH += '/ARM/ARMCC/bin' - print(EXEC_PATH) - - CFLAGS += ' --c99' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config gd32_rom.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH += '/arm/bin/' - POST_ACTION = '' - diff --git a/bsp/gd32107c-eval/template.ewp b/bsp/gd32107c-eval/template.ewp deleted file mode 100644 index 716042958e..0000000000 --- a/bsp/gd32107c-eval/template.ewp +++ /dev/null @@ -1,1889 +0,0 @@ - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/gd32107c-eval/template.uvoptx b/bsp/gd32107c-eval/template.uvoptx deleted file mode 100644 index 9b7e267e46..0000000000 --- a/bsp/gd32107c-eval/template.uvoptx +++ /dev/null @@ -1,177 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f107 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\list\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U58001139 -O14 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(790007A3) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL0300000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F10x_CL -FL040000 -FS08000000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - diff --git a/bsp/gd32107c-eval/template.uvprojx b/bsp/gd32107c-eval/template.uvprojx deleted file mode 100644 index 4d7aabdeb7..0000000000 --- a/bsp/gd32107c-eval/template.uvprojx +++ /dev/null @@ -1,405 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread_gd32f107 - 0x4 - ARM-ADS - 0 - - - GD32F107VC - GigaDevice - GigaDevice.GD32F10x_DFP.2.0.3 - https://gd32mcu.com/data/documents/pack/ - IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F10x_CL -FS08000000 -FL040000 -FP0($$Device:GD32F107VC$Flash\GD32F10x_CL.FLM)) - 0 - $$Device:GD32F107VC$Device\Include\gd32f10x.h - - - - - - - - - - $$Device:GD32F107VC$SVD\GD32F10x\GD32F10x_CL.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\output\ - Project - 1 - 0 - 1 - 1 - 1 - .\list\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x18000 - - - 1 - 0x8000000 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x18000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - ..\..\..\..\GD32F10x_Firmware_Library\CMSIS;..\..\..\..\GD32F10x_Firmware_Library\CMSIS\GD\GD32F10x\Include;..\..\..\..\GD32F10x_Firmware_Library\GD32F10x_standard_peripheral\Include;..\..\..\Utilities;..\ - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - - - - - - - - - - - <Project Info> - - - - - - 0 - 1 - - - - - diff --git a/bsp/gd32303e-eval/.config b/bsp/gd32303e-eval/.config deleted file mode 100644 index bceb791cb6..0000000000 --- a/bsp/gd32303e-eval/.config +++ /dev/null @@ -1,1048 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_INIT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50002 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=4 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -CONFIG_RT_DFS_ELM_USE_LFN_0=y -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set -CONFIG_RT_DFS_ELM_USE_LFN=0 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_MQUEUE is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -# CONFIG_RT_USING_I2C_BITOPS is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -CONFIG_RT_USING_SFUD=y -# CONFIG_RT_SFUD_USING_SFDP is not set -CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y -# CONFIG_RT_SFUD_USING_QSPI is not set -CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 -# CONFIG_RT_DEBUG_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_KTIME is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# -CONFIG_SOC_GD32303E=y -CONFIG_RT_USING_USART0=y -CONFIG_RT_USING_USART1=y -# CONFIG_RT_USING_USART2 is not set -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set -CONFIG_RT_USING_SPI0=y -CONFIG_RT_USING_SPI1=y -# CONFIG_RT_USING_SPI2 is not set -# CONFIG_RT_USING_SPI3 is not set -CONFIG_RT_USING_I2C0=y -# CONFIG_RT_USING_I2C1 is not set diff --git a/bsp/gd32303e-eval/Kconfig b/bsp/gd32303e-eval/Kconfig deleted file mode 100644 index 692f18d25f..0000000000 --- a/bsp/gd32303e-eval/Kconfig +++ /dev/null @@ -1,84 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_GD32303E - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -config RT_USING_USART0 - bool "Using USART0" - select RT_USING_SERIAL - default y - -config RT_USING_USART1 - bool "Using USART1" - select RT_USING_SERIAL - default n - -config RT_USING_USART2 - bool "Using USART2" - select RT_USING_SERIAL - default n - -config RT_USING_UART3 - bool "Using UART3" - select RT_USING_SERIAL - default n - -config RT_USING_UART4 - bool "Using UART4" - select RT_USING_SERIAL - default n - -config RT_USING_SPI0 - bool "Using SPI0" - select RT_USING_SPI - default y - -config RT_USING_SPI1 - bool "Using SPI1" - select RT_USING_SPI - default n - -config RT_USING_SPI2 - bool "Using SPI2" - select RT_USING_SPI - default n - -config RT_USING_SPI3 - bool "Using SPI2 BUS (software simulation)" - select RT_USING_SPI - select RT_USING_SPI_BITOPS - default n - -config RT_USING_I2C0 - bool "Using I2C0" - select RT_USING_I2C - default n - -config RT_USING_I2C1 - bool "Using I2C1" - select RT_USING_I2C - default n - - - diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Include/gd32f30x.h b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Include/gd32f30x.h deleted file mode 100644 index 8a8f43d8e4..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Include/gd32f30x.h +++ /dev/null @@ -1,329 +0,0 @@ -/*! - \file gd32f30x.h - \brief general definitions for GD32F30x -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_H -#define GD32F30X_H - -#ifdef cplusplus - extern "C" { -#endif - -/* define GD32F30x */ -#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL) - /* #define GD32F30X_HD */ - /* #define GD32F30X_XD */ - /* #define GD32F30X_CL */ -#endif /* define GD32F30x */ - -#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL) - #error "Please select the target GD32F30x device in gd32f30x.h file" -#endif /* undefine GD32F30x tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined HXTAL_VALUE -#ifdef GD32F30X_CL -#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ -#else -#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/ -#endif /* HXTAL_VALUE */ -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */ -#if !defined (IRC48M_VALUE) -#define IRC48M_VALUE ((uint32_t)48000000) -#endif /* internal 48MHz RC oscillator value */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* GD32F30x firmware library version number V1.0 */ -#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32F30x_STDPERIPH_VERSION_RC)) - -/* configuration of the Cortex-M4 processor and core peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */ -#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */ -#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ -/* define interrupt number */ -typedef enum IRQn -{ - /* Cortex-M4 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ - RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ - FMC_IRQn = 4, /*!< FMC interrupt */ - RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ - EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ - EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ - EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ - EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ - EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ - DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ - DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ - DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ - DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ - DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ - DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ - ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ -#ifdef GD32F30X_HD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ - TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */ - TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */ - TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - ADC2_IRQn = 47, /*!< ADC2 global interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - SDIO_IRQn = 49, /*!< SDIO global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ -#endif /* GD32F30X_HD */ - -#ifdef GD32F30X_XD - USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - ADC2_IRQn = 47, /*!< ADC2 global interrupt */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - SDIO_IRQn = 49, /*!< SDIO global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ -#endif /* GD32F30X_XD */ - -#ifdef GD32F30X_CL - CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */ - CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */ - USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupts */ - EXMC_IRQn = 48, /*!< EXMC global interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 51, /*!< SPI2 global interrupt */ - UART3_IRQn = 52, /*!< UART3 global interrupt */ - UART4_IRQn = 53, /*!< UART4 global interrupt */ - TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ - ENET_IRQn = 61, /*!< ENET global interrupt */ - ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS global interrupt */ -#endif /* GD32F30X_CL */ - -} IRQn_Type; - -/* includes */ -#include "core_cm4.h" -#include "system_gd32f30x.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ -#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ - -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ -#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ - -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ -#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ -#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ -#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ - -/* advanced peripheral bus 2 memory map */ -#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ - -/* advanced high performance bus 1 memory map */ -#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ -#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ -#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - -/* define marco USE_STDPERIPH_DRIVER */ -#if !defined USE_STDPERIPH_DRIVER -#define USE_STDPERIPH_DRIVER -#endif -#ifdef USE_STDPERIPH_DRIVER -#include "gd32f30x_libopt.h" -#endif /* USE_STDPERIPH_DRIVER */ - -#ifdef cplusplus -} -#endif -#endif diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h deleted file mode 100644 index 97400790de..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h +++ /dev/null @@ -1,58 +0,0 @@ -/*! - \file system_gd32f30x.h - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for - GD32F30x Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32F30X_H -#define SYSTEM_GD32F30X_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit (void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32F30X_H */ diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_cl.s b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_cl.s deleted file mode 100644 index d5e79d0297..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_cl.s +++ /dev/null @@ -1,359 +0,0 @@ -;/*! -; \file startup_gd32f30x_cl.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2017 GigaDevice - -; 2017-02-10, V1.0.1, firmware for GD32F30x -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD 0 ; Reserved - DCD EXMC_IRQHandler ; 64:EXMC - DCD 0 ; Reserved - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD ENET_IRQHandler ; 77:Ethernet - DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_CTC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT CAN0_TX_IRQHandler [WEAK] - EXPORT CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] - EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBFS_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] - EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT ENET_WKUP_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_EWMC_IRQHandler [WEAK] - EXPORT USBFS_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_CTC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -CAN0_TX_IRQHandler -CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_TIMER8_IRQHandler -TIMER0_UP_TIMER9_IRQHandler -TIMER0_TRG_CMT_TIMER10_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBFS_WKUP_IRQHandler -TIMER7_BRK_TIMER11_IRQHandler -TIMER7_UP_TIMER12_IRQHandler -TIMER7_TRG_CMT_TIMER13_IRQHandler -TIMER7_Channel_IRQHandler -EXMC_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -ENET_IRQHandler -ENET_WKUP_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_EWMC_IRQHandler -USBFS_IRQHandler - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s deleted file mode 100644 index 0b0c3855f5..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s +++ /dev/null @@ -1,339 +0,0 @@ -;/*! -; \file startup_gd32f30x_hd.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2017 GigaDevice - -; 2017-02-10, V1.0.1, firmware for GD32F30x -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD HP and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD LP and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup - DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break - DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update - DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_CTC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_IRQHandler [WEAK] - EXPORT TIMER0_UP_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_IRQHandler [WEAK] - EXPORT TIMER7_UP_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_4_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_CTC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_IRQHandler -TIMER0_UP_IRQHandler -TIMER0_TRG_CMT_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -TIMER7_BRK_IRQHandler -TIMER7_UP_IRQHandler -TIMER7_TRG_CMT_IRQHandler -TIMER7_Channel_IRQHandler -ADC2_IRQHandler -EXMC_IRQHandler -SDIO_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_4_IRQHandler - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_xd.s b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_xd.s deleted file mode 100644 index c975afcb32..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_xd.s +++ /dev/null @@ -1,339 +0,0 @@ -;/*! -; \file startup_gd32f30x_xd.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2017 GigaDevice - -; 2017-02-10, V1.0.1, firmware for GD32F30x -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD HP and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD LP and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_CTC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC0_1_IRQHandler [WEAK] - EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK] - EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] - EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBD_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] - EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] - EXPORT TIMER7_Channel_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_4_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_CTC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC0_1_IRQHandler -USBD_HP_CAN0_TX_IRQHandler -USBD_LP_CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_TIMER8_IRQHandler -TIMER0_UP_TIMER9_IRQHandler -TIMER0_TRG_CMT_TIMER10_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBD_WKUP_IRQHandler -TIMER7_BRK_TIMER11_IRQHandler -TIMER7_UP_TIMER12_IRQHandler -TIMER7_TRG_CMT_TIMER13_IRQHandler -TIMER7_Channel_IRQHandler -ADC2_IRQHandler -EXMC_IRQHandler -SDIO_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_4_IRQHandler - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S deleted file mode 100644 index 9d88020123..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S +++ /dev/null @@ -1,257 +0,0 @@ -;/* -; * Copyright (c) 2006-2021, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-05-22 tanek first implementation -; */ - -.syntax unified -.cpu cortex-m4 -.fpu softvfp -.thumb - -.global g_pfnVectors -.global Default_Handler - - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - -g_pfnVectors: - .word _estack // Top of Stack - .word Reset_Handler // Reset Handler - .word NMI_Handler // NMI Handler - .word HardFault_Handler // Hard Fault Handler - .word MemManage_Handler // MPU Fault Handler - .word BusFault_Handler // Bus Fault Handler - .word UsageFault_Handler // Usage Fault Handler - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word SVC_Handler // SVCall Handler - .word DebugMon_Handler // Debug Monitor Handler - .word 0 // Reserved - .word PendSV_Handler // PendSV Handler - .word SysTick_Handler // SysTick Handler - - // external interrupts handler - .word WWDGT_IRQHandler // 16:Window Watchdog Timer - .word LVD_IRQHandler // 17:LVD through EXTI Line detect - .word TAMPER_IRQHandler // 18:Tamper through EXTI Line detect - .word RTC_IRQHandler // 19:RTC through EXTI Line - .word FMC_IRQHandler // 20:FMC - .word RCU_CTC_IRQHandler // 21:RCU and CTC - .word EXTI0_IRQHandler // 22:EXTI Line 0 - .word EXTI1_IRQHandler // 23:EXTI Line 1 - .word EXTI2_IRQHandler // 24:EXTI Line 2 - .word EXTI3_IRQHandler // 25:EXTI Line 3 - .word EXTI4_IRQHandler // 26:EXTI Line 4 - .word DMA0_Channel0_IRQHandler // 27:DMA0 Channel0 - .word DMA0_Channel1_IRQHandler // 28:DMA0 Channel1 - .word DMA0_Channel2_IRQHandler // 29:DMA0 Channel2 - .word DMA0_Channel3_IRQHandler // 30:DMA0 Channel3 - .word DMA0_Channel4_IRQHandler // 31:DMA0 Channel4 - .word DMA0_Channel5_IRQHandler // 32:DMA0 Channel5 - .word DMA0_Channel6_IRQHandler // 33:DMA0 Channel6 - .word ADC0_1_IRQHandler // 34:ADC0 and ADC1 - .word USBD_HP_CAN0_TX_IRQHandler // 35:USBD HP and CAN0 TX - .word USBD_LP_CAN0_RX0_IRQHandler // 36:USBD LP and CAN0 RX0 - .word CAN0_RX1_IRQHandler // 37:CAN0 RX1 - .word CAN0_EWMC_IRQHandler // 38:CAN0 EWMC - .word EXTI5_9_IRQHandler // 39:EXTI5 to EXTI9 - .word TIMER0_BRK_IRQHandler // 40:TIMER0 Break - .word TIMER0_UP_IRQHandler // 41:TIMER0 Update - .word TIMER0_TRG_CMT_IRQHandler // 42:TIMER0 Trigger and Commutation - .word TIMER0_Channel_IRQHandler // 43:TIMER0 Channel Capture Compare - .word TIMER1_IRQHandler // 44:TIMER1 - .word TIMER2_IRQHandler // 45:TIMER2 - .word TIMER3_IRQHandler // 46:TIMER3 - .word I2C0_EV_IRQHandler // 47:I2C0 Event - .word I2C0_ER_IRQHandler // 48:I2C0 Error - .word I2C1_EV_IRQHandler // 49:I2C1 Event - .word I2C1_ER_IRQHandler // 50:I2C1 Error - .word SPI0_IRQHandler // 51:SPI0 - .word SPI1_IRQHandler // 52:SPI1 - .word USART0_IRQHandler // 53:USART0 - .word USART1_IRQHandler // 54:USART1 - .word USART2_IRQHandler // 55:USART2 - .word EXTI10_15_IRQHandler // 56:EXTI10 to EXTI15 - .word RTC_Alarm_IRQHandler // 57:RTC Alarm - .word USBD_WKUP_IRQHandler // 58:USBD Wakeup - .word TIMER7_BRK_IRQHandler // 59:TIMER7 Break - .word TIMER7_UP_IRQHandler // 60:TIMER7 Update - .word TIMER7_TRG_CMT_IRQHandler // 61:TIMER7 Trigger and Commutation - .word TIMER7_Channel_IRQHandler // 62:TIMER7 Channel Capture Compare - .word ADC2_IRQHandler // 63:ADC2 - .word EXMC_IRQHandler // 64:EXMC - .word SDIO_IRQHandler // 65:SDIO - .word TIMER4_IRQHandler // 66:TIMER4 - .word SPI2_IRQHandler // 67:SPI2 - .word UART3_IRQHandler // 68:UART3 - .word UART4_IRQHandler // 69:UART4 - .word TIMER5_IRQHandler // 70:TIMER5 - .word TIMER6_IRQHandler // 71:TIMER6 - .word DMA1_Channel0_IRQHandler // 72:DMA1 Channel0 - .word DMA1_Channel1_IRQHandler // 73:DMA1 Channel1 - .word DMA1_Channel2_IRQHandler // 74:DMA1 Channel2 - .word DMA1_Channel3_4_IRQHandler // 75:DMA1 Channel3 and Channel4 - - .size g_pfnVectors, .-g_pfnVectors - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r1, =_sidata - ldr r2, =_sdata - ldr r3, =_edata - - subs r3, r2 - ble fill_bss_start - -loop_copy_data: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt loop_copy_data - -fill_bss_start: - ldr r1, =__bss_start - ldr r2, =__bss_end - movs r0, 0 - subs r2, r1 - ble startup_enter - -loop_fill_bss: - subs r2, #4 - str r0, [r1, r2] - bgt loop_fill_bss - -startup_enter: - bl SystemInit - bl entry - - /* Exception Handlers */ - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - b . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - b . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - /* IQR Handler */ - .section .text.Default_Handler,"ax",%progbits - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WWDGT_IRQHandler - IRQ LVD_IRQHandler - IRQ TAMPER_IRQHandler - IRQ RTC_IRQHandler - IRQ FMC_IRQHandler - IRQ RCU_CTC_IRQHandler - IRQ EXTI0_IRQHandler - IRQ EXTI1_IRQHandler - IRQ EXTI2_IRQHandler - IRQ EXTI3_IRQHandler - IRQ EXTI4_IRQHandler - IRQ DMA0_Channel0_IRQHandler - IRQ DMA0_Channel1_IRQHandler - IRQ DMA0_Channel2_IRQHandler - IRQ DMA0_Channel3_IRQHandler - IRQ DMA0_Channel4_IRQHandler - IRQ DMA0_Channel5_IRQHandler - IRQ DMA0_Channel6_IRQHandler - IRQ ADC0_1_IRQHandler - IRQ USBD_HP_CAN0_TX_IRQHandler - IRQ USBD_LP_CAN0_RX0_IRQHandler - IRQ CAN0_RX1_IRQHandler - IRQ CAN0_EWMC_IRQHandler - IRQ EXTI5_9_IRQHandler - IRQ TIMER0_BRK_IRQHandler - IRQ TIMER0_UP_IRQHandler - IRQ TIMER0_TRG_CMT_IRQHandler - IRQ TIMER0_Channel_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ I2C0_EV_IRQHandler - IRQ I2C0_ER_IRQHandler - IRQ I2C1_EV_IRQHandler - IRQ I2C1_ER_IRQHandler - IRQ SPI0_IRQHandler - IRQ SPI1_IRQHandler - IRQ USART0_IRQHandler - IRQ USART1_IRQHandler - IRQ USART2_IRQHandler - IRQ EXTI10_15_IRQHandler - IRQ RTC_Alarm_IRQHandler - IRQ USBD_WKUP_IRQHandler - IRQ TIMER7_BRK_IRQHandler - IRQ TIMER7_UP_IRQHandler - IRQ TIMER7_TRG_CMT_IRQHandler - IRQ TIMER7_Channel_IRQHandler - IRQ ADC2_IRQHandler - IRQ EXMC_IRQHandler - IRQ SDIO_IRQHandler - IRQ TIMER4_IRQHandler - IRQ SPI2_IRQHandler - IRQ UART3_IRQHandler - IRQ UART4_IRQHandler - IRQ TIMER5_IRQHandler - IRQ TIMER6_IRQHandler - IRQ DMA1_Channel0_IRQHandler - IRQ DMA1_Channel1_IRQHandler - IRQ DMA1_Channel2_IRQHandler - IRQ DMA1_Channel3_4_IRQHandler diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_cl.s b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_cl.s deleted file mode 100644 index 6be00f7bbb..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_cl.s +++ /dev/null @@ -1,501 +0,0 @@ -;/*! -; \file startup_gd32f30x_cl.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2017 GigaDevice - -; 2017-02-10, V1.0.1, firmware for GD32F30x -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler - DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler - DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD 0 ; 63:Reserved - DCD EXMC_IRQHandler ; 64:EXMC - DCD 0 ; 65:Reserved - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD ENET_IRQHandler ; 77:Ethernet - DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_CTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_CTC_IRQHandler - B RCU_CTC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_TX_IRQHandler - B CAN0_TX_IRQHandler - - PUBWEAK CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX0_IRQHandler - B CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_TIMER8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_TIMER8_IRQHandler - B TIMER0_BRK_TIMER8_IRQHandler - - PUBWEAK TIMER0_UP_TIMER9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_TIMER9_IRQHandler - B TIMER0_UP_TIMER9_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_TIMER10_IRQHandler - B TIMER0_TRG_CMT_TIMER10_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBFS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_WKUP_IRQHandler - B USBFS_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_TIMER11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_TIMER11_IRQHandler - B TIMER7_BRK_TIMER11_IRQHandler - - PUBWEAK TIMER7_UP_TIMER12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_TIMER12_IRQHandler - B TIMER7_UP_TIMER12_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_TIMER13_IRQHandler - B TIMER7_TRG_CMT_TIMER13_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK ENET_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_WKUP_IRQHandler - B ENET_WKUP_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_EWMC_IRQHandler - B CAN1_EWMC_IRQHandler - - PUBWEAK USBFS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_IRQHandler - B USBFS_IRQHandler - END \ No newline at end of file diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s deleted file mode 100644 index 473ca3e053..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s +++ /dev/null @@ -1,463 +0,0 @@ -;/*! -; \file startup_gd32f30x_hd.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2017 GigaDevice - -; 2017-02-10, V1.0.1, firmware for GD32F30x -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler - DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler - DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD HP and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD LP and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break - DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update - DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commucation - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup - DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break - DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update - DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commucation - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and channel4 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_CTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_CTC_IRQHandler - B RCU_CTC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_IRQHandler - B TIMER0_BRK_IRQHandler - - PUBWEAK TIMER0_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_IRQHandler - B TIMER0_UP_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_IRQHandler - B TIMER0_TRG_CMT_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_IRQHandler - B TIMER7_BRK_IRQHandler - - PUBWEAK TIMER7_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_IRQHandler - B TIMER7_UP_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_IRQHandler - B TIMER7_TRG_CMT_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_4_IRQHandler - B DMA1_Channel3_4_IRQHandler - END \ No newline at end of file diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_xd.s b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_xd.s deleted file mode 100644 index 612753a046..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_xd.s +++ /dev/null @@ -1,463 +0,0 @@ -;/*! -; \file startup_gd32f30x_xd.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2017 GigaDevice - -; 2017-02-10, V1.0.1, firmware for GD32F30x -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler - DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler - DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_IRQHandler ; 18:Tamper through EXTI Line detect - DCD RTC_IRQHandler ; 19:RTC through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1 - DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD HP and CAN0 TX - DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD LP and CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 - DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBD_WKUP_IRQHandler ; 58:USBD Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 - DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare - DCD ADC2_IRQHandler ; 63:ADC2 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_IRQHandler ; 70:TIMER5 - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and channel4 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_IRQHandler - B TAMPER_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_CTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_CTC_IRQHandler - B RCU_CTC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC0_1_IRQHandler - B ADC0_1_IRQHandler - - PUBWEAK USBD_HP_CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_HP_CAN0_TX_IRQHandler - B USBD_HP_CAN0_TX_IRQHandler - - PUBWEAK USBD_LP_CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_LP_CAN0_RX0_IRQHandler - B USBD_LP_CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_TIMER8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_TIMER8_IRQHandler - B TIMER0_BRK_TIMER8_IRQHandler - - PUBWEAK TIMER0_UP_TIMER9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_TIMER9_IRQHandler - B TIMER0_UP_TIMER9_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_TIMER10_IRQHandler - B TIMER0_TRG_CMT_TIMER10_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBD_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBD_WKUP_IRQHandler - B USBD_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_TIMER11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_TIMER11_IRQHandler - B TIMER7_BRK_TIMER11_IRQHandler - - PUBWEAK TIMER7_UP_TIMER12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_TIMER12_IRQHandler - B TIMER7_UP_TIMER12_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_TIMER13_IRQHandler - B TIMER7_TRG_CMT_TIMER13_IRQHandler - - PUBWEAK TIMER7_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_Channel_IRQHandler - B TIMER7_Channel_IRQHandler - - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_4_IRQHandler - B DMA1_Channel3_4_IRQHandler - END \ No newline at end of file diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c b/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c deleted file mode 100644 index 7eaeef6ca1..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c +++ /dev/null @@ -1,987 +0,0 @@ -/*! - \file system_gd32f30x.c - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for - GD32F30x Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32f30x.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -/* select a system clock by uncommenting the following line */ -/* use IRC8M */ -//#define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M) -//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) -//#define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000) - -/* use HXTAL(XD series CK_HXTAL = 8M, CL series CK_HXTAL = 25M) */ -//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) -//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) -#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000) - -#define SEL_IRC8M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLL 0x02U - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_IRC8M -uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M; -static void system_clock_8m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; -static void system_clock_48m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; -static void system_clock_72m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; -static void system_clock_108m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M; -static void system_clock_120m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; -static void system_clock_hxtal(void); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; -static void system_clock_48m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; -static void system_clock_108m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL; -static void system_clock_120m_hxtal(void); -#endif /* __SYSTEM_CLOCK_IRC8M */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit (void) -{ - /* FPU settings */ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ -#endif - /* reset the RCU clock configuration to the default reset state */ - /* Set IRC8MEN bit */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* Reset CFG0 and CFG1 registers */ - RCU_CFG0 = 0x00000000U; - RCU_CFG1 = 0x00000000U; - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - /* reset HXTALEN, CKMEN and PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x009f0000U; -#elif defined(GD32F30X_CL) - /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x00ff0000U; -#endif - - /* reset HXTALBPS bit */ - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - - /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ - system_clock_config(); -} -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_IRC8M - system_clock_8m_irc8m(); -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) - system_clock_48m_irc8m(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) - system_clock_108m_irc8m(); -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) - system_clock_120m_irc8m(); - -#elif defined (__SYSTEM_CLOCK_HXTAL) - system_clock_hxtal(); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) - system_clock_48m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) - system_clock_108m_hxtal(); -#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) - system_clock_120m_hxtal(); -#endif /* __SYSTEM_CLOCK_IRC8M */ -} - -#ifdef __SYSTEM_CLOCK_IRC8M -/*! - \brief configure the system clock to 8M by IRC8M - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* select IRC8M as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; - - /* wait until IRC8M is selected as system clock */ - while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) -/*! - \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* LDO output voltage high mode */ - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL12; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* LDO output voltage high mode */ - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL18; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -/*! - \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* LDO output voltage high mode */ - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL27; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M) -/*! - \brief configure the system clock to 120M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - }while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* LDO output voltage high mode */ - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL30; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_HXTAL) -/*! - \brief configure the system clock to HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -/*! - \brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL12; - -#elif defined(GD32F30X_CL) - /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PREDV0SEL_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F30X_HD and GD32F30X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL18; - -#elif defined(GD32F30X_CL) - /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PREDV0SEL_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F30X_HD and GD32F30X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -/*! - \brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL27; - -#elif defined(GD32F30X_CL) - /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PLLPRESEL_HXTAL | RCU_PREDV0SEL_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } -#endif /* GD32F30X_HD and GD32F30X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL) -/*! - \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - /* select HXTAL/2 as clock source */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_CFG0_PREDV0); - - /* CK_PLL = (CK_HXTAL/2) * 30 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= RCU_PLL_MUL30; - -#elif defined(GD32F30X_CL) - /* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){ - } -#endif /* GD32F30X_HD and GD32F30X_XD */ - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* enable the high-drive to extend the clock frequency to 120 MHz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} -#endif /* __SYSTEM_CLOCK_IRC8M */ - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate (void) -{ - uint32_t sws; - uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src; -#ifdef GD32F30X_CL - uint32_t predv0, predv1, pll1mf; -#endif /* GD32F30X_CL */ - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if (RCU_PLLSRC_HXTAL_IRC48M == pllsel) { - /* PLL clock source is HXTAL or IRC48M */ - pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); - - if(RCU_PLLPRESRC_HXTAL == pllpresel){ - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - }else{ - /* PLL clock source is IRC48 */ - ck_src = IRC48M_VALUE; - } - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); - /* PREDV0 input source clock divided by 2 */ - if(RCU_CFG0_PREDV0 == predv0sel){ - ck_src = HXTAL_VALUE/2U; - } -#elif defined(GD32F30X_CL) - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ - pll1mf = 20U; - } - ck_src = (ck_src/predv1)*pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; -#endif /* GD32F30X_HD and GD32F30X_XD */ - }else{ - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE/2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ - pllmf |= 0x10U; - } - if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){ - pllmf |= 0x20U; - } - - if( pllmf >= 15U){ - pllmf += 1U; - }else{ - pllmf += 2U; - } - if(pllmf > 61U){ - pllmf = 63U; - } - SystemCoreClock = ck_src*pllmf; - #ifdef GD32F30X_CL - if(15U == pllmf){ - SystemCoreClock = ck_src*6U + ck_src/2U; - } - #endif /* GD32F30X_CL */ - - break; - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } - -} diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/core_cm4.h b/bsp/gd32303e-eval/Libraries/CMSIS/core_cm4.h deleted file mode 100644 index d82841442c..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/core_cm4.h +++ /dev/null @@ -1,1790 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/core_cm4_simd.h b/bsp/gd32303e-eval/Libraries/CMSIS/core_cm4_simd.h deleted file mode 100644 index f9bceff1e5..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/core_cm4_simd.h +++ /dev/null @@ -1,697 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* not yet supported */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_SIMD_H */ diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32303e-eval/Libraries/CMSIS/core_cmFunc.h deleted file mode 100644 index 3c932e0d6e..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32303e-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32303e-eval/Libraries/CMSIS/core_cmInstr.h deleted file mode 100644 index 597e64df04..0000000000 --- a/bsp/gd32303e-eval/Libraries/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h deleted file mode 100644 index 6c8b6d37db..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h +++ /dev/null @@ -1,371 +0,0 @@ -/*! - \file gd32f30x_adc.h - \brief definitions for the ADC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_ADC_H -#define GD32F30X_ADC_H - -#include "gd32f30x.h" - -/* ADC definitions */ -#define ADC0 ADC_BASE -#define ADC1 (ADC_BASE + 0x400U) -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define ADC2 (ADC_BASE + 0x1800U) -#endif - -/* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - -/* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ -#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ - -/* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ -#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< oversampling shift */ - - -/* constants definitions */ -/* adc_stat register value */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ - -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ - -#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ -#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ -#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ -#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ - -/* adc_ctl1 register value */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ - -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< timer 2 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< timer 3 CC3 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< timer 7 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - -#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< timer 2 CC0 event select */ -#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< timer 1 CC2 event select */ -#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< timer 7 CC0 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< timer 7 TRGO event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< timer 4 CC0 event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */ - -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< timer 1 CC0 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< timer 2 CC3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< timer 3 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< timer 7 CC3 event select */ -#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - -#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ -#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ -#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< timer 3 CC2 event select */ -#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< timer 7 CC1 event select */ -#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< timer 7 CC3 event select */ -#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< timer 4 TRGO event select */ -#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< timer 4 CC3 event select */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - -/* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - -/* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - -/* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - -/* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - -/* adc_ovsampctl register value */ -#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ -#define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ - -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ - -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ - -/* ADC interrupt */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* function declarations */ -/* reset ADC */ -void adc_deinit(uint32_t adc_periph); -/* enable ADC interface */ -void adc_enable(uint32_t adc_periph); -/* disable ADC interface */ -void adc_disable(uint32_t adc_periph); -/* ADC calibration and reset calibration */ -void adc_calibration_enable(uint32_t adc_periph); -/* enable DMA request */ -void adc_dma_mode_enable(uint32_t adc_periph); -/* disable DMA request */ -void adc_dma_mode_disable(uint32_t adc_periph); -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); - -/* configure ADC resolution */ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); - -/* configure the ADC mode */ -void adc_mode_config(uint32_t mode); -/* enable or disable ADC special function */ -void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); -/* enable ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); - -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); -/* read the last ADC0 and ADC1 conversion result data in sync mode */ -uint32_t adc_sync_mode_convert_value_read(void); - -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); - -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); - -/* configure ADC oversample mode */ -void adc_oversample_mode_config(uint32_t adc_periph , uint8_t mode , uint16_t shift , uint8_t ratio); -/* enable ADC oversample mode */ -void adc_oversample_mode_enable(uint32_t adc_periph); -/* disable ADC oversample mode */ -void adc_oversample_mode_disable(uint32_t adc_periph); -#endif /* GD32F30X_ADC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h deleted file mode 100644 index 45ed9444c7..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h +++ /dev/null @@ -1,218 +0,0 @@ -/*! - \file gd32f30x_bkp.h - \brief definitions for the BKP -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.2, firmware for GD32F30x -*/ - -#ifndef GD32F30X_BKP_H -#define GD32F30X_BKP_H - -#include "gd32f30x.h" - -/* BKP definitions */ -#define BKP BKP_BASE /*!< BKP base address */ - -/* registers definitions */ -#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ -#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ -#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ -#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ -#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ -#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ -#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ -#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ -#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ -#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ -#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ -#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ -#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ -#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ -#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ -#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ -#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ -#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ -#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ -#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ -#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ -#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ -#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ -#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ -#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ -#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ -#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ -#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ -#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ -#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ -#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ -#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ -#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ -#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ -#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ -#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ -#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ -#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ -#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ -#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ -#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ -#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ -#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ -#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ -#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ - -/* bits definitions */ -/* BKP_DATA */ -#define BKP_DATA BITS(0,15) /*!< backup data */ - -/* BKP_OCTL */ -#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ -#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ -#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ -#define BKP_OCTL_CCOSEL BIT(14) /*!< RTC clock output selection */ -#define BKP_OCTL_CALDIR BIT(15) /*!< RTC clock calibration direction */ - -/* BKP_TPCTL */ -#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ -#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ - -/* BKP_TPCS */ -#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ -#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ -#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ -#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ -#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ - -/* constants definitions */ -/* BKP register */ -#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) -#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) - -/* get data of BKP data register */ -#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - -/* RTC clock calibration value */ -#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/* RTC output selection */ -#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ -#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ - -/* RTC clock output selection */ -#define RTC_CLOCK_DIV_64 ((uint16_t)0x0000U) /*!< RTC clock div 64 */ -#define RTC_CLOCK_DIV_1 ((uint16_t)0x4000U) /*!< RTC clock div 1 */ - -/* RTC clock calibration direction */ -#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */ -#define RTC_CLOCK_SPEED_UP ((uint16_t)0x8000U) /*!< RTC clock speed up */ - -/* tamper pin active level */ -#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ -#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ - -/* tamper flag */ -#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ - -/* tamper interrupt flag */ -#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ - -/* BKP data register number */ -typedef enum -{ - BKP_DATA_0 = 1, /*!< BKP data register 0 */ - BKP_DATA_1, /*!< BKP data register 1 */ - BKP_DATA_2, /*!< BKP data register 2 */ - BKP_DATA_3, /*!< BKP data register 3 */ - BKP_DATA_4, /*!< BKP data register 4 */ - BKP_DATA_5, /*!< BKP data register 5 */ - BKP_DATA_6, /*!< BKP data register 6 */ - BKP_DATA_7, /*!< BKP data register 7 */ - BKP_DATA_8, /*!< BKP data register 8 */ - BKP_DATA_9, /*!< BKP data register 9 */ - BKP_DATA_10, /*!< BKP data register 10 */ - BKP_DATA_11, /*!< BKP data register 11 */ - BKP_DATA_12, /*!< BKP data register 12 */ - BKP_DATA_13, /*!< BKP data register 13 */ - BKP_DATA_14, /*!< BKP data register 14 */ - BKP_DATA_15, /*!< BKP data register 15 */ - BKP_DATA_16, /*!< BKP data register 16 */ - BKP_DATA_17, /*!< BKP data register 17 */ - BKP_DATA_18, /*!< BKP data register 18 */ - BKP_DATA_19, /*!< BKP data register 19 */ - BKP_DATA_20, /*!< BKP data register 20 */ - BKP_DATA_21, /*!< BKP data register 21 */ - BKP_DATA_22, /*!< BKP data register 22 */ - BKP_DATA_23, /*!< BKP data register 23 */ - BKP_DATA_24, /*!< BKP data register 24 */ - BKP_DATA_25, /*!< BKP data register 25 */ - BKP_DATA_26, /*!< BKP data register 26 */ - BKP_DATA_27, /*!< BKP data register 27 */ - BKP_DATA_28, /*!< BKP data register 28 */ - BKP_DATA_29, /*!< BKP data register 29 */ - BKP_DATA_30, /*!< BKP data register 30 */ - BKP_DATA_31, /*!< BKP data register 31 */ - BKP_DATA_32, /*!< BKP data register 32 */ - BKP_DATA_33, /*!< BKP data register 33 */ - BKP_DATA_34, /*!< BKP data register 34 */ - BKP_DATA_35, /*!< BKP data register 35 */ - BKP_DATA_36, /*!< BKP data register 36 */ - BKP_DATA_37, /*!< BKP data register 37 */ - BKP_DATA_38, /*!< BKP data register 38 */ - BKP_DATA_39, /*!< BKP data register 39 */ - BKP_DATA_40, /*!< BKP data register 40 */ - BKP_DATA_41, /*!< BKP data register 41 */ -}bkp_data_register_enum; - -/* function declarations */ -/* reset BKP registers */ -void bkp_deinit(void); -/* write BKP data register */ -void bkp_write_data(bkp_data_register_enum register_number, uint16_t data); -/* read BKP data register */ -uint16_t bkp_read_data(bkp_data_register_enum register_number); - -/* RTC related functions */ -/* enable RTC clock calibration output */ -void bkp_rtc_calibration_output_enable(void); -/* disable RTC clock calibration output */ -void bkp_rtc_calibration_output_disable(void); -/* enable RTC alarm or second signal output */ -void bkp_rtc_signal_output_enable(void); -/* disable RTC alarm or second signal output */ -void bkp_rtc_signal_output_disable(void); -/* RTC output selection */ -void bkp_rtc_output_select(uint16_t outputsel); -/* RTC clock output selection */ -void bkp_rtc_clock_output_select(uint16_t clocksel); -/* RTC clock calibration direction */ -void bkp_rtc_clock_calibration_direction(uint16_t direction); -/* set RTC clock calibration value */ -void bkp_rtc_calibration_value_set(uint8_t value); - -/* tamper pin related functions */ -/* enable tamper pin detection */ -void bkp_tamper_detection_enable(void); -/* disable tamper pin detection */ -void bkp_tamper_detection_disable(void); -/* set tamper pin active level */ -void bkp_tamper_active_level_set(uint16_t level); -/* enable tamper pin interrupt */ -void bkp_tamper_interrupt_enable(void); -/* disable tamper pin interrupt */ -void bkp_tamper_interrupt_disable(void); - -/* flag functions */ -/* get BKP flag state */ -FlagStatus bkp_flag_get(uint16_t flag); -/* clear BKP flag state */ -void bkp_flag_clear(uint16_t flag); -/* get BKP interrupt flag state */ -FlagStatus bkp_interrupt_flag_get(uint16_t flag); -/* clear BKP interrupt flag state */ -void bkp_interrupt_flag_clear(uint16_t flag); - -#endif /* GD32F30X_BKP_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_can.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_can.h deleted file mode 100644 index 9ce47e7287..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_can.h +++ /dev/null @@ -1,680 +0,0 @@ -/*! - \file gd32f30x_can.h - \brief definitions for the CAN -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_CAN_H -#define GD32F30X_CAN_H - -#include "gd32f30x.h" - -/* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ - -/* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ - -/* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ - -/* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ - -/* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ - -/* bits definitions */ -/* CAN_CTL */ -#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ -#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ -#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ -#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ -#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ -#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ -#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ -#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ -#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ -#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ - -/* CAN_STAT */ -#define CAN_STAT_IWS BIT(0) /*!< initial working state */ -#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ -#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ -#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ -#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ -#define CAN_STAT_TS BIT(8) /*!< transmitting state */ -#define CAN_STAT_RS BIT(9) /*!< receiving state */ -#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ -#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ - -/* CAN_TSTAT */ -#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ -#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ -#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ -#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ -#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ -#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ -#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ -#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ -#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ -#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ -#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ -#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ -#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ -#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ -#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ -#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ -#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ -#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ -#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ -#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ -#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - -/* CAN_RFIFO0 */ -#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ -#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ -#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - -/* CAN_RFIFO1 */ -#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ -#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ -#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ - -/* CAN_INTEN */ -#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ -#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ -#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ -#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ -#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ -#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ -#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ -#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ -#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ - -/* CAN_ERR */ -#define CAN_ERR_WERR BIT(0) /*!< warning error */ -#define CAN_ERR_PERR BIT(1) /*!< passive error */ -#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ -#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ -#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ -#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ - -/* CAN_BT */ -#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ -#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ -#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ -#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ -#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ -#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - -/* CAN_TMIx */ -#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ -#define CAN_TMI_FT BIT(1) /*!< frame type */ -#define CAN_TMI_FF BIT(2) /*!< frame format */ -#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_TMPx */ -#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ -#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_TMDATA0x */ -#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ -#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ -#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ -#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ - -/* CAN_TMDATA1x */ -#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ -#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ -#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ -#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ - -/* CAN_RFIFOMIx */ -#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ -#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ -#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_RFIFOMPx */ -#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ -#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ -#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_RFIFOMDATA0x */ -#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ -#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ -#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ -#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ - -/* CAN_RFIFOMDATA1x */ -#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ -#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ -#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ -#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ - -/* CAN_FCTL */ -#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ -#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ - -/* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ - -/* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ - -/* CAN_FAFIFO */ -#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ - -/* CAN_FW */ -#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ - -/* CAN_FxDATAy */ -#define CAN_FD BITS(0,31) /*!< filter data */ - -/* consts definitions */ -/* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) -#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ -#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ -#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ -#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ -#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ - -/* CAN flags */ -typedef enum -{ - /* flags in TSTAT register */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ - /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ - /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ - /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -}can_flag_enum; - -/* CAN interrupt flags */ -typedef enum -{ - /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ - /* interrupt flags in TSTAT register */ - CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ - CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ - CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ -}can_interrupt_flag_enum; - -/* CAN initiliaze parameters struct */ -typedef struct -{ - uint8_t working_mode; /*!< CAN working mode */ - uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ - uint8_t time_segment_1; /*!< time segment 1 */ - uint8_t time_segment_2; /*!< time segment 2 */ - ControlStatus time_triggered; /*!< time triggered communication mode */ - ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ - ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode */ - ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ - ControlStatus trans_fifo_order; /*!< transmit FIFO order */ - uint16_t prescaler; /*!< baudrate prescaler */ -}can_parameter_struct; - -/* CAN transmit message struct */ -typedef struct -{ - uint32_t tx_sfid; /*!< standard format frame identifier */ - uint32_t tx_efid; /*!< extended format frame identifier */ - uint8_t tx_ff; /*!< format of frame, standard or extended format */ - uint8_t tx_ft; /*!< type of frame, data or remote */ - uint8_t tx_dlen; /*!< data length */ - uint8_t tx_data[8]; /*!< transmit data */ -}can_trasnmit_message_struct; - -/* CAN receive message struct */ -typedef struct -{ - uint32_t rx_sfid; /*!< standard format frame identifier */ - uint32_t rx_efid; /*!< extended format frame identifier */ - uint8_t rx_ff; /*!< format of frame, standard or extended format */ - uint8_t rx_ft; /*!< type of frame, data or remote */ - uint8_t rx_dlen; /*!< data length */ - uint8_t rx_data[8]; /*!< receive data */ - uint8_t rx_fi; /*!< filtering index */ -} can_receive_message_struct; - -/* CAN filter parameters struct */ -typedef struct -{ - uint16_t filter_list_high; /*!< filter list number high bits*/ - uint16_t filter_list_low; /*!< filter list number low bits */ - uint16_t filter_mask_high; /*!< filter mask number high bits */ - uint16_t filter_mask_low; /*!< filter mask number low bits */ - uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ - uint16_t filter_number; /*!< filter number */ - uint16_t filter_mode; /*!< filter mode, list or mask */ - uint16_t filter_bits; /*!< filter scale */ - ControlStatus filter_enable; /*!< filter work or not */ -}can_filter_parameter_struct; - -/* CAN errors */ -typedef enum -{ - CAN_ERROR_NONE = 0, /*!< no error */ - CAN_ERROR_FILL, /*!< fill error */ - CAN_ERROR_FORMATE, /*!< format error */ - CAN_ERROR_ACK, /*!< ACK error */ - CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ - CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ - CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG, /*!< software configure */ -}can_error_enum; - -/* transmit states */ -typedef enum -{ - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ -}can_transmit_state_enum; - -/* CAN baudrate prescaler*/ -#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) - -/* CAN bit segment 1*/ -#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) - -/* CAN bit segment 2*/ -#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) - -/* CAN resynchronization jump width*/ -#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) - -/* CAN communication mode*/ -#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) - -/* CAN FDATA high 16 bits */ -#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) - -/* CAN FDATA low 16 bits */ -#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) - -/* CAN1 filter start bank_number*/ -#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) - -/* CAN transmit mailbox extended identifier*/ -#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) - -/* CAN transmit mailbox standard identifier*/ -#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) - -/* transmit data byte 0 */ -#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 1 */ -#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 2 */ -#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 3 */ -#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* transmit data byte 4 */ -#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 5 */ -#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 6 */ -#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 7 */ -#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* receive mailbox extended identifier*/ -#define RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) - -/* receive mailbox standrad identifier*/ -#define RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) - -/* receive data length */ -#define RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) - -/* the index of the filter by which the frame is passed */ -#define RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 0 */ -#define RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 1 */ -#define RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 2 */ -#define RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 3 */ -#define RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* receive data byte 4 */ -#define RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 5 */ -#define RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 6 */ -#define RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 7 */ -#define RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* CAN errors */ -#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ - -#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ - -/* CAN communication mode */ -#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ -#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ -#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ -#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ - -/* CAN resynchronisation jump width */ -#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ - -/* CAN time segment 1 */ -#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ -#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ -#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ -#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ -#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ -#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ -#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ -#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ -#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ - -/* CAN time segment 2 */ -#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ - -/* CAN mailbox number */ -#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ -#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ -#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ -#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ - -/* CAN frame format */ -#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ -#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ - -/* CAN receive fifo */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ - -/* frame number of receive fifo */ -#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ - -#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ -#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ - -/* CAN working mode */ -#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ -#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ -#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ - -/* filter bits */ -#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ -#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ - -/* filter mode */ -#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ -#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ - -/* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) - -/* frame type */ -#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ -#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ - -/* CAN timeout */ -#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ - -/* interrupt enable bits */ -#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ -#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ -#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ -#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ -#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ -#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ -#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ -#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ -#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ -#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ - -/* function declarations */ -/* deinitialize CAN */ -void can_deinit(uint32_t can_periph); -/* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); - -/* set can1 fliter start bank number */ -void can1_filter_start_bank(uint8_t start_bank); -/* enable functions */ -/* CAN debug freeze enable */ -void can_debug_freeze_enable(uint32_t can_periph); -/* CAN debug freeze disable */ -void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time triggle mode enable */ -void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time triggle mode disable */ -void can_time_trigger_mode_disable(uint32_t can_periph); - -/* transmit functions */ -/* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); -/* get CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); -/* stop CAN transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); -/* CAN release fifo */ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive message length */ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); -/* CAN working mode */ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); -/* CAN wakeup from sleep mode */ -ErrStatus can_wakeup(uint32_t can_periph); - -/* CAN get error */ -can_error_enum can_error_get(uint32_t can_periph); -/* get CAN receive error number */ -uint8_t can_receive_error_number_get(uint32_t can_periph); -/* get CAN transmit error number */ -uint8_t can_transmit_error_number_get(uint32_t can_periph); - -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* CAN get flag state */ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); -/* CAN clear flag state */ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag); -/* CAN get interrupt flag state */ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); -/* CAN clear interrupt flag state */ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); - -#endif /* GD32F30X_CAN_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h deleted file mode 100644 index 9a258c0a3e..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h +++ /dev/null @@ -1,55 +0,0 @@ -/*! - \file gd32f30x_crc.h - \brief definitions for the CRC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef GD32F30X_CRC_H -#define GD32F30X_CRC_H - -#include "gd32f30x.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ - - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* reset data register to the value of initializaiton data register */ -void crc_data_register_reset(void); -/* read the data register */ -uint32_t crc_data_register_read(void); - -/* read the free data register */ -uint8_t crc_free_data_register_read(void); -/* write the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* CRC calculate a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* CRC calculate a 32-bit data array */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32F30X_CRC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h deleted file mode 100644 index ad4e3c2a6b..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h +++ /dev/null @@ -1,161 +0,0 @@ -/*! - \file gd32f30x_ctc.h - \brief definitions for the CTC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_CTC_H -#define GD32F30X_CTC_H - -#include "gd32f30x.h" - -/* CTC definitions */ -#define CTC CTC_BASE - -/* registers definitions */ -#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ -#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ -#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ -#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ - -/* bits definitions */ -/* CTC_CTL0 */ -#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ -#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ -#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ -#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ -#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ -#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ -#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ -#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ - -/* CTC_CTL1 */ -#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ -#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ -#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ -#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ - -/* CTC_STAT */ -#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ -#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ -#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ -#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ -#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ -#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ -#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ -#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ -#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ - -/* CTC_INTC */ -#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ -#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ -#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ -#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ - -/* constants definitions */ -/* hardware automatically trim mode definitions */ -#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ -#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ - -/* reference signal source polarity definitions */ -#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ -#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ - -/* reference signal source selection definitions */ -#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ -#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ -#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBDSOF or USBFSSOF selected */ - -/* reference signal source prescaler definitions */ -#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ -#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ -#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ -#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ -#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ -#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ -#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ -#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ - -/* CTC interrupt enable definitions */ -#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ -#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ -#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ -#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ - -/* CTC interrupt source definitions */ -#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ -#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ -#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ -#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ -#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ - -/* CTC flag definitions */ -#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ -#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ -#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ -#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ -#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ - -/* function declarations */ -/* reset ctc clock trim controller */ -void ctc_deinit(void); - -/* enable the CTC interrupt */ -void ctc_interrupt_enable(uint32_t ctc_interrupt); -/* disable the CTC interrupt */ -void ctc_interrupt_disable(uint32_t ctc_interrupt); -/* get CTC interrupt flag */ -FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt); -/* clear CTC interrupt flag */ -void ctc_interrupt_flag_clear(uint32_t ctc_interrupt); - -/* get CTC flag */ -FlagStatus ctc_flag_get(uint32_t ctc_flag); -/* clear CTC flag */ -void ctc_flag_clear(uint32_t ctc_flag); - -/* configure the IRC48M trim value */ -void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value); -/* generate software reference source sync pulse */ -void ctc_software_refsource_pulse_generate(void); -/* configure hardware automatically trim mode */ -void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode); - -/* enable CTC trim counter */ -void ctc_counter_enable(void); -/* disable CTC trim counter */ -void ctc_counter_disable(void); - -/* configure reference signal source polarity */ -void ctc_refsource_polarity_config(uint32_t ctc_polarity); -/* select reference signal source */ -void ctc_refsource_signal_select(uint32_t ctc_refs); -/* configure reference signal source prescaler */ -void ctc_refsource_prescaler_config(uint32_t ctc_prescaler); -/* configure clock trim base limit value */ -void ctc_clock_limit_value_config(uint8_t ctc_limit_value); -/* configure CTC counter reload value */ -void ctc_counter_reload_value_config(uint16_t ctc_reload_value); - -/* read CTC counter capture value when reference sync pulse occurred */ -uint16_t ctc_counter_capture_value_read(void); -/* read CTC trim counter direction when reference sync pulse occurred */ -FlagStatus ctc_counter_direction_read(void); -/* read CTC counter reload value */ -uint16_t ctc_counter_reload_value_read(void); -/* read the IRC48M trim value */ -uint8_t ctc_irc48m_trim_value_read(void); - -#endif /* GD32F30X_CTC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h deleted file mode 100644 index 804c725ba2..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h +++ /dev/null @@ -1,220 +0,0 @@ -/*! - \file gd32f30x_dac.h - \brief definitions for the DAC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_DAC_H -#define GD32F30X_DAC_H - -#include "gd32f30x.h" - -/* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 0U -#define DAC1 1U - -/* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ - -/* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - -/* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - -/* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - -/* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - -/* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - -/* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - -/* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - -/* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - -/* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - -/* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - -/* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - -/* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ - -/* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ - -/* constants definitions */ -/* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ -#elif defined(GD32F30X_CL) -#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ -#endif /* GD32F30X_HD and GD32F30X_XD */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - -/* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - -/* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ - -/* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ - -/* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ - -/* function declarations */ -/* deinitialize DAC */ -void dac_deinit(void); -/* enable DAC */ -void dac_enable(uint32_t dac_periph); -/* disable DAC */ -void dac_disable(uint32_t dac_periph); -/* enable DAC DMA */ -void dac_dma_enable(uint32_t dac_periph); -/* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); -/* enable DAC output buffer */ -void dac_output_buffer_enable(uint32_t dac_periph); -/* disable DAC output buffer */ -void dac_output_buffer_disable(uint32_t dac_periph); -/* enable DAC trigger */ -void dac_trigger_enable(uint32_t dac_periph); -/* disable DAC trigger */ -void dac_trigger_disable(uint32_t dac_periph); -/* enable DAC software trigger */ -void dac_software_trigger_enable(uint32_t dac_periph); -/* disable DAC software trigger */ -void dac_software_trigger_disable(uint32_t dac_periph); - -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); -/* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); -/* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); -/* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); - -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); - -/* enable DAC concurrent mode */ -void dac_concurrent_enable(void); -/* disable DAC concurrent mode */ -void dac_concurrent_disable(void); -/* enable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_enable(void); -/* disable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_disable(void); -/* enable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_enable(void); -/* disable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_disable(void); - -#endif /* GD32F30X_DAC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h deleted file mode 100644 index db18eec510..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h +++ /dev/null @@ -1,119 +0,0 @@ -/*! - \file gd32f30x_dbg.h - \brief definitions for the DBG -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef GD32F30X_DBG_H -#define GD32F30X_DBG_H - -#include "gd32f30x.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL0 */ -#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ -#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ -#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ -#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ -#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ -#define DBG_CTL0_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ -#define DBG_CTL0_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ -#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL0_TIMER4_HOLD BIT(17) /*!< hold TIMER4 counter when core is halted */ -#define DBG_CTL0_TIMER5_HOLD BIT(18) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL0_TIMER6_HOLD BIT(19) /*!< hold TIMER6 counter when core is halted */ -#define DBG_CTL0_TIMER7_HOLD BIT(20) /*!< hold TIMER7 counter when core is halted */ -#ifdef GD32F30X_CL -#define DBG_CTL0_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ -#endif /* GD32F30X_CL */ -#ifndef GD32F30X_HD -#define DBG_CTL0_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ -#define DBG_CTL0_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ -#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ -#define DBG_CTL0_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ -#define DBG_CTL0_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ -#define DBG_CTL0_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ -#endif /* GD32F30X_HD */ - -/* constants definitions */ -#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ - -typedef enum -{ - DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ - DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ - DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ - DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ - DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ - DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ - DBG_TIMER7_HOLD = BIT(20), /*!< hold TIMER7 counter when core is halted */ -#ifdef GD32F30X_CL - DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ -#endif /* GD32F30X_CL */ -#ifndef GD32F30X_HD - DBG_TIMER11_HOLD = BIT(25), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = BIT(26), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = BIT(27), /*!< hold TIMER13 counter when core is halted */ - DBG_TIMER8_HOLD = BIT(28), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = BIT(29), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */ -#endif /* GD32F30X_HD */ -}dbg_periph_enum; - -#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) -#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ -#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ -#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ -#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ - -/* function declarations */ -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -/* enable trace pin assignment */ -void dbg_trace_pin_enable(void); -/* disable trace pin assignment */ -void dbg_trace_pin_disable(void); -/* set trace pin mode */ -void dbg_trace_pin_mode_set(uint32_t trace_mode); - -#endif /* GD32F30X_DBG_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h deleted file mode 100644 index ff83bde6cc..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h +++ /dev/null @@ -1,259 +0,0 @@ -/*! - \file gd32f30x_dma.h - \brief definitions for the DMA -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_DMA_H -#define GD32F30X_DMA_H - -#include "gd32f30x.h" - -/* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ - -/* registers definitions */ -#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ - -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ - -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ - -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ - -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ - -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ - -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ - -#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL, x=0..6 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT,x=0..6 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR,x=0..6 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR,x=0..6 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA Channel0 */ - DMA_CH1, /*!< DMA Channel1 */ - DMA_CH2, /*!< DMA Channel2 */ - DMA_CH3, /*!< DMA Channel3 */ - DMA_CH4, /*!< DMA Channel4 */ - DMA_CH5, /*!< DMA Channel5 */ - DMA_CH6 /*!< DMA Channel6 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ - -} dma_parameter_struct; - -#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_register address */ -#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ -/* circular mode */ -#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000000U) /*!< circular mode disable */ -#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000001U) /*!< circular mode enable */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ - -/* memory to memory mode */ -#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) -#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ - - - -/* function declarations */ -/* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); -/* initialize DMA channel */ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct); -/* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); - -/* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set DMA Memory base address */ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); - -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); - -#endif /* GD32F30X_DMA_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h deleted file mode 100644 index fddb6e67c3..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h +++ /dev/null @@ -1,1680 +0,0 @@ -/*! - \file gd32f30x_enet.h - \brief definitions for the ENET -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_ENET_H -#define GD32F30X_ENET_H - -#include "gd32f30x.h" -#include - -#define IF_USE_EXTERNPHY_LIB 0 -#if (1 == IF_USE_EXTERNPHY_LIB) -#include "phy.h" -#endif - -#ifndef ENET_RXBUF_NUM -#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ -#endif - -#ifndef ENET_TXBUF_NUM -#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ -#endif - -#ifndef ENET_RXBUF_SIZE -#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ -#endif - -#ifndef ENET_TXBUF_SIZE -#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ -#endif - -/* #define SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* #define USE_DELAY */ - -#ifndef _PHY_H_ -#define DP83848 0 -#define LAN8700 1 -#define PHY_TYPE DP83848 - -#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ - -/* PHY read write timeouts */ -#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ -#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ - -/* PHY delay */ -#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ -#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ - -/* PHY register address */ -#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ -#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ - -/* PHY basic control register */ -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ - -/* PHY basic status register */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ - -#if(PHY_TYPE == LAN8700) -#define PHY_SR 31U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ -#elif(PHY_TYPE == DP83848) -#define PHY_SR 16U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ -#endif /* PHY_TYPE */ - -#endif /* _PHY_H_ */ - - -/* ENET definitions */ -#define ENET ENET_BASE - -/* registers definitions */ -#define ENET_MAC_CFG REG32((ENET) + 0x00U) /*!< ethernet MAC configuration register */ -#define ENET_MAC_FRMF REG32((ENET) + 0x04U) /*!< ethernet MAC frame filter register */ -#define ENET_MAC_HLH REG32((ENET) + 0x08U) /*!< ethernet MAC hash list high register */ -#define ENET_MAC_HLL REG32((ENET) + 0x0CU) /*!< ethernet MAC hash list low register */ -#define ENET_MAC_PHY_CTL REG32((ENET) + 0x10U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x14U) /*!< ethernet MAC MII data register */ -#define ENET_MAC_FCTL REG32((ENET) + 0x18U) /*!< ethernet MAC flow control register */ -#define ENET_MAC_VLT REG32((ENET) + 0x1CU) /*!< ethernet MAC VLAN tag register */ -#define ENET_MAC_RWFF REG32((ENET) + 0x28U) /*!< ethernet MAC remote wakeup frame filter register */ -#define ENET_MAC_WUM REG32((ENET) + 0x2CU) /*!< ethernet MAC wakeup management register */ -#define ENET_MAC_DBG REG32((ENET) + 0x34U) /*!< ethernet MAC debug register */ -#define ENET_MAC_INTF REG32((ENET) + 0x38U) /*!< ethernet MAC interrupt flag register */ -#define ENET_MAC_INTMSK REG32((ENET) + 0x3CU) /*!< ethernet MAC interrupt mask register */ -#define ENET_MAC_ADDR0H REG32((ENET) + 0x40U) /*!< ethernet MAC address 0 high register */ -#define ENET_MAC_ADDR0L REG32((ENET) + 0x44U) /*!< ethernet MAC address 0 low register */ -#define ENET_MAC_ADDR1H REG32((ENET) + 0x48U) /*!< ethernet MAC address 1 high register */ -#define ENET_MAC_ADDR1L REG32((ENET) + 0x4CU) /*!< ethernet MAC address 1 low register */ -#define ENET_MAC_ADDT2H REG32((ENET) + 0x50U) /*!< ethernet MAC address 2 high register */ -#define ENET_MAC_ADDR2L REG32((ENET) + 0x54U) /*!< ethernet MAC address 2 low register */ -#define ENET_MAC_ADDR3H REG32((ENET) + 0x58U) /*!< ethernet MAC address 3 high register */ -#define ENET_MAC_ADDR3L REG32((ENET) + 0x5CU) /*!< ethernet MAC address 3 low register */ -#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ - -#define ENET_MSC_CTL REG32((ENET) + 0x100U) /*!< ethernet MSC control register */ -#define ENET_MSC_RINTF REG32((ENET) + 0x104U) /*!< ethernet MSC receive interrupt flag register */ -#define ENET_MSC_TINTF REG32((ENET) + 0x108U) /*!< ethernet MSC transmit interrupt flag register */ -#define ENET_MSC_RINTMSK REG32((ENET) + 0x10CU) /*!< ethernet MSC receive interrupt mask register */ -#define ENET_MSC_TINTMSK REG32((ENET) + 0x110U) /*!< ethernet MSC transmit interrupt mask register */ -#define ENET_MSC_SCCNT REG32((ENET) + 0x14CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ -#define ENET_MSC_MSCCNT REG32((ENET) + 0x150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ -#define ENET_MSC_TGFCNT REG32((ENET) + 0x168U) /*!< ethernet MSC transmitted good frames counter register */ -#define ENET_MSC_RFCECNT REG32((ENET) + 0x194U) /*!< ethernet MSC received frames with CRC error counter register */ -#define ENET_MSC_RFAECNT REG32((ENET) + 0x198U) /*!< ethernet MSC received frames with alignment error counter register */ -#define ENET_MSC_RGUFCNT REG32((ENET) + 0x1C4U) /*!< ethernet MSC received good unicast frames counter register */ - -#define ENET_PTP_TSCTL REG32((ENET) + 0x700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x704U) /*!< ethernet PTP subsecond increment register */ -#define ENET_PTP_TSH REG32((ENET) + 0x708U) /*!< ethernet PTP time stamp high register */ -#define ENET_PTP_TSL REG32((ENET) + 0x70CU) /*!< ethernet PTP time stamp low register */ -#define ENET_PTP_TSUH REG32((ENET) + 0x710U) /*!< ethernet PTP time stamp update high register */ -#define ENET_PTP_TSUL REG32((ENET) + 0x714U) /*!< ethernet PTP time stamp update low register */ -#define ENET_PTP_TSADDEND REG32((ENET) + 0x718U) /*!< ethernet PTP time stamp addend register */ -#define ENET_PTP_ETH REG32((ENET) + 0x71CU) /*!< ethernet PTP expected time high register */ -#define ENET_PTP_ETL REG32((ENET) + 0x720U) /*!< ethernet PTP expected time low register */ -#define ENET_PTP_TSF REG32((ENET) + 0x728U) /*!< ethernet PTP time stamp flag register */ -#define ENET_PTP_PPSCTL REG32((ENET) + 0x72CU) /*!< ethernet PTP PPS control register */ - -#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ -#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ -#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ -#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ -#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ -#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ -#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ -#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ -#define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ -#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ -#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ -#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ - -/* bits definitions */ -/* ENET_MAC_CFG */ -#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ -#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ -#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ -#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ -#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ -#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ -#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ -#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ -#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ -#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ -#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ -#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ -#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ -#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ -#define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ - -/* ENET_MAC_FRMF */ -#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ -#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - -/* ENET_MAC_HLH */ -#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - -/* ENET_MAC_HLL */ -#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - -/* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - -/* ENET_MAC_PHY_DATA */ -#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - -/* ENET_MAC_FCTL */ -#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ -#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ -#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ -#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ -#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ -#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - -/* ENET_MAC_VLT */ -#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ -#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - -/* ENET_MAC_RWFF */ -#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ -#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ -#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ -#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ -#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ -#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ -#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ -#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ - -/* ENET_MAC_DBG */ -#define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ -#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ -#define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ -#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ -#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ -#define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ -#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ -#define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ -#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ -#define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ -#define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ -#define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ - -/* ENET_MAC_INTF */ -#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ -#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ -#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ -#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ -#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ - -/* ENET_MAC_INTMSK */ -#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ -#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ - -/* ENET_MAC_ADDR0H */ -#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ -#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - -/* ENET_MAC_ADDR0L */ -#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - -/* ENET_MAC_ADDR1H */ -#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR1L */ -#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - -/* ENET_MAC_ADDR2H */ -#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ -#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR2L */ -#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - -/* ENET_MAC_ADDR3H */ -#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ -#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR3L */ -#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - -/* ENET_MAC_FCTH */ -#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ -#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - -/* ENET_MSC_CTL */ -#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ -#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ -#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ -#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ -#define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */ -#define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */ - -/* ENET_MSC_RINTF */ -#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ -#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ -#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - -/* ENET_MSC_TINTF */ -#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ -#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ -#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ - -/* ENET_MSC_RINTMSK */ -#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ -#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ -#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - -/* ENET_MSC_TINTMSK */ -#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - -/* ENET_MSC_SCCNT */ -#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - -/* ENET_MSC_MSCCNT */ -#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - -/* ENET_MSC_TGFCNT */ -#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - -/* ENET_MSC_RFCECNT */ -#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - -/* ENET_MSC_RFAECNT */ -#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - -/* ENET_MSC_RGUFCNT */ -#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - -/* ENET_PTP_TSCTL */ -#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ -#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ -#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ -#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ -#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ -#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ -#define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */ -#define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */ -#define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */ -#define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */ -#define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */ -#define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ -#define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ -#define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ -#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ -#define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ - -/* ENET_PTP_SSINC */ -#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - -/* ENET_PTP_TSH */ -#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - -/* ENET_PTP_TSL */ -#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ -#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - -/* ENET_PTP_TSUH */ -#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - -/* ENET_PTP_TSUL */ -#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ -#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ - -/* ENET_PTP_TSADDEND */ -#define ENET_PTP_TSADDEND_TMSA BITS(0,31) /*!< timestamp addend */ - -/* ENET_PTP_ETH */ -#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - -/* ENET_PTP_ETL */ -#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - -/* ENET_PTP_TSF */ -#define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ -#define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ - -/* ENET_PTP_PPSCTL */ -#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ - -/* ENET_DMA_BCTL */ -#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ -#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ -#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ -#define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ -#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ -#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ -#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ -#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ -#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ -#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ -#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ -#define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ - -/* ENET_DMA_TPEN */ -#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - -/* ENET_DMA_RPEN */ -#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ - -/* ENET_DMA_RDTADDR */ -#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - -/* ENET_DMA_TDTADDR */ -#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - -/* ENET_DMA_STAT */ -#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ -#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ -#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ -#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ -#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ -#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ -#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ -#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ -#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ -#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ -#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ -#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ -#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ -#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ -#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ -#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ -#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ -#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ -#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ -#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ -#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - -/* ENET_DMA_CTL */ -#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ -#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ -#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ -#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ -#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ -#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ -#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ -#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ -#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ -#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ -#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ -#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - -/* ENET_DMA_INTEN */ -#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ -#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ -#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ -#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ -#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ -#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ -#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ -#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ -#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ -#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ -#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ -#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ -#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - -/* ENET_DMA_MFBOCNT */ -#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ -#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ - -/* ENET_DMA_RSWDC */ -#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ - -/* ENET_DMA_CTDADDR */ -#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ - -/* ENET_DMA_CRDADDR */ -#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - -/* ENET_DMA_CTBADDR */ -#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - -/* ENET_DMA_CRBADDR */ -#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ - -/* ENET DMA Tx descriptor TDES0 */ -#define ENET_TDES0_DB BIT(0) /*!< deferred */ -#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ -#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ -#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ -#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ -#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ -#define ENET_TDES0_LCO BIT(9) /*!< late collision */ -#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ -#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ -#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ -#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ -#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ -#define ENET_TDES0_ES BIT(15) /*!< error summary */ -#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ -#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ -#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ -#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ -#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ -#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ -#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ -#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ -#define ENET_TDES0_FSG BIT(28) /*!< first segment */ -#define ENET_TDES0_LSG BIT(29) /*!< last segment */ -#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ -#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ - -/* ENET DMA Tx descriptor TDES1 */ -#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ -#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ - -/* ENET DMA Tx descriptor TDES2 */ -#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ - -/* ENET DMA Tx descriptor TDES3 */ -#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/* ENET DMA Tx descriptor TDES6 */ -#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ - -/* ENET DMA Tx descriptor TDES7 */ -#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* ENET DMA Rx descriptor RDES0 */ -#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ -#define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */ -#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ -#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ -#define ENET_RDES0_RERR BIT(3) /*!< receive error */ -#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ -#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ -#define ENET_RDES0_LCO BIT(6) /*!< late collision */ -#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ -#define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ -#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ -#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ -#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ -#define ENET_RDES0_LERR BIT(12) /*!< length error */ -#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ -#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ -#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ -#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ -#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ -#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ - -/* ENET DMA Rx descriptor RDES1 */ -#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ -#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ -#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ -#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ -#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ - -/* ENET DMA Rx descriptor RDES2 */ -#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ - -/* ENET DMA Rx descriptor RDES3 */ -#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/* ENET DMA Rx descriptor RDES4 */ -#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ -#define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ -#define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ -#define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ -#define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ -#define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ -#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ -#define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ -#define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ - -/* ENET DMA Rx descriptor RDES6 */ -#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ - -/* ENET DMA Rx descriptor RDES7 */ -#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* constants definitions */ -/* define bit position and its register index offset */ -#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph)>>6))) -#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* ENET clock range judgement */ -#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) - -/* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) -#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) -#define ENET_ADDRH_BASE ((ENET) + 0x40U) -#define ENET_ADDRL_BASE ((ENET) + 0x44U) -#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) - -/* register offset */ -#define MAC_FCTL_REG_OFFSET 0x0018U /*!< MAC flow control register offset */ -#define MAC_WUM_REG_OFFSET 0x002CU /*!< MAC wakeup management register offset */ -#define MAC_INTF_REG_OFFSET 0x0038U /*!< MAC interrupt flag register offset */ -#define MAC_INTMSK_REG_OFFSET 0x003CU /*!< MAC interrupt mask register offset */ - -#define MSC_RINTF_REG_OFFSET 0x0104U /*!< MSC receive interrupt flag register offset */ -#define MSC_TINTF_REG_OFFSET 0x0108U /*!< MSC transmit interrupt flag register offset */ -#define MSC_RINTMSK_REG_OFFSET 0x010CU /*!< MSC receive interrupt mask register offset */ -#define MSC_TINTMSK_REG_OFFSET 0x0110U /*!< MSC transmit interrupt mask register offset */ -#define MSC_SCCNT_REG_OFFSET 0x014CU /*!< MSC transmitted good frames after a single collision counter register offset */ -#define MSC_MSCCNT_REG_OFFSET 0x0150U /*!< MSC transmitted good frames after more than a single collision counter register offset */ -#define MSC_TGFCNT_REG_OFFSET 0x0168U /*!< MSC transmitted good frames counter register offset */ -#define MSC_RFCECNT_REG_OFFSET 0x0194U /*!< MSC received frames with CRC error counter register offset */ -#define MSC_RFAECNT_REG_OFFSET 0x0198U /*!< MSC received frames with alignment error counter register offset */ -#define MSC_RGUFCNT_REG_OFFSET 0x01C4U /*!< MSC received good unicast frames counter register offset */ - -#define PTP_TSF_REG_OFFSET 0x0728U /*!< PTP time stamp flag register offset */ - -#define DMA_STAT_REG_OFFSET 0x1014U /*!< DMA status register offset */ -#define DMA_INTEN_REG_OFFSET 0x101CU /*!< DMA interrupt enable register offset */ -#define DMA_TDTADDR_REG_OFFSET 0x1010U /*!< DMA transmit descriptor table address register offset */ -#define DMA_CTDADDR_REG_OFFSET 0x1048U /*!< DMA current transmit descriptor address register */ -#define DMA_CTBADDR_REG_OFFSET 0x1050U /*!< DMA current transmit buffer address register */ -#define DMA_RDTADDR_REG_OFFSET 0x100CU /*!< DMA receive descriptor table address register */ -#define DMA_CRDADDR_REG_OFFSET 0x104CU /*!< DMA current receive descriptor address register */ -#define DMA_CRBADDR_REG_OFFSET 0x1054U /*!< DMA current receive buffer address register */ - -/* ENET status flag get */ -typedef enum -{ - /* ENET_MAC_WUM register */ - ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ - /* ENET_MAC_FCTL register */ - ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ - /* ENET_MAC_INTF register */ - ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_PTP_TSF register */ - ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ - ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ - ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ - ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ - ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_flag_enum; - -/* ENET stutus flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_flag_clear_enum; - -/* ENET interrupt enable/disable */ -typedef enum -{ - /* ENET_MAC_INTMSK register */ - ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ - ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ - ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ - ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ - ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ - ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ - ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ - ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ - ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ - ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ - ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ - ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ - ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ - ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ - ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ - ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ - ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ - ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ - ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ - ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ - ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ - ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ - ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ -}enet_int_enum; - -/* ENET interrupt flag get */ -typedef enum -{ - /* ENET_MAC_INTF register */ - ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_int_flag_enum; - -/* ENET interrupt flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_int_flag_clear_enum; - -/* current RX/TX descriptor/buffer/descriptor table address get */ -typedef enum -{ - ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ - ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ - ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ - ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ - ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ - ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ -}enet_desc_reg_enum; - -/* MAC statistics counter get */ -typedef enum -{ - ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ - ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ - ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ - ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ - ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ - ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; - -/* function option, used for ENET initialization */ -typedef enum -{ - FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ - DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ - DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ - DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ - STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ - DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ - VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ - FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ - HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ - HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ - FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ - HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ - TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ - INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ -}enet_option_enum; - -/* phy mode and mac loopback configurations */ -typedef enum -{ - ENET_AUTO_NEGOTIATION = 0x01u, /*!< PHY auto negotiation */ - ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ - ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ - ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ - ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ - ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ -}enet_mediamode_enum; - -/* IP frame checksum function */ -typedef enum -{ - ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ - ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ - ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped */ -}enet_chksumconf_enum; - -/* received frame filter function */ -typedef enum -{ - ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ - ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ - ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ - ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ -}enet_frmrecept_enum; - -/* register group value get */ -typedef enum -{ - ALL_MAC_REG = 0, /*!< MAC register group */ - ALL_MSC_REG = 22, /*!< MSC register group */ - ALL_PTP_REG = 33, /*!< PTP register group */ - ALL_DMA_REG = 44, /*!< DMA register group */ -}enet_registers_type_enum; - -/* dma direction select */ -typedef enum -{ - ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ - ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ -}enet_dmadirection_enum; - -/* PHY operation direction select */ -typedef enum -{ - ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ - ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ -}enet_phydirection_enum; - -/* register operation direction select */ -typedef enum -{ - ENET_REG_READ, /*!< read register */ - ENET_REG_WRITE /*!< write register */ -}enet_regdirection_enum; - -/* ENET MAC addresses */ -typedef enum -{ - ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ - ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ - ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ - ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ -}enet_macaddress_enum; - -/* descriptor information */ -typedef enum -{ - TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ - TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ - RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ - RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ - RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ - RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ -}enet_descstate_enum; - -/* MSC counters preset mode */ -typedef enum -{ - ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ - ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ - ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ -}enet_msc_preset_enum; - -/* structure for initialization of the ENET */ -typedef struct -{ - uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ - uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ - uint32_t dma_maxburst; /*!< DMA max burst related parameters */ - uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ - uint32_t store_forward_mode; /*!< store forward mode related parameters */ - uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ - uint32_t flow_control; /*!< flow control related parameters */ - uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ - uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ - uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ - uint32_t timer_config; /*!< frame timer related parameters */ - uint32_t interframegap; /*!< inter frame gap related parameters */ -}enet_initpara_struct; - -/* structure for ENET DMA desciptors */ -typedef struct -{ - uint32_t status; /*!< status */ - uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ - uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ - uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE - uint32_t extended_status; /*!< extended status */ - uint32_t reserved; /*!< reserved */ - uint32_t timestamp_low; /*!< timestamp low */ - uint32_t timestamp_high; /*!< timestamp high */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -} enet_descriptors_struct; - -/* structure of PTP system time */ -typedef struct -{ - uint32_t second; /*!< second of system time */ - uint32_t nanosecond; /*!< nanosecond of system time */ - uint32_t sign; /*!< sign of system time */ -}enet_ptp_systime_struct; - -/* mac_cfg register value */ -#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ -#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ -#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ -#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ - -#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ -#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ -#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ -#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ -#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ -#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ -#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ -#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ - -#define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ -#define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ -#define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */ - -#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ -#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - -#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ -#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ - -#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ -#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - -#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ -#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ - -#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ -#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ - -#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ -#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ - -#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ -#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ - -#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ -#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ - -#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ -#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ - -#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ -#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ -#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ - -#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ -#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ - -/* mac_frmf register value */ -#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ -#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ -#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ -#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ -#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - -#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ -#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - -#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ -#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ -#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ -#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ -#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ - -#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ -#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - -#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ - -#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ -#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - -#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ -#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ -#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ -#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ -#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ -#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ -#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ - -#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ -#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ -#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ -#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ - -/* mac_phy_ctl register value */ -#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ -#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ -#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-120 MHz; MDC clock= HCLK/62 */ -#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ -#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ - -#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ - -#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ - -/* mac_phy_data register value */ -#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ - -/* mac_fctl register value */ -#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ -#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ -#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ -#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ - -#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ - -#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ -#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - -#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ -#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ -#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ - -#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ - -#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - -#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ -/* mac_vlt register value */ -#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - -#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ -#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ - -/* mac_wum register value */ -#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ -#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ -#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ -#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ - -/* mac_dbg register value */ -#define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ -#define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ -#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ -#define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ -#define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ -#define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ -#define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ -#define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ -#define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ -#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ -#define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ -#define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ - -#define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */ - -#define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */ - -#define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */ - -#define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */ - -#define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ - -/* mac_addr0h register value */ -#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ - -/* mac_addrxh register value, x = 1,2,3 */ -#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ - -#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ -#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ -#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ -#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ - -#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ -#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - -/* mac_fcth register value */ -#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ -#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ -#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ -#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ -#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ -#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ -#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ -#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ - -#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ -#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ -#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ -#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ - -/* msc_ctl register value */ -#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ -#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ -#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ - -/* ptp_tsctl register value */ -#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ - -#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ -#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ -#define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */ -#define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */ -#define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */ -#define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */ -#define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ - -/* ptp_ssinc register value */ -#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ - -/* ptp_tsl register value */ -#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - -#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ -#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ - -#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ - -/* ptp_tsul register value */ -#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ - -#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ -#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ - -/* ptp_ppsctl register value */ -#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ -#define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ -#define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ -#define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ -#define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */ -#define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */ -#define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */ -#define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */ -#define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */ -#define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */ -#define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */ -#define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */ -#define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */ -#define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */ -#define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */ -#define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */ -#define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ - -/* dma_bctl register value */ -#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ -#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ - -#define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ -#define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ - -#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ -#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ -#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ -#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ -#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ - -#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ -#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ -#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ -#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ -#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ - -#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ -#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ - -#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ -#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ -#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ -#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ -#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ -#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ -#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ -#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ -#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ - -#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ -#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ - -#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ -#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ - -#define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */ -#define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */ - -/* dma_stat register value */ -#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ -#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ -#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ -#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ -#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ -#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ -#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ - -#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ -#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ -#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ -#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ -#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ -#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ -#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ - -#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ -#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ -#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ -#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ - -/* dma_ctl register value */ -#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ -#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ -#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ -#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ - -#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ -#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ -#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ -#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ -#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ -#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ -#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ -#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ - -#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ -#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ - -#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ -#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ - -#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ -#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ -#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush frames function */ - -#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ -#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ - -#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ -#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ -#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ - -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ - -#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ -#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ -#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ - -/* dma_mfbocnt register value */ -#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ - -#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ - -/* dma_rswdc register value */ -#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ - -/* dma tx descriptor tdes0 register value */ -#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ -#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ - -#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ - -/* dma tx descriptor tdes1 register value */ -#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ - -#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ - -/* dma rx descriptor rdes0 register value */ -#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ -#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ - -/* dma rx descriptor rdes1 register value */ -#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ -#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ - -#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ - -#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ - -/* dma rx descriptor rdes4 register value */ -#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ -#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ - -#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ -#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ - -/* ENET register mask value */ -#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ -#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ -#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ -#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ -#define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -#define ETH_DMATXDESC_SIZE 0x20U /*!< TxDMA enhanced descriptor size */ -#define ETH_DMARXDESC_SIZE 0x20U /*!< RxDMA enhanced descriptor size */ -#else -#define ETH_DMATXDESC_SIZE 0x10U /*!< TxDMA descriptor size */ -#define ETH_DMARXDESC_SIZE 0x10U /*!< RxDMA descriptor size */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - - -typedef enum{ - ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ - ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ - ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ - ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ - ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ - ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ - ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ - ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ - ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ - ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ - ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)), /*!< version 2 */ - ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ - ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)), /*!< only event type messages are taken snapshot */ - ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ - ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)), /*!< snapshot is only take for master node message */ - ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ -}enet_ptp_function_enum; - - -/* ENET remote wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ - -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ - -/* ENET delay timeout */ -#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ -#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ - - - -/* function declarations */ -/* main function */ -/* deinitialize the ENET, and reset structure parameters for ENET initialization */ -void enet_deinit(void); -/* configure the parameters which are usually less cared for initialization */ -void enet_initpara_config(enet_option_enum option, uint32_t para); -/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); -/* reset all core internal registers located in CLK_TX and CLK_RX */ -ErrStatus enet_software_reset(void); -/* check receive frame valid and return frame size */ -uint32_t enet_rxframe_size_get(void); -/* initialize the dma tx/rx descriptors's parameters in chain mode */ -void enet_descriptors_chain_init(enet_dmadirection_enum direction); -/* initialize the dma tx/rx descriptors's parameters in ring mode */ -void enet_descriptors_ring_init(enet_dmadirection_enum direction); -/* handle current received frame data to application buffer */ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); -/* handle current received frame but without data copy to application buffer */ -#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) -/* handle application buffer data to transmit it */ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); -/* handle current transmit frame but without data copy from application buffer */ -#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) -/* configure the transmit IP frame checksum offload calculation and insertion */ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); -/* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); -/* ENET Tx and Rx function disable (include MAC and DMA module) */ -void enet_disable(void); -/* configure MAC address */ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); - -/* get the ENET MAC/MSC/PTP/DMA status flag */ -FlagStatus enet_flag_get(enet_flag_enum enet_flag); -/* clear the ENET DMA status flag */ -void enet_flag_clear(enet_flag_clear_enum enet_flag); -/* enable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_enable(enet_int_enum enet_int); -/* disable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_disable(enet_int_enum enet_int); -/* get ENET MAC/MSC/DMA interrupt flag */ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); -/* clear ENET DMA interrupt flag */ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); - -/* MAC function */ -/* ENET Tx function enable (include MAC and DMA module) */ -void enet_tx_enable(void); -/* ENET Tx function disable (include MAC and DMA module) */ -void enet_tx_disable(void); -/* ENET Rx function enable (include MAC and DMA module) */ -void enet_rx_enable(void); -/* ENET Rx function disable (include MAC and DMA module) */ -void enet_rx_disable(void); -/* put registers value into the application buffer */ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); -/* get the enet debug status from the debug register */ -uint32_t enet_debug_status_get(uint32_t mac_debug); -/* enable the MAC address filter */ -void enet_address_filter_enable(enet_macaddress_enum mac_addr); -/* disable the MAC address filter */ -void enet_address_filter_disable(enet_macaddress_enum mac_addr); -/* configure the MAC address filter */ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); -/* PHY interface configuration (configure SMI clock and reset PHY chip) */ -ErrStatus enet_phy_config(void); -/* write to/read from a PHY register */ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); -/* enable the loopback function of phy chip */ -ErrStatus enet_phyloopback_enable(void); -/* disable the loopback function of phy chip */ -ErrStatus enet_phyloopback_disable(void); -/* enable ENET forward feature */ -void enet_forward_feature_enable(uint32_t feature); -/* disable ENET forward feature */ -void enet_forward_feature_disable(uint32_t feature); -/* enable ENET fliter feature */ -void enet_fliter_feature_enable(uint32_t feature); -/* disable ENET fliter feature */ -void enet_fliter_feature_disable(uint32_t feature); - -/* flow control function */ -/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ -ErrStatus enet_pauseframe_generate(void); -/* configure the pause frame detect type */ -void enet_pauseframe_detect_config(uint32_t detect); -/* configure the pause frame parameters */ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); -/* configure the threshold of the flow control(deactive and active threshold) */ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); -/* enable ENET flow control feature */ -void enet_flowcontrol_feature_enable(uint32_t feature); -/* disable ENET flow control feature */ -void enet_flowcontrol_feature_disable(uint32_t feature); - -/* DMA function */ -/* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); -/* poll the dma transmission/reception enable */ -void enet_dmaprocess_resume(enet_dmadirection_enum direction); -/* check and recover the Rx process */ -void enet_rxprocess_check_recovery(void); -/* flush the ENET transmit fifo, and wait until the flush operation completes */ -ErrStatus enet_txfifo_flush(void); -/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); -/* get the Tx or Rx descriptor information */ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); -/* get the number of missed frames during receiving */ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); - -/* descriptor function */ -/* get the bit flag of ENET dma descriptor */ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); -/* set the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); -/* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ -void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ -void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time); -/* drop current receive frame */ -void enet_rxframe_drop(void); -/* enable DMA feature */ -void enet_dma_feature_enable(uint32_t feature); -/* disable DMA feature */ -void enet_dma_feature_disable(uint32_t feature); - - -/* special enhanced mode function */ -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/* get the bit of extended status flag in ENET DMA descriptor */ -uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); -/* configure descriptor to work in enhanced mode */ -void enet_desc_select_enhanced_mode(void); -/* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */ -void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction); -/* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */ -void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction); -/* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */ -ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); -/* handle current received frame but without data copy to application buffer in PTP enhanced mode */ -#define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr)) -/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */ -ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); -/* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */ -#define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr)) - -#else - -/* configure descriptor to work in normal mode */ -void enet_desc_select_normal_mode(void); -/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); -/* handle current received frame but without data copy to application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) -/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); -/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) - -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* WUM function */ -/* wakeup frame filter register pointer reset */ -void enet_wum_filter_register_pointer_reset(void); -/* set the remote wakeup frame registers */ -void enet_wum_filter_config(uint32_t pdata[]); -/* enable wakeup management features */ -void enet_wum_feature_enable(uint32_t feature); -/* disable wakeup management features */ -void enet_wum_feature_disable(uint32_t feature); - -/* MSC function */ -/* reset the MAC statistics counters */ -void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ -void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ -void enet_msc_feature_disable(uint32_t feature); -/* configure MAC statistics counters preset mode */ -void enet_msc_counters_preset_config(enet_msc_preset_enum mode); -/* get MAC statistics counter */ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); - -/* PTP function */ -/* change subsecond to nanosecond */ -uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond); -/* change nanosecond to subsecond */ -uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond); -/* enable the PTP features */ -void enet_ptp_feature_enable(uint32_t feature); -/* disable the PTP features */ -void enet_ptp_feature_disable(uint32_t feature); -/* configure the PTP timestamp function */ -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); -/* configure the PTP system time subsecond increment value */ -void enet_ptp_subsecond_increment_config(uint32_t subsecond); -/* adjusting the PTP clock frequency only in fine update mode */ -void enet_ptp_timestamp_addend_config(uint32_t add); -/* initializing or adding/subtracting to second of the PTP system time */ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); -/* configure the PTP expected target time */ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); -/* get the PTP current system time */ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); -/* configure the PPS output frequency */ -void enet_ptp_pps_output_frequency_config(uint32_t freq); -/* configure and start PTP timestamp counter */ -void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg); -/* adjust frequency in fine method by configure addend register */ -void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg); -/* update system time in coarse method */ -void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct); -/* set system time in fine method */ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct); -/* get the ptp flag status */ -FlagStatus enet_ptp_flag_get(uint32_t flag); - -/* internal function */ -/* reset the ENET initpara struct, call it before using enet_initpara_config() */ -void enet_initpara_reset(void); -/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ -static void enet_default_init(void); -#ifdef USE_DELAY -/* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms -#else -/* insert a delay time */ -static void enet_delay(uint32_t ncount); -/* default _ENET_DELAY_ function with less precise timing */ -#define _ENET_DELAY_ enet_delay -#endif - -#endif /* GD32F30X_ENET_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h deleted file mode 100644 index b93532934b..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h +++ /dev/null @@ -1,420 +0,0 @@ -/*! - \file gd32f30x_exmc.h - \brief definitions for the EXMC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.2, firmware for GD32F30x -*/ - -#ifndef GD32F30X_EXMC_H -#define GD32F30X_EXMC_H - -#include "gd32f30x.h" - -/* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ - -/* registers definitions */ -/* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ - -#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register 1 */ -#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register 1 */ -#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register 1 */ - -#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register 2 */ -#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register 2 */ -#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register 2 */ - -#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register 3 */ -#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register 3 */ -#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register 3 */ - -/* NAND/PC card */ -#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register 1 */ -#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register 1 */ -#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register 1 */ -#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register 1 */ -#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register 1 */ - -#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register 2 */ -#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register 2 */ -#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register 2 */ -#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register 2 */ -#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register 2 */ - -#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register 3 */ -#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register 3 */ -#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register 3 */ -#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register 3 */ -#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */ - -/* bits definitions */ -/* EXMC_SNCTLx,x=0..3 */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ -#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ -#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ - -/* EXMC_SNTCFGx,x=0..3 */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ -#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* EXMC_SNWTCFGx,x=0..3 */ -#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* EXMC_NPCTLx,x=1..3 */ -#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ -#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ -#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ -#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ -#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ -#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ -#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ -#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ - -/* EXMC_NPINTENx,x=1..3 */ -#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ -#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ -#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ -#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ -#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ -#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ -#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ - -/* EXMC_NPCTCFGx,x=1..3 */ -#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ -#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ -#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ -#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ - -/* EXMC_NPATCFGx,x=1..3 */ -#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ -#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ -#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ -#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ - -/* EXMC_PIOTCFG3 */ -#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ -#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ -#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ -#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ - -/* EXMC_NECCx,x=1,2 */ -#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ - -/* constants definitions */ -/* EXMC NOR/SRAM timing initialize struct */ -typedef struct -{ - uint32_t asyn_access_mode; /*!< asynchronous access mode */ - uint32_t syn_data_latency; /*!< configure the data latency */ - uint32_t syn_clk_division; /*!< configure the clock divide ratio */ - uint32_t bus_latency; /*!< configure the bus latency */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ - uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ -}exmc_norsram_timing_parameter_struct; - -/* EXMC NOR/SRAM initialize struct */ -typedef struct -{ - uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ - uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ - uint32_t extended_mode; /*!< enable or disable the extended mode */ - uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ - uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ - uint32_t memory_write; /*!< enable or disable the write operation */ - uint32_t nwait_config; /*!< NWAIT signal configuration */ - uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ - uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ - uint32_t burst_mode; /*!< enable or disable the burst mode */ - uint32_t databus_width; /*!< specifies the databus width of external memory */ - uint32_t memory_type; /*!< specifies the type of external memory */ - uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing - parameters for read if the extended mode is used */ - exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ -}exmc_norsram_parameter_struct; - -/* EXMC NAND/PC card timing initialize struct */ -typedef struct -{ - uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ - uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ - uint32_t waittime; /*!< configure the minimum wait time */ - uint32_t setuptime; /*!< configure the address setup time */ -}exmc_nand_pccard_timing_parameter_struct; - -/* EXMC NAND initialize struct */ -typedef struct -{ - uint32_t nand_bank; /*!< select the bank of NAND */ - uint32_t ecc_size; /*!< the page size for the ECC calculation */ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ - uint32_t databus_width; /*!< the NAND flash databus width */ - uint32_t wait_feature; /*!< enables or disables the wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ -}exmc_nand_parameter_struct; - -/* EXMC PC card initialize struct */ -typedef struct -{ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t wait_feature; /*!< enables or disables the Wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ - exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for NAND flash IO space */ -}exmc_pccard_parameter_struct;; - - -/* EXMC_register address */ -#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ -#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration register */ - -#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control register */ -#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable register */ -#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration register */ -#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration register */ -#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC register */ - -/* CRAM page size */ -#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ -#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ -#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ -#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ -#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ - -/* NOR bank memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ - -/* NOR bank memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - -/* asynchronous access mode */ -#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ -#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ -#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ -#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ - -/* data latency for NOR flash */ -#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ -#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ -#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ -#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ -#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ -#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ -#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ -#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ -#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ -#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ -#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ -#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ -#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ -#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ -#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ -#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ - -/* synchronous clock divide ratio */ -#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ - -/* ECC size */ -#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* 256 bytes */ -#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* 512 bytes */ -#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* 1024 bytes */ -#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* 2048 bytes */ -#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* 4096 bytes */ -#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* 8192 bytes */ - -/* ALE to RE delay */ -#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ -#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ -#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ -#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ -#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ -#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ -#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ -#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ -#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ -#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ -#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ -#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ -#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ -#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ -#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ -#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ - -/* CLE to RE delay */ -#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ -#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ -#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ -#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ -#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ -#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ -#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ -#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ -#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ -#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ -#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ -#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ -#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ -#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ -#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ -#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ - -/* NAND bank memory data bus width */ -#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width 8 bits */ -#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width 16 bits */ - -/* EXMC NOR/SRAM bank region definition */ -#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ -#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ -#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ -#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ - -/* EXMC NOR/SRAM write mode */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ -#define EXMC_SYN_WRITE ((uint32_t)0x00080000U) /*!< synchronous write mode */ - -/* EXMC NWAIT signal configuration */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ -#define EXMC_NWAIT_CONFIG_DURING ((uint32_t)0x00000800U) /*!< NWAIT signal is active during wait state */ - -/* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ - -/* EXMC NAND/PC card bank definition */ -#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */ -#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */ -#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */ - -/* EXMC flag bits */ -#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ -#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ -#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ -#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ - -/* EXMC interrupt enable bits */ -#define EXMC_NAND_PCCARD_INT_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ -#define EXMC_NAND_PCCARD_INT_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ -#define EXMC_NAND_PCCARD_INT_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ - -/* EXMC interrupt flag bits */ -#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< interrupt rising edge detection enable */ -#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< interrupt high-level detection enable */ -#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< interrupt falling edge detection enable */ - -/* function declarations */ -/* deinitialize EXMC NOR/SRAM region */ -void exmc_norsram_deinit(uint32_t exmc_norsram_region); -/* initialize EXMC NOR/SRAM region */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* CRAM page size configure */ -void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); -/* EXMC NOR/SRAM bank enable */ -void exmc_norsram_enable(uint32_t exmc_norsram_region); -/* EXMC NOR/SRAM bank disable */ -void exmc_norsram_disable(uint32_t exmc_norsram_region); - - -/* deinitialize EXMC NAND bank */ -void exmc_nand_deinit(uint32_t exmc_nand_bank); -/* initialize EXMC NAND bank */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* EXMC NAND bank enable */ -void exmc_nand_enable(uint32_t exmc_nand_bank); -/* EXMC NAND bank disable */ -void exmc_nand_disable(uint32_t exmc_nand_bank); -/* enable or disable the EXMC NAND ECC function */ -void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); -/* get the EXMC ECC value */ -uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); - -/* deinitialize EXMC PC card bank */ -void exmc_pccard_deinit(void); -/* initialize EXMC PC card bank */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* exmc_pccard_parameter_struct parameter initialize */ -void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* EXMC PC card bank enable */ -void exmc_pccard_enable(void); -/* EXMC PC card bank disable */ -void exmc_pccard_disable(void); - -/* check EXMC flag is set or not */ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); -/* clear EXMC flag */ -void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); -/* check EXMC flag is set or not */ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source); -/* clear EXMC flag */ -void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source); -/* enable EXMC interrupt */ -void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source); -/* disable EXMC interrupt */ -void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source); - -#endif /* GD32F30X_EXMC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h deleted file mode 100644 index c95a0d1e1f..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h +++ /dev/null @@ -1,229 +0,0 @@ -/*! - \file gd32f30x_exti.h - \brief definitions for the EXTI -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef GD32F30X_EXTI_H -#define GD32F30X_EXTI_H - -#include "gd32f30x.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ -#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ -#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ -#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ -#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ -#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum -{ - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ -}exti_line_enum; - -/* external interrupt and event */ -typedef enum -{ - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum -{ - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ -}exti_trig_type_enum; - -/* function declarations */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - -/* get EXTI lines pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); -/* enable the EXTI software interrupt event */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable the EXTI software interrupt event */ -void exti_software_interrupt_disable(exti_line_enum linex); - -#endif /* GD32F30X_EXTI_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h deleted file mode 100644 index 4de9ce2573..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h +++ /dev/null @@ -1,343 +0,0 @@ -/*! - \file gd32f30x_fmc.h - \brief definitions for the FMC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_FMC_H -#define GD32F30X_FMC_H - -#include "gd32f30x.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option bytes base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ -#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ -#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ -#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ -#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ -#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ -#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ -#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ -#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ -#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ -#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ -#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ -#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ - -/* FMC_KEY0 */ -#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT0 */ -#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL0 */ -#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ -#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ -#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ -#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ -#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR0 */ -#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ -#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ -#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ -#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - -/* FMC_WP */ -#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ - -/* FMC_KEY1 */ -#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ - -/* FMC_STAT1 */ -#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL1 */ -#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ -#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ -#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ -#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ -#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR1 */ -#define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ - -/* FMC_WSEN */ -#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* define the FMC bit position and its register index offset */ -#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) -#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) -#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) - -/* configuration register */ -#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ -#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ -#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ -#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ -#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ - -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ -}fmc_state_enum; - -/* FMC interrupt enable */ -typedef enum -{ - FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ - FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ - FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ - FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ -}fmc_int_enum; - -/* FMC flags */ -typedef enum -{ - FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ - FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ - FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ - FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ - FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ - FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ - FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ - FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ - FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ -}fmc_flag_enum; - -/* FMC interrupt flags */ -typedef enum -{ - FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ - FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ - FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ - FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ -}fmc_interrupt_flag_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* FMC wait state counter */ -#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ -#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ -#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ - -/* option bytes software/hardware free watch dog timer */ -#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ -#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ - -/* option bytes reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ - -/* option bytes reset or not entering standby mode */ -#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ -#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ - -/* option bytes boot bank value */ -#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ -#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ - -#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ - -/* read protect configure */ -#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ -#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ - -/* OB_SPC */ -#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ -#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ - -/* OB_USER */ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ -#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ - -/* OB_WP0 */ -#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ - -/* OB_WP1 */ -#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ - -/* OB_WP2 */ -#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ - -/* OB_WP3 */ -#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ - -/* option bytes write protection */ -#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ -#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ -#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ -#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ -#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ -#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ -#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ -#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ -#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ -#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ -#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ -#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ -#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ -#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ -#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ -#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ -#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ -#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ -#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ -#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ -#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ - -/* FMC timeout */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ - -/* FMC BANK address */ -#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ -#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ -#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* set the FMC wait state counter */ -void fmc_wscnt_set(uint32_t wscnt); -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* unlock the FMC bank0 operation */ -void fmc_bank0_unlock(void); -/* unlock the FMC bank1 operation */ -void fmc_bank1_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* lock the bank0 FMC operation */ -void fmc_bank0_lock(void); -/* lock the bank1 FMC operation */ -void fmc_bank1_lock(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC erase whole bank0 */ -fmc_state_enum fmc_bank0_erase(void); -/* FMC erase whole bank1 */ -fmc_state_enum fmc_bank1_erase(void); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* erase the option byte */ -fmc_state_enum ob_erase(void); -/* enable write protect */ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); -/* configure the option byte security protection */ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte */ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); -/* program option bytes data */ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data); -/* get the FMC option byte user */ -uint8_t ob_user_get(void); -/* get OB_DATA in register FMC_OBSTAT */ -uint16_t ob_data_get(void); -/* get the FMC option byte write protection */ -uint32_t ob_write_protection_get(void); -/* get option byte security protection code value */ -FlagStatus ob_spc_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* check flag is set or not */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC flag */ -void fmc_flag_clear(uint32_t flag); -/* get FMC interrupt flag state */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); -/* clear FMC interrupt flag state */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); -/* return the FMC bank0 state */ -fmc_state_enum fmc_bank0_state_get(void); -/* return the FMC bank1 state */ -fmc_state_enum fmc_bank1_state_get(void); -/* check FMC bank0 ready or not */ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); -/* check FMC bank1 ready or not */ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); - -#endif /* GD32F30X_FMC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h deleted file mode 100644 index 9c8d4e8517..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h +++ /dev/null @@ -1,79 +0,0 @@ -/*! - \file gd32f30x_fwdgt.h - \brief definitions for the FWDGT -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_FWDGT_H -#define GD32F30X_FWDGT_H - -#include "gd32f30x.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ - -/* constants definitions */ -/* psc register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ - -/* function declarations */ -/* disable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32F30X_FWDGT_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h deleted file mode 100644 index b1baadcfe8..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h +++ /dev/null @@ -1,504 +0,0 @@ -/*! - \file gd32f30x_gpio.h - \brief definitions for the GPIO -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_GPIO_H -#define GD32F30X_GPIO_H - -#include "gd32f30x.h" - -/* GPIOx(x=A,B,C,D,E,F,G) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOE (GPIO_BASE + 0x00001000U) -#define GPIOF (GPIO_BASE + 0x00001400U) -#define GPIOG (GPIO_BASE + 0x00001800U) - -/* AFIO definitions */ -#define AFIO AFIO_BASE - -/* registers definitions */ -/* GPIO registers definitions */ -#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ -#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ -#define GPIOx_SPD(gpiox) REG32((gpiox) + 0x3CU) /*!< GPIO port bit speed register */ - -/* AFIO registers definitions */ -#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ -#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ -#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ -#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ -#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ -#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ -#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ -#define AFIO_CPSCTL REG32(AFIO + 0x20U) /*!< IO compensation control register */ - -/* bits definitions */ -/* GPIO_CTL0 */ -#define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ -#define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ -#define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ -#define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ -#define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ -#define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ -#define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ -#define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ -#define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ -#define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ -#define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ -#define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ -#define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ -#define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ -#define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ -#define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ - -/* GPIO_CTL1 */ -#define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ -#define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ -#define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ -#define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ -#define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ -#define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ -#define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ -#define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ -#define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ -#define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ -#define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ -#define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ -#define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ -#define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ -#define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ -#define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* GPIO_SPD */ -#define GPIO_SPD_SPD0 BIT(0) /*!< pin 0 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD1 BIT(1) /*!< pin 1 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD2 BIT(2) /*!< pin 2 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD3 BIT(3) /*!< pin 3 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD4 BIT(4) /*!< pin 4 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD5 BIT(5) /*!< pin 5 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD6 BIT(6) /*!< pin 6 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD7 BIT(7) /*!< pin 7 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD8 BIT(8) /*!< pin 8 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD9 BIT(9) /*!< pin 9 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD10 BIT(10) /*!< pin 10 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD11 BIT(11) /*!< pin 11 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD12 BIT(12) /*!< pin 12 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD13 BIT(13) /*!< pin 13 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD14 BIT(14) /*!< pin 14 set very high output speed when MDx is 0b11 */ -#define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ - -/* AFIO_EC */ -#define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ -#define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ -#define AFIO_EC_EOE BIT(7) /*!< event output enable */ - -/* AFIO_PCF0 */ -#ifdef GD32F30X_CL -/* memory map and bit definitions for GD32F30X_CL devices */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN0_REMAP BITS(13,14) /*!< CAN0 remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ -#define AFIO_PCF0_ENET_REMAP BIT(21) /*!< ethernet MAC I/O remapping */ -#define AFIO_PCF0_CAN1_REMAP BIT(22) /*!< CAN1 remapping */ -#define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ -#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ -#define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ -#define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ - -#else -/* memory map and bit definitions for GD32F30X_HD devices and GD32F30X_XD devices */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN_REMAP BITS(13,14) /*!< CAN remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_REMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ -#define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ -#define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ -#endif /* GD32F30X_CL */ - -/* AFIO_EXTISS0 */ -#define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ -#define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ -#define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ -#define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ - -/* AFIO_EXTISS1 */ -#define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ -#define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ -#define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ -#define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ - -/* AFIO_EXTISS2 */ -#define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ -#define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ -#define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ -#define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ - -/* AFIO_EXTISS3 */ -#define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ -#define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ -#define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ -#define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ - -/* AFIO_PCF1 */ -#define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ -#define AFIO_PCF1_TIMER9_REMAP BIT(6) /*!< TIMER9 remapping */ -#define AFIO_PCF1_TIMER10_REMAP BIT(7) /*!< TIMER10 remapping */ -#define AFIO_PCF1_TIMER12_REMAP BIT(8) /*!< TIMER12 remapping */ -#define AFIO_PCF1_TIMER13_REMAP BIT(9) /*!< TIMER13 remapping */ -#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ -#define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ - -/* AFIO_CPSCTL */ -#define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ -#define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* GPIO mode values set */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) -#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) - -/* GPIO mode definitions */ -#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ -#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ -#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ -#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ -#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ -#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ -#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ -#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ - -/* GPIO output max speed value */ -#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ -#define GPIO_OSPEED_MAX ((uint8_t)0x04U) /*!< GPIO very high output speed, max speed more than 50MHz */ - -/* GPIO event output port definitions */ -#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ -#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ -#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ -#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ -#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ - -/* GPIO output port source definitions */ -#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ -#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ -#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ -#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ -#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ -#define GPIO_PORT_SOURCE_GPIOF ((uint8_t)0x05U) /*!< output port source F */ -#define GPIO_PORT_SOURCE_GPIOG ((uint8_t)0x06U) /*!< output port source G */ - -/* GPIO event output pin definitions */ -#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ -#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ -#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ -#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ -#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ -#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ -#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ -#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ -#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ -#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ -#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ -#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ -#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ -#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ -#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ -#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ - -/* GPIO output pin source definitions */ -#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ -#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ -#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ -#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ -#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ -#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ -#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ -#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ -#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ -#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ -#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ -#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ -#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ -#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ -#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ -#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* GPIO remap definitions */ -#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ -#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ -#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ -#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ -#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ -#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ -#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ -#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ -#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ -#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ -#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ -#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define GPIO_CAN_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN partial remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#define GPIO_CAN_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN full remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#endif /* GD32F30X_HD||GD32F30X_XD */ -#if (defined(GD32F30X_CL) || defined(GD32F30X_HD)) -#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping(only for GD32F30X_CL devices and GD32F30X_HD devices) */ -#endif /* GD32F30X_CL||GD32F30X_HD */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200002U) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200004U) /*!< ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200008U) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200010U) /*!< ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#endif /* GD32F30X_HD||GD32F30X_XD */ -#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ -#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled and SW-DP enabled */ -#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled and SW-DP disabled */ -#ifdef GD32F30X_CL -#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping(only for GD32F30X_CL devices) */ -#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping(only for GD32F30X_CL devices) */ -#define GPIO_ENET_REMAP ((uint32_t)0x00200020U) /*!< ENET remapping(only for GD32F30X_CL devices) */ -#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping(only for GD32F30X_CL devices) */ -#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping(only for GD32F30X_CL devices) */ -#define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) */ -#define GPIO_PTP_PPS_REMAP ((uint32_t)0x00204000U) /*!< ethernet PTP PPS remapping(only for GD32F30X_CL devices) */ -#endif /* GD32F30X_CL */ -#define GPIO_TIMER8_REMAP ((uint32_t)0x80000020U) /*!< TIMER8 remapping */ -#define GPIO_TIMER9_REMAP ((uint32_t)0x80000040U) /*!< TIMER9 remapping */ -#define GPIO_TIMER10_REMAP ((uint32_t)0x80000080U) /*!< TIMER10 remapping */ -#define GPIO_TIMER12_REMAP ((uint32_t)0x80000100U) /*!< TIMER12 remapping */ -#define GPIO_TIMER13_REMAP ((uint32_t)0x80000200U) /*!< TIMER13 remapping */ -#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ -#define GPIO_CTC_REMAP0 ((uint32_t)0x801B0800U) /*!< CTC remapping(PD15)*/ -#define GPIO_CTC_REMAP1 ((uint32_t)0x801B1000U) /*!< CTC remapping(PF0) */ - -#ifdef GD32F30X_CL -/* ethernet MII or RMII PHY selection */ -#define GPIO_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< configure ethernet MAC for connection with an MII PHY */ -#define GPIO_ENET_PHY_RMII AFIO_PCF0_ENET_PHY_SEL /*!< configure ethernet MAC for connection with an RMII PHY */ -#endif /* GD32F30X_CL */ - -/* I/O compensation cell enable/disable */ -#define GPIO_COMPENSATION_ENABLE AFIO_CPSCTL_CPS_EN /*!< I/O compensation cell is enable */ -#define GPIO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell is disable */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* reset alternate function I/O(AFIO) */ -void gpio_afio_deinit(void); -/* GPIO parameter initialization */ -void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -/* configure GPIO pin event output */ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); -/* enable GPIO pin event output */ -void gpio_event_output_enable(void); -/* disable GPIO pin event output */ -void gpio_event_output_disable(void); - -/* select GPIO pin exti sources */ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); - -#ifdef GD32F30X_CL -/* select ethernet MII or RMII PHY */ -void gpio_ethernet_phy_select(uint32_t enet_sel); -#endif /* GD32F30X_CL */ - -/* configure GPIO pin remap */ -void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue); - -/* configure the I/O compensation cell */ -void gpio_compensation_config(uint32_t compensation); -/* check the I/O compensation cell is ready or not */ -FlagStatus gpio_compensation_flag_get(void); - -#endif /* GD32F30X_GPIO_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h deleted file mode 100644 index cc48ecea8e..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h +++ /dev/null @@ -1,301 +0,0 @@ -/*! - \file gd32f30x_i2c.h - \brief definitions for the I2C -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_I2C_H -#define GD32F30X_I2C_H - -#include "gd32f30x.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ -#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_DISSTRC BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TRS BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_ECV BITS(8,15) /*!< packet error checking value */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ - -/* I2Cx_FMPCFG */ -#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ - -/* constants definitions */ -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_DISSTRC /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - -/* fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C flag definitions */ -#define I2C_FLAG_SBSEND BIT(0) /*!< start condition sent out in master mode */ -#define I2C_FLAG_ADDSEND BIT(1) /*!< address is sent in master mode or received and matches in slave mode */ -#define I2C_FLAG_BTC BIT(2) /*!< byte transmission finishes */ -#define I2C_FLAG_ADD10SEND BIT(3) /*!< header of 10-bit address is sent in master mode */ -#define I2C_FLAG_STPDET BIT(4) /*!< etop condition detected in slave mode */ -#define I2C_FLAG_RBNE BIT(6) /*!< I2C_DATA is not Empty during receiving */ -#define I2C_FLAG_TBE BIT(7) /*!< I2C_DATA is empty during transmitting */ -#define I2C_FLAG_BERR BIT(8) /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ -#define I2C_FLAG_LOSTARB BIT(9) /*!< arbitration lost in master mode */ -#define I2C_FLAG_AERR BIT(10) /*!< acknowledge error */ -#define I2C_FLAG_OUERR BIT(11) /*!< over-run or under-run situation occurs in slave mode */ -#define I2C_FLAG_PECERR BIT(12) /*!< PEC error when receiving data */ -#define I2C_FLAG_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_FLAG_SMBALT BIT(15) /*!< SMBus alert status */ -#define I2C_FLAG_MASTER (BIT(0)|BIT(31)) /*!< a flag indicating whether I2C block is in master or slave mode */ -#define I2C_FLAG_I2CBSY (BIT(1)|BIT(31)) /*!< busy flag */ -#define I2C_FLAG_TRS (BIT(2)|BIT(31)) /*!< whether the I2C is a transmitter or a receiver */ -#define I2C_FLAG_RXGC (BIT(4)|BIT(31)) /*!< general call address (00h) received */ -#define I2C_FLAG_DEFSMB (BIT(5)|BIT(31)) /*!< default address of SMBus device */ -#define I2C_FLAG_HSTSMB (BIT(6)|BIT(31)) /*!< SMBus host header detected in slave mode */ -#define I2C_FLAG_DUMOD (BIT(7)|BIT(31)) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ - -/* I2C interrupt flags */ -#define I2C_INT_FLAG_SBSEND I2C_FLAG_SBSEND /*!< start condition sent out in master mode interrupt flag */ -#define I2C_INT_FLAG_ADDSEND I2C_FLAG_ADDSEND /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ -#define I2C_INT_FLAG_BTC I2C_FLAG_BTC /*!< byte transmission finishes */ -#define I2C_INT_FLAG_ADD10SEND I2C_FLAG_ADD10SEND /*!< header of 10-bit address is sent in master mode interrupt flag */ -#define I2C_INT_FLAG_STPDET I2C_FLAG_STPDET /*!< stop condition detected in slave mode interrupt flag */ -#define I2C_INT_FLAG_RBNE I2C_FLAG_RBNE /*!< I2C_DATA is not Empty during receiving interrupt flag */ -#define I2C_INT_FLAG_TBE I2C_FLAG_TBE /*!< I2C_DATA is empty during transmitting interrupt flag */ -#define I2C_INT_FLAG_BERR I2C_FLAG_BERR /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ -#define I2C_INT_FLAG_LOSTARB I2C_FLAG_LOSTARB /*!< arbitration lost in master mode interrupt flag */ -#define I2C_INT_FLAG_AERR I2C_FLAG_AERR /*!< acknowledge error interrupt flag */ -#define I2C_INT_FLAG_OUERR I2C_FLAG_OUERR /*!< over-run or under-run situation occurs in slave mode interrupt flag */ -#define I2C_INT_FLAG_PECERR I2C_FLAG_PECERR /*!< PEC error when receiving data interrupt flag */ -#define I2C_INT_FLAG_SMBTO I2C_FLAG_SMBTO /*!< timeout signal in SMBus mode interrupt flag */ -#define I2C_INT_FLAG_SMBALT I2C_FLAG_SMBALT /*!< SMBus Alert status interrupt flag */ - -/* I2C interrupt enable bit */ -#define I2C_INT_ERR I2C_CTL1_ERRIE /*!< error interrupt enable */ -#define I2C_INT_EV I2C_CTL1_EVIE /*!< event interrupt enable */ -#define I2C_INT_BUF I2C_CTL1_BUFIE /*!< buffer interrupt enable */ - -/* I2C duty cycle in fast mode or fast mode plus */ -#define CKCFG_DTCY(regval) (BIT(14) & ((uint32_t)(regval) << 14)) -#define I2C_DTCY_2 CKCFG_DTCY(0) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 CKCFG_DTCY(1) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define SADDR0_ADDFORMAT(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define I2C_ADDFORMAT_7BITS SADDR0_ADDFORMAT(0) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS SADDR0_ADDFORMAT(1) /*!< address:10 bits */ - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master send slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* dual-address mode switch */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); - -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* I2C DMA mode enable */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* flag indicating DMA last transfer */ -void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara ); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,uint32_t intflag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph,uint32_t intflag); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -#endif /* GD32F30X_I2C_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h deleted file mode 100644 index 97ff25ff0a..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h +++ /dev/null @@ -1,68 +0,0 @@ -/*! - \file gd32f30x_misc.h - \brief definitions for the MISC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef GD32F30X_MISC_H -#define GD32F30X_MISC_H - -#include "gd32f30x.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ -/* set the priority group */ -void nvic_priority_group_set(uint32_t nvic_prigroup); - -/* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); -/* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32F30X_MISC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h deleted file mode 100644 index 53070e97b6..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h +++ /dev/null @@ -1,160 +0,0 @@ -/*! - \file gd32f30x_pmu.h - \brief definitions for the PMU -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef GD32F30X_PMU_H -#define GD32F30X_PMU_H - -#include "gd32f30x.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ -#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ -#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ -#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ -#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ -#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ -#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ -#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ -#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - -/* PMU LDO output voltage select definitions */ -#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ -#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ -#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ - -/* PMU high-driver mode switch */ -#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) -#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ -#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ - -/* PMU low-driver mode when use low power LDO */ -#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) -#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ -#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ - -/* PMU low-driver mode when use normal power LDO */ -#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) -#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ -#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ - -/* PMU low power mode ready flag definitions */ -#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ -#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ -#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ -#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ -#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ -#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU registers */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* select LDO output voltage */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* functions of low-driver mode and high-driver mode in deep-sleep mode */ -/* switch high-driver mode */ -void pmu_highdriver_switch_select(uint32_t highdr_switch); -/* enable high-driver mode */ -void pmu_highdriver_mode_enable(void); -/* disable high-driver mode */ -void pmu_highdriver_mode_disable(void); -/* enable low-driver mode in deep-sleep mode */ -void pmu_lowdriver_mode_enable(void); -/* disable low-driver mode in deep-sleep mode */ -void pmu_lowdriver_mode_disable(void); -/* in deep-sleep mode, driver mode when use low power LDO */ -void pmu_lowpower_driver_config(uint32_t mode); -/* in deep-sleep mode, driver mode when use normal power LDO */ -void pmu_normalpower_driver_config(uint32_t mode); - -/* set PMU mode */ -/* PMU work at sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(void); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(void); - -/* backup related functions */ -/* enable backup domain write */ -void pmu_backup_write_enable(void); -/* disable backup domain write */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag_reset); -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); - -#endif /* GD32F30X_PMU_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h deleted file mode 100644 index b408df9ae5..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h +++ /dev/null @@ -1,1027 +0,0 @@ -/*! - \file gd32f30x_rcu.h - \brief definitions for the RCU -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_RCU_H -#define GD32F30X_RCU_H - -#include "gd32f30x.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ -#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ -#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ -#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ -#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ -#elif defined(GD32F30X_CL) -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ -#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ -#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ -#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ -#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* bits definitions */ -/* RCU_CTL */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#elif defined(GD32F30X_CL) -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ -#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ -#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ -#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* RCU_CFG0 */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0 BIT(17) /*!< PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBDPSC BITS(22,23) /*!< USBD clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,26) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_PLLMF_4 BIT(27) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ -#define RCU_CFG0_USBDPSC_2 BIT(31) /*!< bit 2 of USBDPSC */ -#elif defined(GD32F30X_CL) -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ -#define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* RCU_INT */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K Stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M Stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#elif defined(GD32F30X_CL) -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ -#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ -#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ -#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ -#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ -#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ -#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ -#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ -#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ -#define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ -#define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ -#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ -#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#ifndef GD32F30X_CL -#define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ -#endif /* GD32F30X_CL */ -#ifndef GD32F30X_HD -#define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ -#define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ -#define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ -#endif /* GD32F30X_HD */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ -#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ -#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ -#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ -#ifndef GD32F30X_HD -#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ -#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ -#endif /* GD32F30X_HD */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ -#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ -#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_APB1RST_USBDRST BIT(23) /*!< USBD reset */ -#endif /* GD32F30X_HD and GD32F30X_XD */ -#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ -#ifdef GD32F30X_CL -#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ -#endif /* GD32F30X_CL */ -#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ -#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ -#elif defined(GD32F30X_CL) -#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ -#define RCU_AHBEN_ENETEN BIT(14) /*!< ENET clock enable */ -#define RCU_AHBEN_ENETTXEN BIT(15) /*!< Ethernet TX clock enable */ -#define RCU_AHBEN_ENETRXEN BIT(16) /*!< Ethernet RX clock enable */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ -#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ -#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ -#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ -#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ -#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ -#define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ -#define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ -#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ -#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#ifndef GD32F30X_CL -#define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ -#endif /* GD32F30X_CL */ -#ifndef GD32F30X_HD -#define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ -#define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ -#define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ -#endif /* GD32F30X_HD */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ -#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ -#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ -#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ -#ifndef GD32F30X_HD -#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ -#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ -#endif /* GD32F30X_HD */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ -#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ -#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_APB1EN_USBDEN BIT(23) /*!< USBD clock enable */ -#endif /* GD32F30X_HD and GD32F30X_XD */ -#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ -#ifdef GD32F30X_CL -#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ -#endif /* GD32F30X_CL */ -#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -#ifdef GD32F30X_CL -/* RCU_AHBRST */ -#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ -#define RCU_AHBRST_ENETRST BIT(14) /*!< ENET reset */ -#endif /* GD32F30X_CL */ - -/* RCU_CFG1 */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ -#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ -#elif defined(GD32F30X_CL) -#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ -#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ -#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ -#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ -#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ -#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ -#define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ -#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ -#define RCU_CFG1_PLL2MF_4 BIT(31) /*!< bit 5 of PLL2MF */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ - -/* RCU_ADDCTL */ -#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ -#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ -#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ -#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ - -/* RCU_ADDINT */ -#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ -#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ -#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ - -/* RCU_ADDAPB1RST */ -#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ - -/* RCU_ADDAPB1EN */ -#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ - - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -/* peripherals enable */ -#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ -#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ -#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ -#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ - -/* peripherals reset */ -#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ -#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ -#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ -#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ -#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ - -/* clock control */ -#define CTL_REG_OFFSET 0x00U /*!< control register offset */ -#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ -#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ - -/* clock stabilization and stuck interrupt */ -#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ -#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ - -/* configuration register */ -#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ -#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ - -/* peripheral clock enable */ -typedef enum -{ - /* AHB peripherals */ - RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ - RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ - RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ - RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ -#elif defined(GD32F30X_CL) - RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ - RCU_ENET = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 14U), /*!< ENET clock */ - RCU_ENETTX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 15U), /*!< ENETTX clock */ - RCU_ENETRX = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 16U), /*!< ENETRX clock */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ -#ifndef GD32F30X_HD - RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ - RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ -#endif /* GD32F30X_HD */ - RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - RCU_USBD = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< USBD clock */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ -#ifdef GD32F30X_CL - RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ -#endif /* GD32F30X_CL */ - RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ - RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ - - /* APB2 peripherals */ - RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ - RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ - RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ - RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ - RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ - RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ - RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ - RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ -#ifndef GD32F30X_CL - RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ -#endif /* GD32F30X_CL */ -#ifndef GD32F30X_HD - RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ - RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ - RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ -#endif /* GD32F30X_HD */ -}rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum -{ - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ -}rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum -{ - /* AHB peripherals */ -#ifdef GD32F30X_CL - RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 14U), /*!< ENET clock reset */ -#endif /* GD32F30X_CL */ - - /* APB1 peripherals */ - RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ - RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ - RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ - RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ -#ifndef GD32F30X_HD - RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ - RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ -#endif /* GD32F30X_HD */ - RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ - RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ - RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ - RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ - RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ - RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - RCU_USBDRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< USBD clock reset */ -#endif /* GD32F30X_HD and GD32F30X_XD */ - RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ -#ifdef GD32F30X_CL - RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ -#endif /* GD32F30X_CL */ - RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ - RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ - RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< RTC clock reset */ - - /* APB2 peripherals */ - RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ - RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ - RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ - RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ - RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ - RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ - RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ -#ifndef GD32F30X_CL - RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ -#endif /* GD32F30X_CL */ -#ifndef GD32F30X_HD - RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ - RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ - RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ -#endif /* GD32F30X_HD */ -}rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum -{ - /* clock stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ -#ifdef GD32F30X_CL - RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ - RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ -#endif /* GD32F30X_CL */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ - RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ - /* reset source flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ -}rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ -#ifdef GD32F30X_CL - RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ - RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ -#endif /* GD32F30X_CL */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ - RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ -}rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ -#ifdef GD32F30X_CL - RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ -#endif /* GD32F30X_CL */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ - RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ -}rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum -{ - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ -#ifdef GD32F30X_CL - RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ - RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ -#endif /* GD32F30X_CL */ - RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ -}rcu_int_enum; - -/* oscillator types */ -typedef enum -{ - RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ - RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ - RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ -#ifdef GD32F30X_CL - RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ - RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ -#endif /* GD32F30X_CL */ -}rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum -{ - CK_SYS = 0, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ -}rcu_clock_freq_enum; - -/* RCU_CFG0 register bit define */ -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC prescaler select */ -#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ -#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ -#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ -#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ -#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ -#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ -#define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/5 */ -#define RCU_CKADC_CKAHB_DIV6 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/6 */ -#define RCU_CKADC_CKAHB_DIV10 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/10 */ -#define RCU_CKADC_CKAHB_DIV20 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/20 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ -#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */ - -/* PLL clock multiplication factor */ -#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ -#define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */ -#define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */ - -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ -#elif defined(GD32F30X_CL) -#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ -#endif /* GD32F30X_HD and GD32F30X_XD */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ -#define RCU_PLL_MUL33 (PLLMF_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 33 */ -#define RCU_PLL_MUL34 (PLLMF_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 34 */ -#define RCU_PLL_MUL35 (PLLMF_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 35 */ -#define RCU_PLL_MUL36 (PLLMF_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 36 */ -#define RCU_PLL_MUL37 (PLLMF_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 37 */ -#define RCU_PLL_MUL38 (PLLMF_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 38 */ -#define RCU_PLL_MUL39 (PLLMF_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 39 */ -#define RCU_PLL_MUL40 (PLLMF_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 40 */ -#define RCU_PLL_MUL41 (PLLMF_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 41 */ -#define RCU_PLL_MUL42 (PLLMF_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 42 */ -#define RCU_PLL_MUL43 (PLLMF_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 43 */ -#define RCU_PLL_MUL44 (PLLMF_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 44 */ -#define RCU_PLL_MUL45 (PLLMF_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 45 */ -#define RCU_PLL_MUL46 (PLLMF_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 46 */ -#define RCU_PLL_MUL47 (PLLMF_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 47 */ -#define RCU_PLL_MUL48 (PLLMF_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 48 */ -#define RCU_PLL_MUL49 (PLLMF_4_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 49 */ -#define RCU_PLL_MUL50 (PLLMF_4_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 50 */ -#define RCU_PLL_MUL51 (PLLMF_4_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 51 */ -#define RCU_PLL_MUL52 (PLLMF_4_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 52 */ -#define RCU_PLL_MUL53 (PLLMF_4_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 53 */ -#define RCU_PLL_MUL54 (PLLMF_4_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 54 */ -#define RCU_PLL_MUL55 (PLLMF_4_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 55 */ -#define RCU_PLL_MUL56 (PLLMF_4_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 56 */ -#define RCU_PLL_MUL57 (PLLMF_4_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 57 */ -#define RCU_PLL_MUL58 (PLLMF_4_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 58 */ -#define RCU_PLL_MUL59 (PLLMF_4_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 59 */ -#define RCU_PLL_MUL60 (PLLMF_4_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 60 */ -#define RCU_PLL_MUL61 (PLLMF_4_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 61 */ -#define RCU_PLL_MUL62 (PLLMF_4_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 62 */ -#define RCU_PLL_MUL63 (PLLMF_4_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 63 */ - -#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define USBPSC_2 RCU_CFG0_USBDPSC_2 -#elif defined(GD32F30X_CL) -#define USBPSC_2 RCU_CFG0_USBFSPSC_2 -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* USBD/USBFS prescaler select */ -#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBD/USBFS prescaler select CK_PLL/1.5 */ -#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBD/USBFS prescaler select CK_PLL/1 */ -#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBD/USBFS prescaler select CK_PLL/2.5 */ -#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBD/USBFS prescaler select CK_PLL/2 */ -#define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBD/USBFS prescaler select CK_PLL/3.5 */ -#define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBD/USBFS prescaler select CK_PLL/3 */ -#define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBD/USBFS prescaler select CK_PLL/4 */ - -/* CKOUT0 Clock source selection */ -#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ -#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ -#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ -#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ -#ifdef GD32F30X_CL -#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ -#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ -#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ -#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ -#endif /* GD32F30X_CL */ - -/* LXTAL drive capability */ -#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ -#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ -#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ -#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ -#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - -/* PREDV0 division factor */ -#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ -#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ -#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ -#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ -#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ -#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ -#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ -#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ -#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ -#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ -#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ -#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ -#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ -#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ -#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ -#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - -/* PREDV1 division factor */ -#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ -#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ -#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ -#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ -#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ -#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ -#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ -#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ -#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ -#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ -#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ -#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ -#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ -#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ -#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ -#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - -/* PLL1 clock multiplication factor */ -#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ -#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ -#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ -#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ -#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ -#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ -#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ -#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ -#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ -#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - -/* PLL2 clock multiplication factor */ -#define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */ - -#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ -#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ -#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ -#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ -#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ -#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ -#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ -#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ -#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ -#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ -#define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 18 */ -#define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 19 */ -#define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 21 */ -#define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 22 */ -#define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 23 */ -#define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 24 */ -#define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 25 */ -#define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 26 */ -#define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 27 */ -#define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 28 */ -#define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 29 */ -#define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 30 */ -#define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 31 */ -#define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 32 */ -#define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 40 */ - -#ifdef GD32F30X_CL -/* PREDV0 input clock source selection */ -#define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */ -#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ - -/* I2S1 clock source selection */ -#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ -#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ - -/* I2S2 clock source selection */ -#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ -#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ -#endif /* GD32F30X_CL */ - -/* PLL input clock source selection */ -#define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */ -#define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ - -/* deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ - -/* 48MHz clock selection */ -#define RCU_CK48MSRC_CKPLL ((uint32_t)0x00000000U) /*!< use CK_PLL clock */ -#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< select IRC48M clock */ - -/* function declarations */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP domain */ -void rcu_bkp_reset_enable(void); -/* disable the BKP domain reset */ -void rcu_bkp_reset_disable(void); - -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the CK_OUT0 clock source and divider */ -void rcu_ckout0_config(uint32_t ckout0_src); -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -/* configure the PLL clock source preselection */ -void rcu_pllpresel_config(uint32_t pll_presel); -#if(defined(GD32F30X_HD) || defined(GD32F30X_XD)) -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_div); -#elif defined(GD32F30X_CL) -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); -/* configure the PREDV1 division factor */ -void rcu_predv1_config(uint32_t predv1_div); -/* configure the PLL1 clock */ -void rcu_pll1_config(uint32_t pll_mul); -/* configure the PLL2 clock */ -void rcu_pll2_config(uint32_t pll_mul); -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/* configure the ADC division factor */ -void rcu_adc_clock_config(uint32_t adc_psc); -/* configure the USBD/USBFS prescaler factor */ -void rcu_usb_clock_config(uint32_t usb_psc); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -#ifdef GD32F30X_CL -/* configure the I2S1 clock source selection */ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source); -/* configure the I2S2 clock source selection */ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source); -#endif /* GD32F30X_CL */ -/* configure the CK48M clock selection */ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); - - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); - -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32F30X_RCU_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h deleted file mode 100644 index 427ba955c0..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h +++ /dev/null @@ -1,111 +0,0 @@ -/*! - \file gd32f30x_rtc.h - \brief definitions for the RTC -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_RTC_H -#define GD32F30X_RTC_H - -#include "gd32f30x.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ -#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ -#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ -#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ -#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ -#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ -#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ -#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ -#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ -#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ - -/* bits definitions */ -/* RTC_INTEN */ -#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ -#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ -#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ - -/* RTC_CTL */ -#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ -#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ -#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ -#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ -#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ -#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - -/* RTC_PSC */ -#define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ -#define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ - -/* RTC_DIV */ -#define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ -#define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ - -/* RTC_CNT */ -#define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ -#define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ - -/* RTC_ALRM */ -#define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ -#define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ - -/* constants definitions */ -#define RTC_HIGH_VALUE 0x000F0000U /*!< RTC high value */ -#define RTC_LOW_VALUE 0x0000FFFFU /*!< RTC low value */ - -/* RTC interrupt enable or disable definitions */ -#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ -#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ -#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ - -/* RTC flag definitions */ -#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ -#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ - -/* function declarations */ -/* enable RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disable RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); - -/* enter RTC configuration mode */ -void rtc_configuration_mode_enter(void); -/* exit RTC configuration mode */ -void rtc_configuration_mode_exit(void); - -/* wait RTC last write operation finished flag set */ -void rtc_lwoff_wait(void); -/* wait RTC registers synchronized flag set */ -void rtc_register_sync_wait(void); - -/* get RTC counter value */ -uint32_t rtc_counter_get(void); -/* set RTC counter value */ -void rtc_counter_set(uint32_t cnt); - -/* set RTC prescaler value */ -void rtc_prescaler_set(uint32_t psc); -/* set RTC alarm value */ -void rtc_alarm_config(uint32_t alarm); -/* get RTC divider value */ -uint32_t rtc_divider_get(void); - -/* get RTC flag status */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear RTC flag status */ -void rtc_flag_clear(uint32_t flag); - -#endif /* GD32F30X_RTC_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h deleted file mode 100644 index 46c7bdd4e4..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h +++ /dev/null @@ -1,404 +0,0 @@ -/*! - \file gd32f30x_sdio.h - \brief definitions for the SDIO -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_SDIO_H -#define GD32F30X_SDIO_H - -#include "gd32f30x.h" - -/* SDIO definitions */ -#define SDIO SDIO_BASE - -/* registers definitions */ -#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ -#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ -#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ -#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ -#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ -#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ -#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ -#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ -#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ -#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ -#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ -#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ -#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ -#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ -#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ -#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ -#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ -#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ - -/* bits definitions */ -/* SDIO_PWRCTL */ -#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ - -/* SDIO_CLKCTL */ -#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ -#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ -#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ -#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ -#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ -#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ -#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ - -/* SDIO_CMDAGMT */ -#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ - -/* SDIO_CMDCTL */ -#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ -#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ -#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ -#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ -#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ -#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ -#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ -#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ -#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ - -/* SDIO_DATATO */ -#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ - -/* SDIO_DATALEN */ -#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ - -/* SDIO_DATACTL */ -#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ -#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ -#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ -#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ -#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ -#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ -#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ -#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ -#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ - -/* SDIO_STAT */ -#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ -#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ -#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ -#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ -#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ -#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ -#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ -#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ -#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ -#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ -#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ -#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ -#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ -#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ -#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ -#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ -#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ -#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ -#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ -#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ -#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ -#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ -#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ -#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ - -/* SDIO_INTC */ -#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ -#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ -#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ -#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ -#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ -#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ -#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ -#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ -#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ -#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ -#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ -#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ -#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ - -/* SDIO_INTEN */ -#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ -#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ -#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ -#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ -#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ -#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ -#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ -#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ -#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ -#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ -#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ -#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ -#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ -#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ -#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ -#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ -#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ -#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ -#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ -#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ -#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ -#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ -#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ -#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ - -/* SDIO_FIFO */ -#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ - -/* constants definitions */ -/* SDIO flags */ -#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ -#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ -#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ -#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ -#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ -#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ -#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ -#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ -#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ -#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ -#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ -#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ -#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ -#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ -#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ -#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ -#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ -#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ -#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ -#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ -#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ -#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ -#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ -#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ - -/* SDIO interrupt enable or disable */ -#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ -#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ -#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ -#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ -#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ -#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ -#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ -#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ -#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ -#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ -#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ -#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ -#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ -#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ -#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ -#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ -#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ -#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ -#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ -#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ -#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ -#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ -#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ -#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ - -/* SDIO interrupt flags */ -#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ -#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ -#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ -#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ -#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt */ -#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt */ -#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ -#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ -#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt */ -#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt */ -#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ -#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ -#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ -#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ -#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt */ -#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt */ -#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt */ -#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt */ -#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt */ -#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt */ -#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ -#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ -#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ -#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ - -/* SDIO power control */ -#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ -#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ - -/* SDIO card bus mode control */ -#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ -#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ -#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ - -/* SDIO_CLK clock edge selection */ -#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ -#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ - -/* clock bypass enable or disable */ -#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */ -#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ - -/* SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */ -#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ - -/* SDIO command response type */ -#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ -#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ -#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ - -/* command state machine wait type */ -#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */ -#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ -#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ - -#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */ -#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */ -#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */ -#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ - -/* SDIO data block size */ -#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ -#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ -#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ -#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ -#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ -#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ -#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ -#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ -#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ -#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ -#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ -#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ -#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ -#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ -#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ - -/* SDIO data transfer mode */ -#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */ -#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ - -/* SDIO data transfer direction */ -#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */ -#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ - -/* SDIO read wait type */ -#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */ -#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ - -/* function declarations */ -/* deinitialize the SDIO */ -void sdio_deinit(void); -/* configure the SDIO clock */ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); -/* enable hardware clock control */ -void sdio_hardware_clock_enable(void); -/* disable hardware clock control */ -void sdio_hardware_clock_disable(void); -/* set different SDIO card bus mode */ -void sdio_bus_mode_set(uint32_t bus_mode); -/* set the SDIO power state */ -void sdio_power_state_set(uint32_t power_state); -/* get the SDIO power state */ -uint32_t sdio_power_state_get(void); -/* enable SDIO_CLK clock output */ -void sdio_clock_enable(void); -/* disable SDIO_CLK clock output */ -void sdio_clock_disable(void); - -/* configure the command index, argument, response type, wait type and CSM to send command */ -/* configure the command and response */ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); -/* set the command state machine wait type */ -void sdio_wait_type_set(uint32_t wait_type); -/* enable the CSM(command state machine) */ -void sdio_csm_enable(void); -/* disable the CSM(command state machine) */ -void sdio_csm_disable(void); -/* get the last response command index */ -uint8_t sdio_command_index_get(void); -/* get the response for the last received command */ -uint32_t sdio_response_get(uint32_t responsex); - -/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */ -/* configure the data timeout, data length and data block size */ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); -/* configure the data transfer mode and direction */ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); -/* enable the DSM(data state machine) for data transfer */ -void sdio_dsm_enable(void); -/* disable the DSM(data state machine) */ -void sdio_dsm_disable(void); -/* write data(one word) to the transmit FIFO */ -void sdio_data_write(uint32_t data); -/* read data(one word) from the receive FIFO */ -uint32_t sdio_data_read(void); -/* get the number of remaining data bytes to be transferred to card */ -uint32_t sdio_data_counter_get(void); -/* get the number of words remaining to be written or read from FIFO */ -uint32_t sdio_fifo_counter_get(void); -/* enable the DMA request for SDIO */ -void sdio_dma_enable(void); -/* disable the DMA request for SDIO */ -void sdio_dma_disable(void); - -/* get the flags state of SDIO */ -FlagStatus sdio_flag_get(uint32_t flag); -/* clear the pending flags of SDIO */ -void sdio_flag_clear(uint32_t flag); -/* enable the SDIO interrupt */ -void sdio_interrupt_enable(uint32_t int_flag); -/* disable the SDIO interrupt */ -void sdio_interrupt_disable(uint32_t int_flag); -/* get the interrupt flags state of SDIO */ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); -/* clear the interrupt pending flags of SDIO */ -void sdio_interrupt_flag_clear(uint32_t int_flag); - -/* enable the read wait mode(SD I/O only) */ -void sdio_readwait_enable(void); -/* disable the read wait mode(SD I/O only) */ -void sdio_readwait_disable(void); -/* enable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_enable(void); -/* disable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_disable(void); -/* set the read wait type(SD I/O only) */ -void sdio_readwait_type_set(uint32_t readwait_type); -/* enable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_enable(void); -/* disable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_disable(void); -/* enable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_enable(void); -/* disable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_disable(void); - -/* enable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_enable(void); -/* disable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_disable(void); -/* enable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_enable(void); -/* disable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_disable(void); -/* enable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_enable(void); -/* disable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_disable(void); - -#endif /* GD32F30X_SDIO_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h deleted file mode 100644 index efef2879bb..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h +++ /dev/null @@ -1,328 +0,0 @@ -/*! - \file gd32f30x_spi.h - \brief definitions for the SPI -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_SPI_H -#define GD32F30X_SPI_H - -#include "gd32f30x.h" - -/* SPIx(x=0,1,2) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE -#define SPI2 (SPI_BASE + 0x00000400U) - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register(only SPI0) */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ -#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error bit */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCR BITS(0,15) /*!< RX CRC register */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* SPI_QCTL(only for SPI0) */ -#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ -#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ -#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct -{ - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE ~SPI_CTL0_BDOEN /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI frame size */ -#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ -#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ - -/* function declarations */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize SPI parameter */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); - -/* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); - -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); - -/* enable SPI TI mode */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* disable SPI TI mode */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* enable SPI NSS pulse mode */ -void spi_nssp_mode_enable(uint32_t spi_periph); -/* disable SPI NSS pulse mode */ -void spi_nssp_mode_disable(uint32_t spi_periph); - -/* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); -/* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); -/* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); -/* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); - -#endif /* GD32F30X_SPI_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h deleted file mode 100644 index a271d4fed8..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h +++ /dev/null @@ -1,716 +0,0 @@ -/*! - \file gd32f30x_timer.h - \brief definitions for the TIMER -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.2, firmware for GD32F30x -*/ - -#ifndef GD32F30X_TIMER_H -#define GD32F30X_TIMER_H - -#include "gd32f30x.h" - -/* TIMERx(x=0..13) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER1 (TIMER_BASE + 0x00000000U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER3 (TIMER_BASE + 0x00000800U) -#define TIMER4 (TIMER_BASE + 0x00000C00U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER6 (TIMER_BASE + 0x00001400U) -#define TIMER7 (TIMER_BASE + 0x00013400U) -#define TIMER8 (TIMER_BASE + 0x00014C00U) -#define TIMER9 (TIMER_BASE + 0x00015000U) -#define TIMER10 (TIMER_BASE + 0x00015400U) -#define TIMER11 (TIMER_BASE + 0x00001800U) -#define TIMER12 (TIMER_BASE + 0x00001C00U) -#define TIMER13 (TIMER_BASE + 0x00002000U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ -#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ -#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< channel control update DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* TIMER_IRMP */ -#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ - -/* TIMER_CFG */ -#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ -#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ - -/* constants definitions */ -/* TIMER init parameter struct definitions*/ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint32_t period; /*!< period value */ - uint16_t clockdivision; /*!< clock division value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions*/ -typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint32_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint32_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP ((uint32_t)0x00000001U) /*!< update interrupt */ -#define TIMER_INT_CH0 ((uint32_t)0x00000002U) /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 ((uint32_t)0x00000004U) /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 ((uint32_t)0x00000008U) /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 ((uint32_t)0x00000010U) /*!< channel 3 interrupt */ -#define TIMER_INT_CMT ((uint32_t)0x00000020U) /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG ((uint32_t)0x00000040U) /*!< trigger interrupt */ -#define TIMER_INT_BRK ((uint32_t)0x00000080U) /*!< break interrupt */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ -#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ -#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ -#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ -#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ -#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ -#define TIMER_INT_FLAG_BRK TIMER_INT_BRK - -/* TIMER flag */ -#define TIMER_FLAG_UP ((uint32_t)0x00000001U) /*!< update flag */ -#define TIMER_FLAG_CH0 ((uint32_t)0x00000002U) /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 ((uint32_t)0x00000004U) /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 ((uint32_t)0x00000008U) /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 ((uint32_t)0x00000010U) /*!< channel 3 flag */ -#define TIMER_FLAG_CMT ((uint32_t)0x00000020U) /*!< channel control update flag */ -#define TIMER_FLAG_TRG ((uint32_t)0x00000040U) /*!< trigger flag */ -#define TIMER_FLAG_BRK ((uint32_t)0x00000080U) /*!< break flag */ -#define TIMER_FLAG_CH0O ((uint32_t)0x00000200U) /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O ((uint32_t)0x00000400U) /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O ((uint32_t)0x00000800U) /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O ((uint32_t)0x00001000U) /*!< channel 3 overcapture flag */ - -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)0x0100U) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)0x0200U) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)0x0400U) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)0x0800U) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)0x1000U) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)0x2000U) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)0x4000U) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel y(y=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ - -/* channel enable state*/ -#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ - -/* channel complementary output enable state*/ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable. */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge(not for timer1..6) */ - -/* timer input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CC0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ - -/* timerx(x=0,1,2,13,14,15,16) write cc register selection */ -#define TIMER_CCSEL_DISABLE ((uint16_t)0x0000U) /*!< write CC register selection disable */ -#define TIMER_CCSEL_ENABLE ((uint16_t)0x0002U) /*!< write CC register selection enable */ - -/* the output value selection */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ -#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ - -/* function declarations */ -/* TIMER timebase */ -/* deinit a TIMER */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a TIMER */ -void timer_enable(uint32_t timer_periph); -/* disable a TIMER */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint8_t update); - -/* TIMER interrupt and flag */ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -/* timer DMA and event */ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* timer channel complementary protection */ -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* configure TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* channel capture/compare control shadow register enable */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); - -/* TIMER channel output */ -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode); - -/* TIMER master and slave */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t expolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t expolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); - -/* TIMER configure */ -/* configure TIMER write CHxVAL register selection */ -void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel); -/* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); - -#endif /* GD32F30X_TIMER_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h deleted file mode 100644 index f16d2c7dc6..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h +++ /dev/null @@ -1,418 +0,0 @@ -/*! - \file gd32f30x_usart.h - \brief definitions for GD32F30x -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#ifndef GD32F30X_USART_H -#define GD32F30X_USART_H - -#include "gd32f30x.h" - -/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ -#define USART1 USART_BASE /*!< USART1 base address */ -#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ -#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ -#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ -#define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ - -/* registers definitions */ -#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ -#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ -#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ -#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ -#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ -#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ -#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ -#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ - -/* bits definitions */ -/* USARTx_STAT0 */ -#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT0_TC BIT(6) /*!< transmission complete */ -#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ - -/* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ - -/* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* USARTx_CTL3 */ -#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ -#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ -#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ -#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ -#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ -#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ -#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ - -/* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ - -/* USARTx_STAT1 */ -#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT1_BSY BIT(16) /*!< busy flag */ - -/* constants definitions */ -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ - -/* USART flags */ -typedef enum -{ - /* flags in STAT0 register */ - USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ - /* flags in STAT1 register */ - USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ - /* interrupt flags in CTL3 register */ - USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ - USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ - /* interrupt in CTL3 register */ - USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ - USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ -}usart_interrupt_enum; - -/* USART invert configure */ -typedef enum -{ - /* data bit level inversion */ - USART_DINV_ENABLE, /*!< data bit level inversion */ - USART_DINV_DISABLE, /*!< data bit level not inversion */ - /* TX pin level inversion */ - USART_TXPIN_ENABLE, /*!< TX pin level inversion */ - USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ - /* RX pin level inversion */ - USART_RXPIN_ENABLE, /*!< RX pin level inversion */ - USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ -}usart_invert_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ - -/* USART CK length */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART DMA request for receive configure */ -#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ - -/* USART DMA request for transmission configure */ -#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ - -/* USART RTS configure */ -#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ - -/* USART CTS configure */ -#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* USART data is transmitted/received with the LSB/MSB first */ -#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ -#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); - -/* USART normal mode communication */ -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); -/* data is transmitted/received with the LSB/MSB first */ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); -/* configure USART inverted */ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); -/* enable receiver timeout */ -void usart_receiver_timeout_enable(uint32_t usart_periph); -/* disable receiver timeout */ -void usart_receiver_timeout_disable(uint32_t usart_periph); -/* configure receiver timeout threshold */ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* LIN mode enable */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* LIN mode disable */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen); -/* send break frame */ -void usart_send_break(uint32_t usart_periph); - -/* half-duplex communication */ -/* half-duplex enable */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* half-duplex disable */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* clock enable */ -void usart_synchronous_clock_enable(uint32_t usart_periph); -/* clock disable */ -void usart_synchronous_clock_disable(uint32_t usart_periph); -/* configure usart synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* guard time value configure in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph,uint32_t guat); -/* smartcard mode enable */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* smartcard mode disable */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* NACK enable in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* NACK disable in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* smartcard auto-retry number configure */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* block length configure */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); - -/* flag functions */ -/* get flag in STAT0/STAT1 register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT0/STAT1 register */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); - -/* interrupt functions */ -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); -/* clear interrupt flag in STAT0/STAT1 register */ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); -#endif /* GD32F30x_USART_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h deleted file mode 100644 index 5ee21d9a2e..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h +++ /dev/null @@ -1,63 +0,0 @@ -/*! - \file gd32f30x_wwdgt.h - \brief definitions for the WWDGT -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef GD32F30X_WWDGT_H -#define GD32F30X_WWDGT_H - -#include "gd32f30x.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32F30X_WWDGT_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c deleted file mode 100644 index a5d40072df..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c +++ /dev/null @@ -1,915 +0,0 @@ -/*! - \file gd32f30x_adc.c - \brief ADC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.2, firmware for GD32F30x -*/ - -#include "gd32f30x_adc.h" - -/*! - \brief reset ADC - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_deinit(uint32_t adc_periph) -{ - switch(adc_periph){ - case ADC0: - rcu_periph_reset_enable(RCU_ADC0RST); - rcu_periph_reset_disable(RCU_ADC0RST); - break; - case ADC1: - rcu_periph_reset_enable(RCU_ADC1RST); - rcu_periph_reset_disable(RCU_ADC1RST); - break; -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - case ADC2: - rcu_periph_reset_enable(RCU_ADC2RST); - rcu_periph_reset_disable(RCU_ADC2RST); - break; -#endif - default: - break; - } -} - -/*! - \brief enable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_enable(uint32_t adc_periph) -{ - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_disable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_calibration_enable(uint32_t adc_periph) -{ - /* reset the selected ADC1 calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while((ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while((ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ - } -} - -/*! - \brief enable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief configure ADC resolution - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] resolution: ADC resolution - only one among these parameters can be selected - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) -{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES); - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution; -} - -/*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group - only one among these parameters can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* config the number of conversions in discontinuous mode */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U)); - - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - default: - break; - } -} - -/*! - \brief configure the ADC sync mode - \param[in] mode: ADC mode - only one among these parameters can be selected - \arg ADC_MODE_FREE: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only - \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only - \param[out] none - \retval none -*/ -void adc_mode_config(uint32_t mode) -{ - ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); - ADC_CTL0(ADC0) |= mode; -} - -/*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] function: the function to config - one or more parameters can be selected below - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (function & ADC_SCAN_MODE)){ - ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ - ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] data_alignment: data alignment select - only one parameter can be selected - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment){ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group - only one parameter can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); - - break; - case ADC_INSERTED_CHANNEL: - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-1U)); - - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one among these parameters can be selected - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < 6U){ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); - rsq |= ((uint32_t)adc_channel << (5U*rank)); - ADC_RSQ2(adc_periph) = rsq; - }else if(rank < 12U){ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); - rsq |= ((uint32_t)adc_channel << (5U*(rank-6U))); - ADC_RSQ1(adc_periph) = rsq; - }else if(rank < 16U){ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); - rsq |= ((uint32_t)adc_channel << (5U*(rank-12U))); - ADC_RSQ0(adc_periph) = rsq; - }else{ - } - - /* ADC sampling time config */ - if(adc_channel < 10U){ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); - sampt |= (uint32_t)(sample_time << (3U*adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < 18U){ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); - sampt |= (uint32_t)(sample_time << (3U*(adc_channel-10U))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - only one among these parameters can be selected - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U-(inserted_length-rank)*5U))); - isq |= ((uint32_t)adc_channel << (15U-(inserted_length-rank)*5U)); - ADC_ISQ(adc_periph) = isq; - - /* ADC sampling time config */ - if(adc_channel < 10U){ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*adc_channel))); - sampt |= (uint32_t) sample_time << (3U*adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < 18U){ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(adc_channel-10U)))); - sampt |= ((uint32_t)sample_time << (3U*(adc_channel-10U))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] inserted_channel : insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset : the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - num = 3U - (inserted_length - inserted_channel); - - if(num <= 3U){ - /* calculate the offset of the register */ - num = num * 4U; - /* config the offset of the selected channels */ - REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief enable ADC external trigger - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; - } - }else{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief configure ADC external trigger source - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group - only one parameter can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected - for regular channel: - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select - \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select - \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11 - \arg ADC2_EXTTRIG_REGULAR_T2_CH0: timer 2 CC0 event select - \arg ADC2_EXTTRIG_REGULAR_T1_CH2: timer 1 CC2 event select - \arg ADC2_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select - \arg ADC2_EXTTRIG_REGULAR_T7_CH0: timer 7 CC0 event select - \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH0: timer 4 CC0 event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH2: timer 4 CC2 event select - \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select - \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select - \arg ADC2_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select - \arg ADC2_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select - \arg ADC2_EXTTRIG_INSERTED_T3_CH2: timer 3 CC2 event select - \arg ADC2_EXTTRIG_INSERTED_T7_CH1: timer 7 CC1 event select - \arg ADC2_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select - \arg ADC2_EXTTRIG_INSERTED_T4_TRGO: timer 4 TRGO event select - \arg ADC2_EXTTRIG_INSERTED_T4_CH3: timer 4 CC3 event select - \arg ADC0_1_2_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief enable ADC software trigger - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group) -{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(uint32_t adc_periph) -{ - return (uint16_t)(ADC_RDATA(adc_periph)); -} - -/*! - \brief read ADC inserted group data register - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] inserted_channel : insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - idata = ADC_IDATA0(adc_periph); - break; - case ADC_INSERTED_CHANNEL_1: - idata = ADC_IDATA1(adc_periph); - break; - case ADC_INSERTED_CHANNEL_2: - idata = ADC_IDATA2(adc_periph); - break; - case ADC_INSERTED_CHANNEL_3: - idata = ADC_IDATA3(adc_periph); - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief read the last ADC0 and ADC1 conversion result data in sync mode - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint32_t adc_sync_mode_convert_value_read(void) -{ - /* return conversion value */ - return ADC_RDATA(ADC0); -} - -/*! - \brief get the ADC flag bits - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_flag: the adc flag bits - only one parameter can be selected - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) -{ - FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag bits - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_flag: the adc flag bits - one or more parameters can be selected - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); -} - -/*! - \brief get the ADC interrupt bits - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_interrupt: the adc interrupt bits - only oneparameter can be selected - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch(adc_interrupt){ - case ADC_INT_FLAG_WDE: - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear the ADC flag - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_interrupt: the adc status flag - one or more parameters can be selected - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief enable ADC interrupt - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_interrupt: the adc interrupt - one or more parameters can be selected - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) -{ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - } - - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - } - - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_interrupt: the adc interrupt flag - one or more parameters can be selected - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; - } - - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; - } - - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; - } -} - -/*! - \brief configure ADC analog watchdog single channel - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_channel: the selected ADC channel - only one among these parameters can be selected - \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - - ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_watchdog_disable(uint32_t adc_periph) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] low_threshold: analog watchdog low threshold,0..4095 - \param[in] high_threshold: analog watchdog high threshold,0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) -{ - ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); -} - -/*! - \brief configure ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[in] mode: ADC oversampling mode - only oneparameter can be selected - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only oneparameter can be selected - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only oneparameter can be selected - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio) -{ - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); - } - /* config the shift and ratio */ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief enable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; -} - -/*! - \brief disable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - only one among these parameters can be selected - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c deleted file mode 100644 index 62fcc1e667..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c +++ /dev/null @@ -1,302 +0,0 @@ -/*! - \file gd32f30x_bkp.c - \brief BKP driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.2, firmware for GD32F30x -*/ - -#include "gd32f30x_bkp.h" - -#define TAMPER_FLAG_SHIFT ((uint8_t)8U) - -/*! - \brief reset BKP registers - \param[in] none - \param[out] none - \retval none -*/ -void bkp_deinit(void) -{ - /* reset BKP domain register*/ - rcu_bkp_reset_enable(); - rcu_bkp_reset_disable(); -} - -/*! - \brief write BKP data register - \param[in] register_number: refer to bkp_data_register_enum, only one parameter can be selected - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[in] data: the data to be write in BKP data register - \param[out] none - \retval none -*/ -void bkp_write_data(bkp_data_register_enum register_number, uint16_t data) -{ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - BKP_DATA10_41(register_number-1U) = data; - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - BKP_DATA0_9(register_number-1U) = data; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief read BKP data register - \param[in] register_number: refer to bkp_data_register_enum, only one parameter can be selected - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[out] none - \retval data of BKP data register -*/ -uint16_t bkp_read_data(bkp_data_register_enum register_number) -{ - uint16_t data = 0U; - - /* get the data from the BKP data register */ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - data = BKP_DATA10_41(register_number-1U); - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - data = BKP_DATA0_9(register_number-1U); - }else{ - /* illegal parameters */ - } - return data; -} - -/*! - \brief enable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; -} - -/*! - \brief disable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; -} - -/*! - \brief enable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; -} - -/*! - \brief disable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; -} - -/*! - \brief select RTC output - \param[in] outputsel: RTC output selection - \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output - \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output - \param[out] none - \retval none -*/ -void bkp_rtc_output_select(uint16_t outputsel) -{ - uint16_t ctl = 0U; - - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_ROSEL; - ctl |= outputsel; - BKP_OCTL = ctl; -} - -/*! - \brief select RTC clock output - \param[in] clocksel: RTC clock output selection - \arg RTC_CLOCK_DIV_64: RTC clock div 64 - \arg RTC_CLOCK_DIV_1: RTC clock - \param[out] none - \retval none -*/ -void bkp_rtc_clock_output_select(uint16_t clocksel) -{ - uint16_t ctl = 0U; - - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_CCOSEL; - ctl |= clocksel; - BKP_OCTL = ctl; -} - -/*! - \brief RTC clock calibration direction - \param[in] direction: RTC clock calibration direction - \arg RTC_CLOCK_SLOWED_DOWN: RTC clock slow down - \arg RTC_CLOCK_SPEED_UP: RTC clock speed up - \param[out] none - \retval none -*/ -void bkp_rtc_clock_calibration_direction(uint16_t direction) -{ - uint16_t ctl = 0U; - - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_CALDIR; - ctl |= direction; - BKP_OCTL = ctl; -} - -/*! - \brief set RTC clock calibration value - \param[in] value: RTC clock calibration value - \arg 0x00 - 0x7F - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_value_set(uint8_t value) -{ - uint16_t ctl; - - ctl = BKP_OCTL; - ctl &= (uint16_t)OCTL_RCCV(0); - ctl |= (uint16_t)OCTL_RCCV(value); - BKP_OCTL = ctl; -} - -/*! - \brief enable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_enable(void) -{ - BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; -} - -/*! - \brief disable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_disable(void) -{ - BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; -} - -/*! - \brief set tamper pin active level - \param[in] level: tamper active level - \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high - \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low - \param[out] none - \retval none -*/ -void bkp_tamper_active_level_set(uint16_t level) -{ - uint16_t ctl = 0U; - - ctl = BKP_TPCTL; - ctl &= (uint16_t)~BKP_TPCTL_TPAL; - ctl |= level; - BKP_TPCTL = ctl; -} - -/*! - \brief enable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_interrupt_enable(void) -{ - BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; -} - -/*! - \brief disable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_interrupt_disable(void) -{ - BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; -} - -/*! - \brief get bkp flag state - \param[in] flag - \arg BKP_FLAG_TAMPER: tamper event flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_flag_get(uint16_t flag) -{ - if(RESET != (BKP_TPCS & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear bkp flag state - \param[in] flag - \arg BKP_FLAG_TAMPER: tamper event flag - \param[out] none - \retval none -*/ -void bkp_flag_clear(uint16_t flag) -{ - BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); -} - -/*! - \brief get bkp interrupt flag state - \param[in] flag - \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_interrupt_flag_get(uint16_t flag) -{ - if(RESET != (BKP_TPCS & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear bkp interrupt flag state - \param[in] flag - \arg BKP_INT_FLAG_TAMPER: tamper interrupt flag - \param[out] none - \retval none -*/ -void bkp_interrupt_flag_clear(uint16_t flag) -{ - BKP_TPCS |= (uint16_t)(flag >> TAMPER_FLAG_SHIFT); -} - diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_can.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_can.c deleted file mode 100644 index b64ae36141..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_can.c +++ /dev/null @@ -1,846 +0,0 @@ -/*! - \file gd32f30x_can.c - \brief CAN driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_can.h" - -/*! - \brief deinitialize CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval none -*/ -void can_deinit(uint32_t can_periph) -{ -#ifdef GD32F30X_CL - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - }else{ - rcu_periph_reset_enable(RCU_CAN1RST); - rcu_periph_reset_disable(RCU_CAN1RST); - } -#else - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - } -#endif -} - -/*! - \brief initialize CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] can_parameter_init: parameters for CAN initializtion - \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) - \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) - \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) - \arg time_triggered: ENABLE or DISABLE - \arg auto_bus_off_recovery: ENABLE or DISABLE - \arg auto_wake_up: ENABLE or DISABLE - \arg auto_retrans: ENABLE or DISABLE - \arg rec_fifo_overwrite: ENABLE or DISABLE - \arg trans_fifo_order: ENABLE or DISABLE - \arg prescaler: 0x0001 - 0x03FF - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) -{ - uint32_t timeout = CAN_TIMEOUT; - ErrStatus flag = ERROR; - - /* disable sleep mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - /* enable initialize mode */ - CAN_CTL(can_periph) |= CAN_CTL_IWMOD; - /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ - timeout--; - } - /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - /* set the bit timing register */ - CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ - BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ - BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ - BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ - BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); - /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ - CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; - } - /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ - CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_AWU; - } - /* automatic retransmission mode */ - if(ENABLE == can_parameter_init->auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ARD; - } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } - /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ - CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } - /* disable initialize mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; - timeout = CAN_TIMEOUT; - /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (timeout)){ - timeout--; - } - /* check exit initialize mode */ - if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = SUCCESS; - } - } - return flag; -} - -/*! - \brief initialize CAN filter - \param[in] can_filter_parameter_init: struct for CAN filter initialization - \arg filter_list_high: 0x0000 - 0xFFFF - \arg filter_list_low: 0x0000 - 0xFFFF - \arg filter_mask_high: 0x0000 - 0xFFFF - \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - \arg filter_number: 0 - 27 - \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - \arg filter_enable: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) -{ - uint32_t val = 0U; - - val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* disable filter */ - CAN_FW(CAN0) &= ~(uint32_t)val; - - /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ - /* set filter 16 bits */ - CAN_FSCFG(CAN0) &= ~(uint32_t)val; - /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); - } - /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ - /* set filter 32 bits */ - CAN_FSCFG(CAN0) |= (uint32_t)val; - /* 32 bits list or first 32 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* 32 bits mask or second 32 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); - } - - /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ - /* mask mode */ - CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ - /* list mode */ - CAN_FMCFG(CAN0) |= (uint32_t)val; - } - - /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ - /* FIFO0 */ - CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - }else{ - /* FIFO1 */ - CAN_FAFIFO(CAN0) |= (uint32_t)val; - } - - /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ - - CAN_FW(CAN0) |= (uint32_t)val; - } - - /* filter lock enable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief set CAN1 fliter start bank number - \param[in] start_bank: CAN1 start bank number - \arg (1..27) - \param[out] none - \retval none -*/ -void can1_filter_start_bank(uint8_t start_bank) -{ - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* set CAN1 filter start number */ - CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; - CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief enable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval none -*/ -void can_debug_freeze_enable(uint32_t can_periph) -{ - CAN_CTL(can_periph) |= CAN_CTL_DFZ; -#ifdef GD32F30X_CL - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - }else{ - dbg_periph_enable(DBG_CAN1_HOLD); - } -#else - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - } -#endif -} - -/*! - \brief disable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval none -*/ -void can_debug_freeze_disable(uint32_t can_periph) -{ - CAN_CTL(can_periph) |= CAN_CTL_DFZ; -#ifdef GD32F30X_CL - if(CAN0 == can_periph){ - dbg_periph_disable(DBG_CAN0_HOLD); - }else{ - dbg_periph_disable(DBG_CAN1_HOLD); - } -#else - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - } -#endif -} - -/*! - \brief enable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval none -*/ -void can_time_trigger_mode_enable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* enable the tcc mode */ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - /* enable time stamp */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; - } -} - -/*! - \brief disable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval none -*/ -void can_time_trigger_mode_disable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* disable the TCC mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - /* reset TSEN bits */ - for(mailbox_number=0U; mailbox_number<3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; - } -} - -/*! - \brief transmit CAN message - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] transmit_message: struct for CAN transmit message - \arg tx_sfid: 0x00000000 - 0x000007FF - \arg tx_efid: 0x00000000 - 0x1FFFFFFF - \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg tx_dlenc: 1 - 7 - \arg tx_data[]: 0x00 - 0xFF - \param[out] none - \retval mailbox_number -*/ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) -{ - uint8_t mailbox_number = CAN_MAILBOX0; - - /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ - mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ - mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ - mailbox_number = CAN_MAILBOX2; - }else{ - mailbox_number = CAN_NOMAILBOX; - } - if(CAN_NOMAILBOX == mailbox_number){ - return CAN_NOMAILBOX; - } - - CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ - /* set transmit mailbox standard identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ - /* set transmit mailbox extended identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); - } - /* set the data length */ - CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC); - CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; - /* set the data */ - CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); - CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); - /* enable transmission */ - CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; - - return mailbox_number; -} - -/*! - \brief get CAN transmit state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] mailbox_number - \arg CAN_MAILBOX(x=0,1,2) - \param[out] none - \retval can_transmit_state_enum -*/ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) -{ - can_transmit_state_enum state = CAN_TRANSMIT_FAILED; - uint32_t val = 0U; - - switch(mailbox_number){ - case CAN_MAILBOX0: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); - break; - case CAN_MAILBOX1: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); - break; - case CAN_MAILBOX2: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); - break; - default: - val = CAN_TRANSMIT_FAILED; - break; - } - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): - state = CAN_TRANSMIT_PENDING; - break; - /* transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_OK; - break; - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_OK; - break; - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_OK; - break; - default: - state = CAN_TRANSMIT_FAILED; - break; - } - return state; -} - -/*! - \brief stop CAN transmission - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOXx(x=0,1,2) - \param[out] none - \retval none -*/ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) -{ - if(CAN_MAILBOX0 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - }else if(CAN_MAILBOX1 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - }else if(CAN_MAILBOX2 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief CAN receive message - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] receive_message: struct for CAN receive message - \arg rx_sfid: 0x00000000 - 0x000007FF - \arg rx_efid: 0x00000000 - 0x1FFFFFFF - \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg rx_dlenc: 1 - 7 - \arg rx_data[]: 0x00 - 0xFF - \arg rx_fi: 0 - 27 - \retval none -*/ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) -{ - /* get the frame format */ - receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ - /* get standard identifier */ - receive_message -> rx_sfid = (uint32_t)(RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ - /* get extended identifier */ - receive_message -> rx_efid = (uint32_t)(RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); - } - - /* get frame type */ - receive_message -> rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* get recevie data length */ - receive_message -> rx_dlen = (uint8_t)(RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - /* filtering index */ - receive_message -> rx_fi = (uint8_t)(RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - - /* receive data */ - receive_message -> rx_data[0] = (uint8_t)(RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[1] = (uint8_t)(RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[2] = (uint8_t)(RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[3] = (uint8_t)(RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[4] = (uint8_t)(RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[5] = (uint8_t)(RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[6] = (uint8_t)(RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[7] = (uint8_t)(RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - - /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - } -} - -/*! - \brief release FIFO0 - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval none -*/ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) -{ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief CAN receive message length - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval message length -*/ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) -{ - uint8_t val = 0U; - - if(CAN_FIFO0 == fifo_number){ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ - /* illegal parameters */ - } - return val; -} - -/*! - \brief set CAN working mode - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] can_working_mode - \arg CAN_MODE_INITIALIZE - \arg CAN_MODE_NORMAL - \arg CAN_MODE_SLEEP - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) -{ - ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if(CAN_MODE_INITIALIZE == working_mode){ - /* disable sleep mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); - /* set initialize mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_NORMAL == working_mode){ - /* enter normal mode */ - CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ - timeout--; - } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_SLEEP == working_mode){ - /* disable initialize mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); - /* set sleep mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; - /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else{ - flag = ERROR; - } - return flag; -} - -/*! - \brief wake up CAN - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_wakeup(uint32_t can_periph) -{ - ErrStatus flag = ERROR; - uint32_t timeout = CAN_TIMEOUT; - - /* wakeup */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ - timeout--; - } - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - return flag; -} - -/*! - \brief get CAN error type - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval can_error_enum -*/ -can_error_enum can_error_get(uint32_t can_periph) -{ - can_error_enum error; - error = CAN_ERROR_NONE; - - /* get error type */ - error = (can_error_enum)((CAN_ERR(can_periph) & CAN_ERR_ERRN) >> 4U); - return error; -} - -/*! - \brief get CAN receive error number - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval error number -*/ -uint8_t can_receive_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_RECNT) >> 24U); - return val; -} - -/*! - \brief get CAN transmit error number - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[out] none - \retval error number -*/ -uint8_t can_transmit_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - val = (uint8_t)((CAN_ERR(can_periph) & CAN_ERR_TECNT) >> 16U); - return val; -} - -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] interrupt - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] interrupt - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - -/*! - \brief get CAN flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \param[out] none - \retval none -*/ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag) -{ - CAN_REG_VAL(can_periph, flag) |= BIT(CAN_BIT_POS(flag)); -} - -/*! - \brief get CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag))); - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval none -*/ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - CAN_REG_VALS(can_periph, flag) |= BIT(CAN_BIT_POS0(flag)); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c deleted file mode 100644 index a816ba5a3a..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c +++ /dev/null @@ -1,101 +0,0 @@ -/*! - \file gd32f30x_crc.c - \brief CRC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "gd32f30x_crc.h" - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_DATA = (uint32_t)0xFFFFFFFFU; - CRC_FDATA = (uint32_t)0x00000000U; - CRC_CTL = (uint32_t)CRC_CTL_RST; -} - -/*! - \brief reset data register to the value of initializaiton data register - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write the free data register - \param[in] free_data: specify 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief CRC calculate a 32-bit data - \param[in] sdata: specify 32-bit data - \param[out] none - \retval 32-bit CRC calculate value -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return (CRC_DATA); -} - -/*! - \brief CRC calculate a 32-bit data array - \param[in] array: pointer to an array of 32 bit data words - \param[in] size: size of the array - \param[out] none - \retval 32-bit CRC calculate value -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for(index = 0U; index < size; index++){ - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c deleted file mode 100644 index d9859ce8d5..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c +++ /dev/null @@ -1,344 +0,0 @@ -/*! - \file gd32f30x_ctc.c - \brief CTC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_ctc.h" - -#define CTC_FLAG_MASK ((uint32_t)0x00000700U) - -/*! - \brief reset CTC clock trim controller - \param[in] none - \param[out] none - \retval none -*/ -void ctc_deinit(void) -{ - /* reset CTC */ - rcu_periph_reset_enable(RCU_CTCRST); - rcu_periph_reset_disable(RCU_CTCRST); -} - -/*! - \brief configure the IRC48M trim value - \param[in] ctc_trim_value: 8-bit IRC48M trim value - \param[out] none - \retval none -*/ -void ctc_irc48m_trim_value_config(uint8_t ctc_trim_value) -{ - /* clear TRIMVALUE bits */ - CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); - /* set TRIMVALUE bits */ - CTC_CTL0 |= ((uint32_t)ctc_trim_value << 8); -} - -/*! - \brief generate software reference source sync pulse - \param[in] none - \param[out] none - \retval none -*/ -void ctc_software_refsource_pulse_generate(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; -} - -/*! - \brief configure hardware automatically trim mode - \param[in] ctc_hardmode: - \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable - \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable - \param[out] none - \retval none -*/ -void ctc_hardware_trim_mode_config(uint32_t ctc_hardmode) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); - CTC_CTL0 |= (uint32_t)ctc_hardmode; -} - -/*! - \brief enable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_enable(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; -} - -/*! - \brief disable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_disable(void) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); -} - -/*! - \brief configure reference signal source polarity - \param[in] ctc_polarity: - \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge - \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge - \param[out] none - \retval none -*/ -void ctc_refsource_polarity_config(uint32_t ctc_polarity) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); - CTC_CTL1 |= (uint32_t)ctc_polarity; -} - -/*! - \brief select reference signal source - \param[in] ctc_refs: - \arg CTC_REFSOURCE_GPIO: GPIO is selected - \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected - \arg CTC_REFSOURCE_USBSOF: USBSOF is selected - \param[out] none - \retval none -*/ -void ctc_refsource_signal_select(uint32_t ctc_refs) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); - CTC_CTL1 |= (uint32_t)ctc_refs; -} - -/*! - \brief configure reference signal source prescaler - \param[in] ctc_prescaler: - \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided - \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 - \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 - \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 - \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 - \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 - \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 - \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 - \param[out] none - \retval none -*/ -void ctc_refsource_prescaler_config(uint32_t ctc_prescaler) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); - CTC_CTL1 |= (uint32_t)ctc_prescaler; -} - -/*! - \brief configure clock trim base limit value - \param[in] ctc_limit_value: 8-bit clock trim base limit value - \param[out] none - \retval none -*/ -void ctc_clock_limit_value_config(uint8_t ctc_limit_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); - CTC_CTL1 |= (uint32_t)((uint32_t)ctc_limit_value << 16); -} - -/*! - \brief configure CTC counter reload value - \param[in] ctc_reload_value: 16-bit CTC counter reload value - \param[out] none - \retval none -*/ -void ctc_counter_reload_value_config(uint16_t ctc_reload_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); - CTC_CTL1 |= (uint32_t)ctc_reload_value; -} - -/*! - \brief read CTC counter capture value when reference sync pulse occurred - \param[in] none - \param[out] none - \retval the 16-bit CTC counter capture value -*/ -uint16_t ctc_counter_capture_value_read(void) -{ - uint16_t capture_value = 0U; - capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> 16); - return (capture_value); -} - -/*! - \brief read CTC trim counter direction when reference sync pulse occurred - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - \arg SET: CTC trim counter direction is down-counting - \arg RESET: CTC trim counter direction is up-counting -*/ -FlagStatus ctc_counter_direction_read(void) -{ - if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief read CTC counter reload value - \param[in] none - \param[out] none - \retval the 16-bit CTC counter reload value -*/ -uint16_t ctc_counter_reload_value_read(void) -{ - uint16_t reload_value = 0U; - reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); - return (reload_value); -} - -/*! - \brief read the IRC48M trim value - \param[in] none - \param[out] none - \retval the 8-bit IRC48M trim value -*/ -uint8_t ctc_irc48m_trim_value_read(void) -{ - uint8_t trim_value = 0U; - trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> 8); - return (trim_value); -} - -/*! - \brief enable the CTC interrupt - \param[in] ctc_interrupt: CTC interrupt enable - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_enable(uint32_t ctc_interrupt) -{ - CTC_CTL0 |= (uint32_t)ctc_interrupt; -} - -/*! - \brief disable the CTC interrupt - \param[in] ctc_interrupt: CTC interrupt enable source - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_disable(uint32_t ctc_interrupt) -{ - CTC_CTL0 &= (uint32_t)(~ctc_interrupt); -} - -/*! - \brief get CTC interrupt flag - \param[in] ctc_interrupt: the CTC interrupt flag - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_interrupt_flag_get(uint32_t ctc_interrupt) -{ - uint32_t interrupt = 0U, intenable = 0U; - - if(ctc_interrupt & CTC_FLAG_MASK){ - intenable = CTC_CTL0 & CTC_CTL0_ERRIE; - }else{ - intenable = CTC_CTL0 & ctc_interrupt; - } - interrupt = CTC_STAT & ctc_interrupt; - - if(interrupt && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CTC interrupt flag - \param[in] ctc_interrupt: the CTC interrupt flag - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval none -*/ -void ctc_interrupt_flag_clear(uint32_t ctc_interrupt) -{ - if(ctc_interrupt & CTC_FLAG_MASK){ - CTC_INTC |= CTC_INTC_ERRIC; - }else{ - CTC_INTC |= ctc_interrupt; - } -} - -/*! - \brief get CTC flag - \param[in] ctc_flag: the CTC flag - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_flag_get(uint32_t ctc_flag) -{ - if(RESET != (CTC_STAT & ctc_flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CTC flag - \param[in] ctc_flag: the CTC flag - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval none -*/ -void ctc_flag_clear(uint32_t ctc_flag) -{ - if(ctc_flag & CTC_FLAG_MASK){ - CTC_INTC |= CTC_INTC_ERRIC; - }else{ - CTC_INTC |= ctc_flag; - } -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c deleted file mode 100644 index 50eed8db0e..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c +++ /dev/null @@ -1,508 +0,0 @@ -/*! - \file gd32f30x_dac.c - \brief DAC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "gd32f30x_dac.h" - -/*! - \brief deinitialize DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_deinit(void) -{ - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); -} - -/*! - \brief enable DAC - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DEN0; - }else{ - DAC_CTL |= DAC_CTL_DEN1; - } -} - -/*! - \brief disable DAC - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DEN1; - } -} - -/*! - \brief enable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ - DAC_CTL |= DAC_CTL_DDMAEN1; - } -} - -/*! - \brief disable DAC DMA function - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval none -*/ -void dac_dma_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DDMAEN1; - } -} - -/*! - \brief enable DAC output buffer - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ - DAC_CTL &= ~DAC_CTL_DBOFF1; - } -} - -/*! - \brief disable DAC output buffer - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DBOFF0; - }else{ - DAC_CTL |= DAC_CTL_DBOFF1; - } -} - -/*! - \brief enable DAC trigger - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DTEN0; - }else{ - DAC_CTL |= DAC_CTL_DTEN1; - } -} - -/*! - \brief disable DAC trigger - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DTEN1; - } -} - -/*! - \brief enable DAC software trigger - \param[in] dac_periph - \arg DACx(x =0,1) - \retval none -*/ -void dac_software_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; - }else{ - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph - \arg DACx(x =0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; - } -} - -/*! - \brief set DAC trigger source - \param[in] dac_periph - \arg DACx(x =0,1) - \param[in] triggersource: external triggers of DAC - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F30X_CL) - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO - \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO - \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F30X_HD and GD32F30X_XD) - \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger - \param[out] none - \retval none -*/ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; - }else{ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << 16); - } -} - -/*! - \brief configure DAC wave mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] wave_mode - \arg DAC_WAVE_DISABLE: wave disable - \arg DAC_WAVE_MODE_LFSR: LFSR noise mode - \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode - \param[out] none - \retval none -*/ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DWM0; - DAC_CTL |= wave_mode; - }else{ - DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= wave_mode << 16; - } -} - -/*! - \brief configure DAC wave bit width - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] bit_width - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= bit_width; - }else{ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= bit_width << 16; - } -} - -/*! - \brief configure DAC LFSR noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] unmask_bits - \arg DAC_LFSR_BIT0: unmask the LFSR bit0 - \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] - \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] - \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] - \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] - \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] - \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] - \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] - \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] - \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] - \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] - \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] - \param[out] none - \retval none -*/ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= unmask_bits; - }else{ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= unmask_bits << 16; - } -} - -/*! - \brief configure DAC triangle noise mode - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] amplitude - \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 - \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 - \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 - \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 - \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 - \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 - \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 - \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 - \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 - \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 - \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 - \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 - \param[out] none - \retval none -*/ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= amplitude; - }else{ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= amplitude << 16; - } -} - -/*! - \brief get DAC output value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if(DAC0 == dac_periph){ - data = (uint16_t)DAC0_DO; - }else{ - data = (uint16_t)DAC1_DO; - } - return data; -} - -/*! - \brief enable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL |= (ctl); -} - -/*! - \brief disable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL &= (~ctl); -} - -/*! - \brief enable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_enable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); -} - -/*! - \brief disable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_disable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT &= (~swt); -} - -/*! - \brief enable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL &= (~ctl); -} - -/*! - \brief disable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL |= (ctl); -} - -/*! - \brief set the DAC specified data holding register value - \param[in] dac_periph - \arg DACx(x=0,1) - \param[in] dac_align - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data: data to be loaded - \param[out] none - \retval none -*/ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) -{ - if(DAC0 == dac_periph){ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } - }else{ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } - } -} - -/*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded - \param[out] none - \retval none -*/ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) -{ - uint32_t data = 0U; - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << 16) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << 16) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << 8) | data0; - DACC_R8DH = data; - break; - default: - break; - } -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c deleted file mode 100644 index d7e9402cb6..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c +++ /dev/null @@ -1,125 +0,0 @@ -/*! - \file gd32f30x_dbg.c - \brief DBG driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "gd32f30x_dbg.h" - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL0 |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL0 &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - only one parameter can be selected which is shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_CTL0 |= (uint32_t)dbg_periph; -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - only one parameter can be selected which is shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_CTL0 &= ~(uint32_t)dbg_periph; -} - -/*! - \brief enable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_enable(void) -{ - DBG_CTL0 |= DBG_CTL0_TRACE_IOEN; -} - -/*! - \brief disable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_disable(void) -{ - DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; -} - -/*! - \brief trace pin mode selection - \param[in] trace_mode: - \arg TRACE_MODE_ASYNC: trace pin used for async mode - \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 - \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 - \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 - \param[out] none - \retval none -*/ -void dbg_trace_pin_mode_set(uint32_t trace_mode) -{ - DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE; - DBG_CTL0 |= trace_mode; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c deleted file mode 100644 index 8679b51bf8..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c +++ /dev/null @@ -1,651 +0,0 @@ -/*! - \file gd32f30x_dma.c - \brief DMA driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_dma.h" - -#define DMA_WRONG_HANDLE while(1){} - -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); - -/*! - \brief deinitialize DMA a channel registers - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is deinitialized - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* disable DMA a channel */ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is initialized - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct init_struct) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* configure peripheral base address */ - DMA_CHPADDR(dma_periph, channelx) = init_struct.periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(dma_periph, channelx) = init_struct.memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph, channelx) = (init_struct.number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width, */ - ctl = DMA_CHCTL(dma_periph, channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct.periph_width | init_struct.memory_width | init_struct.priority); - DMA_CHCTL(dma_periph, channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct.periph_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct.memory_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct.direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - }else{ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set peripheral base address - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHPADDR(dma_periph, channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set memory base address - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHMADDR(dma_periph, channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] number: the number of remaining data to be transferred by the DMA - \param[out] none - \retval none -*/ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - return (uint32_t)DMA_CHCNT(dma_periph, channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] priority: priority Level of this channel - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] mwidth: transfer data width of memory - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] pwidth: transfer data width of peripheral - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] direction: specify the direction of data transfer - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - if(DMA_PERIPHERAL_TO_MEMORY == direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ - reval = SET; - }else{ - reval = RESET; - } - - return reval; -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch(flag){ - case DMA_INT_FLAG_FTF: - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; - break; - default: - DMA_WRONG_HANDLE - } - - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~source; -} - -/*! - \brief check whether peripheral and channels match - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) -{ - ErrStatus val = SUCCESS; - - if(DMA1 == dma_periph){ - if(channelx > DMA_CH4){ - val = ERROR; - } - } - - return val; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c deleted file mode 100644 index 5fb06b6d4c..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c +++ /dev/null @@ -1,3615 +0,0 @@ -/*! - \file gd32f30x_enet.c - \brief ENET driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_enet.h" - -#ifdef GD32F30X_CL - -#if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#elif defined ( __ICCARM__ ) /*!< IAR compiler */ -#pragma data_alignment=4 -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -#pragma data_alignment=4 -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -#pragma data_alignment=4 -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -#pragma data_alignment=4 -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#endif /* __CC_ARM */ - -/* global transmit and receive descriptors pointers */ -enet_descriptors_struct *dma_current_txdesc; -enet_descriptors_struct *dma_current_rxdesc; - -/* structure pointer of ptp descriptor for normal mode */ -enet_descriptors_struct *dma_current_ptp_txdesc = NULL; -enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; - -/* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; - -/* array of register offset for debug information get */ -static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, - -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, -0x104C, 0x1050, 0x1054}; - - -/*! - \brief deinitialize the ENET, and reset structure parameters for ENET initialization - \param[in] none - \param[out] none - \retval none -*/ -void enet_deinit(void) -{ - rcu_periph_reset_enable(RCU_ENETRST); - rcu_periph_reset_disable(RCU_ENETRST); - enet_initpara_reset(); -} - -/*! - \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise - configuration will be no effect - \param[in] option: different function option, which is related to several parameters, - only one parameter can be selected which is shown as below, refer to enet_option_enum - \arg FORWARD_OPTION: choose to configure the frame forward related parameters - \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters - \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters - \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters - \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters - \arg VLAN_OPTION: choose to configure vlan related parameters - \arg FLOWCTL_OPTION: choose to configure flow control related parameters - \arg HASHH_OPTION: choose to configure hash high - \arg HASHL_OPTION: choose to configure hash low - \arg FILTER_OPTION: choose to configure frame filter related parameters - \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters - \arg TIMER_OPTION: choose to configure time counter related parameters - \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option - all the related parameters should be configured which are shown as below - FORWARD_OPTION related parameters: - - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; - - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; - - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; - - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . - DMABUS_OPTION related parameters: - - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; - - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; - - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; - DMA_MAXBURST_OPTION related parameters: - - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ - ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ - ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ - ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ - ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; - - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ - ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ - ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ - ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ - ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; - - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; - DMA_ARBITRATION_OPTION related parameters: - - ENET_ARBITRATION_RXPRIORTX - - ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ - ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. - STORE_OPTION related parameters: - - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; - - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; - - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ - ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; - - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ - ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ - ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ - ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . - DMA_OPTION related parameters: - - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; - - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE ; - - ENET_ENHANCED_DESCRIPTOR/ ENET_NORMAL_DESCRIPTOR . - VLAN_OPTION related parameters: - - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; - - MAC_VLT_VLTI(regval) . - FLOWCTL_OPTION related parameters: - - MAC_FCTL_PTM(regval) ; - - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ - ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; - - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . - HASHH_OPTION related parameters: - - 0x0~0xFFFF FFFFU - HASHL_OPTION related parameters: - - 0x0~0xFFFF FFFFU - FILTER_OPTION related parameters: - - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ - ENET_SRC_FILTER_DISABLE ; - - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; - - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ - ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; - - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ - ENET_UNICAST_FILTER_PERFECT ; - - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ - ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . - HALFDUPLEX_OPTION related parameters: - - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; - - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; - - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; - - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ - ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; - - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . - TIMER_OPTION related parameters: - - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; - - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; - INTERFRAMEGAP_OPTION related parameters: - - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ - ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ - ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ - ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . - \param[out] none - \retval none -*/ -void enet_initpara_config(enet_option_enum option, uint32_t para) -{ - switch(option){ - case FORWARD_OPTION: - /* choose to configure forward_frame, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; - enet_initpara.forward_frame = para; - break; - case DMABUS_OPTION: - /* choose to configure dmabus_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; - enet_initpara.dmabus_mode = para; - break; - case DMA_MAXBURST_OPTION: - /* choose to configure dma_maxburst, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; - enet_initpara.dma_maxburst = para; - break; - case DMA_ARBITRATION_OPTION: - /* choose to configure dma_arbitration, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; - enet_initpara.dma_arbitration = para; - break; - case STORE_OPTION: - /* choose to configure store_forward_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)STORE_OPTION; - enet_initpara.store_forward_mode = para; - break; - case DMA_OPTION: - /* choose to configure dma_function, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - -#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE - para &= ~ENET_ENHANCED_DESCRIPTOR; -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - - enet_initpara.dma_function = para; - break; - case VLAN_OPTION: - /* choose to configure vlan_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; - enet_initpara.vlan_config = para; - break; - case FLOWCTL_OPTION: - /* choose to configure flow_control, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; - enet_initpara.flow_control = para; - break; - case HASHH_OPTION: - /* choose to configure hashtable_high, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; - enet_initpara.hashtable_high = para; - break; - case HASHL_OPTION: - /* choose to configure hashtable_low, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; - enet_initpara.hashtable_low = para; - break; - case FILTER_OPTION: - /* choose to configure framesfilter_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; - enet_initpara.framesfilter_mode = para; - break; - case HALFDUPLEX_OPTION: - /* choose to configure halfduplex_param, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; - enet_initpara.halfduplex_param = para; - break; - case TIMER_OPTION: - /* choose to configure timer_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; - break; - case INTERFRAMEGAP_OPTION: - /* choose to configure interframegap, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; - enet_initpara.interframegap = para; - break; - default: - break; - } -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared - parameters - \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum - \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation - \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex - \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex - \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex - \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex - \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII - \param[in] checksum: IP frame checksum offload function, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum - \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function - \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function - \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped - \param[in] recept: frame filter function, only one parameter can be selected - which is shown as below, refer to enet_frmrecept_enum - \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled - \arg ENET_RECEIVEALL: all received frame are forwarded to application - \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames - \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) -{ - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; - uint32_t media_temp = 0U; - uint32_t timeout = 0U; - uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; - - /* PHY interface configuration, configure SMI clock and reset PHY chip */ - if(ERROR == enet_phy_config()){ - _ENET_DELAY_(PHY_RESETDELAY); - if(ERROR == enet_phy_config()){ - return enet_state; - } - } - /* initialize ENET peripheral with generally concerned parameters */ - enet_default_init(); - - /* 1st, configure mediamode */ - media_temp = (uint32_t)mediamode; - /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ - /* wait for PHY_LINKED_STATUS bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; - timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* enable auto-negotiation */ - phy_value = PHY_AUTONEGOTIATION; - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - - /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_AUTONEGO_COMPLETE; - timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); - /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ - media_temp = ENET_MODE_FULLDUPLEX; - }else{ - media_temp = ENET_MODE_HALFDUPLEX; - } - /* configure the communication speed of MAC following the auto-negotiation result */ - if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ - media_temp |= ENET_SPEEDMODE_10M; - }else{ - media_temp |= ENET_SPEEDMODE_100M; - } - }else{ - phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); - phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - /* PHY configuration need some time */ - _ENET_DELAY_(PHY_CONFIGDELAY); - } - /* after configuring the PHY, use mediamode to configure registers */ - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); - reg_value |= media_temp; - ENET_MAC_CFG = reg_value; - - - /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ - ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~ENET_DMA_CTL_DTCERFD; - reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); - ENET_DMA_CTL = reg_value; - } - - /* 3rd, configure recept */ - ENET_MAC_FRMF |= (uint32_t)recept; - - /* 4th, configure different function options */ - /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ - reg_temp = enet_initpara.forward_frame; - - reg_value = ENET_MAC_CFG; - temp = reg_temp; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_TFCD |ENET_MAC_CFG_APCD)); - temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); - reg_value |= temp; - ENET_MAC_CFG = reg_value; - - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); - temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); - reg_value |= (temp >> 2); - ENET_DMA_CTL = reg_value; - } - - /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ - temp = enet_initpara.dmabus_mode; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ - temp = enet_initpara.dma_maxburst; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ - temp = enet_initpara.dma_arbitration; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ - temp = enet_initpara.store_forward_mode; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - } - - /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ - reg_temp = enet_initpara.dma_function; - - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); - temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - - reg_value = ENET_DMA_BCTL; - temp = reg_temp; - /* configure ENET_DMA_BCTL register */ - reg_value &= (~ENET_DMA_BCTL_DFM); - temp &= ENET_DMA_BCTL_DFM; - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ - reg_temp = enet_initpara.vlan_config; - - reg_value = ENET_MAC_VLT; - /* configure ENET_MAC_VLT register */ - reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); - reg_value |= reg_temp; - ENET_MAC_VLT = reg_value; - } - - /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ - reg_temp = enet_initpara.flow_control; - - reg_value = ENET_MAC_FCTL; - temp = reg_temp; - /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - reg_value |= temp; - ENET_MAC_FCTL = reg_value; - - reg_value = ENET_MAC_FCTH; - temp = reg_temp; - /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); - reg_value |= (temp >> 8); - ENET_MAC_FCTH = reg_value; - } - - /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ - ENET_MAC_HLH = enet_initpara.hashtable_high; - } - - /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ - ENET_MAC_HLL = enet_initpara.hashtable_low; - } - - /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ - reg_temp = enet_initpara.framesfilter_mode; - - reg_value = ENET_MAC_FRMF; - /* configure ENET_MAC_FRMF register */ - reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); - reg_value |= reg_temp; - ENET_MAC_FRMF = reg_value; - } - - /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ - reg_temp = enet_initpara.halfduplex_param; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ - reg_temp = enet_initpara.timer_config; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ - reg_temp = enet_initpara.interframegap; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~ENET_MAC_CFG_IGBS; - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - enet_state = SUCCESS; - return enet_state; -} - -/*! - \brief reset all core internal registers located in CLK_TX and CLK_RX - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_software_reset(void) -{ - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - uint32_t dma_flag; - - /* reset all core internal registers located in CLK_TX and CLK_RX */ - ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - - /* wait for reset operation complete */ - do{ - dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); - timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - - /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief check receive frame valid and return frame size - \param[in] none - \param[out] none - \retval size of received frame: 0x0 - 0x3FFF -*/ -uint32_t enet_rxframe_size_get(void) -{ - uint32_t size = 0U; - uint32_t status; - - /* get rdes0 information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - - /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ - return 0U; - } - - /* if has any error, or the frame uses two or more descriptors */ - if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 0U; - } -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE - /* if is an ethernet-type frame, and IP frame payload error occurred */ - if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && - ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 0U; - } -#else - /* if is an ethernet-type frame, and IP frame payload error occurred */ - if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 0U; - } -#endif - /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ - if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ - /* get the size of the received data including CRC */ - size = GET_RDES0_FRML(status); - /* substract the CRC size */ - size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - } - - /* return packet size */ - return size; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_chain_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode */ - desc_status = ENET_TDES0_TCHM; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; - } - } -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_ring_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc; - enet_descriptors_struct *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* set buffer1 size */ - desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - } -} - -/*! - \brief handle current received frame data to application buffer - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] buffer: pointer to the received frame data - note -- if the input is NULL, user should copy data in application by himself - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status); - size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); - } - - }else{ - /* return ERROR */ - return ERROR; - } - } - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief handle application buffer data to transmit it - \param[in] buffer: pointer to the frame data to be transmitted, - note -- if the input is NULL, user should handle the data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) -{ - uint32_t offset = 0U; - uint32_t dma_tbu_flag, dma_tu_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief configure the transmit IP frame checksum offload calculation and insertion - \param[in] desc: the descriptor pointer which users want to configure - \param[in] checksum: IP frame checksum configuration - only one parameter can be selected which is shown as below - \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled - \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled - \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header - \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated - \param[out] none - \retval none -*/ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) -{ - desc->status &= ~ENET_TDES0_CM; - desc->status |= checksum; -} - -/*! - \brief ENET Tx and Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_enable(void) -{ - enet_tx_enable(); - enet_rx_enable(); -} - -/*! - \brief ENET Tx and Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_disable(void) -{ - enet_tx_disable(); - enet_rx_disable(); -} - -/*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: set MAC address 0 filter - \arg ENET_MAC_ADDRESS1: set MAC address 1 filter - \arg ENET_MAC_ADDRESS2: set MAC address 2 filter - \arg ENET_MAC_ADDRESS3: set MAC address 3 filter - \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \param[out] none - \retval none -*/ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); - REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); -} - -/*! - \brief get MAC address - \param[in] mac_addr: select which MAC address will be get, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: get MAC address 0 filter - \arg ENET_MAC_ADDRESS1: get MAC address 1 filter - \arg ENET_MAC_ADDRESS2: get MAC address 2 filter - \arg ENET_MAC_ADDRESS3: get MAC address 3 filter - \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \retval none -*/ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); - paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); - paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); - paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); - paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); - paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); -} - -/*! - \brief get the ENET MAC/MSC/PTP/DMA status flag - \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, - only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag - \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag - \arg ENET_MAC_FLAG_WUM: WUM status flag - \arg ENET_MAC_FLAG_MSC: MSC status flag - \arg ENET_MAC_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag - \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag - \arg ENET_PTP_FLAG_TTM: target time match flag - \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_FLAG_TS: transmit status flag - \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_FLAG_RO: receive overflow status flag - \arg ENET_DMA_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_FLAG_RS: receive status flag - \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_FLAG_ET: early transmit status flag - \arg ENET_DMA_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_FLAG_ER: early receive status flag - \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag - \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag - \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag - \arg ENET_DMA_FLAG_MSC: MSC status flag - \arg ENET_DMA_FLAG_WUM: WUM status flag - \arg ENET_DMA_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_flag_get(enet_flag_enum enet_flag) -{ - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the ENET DMA status flag - \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear - \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear - \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear - \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear - \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear - \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear - \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear - \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear - \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear - \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear - \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear - \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear - \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear - \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear - \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear - \param[out] none - \retval none -*/ -void enet_flag_clear(enet_flag_clear_enum enet_flag) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); -} - -/*! - \brief enable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_enable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief disable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_disable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief get ENET MAC/MSC/DMA interrupt flag - \param[in] int_flag: ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_FLAG_WUM: WUM status flag - \arg ENET_MAC_INT_FLAG_MSC: MSC status flag - \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag - \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_INT_FLAG_TS: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS: receive status flag - \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER: early receive status flag - \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_INT_FLAG_MSC: MSC status flag - \arg ENET_DMA_INT_FLAG_WUM: WUM status flag - \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) -{ - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear ENET DMA interrupt flag - \param[in] int_flag_clear: clear ENET interrupt flag, - only one parameter can be selected which is shown as below - \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag - \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag - \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag - \param[out] none - \retval none -*/ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); -} - -/*! - \brief ENET Tx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_TEN; - enet_txfifo_flush(); - ENET_DMA_CTL |= ENET_DMA_CTL_STE; -} - -/*! - \brief ENET Tx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; - enet_txfifo_flush(); - ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; -} - -/*! - \brief ENET Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_REN; - ENET_DMA_CTL |= ENET_DMA_CTL_SRE; -} - -/*! - \brief ENET Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; - ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; -} - -/*! - \brief put registers value into the application buffer - \param[in] type: register type which will be get, refer to enet_registers_type_enum, - only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH - \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT - \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL - \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR - \param[in] num: the number of registers that the user want to get - \param[out] preg: the application buffer pointer for storing the register value - \retval none -*/ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) -{ - uint32_t offset = 0U, max = 0U, limit = 0U; - - offset = (uint32_t)type; - max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - - /* prevent element in this array is out of range */ - if(max > limit){ - max = limit; - } - - for(; offset < max; offset++){ - /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); - preg++; - } -} - -/*! - \brief get the enet debug status from the debug register - \param[in] mac_debug: enet debug status, - only one parameter can be selected which is shown as below - \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state - \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status - \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation - \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status - \arg ENET_RXFIFO_STATE: RxFIFO state - \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state - \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter - \arg ENET_PAUSE_CONDITION_STATUS: pause condition status - \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status - \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation - \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty - \arg ENET_TXFIFO_FULL: TxFIFO is full - \param[out] none - \retval value of the status users want to get -*/ -uint32_t enet_debug_status_get(uint32_t mac_debug) -{ - uint32_t temp_state = 0U; - - switch(mac_debug){ - case ENET_RX_ASYNCHRONOUS_FIFO_STATE: - temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); - break; - case ENET_RXFIFO_READ_STATUS: - temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); - break; - case ENET_RXFIFO_STATE: - temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); - break; - case ENET_MAC_TRANSMITTER_STATUS: - temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); - break; - case ENET_TXFIFO_READ_STATUS: - temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); - break; - default: - if(RESET != (ENET_MAC_DBG & mac_debug)){ - temp_state = 0x1U; - } - break; - } - return temp_state; -} - -/*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable - \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_enable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief disable the MAC address filter - \param[in] mac_addr: select which MAC address will be disable, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_disable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief configure the MAC address filter - \param[in] mac_addr: select which MAC address will be configured, - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter - \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter - \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter - \param[in] addr_mask: select which MAC address bytes will be mask, - one or more parameters can be selected which are shown as below - \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits - \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits - \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits - \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits - \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits - \param[in] filter_type: select which MAC address filter type will be selected, - only one parameter can be selected which is shown as below - \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame - \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame - \param[out] none - \retval none -*/ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) -{ - uint32_t reg; - - /* get the address filter register value which is to be configured */ - reg = REG32(ENET_ADDRH_BASE + mac_addr); - - /* clear and configure the address filter register */ - reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); - reg |= (addr_mask | filter_type); - REG32(ENET_ADDRH_BASE + mac_addr) = reg; -} - -/*! - \brief PHY interface configuration (configure SMI clock and reset PHY chip) - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_config(void) -{ - uint32_t ahbclk; - uint32_t reg; - uint16_t phy_value; - ErrStatus enet_state = ERROR; - - /* clear the previous MDC clock */ - reg = ENET_MAC_PHY_CTL; - reg &= ~ENET_MAC_PHY_CTL_CLR; - - /* get the HCLK frequency */ - ahbclk = rcu_clock_freq_get(CK_AHB); - - /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ - reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ - reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){ - reg |= ENET_MDC_HCLK_DIV42; - }else if((ENET_RANGE(ahbclk, 100000000U, 120000000U))||(120000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV62; - }else{ - return enet_state; - } - ENET_MAC_PHY_CTL = reg; - - /* reset PHY */ - phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - /* PHY reset need some time */ - _ENET_DELAY_(ENET_DELAY_TO); - - /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - - /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief write to / read from a PHY register - \param[in] direction: only one parameter can be selected which is shown as below - \arg ENET_PHY_WRITE: write data to phy register - \arg ENET_PHY_READ: read data from phy register - \param[in] phy_address: 0x0 - 0x1F - \param[in] phy_reg: 0x0 - 0x1F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction - \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) -{ - uint32_t reg, phy_flag; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* configure ENET_MAC_PHY_CTL with write/read operation */ - reg = ENET_MAC_PHY_CTL; - reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); - - /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; - } - - /* do PHY write/read operation, and wait the operation complete */ - ENET_MAC_PHY_CTL = reg; - do{ - phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); - timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - - /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ - enet_state = SUCCESS; - } - - /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; - } - - return enet_state; -} - -/*! - \brief enable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_enable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* enable the PHY loopback mode */ - temp_phy |= PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief disable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_disable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* disable the PHY loopback mode */ - temp_phy &= (uint16_t)~PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief enable ENET forward feature - \param[in] feature: the feature of ENET forward mode, - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames - \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding - \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames - \param[out] none - \retval none -*/ -void enet_forward_feature_enable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG |= mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); - ENET_DMA_CTL |= (mask >> 2); -} - -/*! - \brief disable ENET forward feature - \param[in] feature: the feature of ENET forward mode, - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function - \arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC - \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_forward_feature_disable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG &= ~mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); - ENET_DMA_CTL &= ~(mask >> 2); -} - -/*! - \brief enable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_enable(uint32_t feature) -{ - ENET_MAC_FRMF |= feature; -} - -/*! - \brief disable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_disable(uint32_t feature) -{ - ENET_MAC_FRMF &= ~feature; -} - -/*! - \brief generate the pause frame, ENET will send pause frame after enable transmit flow control - this function only use in full-dulex mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_pauseframe_generate(void) -{ - ErrStatus enet_state =ERROR; - uint32_t temp = 0U; - - /* in full-duplex mode, must make sure this bit is 0 before writing register */ - temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ - ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; - enet_state = SUCCESS; - } - return enet_state; -} - -/*! - \brief configure the pause frame detect type - \param[in] detect: pause frame detect type, - only one parameter can be selected which is shown as below - \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also - use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified - in IEEE802.3 can be detected - \param[out] none - \retval none -*/ -void enet_pauseframe_detect_config(uint32_t detect) -{ - ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; - ENET_MAC_FCTL |= detect; -} - -/*! - \brief configure the pause frame parameters - \param[in] pausetime: pause time in transmit pause control frame - \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically, - this value must make sure to be less than configured pause time, only one parameter can be - selected which is shown as below - \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times - \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times - \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times - \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times - \param[out] none - \retval none -*/ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) -{ - ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); - ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); -} - -/*! - \brief configure the threshold of the flow control(deactive and active threshold) - \param[in] deactive: the threshold of the deactive flow control, this value - should always be less than active flow control value, only one - parameter can be selected which is shown as below - \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[in] active: the threshold of the active flow control, only one parameter - can be selected which is shown as below - \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[out] none - \retval none -*/ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) -{ - ENET_MAC_FCTH = ((deactive | active) >> 8); -} - -/*! - \brief enable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_enable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL |= feature; -} - -/*! - \brief disable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_disable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL &= ~feature; -} - -/*! - \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: dma transmit process - \arg ENET_DMA_RX: dma receive process - \param[out] none - \retval state of dma process, the value range shows below: - ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, - ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, - ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, - ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING -*/ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) -{ - uint32_t reval; - reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); - return reval; -} - -/*! - \brief poll the DMA transmission/reception enable by writing any value to the - ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, - refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA transmit process - \arg ENET_DMA_RX: DMA receive process - \param[out] none - \retval none -*/ -void enet_dmaprocess_resume(enet_dmadirection_enum direction) -{ - if(ENET_DMA_TX == direction){ - ENET_DMA_TPEN = 0U; - }else{ - ENET_DMA_RPEN = 0U; - } -} - -/*! - \brief check and recover the Rx process - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxprocess_check_recovery(void) -{ - uint32_t status; - - /* get DAV information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with - receive descriptor address pointer updated by RxDMA controller */ - if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; - } -} - -/*! - \brief flush the ENET transmit FIFO, and wait until the flush operation completes - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_txfifo_flush(void) -{ - uint32_t flush_state; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; - /* wait until the flush operation completes */ - do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; - timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(RESET == flush_state){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table - \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum, - only one parameter can be selected which is shown as below - \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table - \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by - the RxDMA controller - \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller - \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table - \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by - the TxDMA controller - \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none - \retval address value -*/ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) -{ - uint32_t reval = 0U; - - reval = REG32((ENET) +(uint32_t)addr_get); - return reval; -} - -/*! - \brief get the Tx or Rx descriptor information - \param[in] desc: the descriptor pointer which users want to get information - \param[in] info_get: the descriptor information type which is selected, - only one parameter can be selected which is shown as below - \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size - \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size - \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer - \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted - \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame - \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame - \param[out] none - \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter -*/ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) -{ - uint32_t reval = 0xFFFFFFFFU; - - switch(info_get){ - case RXDESC_BUFFER_1_SIZE: - reval = GET_RDES1_RB1S(desc->control_buffer_size); - break; - case RXDESC_BUFFER_2_SIZE: - reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: - reval = GET_RDES0_FRML(desc->status); - reval = reval - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ - reval = reval + 4U; - } - break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_COLLISION_COUNT: - reval = GET_TDES0_COCNT(desc->status); - break; - default: - break; - } - return reval; -} - -/*! - \brief get the number of missed frames during receiving - \param[in] none - \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO - \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller - \retval none -*/ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) -{ - uint32_t temp_counter = 0U; - - temp_counter = ENET_DMA_MFBOCNT; - *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); - *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); -} - -/*! - \brief get the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to get flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred - \arg ENET_TDES0_UFE: underflow error - \arg ENET_TDES0_EXD: excessive deferral - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_ECO: excessive collision - \arg ENET_TDES0_LCO: late collision - \arg ENET_TDES0_NCA: no carrier - \arg ENET_TDES0_LCA: loss of carrier - \arg ENET_TDES0_IPPE: IP payload error - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_JT: jabber timeout - \arg ENET_TDES0_ES: error summary - \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error - \arg ENET_RDES0_EXSV: extended status valid - \arg ENET_RDES0_CERR: CRC error - \arg ENET_RDES0_DBERR: dribble bit error - \arg ENET_RDES0_RERR: receive error - \arg ENET_RDES0_RWDT: receive watchdog timeout - \arg ENET_RDES0_FRMT: frame type - \arg ENET_RDES0_LCO: late collision - \arg ENET_RDES0_IPHERR: IP frame header error - \arg ENET_RDES0_TSV: timestamp valid - \arg ENET_RDES0_LDES: last descriptor - \arg ENET_RDES0_FDES: first descriptor - \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error - \arg ENET_RDES0_LERR: length error - \arg ENET_RDES0_SAFF: SA filter fail - \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary - \arg ENET_RDES0_DAFF: destination address filter fail - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - FlagStatus enet_flag = RESET; - - if ((uint32_t)RESET != (desc->status & desc_flag)){ - enet_flag = SET; - } - - return enet_flag; -} - -/*! - \brief set the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to set flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status |= desc_flag; -} - -/*! - \brief clear the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to clear flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor, - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status &= ~desc_flag; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set - \param[in] desc: the descriptor pointer which users want to configure - \param[out] none - \retval none -*/ -void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc) -{ - desc->control_buffer_size &= ~ENET_RDES1_DINTC; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time - \param[in] desc: the descriptor pointer which users want to configure - \param[in] delay_time: delay a time of 256*delay_time HCLK, this value must be between 0 and 0xFF - \param[out] none - \retval none -*/ -void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time) -{ - desc->control_buffer_size |= ENET_RDES1_DINTC; - ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time); -} - -/*! - \brief drop current receive frame - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxframe_drop(void) -{ - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - } - - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - } - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc++; - } - } - } -} - -/*! - \brief enable DMA feature - \param[in] feature: the feature of DMA mode, - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_enable(uint32_t feature) -{ - ENET_DMA_CTL |= feature; -} - -/*! - \brief disable DMA feature - \param[in] feature: the feature of DMA mode, - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_disable(uint32_t feature) -{ - ENET_DMA_CTL &= ~feature; -} - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/*! - \brief get the bit of extended status flag in ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to get the extended status flag - \param[in] desc_status: the extended status want to get, - only one parameter can be selected which is shown as below - \arg ENET_RDES4_IPPLDT: IP frame payload type - \arg ENET_RDES4_IPHERR: IP frame header error - \arg ENET_RDES4_IPPLDERR: IP frame payload error - \arg ENET_RDES4_IPCKSB: IP frame checksum bypassed - \arg ENET_RDES4_IPF4: IP frame in version 4 - \arg ENET_RDES4_IPF6: IP frame in version 6 - \arg ENET_RDES4_PTPMT: PTP message type - \arg ENET_RDES4_PTPOEF: PTP on ethernet frame - \arg ENET_RDES4_PTPVF: PTP version format - \param[out] none - \retval value of extended status -*/ -uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) -{ - uint32_t reval = 0xFFFFFFFFU; - - switch (desc_status){ - case ENET_RDES4_IPPLDT: - reval = GET_RDES4_IPPLDT(desc->extended_status); - break; - case ENET_RDES4_PTPMT: - reval = GET_RDES4_PTPMT(desc->extended_status); - break; - default: - if ((uint32_t)RESET != (desc->extended_status & desc_status)){ - reval = 1U; - }else{ - reval = 0U; - } - } - - return reval; -} - -/*! - \brief configure descriptor to work in enhanced mode - \param[in] none - \param[out] none - \retval none -*/ -void enet_desc_select_enhanced_mode(void) -{ - ENET_DMA_BCTL |= ENET_DMA_BCTL_DFM; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - - /* configuration each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; - } - } -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc; - enet_descriptors_struct *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select ring mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* set buffer1 size */ - desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - } -} - -/*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] buffer: pointer to the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) -{ - uint32_t offset = 0U, size = 0U; - uint32_t timeout = 0U; - uint32_t rdes0_tsv_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); - } - }else{ - return ERROR; - } - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and - write to the RDES6 and RDES7 */ - do{ - rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); - timeout++; - }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_RDES0_TSV flag */ - dma_current_rxdesc->status &= ~ENET_RDES0_TSV; - /* get the timestamp value of the received frame */ - timestamp[0] = dma_current_rxdesc->timestamp_low; - timestamp[1] = dma_current_rxdesc->timestamp_high; - } - - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* Clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - } - } - - return SUCCESS; -} - -/*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode - \param[in] buffer: pointer on the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) -{ - uint32_t offset = 0; - uint32_t dma_tbu_flag, dma_tu_flag; - uint32_t tdes0_ttmss_flag; - uint32_t timeout = 0; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0; offset < length; offset++){ - (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* Clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->timestamp_low; - timestamp[1] = dma_current_txdesc->timestamp_high; - } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - } - } - - return SUCCESS; -} - -#else - -/*! - \brief configure descriptor to work in normal mode - \param[in] none - \param[out] none - \retval none -*/ -void enet_desc_select_normal_mode(void) -{ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DFM; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum, - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select ring mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive ring mode and set buffer1 size */ - desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] timestamp: pointer to the table which stores the timestamp high and low - \param[out] buffer: pointer to the application buffer - note -- if the input is NULL, user should copy data in application by himself - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); - } - - }else{ - return ERROR; - } - } - /* copy timestamp value from Rx descriptor to application array */ - timestamp[0] = dma_current_rxdesc->buffer1_addr; - timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; - - dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; - dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_rxdesc ++; - } - } - - return SUCCESS; -} - -/*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode - \param[in] buffer: pointer on the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) -{ - uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->buffer1_addr; - timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; - } - dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; - dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_txdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; - } - } - return SUCCESS; -} - -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/*! - \brief wakeup frame filter register pointer reset - \param[in] none - \param[out] none - \retval none -*/ -void enet_wum_filter_register_pointer_reset(void) -{ - ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; -} - -/*! - \brief set the remote wakeup frame registers - \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) - \param[out] none - \retval none -*/ -void enet_wum_filter_config(uint32_t pdata[]) -{ - uint32_t num = 0U; - - /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ - ENET_MAC_RWFF = pdata[num]; - } -} - -/*! - \brief enable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_WUM_POWER_DOWN: power down mode - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_enable(uint32_t feature) -{ - ENET_MAC_WUM |= feature; -} - -/*! - \brief disable wakeup management features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_disable(uint32_t feature) -{ - ENET_MAC_WUM &= (~feature); -} - -/*! - \brief reset the MAC statistics counters - \param[in] none - \param[out] none - \retval none -*/ -void enet_msc_counters_reset(void) -{ - /* reset all counters */ - ENET_MSC_CTL |= ENET_MSC_CTL_CTR; -} - -/*! - \brief enable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_enable(uint32_t feature) -{ - ENET_MSC_CTL |= feature; -} - -/*! - \brief disable the MAC statistics counter features - \param[in] feature: one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_disable(uint32_t feature) -{ - ENET_MSC_CTL &= (~feature); -} - -/*! - \brief configure MAC statistics counters preset mode - \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum, - only one parameter can be selected which is shown as below - \arg ENET_MSC_PRESET_NONE: do not preset MSC counter - \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value - \arg ENET_MSC_PRESET_FULL: preset all MSC counters to almost-full(0xFFFF FFF0) value - \param[out] none - \retval none -*/ -void enet_msc_counters_preset_config(enet_msc_preset_enum mode) -{ - ENET_MSC_CTL &= ENET_MSC_PRESET_MASK; - ENET_MSC_CTL |= (uint32_t)mode; -} - -/*! - \brief get MAC statistics counter - \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, - only one parameter can be selected which is shown as below - \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter - \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter - \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter - \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter - \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter - \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter - \param[out] none - \retval the MSC counter value -*/ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) -{ - uint32_t reval; - - reval = REG32((ENET + (uint32_t)counter)); - - return reval; -} - -/*! - \brief change subsecond to nanosecond - \param[in] subsecond: subsecond value - \param[out] none - \retval the nanosecond value -*/ -uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) -{ - uint64_t val = subsecond * 1000000000Ull; - val >>= 31; - return (uint32_t)val; -} - -/*! - \brief change nanosecond to subsecond - \param[in] nanosecond: nanosecond value - \param[out] none - \retval the subsecond value -*/ -uint32_t enet_ptp_nanosecond_2_subsecond(uint32_t nanosecond) -{ - uint64_t val = nanosecond * 0x80000000Ull; - val /= 1000000000U; - return (uint32_t)val; -} - -/*! - \brief enable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot - \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame - \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame - \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame - \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame - \param[out] none - \retval none -*/ -void enet_ptp_feature_enable(uint32_t feature) -{ - ENET_PTP_TSCTL |= feature; -} - -/*! - \brief disable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot - \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame - \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame - \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame - \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame - \param[out] none - \retval none -*/ -void enet_ptp_feature_disable(uint32_t feature) -{ - ENET_PTP_TSCTL &= ~feature; -} - -/*! - \brief configure the PTP timestamp function - \param[in] func: only one parameter can be selected which is shown as below - \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp - \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp - \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp - \arg ENET_CKNT_PEER_TO_PEER: type of peer-to-peer transparent clock node type for timestamp - \arg ENET_PTP_ADDEND_UPDATE: addend register update - \arg ENET_PTP_SYSTIME_UPDATE: timestamp update - \arg ENET_PTP_SYSTIME_INIT: timestamp initialize - \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating - \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating - \arg ENET_SUBSECOND_DIGITAL_ROLLOVER: digital rollover mode - \arg ENET_SUBSECOND_BINARY_ROLLOVER: binary rollover mode - \arg ENET_SNOOPING_PTP_VERSION_2: version 2 - \arg ENET_SNOOPING_PTP_VERSION_1: version 1 - \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot - \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, - management and signaling message - \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message - \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) -{ - uint32_t temp_config = 0U, temp_state = 0U; - uint32_t timeout = 0U; - ErrStatus enet_state = SUCCESS; - - switch(func){ - case ENET_CKNT_ORDINARY: - case ENET_CKNT_BOUNDARY: - case ENET_CKNT_END_TO_END: - case ENET_CKNT_PEER_TO_PEER: - ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; - ENET_PTP_TSCTL |= (uint32_t)func; - break; - case ENET_PTP_ADDEND_UPDATE: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } - break; - case ENET_PTP_SYSTIME_UPDATE: - /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; - case ENET_PTP_SYSTIME_INIT: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; - default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; - } - break; - } - - return enet_state; -} - -/*! - \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time, - this value must be between 0 and 0xFF - \param[out] none - \retval none -*/ -void enet_ptp_subsecond_increment_config(uint32_t subsecond) -{ - ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); -} - -/*! - \brief adjusting the clock frequency only in fine update mode - \param[in] add: the value will be added to the accumulator register to achieve time synchronization - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_addend_config(uint32_t add) -{ - ENET_PTP_TSADDEND = add; -} - -/*! - \brief initialize or add/subtract to second of the system time - \param[in] sign: timestamp update positive or negative sign, - only one parameter can be selected which is shown as below - \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time - \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time - \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time - with 0.46 ns accuracy if required accuracy is 20 ns - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) -{ - ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); -} - -/*! - \brief configure the expected target time - \param[in] second: the expected target second time - \param[in] nanosecond: the expected target nanosecond time (signed) - \param[out] none - \retval none -*/ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) -{ - ENET_PTP_ETH = second; - ENET_PTP_ETL = nanosecond; -} - -/*! - \brief get the current system time - \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \retval none -*/ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) -{ - uint32_t temp_sec = 0U, temp_subs = 0U; - - /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; - temp_subs = (uint32_t)ENET_PTP_TSL; - - /* get sysytem time and construct the enet_ptp_systime_struct structure */ - systime_struct->second = temp_sec; - systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); - systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); - systime_struct->sign = GET_PTP_TSL_STS(temp_subs); -} - -/*! - \brief configure the PPS output frequency - \param[in] freq: PPS output frequency, - only one parameter can be selected which is shown as below - \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency - \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency - \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency - \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency - \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency - \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency - \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency - \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency - \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency - \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency - \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency - \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency - \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency - \arg ENET_PPSOFC_8192HZ: PPS output 8192Hz frequency - \arg ENET_PPSOFC_16384HZ: PPS output 16384Hz frequency - \arg ENET_PPSOFC_32768HZ: PPS output 32768Hz frequency - \param[out] none - \retval none -*/ -void enet_ptp_pps_output_frequency_config(uint32_t freq) -{ - ENET_PTP_PPSCTL = freq; -} - -/*! - \brief configure and start PTP timestamp counter - \param[in] updatemethod: method for updating - \arg ENET_PTP_FINEMODE: fine correction method - \arg ENET_PTP_COARSEMODE: coarse correction method - \param[in] init_sec: second value for initializing system time - \param[in] init_subsec: subsecond value for initializing system time - \param[in] carry_cfg: the value to be added to the accumulator register (in fine method is used) - \param[in] accuracy_cfg: the value to be added to the subsecond value of system time - \param[out] none - \retval none -*/ -void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) -{ - /* mask the timestamp trigger interrupt */ - enet_interrupt_disable(ENET_MAC_INT_TMSTIM); - - /* enable timestamp */ - enet_ptp_feature_enable(ENET_ALL_RX_TIMESTAMP | ENET_RXTX_TIMESTAMP); - - /* configure system time subsecond increment based on the PTP clock frequency */ - enet_ptp_subsecond_increment_config(accuracy_cfg); - - if(ENET_PTP_FINEMODE == updatemethod){ - /* fine correction method: configure the timestamp addend, then update */ - enet_ptp_timestamp_addend_config(carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); - /* wait until update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ - } - } - - /* choose the fine correction method */ - enet_ptp_timestamp_function_config((enet_ptp_function_enum)updatemethod); - - /* initialize the system time */ - enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE - enet_desc_select_enhanced_mode(); -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ -} - -/*! - \brief adjust frequency in fine method by configure addend register - \param[in] carry_cfg: the value to be added to the accumulator register - \param[out] none - \retval none -*/ -void enet_ptp_finecorrection_adjfreq(int32_t carry_cfg) -{ - /* re-configure the timestamp addend, then update */ - enet_ptp_timestamp_addend_config((uint32_t)carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); -} - -/*! - \brief update system time in coarse method - \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \param[out] none - \retval none -*/ -void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_struct) -{ - uint32_t subsecond_val; - uint32_t carry_cfg; - - subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); - - /* save the carry_cfg value */ - carry_cfg = ENET_PTP_TSADDEND_TMSA; - - /* update the system time */ - enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); - - /* wait until the update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ - } - - /* write back the carry_cfg value, then update */ - enet_ptp_timestamp_addend_config(carry_cfg); - enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); -} - -/*! - \brief set system time in fine method - \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - nanosecond: 0x0 - 0x7FFF FFFF * 10^9 / 2^31 - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \param[out] none - \retval none -*/ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) -{ - uint32_t subsecond_val; - - subsecond_val = enet_ptp_nanosecond_2_subsecond(systime_struct->nanosecond); - - /* initialize the system time */ - enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); - enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); - - /* wait until the system time initialzation finished */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ - } -} - -/*! - \brief get the ptp flag status - \param[in] flag: ptp flag status to be checked - \arg ENET_PTP_ADDEND_UPDATE: addend register update - \arg ENET_PTP_SYSTIME_UPDATE: timestamp update - \arg ENET_PTP_SYSTIME_INIT: timestamp initialize - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_ptp_flag_get(uint32_t flag) -{ - FlagStatus bitstatus = RESET; - - if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ - bitstatus = SET; - } - - return bitstatus; -} - -/*! - \brief reset the ENET initpara struct, call it before using enet_initpara_config() - \param[in] none - \param[out] none - \retval none -*/ -void enet_initpara_reset(void) -{ - enet_initpara.option_enable = 0U; - enet_initpara.forward_frame = 0U; - enet_initpara.dmabus_mode = 0U; - enet_initpara.dma_maxburst = 0U; - enet_initpara.dma_arbitration = 0U; - enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; - enet_initpara.vlan_config = 0U; - enet_initpara.flow_control = 0U; - enet_initpara.hashtable_high = 0U; - enet_initpara.hashtable_low = 0U; - enet_initpara.framesfilter_mode = 0U; - enet_initpara.halfduplex_param = 0U; - enet_initpara.timer_config = 0U; - enet_initpara.interframegap = 0U; -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() - \param[in] none - \param[out] none - \retval none -*/ -static void enet_default_init(void) -{ - uint32_t reg_value = 0U; - - /* MAC */ - /* configure ENET_MAC_CFG register */ - reg_value = ENET_MAC_CFG; - reg_value &= MAC_CFG_MASK; - reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_TYPEFRAME_CRC_DROP_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; - ENET_MAC_CFG = reg_value; - - /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; - - /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ - ENET_MAC_HLH = 0x0U; - - ENET_MAC_HLL = 0x0U; - - /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ - reg_value = ENET_MAC_FCTL; - reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; - ENET_MAC_FCTL = reg_value; - - ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - - /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); - - /* DMA */ - /* configure ENET_DMA_CTL register */ - reg_value = ENET_DMA_CTL; - reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; - ENET_DMA_CTL = reg_value; - - /* configure ENET_DMA_BCTL register */ - reg_value = ENET_DMA_BCTL; - reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ - |ENET_NORMAL_DESCRIPTOR; - ENET_DMA_BCTL = reg_value; -} - -#ifndef USE_DELAY -/*! - \brief insert a delay time - \param[in] ncount: specifies the delay time length - \param[out] none - \param[out] none -*/ -static void enet_delay(uint32_t ncount) -{ - uint32_t delay_time = 0U; - - for(delay_time = ncount; delay_time != 0U; delay_time--){ - } -} -#endif /* USE_DELAY */ - -#endif /* GD32F30X_CL */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c deleted file mode 100644 index e943863b07..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c +++ /dev/null @@ -1,629 +0,0 @@ -/*! - \file gd32f30x_exmc.c - \brief EXMC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_exmc.h" - -/* EXMC bank0 register reset value */ -#define BANK0_SNCTL_REGION0_RESET ((uint32_t)0x000030DBU) -#define BANK0_SNCTL_REGION1_2_3_RESET ((uint32_t)0x000030D2U) -#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) -#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) - -/* EXMC bank1/2 register reset mask*/ -#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) - -/* EXMC bank3 register reset mask*/ -#define BANK3_NPCTL_RESET ((uint32_t)0x00000018U) -#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK3_NPCTCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_NPATCFG_RESET ((uint32_t)0xFCFCFCFCU) -#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFCFCFCFCU) - -/* EXMC register bit offset */ -#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) -#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) -#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) -#define SNCTL_WREN_OFFSET ((uint32_t)12U) -#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) -#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) -#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) - -#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) -#define SNTCFG_DSET_OFFSET ((uint32_t)8U) -#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) - -#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U) -#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U) -#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U) - -#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) -#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) - -#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) -#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) - -#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) -#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) -#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) - -#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) -#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) -#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) - -#define INTEN_INTS_OFFSET ((uint32_t)3U) - -/*! - \brief deinitialize EXMC NOR/SRAM region - \param[in] exmc_norsram_region: select the region of bank0 - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_deinit(uint32_t exmc_norsram_region) -{ - /* reset the registers */ - if(EXMC_BANK0_NORSRAM_REGION0 == exmc_norsram_region){ - EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION0_RESET; - }else{ - EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_REGION1_2_3_RESET; - } - EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; - EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; -} - -/*! - \brief initialize EXMC NOR/SRAM region - \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0..3 - write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE - asyn_wait: ENABLE or DISABLE - nwait_signal: ENABLE or DISABLE - memory_write: ENABLE or DISABLE - nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING - wrap_burst_mode: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH - burst_mode: ENABLE or DISABLE - databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR - address_data_mux: ENABLE or DISABLE - read_write_timing: struct exmc_norsram_timing_parameter_struct set the time - write_timing: struct exmc_norsram_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; - - /* get the register value */ - snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); - - /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | - EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | - EXMC_SNCTL_SYNCWR )); - - snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - - sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| - (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | - (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | - (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )| - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ - snctl |= (uint32_t)EXMC_SNCTL_NREN; - } - - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode){ - snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET ) | - (((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD )| - (((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & EXMC_SNWTCFG_WDSET )| - (((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_SNWTCFG_WBUSLAT ) | - exmc_norsram_init_struct->write_timing->asyn_access_mode; - }else{ - snwtcfg = BANK0_SNWTCFG_RESET; - } - - /* configure the registers */ - EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; - EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; - EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; -} - -/*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_norsram_parameter_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - /* configure the structure with default value */ - exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; - exmc_norsram_init_struct->address_data_mux = ENABLE; - exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; - exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; - exmc_norsram_init_struct->burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - exmc_norsram_init_struct->wrap_burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; - exmc_norsram_init_struct->memory_write = ENABLE; - exmc_norsram_init_struct->nwait_signal = ENABLE; - exmc_norsram_init_struct->extended_mode = DISABLE; - exmc_norsram_init_struct->asyn_wait = DISABLE; - exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - - /* read/write timing configure */ - exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; - exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; - exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - - /* write timing configure, when extended mode is used */ - exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; -} - -/*! - \brief CRAM page size configure - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[in] page_size: CRAM page size - \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access - \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes - \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes - \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes - \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes - \param[out] none - \retval none -*/ -void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) -{ - /* reset the bits */ - EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; - - /* set the CPS bits */ - EXMC_SNCTL(exmc_norsram_region) |= page_size; -} - -/*! - \brief enable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_enable(uint32_t exmc_norsram_region) -{ - EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief disable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_disable(uint32_t exmc_norsram_region) -{ - EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief deinitialize EXMC NAND bank - \param[in] exmc_nand_bank: select the bank of NAND - \arg EXMC_BANKx_NAND(x=1..2) - \param[out] none - \retval none -*/ -void exmc_nand_deinit(uint32_t exmc_nand_bank) -{ - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ - EXMC_NPCTL(exmc_nand_bank) = BANK1_2_NPCTL_RESET; - EXMC_NPINTEN(exmc_nand_bank) = BANK1_2_NPINTEN_RESET; - EXMC_NPCTCFG(exmc_nand_bank) = BANK1_2_NPCTCFG_RESET; - EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET; -} - -/*! - \brief initialize EXMC NAND bank - \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter - nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND - ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - ecc_logic: ENABLE or DISABLE - databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - - npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| - EXMC_NPCTL_NDTP | - exmc_nand_init_struct->databus_width | - (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| - exmc_nand_init_struct->ecc_size | - exmc_nand_init_struct->ctr_latency | - exmc_nand_init_struct->atr_latency; - - npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - (((exmc_nand_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ - EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; - EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; - EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; -} - -/*! - \brief initialize the struct exmc_norsram_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_nand_parameter_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - /* configure the structure with default value */ - exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; - exmc_nand_init_struct->wait_feature = DISABLE; - exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; - exmc_nand_init_struct->ecc_logic = DISABLE; - exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; - exmc_nand_init_struct->ctr_latency = 0x0U; - exmc_nand_init_struct->atr_latency = 0x0U; - exmc_nand_init_struct->common_space_timing->setuptime = 0xfcU; - exmc_nand_init_struct->common_space_timing->waittime = 0xfcU; - exmc_nand_init_struct->common_space_timing->holdtime = 0xfcU; - exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->setuptime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->waittime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->holdtime = 0xfcU; - exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xfcU; -} - -/*! - \brief enable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_enable(uint32_t exmc_nand_bank) -{ - EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_disable(uint32_t exmc_nand_bank) -{ - EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_NDBKEN); -} - -/*! - \brief enable or disable the EXMC NAND ECC function - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) -{ - if (ENABLE == newvalue){ - /* enable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; - }else{ - /* disable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) &= (~EXMC_NPCTL_ECCEN); - } -} - -/*! - \brief get the EXMC ECC value - \param[in] exmc_nand_bank: specifie the NAND bank - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval the error correction code(ECC) value -*/ -uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) -{ - return (EXMC_NECC(exmc_nand_bank)); -} - -/*! - \brief deinitialize EXMC PC card bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_deinit(void) -{ - /* EXMC_BANK3_PCCARD */ - EXMC_NPCTL3 = BANK3_NPCTL_RESET; - EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; - EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; - EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; - EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; -} - -/*! - \brief initialize EXMC PC card bank - \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the EXMC bank3 PC card control register */ - EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; - - /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U)& EXMC_NPCTCFG_COMSET ) | - (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD )| - (((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime -1U) << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | - (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | - ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD )| - ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); -} - -/*! - \brief initialize the struct exmc_pccard_parameter_struct - \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer - \retval none -*/ -void exmc_pccard_parameter_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the structure with default value */ - exmc_pccard_init_struct->wait_feature = DISABLE; - exmc_pccard_init_struct->ctr_latency = 0x0U; - exmc_pccard_init_struct->atr_latency = 0x0U; - exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief enable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_enable(void) -{ - EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_disable(void) -{ - EXMC_NPCTL3 &= (~EXMC_NPCTL_NDBKEN); -} - -/*! - \brief check EXMC flag is set or not - \param[in] exmc_bank: specifies the NAND bank , PC card bank - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC Card bank - \param[in] flag: specify get which flag - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) -{ - uint32_t status = 0x00000000U; - - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(exmc_bank); - - if ((status & flag) != (uint32_t)flag ){ - /* flag is reset */ - return RESET; - }else{ - /* flag is set */ - return SET; - } -} - -/*! - \brief clear EXMC flag - \param[in] exmc_bank: specifie the NAND bank , PCCARD bank - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] flag: specify get which flag - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \param[out] none - \retval none -*/ -void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= (~flag); -} - -/*! - \brief check EXMC interrupt flag is set or not - \param[in] exmc_bank: specifies the NAND bank , PC card bank - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt_source) -{ - uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; - - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(exmc_bank); - interrupt_state = (status & (interrupt_source >> INTEN_INTS_OFFSET)); - - interrupt_enable = (status & interrupt_source); - - if ((interrupt_enable) && (interrupt_state)){ - /* interrupt flag is set */ - return SET; - }else{ - /* interrupt flag is reset */ - return RESET; - } -} - -/*! - \brief clear EXMC interrupt flag - \param[in] exmc_bank: specifies the NAND bank , PC card bank - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt_source) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~(interrupt_source >> INTEN_INTS_OFFSET); -} - -/*! - \brief enable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank,PC card bank - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt_source) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) |= interrupt_source; -} - -/*! - \brief disable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank , PC card bank - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \param[in] interrupt_source: specify get which interrupt flag - \arg EXMC_NAND_PCCARD_INT_RISE: interrupt source of rising edge - \arg EXMC_NAND_PCCARD_INT_LEVEL: interrupt source of high-level - \arg EXMC_NAND_PCCARD_INT_FALL: interrupt source of falling edge - \param[out] none - \retval none -*/ -void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt_source) -{ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= (~interrupt_source); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c deleted file mode 100644 index 2f8a04a7a4..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c +++ /dev/null @@ -1,227 +0,0 @@ -/*! - \file gd32f30x_exti.c - \brief EXTI driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "gd32f30x_exti.h" - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x00000000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; -} - -/*! - \brief initialize the EXTI - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling trigger - \arg EXTI_TRIG_BOTH: rising and falling trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch(trig_type){ - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI lines flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c deleted file mode 100644 index 6a37634dcc..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c +++ /dev/null @@ -1,927 +0,0 @@ -/*! - \file gd32f30x_fmc.c - \brief FMC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_fmc.h" - -/*! - \brief set the wait state counter value - \param[in] wscnt:wait state counter value - \arg WS_WSCNT_0: FMC 0 wait - \arg WS_WSCNT_1: FMC 1 wait - \arg WS_WSCNT_2: FMC 2 wait - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint32_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief unlock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ - /* write the FMC unlock key */ - FMC_KEY0 = UNLOCK_KEY0; - FMC_KEY0 = UNLOCK_KEY1; - } - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* write the FMC unlock key */ - if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){ - FMC_KEY1 = UNLOCK_KEY0; - FMC_KEY1 = UNLOCK_KEY1; - } - } -} - -/*! - \brief unlock the FMC bank0 operation - this function can be used for all GD32F20x devices. - for GD32F20x with flash more than 512KB, this function unlocks bank0. - for GD32F20x with flash no more than 512KB and it is equivalent to fmc_unlock function. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank0_unlock(void) -{ - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ - /* write the FMC unlock key */ - FMC_KEY0 = UNLOCK_KEY0; - FMC_KEY0 = UNLOCK_KEY1; - } -} - -/*! - \brief unlock the FMC bank1 operation - this function can be used for GD32F20x with flash more than 512KB. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank1_unlock(void) -{ - if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){ - /* write the FMC unlock key */ - FMC_KEY1 = UNLOCK_KEY0; - FMC_KEY1 = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit */ - FMC_CTL0 |= FMC_CTL0_LK; - - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* set the LK bit */ - FMC_CTL1 |= FMC_CTL1_LK; - } -} - -/*! - \brief lock the FMC bank0 operation - this function can be used for all GD32F20X devices. - for GD32F20x with flash more than 512KB, this function locks bank0. - for GD32F20x with flash no more than 512KB and it is equivalent to fmc_lock function. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank0_lock(void) -{ - /* set the LK bit*/ - FMC_CTL0 |= FMC_CTL0_LK; -} - -/*! - \brief lock the FMC bank1 operation - this function can be used for GD32F20x with flash more than 512KB. - \param[in] none - \param[out] none - \retval none -*/ -void fmc_bank1_lock(void) -{ - /* set the LK bit*/ - FMC_CTL1 |= FMC_CTL1_LK; -} - -/*! - \brief erase page - \param[in] page_address: the page address to be erased. - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state; - - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > page_address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_PER; - FMC_ADDR0 = page_address; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL0 &= ~FMC_CTL0_PER; - } - }else{ - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL1 |= FMC_CTL1_PER; - FMC_ADDR1 = page_address; - if(FMC_OBSTAT & FMC_OBSTAT_SPC){ - FMC_ADDR0 = page_address; - } - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL1 &= ~FMC_CTL1_PER; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_PER; - FMC_ADDR0 = page_address; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL0 &= ~FMC_CTL0_PER; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state; - if(FMC_BANK0_SIZE < FMC_SIZE){ - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL1 |= FMC_CTL1_MER; - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL1 &= ~FMC_CTL1_MER; - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase bank0 - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start FMC bank0 erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief erase bank1 - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start FMC bank1 erase */ - FMC_CTL1 |= FMC_CTL1_MER; - FMC_CTL1 |= FMC_CTL1_START; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL1 &= ~FMC_CTL1_MER; - } - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL1 |= FMC_CTL1_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL1 &= ~FMC_CTL1_PG; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a half word at the corresponding address - \param[in] address: address to program - \param[in] data: halfword to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - if(FMC_BANK0_SIZE < FMC_SIZE){ - if(FMC_BANK0_END_ADDRESS > address){ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - }else{ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL1 |= FMC_CTL1_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL1 &= ~FMC_CTL1_PG; - } - } - }else{ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWEN bit */ - FMC_CTL0 &= ~FMC_CTL0_OBWEN; -} - -/*! - \brief erase the FMC option byte - unlock the FMC_CTL0 and option byte before calling this function - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_erase(void) -{ - uint16_t temp_spc = FMC_NSPC; - - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - /* check the option byte security protection value */ - if(RESET != ob_spc_get()){ - temp_spc = FMC_USPC; - } - - if(FMC_READY == fmc_state){ - - /* start erase the option byte */ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - /* no security protection */ - OB_SPC = (uint16_t)temp_spc; - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected - \arg OB_WPx(x=0..31): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) -{ - uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; - - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - ob_wp = (uint32_t)(~ob_wp); - temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0); - temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U); - temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U); - temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U); - - if(FMC_READY == fmc_state){ - - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - if(0xFFU != temp_wp0){ - OB_WP0 = temp_wp0; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ - OB_WP1 = temp_wp1; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ - OB_WP2 = temp_wp2; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ - OB_WP3 = temp_wp3; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - } - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection - \arg FMC_NSPC: no security protection - \arg FMC_USPC: under security protection - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc) -{ - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - - /* start the option byte program */ - FMC_CTL0 |= FMC_CTL0_OBPG; - - OB_SPC = (uint16_t)ob_spc; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option byte - \param[in] ob_fwdgt: option byte watchdog value - \arg OB_FWDGT_SW: software free watchdog - \arg OB_FWDGT_HW: hardware free watchdog - \param[in] ob_deepsleep: option byte deepsleep reset value - \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \param[in] ob_stdby:option byte standby reset value - \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \param[in] ob_boot: specifies the option byte boot bank value - \arg OB_BOOT_B0: boot from bank0 - \arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) -{ - fmc_state_enum fmc_state = FMC_READY; - uint8_t temp; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); - OB_USER = (uint16_t)temp; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program option bytes data - \param[in] address: the option bytes address to be programmed - \param[in] data: the byte to be programmed - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data) -{ - fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - REG16(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC user option byte - \param[in] none - \param[out] none - \retval the FMC user option byte values -*/ -uint8_t ob_user_get(void) -{ - /* return the FMC user option byte value */ - return (uint8_t)(FMC_OBSTAT >> 2U); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> 10U); -} - -/*! - \brief get the FMC option byte write protection - \param[in] none - \param[out] none - \retval the FMC write protection option byte value -*/ -uint32_t ob_write_protection_get(void) -{ - /* return the FMC write protection option byte value */ - return FMC_WP; -} - -/*! - \brief get the FMC option byte security protection - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ob_spc_get(void) -{ - FlagStatus spc_state = RESET; - - if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ - spc_state = SET; - }else{ - spc_state = RESET; - } - return spc_state; -} - -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - \arg FMC_INT_BANK0_END: enable FMC end of program interrupt - \arg FMC_INT_BANK0_ERR: enable FMC error interrupt - \arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt - \arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief check flag is set or not - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit - \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit - \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit - \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit - \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit - \arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit - \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit - \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit - \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the FMC flag - \param[in] flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit - \arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit - \arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit - \arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit - \arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit - \arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag)); -} - -/*! - \brief get FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit - \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); - }else{ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); - } - - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit - \arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) -{ - FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); -} - -/*! - \brief get the FMC bank0 state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ - fmc_state = FMC_PGERR; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC bank1 state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){ - fmc_state = FMC_PGERR; - } - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC bank0 is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_bank0_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC bank1 is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_bank1_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c deleted file mode 100644 index b932b95bd4..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c +++ /dev/null @@ -1,120 +0,0 @@ -/*! - \file gd32f30x_fwdgt.c - \brief FWDGT driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_fwdgt.h" - -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(FWDGT_STAT & flag){ - return SET; - } - - return RESET; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c deleted file mode 100644 index fd70e4d9e6..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c +++ /dev/null @@ -1,531 +0,0 @@ -/*! - \file gd32f30x_gpio.c - \brief GPIO driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_gpio.h" - -#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ -#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ -#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ -#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ -#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ -#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ -#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch(gpio_periph){ - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOD: - /* reset GPIOD */ - rcu_periph_reset_enable(RCU_GPIODRST); - rcu_periph_reset_disable(RCU_GPIODRST); - break; - case GPIOE: - /* reset GPIOE */ - rcu_periph_reset_enable(RCU_GPIOERST); - rcu_periph_reset_disable(RCU_GPIOERST); - break; - case GPIOF: - /* reset GPIOF */ - rcu_periph_reset_enable(RCU_GPIOFRST); - rcu_periph_reset_disable(RCU_GPIOFRST); - break; - case GPIOG: - /* reset GPIOG */ - rcu_periph_reset_enable(RCU_GPIOGRST); - rcu_periph_reset_disable(RCU_GPIOGRST); - break; - default: - break; - } -} - -/*! - \brief reset alternate function I/O(AFIO) - \param[in] none - \param[out] none - \retval none -*/ -void gpio_afio_deinit(void) -{ - rcu_periph_reset_enable(RCU_AFRST); - rcu_periph_reset_disable(RCU_AFRST); -} - -/*! - \brief GPIO parameter initialization - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] mode: gpio pin mode - \arg GPIO_MODE_AIN: analog input mode - \arg GPIO_MODE_IN_FLOATING: floating input mode - \arg GPIO_MODE_IPD: pull-down input mode - \arg GPIO_MODE_IPU: pull-up input mode - \arg GPIO_MODE_OUT_OD: GPIO output with open-drain - \arg GPIO_MODE_OUT_PP: GPIO output with push-pull - \arg GPIO_MODE_AF_OD: AFIO output with open-drain - \arg GPIO_MODE_AF_PP: AFIO output with push-pull - \param[in] speed: gpio output max speed value - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \arg GPIO_OSPEED_MAX: output max speed more than 50MHz - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t temp_mode = 0U; - uint32_t reg = 0U; - - /* GPIO mode configuration */ - temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); - - /* GPIO speed configuration */ - if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ - /* output mode max speed */ - if(GPIO_OSPEED_MAX == (uint32_t)speed){ - temp_mode |= (uint32_t)0x03U; - /* set the corresponding SPD bit */ - GPIOx_SPD(gpio_periph) |= (uint32_t)pin ; - }else{ - /* output mode max speed:10MHz,2MHz,50MHz */ - temp_mode |= (uint32_t)speed; - } - } - - /* configure the eight low port pins with GPIO_CTL0 */ - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL0(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)pin; - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - } - } - /* set GPIO_CTL0 register */ - GPIO_CTL0(gpio_periph) = reg; - } - } - /* configure the eight high port pins with GPIO_CTL1 */ - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL1(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i - 8U); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i - 8U, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)pin; - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - } - } - /* set GPIO_CTL1 register */ - GPIO_CTL1(gpio_periph) = reg; - } - } -} - -/*! - \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph,uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph,uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph,uint32_t pin,bit_status bit_value) -{ - if(RESET != bit_value){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] data: specify the value to be written to the port output data register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph,uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval input status of gpio pin: SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO port input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval input status of gpio all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t)(GPIO_ISTAT(gpio_periph)); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval output status of gpio pin: SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) -{ - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO port output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[out] none - \retval output status of gpio all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return ((uint16_t)GPIO_OCTL(gpio_periph)); -} - -/*! - \brief lock GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E,F,G) - \param[in] pin: GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph,uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -/*! - \brief configure GPIO pin event output - \param[in] output_port: gpio event output port - \arg GPIO_EVENT_PORT_GPIOA: event output port A - \arg GPIO_EVENT_PORT_GPIOB: event output port B - \arg GPIO_EVENT_PORT_GPIOC: event output port C - \arg GPIO_EVENT_PORT_GPIOD: event output port D - \arg GPIO_EVENT_PORT_GPIOE: event output port E - \param[in] output_pin: GPIO_EVENT_PIN_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) -{ - uint32_t reg = 0U; - reg = AFIO_EC; - - /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ - reg &= (uint32_t)(~(AFIO_EC_PORT|AFIO_EC_PIN)); - - reg |= (uint32_t)((uint32_t)output_port << 0x04U); - reg |= (uint32_t)output_pin; - - AFIO_EC = reg; -} - -/*! - \brief enable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_enable(void) -{ - AFIO_EC |= AFIO_EC_EOE; -} - -/*! - \brief disable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_disable(void) -{ - AFIO_EC &= (uint32_t)(~AFIO_EC_EOE); -} - -/*! - \brief select GPIO pin exti sources - \param[in] output_port: gpio event output port - \arg GPIO_PORT_SOURCE_GPIOA: output port source A - \arg GPIO_PORT_SOURCE_GPIOB: output port source B - \arg GPIO_PORT_SOURCE_GPIOC: output port source C - \arg GPIO_PORT_SOURCE_GPIOD: output port source D - \arg GPIO_PORT_SOURCE_GPIOE: output port source E - \arg GPIO_PORT_SOURCE_GPIOF: output port source F - \arg GPIO_PORT_SOURCE_GPIOG: output port source G - \param[in] output_pin: GPIO_PIN_SOURCE_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) -{ - uint32_t source = 0U; - source = ((uint32_t)0x0FU) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U)); - - /* select EXTI sources */ - if(GPIO_PIN_SOURCE_4 > output_pin){ - /* select EXTI0/EXTI1/EXTI2/EXTI3 */ - AFIO_EXTISS0 &= ~source; - AFIO_EXTISS0 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); - }else if(GPIO_PIN_SOURCE_8 > output_pin){ - /* select EXTI4/EXTI5/EXTI6/EXTI7 */ - AFIO_EXTISS1 &= ~source; - AFIO_EXTISS1 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); - }else if(GPIO_PIN_SOURCE_12 > output_pin){ - /* select EXTI8/EXTI9/EXTI10/EXTI11 */ - AFIO_EXTISS2 &= ~source; - AFIO_EXTISS2 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); - }else{ - /* select EXTI12/EXTI13/EXTI14/EXTI15 */ - AFIO_EXTISS3 &= ~source; - AFIO_EXTISS3 |= (((uint32_t)output_port) << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & (uint8_t)0x03U))); - } -} - -#ifdef GD32F30X_CL -/*! - \brief select ethernet MII or RMII PHY - \param[in] enet_sel: ethernet MII or RMII PHY selection - \arg GPIO_ENET_PHY_MII: configure ethernet MAC for connection with an MII PHY - \arg GPIO_ENET_PHY_RMII: configure ethernet MAC for connection with an RMII PHY - \param[out] none - \retval none -*/ -void gpio_ethernet_phy_select(uint32_t enet_sel) -{ - /* clear AFIO_PCF0_ENET_PHY_SEL bit */ - AFIO_PCF0 &= (uint32_t)(~AFIO_PCF0_ENET_PHY_SEL); - - /* select MII or RMII PHY */ - AFIO_PCF0 |= (uint32_t)enet_sel; -} -#endif /* GD32F30X_CL */ - -/*! - \brief configure GPIO pin remap - \param[in] gpio_remap: select the pin to remap - \arg GPIO_SPI0_REMAP: SPI0 remapping - \arg GPIO_I2C0_REMAP: I2C0 remapping - \arg GPIO_USART0_REMAP: USART0 remapping - \arg GPIO_USART1_REMAP: USART1 remapping - \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping - \arg GPIO_USART2_FULL_REMAP: USART2 full remapping - \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping - \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping - \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping - \arg GPIO_TIMER1_PARTIAL_REMAP2: TIMER1 partial remapping - \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping - \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping - \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping - \arg GPIO_TIMER3_REMAP: TIMER3 remapping - \arg GPIO_CAN_PARTIAL_REMAP: CAN partial remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_CAN_FULL_REMAP: CAN full remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping(only for GD32F30X_CL devices) - \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping(only for GD32F30X_CL devices) - \arg GPIO_PD01_REMAP: PD01 remapping - \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping(only for GD32F30X_CL devices and GD32F30X_HD devices) - \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F30X_CL devices) - \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F30X_CL devices) - \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST - \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled - \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled - \arg GPIO_SPI2_REMAP: SPI2 remapping(only for GD32F30X_CL devices) - \arg GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) - \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F30X_CL devices) - \arg GPIO_TIMER8_REMAP: TIMER8 remapping - \arg GPIO_TIMER9_REMAP: TIMER9 remapping - \arg GPIO_TIMER10_REMAP: TIMER10 remapping - \arg GPIO_TIMER12_REMAP: TIMER12 remapping - \arg GPIO_TIMER13_REMAP: TIMER13 remapping - \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect - \arg GPIO_CTC_REMAP0: CTC remapping(PD15) - \arg GPIO_CTC_REMAP1: CTC remapping(PF0) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void gpio_pin_remap_config(uint32_t gpio_remap, ControlStatus newvalue) -{ - uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; - - if(((uint32_t)0x80000000U) == (gpio_remap & 0x80000000U)){ - /* get AFIO_PCF1 regiter value */ - temp_reg = AFIO_PCF1; - }else{ - /* get AFIO_PCF0 regiter value */ - temp_reg = AFIO_PCF0; - } - - temp_mask = (gpio_remap & PCF_POSITION_MASK) >> 0x10U; - remap1 = gpio_remap & LSB_16BIT_MASK; - - /* judge pin remap type */ - if((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) == (gpio_remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))){ - temp_reg &= PCF_SWJCFG_MASK; - AFIO_PCF0 &= PCF_SWJCFG_MASK; - }else if(PCF_LOCATION2_MASK == (gpio_remap & PCF_LOCATION2_MASK)){ - remap2 = ((uint32_t)0x03U) << temp_mask; - temp_reg &= ~remap2; - temp_reg |= ~PCF_SWJCFG_MASK; - }else{ - temp_reg &= ~(remap1 << ((gpio_remap >> 0x15U)*0x10U)); - temp_reg |= ~PCF_SWJCFG_MASK; - } - - /* set pin remap value */ - if(DISABLE != newvalue){ - temp_reg |= (remap1 << ((gpio_remap >> 0x15U)*0x10U)); - } - - if(AFIO_PCF1_FIELDS == (gpio_remap & AFIO_PCF1_FIELDS)){ - /* set AFIO_PCF1 regiter value */ - AFIO_PCF1 = temp_reg; - }else{ - /* set AFIO_PCF0 regiter value */ - AFIO_PCF0 = temp_reg; - } -} - -/*! - \brief configure the I/O compensation cell - \param[in] compensation: specifies the I/O compensation cell mode - \arg GPIO_COMPENSATION_ENABLE: I/O compensation cell is enabled - \arg GPIO_COMPENSATION_DISABLE: I/O compensation cell is disabled - \param[out] none - \retval none -*/ -void gpio_compensation_config(uint32_t compensation) -{ - uint32_t reg; - reg = AFIO_CPSCTL; - - /* reset the AFIO_CPSCTL_CPS_EN bit and set according to gpio_compensation */ - reg &= ~AFIO_CPSCTL_CPS_EN; - AFIO_CPSCTL = (reg | compensation); -} - -/*! - \brief check the I/O compensation cell is ready or not - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus gpio_compensation_flag_get(void) -{ - if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){ - return SET; - }else{ - return RESET; - } -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c deleted file mode 100644 index 711ea43526..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c +++ /dev/null @@ -1,683 +0,0 @@ -/*! - \file gd32f30x_i2c.c - \brief I2C driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_i2c.h" - -#define I2CCLK_MAX 0x7fU /*!< i2cclk max value */ -#define I2C_FLAG_MASK 0x0000FFFFU /*!< i2c flag mask */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch(i2c_periph){ - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - and fast mode plus (up to 1MHz) - \param[in] dutycyc: duty cycle in fast mode or fast mode plus - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1,clkc,freq,risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) = I2CCLK_MAX; - }else{ - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - }else if(400000U >= clkspeed){ - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if(0U == (clkc & I2C_CKCFG_CLKC)){ - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - }else{ - /* fast mode plus, the maximum SCL rise time is 120ns */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - /* enable fast mode */ - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - /* enable I2C fast mode plus */ - I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief I2C POAP position configure - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master send slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - if(I2C_TRANSMITTER == trandirection){ - addr = addr & I2C_TRANSMITTER; - }else{ - addr = addr | I2C_RECEIVER; - } - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief dual-address mode switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dualaddr: - \arg I2C_DUADEN_DISABLE: disable dual-address mode - \arg I2C_DUADEN_ENABLE: enable dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr) -{ - if(I2C_DUADEN_ENABLE == dualaddr){ - I2C_SADDR1(i2c_periph) |= I2C_SADDR1_DUADEN; - }else{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); - } -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none -*/ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief flag indicating DMA last transfer - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_enable(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_DISSTRC); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag) -{ - uint32_t reg = 0U; - FlagStatus reval = RESET; - /* get the flag in which register */ - reg = (BIT(31) & flag); - if((BIT(31) == reg)){ - if((I2C_STAT1(i2c_periph)&(flag & I2C_FLAG_MASK))){ - reval = SET; - }else{ - reval = RESET; - } - }else{ - if((I2C_STAT0(i2c_periph)&(flag & I2C_FLAG_MASK))){ - reval = SET; - }else{ - reval = RESET; - } - } - /* return the flag status */ - return reval; -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: flag type - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag) -{ - if(I2C_FLAG_ADDSEND == flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_STAT0(i2c_periph) &= ~(flag); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] inttype: interrupt type - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t inttype) -{ - I2C_CTL1(i2c_periph) |= (inttype); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] inttype: interrupt type - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t inttype) -{ - I2C_CTL1(i2c_periph) &= ~(inttype); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: interrupt flag - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, uint32_t intflag) -{ - uint32_t evie, errie, bufie; - - evie = I2C_CTL1(i2c_periph)&I2C_CTL1_EVIE; - errie = I2C_CTL1(i2c_periph)&I2C_CTL1_ERRIE; - /* check I2C event interrupt enable bit */ - if((intflag&0x00ffU) && evie){ - if(intflag&0x001fU){ - /* check I2C event flags except TBE and RBNE */ - if(intflag & I2C_STAT0(i2c_periph)){ - return SET; - }else{ - return RESET; - } - }else{ - /* check I2C event flags TBE and RBNE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - if(bufie){ - if(intflag & I2C_STAT0(i2c_periph)){ - return SET; - }else{ - return RESET; - } - }else{ - return RESET; - } - } - /* check I2C error interrupt enable bit */ - }else if((intflag&0xff00U) && errie){ - /* check I2C error flags */ - if(intflag & I2C_STAT0(i2c_periph)){ - return SET; - }else{ - return RESET; - } - }else{ - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] intflag: interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, uint32_t intflag) -{ - if(I2C_INT_FLAG_ADDSEND == intflag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_STAT0(i2c_periph) &= ~(intflag); - } -} - -/*! - \brief I2C PEC calculation on or off - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none -*/ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_ECV)>>8); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable or disable I2C ARP protocol in SMBus switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c deleted file mode 100644 index de7a064df7..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c +++ /dev/null @@ -1,146 +0,0 @@ -/*! - \file gd32f30x_misc.c - \brief MISC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "gd32f30x_misc.h" - -/*! - \brief set the priority group - \param[in] nvic_prigroup: the NVIC priority group - \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority - \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority - \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority - \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority - \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority - \param[out] none - \retval none -*/ -void nvic_priority_group_set(uint32_t nvic_prigroup) -{ - /* set the priority group value */ - SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; -} - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set - \param[in] nvic_irq_sub_priority: the subpriority needed to set - \param[out] none - \retval none -*/ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, - uint8_t nvic_irq_sub_priority) -{ - uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; - /* use the priority group value to get the temp_pre and the temp_sub */ - if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ - temp_pre=0U; - temp_sub=0x4U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ - temp_pre=1U; - temp_sub=0x3U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ - temp_pre=2U; - temp_sub=0x2U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ - temp_pre=3U; - temp_sub=0x1U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ - temp_pre=4U; - temp_sub=0x0U; - }else{ - } - /* get the temp_priority to fill the NVIC->IP register */ - temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); - temp_priority = temp_priority << 0x04U; - NVIC->IP[nvic_irq] = (uint8_t)temp_priority; - /* enable the selected IRQ */ - NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(uint8_t nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - \arg NVIC_VECTTAB_RAM: RAM base address - \are NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c deleted file mode 100644 index 6c534d6072..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c +++ /dev/null @@ -1,342 +0,0 @@ -/*! - \file gd32f30x_pmu.c - \brief PMU driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "gd32f30x_pmu.h" - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - \arg PMU_LVDT_0: voltage threshold is 2.1V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.6V - \arg PMU_LVDT_4: voltage threshold is 2.7V - \arg PMU_LVDT_5: voltage threshold is 2.9V - \arg PMU_LVDT_6: voltage threshold is 3.0V - \arg PMU_LVDT_7: voltage threshold is 3.1V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief select LDO output voltage - this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL - \param[in] ldo_output: - \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode - \arg PMU_LDOVS_MID: low-driver mode disable in deep-sleep mode - \arg PMU_LDOVS_HIGH: low-driver mode disable in deep-sleep mode - \param[out] none - \retval none -*/ -void pmu_ldo_output_select(uint32_t ldo_output) -{ - PMU_CTL &= ~PMU_CTL_LDOVS; - PMU_CTL |= ldo_output; -} - -/*! - \brief switch high-driver mode - this bit set by software only when IRC16M or HXTAL used as system clock - \param[in] highdr_switch: - \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch - \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch - \param[out] none - \retval none -*/ -void pmu_highdriver_switch_select(uint32_t highdr_switch) -{ - /* wait for HDRF flag set */ - while(SET != pmu_flag_get(PMU_FLAG_HDRF)){ - } - PMU_CTL &= ~PMU_CTL_HDS; - PMU_CTL |= highdr_switch; -} - -/*! - \brief enable low-driver mode in deep-sleep mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lowdriver_mode_enable(void) -{ - PMU_CTL |= PMU_CTL_LDEN; -} - -/*! - \brief disable low-driver mode in deep-sleep mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lowdriver_mode_disable(void) -{ - PMU_CTL &= ~PMU_CTL_LDEN; -} - -/*! - \brief enable high-driver mode - this bit set by software only when IRC16M or HXTAL used as system clock - \param[in] none - \param[out] none - \retval none -*/ -void pmu_highdriver_mode_enable(void) -{ - PMU_CTL |= PMU_CTL_HDEN; -} - -/*! - \brief disable high-driver mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_highdriver_mode_disable(void) -{ - PMU_CTL &= ~PMU_CTL_HDEN; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief driver mode when use low power LDO - \param[in] mode: - \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO - \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO - \param[out] none - \retval none -*/ -void pmu_lowpower_driver_config(uint32_t mode) -{ - PMU_CTL &= ~PMU_CTL_LDLP; - PMU_CTL |= mode; -} - -/*! - \brief driver mode when use normal power LDO - \param[in] mode: - \arg PMU_NORMALDR_NORMALPWR: normal driver when use low power LDO - \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO - \param[out] none - \retval none -*/ -void pmu_normalpower_driver_config(uint32_t mode) -{ - PMU_CTL &= ~PMU_CTL_LDNP; - PMU_CTL |= mode; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo - \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) -{ - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ - __WFI(); - }else{ - __SEV(); - __WFE(); - __WFE(); - } - /* reset sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief clear flag bit - \param[in] flag_reset: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag_reset) -{ - switch(flag_reset){ - case PMU_FLAG_RESET_WAKEUP: - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - break; - case PMU_FLAG_RESET_STANDBY: - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - break; - default : - break; - } -} - -/*! - \brief get flag state - \param[in] flag: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag - \arg PMU_FLAG_HDRF: high-driver ready flag - \arg PMU_FLAG_HDSRF: high-driver switch ready flag - \arg PMU_FLAG_LDRF: low-driver mode ready flag - \param[out] none - \retval FlagStatus SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - if(PMU_CS & flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief enable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief enable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(void) -{ - PMU_CS |= PMU_CS_WUPEN; -} - -/*! - \brief disable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(void) -{ - PMU_CS &= ~PMU_CS_WUPEN; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c deleted file mode 100644 index 01995edc39..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c +++ /dev/null @@ -1,1276 +0,0 @@ -/*! - \file gd32f30x_rcu.c - \brief RCU driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_rcu.h" - -/* define clock source */ -#define SEL_IRC8M ((uint16_t)0U) -#define SEL_HXTAL ((uint16_t)1U) -#define SEL_PLL ((uint16_t)2U) - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - rcu_osci_stab_wait(RCU_IRC8M); - - /* reset CFG0 register */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0 | RCU_CFG0_PLLMF | - RCU_CFG0_USBDPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_PLLMF_4 | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBDPSC_2); -#elif defined(GD32F30X_CL) - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5 | RCU_CFG0_USBFSPSC_2); -#endif /* GD32F30X_HD and GD32F30X_XD */ - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - RCU_CTL &= ~RCU_CTL_HXTALBPS; -#ifdef GD32F30X_CL - RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); -#endif /* GD32F30X_CL */ - - /* reset INT and CFG1 register */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - RCU_INT = 0x009f0000U; - RCU_CFG1 &= ~(RCU_CFG1_ADCPSC_3 | RCU_CFG1_PLLPRESEL); -#elif defined(GD32F30X_CL) - RCU_INT = 0x00ff0000U; - RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | - RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL | RCU_CFG1_ADCPSC_3 | - RCU_CFG1_PLLPRESEL | RCU_CFG1_PLL2MF_4); -#endif /* GD32F30X_HD and GD32F30X_XD */ -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF : alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_CTC: CTC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G): GPIO ports clock - \arg RCU_AF: alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_ENET: ENET clock(CL series available) - \arg RCU_ENETTX: ENETTX clock(CL series available) - \arg RCU_ENETRX: ENETRX clock(CL series available) - \arg RCU_USBD: USBD clock(HD,XD series available) - \arg RCU_USBFS: USBFS clock(CL series available) - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1,CAN1 is only available for CL series): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2,ADC2 is not available for CL series): ADC clock - \arg RCU_SDIO: SDIO clock(not available for CL series) - \arg RCU_CTC: CTC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC - \arg RCU_CTCRST: reset CTC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_ENETRST: reset ENET(CL series available) - \arg RCU_USBDRST: reset USBD(HD,XD series available) - \arg RCU_USBFSRST: reset USBFS(CL series available) - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1,CAN1 is only available for CL series): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2,ADC2 is not available for CL series): reset ADC - \arg RCU_CTCRST: reset CTC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP domain - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP domain reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - reg &= ~RCU_CFG0_SCS; - RCU_CFG0 = (reg | ck_sys); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source - \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source - \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the AHBPSC bits and set according to ck_ahb */ - reg &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (reg | ck_ahb); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB1PSC and set according to ck_apb1 */ - reg &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (reg | ck_apb1); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB2PSC and set according to ck_apb2 */ - reg &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (reg | ck_apb2); -} - -/*! - \brief configure the CK_OUT0 clock source - \param[in] ckout0_src: CK_OUT0 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT0SRC_NONE: no clock selected - \arg RCU_CKOUT0SRC_CKSYS: system clock selected - \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected - \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected - \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected - \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected - \arg RCU_CKOUT0SRC_EXT1: EXT1 selected - \arg RCU_CKOUT0SRC_CKPLL2: PLL selected - \param[out] none - \retval none -*/ -void rcu_ckout0_config(uint32_t ckout0_src) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the CKOUT0SRC, set according to ckout0_src */ - reg &= ~RCU_CFG0_CKOUT0SEL; - RCU_CFG0 = (reg | ckout0_src); -} - -/*! - \brief configure the main PLL clock - \param[in] pll_src: PLL clock source selection - \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL - \arg RCU_PLLSRC_HXTAL_IRC48M: HXTAL or IRC48M selected as source clock of PLL - \param[in] pll_mul: PLL clock multiplication factor - \arg RCU_PLL_MULx (XD series x = 2..63, CL series x = 2..14, 16..63, 6.5) - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - - /* PLL clock source and multiplication factor configuration */ - reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5); - reg |= (pll_src | pll_mul); - - RCU_CFG0 = reg; -} - -/*! - \brief configure the PLL clock source preselection - \param[in] pll_presel: PLL clock source preselection - \arg RCU_PLLPRESRC_HXTAL: HXTAL selected as PLL source clock - \arg RCU_PLLPRESRC_IRC48M: CK_PLL selected as PREDV0 input source clock - \param[out] none - \retval none -*/ -void rcu_pllpresel_config(uint32_t pll_presel) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - - /* PLL clock source preselection */ - reg &= ~RCU_CFG1_PLLPRESEL; - reg |= pll_presel; - - RCU_CFG1 = reg; -} - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -/*! - \brief configure the PREDV0 division factor - \param[in] predv0_div: PREDV0 division factor - \arg RCU_PREDV0_DIVx, x = 1,2 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - /* reset PREDV0 bit */ - reg &= ~RCU_CFG0_PREDV0; - if(RCU_PREDV0_DIV2 == predv0_div){ - /* set the PREDV0 bit */ - reg |= RCU_CFG0_PREDV0; - } - - RCU_CFG0 = reg; -} -#elif defined(GD32F30X_CL) -/*! - \brief configure the PREDV0 division factor and clock source - \param[in] predv0_source: PREDV0 input clock source selection - \arg RCU_PREDV0SRC_HXTAL_IRC48M: HXTAL or IRC48M selected as PREDV0 input source clock - \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock - \param[in] predv0_div: PREDV0 division factor - \arg RCU_PREDV0_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset PREDV0SEL and PREDV0 bits */ - reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); - /* set the PREDV0SEL and PREDV0 division factor */ - reg |= (predv0_source | predv0_div); - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PREDV1 division factor - \param[in] predv1_div: PREDV1 division factor - \arg RCU_PREDV1_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv1_config(uint32_t predv1_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset the PREDV1 bits */ - reg &= ~RCU_CFG1_PREDV1; - /* set the PREDV1 division factor */ - reg |= predv1_div; - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PLL1 clock - \param[in] pll_mul: PLL clock multiplication factor - \arg RCU_PLL1_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll1_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL1MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the PLL2 clock - \param[in] pll_mul: PLL clock multiplication factor - \arg RCU_PLL2_MULx (x = 8..16, 18..32, 40) - \param[out] none - \retval none -*/ -void rcu_pll2_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL2MF; - RCU_CFG1 |= pll_mul; -} -#endif /* GD32F30X_HD and GD32F30X_XD */ - -/*! - \brief configure the ADC prescaler factor - \param[in] adc_psc: ADC prescaler factor - \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 - \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 - \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 - \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 - \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 - \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 - \arg RCU_CKADC_CKAHB_DIV5: ADC prescaler select CK_AHB/5 - \arg RCU_CKADC_CKAHB_DIV6: ADC prescaler select CK_AHB/6 - \arg RCU_CKADC_CKAHB_DIV10: ADC prescaler select CK_AHB/10 - \arg RCU_CKADC_CKAHB_DIV20: ADC prescaler select CK_AHB/20 - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(uint32_t adc_psc) -{ - uint32_t reg0,reg1; - - /* reset the ADCPSC bits */ - reg0 = RCU_CFG0; - reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); - reg1 = RCU_CFG1; - reg1 &= ~RCU_CFG1_ADCPSC_3; - - /* set the ADC prescaler factor */ - switch(adc_psc){ - case RCU_CKADC_CKAPB2_DIV2: - case RCU_CKADC_CKAPB2_DIV4: - case RCU_CKADC_CKAPB2_DIV6: - case RCU_CKADC_CKAPB2_DIV8: - reg0 |= (adc_psc << 14); - break; - - case RCU_CKADC_CKAPB2_DIV12: - case RCU_CKADC_CKAPB2_DIV16: - adc_psc &= ~BIT(2); - reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); - break; - - case RCU_CKADC_CKAHB_DIV5: - case RCU_CKADC_CKAHB_DIV6: - case RCU_CKADC_CKAHB_DIV10: - case RCU_CKADC_CKAHB_DIV20: - adc_psc &= ~BITS(2,3); - reg0 |= (adc_psc << 14); - reg1 |= RCU_CFG1_ADCPSC_3; - break; - - default: - break; - } - - /* set the register */ - RCU_CFG0 = reg0; - RCU_CFG1 = reg1; -} - -/*! - \brief configure the USBD/USBFS prescaler factor - \param[in] adc_div: USB prescaler factor - \arg RCU_CKUSB_CKPLL_DIV1_5: USBD/USBFS prescaler select CK_PLL/1.5 - \arg RCU_CKUSB_CKPLL_DIV1: USBD/USBFS prescaler select CK_PLL/1 - \arg RCU_CKUSB_CKPLL_DIV2_5: USBD/USBFS prescaler select CK_PLL/2.5 - \arg RCU_CKUSB_CKPLL_DIV2: USBD/USBFS prescaler select CK_PLL/2 - \arg RCU_CKUSB_CKPLL_DIV3: USBD/USBFS prescaler select CK_PLL/3 - \arg RCU_CKUSB_CKPLL_DIV3_5: USBD/USBFS prescaler select CK_PLL/3.5 - \arg RCU_CKUSB_CKPLL_DIV4: USBD/USBFS prescaler select CK_PLL/4 - \param[out] none - \retval none -*/ -void rcu_usb_clock_config(uint32_t usb_psc) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* configure the USBD/USBFS prescaler factor */ -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - reg &= ~RCU_CFG0_USBDPSC; -#elif defined(GD32F30X_CL) - reg &= ~RCU_CFG0_USBFSPSC; -#endif /* GD32F30X_HD and GD32F30X_XD */ - - RCU_CFG0 = (reg | usb_psc); -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - uint32_t reg; - - reg = RCU_BDCTL; - /* reset the RTCSRC bits and set according to rtc_clock_source */ - reg &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL = (reg | rtc_clock_source); -} - -#ifdef GD32F30X_CL -/*! - \brief configure the I2S1 clock source selection - \param[in] i2s_clock_source: I2S1 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock - \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock - \param[out] none - \retval none -*/ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S1SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S1SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief configure the I2S2 clock source selection - \param[in] i2s_clock_source: I2S2 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock - \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock - \param[out] none - \retval none -*/ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S2SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S2SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} -#endif /* GD32F30X_CL */ - -/*! - \brief configure the CK48M clock source selection - \param[in] ck48m_clock_source: CK48M clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CK48MSRC_CKPLL: CK_PLL selected as CK48M source clock - \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock - \param[out] none - \retval none -*/ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) -{ - uint32_t reg; - - reg = RCU_ADDCTL; - /* reset the CK48MSEL bit and set according to ck48m_clock_source */ - reg &= ~RCU_ADDCTL_CK48MSEL; - RCU_ADDCTL = (reg | ck48m_clock_source); -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag(CL series only) - \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag(CL series only) - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval none -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag(CL series only) - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear(CL series only) - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable(CL series only) - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable(CL series only) - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief configure the LXTAL drive capability - \param[in] lxtal_dricap: drive capability of LXTAL - only one parameter can be selected which is shown as below: - \arg RCU_LXTAL_LOWDRI: lower driving capability - \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability - \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability - \arg RCU_LXTAL_HIGHDRI: higher driving capability - \param[out] none - \retval none -*/ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) -{ - uint32_t reg; - - reg = RCU_BDCTL; - - /* reset the LXTALDRI bits and set according to lxtal_dricap */ - reg &= ~RCU_BDCTL_LXTALDRI; - RCU_BDCTL = (reg | lxtal_dricap); -} - -/*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - - switch(osci){ - /* wait HXTAL stable */ - case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC48M stable */ - case RCU_IRC48M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ - reval = SUCCESS; - } - break; - -#ifdef GD32F30X_CL - /* wait PLL1 stable */ - case RCU_PLL1_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ - reval = SUCCESS; - } - break; - /* wait PLL2 stable */ - case RCU_PLL2_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ - reval = SUCCESS; - } - break; -#endif /* GD32F30X_CL */ - - default: - break; - } - - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC48M: internal 48M RC oscillators(IRC48M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1(CL series only) - \arg RCU_PLL2_CK: phase locked loop 2(CL series only) - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* enable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg | RCU_CTL_HXTALBPS); - break; - /* enable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F30X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F30X_CL */ - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* disable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); - break; - /* disable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: -#ifdef GD32F30X_CL - case RCU_PLL1_CK: - case RCU_PLL2_CK: -#endif /* GD32F30X_CL */ - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) -{ - uint32_t reg; - - reg = RCU_CTL; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - reg &= ~RCU_CTL_IRC8MADJ; - RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V - \arg RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws, ck_freq = 0U; - uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllsel, pllpresel, predv0sel, pllmf,ck_src, idx, clk_exp; -#ifdef GD32F30X_CL - uint32_t predv0, predv1, pll1mf; -#endif /* GD32F30X_CL */ - - /* exponent of AHB, APB1 and APB2 clock divider */ - uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if(RCU_PLLSRC_HXTAL_IRC48M == pllsel) { - /* PLL clock source is HXTAL or IRC48M */ - pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL); - - if(RCU_PLLPRESRC_HXTAL == pllpresel){ - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - }else{ - /* PLL clock source is IRC48 */ - ck_src = IRC48M_VALUE; - } - -#if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) - predv0sel = (RCU_CFG0 & RCU_CFG0_PREDV0); - /* PREDV0 input source clock divided by 2 */ - if(RCU_CFG0_PREDV0 == predv0sel){ - ck_src = HXTAL_VALUE/2U; - } -#elif defined(GD32F30X_CL) - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ - pll1mf = 20U; - } - ck_src = (ck_src/predv1)*pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; -#endif /* GD32F30X_HD and GD32F30X_XD */ - }else{ - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE/2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ - pllmf |= 0x10U; - } - if((RCU_CFG0 & RCU_CFG0_PLLMF_5)){ - pllmf |= 0x20U; - } - if(pllmf < 15U){ - pllmf += 2U; - }else if((pllmf >= 15U) && (pllmf <= 62U)){ - pllmf += 1U; - }else{ - pllmf = 63U; - } - cksys_freq = ck_src*pllmf; - #ifdef GD32F30X_CL - if(15U == pllmf){ - cksys_freq = ck_src*6U + ck_src/2U; - } - #endif /* GD32F30X_CL */ - - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock){ - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c deleted file mode 100644 index 25073e9470..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c +++ /dev/null @@ -1,203 +0,0 @@ -/*! - \file gd32f30x_rtc.c - \brief RTC driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_rtc.h" - -/*! - \brief enable RTC interrupt - \param[in] interrupt: specify which interrupt to enbale - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - RTC_INTEN |= interrupt; -} - -/*! - \brief disable RTC interrupt - \param[in] interrupt: specify which interrupt to disbale - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - RTC_INTEN &= ~interrupt; -} - -/*! - \brief enter RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_enter(void) -{ - RTC_CTL |= RTC_CTL_CMF; -} - -/*! - \brief exit RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_exit(void) -{ - RTC_CTL &= ~RTC_CTL_CMF; -} - -/*! - \brief wait RTC last write operation finished flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_lwoff_wait(void) -{ - /* loop until LWOFF flag is set */ - while (RESET == (RTC_CTL & RTC_CTL_LWOFF)){ - } -} - -/*! - \brief wait RTC registers synchronized flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_register_sync_wait(void) -{ - /* clear RSYNF flag */ - RTC_CTL &= ~RTC_CTL_RSYNF; - /* loop until RSYNF flag is set */ - while (RESET == (RTC_CTL & RTC_CTL_RSYNF)){ - } -} - -/*! - \brief get RTC counter value - \param[in] none - \param[out] none - \retval RTC counter value -*/ -uint32_t rtc_counter_get(void) -{ - uint32_t temp = 0x0U; - temp = RTC_CNTL; - temp |= (RTC_CNTH << 16); - return temp; -} - -/*! - \brief set RTC counter value - \param[in] cnt: RTC counter value - \param[out] none - \retval none -*/ -void rtc_counter_set(uint32_t cnt) -{ - rtc_configuration_mode_enter(); - /* set the RTC counter high bits */ - RTC_CNTH = cnt >> 16; - /* set the RTC counter low bits */ - RTC_CNTL = (cnt & RTC_LOW_VALUE); - rtc_configuration_mode_exit(); -} - -/*! - \brief set RTC prescaler value - \param[in] psc: RTC prescaler value - \param[out] none - \retval none -*/ -void rtc_prescaler_set(uint32_t psc) -{ - rtc_configuration_mode_enter(); - /* set the RTC prescaler high bits */ - RTC_PSCH = (psc & RTC_HIGH_VALUE) >> 16; - /* set the RTC prescaler low bits */ - RTC_PSCL = (psc & RTC_LOW_VALUE); - rtc_configuration_mode_exit(); -} - -/*! - \brief set RTC alarm value - \param[in] alarm: RTC alarm value - \param[out] none - \retval none -*/ -void rtc_alarm_config(uint32_t alarm) -{ - rtc_configuration_mode_enter(); - /* set the alarm high bits */ - RTC_ALRMH = alarm >> 16; - /* set the alarm low bits */ - RTC_ALRML = (alarm & RTC_LOW_VALUE); - rtc_configuration_mode_exit(); -} - -/*! - \brief get RTC divider value - \param[in] none - \param[out] none - \retval RTC divider value -*/ -uint32_t rtc_divider_get(void) -{ - uint32_t temp = 0x00U; - temp = (RTC_DIVH & RTC_DIVH_DIV) << 16; - temp |= RTC_DIVL; - return temp; -} - -/*! - \brief get RTC flag status - \param[in] flag: specify which flag status to get - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \arg RTC_FLAG_LWOF: last write operation finished flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear RTC flag status - \param[in] flag: specify which flag status to clear - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - /* clear RTC flag */ - RTC_CTL &= ~flag; -} - diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c deleted file mode 100644 index 7e10d89ba4..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c +++ /dev/null @@ -1,772 +0,0 @@ -/*! - \file gd32f30x_sdio.c - \brief SDIO driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_sdio.h" - -#define DEFAULT_RESET_VALUE 0x00000000U - -/*! - \brief deinitialize the SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_deinit(void) -{ - SDIO_PWRCTL = DEFAULT_RESET_VALUE; - SDIO_CLKCTL = DEFAULT_RESET_VALUE; - SDIO_CMDAGMT = DEFAULT_RESET_VALUE; - SDIO_CMDCTL = DEFAULT_RESET_VALUE; - SDIO_DATATO = DEFAULT_RESET_VALUE; - SDIO_DATALEN = DEFAULT_RESET_VALUE; - SDIO_DATACTL = DEFAULT_RESET_VALUE; - SDIO_INTC = DEFAULT_RESET_VALUE; - SDIO_INTEN = DEFAULT_RESET_VALUE; -} - -/*! - \brief configure the SDIO clock - \param[in] clock_edge: SDIO_CLK clock edge - \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK - \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK - \param[in] clock_bypass: clock bypass - \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass - \arg SDIO_CLOCKBYPASS_DISABLE: no bypass - \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving - \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle - \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on - \param[in] clock_division: clock division, less than 512 - \param[out] none - \retval none -*/ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) -{ - uint32_t clock_config = 0U; - clock_config = SDIO_CLKCTL; - /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ - clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); - /* if the clock division is greater or equal to 256, set the DIV[8] */ - if(clock_division >= 256U){ - clock_config |= SDIO_CLKCTL_DIV8; - clock_division -= 256U; - } - /* configure the SDIO_CLKCTL according to the parameters */ - clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); - SDIO_CLKCTL = clock_config; -} - -/*! - \brief enable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief disable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief set different SDIO card bus mode - \param[in] bus_mode: SDIO card bus mode - \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode - \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode - \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode - \param[out] none - \retval none -*/ -void sdio_bus_mode_set(uint32_t bus_mode) -{ - /* reset the SDIO card bus mode bits and set according to bus_mode */ - SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; - SDIO_CLKCTL |= bus_mode; -} - -/*! - \brief set the SDIO power state - \param[in] power_state: SDIO power state - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off - \param[out] none - \retval none -*/ -void sdio_power_state_set(uint32_t power_state) -{ - SDIO_PWRCTL = power_state; -} - -/*! - \brief get the SDIO power state - \param[in] none - \param[out] none - \retval SDIO power state - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off -*/ -uint32_t sdio_power_state_get(void) -{ - return SDIO_PWRCTL; -} - -/*! - \brief enable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; -} - -/*! - \brief disable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; -} - -/*! - \brief configure the command and response - \param[in] cmd_index: command index, refer to the related specifications - \param[in] cmd_argument: command argument, refer to the related specifications - \param[in] response_type: response type - \arg SDIO_RESPONSETYPE_NO: no response - \arg SDIO_RESPONSETYPE_SHORT: short response - \arg SDIO_RESPONSETYPE_LONG: long response - \param[out] none - \retval none -*/ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) -{ - uint32_t cmd_config = 0U; - /* reset the command index, command argument and response type */ - SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; - SDIO_CMDAGMT = cmd_argument; - cmd_config = SDIO_CMDCTL; - cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); - /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ - cmd_config |= (cmd_index | response_type); - SDIO_CMDCTL = cmd_config; -} - -/*! - \brief set the command state machine wait type - \param[in] wait_type: wait type - \arg SDIO_WAITTYPE_NO: not wait interrupt - \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt - \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer - \param[out] none - \retval none -*/ -void sdio_wait_type_set(uint32_t wait_type) -{ - /* reset INTWAIT and WAITDEND */ - SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); - /* set the wait type according to wait_type */ - SDIO_CMDCTL |= wait_type; -} - -/*! - \brief enable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; -} - -/*! - \brief disable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; -} - -/*! - \brief get the last response command index - \param[in] none - \param[out] none - \retval last response command index -*/ -uint8_t sdio_command_index_get(void) -{ - return (uint8_t)SDIO_RSPCMDIDX; -} - -/*! - \brief get the response for the last received command - \param[in] responsex: SDIO response - \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] - \arg SDIO_RESPONSE1: card response[95:64] - \arg SDIO_RESPONSE2: card response[63:32] - \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 - \param[out] none - \retval response for the last received command -*/ -uint32_t sdio_response_get(uint32_t responsex) -{ - uint32_t resp_content = 0U; - switch(responsex){ - case SDIO_RESPONSE0: - resp_content = SDIO_RESP0; - break; - case SDIO_RESPONSE1: - resp_content = SDIO_RESP1; - break; - case SDIO_RESPONSE2: - resp_content = SDIO_RESP2; - break; - case SDIO_RESPONSE3: - resp_content = SDIO_RESP3; - break; - default: - break; - } - return resp_content; -} - -/*! - \brief configure the data timeout, data length and data block size - \param[in] data_timeout: data timeout period in card bus clock periods - \param[in] data_length: number of data bytes to be transferred - \param[in] data_blocksize: size of data block for block transfer - \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte - \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes - \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes - \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes - \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes - \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes - \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes - \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes - \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes - \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes - \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes - \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes - \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes - \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes - \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes - \param[out] none - \retval none -*/ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) -{ - /* reset data timeout, data length and data block size */ - SDIO_DATATO &= ~SDIO_DATATO_DATATO; - SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; - SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; - /* configure the related parameters of data */ - SDIO_DATATO = data_timeout; - SDIO_DATALEN = data_length; - SDIO_DATACTL |= data_blocksize; -} - -/*! - \brief configure the data transfer mode and direction - \param[in] transfer_mode: mode of data transfer - \arg SDIO_TRANSMODE_BLOCK: block transfer - \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer - \param[in] transfer_direction: data transfer direction, read or write - \arg SDIO_TRANSDIRECTION_TOCARD: write data to card - \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card - \param[out] none - \retval none -*/ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) -{ - uint32_t data_trans = 0U; - /* reset the data transfer mode, transfer direction and set according to the parameters */ - data_trans = SDIO_DATACTL; - data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); - data_trans |= (transfer_mode | transfer_direction); - SDIO_DATACTL = data_trans; -} - -/*! - \brief enable the DSM(data state machine) for data transfer - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DATAEN; -} - -/*! - \brief disable the DSM(data state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; -} - -/*! - \brief write data(one word) to the transmit FIFO - \param[in] data: 32-bit data write to card - \param[out] none - \retval none -*/ -void sdio_data_write(uint32_t data) -{ - SDIO_FIFO = data; -} - -/*! - \brief read data(one word) from the receive FIFO - \param[in] none - \param[out] none - \retval received data -*/ -uint32_t sdio_data_read(void) -{ - return SDIO_FIFO; -} - -/*! - \brief get the number of remaining data bytes to be transferred to card - \param[in] none - \param[out] none - \retval number of remaining data bytes to be transferred -*/ -uint32_t sdio_data_counter_get(void) -{ - return SDIO_DATACNT; -} - -/*! - \brief get the number of words remaining to be written or read from FIFO - \param[in] none - \param[out] none - \retval remaining number of words -*/ -uint32_t sdio_fifo_counter_get(void) -{ - return SDIO_FIFOCNT; -} - -/*! - \brief enable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DMAEN; -} - -/*! - \brief disable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; -} - -/*! - \brief get the flags state of SDIO - \param[in] flag: flags state of SDIO - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_CMDRUN: command transmission in progress flag - \arg SDIO_FLAG_TXRUN: data transmission in progress flag - \arg SDIO_FLAG_RXRUN: data reception in progress flag - \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO - \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO - \arg SDIO_FLAG_TFF: transmit FIFO is full flag - \arg SDIO_FLAG_RFF: receive FIFO is full flag - \arg SDIO_FLAG_TFE: transmit FIFO is empty flag - \arg SDIO_FLAG_RFE: receive FIFO is empty flag - \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag - \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_flag_get(uint32_t flag) -{ - FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & flag)){ - temp_flag = SET; - } - return temp_flag; -} - -/*! - \brief clear the pending flags of SDIO - \param[in] flag: flags state of SDIO - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_flag_clear(uint32_t flag) -{ - SDIO_INTC = flag; -} - -/*! - \brief enable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_enable(uint32_t int_flag) -{ - SDIO_INTEN |= int_flag; -} - -/*! - \brief disable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_disable(uint32_t int_flag) -{ - SDIO_INTEN &= ~int_flag; -} - -/*! - \brief get the interrupt flags state of SDIO - \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt - \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt - \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt - \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt - \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt - \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt - \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) -{ - uint32_t state = 0U; - state = SDIO_STAT; - if(state & int_flag){ - state = SDIO_INTEN; - /* check whether the corresponding bit in SDIO_INTEN is set or not */ - if(state & int_flag){ - return SET; - } - } - return RESET; -} - -/*! - \brief clear the interrupt pending flags of SDIO - \param[in] int_flag: interrupt flags state of SDIO - \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag - \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_interrupt_flag_clear(uint32_t int_flag) -{ - SDIO_INTC = int_flag; -} - -/*! - \brief enable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWEN; -} - -/*! - \brief disable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; -} - -/*! - \brief enable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; -} - -/*! - \brief disable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; -} - -/*! - \brief set the read wait type(SD I/O only) - \param[in] readwait_type: SD I/O read wait type - \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK - \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] - \param[out] none - \retval none -*/ -void sdio_readwait_type_set(uint32_t readwait_type) -{ - if(SDIO_READWAITTYPE_CLK == readwait_type){ - SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; - }else{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; - } -} - -/*! - \brief enable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_IOEN; -} - -/*! - \brief disable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; -} - -/*! - \brief enable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief disable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief enable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; -} - -/*! - \brief disable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; -} - -/*! - \brief enable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_enable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; -} - -/*! - \brief disable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_disable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; -} - -/*! - \brief enable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; -} - -/*! - \brief disable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c deleted file mode 100644 index ef589e6134..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c +++ /dev/null @@ -1,792 +0,0 @@ -/*! - \file gd32f30x_spi.c - \brief SPI driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_spi.h" - -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ -#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ -#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ -#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph){ - case SPI0: - /* reset SPI0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 and I2S1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - case SPI2: - /* reset SPI2 and I2S2 */ - rcu_periph_reset_enable(RCU_SPI2RST); - rcu_periph_reset_disable(RCU_SPI2RST); - break; - default : - break; - } -} - -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval none -*/ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ - uint32_t reg = 0U; - reg = SPI_CTL0(spi_periph); - reg &= SPI_INIT_MASK; - - /* select SPI as master or slave */ - reg |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg |= spi_struct->trans_mode; - /* select SPI frame size */ - reg |= spi_struct->frame_size; - /* select SPI NSS use hardware or software */ - reg |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg |= spi_struct->endian; - /* select SPI polarity and phase */ - reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg |= spi_struct->prescale; - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg; - - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPIx(x=1,2) - \param[in] audiosample: I2S audio sample rate - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - -#ifdef GD32F30X_CL - uint32_t pll2mf_4 = 0U; -#endif /* GD32F30X_CL */ - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = 0x0002U; - -#ifdef GD32F30X_CL - /* get the I2S clock source */ - if(((uint32_t)spi_periph) == SPI1){ - /* I2S1 clock source selection */ - clks = I2S1_CLOCK_SEL; - }else{ - /* I2S2 clock source selection */ - clks = I2S2_CLOCK_SEL; - } - - if(0U != (RCU_CFG1 & clks)){ - /* get RCU PLL2 clock multiplication factor */ - clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> 12U); - - pll2mf_4 = RCU_CFG1 & RCU_CFG1_PLL2MF_4; - - if( 0U == pll2mf_4){ - if((clks > 5U) && (clks < 15U)){ - /* multiplier is between 8 and 16 */ - clks += 2U; - }else{ - if(15U == clks){ - /* multiplier is 20 */ - clks = 20U; - } - } - }else{ - if(clks < 15U){ - /* multiplier is between 18 and 32 */ - clks += 18U; - }else{ - if(15U == clks){ - /* multiplier is 40 */ - clks = 40U; - } - } - } - - /* get the PREDV1 value */ - i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> 4U) + 1U); - /* calculate i2sclock based on PLL2 and PREDV1 */ - i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); - }else{ - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - } -#else - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); -#endif /* GD32F30X_CL */ - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout){ - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)){ - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPIx(x=1,2) - \param[in] mode: I2S operation mode - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - \arg I2S_STD_PHILLIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg= 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA - \arg SPI_DMA_RECEIVE: SPI receive data use DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA - \arg SPI_DMA_RECEIVE: SPI receive data use DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] frame_format: SPI frame size - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \param[out] none - \retval none -*/ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* confige SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= (uint32_t)frame_format; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - SPI_DATA(spi_periph) = (uint32_t)data; -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - return ((uint16_t)SPI_DATA(spi_periph)); -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] transfer_direction: SPI transfer direction - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt flag status - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI/I2S format error interrupt */ - case SPI_I2S_INT_FLAG_FERR: - reg1 = reg1 & SPI_STAT_FERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - /*get SPI/I2S interrupt flag status */ - if(reg1 && reg2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] flag: SPI/I2S flag status - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(SPI_STAT(spi_periph) & flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief set CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc: SPI crc value - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc) -{ - if(SPI_CRC_TX == crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - -/*! - \brief enable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nssp_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; -} - -/*! - \brief disable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nssp_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); -} - -/*! - \brief enable quad wire SPI - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; -} - -/*! - \brief disable quad wire SPI - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); -} - -/*! - \brief enable quad wire SPI write - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_write_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); -} - -/*! - \brief enable quad wire SPI read - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_read_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; -} - -/*! - \brief enable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ -void qspi_io23_output_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; -} - - /*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=0) - \param[out] none - \retval none -*/ - void qspi_io23_output_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c deleted file mode 100644 index 14daaafe96..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c +++ /dev/null @@ -1,1872 +0,0 @@ -/*! - \file gd32f30x_timer.c - \brief TIMER driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.2, firmware for GD32F30x -*/ - -#include "gd32f30x_timer.h" - -/*! - \brief deinit a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph){ - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER1: - /* reset TIMER1 */ - rcu_periph_reset_enable(RCU_TIMER1RST); - rcu_periph_reset_disable(RCU_TIMER1RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER3: - /* reset TIMER3 */ - rcu_periph_reset_enable(RCU_TIMER3RST); - rcu_periph_reset_disable(RCU_TIMER3RST); - break; - case TIMER4: - /* reset TIMER4 */ - rcu_periph_reset_enable(RCU_TIMER4RST); - rcu_periph_reset_disable(RCU_TIMER4RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER6: - /* reset TIMER6 */ - rcu_periph_reset_enable(RCU_TIMER6RST); - rcu_periph_reset_disable(RCU_TIMER6RST); - break; - case TIMER7: - /* reset TIMER7 */ - rcu_periph_reset_enable(RCU_TIMER7RST); - rcu_periph_reset_disable(RCU_TIMER7RST); - break; -#ifndef GD32F30X_HD - case TIMER8: - /* reset TIMER8 */ - rcu_periph_reset_enable(RCU_TIMER8RST); - rcu_periph_reset_disable(RCU_TIMER8RST); - break; - case TIMER9: - /* reset TIMER9 */ - rcu_periph_reset_enable(RCU_TIMER9RST); - rcu_periph_reset_disable(RCU_TIMER9RST); - break; - case TIMER10: - /* reset TIMER10 */ - rcu_periph_reset_enable(RCU_TIMER10RST); - rcu_periph_reset_disable(RCU_TIMER10RST); - break; - case TIMER11: - /* reset TIMER11 */ - rcu_periph_reset_enable(RCU_TIMER11RST); - rcu_periph_reset_disable(RCU_TIMER11RST); - break; - case TIMER12: - /* reset TIMER12 */ - rcu_periph_reset_enable(RCU_TIMER12RST); - rcu_periph_reset_disable(RCU_TIMER12RST); - break; - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; -#endif /* GD32F30X_HD */ - default: - break; - } -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock,0~65535 - alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN - period: counter auto reload value - clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) - || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; - } - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] aligned: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph,uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] prescaler: prescaler value - \param[in] pscreload: prescaler reload mode - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint8_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] repetition: the counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] autoreload: the counter auto-reload value - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] counter: the counter value - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph , uint32_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0..8,11) - \param[in] spmode: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph,uint8_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] update: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph,uint8_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(update == TIMER_UPDATE_SRC_GLOBAL){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ - } -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source enable - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph,uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t interrupt) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph , uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph , uint32_t flag) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)flag); -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: TIMERx(x=0,1,2,5,14,15,16) - \param[in] dma: timer DMA source enable - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph,uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: timer DMA source enable - \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA enable,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request enable,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA enable,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph,uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] dma_request: channel DMA request source selection - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: please refer to the following parameters - \param[in] dma_baseaddr: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) - \param[in] dma_lenth: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: please refer to the following parameters - \param[in] event: the timer software event generation sources - \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph,uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph,timer_break_parameter_struct* breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| - ((uint32_t)(breakpara->ideloffstate))| - ((uint32_t)(breakpara->deadtime))| - ((uint32_t)(breakpara->breakpolarity))| - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode))| - ((uint32_t)(breakpara->breakstate))) ; -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief configure TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief channel capture/compare control shadow register enable - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] ccuctl: channel control shadow register update control - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl){ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - } -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct* ocpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 4U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 2U); - } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 8U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate)<< 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity)<< 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate)<< 4U); - } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate<< 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity)<< 12U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate)<< 6U); - } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocmode: channel output compare mode - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode)<< 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] pulse: channel output pulse value - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse) -{ - switch(channel){ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocshadow: channel output shadow state - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocfast: channel output fast function - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph,uint16_t channel,uint16_t ocfast) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \arg TIMER_CH_3: TIMER channel3 - \param[in] occlear: channel output clear function - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocpolarity: channel output polarity - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7)) - \param[in] ocnpolarity: channel complementary output polarity - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] state: TIMER channel enable state - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,7)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,7)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,7)) - \param[in] ocnstate: TIMER channel complementary output enable state - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct* icpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity)<< 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)<< 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter)<< 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,channel,(uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] prescaler: channel input capture prescaler value - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel){ - case TIMER_CH_0: - count_value = TIMER_CH0CV(timer_periph); - break; - case TIMER_CH_1: - count_value = TIMER_CH1CV(timer_periph); - break; - case TIMER_CH_2: - count_value = TIMER_CH2CV(timer_periph); - break; - case TIMER_CH_3: - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] channel: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct* icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ - icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ - icpolarity = TIMER_IC_POLARITY_RISING; - } - - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ - icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel){ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity)<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection)<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter)<< 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] hallmode: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph,uint8_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 Edge Detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0..7) - \param[in] outrigger: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output - \arg TIMER_TRI_OUT_SRC_CC0: a capture or a compare match occurred in channal0 as trigger output TRGO - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] slavemode: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] masterslave: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph,uint8_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler, - uint32_t expolarity,uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP|TIMER_SMCFG_ETPSC|TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler|expolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter<< 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] decomode: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode, - uint16_t ic0polarity,uint16_t ic1polarity) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U)); - - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity<< 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph,intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extrigger: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] expolarity: - \arg TIMER_IC_POLARITY_RISING: active low or falling edge active - \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger, - uint16_t expolarity,uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)expolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI<< 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter<< 8U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)expolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extprescaler: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler, - uint32_t expolarity,uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter); - - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] expolarity: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler, - uint32_t expolarity,uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph,extprescaler,expolarity,extfilter); - - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief configure TIMER write CHxVAL register selection - \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) - \param[in] ccsel: - \arg TIMER_CCSEL_DISABLE: no effect - \arg TIMER_CCSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored - \param[out] none - \retval none -*/ -void timer_write_cc_register_config(uint32_t timer_periph, uint16_t ccsel) -{ - if(TIMER_CCSEL_ENABLE == ccsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CCSEL_DISABLE == ccsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - }else{ - } -} - -/*! - \brief configure TIMER output value selection - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] outsel: - \arg TIMER_OUTSEL_DISABLE: no effect - \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled - \param[out] none - \retval none -*/ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) -{ - if(TIMER_OUTSEL_ENABLE == outsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == outsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - }else{ - } -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c deleted file mode 100644 index 16ddbcbfe7..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c +++ /dev/null @@ -1,841 +0,0 @@ -/*! - \file gd32f30x_usart.c - \brief USART driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.1, firmware for GD32F30x -*/ - -#include "gd32f30x_usart.h" - -/*! - \brief reset USART/UART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph){ - case USART0: - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - case USART2: - rcu_periph_reset_enable(RCU_USART2RST); - rcu_periph_reset_disable(RCU_USART2RST); - break; - case UART3: - rcu_periph_reset_enable(RCU_UART3RST); - rcu_periph_reset_disable(RCU_UART3RST); - break; - case UART4: - rcu_periph_reset_enable(RCU_UART4RST); - rcu_periph_reset_disable(RCU_UART4RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ - case USART0: - uclk=rcu_clock_freq_get(CK_APB2); - break; - case USART1: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case USART2: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART3: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART4: - uclk=rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; - intdiv = udiv & 0xfff0U; - fradiv = udiv & 0xfU; - USART_BAUD(usart_periph) |= ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] paritycfg: configure USART parity - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg ; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wlen: USART word length configure - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] stblen: USART stop bit configure - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - /* configure USART stop bits */ - USART_CTL1(usart_periph) |= stblen; -} -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] txconfig: enable or disable USART transmitter - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_TEN; - ctl |= txconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] rxconfig: enable or disable USART receiver - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_REN; - ctl |= rxconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief data is transmitted/received with the LSB/MSB first - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] msbf: LSB/MSB - \arg USART_MSBF_LSB: LSB first - \arg USART_MSBF_MSB: MSB first - \param[out] none - \retval none -*/ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) -{ - USART_CTL3(usart_periph) &= ~(USART_CTL3_MSBF); - USART_CTL3(usart_periph) |= msbf; -} - -/*! - \brief configure USART inversion - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] invertpara: refer to enum USART_INVERT_CONFIG - \arg USART_DINV_ENABLE: data bit level inversion - \arg USART_DINV_DISABLE: data bit level not inversion - \arg USART_TXPIN_ENABLE: TX pin level inversion - \arg USART_TXPIN_DISABLE: TX pin level not inversion - \arg USART_RXPIN_ENABLE: RX pin level inversion - \arg USART_RXPIN_DISABLE: RX pin level not inversion - \param[out] none - \retval none -*/ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) -{ - /* inverted or not the specified siginal */ - switch(invertpara){ - case USART_DINV_ENABLE: - USART_CTL3(usart_periph) |= USART_CTL3_DINV; - break; - case USART_TXPIN_ENABLE: - USART_CTL3(usart_periph) |= USART_CTL3_TINV; - break; - case USART_RXPIN_ENABLE: - USART_CTL3(usart_periph) |= USART_CTL3_RINV; - break; - case USART_DINV_DISABLE: - USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); - break; - case USART_TXPIN_DISABLE: - USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); - break; - case USART_RXPIN_DISABLE: - USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); - break; - default: - break; - } -} - -/*! - \brief enable receiver timeout of USART - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_enable(uint32_t usart_periph) -{ - USART_CTL3(usart_periph) |= USART_CTL3_RTEN; -} - -/*! - \brief disable receiver timeout of USART - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_disable(uint32_t usart_periph) -{ - USART_CTL3(usart_periph) &= ~(USART_CTL3_RTEN); -} - -/*! - \brief set the receiver timeout threshold of USART - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] rtimeout: 0-0xFFFFFF - \param[out] none - \retval none -*/ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) -{ - USART_RT(usart_periph) &= ~(USART_RT_RT); - USART_RT(usart_periph) |= rtimeout; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); -} - -/*! - \brief configure the address of the USART in wake up by address match mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] addr: address of USART/UART - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); -} - -/*! - \brief receiver in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_RWU; -} - -/*! - \brief receiver in active mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wmethod: two methods be used to enter or exit the mute mode - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mask - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief configure lin break frame length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] lblen: lin break frame length - \arg USART_LBLEN_10B: 10 bits - \arg USART_LBLEN_11B: 11 bits - \param[out] none - \retval none -*/ -void usart_lin_break_dection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); -} - -/*! - \brief send break frame - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_send_break(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; -} - -/*! - \brief enable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] clen: CK length - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame - \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame - \param[in] cph: clock phase - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) |= ctl; -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] guat: guard time value - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) -{ - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)<<8)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief configure smartcard auto-retry number - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] scrtnum: smartcard auto-retry number - \param[out] none - \retval none -*/ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) -{ - USART_CTL3(usart_periph) &= ~(USART_CTL3_SCRTNUM); - USART_CTL3(usart_periph) |= (USART_CTL3_SCRTNUM & ((scrtnum)<<1)); -} - -/*! - \brief configure block length in Smartcard T=1 reception - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] bl: block length - \param[out] none - \retval none -*/ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl) -{ - USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl)<<24)); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] psc: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) -{ - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] irlp: IrDA low-power or normal - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] hardwareflow: enable or disable RTS - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_RTSEN; - ctl |= rtsconfig; - /* configure RTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] hardwareflow: enable or disable CTS - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_CTSEN; - ctl |= ctsconfig; - /* configure CTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for reception - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENR; - ctl |= dmacmd; - /* configure DMA reception */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for transmission - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENT; - ctl |= dmacmd; - /* configure DMA transmission */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief get flag in STAT0/STAT1 register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one among these parameters can be selected - \arg USART_FLAG_CTS: CTS change flag - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_TBE: transmit data buffer empty - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_IDLE: IDLE frame detected flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_BSY: busy flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_RT: receiver timeout flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag in STAT0/STAT1 register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one among these parameters can be selected - \arg USART_FLAG_CTS: CTS change flag - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_RT: receiver timeout flag - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one among these parameters can be selected - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_RT: interrupt enable bit of receive timeout event - \arg USART_INT_EB: interrupt enable bit of end of block event - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one among these parameters can be selected - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_RT: interrupt enable bit of receive timeout event - \arg USART_INT_EB: interrupt enable bit of end of block event - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - \arg USART_INT_FLAG_PERR: parity error interrupt and flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag - \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag - \arg USART_INT_FLAG_EB: interrupt enable bit of end of block event and flag - \arg USART_INT_FLAG_RT: interrupt enable bit of receive timeout event and flag - \param[out] none - \retval FlagStatus -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if(flagstatus && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART interrupt flag in STAT0/STAT1 register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART interrupt flag - \arg USART_INT_FLAG_CTS: CTS change flag - \arg USART_INT_FLAG_LBD: LIN break detected flag - \arg USART_INT_FLAG_TC: transmission complete - \arg USART_INT_FLAG_RBNE: read data buffer not empty - \arg USART_INT_FLAG_EB: end of block flag - \arg USART_INT_FLAG_RT: receiver timeout flag - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) -{ - USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c b/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c deleted file mode 100644 index 4595a36a1e..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c +++ /dev/null @@ -1,122 +0,0 @@ -/*! - \file gd32f30x_wwdgt.c - \brief WWDGT driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "gd32f30x_wwdgt.h" - -/* write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -/* write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00 - 0x7F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F - \param[in] window: 0x00 - 0x7F - \param[in] prescaler: wwdgt prescaler value - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - uint32_t reg_cfg = 0U, reg_ctl = 0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); - reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= CFG_WIN(window); - reg_cfg |= prescaler; - reg_ctl |= CTL_CNT(counter); - - WWDGT_CTL = reg_ctl; - WWDGT_CFG = reg_cfg; -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if(WWDGT_STAT & WWDGT_STAT_EWIF){ - return SET; - } - - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (~WWDGT_STAT_EWIF); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_core.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_core.h deleted file mode 100644 index 91c40c9f4a..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_core.h +++ /dev/null @@ -1,191 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device driver core -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usbd_regs.h" - -/* interrupt flag mask which decide what event should be handled by application */ -#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ - | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE) - -#ifdef LPM_ENABLED -#undef IER_MASK - -#define IER_MASK (CTL_STIE | CTL_WKUPIE | CTL_SPSIE \ - | CTL_SOFIE | CTL_ESOFIE | CTL_RSTIE | CTL_L1REQIE) -#endif /* LPM_ENABLED */ - -/* USB device endpoint0 max packet size */ -#define USBD_EP0_MAX_SIZE 64U - -#define USBD_CONTRL_STATUS_TX() do \ -{ \ - pbuf_reg->tx_count = 0U; \ - USBD_ENDP_TX_STATUS_SET(EP0, EPTX_VALID); \ -} while(0) - -#define USBD_CONTRL_STATUS_RX() do \ -{ \ - USBD_STATUS_OUT_SET(EP0); \ - USBD_ENDP_RX_STATUS_SET(EP0, EPRX_VALID); \ -} while(0) - -#define ENDP_BUF_ADDR (sizeof(usbd_ep_buf_struct) * EP_COUNT) - -/* USB device endpoint type */ -typedef enum -{ - ENDP_CONTROL = 0, /*!< control endpoint type value */ - ENDP_ISOC, /*!< isochronous endpoint type value */ - ENDP_BULK, /*!< bulk endpoint type value */ - ENDP_INT /*!< interupt endpoint type value */ -}usbd_eptype_enum; - -/* USB device endpoint kind */ -typedef enum -{ - ENDP_SNG_BUF = 0, /*!< single buffer endpoint type value */ - ENDP_DBL_BUF /*!< double buffer endpoint type value */ -}usbd_epkind_enum; - -/* transfer direction */ -typedef enum -{ - USBD_RX = 0, /*!< receive direction type value */ - USBD_TX /*!< transmit direction type value */ -}usbd_dir_enum; - -/* USB device status */ -typedef enum -{ - USBD_UNCONNECTED = 0, /*!< USB device unconnected status */ - USBD_DEFAULT, /*!< USB device default status */ - USBD_ADDRESSED, /*!< USB device addressed status */ - USBD_CONFIGURED, /*!< USB device configured status */ - USBD_SUSPENDED, /*!< USB device suspended status */ - USBD_CONNECTED /*!< USB device connected status */ -}usbd_run_status_enum; - -/* USB device operation state */ -typedef enum -{ - USBD_OK = 0, /*!< USB device ok */ - USBD_BUSY, /*!< USB device busy */ - USBD_FAIL /*!< USB device fail */ -}usbd_status_enum; - -typedef struct -{ - uint16_t tx_addr; /*!< transmission address */ - uint16_t reserved0; - uint16_t tx_count; /*!< transmission count */ - uint16_t reserved1; - uint16_t rx_addr; /*!< reception address */ - uint16_t reserved2; - uint16_t rx_count; /*!< reception count */ - uint16_t reserved3; -}usbd_ep_buf_struct; - -/* USB endpoint structure */ -typedef struct -{ - /* basic parameters */ - uint8_t stall; /*!< endpoint stall status */ - uint32_t maxpacket; /*!< the maxpacket of the endpoint */ - - /* transaction level parameters */ - uint8_t *trs_buf; /*!< transaction buffer address */ - uint32_t trs_len; /*!< transaction buffer length */ - uint32_t trs_count; /*!< transaction data counts */ -}usb_ep_struct; - -/* USB standard device request structure */ -typedef struct -{ - uint8_t bmRequestType; /*!< the property of the request */ - uint8_t bRequest; /*!< the code of the request */ - uint16_t wValue; /*!< the value of the request which used to choose the different request in the same code request */ - uint16_t wIndex; /*!< USB standard device request index */ - uint16_t wLength; /*!< the return datas length that the host wants to get */ -}usb_device_req_struct; - -/* USB core driver struct */ -typedef struct -{ - /* basic parameters */ - uint8_t config_num; /*!< the number of the USB device configuration */ - uint8_t status; /*!< USB device status */ - uint8_t prev_status; /*!< the previous USB device status */ - uint8_t remote_wakeup; /*!< the flag that point out the device whether support the - remte wakeup function */ - - /* the parameters which needs in control transfer */ - uint8_t setup_packet[8]; /*!< the buffer used to store the setup packet */ - uint32_t ctl_count; /*!< the datas length of control transfer request */ - - /* device endpoints */ - usb_ep_struct in_ep[EP_COUNT]; /*!< the IN direction endpoints */ - usb_ep_struct out_ep[EP_COUNT]; /*!< the OUT direction endpoints */ - -#ifdef LPM_ENABLED - uint8_t *bos_desc; /*!< BOS descriptor */ -#endif /* LPM_ENABLED */ - - uint8_t *dev_desc; /*!< device descriptor */ - uint8_t *config_desc; /*!< configuration descriptor */ - void* const *strings; /*!< configuration strings */ - - /* device class handler */ - usbd_status_enum (*class_init) (void *pudev, uint8_t config_index); - usbd_status_enum (*class_deinit) (void *pudev, uint8_t config_index); - usbd_status_enum (*class_req_handler) (void *pudev, usb_device_req_struct *req); - usbd_status_enum (*class_data_handler) (void *pudev, usbd_dir_enum rx_tx, uint8_t ep_num); -}usbd_core_handle_struct; - -extern uint32_t g_free_buf_addr; -extern usbd_ep_buf_struct *pbuf_reg; - -/* function declarations */ -/* device core register initialization */ -void usbd_core_init (usbd_core_handle_struct *pudev); -/* device core register configure when stop device */ -void usbd_core_deinit (void); - -/* free buffer used from application by toggling the SW_BUF byte */ -void user_buffer_free (uint8_t ep_num, uint8_t dir); - -/* endpoint initialization */ -void usbd_ep_init (usbd_core_handle_struct *pudev, void *pep_desc); -/* configure the endpoint when it is disabled */ -void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* set an endpoint to STALL status */ -void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr); -/* write datas from user fifo to USBRAM */ -void usbd_ep_data_write (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); -/* read datas from USBRAM to user fifo */ -void usbd_ep_data_read (uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes); - -/* get the endpoint status */ -uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr); - -/* get the received data length */ -uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_int.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_int.h deleted file mode 100644 index 920f96e0f0..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_int.h +++ /dev/null @@ -1,32 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device interrupt handler header file -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" -#include "usbd_std.h" -#include "usbd_pwr.h" - -extern usbd_core_handle_struct usb_device_dev; - -typedef struct -{ - uint8_t (*SOF) (usbd_core_handle_struct *pudev); /*!< SOF ISR callback */ -}usbd_int_cb_struct; - -extern usbd_int_cb_struct *usbd_int_fops; - -/* function declarations */ -/* USB device interrupt service routine */ -void usbd_isr (void); - -#endif /* USBD_INT_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_pwr.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_pwr.h deleted file mode 100644 index 9d885a6cb9..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_pwr.h +++ /dev/null @@ -1,25 +0,0 @@ -/*! - \file usbd_pwr.h - \brief USB device power management functions prototype -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBD_PWR_H -#define USBD_PWR_H - -#include "usbd_core.h" - -/* function declarations */ -/* USB wakeup first operation is to wakeup mcu */ -void resume_mcu (void); -/* set USB device to suspend mode */ -void usbd_suspend (void); -/* start to remote wakeup */ -void usbd_remote_wakeup_active (void); - -#endif /* USBD_PWR_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_regs.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_regs.h deleted file mode 100644 index 30c6737bc8..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_regs.h +++ /dev/null @@ -1,270 +0,0 @@ -/*! - \file usbd_regs.h - \brief USB device registers -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBD_REGS_H -#define USBD_REGS_H - -#include "usbd_conf.h" - -/* USB device registers base address */ -#define USBD USBD_BASE -#define USBD_RAM (APB1_BUS_BASE + 0x00006000U) - -/* registers definitions */ -/* common registers */ -#define USBD_CTL (REG32(USBD + 0x40U)) /*!< control register */ -#define USBD_INTF (REG32(USBD + 0x44U)) /*!< interrupt flag register */ -#define USBD_STAT (REG32(USBD + 0x48U)) /*!< status register */ -#define USBD_DADDR (REG32(USBD + 0x4CU)) /*!< device address register */ -#define USBD_BADDR (REG32(USBD + 0x50U)) /*!< buffer address register */ - -/* endpoint control and status register */ -#define USBD_EPxCS(ep_id) (REG32(USBD + (ep_id) * 4U)) /*!< endpoint x control and status register address */ - -/* LPM Registers */ -#define USBD_LPMCS (REG32(USBD + 0x54U)) /*!< USBD LPM control and status register */ - -/* bits definitions */ -/* USBD_CTL */ -#define CTL_STIE BIT(15) /*!< successful transfer interrupt enable mask */ -#define CTL_PMOUIE BIT(14) /*!< packet memory overrun/underrun interrupt enable mask */ -#define CTL_ERRIE BIT(13) /*!< error interrupt enable mask */ -#define CTL_WKUPIE BIT(12) /*!< wakeup interrupt enable mask */ -#define CTL_SPSIE BIT(11) /*!< suspend state interrupt enable mask */ -#define CTL_RSTIE BIT(10) /*!< reset interrupt enable mask */ -#define CTL_SOFIE BIT(9) /*!< start of frame interrupt enable mask */ -#define CTL_ESOFIE BIT(8) /*!< expected start of frame interrupt enable mask */ -#define CTL_L1REQIE BIT(7) /*!< LPM L1 state request interrupt enable */ -#define CTL_L1RSREQ BIT(5) /*!< LPM L1 resume request */ -#define CTL_RSREQ BIT(4) /*!< resume request */ -#define CTL_SETSPS BIT(3) /*!< set suspend state */ -#define CTL_LOWM BIT(2) /*!< low-power mode at suspend state */ -#define CTL_CLOSE BIT(1) /*!< goes to close state */ -#define CTL_SETRST BIT(0) /*!< set USB reset */ - -/* USBD_INTF */ -#define INTF_STIF BIT(15) /*!< successful transfer interrupt flag (read only bit) */ -#define INTF_PMOUIF BIT(14) /*!< packet memory overrun/underrun interrupt flag (clear-only bit) */ -#define INTF_ERRIF BIT(13) /*!< error interrupt flag (clear-only bit) */ -#define INTF_WKUPIF BIT(12) /*!< wakeup interrupt flag (clear-only bit) */ -#define INTF_SPSIF BIT(11) /*!< suspend state interrupt flag (clear-only bit) */ -#define INTF_RSTIF BIT(10) /*!< reset interrupt flag (clear-only bit) */ -#define INTF_SOFIF BIT(9) /*!< start of frame interrupt flag (clear-only bit) */ -#define INTF_ESOFIF BIT(8) /*!< expected start of frame interrupt flag(clear-only bit) */ -#define INTF_L1REQ BIT(7) /*!< LPM L1 transaction is successfully received and acknowledged */ -#define INTF_DIR BIT(4) /*!< direction of transaction (read-only bit) */ -#define INTF_EPNUM BITS(0, 3) /*!< endpoint number (read-only bit) */ - -/* USBD_STAT */ -#define STAT_RXDP BIT(15) /*!< data plus line status */ -#define STAT_RXDM BIT(14) /*!< data minus line status */ -#define STAT_LOCK BIT(13) /*!< locked the USB */ -#define STAT_SOFLN BITS(11, 12) /*!< SOF lost number */ -#define STAT_FCNT BITS(0, 10) /*!< frame number count */ - -/* USBD_DADDR */ -#define DADDR_USBEN BIT(7) /*!< USB module enable */ -#define DADDR_USBDAR BITS(0, 6) /*!< USB device address */ - -/* USBD_EPxCS */ -#define EPxCS_RX_ST BIT(15) /*!< endpoint reception successful transferred */ -#define EPxCS_RX_DTG BIT(14) /*!< endpoint reception data PID toggle */ -#define EPxCS_RX_STA BITS(12, 13) /*!< endpoint reception status bits */ -#define EPxCS_SETUP BIT(11) /*!< endpoint setup transaction completed */ -#define EPxCS_CTL BITS(9, 10) /*!< endpoint type control */ -#define EPxCS_KCTL BIT(8) /*!< endpoint kind control */ -#define EPxCS_TX_ST BIT(7) /*!< endpoint transmission successful transfer */ -#define EPxCS_TX_DTG BIT(6) /*!< endpoint transmission data toggle */ -#define EPxCS_TX_STA BITS(4, 5) /*!< endpoint transmission transfers status bits */ -#define EPxCS_ADDR BITS(0, 3) /*!< endpoint address */ - -/* USBD_LPMCS */ -#define LPMCS_BLSTAT BITS(4, 7) /*!< bLinkState value */ -#define LPMCS_REMWK BIT(3) /*!< bRemoteWake value */ -#define LPMCS_LPMACK BIT(1) /*!< LPM token acknowledge enable */ -#define LPMCS_LPMEN BIT(0) /*!< LPM support enable */ - -/* constants definitions */ -/* endpoint control and status register mask (no toggle fields) */ -#define EPCS_MASK (EPxCS_RX_ST|EPxCS_SETUP|EPxCS_CTL|EPxCS_KCTL|EPxCS_TX_ST|EPxCS_ADDR) - -/* EPxCS_CTL[1:0] endpoint type control */ -#define ENDP_TYPE(regval) (EPxCS_CTL & ((regval) << 9U)) - -#define EP_BULK ENDP_TYPE(0U) /* bulk transfers */ -#define EP_CONTROL ENDP_TYPE(1U) /* control transfers */ -#define EP_ISO ENDP_TYPE(2U) /* isochronous transfers */ -#define EP_INTERRUPT ENDP_TYPE(3U) /* interrupt transfers */ -#define EP_CTL_MASK (~EPxCS_CTL & EPCS_MASK) - -/* endpoint kind control mask */ -#define EPKCTL_MASK (~EPxCS_KCTL & EPCS_MASK) - -/* EPxCS_TX_STA[1:0] status for Tx transfer */ -#define ENDP_TXSTAT(regval) (EPxCS_TX_STA & ((regval) << 4U)) - -#define EPTX_DISABLED ENDP_TXSTAT(0U) /* transmission state is disabled */ -#define EPTX_STALL ENDP_TXSTAT(1U) /* transmission state is STALL */ -#define EPTX_NAK ENDP_TXSTAT(2U) /* transmission state is NAK */ -#define EPTX_VALID ENDP_TXSTAT(3U) /* transmission state is enabled */ -#define EPTX_DTGMASK (EPxCS_TX_STA | EPCS_MASK) - -/* EPxCS_RX_STA[1:0] status for Rx transfer */ -#define ENDP_RXSTAT(regval) (EPxCS_RX_STA & ((regval) << 12U)) - -#define EPRX_DISABLED ENDP_RXSTAT(0U) /* reception state is disabled */ -#define EPRX_STALL ENDP_RXSTAT(1U) /* reception state is STALL */ -#define EPRX_NAK ENDP_RXSTAT(2U) /* reception state is NAK */ -#define EPRX_VALID ENDP_RXSTAT(3U) /* reception state is enabled */ -#define EPRX_DTGMASK (EPxCS_RX_STA | EPCS_MASK) - -/* endpoint receive/transmission counter register bit definitions */ -#define EPRCNT_BLKSIZ BIT(15) /* reception data block size */ -#define EPRCNT_BLKNUM BITS(10, 14) /* reception data block number */ -#define EPRCNT_CNT BITS(0, 9) /* reception data count */ - -#define EPTCNT_CNT BITS(0, 9) /* transmisson data count */ - -/* interrupt flag clear bits */ -#define CLR_STIF (~INTF_STIF) -#define CLR_PMOUIF (~INTF_PMOUIF) -#define CLR_ERRIF (~INTF_ERRIF) -#define CLR_WKUPIF (~INTF_WKUPIF) -#define CLR_SPSIF (~INTF_SPSIF) -#define CLR_RSTIF (~INTF_RSTIF) -#define CLR_SOFIF (~INTF_SOFIF) -#define CLR_ESOFIF (~INTF_ESOFIF) -#define CLR_L1REQ (~INTF_L1REQ) - -/* endpoint receive/transmission counter register bit offset */ -#define BLKSIZE_OFFSET (0x01U) -#define BLKNUM_OFFSET (0x05U) -#define RXCNT_OFFSET (0x0AU) - -#define TXCNT_OFFSET (0x0AU) - -#define BLKSIZE32_MASK (0x1fU) -#define BLKSIZE2_MASK (0x01U) - -#define BLKSIZE32_OFFSETMASK (0x05U) -#define BLKSIZE2_OFFSETMASK (0x01U) - -/* double buffer endpoint direction */ -typedef enum -{ - DBUF_EP_IN, /* double buffer IN direction */ - DBUF_EP_OUT, /* double buffer OUT direction */ - DBUF_EP_ERR, /* double buffer errer direction */ -}dbuf_ep_dir_enum; - -/* endpoints address */ -/* first bit is direction(0 for Rx and 1 for Tx) */ -#define EP0_OUT ((uint8_t)0x00) /* OUT endpoint 0 address */ -#define EP0_IN ((uint8_t)0x80) /* IN endpoint 0 address */ -#define EP1_OUT ((uint8_t)0x01) /* OUT endpoint 1 address */ -#define EP1_IN ((uint8_t)0x81) /* IN endpoint 1 address */ -#define EP2_OUT ((uint8_t)0x02) /* OUT endpoint 2 address */ -#define EP2_IN ((uint8_t)0x82) /* IN endpoint 2 address */ -#define EP3_OUT ((uint8_t)0x03) /* OUT endpoint 3 address */ -#define EP3_IN ((uint8_t)0x83) /* IN endpoint 3 address */ -#define EP4_OUT ((uint8_t)0x04) /* OUT endpoint 4 address */ -#define EP4_IN ((uint8_t)0x84) /* IN endpoint 4 address */ -#define EP5_OUT ((uint8_t)0x05) /* OUT endpoint 5 address */ -#define EP5_IN ((uint8_t)0x85) /* IN endpoint 5 address */ -#define EP6_OUT ((uint8_t)0x06) /* OUT endpoint 6 address */ -#define EP6_IN ((uint8_t)0x86) /* IN endpoint 6 address */ -#define EP7_OUT ((uint8_t)0x07) /* OUT endpoint 7 address */ -#define EP7_IN ((uint8_t)0x87) /* IN endpoint 7 address */ - -/* endpoints_Identifier */ -#define EP0 ((uint8_t)0) /* endpoint 0 ID */ -#define EP1 ((uint8_t)1) /* endpoint 1 ID */ -#define EP2 ((uint8_t)2) /* endpoint 2 ID */ -#define EP3 ((uint8_t)3) /* endpoint 3 ID */ -#define EP4 ((uint8_t)4) /* endpoint 4 ID */ -#define EP5 ((uint8_t)5) /* endpoint 5 ID */ -#define EP6 ((uint8_t)6) /* endpoint 6 ID */ -#define EP7 ((uint8_t)7) /* endpoint 7 ID */ - -/* USBD operation macros */ - -/* set register value */ -#define USBD_REG_SET(reg, regvalue) ((reg) = (uint16_t)(regvalue)) - -/* get register value */ -#define USBD_REG_GET(reg) ((uint16_t)(reg)) - -#define _EP_ADDR_SET(ep_num, addr) USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK) | addr) - -/* Tx or Rx transfer status setting (bits EPTX_STA[1:0]) */ -#define USBD_ENDP_TX_STATUS_SET(ep_num, state) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPTX_DTGMASK;\ - USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ -} while(0) - -#define USBD_ENDP_RX_STATUS_SET(ep_num, state) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)EPRX_DTGMASK;\ - USBD_REG_SET(USBD_EPxCS(ep_num), ((_regval) ^ (state))); \ -} while(0) - -/* Tx or Rx transfer status getting (bits EPxCS_RX_STA[1:0]) */ -#define USBD_ENDP_TX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_STA) -#define USBD_ENDP_RX_STATUS_GET(ep_num) (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_STA) - -/* Rx and Tx transfer status setting (bits EPxCS_RX_STA[1:0] & EPxCS_TX_STA[1:0]) */ -#define USBD_ENDP_RX_TX_STATUS_SET(ep_num, state_rx, state_tx) do {\ - register uint16_t _regval; \ - _regval = USBD_REG_GET(USBD_EPxCS(ep_num)) & (uint16_t)(EPRX_DTGMASK | EPxCS_TX_STA) ;\ - USBD_REG_SET(USBD_EPxCS(ep_num), (((_regval) ^ (state_rx)) ^ (state_tx))); \ -} while(0) - -/* set and clear endpoint kind (bit EPxCS_KCTL) */ -#define USBD_ENDP_KIND_SET(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), ((USBD_REG_GET(USBD_EPxCS(ep_num)) | EPxCS_KCTL) & EPCS_MASK))) -#define USBD_ENDP_KIND_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPKCTL_MASK))) - -/* set and clear directly STATUS_OUT state of endpoint */ -#define USBD_STATUS_OUT_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) -#define USBD_STATUS_OUT_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) - -/* clear bit EPxCS_RX_ST/EPxCS_TX_ST in the endpoint control and status register */ -#define USBD_ENDP_RX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0x7FFFU & (uint16_t)EPCS_MASK)) -#define USBD_ENDP_TX_STAT_CLEAR(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), USBD_REG_GET(USBD_EPxCS(ep_num)) & 0xFF7FU & (uint16_t)EPCS_MASK)) - -/* toggle EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ -#define USBD_DTG_RX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_RX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) -#define USBD_DTG_TX_TOGGLE(ep_num) (USBD_REG_SET(USBD_EPxCS(ep_num), EPxCS_TX_DTG | (USBD_REG_GET(USBD_EPxCS(ep_num)) & EPCS_MASK))) - -/* clear EPxCS_RX_DTG or EPxCS_TX_DTG bit in the endpoint control and status register */ -#define USBD_DTG_RX_CLEAR(ep_num) do {\ - if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_RX_DTG) != 0U) {\ - USBD_DTG_RX_TOGGLE(ep_num);\ - } else {\ - }\ -} while(0) - -#define USBD_DTG_TX_CLEAR(ep_num) do {\ - if ((USBD_REG_GET(USBD_EPxCS(ep_num)) & EPxCS_TX_DTG) != 0U) {\ - USBD_DTG_TX_TOGGLE(ep_num);\ - } else {\ - }\ -} while(0) - -/* set and clear directly double buffered feature of endpoint */ -#define USBD_ENDP_DOUBLE_BUF_SET(ep_num) USBD_ENDP_KIND_SET(ep_num) -#define USBD_ENDP_DOUBLE_BUF_CLEAR(ep_num) USBD_ENDP_KIND_CLEAR(ep_num) - -/* toggle SW_BUF bit in the double buffered endpoint */ -#define USBD_SWBUF_TX_TOGGLE(ep_num) USBD_DTG_RX_TOGGLE(ep_num) -#define USBD_SWBUF_RX_TOGGLE(ep_num) USBD_DTG_TX_TOGGLE(ep_num) - -#endif /* USBD_REGS_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_std.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_std.h deleted file mode 100644 index 4af670272a..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Include/usbd_std.h +++ /dev/null @@ -1,194 +0,0 @@ -/*! - \file usbd_std.h - \brief USB standard definitions -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usbd_core.h" -#include - -#ifndef NULL -#define NULL 0U -#endif - -/* constants definitions */ -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /* device qualifier descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /* configuration descriptor length */ - -#define USBD_LANGID_STR_IDX 0x00U /* language ID string index */ -#define USBD_MFC_STR_IDX 0x01U /* manufacturer string index */ -#define USBD_PRODUCT_STR_IDX 0x02U /* product string index */ -#define USBD_SERIAL_STR_IDX 0x03U /* serial string index */ -#define USBD_CONFIG_STR_IDX 0x04U /* configuration string index */ -#define USBD_INTERFACE_STR_IDX 0x05U /* interface string index */ - -#define USB_STANDARD_REQ 0x00U /* standard request */ -#define USB_CLASS_REQ 0x20U /* device class request */ -#define USB_VENDOR_REQ 0x40U /* vendor request */ -#define USB_REQ_MASK 0x60U /* request type mask */ - -#define USB_REQTYPE_DEVICE 0x00U /* request recipient is device */ -#define USB_REQTYPE_INTERFACE 0x01U /* request recipient is interface */ -#define USB_REQTYPE_ENDPOINT 0x02U /* request recipient is endpoint */ -#define USB_REQ_RECIPIENT_MASK 0x1fU /* request recipient mask */ - -#define USBREQ_GET_STATUS 0x00U /* Get_Status standard requeset */ -#define USBREQ_CLEAR_FEATURE 0x01U /* Clear_Feature standard requeset */ -#define USBREQ_SET_FEATURE 0x03U /* Set_Feature standard requeset */ -#define USBREQ_SET_ADDRESS 0x05U /* Set_Address standard requeset */ -#define USBREQ_GET_DESCRIPTOR 0x06U /* Get_Descriptor standard requeset */ -#define USBREQ_GET_CONFIGURATION 0x08U /* Get_Configuration standard requeset */ -#define USBREQ_SET_CONFIGURATION 0x09U /* Set_Configuration standard requeset */ -#define USBREQ_GET_INTERFACE 0x0AU /* Get_Interface standard requeset */ -#define USBREQ_SET_INTERFACE 0x0BU /* Set_Interface standard requeset */ - -#define USB_DESCTYPE_DEVICE 0x01U /* device descriptor type */ -#define USB_DESCTYPE_CONFIGURATION 0x02U /* configuration descriptor type */ -#define USB_DESCTYPE_STRING 0x03U /* string descriptor type */ -#define USB_DESCTYPE_INTERFACE 0x04U /* interface descriptor type */ -#define USB_DESCTYPE_ENDPOINT 0x05U /* endpoint descriptor type */ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /* device qualifier descriptor type */ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /* other speed configuration descriptor type */ -#define USB_DESCTYPE_BOS 0x0FU /* BOS descriptor type */ - -#define USB_STATUS_REMOTE_WAKEUP 2U /* USB is in remote wakeup status */ -#define USB_STATUS_SELF_POWERED 1U /* USB is in self powered status */ - -#define USB_FEATURE_ENDP_HALT 0U /* USB has endpoint halt feature */ -#define USB_FEATURE_REMOTE_WAKEUP 1U /* USB has endpoint remote wakeup feature */ -#define USB_FEATURE_TEST_MODE 2U /* USB has endpoint test mode feature */ - -#define ENG_LANGID 0x0409U /* english language ID */ -#define CHN_LANGID 0x0804U /* chinese language ID */ - -#define USB_EPTYPE_MASK 0x03U - -#define USB_DEVICE_DESC_SIZE 0x12U - -/* USB device exported macros */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (void *)&(const struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -#pragma pack(1) - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -#pragma pack() - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -#pragma pack(1) - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -/* function declarations */ -/* USB SETUP transaction processing */ -uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev); -/* USB OUT transaction processing */ -uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); -/* USB IN transaction processing */ -uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num); - -/* handle USB standard device request */ -uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle device class request */ -uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle USB vendor request */ -uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -/* decode setup data packet */ -void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -/* handle USB enumeration error event */ -void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_core.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_core.c deleted file mode 100644 index 7b3b15d361..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_core.c +++ /dev/null @@ -1,389 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -uint32_t g_interrupt_mask = 0U; -uint32_t g_free_buf_addr = ENDP_BUF_ADDR; - -usbd_ep_buf_struct *pbuf_reg = (usbd_ep_buf_struct *)USBD_RAM; - -/*! - \brief device core register initialization - \param[in] none - \param[out] none - \retval none -*/ -void usbd_core_init (usbd_core_handle_struct *pudev) -{ - /* disable remote wakeup feature */ - pudev->remote_wakeup = 0U; - - /* just reset the CLOSE bit */ - USBD_REG_SET(USBD_CTL, CTL_SETRST); - - /* may be need wait some time(tSTARTUP) ... */ - - /* clear SETRST bit in USBD_CTL register */ - USBD_REG_SET(USBD_CTL, 0U); - - /* clear all pending interrupts */ - USBD_REG_SET(USBD_INTF, 0U); - - /* set allocation buffer address */ - USBD_REG_SET(USBD_BADDR, BUFFER_ADDRESS & 0xFFF8U); - - g_interrupt_mask = IER_MASK; - -#ifdef LPM_ENABLED - /* enable L1REQ interrupt */ - USBD_REG_SET(USBD_LPMCS, LPMCS_LPMACK | LPMCS_LPMEN); -#endif /* LPM_ENABLED */ - - /* enable all interrupts mask bits */ - USBD_REG_SET(USBD_CTL, g_interrupt_mask); -} - -/*! - \brief free buffer used from application by toggling the SW_BUF byte - \param[in] ep_num: endpoint identifier (0..7) - \param[in] dir: endpoint direction which can be OUT(0) or IN(1) - \param[out] none - \retval None -*/ -void user_buffer_free (uint8_t ep_num, uint8_t dir) -{ - if (DBUF_EP_OUT == dir) { - USBD_SWBUF_RX_TOGGLE(ep_num); - } else if (DBUF_EP_IN == dir) { - USBD_SWBUF_TX_TOGGLE(ep_num); - } else { - /* no operation */ - } -} - -/*! - \brief device core register configure when stop device - \param[in] none - \param[out] none - \retval none -*/ -void usbd_core_deinit (void) -{ - /* disable all interrupts and set USB reset */ - USBD_REG_SET(USBD_CTL, CTL_SETRST); - - /* clear all interrupt flags */ - USBD_REG_SET(USBD_INTF, 0U); - - /* close device */ - USBD_REG_SET(USBD_CTL, CTL_SETRST | CTL_CLOSE); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to USB core instance - \param[in] pep_desc: pointer to endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usbd_core_handle_struct *pudev, void *ep_desc) -{ - usb_ep_struct *ep; - uint8_t ep_num = ((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress & 0x0FU; - uint32_t reg_value = ((usb_descriptor_endpoint_struct *)ep_desc)->wMaxPacketSize; - - if (((usb_descriptor_endpoint_struct *)ep_desc)->bEndpointAddress >> 7U) { - ep = &pudev->in_ep[ep_num]; - - ep->maxpacket = reg_value; - - /* set the endpoint transmit buffer address */ - (pbuf_reg + ep_num)->tx_addr = (uint16_t)g_free_buf_addr; - - reg_value = (reg_value + 1U) & ~1U; - - /* configure the endpoint status as NAK status */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_NAK); - } else { - ep = &pudev->out_ep[ep_num]; - - ep->maxpacket = reg_value; - - /* set the endpoint receive buffer address */ - (pbuf_reg + ep_num)->rx_addr = (uint16_t)g_free_buf_addr; - - if (reg_value > 62U) { - reg_value = (reg_value + 31U) & ~31U; - (pbuf_reg + ep_num)->rx_count = ((reg_value << 5U) - 1U) | 0x8000U; - } else { - reg_value = (reg_value + 1U) & ~1U; - (pbuf_reg + ep_num)->rx_count = reg_value << 9U; - } - - /* configure the endpoint status as NAK status */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_NAK); - } - - g_free_buf_addr += reg_value; - - /* set the endpoint type */ - switch (((usb_descriptor_endpoint_struct *)ep_desc)->bmAttributes & USB_EPTYPE_MASK) { - case ENDP_CONTROL: - reg_value = EP_CONTROL; - break; - case ENDP_BULK: - reg_value = EP_BULK; - break; - case ENDP_INT: - reg_value = EP_INTERRUPT; - break; - case ENDP_ISOC: - reg_value = EP_ISO; - break; - default: - break; - } - - USBD_REG_SET(USBD_EPxCS(ep_num), reg_value | ep_num); - - ep->stall = 0; -} - -/*! - \brief configure the endpoint when it is disabled - \param[in] pudev: pointer to USB core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7F; - - if (ep_addr >> 7) { - USBD_DTG_TX_CLEAR(ep_num); - - /* configure the endpoint status as DISABLED */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_DISABLED); - } else { - USBD_DTG_RX_CLEAR(ep_num); - - /* configure the endpoint status as DISABLED */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_DISABLED); - } -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[in] pbuf: user buffer address pointer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - - ep = &pudev->out_ep[ep_num]; - - /* configure the transaction level parameters */ - ep->trs_buf = pbuf; - ep->trs_len = buf_len; - - /* enable endpoint to receive */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to USB core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[in] pbuf: transmit buffer address pointer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usbd_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - __IO uint32_t len = 0U; - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - /* configure the transaction level parameters */ - ep->trs_buf = pbuf; - ep->trs_len = buf_len; - ep->trs_count = 0U; - - /* transmit length is more than one packet */ - if (ep->trs_len > ep->maxpacket) { - len = ep->maxpacket; - } else { - len = ep->trs_len; - } - - usbd_ep_data_write(ep->trs_buf, (pbuf_reg + ep_num)->tx_addr, (uint16_t)len); - (pbuf_reg + ep_num)->tx_count = (uint16_t)len; - - /* enable endpoint to transmit */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); -} - -/*! - \brief set an endpoint to STALL status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep; - - if (ep_addr >> 7U) { - ep = &pudev->in_ep[ep_num]; - - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_STALL); - } else { - ep = &pudev->out_ep[ep_num]; - - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_STALL); - } - - ep->stall = 1U; - - if (0U == ep_num) { - /* control endpoint need to be stalled in two directions */ - USBD_ENDP_RX_TX_STATUS_SET(ep_num, EPRX_STALL, EPTX_STALL); - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - usb_ep_struct *ep; - - if (ep_addr >> 7U) { - ep = &pudev->in_ep[ep_num]; - - /* clear endpoint data toggle bit */ - USBD_DTG_TX_CLEAR(ep_num); - - /* clear endpoint stall status */ - USBD_ENDP_TX_STATUS_SET(ep_num, EPTX_VALID); - } else { - ep = &pudev->out_ep[ep_num]; - - /* clear endpoint data toggle bit */ - USBD_DTG_RX_CLEAR(ep_num); - - /* clear endpoint stall status */ - USBD_ENDP_RX_STATUS_SET(ep_num, EPRX_VALID); - } - - ep->stall = 0U; -} - -/*! - \brief get the endpoint status - \param[in] pudev: pointer to usb core instance - \param[in] ep_addr: endpoint address - in this parameter: - bit0..bit6: endpoint number (0..7) - bit7: endpoint direction which can be IN(1) or OUT(0) - \param[out] none - \retval endpoint status -*/ -uint8_t usbd_ep_status_get (usbd_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7U) { - return (uint8_t)USBD_ENDP_TX_STATUS_GET((ep_addr & 0x7FU)); - } else { - return (uint8_t)USBD_ENDP_RX_STATUS_GET(ep_addr); - } -} - -/*! - \brief write datas from user fifo to USBRAM - \param[in] user_fifo: pointer to user fifo - \param[in] usbram_addr: the allocation buffer address of the endpoint - \param[in] bytes: the bytes count of the write datas - \param[out] none - \retval none -*/ -void usbd_ep_data_write(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) -{ - uint32_t n; - uint32_t *write_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); - - for (n = 0U; n < (bytes + 1U) / 2U; n++) { - *write_addr++ = *((__packed uint16_t*)user_fifo); - user_fifo += 2U; - } -} - -/*! - \brief read datas from USBRAM to user fifo - \param[in] user_fifo: pointer to user fifo - \param[in] usbram_addr: the allocation buffer address of the endpoint - \param[in] bytes: the bytes count of the read datas - \param[out] none - \retval none -*/ -void usbd_ep_data_read(uint8_t *user_fifo, uint16_t usbram_addr, uint16_t bytes) -{ - uint32_t n; - uint32_t *read_addr = (uint32_t *)((uint32_t)(usbram_addr * 2U + USBD_RAM)); - - for (n = 0U; n < (bytes + 1U) / 2U; n++) { - *((__packed uint16_t*)user_fifo) = (uint16_t)*read_addr++; - user_fifo += 2U; - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to USB core instance - \param[in] ep_num: endpoint identifier which is in (0..7) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rx_count_get (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - return (uint16_t)pudev->out_ep[ep_num].trs_count; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_int.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_int.c deleted file mode 100644 index b8e645213b..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_int.c +++ /dev/null @@ -1,331 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device power interrupt routines -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbd_int.h" - -extern uint32_t g_interrupt_mask; -extern __IO uint8_t g_suspend_enabled; -extern __IO uint8_t g_remote_wakeup_on; -extern __IO uint8_t g_ESOF_count; - -#ifdef LPM_ENABLED -__IO uint32_t L1_remote_wakeup = 0U; -__IO uint32_t L1_resume = 0U; -__IO uint32_t besl = 0U; -#endif /* LPM_ENABLED */ - -static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev); -static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev); - -/*! - \brief USB interrupt events service routine - \param[in] none - \param[out] none - \retval none -*/ -void usbd_isr (void) -{ - __IO uint16_t interrupt_flag = 0U; - __IO uint16_t ctlr = 0U; - - interrupt_flag = USBD_REG_GET(USBD_INTF); - - if (g_interrupt_mask & INTF_STIF & interrupt_flag) { - /* the endpoint successful transfer interrupt service */ - usbd_intf_lpst(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_WKUPIF & interrupt_flag) { - /* clear wakeup interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_WKUPIF); - - /* USB wakeup interrupt handle */ - usbd_intf_wakeup(&usb_device_dev); - -#ifdef LPM_ENABLED - /* clear L1 remote wakeup flag */ - L1_remote_wakeup = 0; -#endif /* LPM_ENABLED */ - } - - if (g_interrupt_mask & INTF_SPSIF & interrupt_flag) { - if(!(USBD_REG_GET(USBD_CTL) & CTL_RSREQ)) { - /* process library core layer suspend routine*/ - usbd_intf_suspend(&usb_device_dev); - - /* clear of suspend interrupt flag bit must be done after setting of CTLR_SETSPS */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SPSIF); - } - } - - if (g_interrupt_mask & INTF_SOFIF & interrupt_flag) { - /* clear SOF interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_SOFIF); - - /* USB SOF interrupt handle */ - usbd_intf_sof(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_ESOFIF & interrupt_flag) { - /* clear ESOF interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_ESOFIF); - - /* USB ESOF interrupt handle */ - usbd_intf_esof(&usb_device_dev); - } - - if (g_interrupt_mask & INTF_RSTIF & interrupt_flag) { - /* clear reset interrupt flag in INTF */ - USBD_REG_SET(USBD_INTF, (uint16_t)CLR_RSTIF); - - /* USB reset interrupt handle */ - usbd_intf_reset(&usb_device_dev); - } - -#ifdef LPM_ENABLED - if (g_interrupt_mask & INTF_L1REQ & interrupt_flag) { - /* clear L1 ST bit in LPM INTF */ - USBD_REG_SET(USBD_INTF, CLR_L1REQ); - - /* read BESL field from subendpoint0 register which coressponds to HIRD parameter in LPM spec */ - besl = (USBD_REG_GET(USBD_LPMCS) & LPMCS_BLSTAT) >> 4; - - /* read BREMOTEWAKE bit from subendpoint0 register which corresponding to bRemoteWake bit in LPM request */ - L1_remote_wakeup = (USBD_REG_GET(USBD_LPMCS) & LPMCS_REMWK) >> 8; - - /* process USB device core layer suspend routine */ - /* enter USB model in suspend and system in low power mode (DEEP_SLEEP mode) */ - usbd_intf_suspend(&usb_device_dev); - } -#endif /* LPM_ENABLED */ -} - -/*! - \brief handle USB low priority successful transfer event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_lpst (usbd_core_handle_struct *pudev) -{ - uint8_t ep_num = 0U; - - __IO uint16_t int_status = 0U; - __IO uint16_t ep_value = 0U; - - usb_ep_struct *ep = NULL; - - /* wait till interrupts are not pending */ - while (0U != ((int_status = USBD_REG_GET(USBD_INTF)) & (uint16_t)INTF_STIF)) { - /* get endpoint number and the value of control and state register */ - ep_num = (uint8_t)(int_status & INTF_EPNUM); - ep_value = USBD_REG_GET(USBD_EPxCS(ep_num)); - - if (0U == (int_status & INTF_DIR)) { - /* handle the in direction transaction */ - - ep = &(pudev->in_ep[ep_num]); - - if (0U != (ep_value & EPxCS_TX_ST)) { - /* clear successful transmit interrupt flag */ - USBD_ENDP_TX_STAT_CLEAR(ep_num); - - /* just handle single buffer situation */ - ep->trs_count = (pbuf_reg + ep_num)->tx_count & EPTCNT_CNT; - - /* maybe mutiple packets */ - ep->trs_buf += ep->trs_count; - - usbd_in_transaction(pudev, ep_num); - } - } else { - /* handle the out direction transaction */ - - uint16_t count = 0U; - - ep = &(pudev->out_ep[ep_num]); - - if (0U != (ep_value & EPxCS_RX_ST)) { - /* clear successful receive interrupt flag */ - USBD_ENDP_RX_STAT_CLEAR(ep_num); - - count = (pbuf_reg + ep_num)->rx_count & (uint16_t)EPRCNT_CNT; - - if (0U != count) { - if (0U != (ep_value & EPxCS_SETUP)) { - /* handle setup packet */ - usbd_ep_data_read(&(pudev->setup_packet[0]), pbuf_reg->rx_addr, count); - - /* enter setup status */ - usbd_setup_transaction(pudev); - - return USBD_OK; - } else { - usbd_ep_data_read(ep->trs_buf, (pbuf_reg + ep_num)->rx_addr, count); - } - } - - /* maybe mutiple packets */ - ep->trs_count += count; - ep->trs_buf += count; - ep->trs_len -= count; - - if ((0U == ep->trs_len) || (count < ep->maxpacket)) { - /* enter data OUT status */ - usbd_out_transaction(pudev, ep_num); - - ep->trs_count = 0U; - } else { - usbd_ep_rx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); - } - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB SOF event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_sof (usbd_core_handle_struct *pudev) -{ - /* if necessary, user can add code here */ - if (NULL != usbd_int_fops) { - usbd_int_fops->SOF(pudev); - } - - return USBD_OK; -} - -/*! - \brief handle USB expect SOF event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_esof (usbd_core_handle_struct *pudev) -{ - /* control resume time by ESOFs */ - if (g_ESOF_count > 0U) { - g_ESOF_count--; - - if (0U == g_ESOF_count) { - if (1U == g_remote_wakeup_on) { - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_RSREQ); - - g_remote_wakeup_on = 0U; - } else { - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); - - g_ESOF_count = 3U; - g_remote_wakeup_on = 1U; - } - } - } - - return USBD_OK; -} - -/*! - \brief handle USB reset event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_reset (usbd_core_handle_struct *pudev) -{ -// uint8_t i; - - g_free_buf_addr = ENDP_BUF_ADDR; - - /* configure endpoint 0 buffer */ - pbuf_reg->tx_addr = (uint16_t)g_free_buf_addr; - g_free_buf_addr += USBD_EP0_MAX_SIZE; - - pbuf_reg->rx_addr = (uint16_t)g_free_buf_addr; - g_free_buf_addr += USBD_EP0_MAX_SIZE; - - /* configure endpoint 0 Rx count */ - pbuf_reg->rx_count = ((USBD_EP0_MAX_SIZE << 5) - 1) | 0x8000; - - pudev->in_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; - pudev->out_ep[EP0].maxpacket = USBD_EP0_MAX_SIZE; - - USBD_REG_SET(USBD_EPxCS(EP0), EP_CONTROL | EPRX_VALID | EPTX_NAK); - - /* set device address as default address 0 */ - USBD_REG_SET(USBD_DADDR, DADDR_USBEN); - - pudev->status = USBD_DEFAULT; - - return USBD_OK; -} - -/*! - \brief handle USB suspend event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_suspend (usbd_core_handle_struct *pudev) -{ - /* store the device current status */ - pudev->prev_status = pudev->status; - - /* set device in suspended state */ - pudev->status = USBD_SUSPENDED; - - /* enter USB in suspend and mcu system in low power mode */ - if (g_suspend_enabled) { - usbd_suspend(); - } else { - /* if not possible then resume after xx ms */ - g_ESOF_count = 3U; - } - - return USBD_OK; -} - -/*! - \brief handle USB wakeup event - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -static uint8_t usbd_intf_wakeup (usbd_core_handle_struct *pudev) -{ - /* restore the old status */ - pudev->status = pudev->prev_status; - -#ifdef LPM_ENABLED - if ((0U == g_remote_wakeup_on) && (0U == L1_resume)) { - resume_mcu(); - } else if (1U == g_remote_wakeup_on) { - /* no operation */ - } else { - L1_resume = 0U; - } -#else - if (0U == g_remote_wakeup_on) { - resume_mcu(); - } -#endif /* LPM_ENABLED */ - - return USBD_OK; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_pwr.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_pwr.c deleted file mode 100644 index 16258c20e4..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_pwr.c +++ /dev/null @@ -1,132 +0,0 @@ -/*! - \file usbd_pwr.c - \brief USB device power management driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbd_pwr.h" - -#ifdef USBD_LOWPWR_MODE_ENABLE -static void lowpower_mode_exit (void); -#endif /* USBD_LOWPWR_MODE_ENABLE */ - -__IO uint8_t g_ESOF_count = 0U; -__IO uint8_t g_suspend_enabled = 1U; -__IO uint8_t g_remote_wakeup_on = 0U; - -#ifdef LPM_ENABLED -extern __IO uint32_t L1_resume; -#endif /* LPM_ENABLED */ - -/*! - \brief USB wakeup first operation is to wakeup mcu - \param[in] none - \param[out] none - \retval none -*/ -void resume_mcu (void) -{ - /* clear low_power mode bit in USBD_CTL */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_LOWM)); - -#ifdef USBD_LOWPWR_MODE_ENABLE - - /* restore normal operations */ - lowpower_mode_exit(); - -#endif /* USBD_LOWPWR_MODE_ENABLE */ - - /* clear SETSPS bit */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & (~CTL_SETSPS)); -} - -#ifdef USBD_LOWPWR_MODE_ENABLE - -/*! - \brief restore system clocks and power while exiting suspend mode - \param[in] none - \param[out] none - \retval none -*/ -static void lowpower_mode_exit (void) -{ - /* restore system clock */ - - /* enable HSE */ - rcu_osci_on(RCU_HXTAL); - - /* wait till HSE is ready */ - while(RESET == rcu_flag_get(RCU_FLAG_HXTALSTB)); - - /* enable PLL */ - rcu_osci_on(RCU_PLL_CK); - - /* wait till PLL is ready */ - while(RESET == rcu_flag_get(RCU_FLAG_PLLSTB)); - - /* select PLL as system clock source */ - rcu_system_clock_source_config(RCU_CKSYSSRC_PLL); - - /* wait till PLL is used as system clock source */ - while(0x08 != rcu_system_clock_source_get()); - - /* low power sleep on exit disabled */ - system_lowpower_reset(SCB_LPM_DEEPSLEEP); -} - -#endif /* USBD_LOWPWR_MODE_ENABLE */ - -/*! - \brief set USB device to suspend mode - \param[in] none - \param[out] none - \retval none -*/ -void usbd_suspend (void) -{ - /* set usb module to suspend and low-power mode */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_SETSPS | CTL_LOWM); - -#ifdef USBD_LOWPWR_MODE_ENABLE - - /* check wakeup flag is set */ - if (0 == (USBD_REG_GET(USBD_INTF) & INTF_WKUPIF)) { - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } else { - /* clear wakeup interrupt flag */ - USBD_REG_SET(USBD_INTF, CLR_WKUPIF); - - /* clear set_suspend flag */ - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) & ~CTL_SETSPS); - } - -#endif /* USBD_LOWPWR_MODE_ENABLE */ -} - -/*! - \brief start to remote wakeup - \param[in] none - \param[out] none - \retval none -*/ -void usbd_remote_wakeup_active(void) -{ - resume_mcu(); - -#ifdef LPM_ENABLED - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_L1RSREQ); - - L1_resume = 1U; -#else - g_remote_wakeup_on = 1U; - - g_ESOF_count = 15U; - USBD_REG_SET(USBD_CTL, USBD_REG_GET(USBD_CTL) | CTL_RSREQ); -#endif /* LPM_ENABLED */ -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_std.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_std.c deleted file mode 100644 index 9c49cc076d..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbd_driver/Source/usbd_std.c +++ /dev/null @@ -1,834 +0,0 @@ -/*! - \file usbd_std.c - \brief USB device stand routines - \note about USB standard, please refer to the USB2.0 protocol -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbd_std.h" - -uint8_t g_device_address = 0U; - -/* USB enumeration handle functions */ -static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, - uint8_t index, - uint16_t *pLen); - -#ifdef LPM_ENABLED -static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen); -#endif /* LPM_ENABLED */ - -/* standard device request handler */ -static void (*standard_device_request[])(usbd_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clearfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfiguration, - usbd_setconfiguration, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_setup_transaction (usbd_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse (pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, 0x00U); - break; - } - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_num: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_out_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - usb_ep_struct *ep = &pudev->out_ep[ep_num]; - - if (0U == ep_num) { - if (0U != pudev->ctl_count) { - if (ep->trs_len > ep->maxpacket) { - /* one data packet has been received, update trs_len */ - ep->trs_len -= ep->maxpacket; - - /* continue to receive remain data */ - usbd_ep_rx(pudev, EP0_OUT, ep->trs_buf, (uint16_t)ep->trs_len); - } else { - if (USBD_CONFIGURED == pudev->status) { - /* device class handle */ - pudev->class_data_handler(pudev, USBD_RX, EP0); - } - - /* enter the control transaction status stage */ - USBD_CONTRL_STATUS_TX(); - - pudev->ctl_count = 0U; - } - } else { - /* clear endpoint status_out status */ - USBD_STATUS_OUT_CLEAR(EP0); - } - } else { - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_RX, ep_num); - } - } - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_num: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_in_transaction (usbd_core_handle_struct *pudev, uint8_t ep_num) -{ - usb_ep_struct *ep = &pudev->in_ep[ep_num]; - - if (0U == ep_num) { - if (0U != pudev->ctl_count) { - if (ep->trs_len > ep->maxpacket) { - /* one data packet has been transmited, update trs_len */ - ep->trs_len -= ep->maxpacket; - - /* continue to transmit remain data */ - usbd_ep_tx (pudev, EP0_IN, ep->trs_buf, (uint16_t)ep->trs_len); - -// usbd_ep_rx (pudev, 0, NULL, 0); - } else { -#ifndef USB_DFU - /* transmit length is maxpacket multiple, so send zero length packet */ - if ((0U == (ep->trs_len % ep->maxpacket)) && (ep->trs_len < pudev->ctl_count)) { - usbd_ep_tx (pudev, EP0_IN, NULL, 0U); - - pudev->ctl_count = 0U; - -// usbd_ep_rx (pudev, 0, NULL, 0); - } else -#endif /* USB_DFU */ - { - ep->trs_len = 0U; - - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_TX, EP0); - } - - USBD_CONTRL_STATUS_RX(); - - pudev->ctl_count = 0U; - } - } - } else { - if (0U != g_device_address) { - USBD_REG_SET(USBD_DADDR, DADDR_USBEN | g_device_address); - g_device_address = 0U; - } - } - } else { - ep->trs_len -= ep->trs_count; - - if (0U == ep->trs_len) { - if (USBD_CONFIGURED == pudev->status) { - pudev->class_data_handler(pudev, USBD_TX, ep_num); - } - } else { - usbd_ep_tx(pudev, ep_num, ep->trs_buf, (uint16_t)ep->trs_len); - } - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_standard_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*standard_device_request[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_device_class_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret; - - switch (pudev->status) { - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* call device class handle function */ - ret = (usbd_status_enum)(pudev->class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - USBD_CONTRL_STATUS_TX(); - } - } else { - usbd_enum_error(pudev, req); - } - break; - default: - usbd_enum_error(pudev, req); - break; - } - - return USBD_OK; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -uint8_t usbd_vendor_request (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation */ -} - -#ifdef LPM_ENABLED - -static uint8_t* usbd_bos_descriptor_get (usbd_core_handle_struct *pudev, uint16_t *pLen) -{ - *pLen = pudev->bos_desc[2] | ((uint16_t)pudev->bos_desc[3] << 8); - - return pudev->bos_desc; -} - -#endif /* LPM_ENABLED */ - -/*! - \brief get the device descriptor - \param[in] pudev: pointer to USB device instance - \param[in] index: no use - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev_desc[0]; - - return pudev->dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] pudev: pointer to USB device instance - \brief[in] index: no use - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->config_desc[2]; - - return pudev->config_desc; -} - -/*! - \brief get string descriptor - \param[in] pudev: pointer to USB device instance - \param[in] index: string descriptor index - \param[out] pLen: pointer to string length - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usbd_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr; - uint16_t config_status = 0x0000U; - uint16_t endp_status = 0x0000U; - - switch(req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - -#ifdef USBD_SELF_POWERED - config_status = USB_STATUS_SELF_POWERED; -#endif /* USBD_SELF_POWERED */ - - if (pudev->remote_wakeup) { - config_status |= USB_STATUS_REMOTE_WAKEUP; - } - - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&config_status, 2U); - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get enndpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - if ((ep_addr & 0x80U) == 0x80U) { - if(pudev->in_ep[ep_addr & 0x7FU].stall) { - endp_status = 0x0001U; - } - } else { - if (pudev->out_ep[ep_addr].stall) { - endp_status = 0x0001U; - } - } - usbd_ep_tx(pudev, EP0_IN, (uint8_t *)&endp_status, 2U); - break; - - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clearfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - /* clear device remote wakeup feature */ - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->remote_wakeup = 0U; - pudev->class_req_handler(pudev, req); - USBD_CONTRL_STATUS_TX(); - } else if (USB_FEATURE_TEST_MODE == req->wValue) { - /* can not clear test_mode feature */ - usbd_enum_error(pudev, req); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error (pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get endpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - /* clear endpoint halt feature */ - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - } - } - - pudev->class_req_handler(pudev, req); - - USBD_CONTRL_STATUS_TX(); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQ_RECIPIENT_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->status) { - case USBD_ADDRESSED: - case USBD_CONFIGURED: - /* set device remote wakeup feature */ - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->remote_wakeup = 1U; - - USBD_CONTRL_STATUS_TX(); - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - /* get endpoint address */ - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->status) { - case USBD_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_enum_error(pudev, req); - } - break; - case USBD_CONFIGURED: - /* set endpoint halt feature */ - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - USBD_CONTRL_STATUS_TX(); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if ((0U == req->wIndex) && (0U == req->wLength)) { - g_device_address = (uint8_t)(req->wValue) & 0x7FU; - - if (USBD_CONFIGURED == pudev->status) { - usbd_enum_error(pudev, req); - } else { - USBD_CONTRL_STATUS_TX(); - - if (0U != g_device_address) { - pudev->status = USBD_ADDRESSED; - } else { - pudev->status = USBD_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { - uint8_t *pbuf = NULL; - uint8_t desc_index = (uint8_t)(req->wValue >> 8); - uint16_t len = 0U; - - if (desc_index <= 0x03U) { - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_index - 1U](pudev, (uint8_t)(req->wValue) & 0xFFU, &len); - } -#ifdef LPM_ENABLED - else if (USB_DESCTYPE_BOS == desc_index) { - pbuf = usbd_bos_descriptor_get(pudev, &len); - } -#endif /* LPM_ENABLED */ - else { - usbd_enum_error(pudev, req); - } - - if ((0U != len) && (0U != req->wLength)) { - len = MIN(len, req->wLength); - - usbd_ep_tx (pudev, EP0_IN, pbuf, len); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQ_RECIPIENT_MASK)) { - if (NULL != pudev->class_req_handler) { - /* get device class special descriptor */ - pudev->class_req_handler(pudev, req); - } - } else { - - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t usbd_default_config = 0U; - - if (req->wLength != 1) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_ep_tx (pudev, EP0_IN, (uint8_t *)&usbd_default_config, 1U); - break; - case USBD_CONFIGURED: - usbd_ep_tx (pudev, EP0_IN, &pudev->config_num, 1); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfiguration (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->status) { - case USBD_ADDRESSED: - if (cfgidx){ - pudev->config_num = cfgidx; - pudev->status = USBD_CONFIGURED; - pudev->class_init(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else { - USBD_CONTRL_STATUS_TX(); - } - break; - case USBD_CONFIGURED: - if (0U == cfgidx) { - pudev->status = USBD_ADDRESSED; - pudev->config_num = cfgidx; - pudev->class_deinit(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else if (cfgidx != pudev->config_num) { - /* clear old configuration */ - pudev->class_deinit(pudev, pudev->config_num); - - /* set new configuration */ - pudev->config_num = cfgidx; - pudev->class_init(pudev, cfgidx); - USBD_CONTRL_STATUS_TX(); - } else { - USBD_CONTRL_STATUS_TX(); - } - break; - default: - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - if (NULL != pudev->class_req_handler) { - pudev->class_req_handler(pudev, req); - } - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - switch (pudev->status) { - case USBD_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USBD_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - if (NULL != pudev->class_req_handler) { - pudev->class_req_handler(pudev, req); - } - - USBD_CONTRL_STATUS_TX(); - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_setup_request_parse (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *setup_data = pudev->setup_packet; - - req->bmRequestType = *setup_data; - req->bRequest = *(uint8_t *)(setup_data + 1U); - req->wValue = SWAPBYTE (setup_data + 2U); - req->wIndex = SWAPBYTE (setup_data + 4U); - req->wLength = SWAPBYTE (setup_data + 6U); - - pudev->ctl_count = req->wLength; -} - -/*! - \brief handle USB enumeration error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error (usbd_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, EP0); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_core.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_core.h deleted file mode 100644 index 4cdb2da211..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_core.h +++ /dev/null @@ -1,276 +0,0 @@ -/*! - \file usb_core.h - \brief USB core driver header file -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USB_CORE_H -#define USB_CORE_H - -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - -#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */ -#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ -#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ - -#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT -#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) - -/* USB core status */ -typedef enum -{ - USB_OK = 0, /* USB core OK status */ - USB_FAIL /* USB core fail status */ -}usb_status_enum; - -/* USB host channel status */ -typedef enum -{ - HC_IDLE = 0, /* USB host channel idle status */ - HC_XF, /* USB host channel transfer status */ - HC_HALTED, /* USB host channel halted status */ - HC_NAK, /* USB host channel nak status */ - HC_NYET, /* USB host channel nyet status */ - HC_STALL, /* USB host channel stall status */ - HC_TRACERR, /* USB host channel tracerr status */ - HC_BBERR, /* USB host channel bberr status */ - HC_DTGERR, /* USB host channel dtgerr status */ -}hc_status_enum; - -/* USB URB(USB request block) state */ -typedef enum -{ - URB_IDLE = 0, /* USB URB idle status */ - URB_DONE, /* USB URB done status */ - URB_NOTREADY, /* USB URB notready status */ - URB_ERROR, /* USB URB error status */ - URB_STALL, /* USB URB stall status */ - URB_PING /* USB URB ping status */ -}urb_state_enum; - -/* USB core configuration */ -typedef struct -{ - uint8_t core_id; /* USB core id */ - uint8_t core_speed; /* USB core speed */ - uint8_t phy_interface; /* USB PHY interface */ - uint8_t host_channel_num; /* USB host channel number */ - uint8_t dev_endp_num; /* USB device endpoint number */ - uint8_t sof_output; /* USB SOF output */ - uint8_t low_power; /* USB low power */ - uint16_t max_packet_size; /* USB max packet size */ - uint16_t max_fifo_size; /* USB fifo size */ -}usb_core_cfgs_struct; - -typedef enum -{ - USBD_OK = 0, /* USB device ok status */ - USBD_BUSY, /* USB device busy status */ - USBD_FAIL, /* USB device fail stauts */ -}usbd_status_enum; - -/* USB control transfer state */ -typedef enum -{ - USB_CTRL_IDLE = 0, /* USB control transfer idle state */ - USB_CTRL_SETUP, /* USB control transfer setup state */ - USB_CTRL_DATA_IN, /* USB control transfer data in state */ - USB_CTRL_DATA_OUT, /* USB control transfer data out state */ - USB_CTRL_STATUS_IN, /* USB control transfer status in state*/ - USB_CTRL_STATUS_OUT, /* USB control transfer status out state */ - USB_CTRL_STALL /* USB control transfer stall state */ -}usbd_control_state_enum; - -/* USB transfer direction */ -typedef enum -{ - USB_RX = 0, /* receive direction type value */ - USB_TX /* transmit direction type value */ -}usb_dir_enum; - -/* USB endpoint in device mode */ -typedef struct -{ - uint8_t endp_type; /* USB endpoint type */ - uint8_t endp_frame; /* USB endpoint frame */ - uint32_t endp_mps; /* USB endpoint max packet size */ - - /* Transaction level variables */ - uint8_t *xfer_buff; /* USB transfer buffer */ - uint32_t xfer_len; /* USB transfer length */ - uint32_t xfer_count; /* USB transfer count */ - - uint32_t dma_addr; /* USBHS can use DMA */ -}usb_ep_struct; - -/* USB device standard request */ -typedef struct -{ - uint8_t bmRequestType; /* USB device request type */ - uint8_t bRequest; /* USB device request */ - uint16_t wValue; /* USB device request value */ - uint16_t wIndex; /* USB device request index */ - uint16_t wLength; /* USB device request length */ -}usb_device_req_struct; - -/* USB core device driver */ -typedef struct -{ - uint8_t config_num; /* USB configuration number */ - uint8_t status; /* USB status */ - uint8_t ctl_status; /* USB control status */ - uint8_t prev_status; /* USB previous status */ - uint8_t connection_status; /* USB connection status */ - uint32_t remote_wakeup; /* USB remote wakeup */ - - /* transfer level variables */ - uint32_t remain_len; /* USB remain length */ - uint32_t sum_len; /* USB sum length */ - uint32_t ctl_len; /* USB control length */ - uint8_t setup_packet[8 * 3]; /* USB setup packet */ - - usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB IN endpoint */ - usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB OUT endpoint */ - - uint8_t *dev_desc; /* device descriptor */ - uint8_t *config_desc; /* configuration descriptor */ - uint8_t* *strings; /* configuration strings */ - - /* device class handler */ - uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ - uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ - uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ - uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */ -}dcd_dev_struct; - -/* USB core host mode channel */ -typedef struct -{ - uint8_t dev_addr; /* device address */ - uint8_t dev_speed; /* device speed */ - uint8_t DPID; /* endpoint transfer data pid */ - uint8_t endp_id; /* endpoint number */ - uint8_t endp_in; /* endpoint in */ - uint8_t endp_type; /* endpoint type */ - uint16_t endp_mps; /* endpoint max pactet size */ - uint16_t info; /* channel information */ - - uint8_t *xfer_buff; /* transfer buffer */ - uint32_t xfer_len; /* transfer length */ - uint32_t xfer_count; /* trasnfer count */ - - uint32_t err_count; /* USB transfer error count */ - - hc_status_enum status; /* channel status */ - urb_state_enum urb_state; /* URB state */ - - uint8_t data_tg_in; /* data in toggle */ - uint8_t data_tg_out; /* data out toggle */ -}usb_hostchannel_struct; - -/* USB core host driver */ -typedef struct -{ - uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */ - uint8_t connect_status; /* device connect status */ - usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */ - void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */ -}hcd_dev_struct; - -#ifdef USE_OTG_MODE - -/* USB core OTG-mode driver */ -typedef struct -{ - uint8_t OTG_State; /* OTG state */ - uint8_t OTG_PrevState; /* OTG previous state */ - uint8_t OTG_Mode; /* OTG mode */ -}otg_dev_struct; - -#endif /* USE_OTG_MODE */ - -/* USB core driver */ -typedef struct -{ - usb_core_cfgs_struct cfg; - -#ifdef USE_DEVICE_MODE - dcd_dev_struct dev; -#endif /* USE_DEVICE_MODE */ - -#ifdef USE_HOST_MODE - hcd_dev_struct host; -#endif /* USE_HOST_MODE */ - -#ifdef USE_OTG_MODE - otg_dev_struct otg; -#endif /* USE_OTG_MODE */ - - void (*udelay) (const uint32_t usec); - void (*mdelay) (const uint32_t msec); -}usb_core_handle_struct; - -/* function declarations */ - -/* global APIs */ -/* initializes the USB controller registers and prepares the core device mode or host mode operation */ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev); -/* initialize core parameters */ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* read a packet from the Rx FIFO associated with the endpoint */ -void* usb_fifo_read (uint8_t *dest, uint16_t len); -/* write a packet into the Tx FIFO associated with the endpoint */ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len); -/* flush a Tx FIFO or all Tx FIFOs */ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); -/* flush the entire Rx FIFO */ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev); -/* set operation mode (host or device) */ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode); - -/* host APIs */ -#ifdef USE_HOST_MODE - -/* initializes USB core for host mode */ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev); -/* enables the host mode interrupts */ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev); -/* initialize host channel */ -usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num); -/* halt channel */ -usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); -/* prepare host channel for transferring packets */ -usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); -/* reset host port */ -uint32_t usb_port_reset (usb_core_handle_struct *pudev); -/* control the VBUS to power */ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state); -/* stop the USB host and clean up fifos */ -void usb_host_stop (usb_core_handle_struct *pudev); - -#endif /* USE_HOST_MODE */ - -/* device APIs */ -#ifdef USE_DEVICE_MODE - -/* initialize USB core registers for device mode */ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev); -/* configures endpoint 0 to receive SETUP packets */ -void usb_ep0_startout (usb_core_handle_struct *pudev); -/* active remote wakeup signalling */ -void usb_remotewakeup_active (usb_core_handle_struct *pudev); -/* active USB core clock */ -void usb_clock_ungate (usb_core_handle_struct *pudev); -/* stop the device and clean up fifos */ -void usb_device_stop (usb_core_handle_struct *pudev); - -#endif /* USE_DEVICE_MODE */ - -#endif /* USB_CORE_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_defines.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_defines.h deleted file mode 100644 index fec5a35019..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_defines.h +++ /dev/null @@ -1,100 +0,0 @@ -/*! - \file usb_defines.h - \brief USB core defines -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USB_DEFINES_H -#define USB_DEFINES_H - -#include "usb_conf.h" - -#ifndef NULL - #define NULL (void *)0 /*!< USB null marco value*/ -#endif /* NULL */ - -#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */ -#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */ - -#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */ -#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */ -#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */ -#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */ - -#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */ -#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */ -#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */ -#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */ - -#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */ -#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */ - -#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ -#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ - -#define GRSTATR_RPCKST_IN 2U /* IN data packet received */ -#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */ - -#define DEVICE_MODE 0U /* USB core in device mode */ -#define HOST_MODE 1U /* USB core in host mode */ -#define OTG_MODE 2U /* USB core in OTG mode */ - -#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */ -#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */ -#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */ -#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */ -#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */ - -#define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ -#define RXSTAT_DATA_UPDT 2U /* OUT data packet received */ -#define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ -#define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ -#define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */ - -#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ -#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ -#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ -#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ - -#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */ -#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */ -#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */ -#define HC_PID_SETUP 3U /* host channel data PID is SETUP */ - -#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */ -#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */ -#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */ - -#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */ -#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */ -#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */ - -#define HCCHAR_CTRL 0U /* control channel type */ -#define HCCHAR_ISOC 1U /* synchronous channel type */ -#define HCCHAR_BULK 2U /* bulk channel type */ -#define HCCHAR_INTR 3U /* interrupt channel type */ - -typedef enum -{ - USB_HS_CORE_ID = 0, - USB_FS_CORE_ID = 1 -}usb_core_id_enum; - -typedef enum -{ - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}usb_speed_enum; - -#endif /* USB_DEFINES_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_regs.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_regs.h deleted file mode 100644 index 253d5856e6..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_regs.h +++ /dev/null @@ -1,630 +0,0 @@ -/*! - \file usb_regs.h - \brief USB FS cell registers definition and handle macros -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USB_REGS_H -#define USB_REGS_H - -#include "usb_conf.h" - -#define USBFS USBFS_BASE /*!< base address of USBFS registers */ - -/* registers location definitions */ -#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device IN endpoint-x transfer length registers */ -#define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ -#define LOCATE_HCHSTCTL(x) (0x504U + 0x20U * (x)) /*!< locate host channel-x split transaction control registers */ -#define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ -#define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ -#define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ -#define LOCATE_HCHDMAADDR(x) (0x514U + 0x20U * (x)) /*!< locate host channel-x DMA address registers */ -#define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device IN endpoint-x control registers */ -#define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device OUT endpoint-x control registers */ -#define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device IN endpoint-x interrupt flag registers */ -#define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device OUT endpoint-x interrupt flag registers */ -#define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device IN endpoint-x transfer length registers */ -#define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device OUT endpoint-x transfer length registers */ -#define LOCATE_DIEPxDMAADDR(x) (0x914U + 0x20U * (x)) /*!< locate device IN endpoint-x DMA address registers */ -#define LOCATE_DOEPxDMAADDR(x) (0xB14U + 0x20U * (x)) /*!< locate device OUT endpoint-x DMA address registers */ -#define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device IN endpoint-x transmit FIFO status register */ -#define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ - -/* registers definitions */ -#define USB_GOTGCS REG32(((USBFS) + 0x0000U)) /*!< global OTG control and status register */ -#define USB_GOTGINTF REG32(((USBFS) + 0x0004U)) /*!< global OTG interrupt flag register */ -#define USB_GAHBCS REG32(((USBFS) + 0x0008U)) /*!< global AHB control and status register */ -#define USB_GUSBCS REG32(((USBFS) + 0x000CU)) /*!< global USB control and status register */ -#define USB_GRSTCTL REG32(((USBFS) + 0x0010U)) /*!< global reset control register */ -#define USB_GINTF REG32(((USBFS) + 0x0014U)) /*!< global interrupt flag register */ -#define USB_GINTEN REG32(((USBFS) + 0x0018U)) /*!< global interrupt enable register */ -#define USB_GRSTATR REG32(((USBFS) + 0x001CU)) /*!< global receive status read register */ -#define USB_GRSTATP REG32(((USBFS) + 0x0020U)) /*!< global receive status read and pop register */ -#define USB_GRFLEN REG32(((USBFS) + 0x0024U)) /*!< global receive FIFO length register */ -#define USB_HNPTFLEN REG32(((USBFS) + 0x0028U)) /*!< host non-periodic transmit FIFO length register */ -#define USB_DIEP0TFLEN REG32(((USBFS) + 0x0028U)) /*!< device IN endpoint 0 transmit FIFO length register */ -#define USB_HNPTFQSTAT REG32(((USBFS) + 0x002CU)) /*!< host non-periodic transmint FIFO/queue status register */ -#define USB_GCCFG REG32(((USBFS) + 0x0038U)) /*!< global core configuration register */ -#define USB_CID REG32(((USBFS) + 0x003CU)) /*!< core id register */ -#define USB_HPTFLEN REG32(((USBFS) + 0x0100U)) /*!< host periodic transmit FIFO length register */ -#define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x))) /*!< device IN endpoint transmit FIFO length register */ - -#define USB_HCTL REG32(((USBFS) + 0x0400U)) /*!< host control register */ -#define USB_HFT REG32(((USBFS) + 0x0404U)) /*!< host frame interval register */ -#define USB_HFINFR REG32(((USBFS) + 0x0408U)) /*!< host frame information remaining register */ -#define USB_HPTFQSTAT REG32(((USBFS) + 0x0410U)) /*!< host periodic transmit FIFO/queue status register */ -#define USB_HACHINT REG32(((USBFS) + 0x0414U)) /*!< host all channels interrupt register */ -#define USB_HACHINTEN REG32(((USBFS) + 0x0418U)) /*!< host all channels interrupt enable register */ -#define USB_HPCS REG32(((USBFS) + 0x0440U)) /*!< host port control and status register */ -#define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ -#define USB_HCHxSTCTL(x) REG32(((USBFS) + LOCATE_HCHSTCTL(x))) /*!< host channel-x split transaction control register */ -#define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ -#define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ -#define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ -#define USB_HCHxDMAADDR(x) REG32(((USBFS) + LOCATE_HCHDMAADDR(x))) /*!< host channel-x DMA address register */ - -#define USB_DCFG REG32(((USBFS) + 0x0800U)) /*!< device configuration register */ -#define USB_DCTL REG32(((USBFS) + 0x0804U)) /*!< device control register */ -#define USB_DSTAT REG32(((USBFS) + 0x0808U)) /*!< device status register */ -#define USB_DIEPINTEN REG32(((USBFS) + 0x0810U)) /*!< device IN endpoint common interrupt enable register */ -#define USB_DOEPINTEN REG32(((USBFS) + 0x0814U)) /*!< device OUT endpoint common interrupt enable register */ -#define USB_DAEPINT REG32(((USBFS) + 0x0818U)) /*!< device all endpoints interrupt register */ -#define USB_DAEPINTEN REG32(((USBFS) + 0x081CU)) /*!< device all endpoints interrupt enable register */ -#define USB_DVBUSDT REG32(((USBFS) + 0x0828U)) /*!< device vbus discharge time register */ -#define USB_DVBUSPT REG32(((USBFS) + 0x082CU)) /*!< device vbus pulsing time register */ -#define USB_DIEPFEINTEN REG32(((USBFS) + 0x0834U)) /*!< device IN endpoint FIFO empty interrupt enable register */ -#define USB_DEP1INT REG32(((USBFS) + 0x0838U)) /*!< device endpoint 1 interrupt register */ -#define USB_DEP1INTEN REG32(((USBFS) + 0x083CU)) /*!< device endpoint 1 interrupt enable register */ -#define USB_DIEP1INTEN REG32(((USBFS) + 0x0844U)) /*!< device IN endpoint 1 interrupt enable register */ -#define USB_DOEP1INTEN REG32(((USBFS) + 0x0884U)) /*!< device OUT endpoint 1 interrupt enable register */ -#define USB_DIEP0CTL REG32(((USBFS) + 0x0900U)) /*!< device IN endpoint 0 control register */ -#define USB_DIEP0LEN REG32(((USBFS) + 0x0910U)) /*!< device IN endpoint 0 transfer length register */ -#define USB_DOEP0CTL REG32(((USBFS) + 0x0B00U)) /*!< device OUT endpoint 0 control register */ -#define USB_DOEP0LEN REG32(((USBFS) + 0x0B10U)) /*!< device OUT endpoint 0 transfer length register */ -#define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x))) /*!< device IN endpoint-x control register */ -#define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x))) /*!< device OUT endpoint-x control register */ -#define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x))) /*!< device IN endpoint-x interrupt flag register */ -#define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x))) /*!< device OUT endpoint-x interrupt flag register */ -#define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x))) /*!< device IN endpoint-x transfer length register */ -#define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x))) /*!< device OUT endpoint-x transfer length register */ -#define USB_DIEPxDMAADDR(x) REG32(((USBFS) + LOCATE_DIEPxDMAADDR(x)))/*!< device IN endpoint-x DMA address register */ -#define USB_DOEPxDMAADDR(x) REG32(((USBFS) + LOCATE_DOEPxDMAADDR(x)))/*!< device OUT endpoint-x DMA address register */ -#define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x))) /*!< device IN endpoint-x transmit FIFO status register */ - -#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U)) /*!< power and clock register */ - -#define USB_FIFO(x) (®32(((USBFS) + LOCATE_FIFO(x)))) /*!< FIFO memory */ - -/* global OTG control and status register bits definitions */ -#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ -#define GOTGCS_ASV BIT(18) /*!< A-session valid */ -#define GOTGCS_DI BIT(17) /*!< debounce interval */ -#define GOTGCS_CIDPS BIT(16) /*!< id pin status */ -#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ -#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ -#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ -#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ -#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ -#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ - -/* global OTG interrupt flag register bits definitions */ -#define GOTGINTF_DF BIT(19) /*!< debounce finish */ -#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ -#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ -#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ -#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ -#define GOTGINTF_SESEND BIT(2) /*!< session end */ - -/* global AHB control and status register bits definitions */ -#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ -#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ -#define GAHBCS_DMAEN BIT(5) /*!< DMA function Enable */ -#define GAHBCS_BURST BITS(1, 4) /*!< the AHB burst type used by DMA */ -#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ - -/* global USB control and status register bits definitions */ -#define GUSBCS_FDM BIT(30) /*!< force device mode */ -#define GUSBCS_FHM BIT(29) /*!< force host mode */ -#define GUSBCS_ULPIEOI BIT(21) /*!< ULPI external over-current indicator */ -#define GUSBCS_ULPIEVD BIT(20) /*!< ULPI external VBUS driver */ -#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ -#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ -#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ -#define GUSBCS_EMBPHY BIT(6) /*!< embedded PHY selected */ -#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ - -/* global reset control register bits definitions */ -#define GRSTCTL_DMAIDL BIT(31) /*!< DMA idle state */ -#define GRSTCTL_DMABSY BIT(30) /*!< DMA busy */ -#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ -#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ -#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ -#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ -#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ -#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ - -/* global interrupt flag register bits definitions */ -#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ -#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ -#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ -#define GINTF_IDPSC BIT(28) /*!< id pin status change */ -#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ -#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ -#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ -#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ -#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ -#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ -#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ -#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ -#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ -#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ -#define GINTF_ENUMFIF BIT(13) /*!< enumeration finished */ -#define GINTF_RST BIT(12) /*!< USB reset */ -#define GINTF_SP BIT(11) /*!< USB suspend */ -#define GINTF_ESP BIT(10) /*!< early suspend */ -#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ -#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ -#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ -#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ -#define GINTF_SOF BIT(3) /*!< start of frame */ -#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ -#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ -#define GINTF_COPM BIT(0) /*!< current operation mode */ - -/* global interrupt enable register bits definitions */ -#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ -#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ -#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ -#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ -#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ -#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ -#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ -#define GINTEN_IPXIE BIT(21) /*!< periodic transfer not complete interrupt enable */ -#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ -#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ -#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ -#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ -#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ -#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ -#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ -#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ -#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ -#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ -#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ -#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ -#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ -#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ -#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ -#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ -#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ - -/* global receive status read and pop register bits definitions */ -#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ -#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ - -/* global receive FIFO length register bits definitions */ -#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ - -/* host non-periodic transmit FIFO length register bits definitions */ -#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ -#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ - -/* IN endpoint 0 transmit FIFO length register bits definitions */ -#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ -#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ - -/* host non-periodic transmit FIFO/queue status register bits definitions */ -#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ -#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ -#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ -#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ -#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* global core configuration register bits definitions */ -#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ -#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ -#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ -#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ -#define GCCFG_PWRON BIT(16) /*!< power on */ - -/* core ID register bits definitions */ -#define CID_CID BITS(0, 31) /*!< core ID */ - -/* host periodic transmit FIFO length register bits definitions */ -#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ -#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ - -/* device IN endpoint transmit FIFO length register bits definitions */ -#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ -#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ - -/* host control register bits definitions */ -#define HCTL_SPDFSLS BIT(2) /*!< speed limited to FS and LS */ -#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ - -/* host frame interval register bits definitions */ -#define HFT_FRI BITS(0, 15) /*!< frame interval */ - -/* host frame information remaining register bits definitions */ -#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ -#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ - -/* host periodic transmit FIFO/queue status register bits definitions */ -#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ -#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ -#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ -#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ -#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ -#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* host all channels interrupt register bits definitions */ -#define HACHINT_HACHINT BITS(0, 11) /*!< host all channel interrupts */ - -/* host all channels interrupt enable register bits definitions */ -#define HACHINTEN_CINTEN BITS(0, 11) /*!< channel interrupt enable */ - -/* host port control and status register bits definitions */ -#define HPCS_PS BITS(17, 18) /*!< port speed */ -#define HPCS_PP BIT(12) /*!< port power */ -#define HPCS_PLST BITS(10, 11) /*!< port line status */ -#define HPCS_PRST BIT(8) /*!< port reset */ -#define HPCS_PSP BIT(7) /*!< port suspend */ -#define HPCS_PREM BIT(6) /*!< port resume */ -#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ -#define HPCS_PE BIT(2) /*!< port enable */ -#define HPCS_PCD BIT(1) /*!< port connect detected */ -#define HPCS_PCST BIT(0) /*!< port connect status */ - -/* host channel-x control register bits definitions */ -#define HCHCTL_CEN BIT(31) /*!< channel enable */ -#define HCHCTL_CDIS BIT(30) /*!< channel disable */ -#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ -#define HCHCTL_DAR BITS(22, 28) /*!< device address */ -#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ -#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define HCHCTL_LSD BIT(17) /*!< low-speed device */ -#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ -#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ -#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* host channel-x split transaction register bits definitions */ -#define HCHSTCTL_SPLEN BIT(31) /*!< enable high-speed split transaction */ -#define HCHSTCTL_CSPLT BIT(16) /*!< complete-split enable */ -#define HCHSTCTL_ISOPCE BITS(14, 15) /*!< isochronous OUT payload continuation encoding */ -#define HCHSTCTL_HADDR BITS(7, 13) /*!< HUB address */ -#define HCHSTCTL_PADDR BITS(0, 6) /*!< port address */ - -/* host channel-x interrupt flag register bits definitions */ -#define HCHINTF_DTER BIT(10) /*!< data toggle error */ -#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ -#define HCHINTF_BBER BIT(8) /*!< babble error */ -#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ -#define HCHINTF_NYET BIT(6) /*!< NYET */ -#define HCHINTF_ACK BIT(5) /*!< ACK */ -#define HCHINTF_NAK BIT(4) /*!< NAK */ -#define HCHINTF_STALL BIT(3) /*!< STALL */ -#define HCHINTF_DMAER BIT(2) /*!< DMA error */ -#define HCHINTF_CH BIT(1) /*!< channel halted */ -#define HCHINTF_TF BIT(0) /*!< transfer finished */ - -/* host channel-x interrupt enable register bits definitions */ -#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ -#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ -#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ -#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ -#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ -#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ -#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ -#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ -#define HCHINTEN_DMAERIE BIT(2) /*!< DMA error interrupt enable */ -#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ -#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ - -/* host channel-x transfer length register bits definitions */ -#define HCHLEN_PING BIT(31) /*!< PING token request */ -#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ -#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ -#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* host channel-x DMA address register bits definitions */ -#define HCHDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - -/* device control and status registers */ -/* device configuration registers bits definitions */ -#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ -#define DCFG_DAR BITS(4, 10) /*!< device address */ -#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ -#define DCFG_DS BITS(0, 1) /*!< device speed */ - -/* device control registers bits definitions */ -#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ -#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ -#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ -#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ -#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ -#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ -#define DCTL_GINS BIT(2) /*!< global IN NAK status */ -#define DCTL_SD BIT(1) /*!< soft disconnect */ -#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ - -/* device status registers bits definitions */ -#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ -#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ -#define DSTAT_SPST BIT(0) /*!< suspend status */ - -/* device IN endpoint common interrupt enable registers bits definitions */ -#define DIEPINTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ -#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ -#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ -#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ -#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ -#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device OUT endpoint common interrupt enable registers bits definitions */ -#define DOEPINTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ -#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ -#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ -#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ -#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device all endpoints interrupt registers bits definitions */ -#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ -#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ - -/* device all endpoints interrupt enable registers bits definitions */ -#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ -#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ - -/* device Vbus discharge time registers bits definitions */ -#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ - -/* device Vbus pulsing time registers bits definitions */ -#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ - -/* device IN endpoint FIFO empty interrupt enable register bits definitions */ -#define DIEPFEINTEN_IEPTXFEIE BITS(0, 5) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ - -/* device endpoint 1 interrupt register bits definitions */ -#define DEP1INT_OEP1INT BIT(17) /*!< OUT Endpoint 1 interrupt */ -#define DEP1INT_IEP1INT BIT(1) /*!< IN Endpoint 1 interrupt */ - -/* device endpoint 1 interrupt register enable bits definitions */ -#define DEP1INTEN_OEP1INTEN BIT(17) /*!< OUT Endpoint 1 interrupt enable */ -#define DEP1INTEN_IEP1INTEN BIT(1) /*!< IN Endpoint 1 interrupt enable */ - -/* device IN endpoint 1 interrupt enable register bits definitions */ -#define DIEP1INTEN_NAKEN BIT(13) /*!< NAK handshake sent by USBHS interrupt enable bit */ -#define DIEP1INTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ -#define DIEP1INTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ -#define DIEP1INTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ -#define DIEP1INTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEP1INTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device OUT endpoint 1 interrupt enable register bits definitions */ -#define DOEP1INTEN_NYETEN BIT(14) /*!< NYET handshake is sent interrupt enable bit */ -#define DOEP1INTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ -#define DOEP1INTEN_EPRXOVREN BIT(4) /*!< endpoint Rx FIFO over run interrupt enable bit */ -#define DOEP1INTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ -#define DOEP1INTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEP1INTEN_TFEN BIT(0) /*!< back-to-back SETUP packets interrupt enable bit */ - -/* device endpoint 0 control register bits definitions */ -#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DOEP0CTL_SNOOP BIT(20) /*!< snoop mode */ -#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ - -/* device endpoint x control register bits definitions */ -#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DOEPCTL_SNOOP BIT(20) /*!< snoop mode */ -#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* device IN endpoint-x interrupt flag register bits definitions */ -#define DIEPINTF_NAK BIT(13) /*!< NAK handshake sent by USBHS */ -#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ -#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ -#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ -#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ -#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DIEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device OUT endpoint-x interrupt flag register bits definitions */ -#define DOEPINTF_NYET BIT(14) /*!< NYET handshake is sent */ -#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ -#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ -#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ -#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DOEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device IN endpoint 0 transfer length register bits definitions */ -#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ -#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device OUT endpoint 0 transfer length register bits definitions */ -#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ -#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device OUT endpoint-x transfer length register bits definitions */ -#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ -#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ -#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device IN endpoint-x DMA address register bits definitions */ -#define DIEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - -/* device OUT endpoint-x DMA address register bits definitions */ -#define DOEPDMAADDR_DMAADDR BITS(0, 31) /*!< DMA address */ - -/* device IN endpoint-x transmit FIFO status register bits definitions */ -#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint¡¯s Tx FIFO space remaining */ - -/* USB power and clock registers bits definition */ -#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ -#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ - -/* register options defines */ -#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ - -#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ -#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ -#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ - -#define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */ - -#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U) /*!< Tx FIFO half empty */ -#define TXFIFO_EMPTY GAHBCS_TFEL(1U) /*!< Tx FIFO completely empty */ - -#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ - -#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ -#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ -#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ -#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ -#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ - -#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ - -#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ -#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ -#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ -#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ - -#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ - -#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ -#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ -#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ -#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ - -/* endpoints address */ - -/* first bit is direction(0 for Rx and 1 for Tx) */ -#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */ -#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */ -#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */ -#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */ -#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */ -#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */ -#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */ -#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */ - -/* enable global interrupt */ -#define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN) - -/* disable global interrupt */ -#define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN) - -/* get current operation mode */ -#define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM) - -/* read global interrupt flag */ -#define USB_CORE_INTR_READ(x) \ -do { \ - uint32_t global_intf = USB_GINTF; \ - (x) = global_intf & USB_GINTEN; \ -} while(0) - -/* read global interrupt flag */ -#define USB_DAOEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t out_ep_intb = DAEPINT_OEPITB; \ - (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ -} while(0) - -/* read out endpoint-x interrupt flag */ -#define USB_DOEP_INTR_READ(x, EpID) \ -do { \ - uint32_t out_epintf = USB_DOEPxINTF(EpID); \ - (x) = out_epintf & USB_DOEPINTEN; \ -} while(0) - -/* read all in endpoint interrupt flag */ -#define USB_DAIEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t in_ep_intb = DAEPINT_IEPITB; \ - (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ -} while(0) - - -/* read in endpoint-x interrupt flag */ -#define USB_DIEP_INTR_READ(x, EpID) \ -do { \ - uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \ - uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \ - uint32_t dev_inep_inten = USB_DIEPINTEN; \ - (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \ -} while(0) - -/* generate remote wakup signal */ -#define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP) - -/* no remote wakup signal generate */ -#define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP) - -/* generate soft disconnect */ -#define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD) - -/* no soft disconnect generate */ -#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD) - -/* set device address */ -#define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U) - -/* check whether frame is even */ -#define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U)) - -/* read port status */ -#define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC)) - -/* usb clock initialize */ -#define USB_FSLSCLOCK_INIT(ClockFreq) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq)) - -/* get usb current speed */ -#define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17) - -/* get usb current frame */ -#define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU) - -#endif /* USB_REGS_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_std.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_std.h deleted file mode 100644 index 60517f953c..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usb_std.h +++ /dev/null @@ -1,188 +0,0 @@ -/*! - \file usb_std.h - \brief USB 2.0 standard defines -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USB_STD_H -#define USB_STD_H - -#include "usb_conf.h" - -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ -#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */ -#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */ -#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */ -#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ - -/* bit 7 of bmRequestType: data phase transfer direction */ -#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */ -#define USB_DIR_OUT 0x00U /*!< USB transfer OUT direction */ -#define USB_DIR_IN 0x80U /*!< USB transfer IN direction */ - -/* bit 6..5 of bmRequestType: request type */ -#define USB_STANDARD_REQ 0x00U /*!< USB standard request */ -#define USB_CLASS_REQ 0x20U /*!< USB class request */ -#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */ -#define USB_REQ_MASK 0x60U /*!< USB request mask */ - -/* bit 4..0 of bmRequestType: recipient type */ -#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */ -#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/ -#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/ -#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/ - -/* bRequest value */ -#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/ -#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/ -#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/ -#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/ -#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/ -#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/ -#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/ -#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/ -#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/ -#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/ -#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/ - -/* descriptor types of usb specifications */ -#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/ -#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/ -#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/ -#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/ -#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/ -#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/ - -#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/ -#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/ - -#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/ -#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/ -#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/ -#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/ - -/* descriptor type and descriptor index */ -/* use the following values when USB host need to get descriptor */ -#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */ -#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */ -#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */ -#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */ -#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */ -#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */ -#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */ -#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */ -#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */ -#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */ - -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -/* supported classes */ -#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/ -#define USB_HID_CLASS 0x03U /*!< USB HID class*/ - -/* interface descriptor field values for hid boot protocol */ -#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/ -#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/ -#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/ - -/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec - standard request with no data stage timeout : 50ms */ -#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ -#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ - -#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \ - + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */ - -#pragma pack(1) - -typedef union -{ - uint8_t data[8]; - - struct _setup_packet_struct - { - uint8_t bmRequestType; /*!< type of request */ - uint8_t bRequest; /*!< request of setup packet */ - uint16_t wValue; /*!< value of setup packet */ - uint16_t wIndex; /*!< index of setup packet */ - uint16_t wLength; /*!< length of setup packet */ - } b; -}usb_setup_union; - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -#endif /* USB_STD_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_core.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_core.h deleted file mode 100644 index d8ef3baf81..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_core.h +++ /dev/null @@ -1,54 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device mode core driver header file -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usb_core.h" -#include "usbd_std.h" - -/* device status */ -#define USB_STATUS_DEFAULT 1U /* default status */ -#define USB_STATUS_ADDRESSED 2U /* addressed status */ -#define USB_STATUS_CONFIGURED 3U /* configured status */ -#define USB_STATUS_SUSPENDED 4U /* suspended status */ - -/* function declarations */ -/* initailizes the USB device-mode handler stack */ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* endpoint initialization */ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc); -/* endpoint deinitialize */ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); -/* transmit data on the control channel */ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* receive data on the control channel */ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* transmit status on the control channel */ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev); -/* receive status on the control channel */ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev); -/* set an endpoint to STALL status */ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* flushes the FIFOs */ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* get the received data length */ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_int.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_int.h deleted file mode 100644 index 8784c83cb3..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_int.h +++ /dev/null @@ -1,29 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device mode interrupt handler header file -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" - -typedef struct -{ - uint8_t (*SOF) (usb_core_handle_struct *pudev); -}usbd_int_cb_struct; - -extern usbd_int_cb_struct *usbd_int_fops; - -/* function declarations */ -/* USB device-mode interrupts global service routine handler */ -uint32_t usbd_isr (usb_core_handle_struct *pudev); - -#endif /* USBD_INT_H */ - diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_std.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_std.h deleted file mode 100644 index 2a026fb28d..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbd_std.h +++ /dev/null @@ -1,70 +0,0 @@ -/*! - \file usbd_std.h - \brief USB 2.0 standard defines -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usb_std.h" -#include "usbd_core.h" -#include "usbd_conf.h" -#include - -#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/ -#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/ -#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/ -#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/ -#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/ -#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/ - -#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/ -#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/ - -#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/ -#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/ -#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/ - -#define ENG_LANGID 0x0409U /*!< USB english language id*/ -#define CHN_LANGID 0x0804U /*!< USB chinese language id*/ - -#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/ - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/ -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/ - -#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/ - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (uint8_t *)&(struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -/* function declarations */ -/* USB device setup transaction*/ -usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev); -/* USB device out transaction*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device in transaction*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device enum error handle*/ -void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_core.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_core.h deleted file mode 100644 index dd38440499..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_core.h +++ /dev/null @@ -1,283 +0,0 @@ -/*! - \file usbh_core.h - \brief header file for usbh_core.c -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBH_CORE_H -#define USBH_CORE_H - -#include "usbh_conf.h" -#include "usb_std.h" -#include "usb_core.h" - -#define MSC_CLASS 0x08 /*!< the MSC class define */ -#define HID_CLASS 0x03 /*!< the HID class define */ -#define MSC_PROTOCOL 0x50 /*!< the MSC protocal define */ -#define CBI_PROTOCOL 0x01 /*!< the CBI protocal define */ - -#define USBH_DEVICE_ADDRESS_DEFAULT 0U /*!< the default device address define */ -#define USBH_DEVICE_ADDRESS 1U /*!< the device address define */ -#define USBH_MAX_ERROR_COUNT 2U /*!< the max error count define */ - -#define HOST_USER_SELECT_CONFIGURATION 1U /*!< the user select configuration define */ -#define HOST_USER_CLASS_ACTIVE 2U /*!< the user class active define */ -#define HOST_USER_CLASS_SELECTED 3U /*!< the user class selected define */ -#define HOST_USER_CONNECTION 4U /*!< the user connecttion define */ -#define HOST_USER_DISCONNECTION 5U /*!< the user disconnection define */ -#define HOST_USER_UNRECOVERED_ERROR 6U /*!< the user unrecovered error define */ - -#define MAX_USBH_STATE_STACK_DEEP 4 /*!< the max state stack deep define */ -#define MAX_USBH_STATE_TABLE_NUM 10U /*!< the max state table number */ - -#define HOST_FSM_ID 0U /*!< the host state table id */ -#define ENUM_FSM_ID 1U /*!< the enum state table id */ -#define CMD_FSM_ID 2U /*!< the cmd state table id */ -#define CTRL_FSM_ID 3U /*!< the ctrl state table id */ -#define CLASS_REQ_FSM_ID 4U /*!< the class req state table id */ -#define CLASS_FSM_ID 5U /*!< the class state table id */ - -#define UP_STATE 100U /*!< up state define */ -#define GO_TO_UP_STATE_EVENT 100U /*!< go to up state event define */ - -#define HOST_HANDLE_TABLE_SIZE 9U /*!< the host handle table size define */ - -/* the enum of host state */ -typedef enum -{ - HOST_IDLE = 0, /* the host idle state definition */ - HOST_DEV_ATTACHED, /* the host device attached state definition */ - HOST_DEV_DETACHED, /* the host device detached state definition */ - HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */ - HOST_ENUMERATION, /* the host enumeration state definition */ - HOST_CLASS_REQUEST, /* the host class request state definition */ - HOST_CLASS, /* the host class state definition */ - HOST_USER_INPUT, /* the host user input state definition */ - HOST_SUSPENDED, /* the host suspended state definition */ - HOST_ERROR /* the host error state definition */ -}host_state_enum; - -/* the enum of host event */ -typedef enum -{ - HOST_EVENT_ATTACHED = 0, /* the host attached event */ - HOST_EVENT_ENUM, /* the host enum event */ - HOST_EVENT_USER_INPUT, /* the host user input event */ - HOST_EVENT_CLASS_REQ, /* the host class request event */ - HOST_EVENT_CLASS, /* the host class event */ - HOST_EVENT_ERROR, /* the host error event */ - HOST_EVENT_DEV_DETACHED, /* the host device detached event */ - HOST_EVENT_IDLE /* the host idle event */ -}host_event_enum; - -/* the enum of enum state */ -typedef enum -{ - ENUM_IDLE = 0, /* the enum idle state definition */ - ENUM_SET_ADDR, /* the enum set address state definition */ - ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */ - ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */ - ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */ - ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */ - ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */ - ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */ - ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */ - ENUM_DEV_CONFIGURED /* the enum device configuration state definition */ -}enum_state_enum; - -/* the enum of ctrl state */ -typedef enum -{ - CTRL_IDLE = 0, /* the ctrl idle state definition */ - CTRL_SETUP, /* the ctrl setup state definition */ - CTRL_DATA, /* the ctrl data state definition */ - CTRL_STATUS, /* the ctrl status state definition */ - CTRL_ERROR, /* the ctrl error state definition */ - CTRL_STALLED, /* the ctrl stalled state definition */ - CTRL_COMPLETE /* the ctrl complete state definition */ -}ctrl_state_enum; - -/* the enum of host status */ -typedef enum -{ - USBH_OK = 0, /* the usbh ok status definition */ - USBH_BUSY, /* the usbh busy status definition */ - USBH_FAIL, /* the usbh fail status definition */ - USBH_NOT_SUPPORTED, /* the usbh not supported status definition */ - USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */ - USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */ - USBH_APPLY_DEINIT /* the usbh apply deinit status definition */ -}usbh_status_enum; - -/* the state of user action */ -typedef enum -{ - USBH_USER_NO_RESP = 0, /* the user no response */ - USBH_USER_RESP_OK = 1, /* the user response ok */ -}usbh_user_status_enum; - -/* control transfer information */ -typedef struct -{ - uint8_t hc_in_num; /* the host in channel number */ - uint8_t hc_out_num; /* the host out channel number */ - uint8_t ep0_size; /* the endpoint 0 max packet size */ - uint8_t error_count; /* the error count */ - uint16_t length; /* the length */ - uint16_t timer; /* the timer */ - uint8_t *buff; /* the buffer */ - usb_setup_union setup; /* the setup packet */ -}usbh_ctrl_struct; - -/* device property */ -typedef struct -{ - uint8_t address; /* the device address */ - uint8_t speed; /* the device speed */ - usb_descriptor_device_struct dev_desc; /* the device descripter */ - usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */ - usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */ - usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */ -}usbh_device_struct; - -/* user callbacks */ -typedef struct -{ - void (*init) (void); /* the user callback init function */ - void (*deinit) (void); /* the user callback deinit function */ - void (*device_connected) (void); /* the user callback device connected function */ - void (*device_reset) (void); /* the user callback device reset function */ - void (*device_disconnected) (void); /* the user callback device disconnected function */ - void (*over_current_detected) (void); /* the user callback over current detected function */ - void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */ - void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */ - void (*device_address_set) (void); /* the user callback set device address function */ - - void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct *ep_desc); - /* the configuration descripter available function */ - - void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */ - void (*product_string) (void *prod_string); /* the user callback product string function */ - void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */ - void (*enumeration_finish) (void); /* the user callback enumeration finish function */ - usbh_user_status_enum (*user_input) (void); /* the user callback user input function */ - int (*user_application) (usb_core_handle_struct *pudev, uint8_t id); - /* the user callback user appliction function */ - void (*device_not_supported) (void); /* the user callback device not supported function */ - void (*unrecovered_error) (void); /* the user callback unrecovered error function */ -}usbh_user_callback_struct; - -/* the backup state struct */ -typedef struct -{ - host_state_enum host_backup_state; /* the host backup state */ - enum_state_enum enum_backup_state; /* the enum backup state */ - ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */ - uint8_t class_req_backup_state;/* the class request backup state */ - uint8_t class_backup_state; /* the class backup state */ -} backup_state_struct; - -/* host information */ -typedef struct -{ - backup_state_struct usbh_backup_state; /* the usbh backup state variable */ - usbh_ctrl_struct control; /* the control struct variable */ - usbh_device_struct device; /* the device struct variable */ - usbh_user_callback_struct *usr_cb; /* the user callback function */ - usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */ - void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */ -}usbh_host_struct; - -/* the action function definition */ -typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate); - -/* the state table struct */ -typedef struct -{ - uint8_t cur_state; /* the current state */ - uint8_t cur_event; /* the current event */ - uint8_t next_state; /* the next state */ - ACT_FUN event_action_fun; /* the event action function entry */ -} state_table_struct; - -/* the state stack struct */ -typedef struct -{ - uint8_t state; /* the state in state stack */ - state_table_struct* table; /* the table in state stack */ - uint8_t table_size; /* the table size in state stack */ -} usbh_state_stack_struct; - -/* the state regist table struct */ -typedef struct -{ - uint8_t id; /* the id of the state table */ - state_table_struct* table; /* the table entry to regist */ - uint8_t table_size; /* the table size to regist */ -} usbh_state_regist_table_struct; - -/* the state handle struct */ -typedef struct -{ - uint8_t usbh_current_state; /* current state */ - uint8_t usbh_current_state_table_size; /* current state table size */ - state_table_struct* usbh_current_state_table; /* current state table */ - - usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */ - int8_t usbh_current_state_stack_top; /* the current state top */ - - usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */ - uint8_t usbh_regist_state_table_num; /* the number of regist state table */ -} usbh_state_handle_struct; - -/* function declarations */ -/* the host core driver function */ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* initialize the host portion of the driver */ -uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* check if the device is connected */ -uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev); -/* this function returns the last URBstate */ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* this function returns the last URBstate */ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* de-initialize host */ -usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate); - -/* the state core driver function */ -/* state core driver init */ -void scd_init (usbh_state_handle_struct* pustate); -/* state core driver table regist */ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size); -/* state core driver begin */ -void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id); -/* state core driver move state */ -void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state); -/* state core driver event handle */ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state); -/* state core driver table push */ -void scd_table_push (usbh_state_handle_struct* pustate); -/* state core driver table pop */ -void scd_table_pop (usbh_state_handle_struct* pustate); -/* the function is only used to state move */ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* the function to the up state */ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -#endif /* USBH_CORE_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_ctrl.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_ctrl.h deleted file mode 100644 index 1d866dfed1..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_ctrl.h +++ /dev/null @@ -1,45 +0,0 @@ -/*! - \file usbh_ctrl.h - \brief header file for usbh_ctrl.c -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBH_CTRL_H -#define USBH_CTRL_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ - -extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; -extern uint8_t ctrl_polling_handle_flag; - -/* the enum of CTRL event */ -typedef enum -{ - CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ - CTRL_EVENT_SETUP, /* the ctrl setup event */ - CTRL_EVENT_DATA, /* the ctrl data event */ - CTRL_EVENT_STATUS, /* the ctrl status event */ - CTRL_EVENT_COMPLETE, /* the ctrl complete event */ - CTRL_EVENT_ERROR, /* the ctrl error event */ - CTRL_EVENT_STALLED, /* the ctrl stalled event */ -}ctrl_event_enum; - -/* function declarations */ -/* the polling function of control transfer state handle */ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* send datas from the host channel */ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); -/* send the setup packet to the device */ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); -/* this function prepare a hc and start a transfer */ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); - -#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_hcs.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_hcs.h deleted file mode 100644 index 57aa4dc226..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_hcs.h +++ /dev/null @@ -1,46 +0,0 @@ -/*! - \file usbh_hcs.h - \brief header file for usbh_hcs.c -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBH_HCS_H -#define USBH_HCS_H - -#include "usbh_core.h" - -#define HC_MAX 8U - -#define HC_OK 0x0000U -#define HC_USED 0x8000U -#define HC_ERROR 0xFFFFU -#define HC_USED_MASK 0x7FFFU - -/* function declarations */ -/* allocate a new channel for the pipe */ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* free all usb host channel */ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); -/* free the usb host channel */ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); -/* open a channel */ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); -/* modify a channel */ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); - -#endif /* USBH_HCS_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_int.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_int.h deleted file mode 100644 index dade4f3d9c..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_int.h +++ /dev/null @@ -1,30 +0,0 @@ -/*! - \file usbh_int.h - \brief USB host mode interrupt handler header file -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBH_INT_H -#define USBH_INT_H - -#include "usb_core.h" - -typedef struct -{ - uint8_t (*sof) (usb_core_handle_struct *pudev); - uint8_t (*device_connected) (usb_core_handle_struct *pudev); - uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); -}usbh_hcd_int_cb_struct; - -extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; - -/* function declarations */ -/* handle global host interrupt */ -uint32_t usbh_isr (usb_core_handle_struct *pudev); - -#endif /* USBH_INT_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_std.h b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_std.h deleted file mode 100644 index 0165d933ce..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Include/usbh_std.h +++ /dev/null @@ -1,74 +0,0 @@ -/*! - \file usbh_std.h - \brief header file for usbh_std.c -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#ifndef USBH_STD_H -#define USBH_STD_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -/* standard feature selector for clear feature command */ -#define FEATURE_SELECTOR_ENDPOINT 0x00U -#define FEATURE_SELECTOR_DEVICE 0x01U - -#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */ -#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */ - -extern uint8_t usbh_cfg_desc[512]; -extern uint8_t enum_polling_handle_flag; -extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]; - -typedef enum -{ - ENUN_EVENT_IDLE = 0, /* the enum idle event */ - ENUM_EVENT_SET_ADDR, /* the enum set address event */ - ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */ - ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */ - ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */ - ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */ - ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */ - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */ - ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */ - ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */ -}enum_event_enum; - -/* function declarations */ -/* the polling function of enumeration state */ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* get descriptor in usb host enumeration stage */ -void usbh_enum_desc_get (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len); -/* set address in usb host enumeration stage */ -void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address); -/* set configuration in usb host enumeration stage */ -void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx); -/* parse the device descriptor */ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len); -/* parse the configuration descriptor */ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len); -/* parse the interface descriptor */ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf); -/* parse the endpoint descriptor */ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf); -/* parse the string descriptor */ -void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); -/* get the next descriptor header */ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr); - -#endif /* USBH_STD_H */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usb_core.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usb_core.c deleted file mode 100644 index bcf3e94f3f..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usb_core.c +++ /dev/null @@ -1,935 +0,0 @@ -/*! - \file usb_core.c - \brief USB core driver which can operate in host-mode and device-mode -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usb_core.h" - -static void usb_commonint_enable (usb_core_handle_struct *pudev); -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev); - -/*! - \brief enable the commmon interrupts which are used in both device and host modes - \param[in] pudev: pointer to selected usb device - \param[out] none - \retval none -*/ -static void usb_commonint_enable (usb_core_handle_struct *pudev) -{ -#ifndef USE_OTG_MODE - - /* clear any pending USB interrupts */ - USB_GOTGINTF = 0xFFFFFFFFU; - -#endif /* USE_OTG_MODE */ - - /* enable the usb wakeup and suspend interrupts */ - USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; - -#ifdef USE_OTG_MODE - - /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */ - USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; - -#endif /* USE_OTG_MODE */ -} - -/*! - \brief soft reset of the OTG_FS core - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - /* enable core soft reset */ - USB_GRSTCTL |= GRSTCTL_CSRST; - - /* wait for the core to be soft reset */ - do { - if (++count > 200000U) { - break; - } - } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST)); - - /* wait for addtional 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief write a packet into the Tx FIFO associated with the endpoint - \param[in] src: pointer to source buffer - \param[in] chep_num: channel or endpoint identifier which is in (0..3) - \param[in] len: packet length - \param[out] none - \retval operation status -*/ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len) -{ - uint32_t count32b = 0U, i = 0U; - __IO uint32_t *fifo = USB_FIFO(chep_num); - - count32b = (len + 3U) / 4U; - - for (i = 0U; i < count32b; i++) { - *fifo = *((__packed uint32_t *)src); - - src += 4U; - } - - return USB_OK; -} - -/*! - \brief read a packet from the Rx FIFO associated with the endpoint - \param[in] dest: pointer to destination buffer - \param[in] len: packet length - \param[out] none - \retval void type pointer -*/ -void *usb_fifo_read (uint8_t *dest, uint16_t len) -{ - uint32_t i = 0U; - uint32_t count32b = (len + 3U) / 4U; - - __IO uint32_t *fifo = USB_FIFO(0U); - - for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = *fifo; - - dest += 4U; - } - - return ((void *)dest); -} - -/*! - \brief initialize core parameters - \param[in] pudev: pointer to usb device - \param[in] core_id: USB core id - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* at startup the core is in FS mode */ - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - /* initialize the core parameters */ - if (USB_FS_CORE_ID == core_id) { - - pudev->cfg.core_id = USB_FS_CORE_ID; - - /* set the host channel numbers */ - pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT; - - /* set the device endpoint numbers */ - pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT; - - /* fifo size is in terms of DWORD */ - pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN; - - /* OTG_FS core use embedded physical layer */ - pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; - - #ifdef USBFS_SOF_OUTPUT_ENABLED - pudev->cfg.sof_output = 1U; - #endif /* USBFS_SOF_OUTPUT_ENABLED */ - - #ifdef USBFS_LOW_PWR_MGMT_SUPPORT - pudev->cfg.low_power = 1U; - #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ - } - - return USB_OK; -} - -/*! - \brief initializes the USB controller registers and - prepares the core device mode or host mode operation - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev) -{ - /* soft reset the core */ - usb_core_reset(pudev); - - /* active the transceiver and enable vbus sensing */ - USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - - /* set Tx FIFO empty level to half empty mode */ - USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; - -#ifndef VBUS_SENSING_ENABLED - USB_GCCFG |= GCCFG_VBUSIG; -#endif /* VBUS_SENSING_ENABLED */ - - if (pudev->cfg.sof_output) { - USB_GCCFG |= GCCFG_SOFOEN; - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - -#ifdef USE_OTG_MODE - /* enable OTG features */ - USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; - USB_OTG_EnableCommonInt(pudev); - -#endif /* USE_OTG_MODE */ - - return USB_OK; -} - -/*! - \brief flush a Tx FIFO or all Tx FIFOs - \param[in] pudev: pointer to usb device - \param[in] fifo_num: FIFO number which is in (0..3) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num) -{ - uint32_t count = 0U; - - USB_GRSTCTL &= ~GRSTCTL_TXFNUM; - USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; - - /* wait for Tx FIFO flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_TXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief flush the entire Rx FIFO - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - USB_GRSTCTL = GRSTCTL_RXFF; - - /* wait for Rx FIFO flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_RXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief set operation mode (host or device) - \param[in] pudev: pointer to usb device - \param[in] mode: operation mode which need to set - \arg HOST_MODE - \arg DEVICE_MODE - \param[out] none - \retval operation status -*/ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) -{ - if (HOST_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FDM; - USB_GUSBCS |= GUSBCS_FHM; - } else if (DEVICE_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FHM; - USB_GUSBCS |= GUSBCS_FDM; - } else { - /* no operation */ - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(50U); - } - - return USB_OK; -} - -#ifdef USE_HOST_MODE - -/*! - \brief initializes USB core for host mode - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i = 0U; - __IO uint32_t nptxfifolen = 0U; - __IO uint32_t ptxfifolen = 0U; - -#ifdef USE_OTG_MODE - __IO uint32_t otgctl = 0; -#endif /* USE_OTG_MODE */ - - /* restart the PHY clock */ - USB_PWRCLKCTL = 0U; - - /* initialize host configuration register */ - if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ); - } else { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - - /* configure data FIFO sizes */ - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set Rx FIFO size */ - USB_GRFLEN = USBFS_RX_FIFO_SIZE; - - /* set non-periodic Tx FIFO size and address */ - nptxfifolen &= ~HNPTFLEN_HNPTXRSAR; - nptxfifolen |= USBFS_RX_FIFO_SIZE; - nptxfifolen &= ~HNPTFLEN_HNPTXFD; - nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = nptxfifolen; - - /* set periodic Tx FIFO size and address */ - ptxfifolen &= ~HPTFLEN_HPTXFSAR; - ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; - ptxfifolen &= ~HPTFLEN_HPTXFD; - ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = ptxfifolen; - } - -#ifdef USE_OTG_MODE - - /* clear Host Set HNP Enable bit in the USB OTG Control Register */ - otgctl |= GOTGCS_HHNPEN; - USB_GOTGCS &= ~otgctl; - USB_GOTGCS |= 0; - -#endif /* USE_OTG_MODE */ - - /* make sure the FIFOs are flushed */ - - /* flush all Tx FIFOs in device or host mode */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush the entire Rx FIFO */ - usb_rxfifo_flush(pudev); - - /* clear all pending host channel interrupts */ - USB_HACHINTEN &= ~HACHINTEN_CINTEN; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxINTEN(i) = 0U; - USB_HCHxINTF(i) = 0xFFFFFFFFU; - } - -#ifndef USE_OTG_MODE - usb_vbus_drive(pudev, 1U); -#endif /* USE_OTG_MODE */ - - usb_hostint_enable(pudev); - - return USB_OK; -} - -/*! - \brief control the VBUS to power - \param[in] pudev: pointer to selected usb host - \param[in] state: VBUS state - \param[out] none - \retval none -*/ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) -{ - __IO uint32_t host_port = 0U; - - /* enable or disable the external charge pump */ - if ((void *)0 != pudev->host.vbus_drive) { - pudev->host.vbus_drive(pudev, state); - } - - /* turn on the host port power. */ - host_port = USB_PORT_READ(); - - if ((0U == (host_port & HPCS_PP)) && (1U == state)) { - host_port |= HPCS_PP; - } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) { - host_port &= ~HPCS_PP; - } else { - /* no operation */ - } - - USB_HPCS = host_port; - - if (NULL != pudev->mdelay) { - pudev->mdelay(200U); - } -} - -/*! - \brief enables the host mode interrupts - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) -{ - uint32_t gintf = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xFFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - gintf |= GINTF_RXFNEIF; - - /* enable host_mode-related interrupts */ - gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF; - - USB_GINTEN &= ~gintf; - USB_GINTEN |= gintf; - - return USB_OK; -} - -/*! - \brief reset host port - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint32_t usb_port_reset (usb_core_handle_struct *pudev) -{ - USB_HPCS = USB_PORT_READ() | HPCS_PRST; - - if (NULL != pudev->mdelay) { - pudev->mdelay(100U); - } - - USB_HPCS &= ~HPCS_PRST; - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - return USB_OK; -} - -/*! - \brief initialize host channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t is_low_speed = 0U; - __IO uint32_t chinten = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* clear old interrupt conditions for this host channel */ - USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; - - /* enable channel interrupts required for this transfer */ - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ - | HCHINTEN_DTERIE | HCHINTEN_NAKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } else { - chinten |= HCHINTEN_NYETIE; - } - break; - - case USB_EPTYPE_INTR: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ - | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } - break; - - case USB_EPTYPE_ISOC: - chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; - } - break; - - default: - break; - } - - USB_HCHxINTEN((uint16_t)hc_num) = chinten; - - /* enable the top level host channel interrupt */ - USB_HACHINTEN |= 1U << hc_num; - - /* make sure host channel interrupts are enabled */ - USB_GINTEN |= GINTEN_HCIE; - - /* program the hcctlr register */ - chctl = 0U; - - if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { - is_low_speed = 1U; - } - - chctl |= (uint32_t)puhc->dev_addr << 22U; - chctl |= (uint32_t)puhc->endp_type << 18U; - chctl |= (uint32_t)puhc->endp_id << 11U; - chctl |= (uint32_t)puhc->endp_in << 15U; - chctl |= (uint32_t)is_low_speed << 17U; - chctl |= puhc->endp_mps; - - if (HCCHAR_INTR == puhc->endp_type) { - chctl |= HCHCTL_ODDFRM; - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief prepare host channel for transferring packets - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint16_t dword_len = 0U; - uint16_t packet_num = 0U; - - __IO uint32_t chxlen = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* compute the expected number of packets associated to the transfer */ - if (puhc->xfer_len > 0U) { - packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps; - - if (packet_num > HC_MAX_PACKET_COUNT) { - packet_num = HC_MAX_PACKET_COUNT; - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - } else { - packet_num = 1U; - } - - if (puhc->endp_in) { - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - - /* initialize the host channel length register */ - chxlen &= ~HCHLEN_TLEN; - chxlen |= puhc->xfer_len; - chxlen &= ~HCHLEN_PCNT; - chxlen |= (uint32_t)packet_num << 19; - chxlen &= ~HCHLEN_DPID; - chxlen |= (uint32_t)(puhc->DPID) << 29; - USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen; - - /* set host channel enable */ - chctl = USB_HCHxCTL((uint16_t)hc_num); - - if (1 == USB_EVEN_FRAME()) { - chctl |= HCHCTL_ODDFRM; - } else { - chctl &= ~HCHCTL_ODDFRM; - } - - chctl |= HCHCTL_CEN; - chctl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { - dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; - - switch (puhc->endp_type) { - /* non-periodic transfer */ - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - /* check if there is enough space in fifo space */ - if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - /* need to process data in non-periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_NPTXFEIE; - } - break; - - /* periodic transfer */ - case USB_EPTYPE_INTR: - case USB_EPTYPE_ISOC: - /* check if there is enough space in FIFO space */ - if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - /* need to process data in periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_PTXFEIE; - } - break; - - default: - break; - } - - /* write packet into the Tx FIFO. */ - usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); - } - - return USB_OK; -} - -/*! - \brief halt channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t endp_type = 0U; - __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num); - - chctl |= HCHCTL_CEN | HCHCTL_CDIS; - - endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U); - - /* check for space in the request queue to issue the halt. */ - if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { - if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } else { - if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief stop the USB host and clean up fifos - \param[in] none - \param[out] none - \retval none -*/ -void usb_host_stop(usb_core_handle_struct *pudev) -{ - uint32_t i; - - /* disable all host channel interrupt */ - USB_HACHINTEN = 0U; - USB_HACHINT = 0xFFFFFFFFU; - - /* flush out any leftover queued requests */ - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR; - } - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} - -#endif /* USE_HOST_MODE */ - - -#ifdef USE_DEVICE_MODE - -/* USB endpoint Tx FIFO size */ -static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = -{ - (uint16_t)TX0_FIFO_FS_SIZE, - (uint16_t)TX1_FIFO_FS_SIZE, - (uint16_t)TX2_FIFO_FS_SIZE, - (uint16_t)TX3_FIFO_FS_SIZE -}; - -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); - -/*! - \brief initialize USB core registers for device mode - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i, ram_address = 0U; - __IO uint32_t devinep0intf = USB_DIEP0TFLEN; - __IO uint32_t devinepintf = 0U; - - /* restart the Phy Clock (Maybe don't need to...) */ - USB_PWRCLKCTL = 0U; - - /* config periodic frmae interval to default */ - USB_DCFG &= ~DCFG_EOPFT; - USB_DCFG |= FRAME_INTERVAL_80; - - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set full speed PHY */ - USB_DCFG &= ~DCFG_DS; - USB_DCFG |= USB_SPEED_INP_FULL; - - /* set Rx FIFO size */ - USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 0 Tx FIFO length and RAM address */ - devinep0intf &= ~DIEP0TFLEN_IEP0TXFD; - devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16; - devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR; - devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE; - - USB_DIEP0TFLEN = devinep0intf; - - ram_address = (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 1 to 3's Tx FIFO length and RAM address */ - for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { - ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; - - devinepintf &= ~DIEPTFLEN_IEPTXFD; - devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; - devinepintf &= ~DIEPTFLEN_IEPTXRSAR; - devinepintf |= ram_address; - - USB_DIEPxTFLEN(i) = devinepintf; - } - } - - /* make sure all FIFOs are flushed */ - - /* flush all Tx FIFOs */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush entire Rx FIFO */ - usb_rxfifo_flush(pudev); - - /* clear all pending device interrupts */ - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - USB_DAEPINTEN = 0U; - - /* configure all IN/OUT endpoints */ - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - if (USB_DIEPxCTL(i) & DEPCTL_EPEN) { - USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DIEPxCTL(i) = 0U; - } - - if (USB_DOEPxCTL(i) & DEPCTL_EPEN) { - USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DOEPxCTL(i) = 0U; - } - - /* set IN/OUT endpoint transfer length to 0 */ - USB_DIEPxLEN(i) = 0U; - USB_DOEPxLEN(i) = 0U; - - /* clear all pending IN/OUT endpoints interrupts */ - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - usb_devint_enable(pudev); - - return USB_OK; -} - -/*! - \brief enable the device mode interrupts - \param[in] pudev: pointer to usb device - \param[out] none - \retval status -*/ -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) -{ - uint32_t int_mask = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xBFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - int_mask = GINTEN_RXFNEIE; - - /* enable device_mode-related interrupts */ - int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ - | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \ - | GINTEN_ISOINCIE; - -#ifdef VBUS_SENSING_ENABLED - int_mask |= GINTEN_SESIE | GINTEN_OTGIE; -#endif /* VBUS_SENSING_ENABLED */ - - USB_GINTEN &= ~int_mask; - USB_GINTEN |= int_mask; - - return USB_OK; -} - -/*! - \brief configures endpoint 0 to receive SETUP packets - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_ep0_startout(usb_core_handle_struct *pudev) -{ - __IO uint32_t ep0len = 0U; - - /* set OUT endpoint 0 receive length to 24 bytes */ - ep0len &= ~DOEP0LEN_TLEN; - ep0len |= 8U * 3U; - - /* set OUT endpoint 0 receive length to 1 packet */ - ep0len &= ~DOEP0LEN_PCNT; - ep0len |= 1U << 19; - - /* set SETUP packet count to 3 */ - ep0len &= ~DOEP0LEN_STPCNT; - ep0len |= 3U << 29; - - USB_DOEPxLEN(0U) = ep0len; -} - -/*! - \brief active remote wakeup signalling - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_remotewakeup_active(usb_core_handle_struct *pudev) -{ - __IO uint32_t power_clock; - - if (pudev->dev.remote_wakeup) { - if (1U == (USB_DSTAT & DSTAT_SPST)) { - if (pudev->cfg.low_power) { - /* ungate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - - /* active remote wakeup signaling */ - USB_DCTL |= DCTL_RWKUP; - - if (pudev->mdelay != (void *)0) { - pudev->mdelay(5U); - } - - USB_DCTL &= ~DCTL_RWKUP; - } - } -} - -/*! - \brief active USB core clock - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_clock_ungate(usb_core_handle_struct *pudev) -{ - if (pudev->cfg.low_power) { - __IO uint32_t power_clock; - - if (1U == (USB_DSTAT & DSTAT_SPST)) { - /* un-gate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - } -} - -/*! - \brief stop the device and clean up fifos - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_device_stop (usb_core_handle_struct *pudev) -{ - uint32_t i; - - pudev->dev.status = 1U; - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} -#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_core.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_core.c deleted file mode 100644 index 410c7051c0..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_core.c +++ /dev/null @@ -1,476 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device mode core driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -/*! - \brief initailizes the USB device-mode handler stack - \param[in] pudev: pointer to usb device instance - \param[in] core_id: USB core ID - \param[out] none - \retval none -*/ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* select USB core */ - usb_core_select (pudev, core_id); - - pudev->dev.status = USB_STATUS_DEFAULT; - - /* disable USB global interrupt */ - USB_GLOBAL_INT_DISABLE(); - - /* init the core (common init.) */ - usb_core_init(pudev); - - /* force device mode*/ - usb_mode_set(pudev, DEVICE_MODE); - - /* set device disconnect */ - USB_SOFT_DISCONNECT_ENABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* init device */ - usb_devcore_init(pudev); - - /* set device Connect */ - USB_SOFT_DISCONNECT_DISABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* enable USB global interrupt */ - USB_GLOBAL_INT_ENABLE(); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to usb device instance - \param[in] ep_desc: pointer to usb endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc) -{ - usb_ep_struct *ep; - usb_dir_enum ep_dir; - - uint32_t devepinten = 0U; - uint32_t devepctl = 0U; - - uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU; - uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK; - uint16_t ep_mps = ep_desc->wMaxPacketSize; - - if (ep_desc->bEndpointAddress >> 7) { - ep = &pudev->dev.in_ep[ep_num]; - - devepinten |= 1U << ep_num; - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - ep_dir = USB_TX; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepinten |= (1U << ep_num) << 16; - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - ep_dir = USB_RX; - } - - /* if the endpoint is not active, need change the endpoint control register */ - if (!(devepctl & DEPCTL_EPACT)) { - devepctl &= ~DEPCTL_MPL; - devepctl |= ep_mps; - - devepctl &= ~DEPCTL_EPTYPE; - devepctl |= (uint32_t)ep_type << 18; - - if (USB_TX == ep_dir) { - devepctl &= ~DIEPCTL_TXFNUM; - devepctl |= (uint32_t)ep_num << 22; - } - - devepctl |= DEPCTL_SD0PID; - devepctl |= DEPCTL_EPACT; - } - - if (USB_TX == ep_dir) { - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else if (USB_RX == ep_dir) { - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* no operation */ - } - - ep->endp_mps = ep_mps; - ep->endp_type = ep_type; - - /* enable the interrupts for this endpoint */ - USB_DAEPINTEN |= devepinten; -} - -/*! - \brief endpoint deinitialize - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint32_t devepinten = 0U; - uint8_t ep_num = ep_addr & 0x7FU; - - if (ep_addr >> 7) { - devepinten |= 1U << ep_num; - - USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } else { - devepinten |= (1U << ep_num) << 16U; - - USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } - - /* disable the interrupts for this endpoint */ - USB_DAEPINTEN &= ~devepinten; -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - uint32_t devepctl = 0U, devepxlen = 0U; - - ep = &pudev->dev.out_ep[ep_num]; - - /* setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - devepxlen = USB_DOEPxLEN((uint16_t)ep_num); - - devepxlen &= ~DEPLEN_TLEN; - devepxlen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - - if (0U == ep_num) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - /* configure the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; - devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps; - } - } - - USB_DOEPxLEN((uint16_t)ep_num) = devepxlen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (ep->endp_frame) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - __IO uint32_t deveplen = 0U; - - ep = &pudev->dev.in_ep[ep_num]; - - /* setup and start the transfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - deveplen = USB_DIEPxLEN((uint16_t)ep_num); - - /* clear transfer length to 0 */ - deveplen &= ~DEPLEN_TLEN; - - /* clear transfer packet to 0 */ - deveplen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set transfer packet count to 1 */ - deveplen |= 1U << 19U; - } else { - if (0U == ep_num) { - if (ep->xfer_len > ep->endp_mps) { - ep->xfer_len = ep->endp_mps; - } - - deveplen |= 1U << 19U; - } else { - deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; - } - - /* configure the transfer size and packet count as follows: - * xfersize = N * maxpacket + short_packet - * pktcnt = N + (short_packet exist ? 1 : 0) - */ - deveplen |= ep->xfer_len; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - deveplen |= DIEPLEN_MCNT & (1U << 29U); - } - } - - USB_DIEPxLEN((uint16_t)ep_num) = deveplen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - - if (USB_EPTYPE_ISOC != ep->endp_type) { - /* enable the Tx FIFO empty interrupt for this endpoint */ - if (ep->xfer_len > 0U) { - USB_DIEPFEINTEN |= 1U << ep_num; - } - } else { - usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len); - } -} - -/*! - \brief transmit data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - usbd_status_enum ret = USBD_OK; - - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_IN; - - usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len); - - return ret; -} - -/*! - \brief receive data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_OUT; - - usbd_ep_rx (pudev, 0U, pbuf, len); - - return USBD_OK; -} - -/*! - \brief transmit status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_IN; - - usbd_ep_tx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief receive status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_OUT; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief set an endpoint to STALL status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if (ep_addr >> 7U) { - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* set the endpoint disable bit */ - if (devepctl & DEPCTL_EPEN) { - devepctl |= DEPCTL_EPD; - } - - /* set the endpoint stall bit */ - devepctl |= DEPCTL_STALL; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* set the endpoint stall bit */ - USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL; - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if(ep_addr >> 7){ - ep = &pudev->dev.in_ep[ep_num]; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* clear the IN endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - /* clear the OUT endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } -} - -/*! - \brief flushes the FIFOs - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7) { - usb_txfifo_flush(pudev, ep_addr & 0x7FU); - } else { - usb_rxfifo_flush(pudev); - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to usb device instance - \param[in] ep_num: endpoint identifier which is in (0..3) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num) -{ - return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_int.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_int.c deleted file mode 100644 index fadd75159d..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_int.c +++ /dev/null @@ -1,648 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device mode interrupt routines -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbd_int.h" -#include "usbd_std.h" - -/* interrupt handlers */ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev); - -static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num); - -#ifdef VBUS_SENSING_ENABLED - - static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); - static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); - -#endif /* VBUS_SENSING_ENABLED */ - -static usb_speed_enum USB_SPEED[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW -}; - -static const uint8_t EP0_MAXLEN[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 -}; - -/*! - \brief USB device-mode interrupts global service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbd_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN; - - /* ensure the core is in device mode */ - if (DEVICE_MODE == USB_CURRENT_MODE_GET()) { - int_status = gintf & ginten; - - /* there are no interrupts, avoid spurious interrupt */ - if (!int_status) { - return 0U; - } - - /* OUT endpoints interrupts */ - if (int_status & GINTF_OEPIF) { - retval |= usbd_intf_outep(pudev); - } - - /* IN endpoints interrupts */ - if (int_status & GINTF_IEPIF) { - retval |= usbd_intf_inep(pudev); - } - - /* mode mismatch interrupt */ - if (int_status & GINTF_MFIF) { - /* clear interrupt */ - USB_GINTF = GINTF_MFIF; - } - - /* early suspend interrupt */ - if (int_status & GINTF_ESP) { - retval |= usbd_intf_earlysuspend(pudev); - } - - /* suspend interrupt */ - if (int_status & GINTF_SP) { - retval |= usbd_intf_suspend(pudev); - } - - /* wakeup interrupt */ - if (int_status & GINTF_WKUPIF) { - retval |= usbd_intf_resume(pudev); - } - - /* start of frame interrupt */ - if (int_status & GINTF_SOF) { - retval |= usbd_intf_sof(pudev); - } - - /* reveive fifo not empty interrupt */ - if (int_status & GINTF_RXFNEIF) { - retval |= usbd_intf_rxfifo(pudev); - } - - /* USB reset interrupt */ - if (int_status & GINTF_RST) { - retval |= usbd_intf_reset(pudev); - } - - /* enumeration has been finished interrupt */ - if (int_status & GINTF_ENUMFIF) { - retval |= usbd_intf_enumfinish(pudev); - } - - /* incomplete synchronization in transfer interrupt*/ - if (int_status & GINTF_ISOINCIF) { - retval |= usbd_intf_isoinincomplete(pudev); - } - - /* incomplete synchronization out transfer interrupt*/ - if (int_status & GINTF_ISOONCIF) { - retval |= usbd_intf_isooutincomplete(pudev); - } - -#ifdef VBUS_SENSING_ENABLED - - /* session request interrupt */ - if (int_status & GINTF_SESIF) { - retval |= usbd_intf_sessionrequest(pudev); - } - - /* OTG mode interrupt */ - if (int_status & GINTF_OTGIF) { - retval |= usbd_intf_otg(pudev); - } -#endif /* VBUS_SENSING_ENABLED */ - } - - return retval; -} - -/*! - \brief indicates that an OUT endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t out_endp_intr = 0U; - - /* read in the device interrupt bits */ - USB_DAOEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num); - - /* transfer complete interrupt */ - if (out_endp_intr & DOEPINTF_TF) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; - - /* data receive is completed */ - usbd_out_transaction(pudev, endp_num); - } - - /* endpoint disable interrupt */ - if (out_endp_intr & DOEPINTF_EPDIS) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS; - } - - /* setup phase finished interrupt (just for control endpoints) */ - if (out_endp_intr & DOEPINTF_STPF) { - /* setup phase is completed */ - usbd_setup_transaction(pudev); - - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF; - } - - /* back to back setup packets received */ - if (out_endp_intr & DOEPINTF_BTBSTP) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that an IN endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t in_endp_intr = 0U; - - /* get all in endpoints which have interrupts */ - USB_DAIEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num); - - if (in_endp_intr & DIEPINTF_TF) { - /* disable the fifo empty interrupt for the endpoint */ - USB_DIEPFEINTEN &= ~(0x1U << endp_num); - - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF; - - /* data transmittion is completed */ - usbd_in_transaction(pudev, endp_num); - } - - if (in_endp_intr & DIEPINTF_CITO) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO; - } - - if (in_endp_intr & DIEPINTF_IEPNE) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE; - } - - if (in_endp_intr & DIEPINTF_EPDIS) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS; - } - - if (in_endp_intr & DIEPINTF_TXFE) { - usbd_emptytxfifo_write(pudev, endp_num); - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that early SUSPEND state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev) -{ - USB_GINTEN &= ~GINTEN_ESPIE; - USB_GINTF = GINTF_ESP; - - return 1U; -} - -/*! - \brief indicates that SUSPEND state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev) -{ - __IO uint8_t low_power = pudev->cfg.low_power; - __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST); - __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U; - - pudev->dev.prev_status = pudev->dev.status; - pudev->dev.status = USB_STATUS_SUSPENDED; - - if (low_power && suspend && is_configured) { - /* switch-off the otg clocks */ - USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; - - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } - - /* clear interrupt */ - USB_GINTF = GINTF_SP; - - return 1U; -} - -/*! - \brief indicates that the USB controller has detected a resume or remote Wake-up sequence - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) -{ - pudev->dev.status = pudev->dev.prev_status; - pudev->dev.status = USB_STATUS_CONFIGURED; - - /* clear interrupt */ - USB_GINTF = GINTF_WKUPIF; - - return 1U; -} - -/*! - \brief handle the SOF interrupts - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) -{ - if (NULL != usbd_int_fops) { - usbd_int_fops->SOF(pudev); - } - - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle the Rx status queue level interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) -{ - usb_ep_struct *ep; - uint8_t data_pid = 0U, endp_num = 0U; - uint32_t bcount = 0U, packet_num = 0U; - - /* get the status from the top of the fifo (must be read to a variable) */ - __IO uint32_t rx_status = USB_GRSTATP; - - /* disable the rx fifo non-empty interrupt */ - USB_GINTEN &= ~GINTEN_RXFNEIE; - - endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM); - bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U; - data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U); - - /* ensure no-DMA mode can work */ - packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT; - if ((1U == endp_num) && (0U == packet_num)) { - uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num); - - devepctl |= DEPCTL_SNAK; - devepctl &= ~DEPCTL_EPEN; - devepctl &= ~DEPCTL_EPD; - - USB_DOEPxCTL((uint16_t)endp_num) = devepctl; - } - - ep = &pudev->dev.out_ep[endp_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17U) { - case RXSTAT_GOUT_NAK: - if(0U != bcount) { - return 0U; - } - break; - case RXSTAT_DATA_UPDT: - if (bcount > 0U) { - usb_fifo_read(ep->xfer_buff, (uint16_t)bcount); - ep->xfer_buff += bcount; - ep->xfer_count += bcount; - } - break; - case RXSTAT_XFER_COMP: - if (0U != bcount) { - return 0U; - } - break; - case RXSTAT_SETUP_COMP: - if(0U != bcount) { - return 0U; - } - break; - case RXSTAT_SETUP_UPDT: - *(uint32_t *)0x5000081CU |= 0x00020000U; - if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { - /* copy the setup packet received in fifo into the setup buffer in ram */ - usb_fifo_read(pudev->dev.setup_packet, 8U); - - ep->xfer_count += bcount; - } - break; - default: - break; - } - - /* enable the Rx fifo non-empty interrupt */ - USB_GINTEN |= GINTEN_RXFNEIE; - - return 1U; -} - -/*! - \brief handle USB reset interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - usb_ep_struct *ep; - - /* clear the remote wakeup signaling */ - USB_DCTL &= ~DCTL_RWKUP; - - /* flush the tx fifo */ - usb_txfifo_flush(pudev, 0U); - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF((uint16_t)i) = 0xFFU; - USB_DOEPxINTF((uint16_t)i) = 0xFFU; - } - - /* clear all pending device endpoint interrupts */ - USB_DAEPINT = 0xFFFFFFFFU; - - /* enable endpoint 0 interrupts */ - USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; - USB_DAEPINTEN &= ~DAEPINTEN_IEPIE; - USB_DAEPINTEN = (1U << 16) | 1U; - - /* enable out endpoint interrupts */ - USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; - - /* enable in endpoint interrupts */ - USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; - - /* reset device address */ - USB_DCFG &= ~DCFG_DAR; - USB_DCFG |= 0U << 4U; - - /* configure endpoint 0 to receive setup packets */ - usb_ep0_startout(pudev); - - /* clear usb reset interrupt */ - USB_GINTF = GINTF_RST; - - /* open EP0 IN */ - ep = &pudev->dev.in_ep[0]; - - USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE; - USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; - - if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DIEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - /* open EP0 OUT */ - ep = &pudev->dev.out_ep[0]; - - USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE; - - if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DOEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - pudev->dev.status = USB_STATUS_DEFAULT; - - return 1U; -} - -/*! - \brief handle enumeration finish interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) -{ - uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U); - - /* set the max packet size of devie in endpoint based on the enumeration speed */ - USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed]; - - /* clear global IN NAK */ - USB_DCTL &= ~DCTL_CGINAK; - USB_DCTL |= DCTL_CGINAK; - - /* set USB turn-around time based on device speed and PHY interface */ - if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) { - pudev->cfg.core_speed = USB_CORE_SPEED_HIGH; - pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x09U << 10; - } else { - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x05U << 10; - } - - /* clear interrupt */ - USB_GINTF = GINTF_ENUMFIF; - - return 1U; -} - -/*! - \brief handle the ISO IN incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev) -{ -// USBD_DCD_INT_fops->IsoINIncomplete (pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_ISOINCIF; - - return 1U; -} - -/*! - \brief handle the ISO OUT incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) -{ -// USBD_DCD_INT_fops->IsoOUTIncomplete (pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_ISOONCIF; - - return 1U; -} - -/*! - \brief check FIFO for the next packet to be loaded - \param[in] pudev: pointer to usb device instance - \param[in] ep_id: endpoint identifier which is in (0..3) - \param[out] none - \retval status -*/ -static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) -{ - uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U; - usb_ep_struct *ep; - - ep = &pudev->dev.in_ep[ep_num]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) && - (ep->xfer_count < ep->xfer_len)) { - /* write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - if(ep->xfer_len == ep->xfer_count) { - fifo_empty_mask = 0x1U << ep_num; - USB_DIEPFEINTEN &= ~fifo_empty_mask; - } - } - - return 1U; -} - -#ifdef VBUS_SENSING_ENABLED - -/*! - \brief indicates that the USB_OTG controller has detected a connection - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev) -{ - pudev->dev.connection_status = 1U; - - /* clear the interrupt bit */ - USB_GINTF = GINTF_SESIF; - - return 1; -} - -/*! - \brief indicates that the USB_OTG controller has detected an OTG event - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev) -{ - if (USB_GOTGINTF & GOTGINTF_SESEND) { - pudev->dev.class_deinit(pudev, 0); - pudev->dev.connection_status = 0; - } - - /* clear OTG interrupt */ - USB_GOTGINTF |= GOTGINTF_SESEND; - - return 1; -} - -#endif /* VBUS_SENSING_ENABLED */ diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_std.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_std.c deleted file mode 100644 index 24382028f5..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbd_std.c +++ /dev/null @@ -1,693 +0,0 @@ -/*! - \file usbd_std.c - \brief USB 2.0 standard handler driver -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbd_std.h" -#include "usb_core.h" - -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); - -static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clrfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfig, - usbd_setconfig, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse(pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, req.bmRequestType & 0x80U); - break; - } - - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.out_ep[0]; - - if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_rx (pudev, - 0U, - ep->xfer_buff, - (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, 0U); - } - - usbd_ctlstatus_tx(pudev); - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.in_ep[0]; - - if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - /* last packet is MPS multiple, so send ZLP packet */ - if ((pudev->dev.sum_len % ep->endp_mps == 0U) && - (pudev->dev.sum_len >= ep->endp_mps) && - (pudev->dev.sum_len < pudev->dev.ctl_len)) { - usbd_ep_tx (pudev, 0U, NULL, 0U); - pudev->dev.ctl_len = 0U; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, 0U); - } - - usbd_ctlstatus_rx(pudev); - } - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*StandardDeviceRequest[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret = USBD_OK; - - switch (pudev->dev.status) { - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - usbd_ctlstatus_tx(pudev); - } - } else { - usbd_enum_error(pudev, req); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - - return ret; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user... */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation... */ -} - -/*! - \brief get the device descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.dev_desc[0]; - - return pudev->dev.dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.config_desc[2]; - - return pudev->dev.config_desc; -} - -/*! - \brief get string descriptor - \param[in] index: string descriptor index - \param[in] pLen: pointer to string length - \param[out] none - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->dev.strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQTYPE_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 0U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - - pudev->dev.class_req_handler(pudev, req); - } - } - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - __IO uint32_t DctlrStatus; - - switch (req->bmRequestType & USB_REQ_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 1U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } else if ((req->wValue == USB_FEATURE_TEST_MODE) && - (0U == (req->wIndex & 0xFFU))) { - DctlrStatus = USB_DCTL; - - usbd_ctlstatus_tx(pudev); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t DevAddr; - - if ((0U == req->wIndex) && (0U == req->wLength)) { - DevAddr = (uint8_t)(req->wValue) & 0x7FU; - - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - usbd_enum_error(pudev, req); - } else { - USB_SET_DEVADDR((uint32_t)DevAddr); - - usbd_ctlstatus_tx(pudev); - - if (0U != DevAddr) { - pudev->dev.status = USB_STATUS_ADDRESSED; - } else { - pudev->dev.status = USB_STATUS_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { - uint8_t desc_index = (uint8_t)(req->wValue >> 8U); - - if (desc_index <= 0x03U) { - uint16_t len; - uint8_t *pbuf; - - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_index - 1U](pudev, (uint8_t)(req->wValue) & 0xFFU, &len); - - if ((0U != len) && (0U != req->wLength)) { - len = USB_MIN(len, req->wLength); - - if ((1U == desc_index) && (64U == req->wLength)) { - len = 8U; - } - - usbd_ctltx(pudev, pbuf, len); - } - } else { - usbd_enum_error(pudev, req); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) { - pudev->dev.class_req_handler(pudev, req); - } else { - /* no operation */ - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t USBD_default_config = 0U; - - if (1U != req->wLength) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U); - break; - case USB_STATUS_CONFIGURED: - usbd_ctltx(pudev, &pudev->dev.config_num, 1U); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (cfgidx) { - pudev->dev.config_num = cfgidx; - pudev->dev.status = USB_STATUS_CONFIGURED; - pudev->dev.class_init(pudev, cfgidx); - } - - usbd_ctlstatus_tx(pudev); - break; - case USB_STATUS_CONFIGURED: - if (0U == cfgidx) { - pudev->dev.status = USB_STATUS_ADDRESSED; - pudev->dev.config_num = cfgidx; - pudev->dev.class_deinit(pudev, cfgidx); - } else if (cfgidx != pudev->dev.config_num) { - /* clear old configuration */ - pudev->dev.class_deinit(pudev, pudev->dev.config_num); - - /* set new configuration */ - pudev->dev.config_num = cfgidx; - pudev->dev.class_init(pudev, cfgidx); - } else { - /* no operation */ - } - - usbd_ctlstatus_tx(pudev); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *psetup = pudev->dev.setup_packet; - - req->bmRequestType = *psetup; - req->bRequest = *(uint8_t *)(psetup + 1U); - req->wValue = SWAPBYTE (psetup + 2U); - req->wIndex = SWAPBYTE (psetup + 4U); - req->wLength = SWAPBYTE (psetup + 6U); - - pudev->dev.ctl_len = req->wLength; -} - -/*! - \brief handle USB low level error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, 0x80U); - usbd_ep_stall(pudev, 0x00U); - usb_ep0_startout(pudev); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_core.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_core.c deleted file mode 100644 index 4aea302f03..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_core.c +++ /dev/null @@ -1,710 +0,0 @@ -/*! - \file usbh_core.c - \brief this file implements the functions for the core state machine process -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbh_hcs.h" -#include "usbh_core.h" -#include "usbh_int.h" -#include "stdio.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" -#include "usb_core.h" - -extern class_polling_fun_cb_struct class_polling_cb; - -uint8_t usbh_sof (usb_core_handle_struct *pudev); -uint8_t usbh_connected (usb_core_handle_struct *pudev); -uint8_t usbh_disconnected (usb_core_handle_struct *pudev); - -usbh_hcd_int_cb_struct usbh_hcd_int_cb = -{ - usbh_sof, - usbh_connected, - usbh_disconnected, -}; - -usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb; -extern usbh_state_handle_struct usbh_state_core; - -static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -/* the host state handle function array */ -void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - host_idle_handle, - host_dev_attached_handle, - host_dev_detached_handle, - host_detect_dev_speed_handle, - host_enum_handle, - host_class_request_handle, - host_class_handle, - host_user_input_handle, - host_suspended_handle, - host_error_handle, -}; - -/* the host state handle table */ -state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move }, - {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move }, - {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move }, - {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move }, - {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, - {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, -}; - -/*! - \brief the polling function of HOST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate; - - scd_begin(p_state, HOST_FSM_ID); - - if (-1 == p_state->usbh_current_state_stack_top) { - uint8_t cur_state = p_state->usbh_current_state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) { - if (HOST_DEV_DETACHED != cur_state) { - p_state->usbh_current_state = HOST_DEV_DETACHED; - cur_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[cur_state](pudev, puhost, p_state); - } else { - uint8_t stack0_state = p_state->stack[0].state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) { - if (HOST_DEV_DETACHED != stack0_state) { - p_state->stack[0].state = HOST_DEV_DETACHED; - stack0_state = HOST_DEV_DETACHED; - p_state->usbh_current_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[stack0_state](pudev, puhost, p_state); - } - - return USBH_OK; -} - -/*! - \brief the handle function of HOST_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (hcd_is_device_connected(pudev)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } -} - -/*! - \brief the handle function of HOST_DEV_ATTACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_attached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usr_cb->device_connected(); - puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U); - puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U); - - /* reset usb device */ - if (0U == usb_port_reset(pudev)) { - puhost->usr_cb->device_reset(); - - /* wait for USB USBH_ISR_PrtEnDisableChange() - * host is now ready to start the enumeration - */ - puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET(); - puhost->usr_cb->device_speed_detected(puhost->device.speed); - - /* open IN control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_in_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - /* open OUT control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_out_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_ENUMERATION state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_enum_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) { - puhost->usr_cb->enumeration_finish(); - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_USER_INPUT, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_USER_INPUT state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_user_input_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) { - if (USBH_OK == (puhost->class_init(pudev, puhost))) { - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_CLASS_REQ, - pustate->usbh_current_state); - } - } -} - -/*! - \brief the handle function of HOST_CLASS_REQUEST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_request_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_CLASS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - class_state_polling_fun(pudev, puhost, pustate); -} - -/*! - \brief the handle function of HOST_SUSPENDED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_suspended_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief the handle function of HOST_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* re-initilaize host for new enumeration */ - usbh_deinit (pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DEV_DETACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_detached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* manage user disconnect operations*/ - puhost->usr_cb->device_disconnected(); - - /* re-initilaize host for new enumeration */ - usbh_deinit(pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - usbh_allchannel_dealloc(pudev); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DETECT_DEV_SPEED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief usb connect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_connected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 1U; - - return 0U; -} - -/*! - \brief usb disconnect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_disconnected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 0U; - - return 0U; -} - -/*! - \brief usb sof callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_sof (usb_core_handle_struct *pudev) -{ - /* this callback could be used to implement a scheduler process */ - return 0U; -} - -/*! - \brief initialize the host portion of the driver. - \param[in] pudev: pointer to usb device - \param[in] core_id: usb otg core identifier(high-speed or full-speed) - \param[out] none - \retval operation status -*/ -uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - pudev->host.connect_status = 0U; - - pudev->host.host_channel[0].endp_mps = 8U; - - usb_core_select(pudev, core_id); - -#ifndef DUAL_ROLE_MODE_ENABLED - - USB_GLOBAL_INT_DISABLE(); - - usb_core_init(pudev); - - /* force host mode*/ - usb_mode_set(pudev, HOST_MODE); - - usb_hostcore_init(pudev); - - USB_GLOBAL_INT_ENABLE(); - -#endif - - return 0U; -} - -/*! - \brief check if the device is connected. - \param[in] pudev: pointer to usb device - \param[out] none - \retval device connection status. 1 -> connected and 0 -> disconnected -*/ -uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev) -{ - return (uint32_t)(pudev->host.connect_status); -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval urb_state_enum -*/ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].urb_state; -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval No. of data bytes transferred -*/ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].xfer_count; -} - -/*! - \brief de-initialize host - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[out] none - \retval host status -*/ -usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate) -{ - /* software init */ - - puhost->control.ep0_size = USB_MAX_EP0_SIZE; - - puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT; - puhost->device.speed = HPRT_PRTSPD_FULL_SPEED; - - usbh_channel_free(pudev, puhost->control.hc_in_num); - usbh_channel_free(pudev, puhost->control.hc_out_num); - - scd_init(pustate); - scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE); - - scd_begin(pustate,HOST_FSM_ID); - scd_state_move(pustate, HOST_IDLE); - - return USBH_OK; -} - -/*! - \brief state core driver init - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_init(usbh_state_handle_struct* pustate) -{ - /* init the state core */ - pustate->usbh_current_state = 0U; - pustate->usbh_current_state_table = NULL; - pustate->usbh_current_state_table_size = 0U; - - pustate->usbh_current_state_stack_top = -1; - pustate->stack->state = 0U; - pustate->stack->table_size = 0U; - pustate->stack->table = NULL; - - pustate->usbh_regist_state_table_num = 0U; - pustate->usbh_regist_state_table->table = NULL; - pustate->usbh_regist_state_table->table_size = 0U; - pustate->usbh_regist_state_table->id = 0U; - - /* init the control and the enumeration polling handle flag */ - ctrl_polling_handle_flag = 0U; - enum_polling_handle_flag = 0U; -} - -/*! - \brief state core driver table regist - \param[in] pustate: pointer to usb state driver - \param[in] pstate_table: pointer to the table to regist - \param[in] table_id: the id of the table to regist - \param[in] current_table_size: the size of the current table to regist - \param[out] none - \retval none -*/ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size) -{ - usbh_state_regist_table_struct *cur_state_reg_table; - - cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num]; - - cur_state_reg_table->id = table_id; - cur_state_reg_table->table = pstate_table; - cur_state_reg_table->table_size = current_table_size; - - pustate->usbh_regist_state_table_num++; -} - -/*! - \brief state core driver begin - \param[in] pustate: pointer to usb state driver - \param[in] table_id: the id of the table to begin - \param[out] none - \retval none -*/ -void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) -{ - uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num; - usbh_state_regist_table_struct *cur_state_reg_table; - - for (i = 0U; i < table_num; i++) { - cur_state_reg_table = &pustate->usbh_regist_state_table[i]; - - if (table_id == cur_state_reg_table->id) { - pustate->usbh_current_state_table = cur_state_reg_table->table; - pustate->usbh_current_state_table_size = cur_state_reg_table->table_size; - break; - } - } -} - -/*! - \brief state core driver move state - \param[in] pustate: pointer to usb state driver - \param[in] state: the state to move - \param[out] none - \retval none -*/ -void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state) -{ - pustate->usbh_current_state = state; -} - -/*! - \brief state core driver event handle - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[in] event: the current event - \param[in] state: the current state - \param[out] none - \retval host status -*/ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state) -{ - uint8_t i = 0U; - ACT_FUN event_act_fun = NULL; - state_table_struct *backup_state_t = pustate->usbh_current_state_table; - state_table_struct *executive_state_table = pustate->usbh_current_state_table; - - /* look up the table to find the action function */ - for (i = 0U; i < pustate->usbh_current_state_table_size; i++) { - if (state == executive_state_table->cur_state) { - if (event == executive_state_table->cur_event) { - state = executive_state_table->next_state; - event_act_fun = executive_state_table->event_action_fun; - break; - } else { - executive_state_table++; - } - } else { - executive_state_table++; - } - } - - pustate->usbh_current_state_table = backup_state_t; - - /* if the action function is not NULL, execute the action function */ - if (event_act_fun) { - if (event_act_fun == &only_state_move) { - pustate->usbh_current_state = state; - } else { - return event_act_fun(pudev, puhost, pustate); - } - } - - return USBH_BUSY; -} - -/*! - \brief state core driver table push - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_push(usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) { - pustate->usbh_current_state_stack_top++; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - /* put the current state table into the state stack */ - top_state_element->state = pustate->usbh_current_state; - top_state_element->table = pustate->usbh_current_state_table; - top_state_element->table_size = pustate->usbh_current_state_table_size; - } -} - -/*! - \brief state core driver table pop - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_pop (usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - if (pustate->usbh_current_state_stack_top > -1) { - /* get the current state table from the state stack */ - pustate->usbh_current_state = top_state_element->state; - pustate->usbh_current_state_table = top_state_element->table; - pustate->usbh_current_state_table_size = top_state_element->table_size; - pustate->usbh_current_state_stack_top--; - } -} -/*! - \brief the polling function of class req state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_req_polling(pudev, puhost, pustate); -} - -/*! - \brief the polling function of class state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_polling(pudev, puhost, pustate); -} - -/*! - \brief the function is only used to state move - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return USBH_OK; -} - -/*! - \brief the function to the up state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - scd_table_pop((usbh_state_handle_struct *)pustate); - - return USBH_OK; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_ctrl.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_ctrl.c deleted file mode 100644 index 2c8495e37c..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_ctrl.c +++ /dev/null @@ -1,612 +0,0 @@ -/*! - \file usbh_ctrl.c - \brief this file implements the functions for the control transmit process -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbh_core.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t ctrl_polling_handle_flag = 0U; -uint8_t ctrl_setup_wait_flag = 0U; -uint8_t ctrl_data_wait_flag = 0U; -uint8_t ctrl_status_wait_flag = 0U; - -static uint16_t timeout = 0U; - -static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the ctrl state handle function array */ -void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) = -{ - ctrl_idle_handle, - ctrl_setup_handle, - ctrl_data_handle, - ctrl_status_handle, - ctrl_error_handle, - ctrl_stalled_handle, - ctrl_complete_handle, -}; - -/* the ctrl state handle table */ -state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of CTRL state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - - p_state = (usbh_state_handle_struct *)pustate; - - /* if first enter this function, begin the ctrl state */ - if (0U == ctrl_polling_handle_flag) { - ctrl_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, CTRL_IDLE); - } - - /* base on the current state to handle the ctrl state */ - scd_begin(p_state, CTRL_FSM_ID); - ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - - /* determine the control transfer whether to complete */ - switch (puhost->usbh_backup_state.ctrl_backup_state) { - case CTRL_COMPLETE: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_OK; - break; - case CTRL_STALLED: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_NOT_SUPPORTED; - break; - case CTRL_ERROR: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_FAIL; - break; - default: - exe_state = USBH_BUSY; - break; - } - - return exe_state; -} - -/*! - \brief the handle function of CTRL_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_SETUP state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_setup_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP; - - if (0U == ctrl_setup_wait_flag) { - ctrl_setup_wait_flag = 1U; - - /* send a setup packet */ - usbh_ctltx_setup (pudev, - puhost->control.setup.data, - puhost->control.hc_out_num); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - /* case setup packet sent successfully */ - if (URB_DONE == urb_status) { - /* check if there is a data stage */ - if (0U != puhost->control.setup.b.wLength) { - ctrl_setup_wait_flag = 0U; - timeout = DATA_STAGE_TIMEOUT; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state); - /* no data stage */ - } else { - timeout = NODATA_STAGE_TIMEOUT; - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - } - - /* set the delay timer to enable timeout for data stage completion */ - puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET(); - } else if (URB_ERROR == urb_status) { - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state); - } else { - /* no operation */ - } - } -} - -/*! - \brief the handle function of CTRL_DATA state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_data_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA; - - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_IN == direction) { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* issue an IN token */ - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_in_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - /* check is data packet transfered successfully */ - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_data_wait_flag = 0U; - - /* timeout for IN transfer */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* start DATA out transfer (only one DATA packet)*/ - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U; - - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_out_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - /* if the setup pkt is sent successful, then change the state */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* nack received from device */ - ctrl_data_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_STATUS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_status_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS; - - /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */ - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_OUT == direction) { - /* handle status in */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status*/ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_status_wait_flag = 0U; - - /* handle timeout */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - /* handle status out */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* handle URB_NOTREADY status */ - ctrl_status_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_ERROR status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR; - - if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { - /* do the transmission again, starting from SETUP Packet */ - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); - } else { - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of CTRL_STALLED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_COMPLETE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_complete_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief send datas from the host channel - \param[in] pudev: pointer to usb device - \param[in] buf: data buffer address to send datas - \param[in] hc_num: the number of the host channel - \param[in] len: length of the send data - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, - uint8_t *buf, - uint8_t hc_num, - uint16_t len) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->xfer_buff = buf; - puhc->xfer_len = len; - - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - if (0U == puhc->endp_in) { - if (0U == len) { - /* for status out stage, length = 0, status out pid = 1 */ - puhc->data_tg_out = 1U; - } - - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - puhc->DPID = HC_PID_DATA1; - } - break; - - case USB_EPTYPE_ISOC: - puhc->DPID = HC_PID_DATA0; - break; - - case USB_EPTYPE_BULK: - if (0U == puhc->endp_in) { - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - } - break; - - case USB_EPTYPE_INTR: - if (0U == puhc->endp_in) { - if (0U == puhc->data_tg_out) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_out ^= 1U; - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_in ^= 1U; - } - break; - - default: - break; - } - - hcd_submit_request (pudev, hc_num); - - return USBH_OK; -} - -/*! - \brief send the setup packet to the device - \param[in] pudev: pointer to usb device - \param[in] buf: buffer pointer from which the data will be send to device - \param[in] hc_num: host channel number - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->DPID = HC_PID_SETUP; - puhc->xfer_buff = buf; - puhc->xfer_len = USBH_SETUP_PACKET_SIZE; - - return (usbh_status_enum)hcd_submit_request (pudev, hc_num); -} - -/*! - \brief this function prepare a hc and start a transfer - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - puhc->urb_state = URB_IDLE; - puhc->xfer_count = 0U; - - return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num); -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_hcs.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_hcs.c deleted file mode 100644 index 8679a8bfd7..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_hcs.c +++ /dev/null @@ -1,158 +0,0 @@ -/*! - \file usbh_hcs.c - \brief this file implements functions for opening and closing host channels -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbh_hcs.h" - -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev); - -/*! - \brief open a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - uint16_t channel_info = puhc->info; - - puhc->endp_id = (uint8_t)channel_info & 0x7FU; - puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7; - puhc->endp_type = ep_type; - puhc->endp_mps = ep_mps; - puhc->dev_addr = dev_addr; - puhc->dev_speed = dev_speed; - - puhc->data_tg_in = 0U; - puhc->data_tg_out = 0U; - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief modify a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB Device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - if (0U != dev_addr) { - puhc->dev_addr = dev_addr; - } - - if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) { - puhc->endp_mps = ep_mps; - } - - if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) { - puhc->dev_speed = dev_speed; - } - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief allocate a new channel for the pipe - \param[in] pudev: pointer to usb device - \param[in] ep_addr: endpoint for which the channel to be allocated - \param[out] none - \retval host channel number -*/ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint16_t hc_num = usbh_freechannel_get(pudev); - - if ((uint16_t)HC_ERROR != hc_num) { - pudev->host.host_channel[hc_num].info = HC_USED | ep_addr; - } - - return (uint8_t)hc_num; -} - -/*! - \brief free the usb host channel - \param[in] pudev: pointer to usb device - \param[in] index: channel number to be freed which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index) -{ - if (index < HC_MAX) { - pudev->host.host_channel[index].info &= HC_USED_MASK; - } - - return USBH_OK; -} - -/*! - \brief free all usb host channel - \param[in] pudev: pointer to usb device - \param[out] none - \retval host operation status -*/ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev) -{ - uint8_t index; - - for (index = 2U; index < HC_MAX; index ++) { - pudev->host.host_channel[index].info = 0U; - } - - return USBH_OK; -} - -/*! - \brief get a free channel number for allocation to a device endpoint - \param[in] pudev: pointer to usb device - \param[out] none - \retval free channel number -*/ -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev) -{ - uint8_t index = 0U; - - for (index = 0U; index < HC_MAX; index++) { - if (0U == (pudev->host.host_channel[index].info & HC_USED)) { - return (uint16_t)index; - } - } - - return HC_ERROR; -} - diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_int.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_int.c deleted file mode 100644 index f440fa61b7..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_int.c +++ /dev/null @@ -1,576 +0,0 @@ -/*! - \file usbh_int.c - \brief USB host mode interrupt handler file -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usb_core.h" -#include "usb_defines.h" -#include "usbh_int.h" - -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev); - -/*! - \brief handle global host interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbh_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_flag = 0U; - - /* check if host mode */ - if (USB_CURRENT_MODE_GET() == HOST_MODE) { - USB_CORE_INTR_READ(int_flag); - - if (!int_flag) { - return 0U; - } - - /* start of frame interrupt handle */ - if (int_flag & GINTF_SOF) { - retval |= usbh_intf_sof (pudev); - } - - /* Rx FIFO non-empty interrupt handle */ - if (int_flag & GINTF_RXFNEIF) { - retval |= usbh_intf_rxfifo_noempty (pudev); - } - - /* Non-Periodic Tx FIFO empty interrupt hanlde */ - if (int_flag & GINTF_NPTXFEIF) { - retval |= usbh_intf_nptxfifo_empty (pudev); - } - - /* periodic Tx FIFO empty interrupt handle */ - if (int_flag & GINTF_PTXFEIF) { - retval |= usbh_intf_ptxfifo_empty (pudev); - } - - /* host channels interrupt handle */ - if (int_flag & GINTF_HCIF) { - retval |= usbh_intf_hc (pudev); - } - - /* host port interrupt handle */ - if (int_flag & GINTF_HPIF) { - retval |= usbh_intf_port (pudev); - } - - /* disconnect interrupt handle */ - if (int_flag & GINTF_DISCIF) { - retval |= usbh_intf_disconnect (pudev); - } - - /* isochronous IN transfer not complete interrupt handle */ - if (int_flag & GINTF_ISOONCIF) { - retval |= usbh_intf_iso_incomplete_xfer (pudev); - } - } - - return retval; -} - -/*! - \brief handle the start-of-frame interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->sof(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle all host channels interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - uint32_t retval = 0U; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) { - if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) { - retval |= usbh_intf_hc_in (pudev, i); - } else { - retval |= usbh_intf_hc_out (pudev, i); - } - } - } - - return retval; -} - -/*! - \brief handle the disconnect interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->device_disconnected(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_DISCIF; - - return 1U; -} - -/*! - \brief handle the non-periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U; - - if (len > puhc->xfer_len) { - /* last packet */ - len = (uint16_t)puhc->xfer_len; - - USB_GINTEN &= ~GINTF_NPTXFEIF; - - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U; - - if (len > puhc->xfer_len) { - len = puhc->xfer_len; - - /* last packet */ - USB_GINTEN &= ~GINTF_PTXFEIF; - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the host port interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) -{ - uint8_t port_speed = 0U; - uint8_t port_reset = 0U; - uint32_t retval = 0U; - __IO uint32_t hostportdup = USB_HPCS; - - /* clear the interrupt bits in gintsts */ - hostportdup &= ~HPCS_PE; - hostportdup &= ~HPCS_PCD; - hostportdup &= ~HPCS_PEDC; - - /* port connect detected */ - if (USB_HPCS & HPCS_PCD) { - hostportdup |= HPCS_PCD; - usbh_hcd_int_fops->device_connected(pudev); - retval |= 1U; - } - - /* port enable changed */ - if (USB_HPCS & HPCS_PEDC) { - hostportdup |= HPCS_PEDC; - - if (USB_HPCS & HPCS_PE) { - port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U); - - if (HPRT_PRTSPD_LOW_SPEED == port_speed) { - USB_HFT = 6000U; - - if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_6_MHZ); - } - port_reset = 1U; - } - } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) { - USB_HFT = 48000U; - - if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - port_reset = 1U; - } - } else { - /* for high speed device and others */ - port_reset = 1U; - } - } - } - - if (port_reset) { - usb_port_reset(pudev); - } - - /* clear port interrupts */ - USB_HPCS = hostportdup; - - return retval; -} - -/*! - \brief handle the OUT channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num); - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - channel_intr &= USB_HCHxINTEN((uint16_t)channel_num); - - if (channel_intr & HCHINTF_ACK) { - if (URB_PING == puhc->urb_state) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channel_intr & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channel_intr & HCHINTF_TF) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } else if (channel_intr & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_STALL; - } else if (channel_intr & HCHINTF_NAK) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_NAK; - } else if (channel_intr & HCHINTF_USBER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->err_count ++; - puhc->status = HC_TRACERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channel_intr & HCHINTF_NYET) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_NYET; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET; - } else if (channel_intr & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->status= HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else if (channel_intr & HCHINTF_CH) { - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - - if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18)) { - puhc->data_tg_out ^= 1U; - } - break; - case HC_NAK: - puhc->urb_state = URB_NOTREADY; - break; - case HC_NYET: - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - case HC_TRACERR: - if (3U == puhc->err_count) { - puhc->urb_state = URB_ERROR; - puhc->err_count = 0U; - } - break; - default: - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the IN channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint8_t endp_type = 0U; - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num); - __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num); - - channle_intf &= USB_HCHxINTEN((uint16_t)channel_num); - - endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U); - - if (channle_intf & HCHINTF_ACK) { - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channle_intf & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_STALL; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - - /* NOTE: When there is a 'stall', reset also nak, - else, the pudev->host.status = HC_STALL - will be overwritten by 'nak' in code below */ - channle_intf &= ~HCHINTF_NAK; - - usb_hostchannel_halt(pudev, channel_num); - } else if (channle_intf & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else { - /* no operation */ - } - - if (channle_intf & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channle_intf & HCHINTF_TF) { - puhc->status = HC_XF; - puhc->err_count = 0U; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - - if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->data_tg_in ^= 1U; - } else if (USB_EPTYPE_INTR == endp_type) { - channel_ctrl |= HCHCTL_ODDFRM; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - puhc->urb_state = URB_DONE; - } else { - /* no operation */ - } - } else if (channle_intf & HCHINTF_CH) { - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - break; - case HC_TRACERR: - case HC_DTGERR: - puhc->err_count = 0U; - puhc->urb_state = URB_ERROR; - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - default: - if (USB_EPTYPE_INTR == endp_type) { - puhc->data_tg_in ^= 1U; - } - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else if (channle_intf & HCHINTF_USBER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - (puhc->err_count)++; - puhc->status = HC_TRACERR; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channle_intf & HCHINTF_NAK) { - if (USB_EPTYPE_INTR == endp_type) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - } else if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - /* re-activate the channel */ - channel_ctrl |= HCHCTL_CEN; - channel_ctrl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - } else { - /* no operation */ - } - - puhc->status = HC_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the rx fifo non-empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - __IO uint8_t channel_num = 0U; - __IO uint32_t rx_status = 0U; - uint32_t usbh_ch_ctl_reg = 0U; - usb_hostchannel_struct *puhc; - - /* disable the Rx status queue level interrupt */ - USB_GINTEN &= ~GINTF_RXFNEIF; - - rx_status = USB_GRSTATP; - channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM); - puhc = &pudev->host.host_channel[channel_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17) { - case GRSTATR_RPCKST_IN: - count = (rx_status & GRSTATRP_BCOUNT) >> 4; - - /* read the data into the host buffer. */ - if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { - usb_fifo_read(puhc->xfer_buff, (uint16_t)count); - - /* manage multiple Xfer */ - puhc->xfer_buff += count; - puhc->xfer_count += count; - - if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) { - /* re-activate the channel when more packets are expected */ - usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num); - usbh_ch_ctl_reg |= HCHCTL_CEN; - usbh_ch_ctl_reg &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg; - } - } - break; - case GRSTATR_RPCKST_IN_XFER_COMP: - case GRSTATR_RPCKST_DATA_TOGGLE_ERR: - case GRSTATR_RPCKST_CH_HALTED: - default: - break; - } - - /* enable the Rx status queue level interrupt */ - USB_GINTEN |= GINTF_RXFNEIF; - - return 1U; -} - -/*! - \brief handle the incomplete periodic transfer interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev) -{ - __IO uint32_t gint_flag = 0U; - - gint_flag = USB_HCHxCTL(0U); - USB_HCHxCTL(0U) = 0U; - - gint_flag = 0U; - - /* clear interrupt */ - gint_flag |= GINTF_ISOONCIF; - USB_GINTF = gint_flag; - - return 1U; -} diff --git a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_std.c b/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_std.c deleted file mode 100644 index 09fe5f498f..0000000000 --- a/bsp/gd32303e-eval/Libraries/GD32F30x_usbfs_driver/Source/usbh_std.c +++ /dev/null @@ -1,807 +0,0 @@ -/*! - \file usbh_std.c - \brief USB 2.0 standard function definition -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-02-10, V1.0.0, firmware for GD32F30x -*/ - -#include "usbh_core.h" -#include "usbh_usr.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t local_buffer[64]; -uint8_t usbh_cfg_desc[512]; -uint8_t enum_polling_handle_flag = 0U; - -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the enumeration state handle function array */ -void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - enum_idle_handle, - enum_set_addr_handle, - enum_get_full_dev_desc_handle, - enum_get_cfg_desc_handle, - enum_get_full_cfg_desc_handle, - enum_get_mfc_string_desc_handle, - enum_get_product_string_desc_handle, - enum_get_serialnum_string_desc_handle, - enum_set_configuration_handle, - enum_dev_configured_handle, -}; - -/* the enumeration state handle table */ -state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move }, - {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move }, - {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move }, - {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move }, - {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move }, - {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move }, - {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move }, - {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move }, - {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move }, - {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of enumeration state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval usb host status -*/ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - p_state = (usbh_state_handle_struct *)pustate; - - if (0U == enum_polling_handle_flag) { - enum_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, ENUM_IDLE); - } - - /* start the enumeration state handle */ - scd_begin(p_state,ENUM_FSM_ID); - - if (0 == p_state->usbh_current_state_stack_top) { - enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - } else { - enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); - } - - /* determine the enumeration whether to complete */ - if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) { - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - enum_polling_handle_flag = 0U; - exe_state = USBH_OK; - } - - return exe_state; -} - -/*! - \brief the handle function of ENUM_IDLE state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - 8U); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U); - puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0; - - /* issue reset */ - usb_port_reset(pudev); - - /* modify control channels configuration for maxpacket size */ - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, - puhost, - pustate, - ENUM_EVENT_SET_ADDR, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_DEV_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - USB_DEVDESC_SIZE); - } - - if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE); - puhost->usr_cb->device_desc_available(&puhost->device.dev_desc); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_ADDR state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_addr_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(2U); - } - puhost->device.address = USBH_DEVICE_ADDRESS; - - /* user callback for device address assigned */ - puhost->usr_cb->device_address_set(); - - /* modify control channels to update device address */ - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - puhost->device.address, - 0U, - 0U, - 0U); - - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - puhost->device.address, - 0U, - 0U, - 0U); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_DEV_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, - USB_CFGDESC_SIZE); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < USB_CFGDESC_SIZE; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - USB_CFGDESC_SIZE); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, puhost->device.cfg_desc.wTotalLength); - } - - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < puhost->device.cfg_desc.wTotalLength; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - puhost->device.cfg_desc.wTotalLength); - - /* User callback for configuration descriptors available */ - puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc[0]); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_MFC_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_MFC_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC; - - if (0U != puhost->device.dev_desc.iManufacturer) { - if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iManufacturer, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - puhost->usr_cb->manufacturer_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_PRODUCT_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->manufacturer_string("N/A"); - scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC); - } -} - -/*! - \brief the handle function of ENUM_GET_PRODUCT_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC; - - if (0U != puhost->device.dev_desc.iProduct) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iProduct, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->product_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->product_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_SERIALNUM_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC; - - if (0U != puhost->device.dev_desc.iSerialNumber) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iSerialNumber, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->serial_num_string(local_buffer); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->serial_num_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_CONFIGURATION state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) { - usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_DEV_CONFIGURED, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_DEV_CONFIGURED state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief get descriptor in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] buf: buffer to store the descriptor - \param[in] ReqType: descriptor type - \param[in] ValueIdx: wValue for the GetDescriptr request - \param[in] Len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_enum_desc_get(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len) -{ - usb_setup_union *pSetup = &(puhost->control.setup); - - pSetup->b.bmRequestType = USB_DIR_IN | req_type; - pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR; - pSetup->b.wValue = value_idx; - - if (USB_STRDESC == (value_idx & 0xff00U)){ - pSetup->b.wIndex = 0x0409U; - } else { - pSetup->b.wIndex = 0U; - } - - pSetup->b.wLength = len; - - puhost->control.buff = buf; - puhost->control.length = len; - -} - -/*! - \brief set address in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] device_address: the device address - \param[out] none - \retval none -*/ -void usbh_enum_addr_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t device_address) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_ADDRESS; - p_setup->b.wValue = (uint16_t)device_address; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0U; - puhost->control.length = 0U; -} - -/*! - \brief set configuration in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] cfg_idx: the index of the configuration - \param[out] none - \retval none -*/ -void usbh_enum_cfg_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint16_t cfg_idx) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_CONFIGURATION; - p_setup->b.wValue = cfg_idx; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0; - puhost->control.length = 0U; -} - -/*! - \brief parse the device descriptor - \param[in] dev_desc: device_descriptor destinaton address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len) -{ - dev_desc->Header.bLength = *(uint8_t *)(buf + 0); - dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - dev_desc->bcdUSB = SWAPBYTE(buf + 2); - dev_desc->bDeviceClass = *(uint8_t *)(buf + 4); - dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5); - dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6); - dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7); - - if (len > 8U){ - /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ - dev_desc->idVendor = SWAPBYTE(buf + 8); - dev_desc->idProduct = SWAPBYTE(buf + 10); - dev_desc->bcdDevice = SWAPBYTE(buf + 12); - dev_desc->iManufacturer = *(uint8_t *)(buf + 14); - dev_desc->iProduct = *(uint8_t *)(buf + 15); - dev_desc->iSerialNumber = *(uint8_t *)(buf + 16); - dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17); - } -} - -/*! - \brief parse the configuration descriptor - \param[in] cfg_desc: configuration descriptor address - \param[in] itf_desc: interface descriptor address - \param[in] ep_desc: endpoint descriptor address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len) -{ - usb_descriptor_interface_struct *pitf = NULL; - usb_descriptor_interface_struct temp_pitf; - usb_descriptor_endpoint_struct *pep = NULL; - usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf; - - uint8_t itf_ix = 0U; - uint8_t ep_ix = 0U; - uint16_t ptr = 0U; - static uint8_t prev_itf = 0U; - static uint16_t prev_ep_size = 0U; - - /* parse configuration descriptor */ - cfg_desc->Header.bLength = *(uint8_t *)(buf + 0); - cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - cfg_desc->wTotalLength = SWAPBYTE(buf + 2); - cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4); - cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5); - cfg_desc->iConfiguration = *(uint8_t *)(buf + 6); - cfg_desc->bmAttributes = *(uint8_t *)(buf + 7); - cfg_desc->bMaxPower = *(uint8_t *)(buf + 8); - - if (len > USB_CFGDESC_SIZE) { - ptr = USB_CFG_DESC_LEN; - - if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) { - pitf = (usb_descriptor_interface_struct *)0; - - for (; ptr < cfg_desc->wTotalLength; ) { - pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr); - - if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) { - itf_ix = *((uint8_t *)pdesc + 2U); - pitf = &itf_desc[itf_ix]; - - if (*((uint8_t *)pdesc + 3U) < 3U) { - usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc); - - /* parse endpoint descriptors relative to the current interface */ - if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) { - for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) { - pdesc = usbh_next_desc_get((void* )pdesc, &ptr); - - if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) { - pep = &ep_desc[itf_ix][ep_ix]; - - if (prev_itf != itf_ix) { - prev_itf = itf_ix; - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } else { - if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) { - break; - } else { - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } - } - - usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc); - prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4); - ep_ix++; - } - } - } - } - } - } - } - - prev_ep_size = 0U; - prev_itf = 0U; - } -} - -/*! - \brief parse the interface descriptor - \param[in] itf_desc: interface descriptor destination - \param[in] buf: buffer where the descriptor data is available - \param[out] none - \retval none -*/ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf) -{ - itf_desc->Header.bLength = *(uint8_t *)(buf + 0); - itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2); - itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3); - itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4); - itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5); - itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6); - itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7); - itf_desc->iInterface = *(uint8_t *)(buf + 8); -} - -/*! - \brief parse the endpoint descriptor - \param[in] ep_desc: endpoint descriptor destination address - \param[in] buf: buffer where the parsed descriptor stored - \param[out] none - \retval none -*/ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf) -{ - ep_desc->Header.bLength = *(uint8_t *)(buf + 0); - ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2); - ep_desc->bmAttributes = *(uint8_t *)(buf + 3); - ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4); - ep_desc->bInterval = *(uint8_t *)(buf + 6); -} - -/*! - \brief parse the string descriptor - \param[in] psrc: source pointer containing the descriptor data - \param[in] pdest: destination address pointer - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len) -{ - uint16_t strlength; - uint16_t idx; - - /* the unicode string descriptor is not null-terminated. the string length is - computed by substracting two from the value of the first byte of the descriptor. - */ - - /* check which is lower size, the size of string or the length of bytes read from the device */ - - if (USB_DESCTYPE_STRING == psrc[1]){ - /* make sure the descriptor is string type */ - - /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ - strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len); - psrc += 2; /* adjust the offset ignoring the string len and descriptor type */ - - for (idx = 0U; idx < strlength; idx += 2U) { - /* copy only the string and ignore the unicode id, hence add the src */ - *pdest = psrc[idx]; - pdest++; - } - - *pdest = 0U; /* mark end of string */ - } -} - -/*! - \brief get the next descriptor header - \param[in] pbuf: pointer to buffer where the cfg descriptor is available - \param[in] ptr: data popinter inside the configuration descriptor - \param[out] none - \retval next descriptor header -*/ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr) -{ - uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength; - - usb_descriptor_header_struct *pnext; - - *ptr += len; - - pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len); - - return(pnext); -} - diff --git a/bsp/gd32303e-eval/Libraries/SConscript b/bsp/gd32303e-eval/Libraries/SConscript deleted file mode 100644 index 244fe1ff5e..0000000000 --- a/bsp/gd32303e-eval/Libraries/SConscript +++ /dev/null @@ -1,33 +0,0 @@ -import rtconfig -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. - -src = Glob('GD32F30x_standard_peripheral/Source/*.c') -src += [cwd + '/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c'] - -#add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += [cwd + '/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [cwd + '/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += [cwd + '/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s'] - -path = [ - cwd + '/CMSIS/GD/GD32F30x/Include', - cwd + '/CMSIS', - cwd + '/GD32F30x_standard_peripheral/Include',] - -if GetDepend(['RT_USING_BSP_USB']): - path += [cwd + '/GD32F30x_usb_driver/Include'] - src += [cwd + '/GD32F30x_usb_driver/Source'] - -CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F30X_HD'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/gd32303e-eval/README.md b/bsp/gd32303e-eval/README.md deleted file mode 100644 index 64ef6e9ce8..0000000000 --- a/bsp/gd32303e-eval/README.md +++ /dev/null @@ -1,93 +0,0 @@ -# GD32303E-EVAL # - -## 1. 简介 - -[GD32303E-EVAL](http://gd32mcu.21ic.com/site)是兆易科技æ供的开å‘æ¿ï¼Œä½¿ç”¨ GD32F303ZET6 作为主控制器。æä¾›åŒ…æ‹¬æ‰©å±•å¼•è„šåœ¨å†…çš„åŠ SWD, Reset, Boot, User button key, LED, CAN, I2C, I2S, USART, RTC, LCD, SPI, ADC, DAC, EXMC, CTC, SDIO,USBD, GD-Link 等外设资æºã€‚ - -æ¿è½½ä¸»è¦èµ„æºå¦‚下： - -| 硬件 | æè¿° | -| -- | -- | -|CPU| Cortex-M4| -|主频| 120MHz | -|SRAM| 64KB | -|Flash| 512KB | - -## 2. 编译说明 - -GD32303E-EVALæ¿çº§åŒ…支æŒMDK5ã€IARå¼€å‘环境和GCC编译器，以下是具体版本信æ¯ï¼š - -| IDE/编译器 | 已测试版本 | -| -- | -- | -| MDK5 | MDK5.25 | -| IAR | IAR8.20 | -| GCC | GCC 5.4.1 20160919 (release) | - -## 3. 烧写åŠæ‰§è¡Œ - -供电方å¼ï¼šå¼€å‘æ¿ä½¿ç”¨ Mini USB 接å£æˆ–者 DC-005 连接器æä¾› 5V 电æºã€‚ - -下载程åºï¼šä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿éœ€è¦ä¸€å¥— JLink 或者使用 GD-Link 工具。 - -解决IDE "Missing Device(s)"问题" -* MDK5: 安装GigaDevice.GD32F30x_AddOn.1.0.1.exe，在 Folder Selection 中的 Destination Folder 那一æ é€‰æ‹© Keil uVision5 软件的安装目录，如 C:\Keil_v5，然åŽåœ¨ Option for Target çš„ Device 选择对应的器件，åŒæ—¶åœ¨ Option forTarget çš„ C/C++中添加路径 C:\Keil_v5\ARM\Pack\ARM\CMSIS\4.2.0\CMSIS\Include。 - -* IAR：安装 IAR_GD32F30x_ADDON.1.0.0.exe - -### 3.1 é…置和仿真 - -工程已ç»é»˜è®¤ä½¿èƒ½äº†RT-Thread UART驱动ã€GPIO驱动ã€SPI驱动ã€I2C驱动。若想进一步é…置工程请 -使用ENV工具。 - -### 3.2 è¿è¡Œç»“æžœ - -打开MDK或者IAR工程，进入仿真åŽå…¨é€Ÿè¿è¡Œï¼Œå°†ä¼šåœ¨ä¸²å£0上看到RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š - -``` - \ | / -- RT - Thread Operating System - / | \ 3.0.3 build Apr 26 2018 - 2006 - 2018 Copyright by rt-thread team -msh /> - -``` - -## 4. 驱动支æŒæƒ…况åŠè®¡åˆ’ - -| 驱动 | 支æŒæƒ…况 | 备注 | -| ------ | ---- | :------: | -| UART | æ”¯æŒ | UART0/1/2/3/4 | -| GPIO | æ”¯æŒ | | -| SPI | æ”¯æŒ | SPI0/1/2 | -| I2C | æ”¯æŒ | I2C0/1| - -### 4.1 IO在æ¿çº§æ”¯æŒåŒ…中的映射情况 - -| IOå· | æ¿çº§åŒ…中的定义 | -| -- | -- | -| PA9 | USART0 TX | -| PA10 | USART0 RX | -| PA2 | USART1 TX | -| PA3 | USART1 RX | -| PA5| SPI0 SCK | -| PA6 | SPI0 MISO | -| PA6 | SPI0 MOSI | -| PB13| SPI1 SCK | -| PB14 | SPI1 MISO | -| PB15 | SPI1 MOSI | -| PB6| I2C0 SCL | -| PB7 | I2C0 SDA | -| PB10| I2C1 SCL | -| PB11 | I2C1 SDA | - -## 5. è”ç³»äººä¿¡æ¯ - -维护人： - -- [misonyo](https://github.com/misonyo) - -## 6. å‚考 - -* [GD32303E-EVAL](http://gd32mcu.21ic.com/site) - - diff --git a/bsp/gd32303e-eval/RTE/_rt-thread_gd32f30x/RTE_Components.h b/bsp/gd32303e-eval/RTE/_rt-thread_gd32f30x/RTE_Components.h deleted file mode 100644 index 3b7880428d..0000000000 --- a/bsp/gd32303e-eval/RTE/_rt-thread_gd32f30x/RTE_Components.h +++ /dev/null @@ -1,20 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'project' - * Target: 'rt-thread_gd32f30x' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "gd32f30x.h" - - -#endif /* RTE_COMPONENTS_H */ diff --git a/bsp/gd32303e-eval/SConscript b/bsp/gd32303e-eval/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/gd32303e-eval/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32303e-eval/SConstruct b/bsp/gd32303e-eval/SConstruct deleted file mode 100644 index 6712d0169f..0000000000 --- a/bsp/gd32303e-eval/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread-gd32f30x.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32303e-eval/applications/SConscript b/bsp/gd32303e-eval/applications/SConscript deleted file mode 100644 index 9bb9abae89..0000000000 --- a/bsp/gd32303e-eval/applications/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -from building import * -import os - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -list = os.listdir(cwd) -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - group = group + SConscript(os.path.join(item, 'SConscript')) - -Return('group') diff --git a/bsp/gd32303e-eval/applications/main.c b/bsp/gd32303e-eval/applications/main.c deleted file mode 100644 index e9947e89d3..0000000000 --- a/bsp/gd32303e-eval/applications/main.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2015-07-29 Arda.Fu first implementation - */ -#include -#include - -int main(void) -{ - /* user app entry */ - - return 0; -} - - - - - diff --git a/bsp/gd32303e-eval/drivers/SConscript b/bsp/gd32303e-eval/drivers/SConscript deleted file mode 100644 index 306cd7e720..0000000000 --- a/bsp/gd32303e-eval/drivers/SConscript +++ /dev/null @@ -1,37 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drivers. -src = Split(""" -board.c -drv_usart.c -""") - -CPPPATH = [cwd] - -# add spi drivers. -if GetDepend('RT_USING_SPI'): - src += ['drv_spi.c'] - -# add softspi drivers. -if GetDepend('RT_USING_SPI_BITOPS'): - src += ['drv_soft_spi.c'] - -# add i2c drivers. -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -# add pin drivers. -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -# add spi flash drivers. -if GetDepend('RT_USING_SFUD'): - src += ['drv_spi_flash.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32303e-eval/drivers/board.c b/bsp/gd32303e-eval/drivers/board.c deleted file mode 100644 index 239d842054..0000000000 --- a/bsp/gd32303e-eval/drivers/board.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - */ -#include -#include -#include -#include - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while (1) - { - } - /* USER CODE END Error_Handler */ -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This function will initial GD32 board. - */ -void rt_hw_board_init() -{ - /* NVIC Configuration */ -#define NVIC_VTOR_MASK 0x3FFFFF80 -#ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); -#else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); -#endif - - SystemClock_Config(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/gd32303e-eval/drivers/board.h b/bsp/gd32303e-eval/drivers/board.h deleted file mode 100644 index 208f3f4c6a..0000000000 --- a/bsp/gd32303e-eval/drivers/board.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#ifdef __ICCARM__ -// Use *.icf ram symbal, to avoid hardcode. -extern char __ICFEDIT_region_RAM_end__; -#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ -#else -#define GD32_SRAM_SIZE 64 -#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) -#endif - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif - -#define HEAP_END GD32_SRAM_END - -#endif - -//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.c b/bsp/gd32303e-eval/drivers/drv_gpio.c deleted file mode 100644 index 4ac20e396f..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_gpio.c +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-10-20 ZYH the first version - * 2018-04-23 misonyo port to gd32f30x - */ - -#include "drv_gpio.h" -#include -#include -#include "gd32f30x.h" -#include "gd32f30x_exti.h" - -#ifdef RT_USING_PIN - -#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \ - GPIO_PIN_##pin, GPIO_PORT_SOURCE_GPIO##port, GPIO_PIN_SOURCE_##pin} -#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} - -/* GD32 GPIO driver */ -struct pin_index -{ - rt_int16_t index; - rcu_periph_enum clk; - rt_uint32_t gpio_periph; - rt_uint32_t pin; - rt_uint8_t port_src; - rt_uint8_t pin_src; -}; - -static const struct pin_index pins[] = -{ - __GD32_PIN_DEFAULT, - __GD32_PIN(1, E, 2), - __GD32_PIN(2, E, 3), - __GD32_PIN(3, E, 4), - __GD32_PIN(4, E, 5), - __GD32_PIN(5, E, 6), - __GD32_PIN_DEFAULT, - __GD32_PIN(7, C, 13), - __GD32_PIN(8, C, 14), - __GD32_PIN(9, C, 15), - __GD32_PIN(10, F, 0), - __GD32_PIN(11, F, 1), - __GD32_PIN(12, F, 2), - __GD32_PIN(13, F, 3), - __GD32_PIN(14, F, 4), - __GD32_PIN(15, F, 5), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(18, F, 6), - __GD32_PIN(19, F, 7), - __GD32_PIN(20, F, 8), - __GD32_PIN(21, F, 9), - __GD32_PIN(22, F, 10), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(26, C, 0), - __GD32_PIN(27, C, 1), - __GD32_PIN(28, C, 2), - __GD32_PIN(29, C, 3), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(34, A, 0), - __GD32_PIN(35, A, 1), - __GD32_PIN(36, A, 2), - __GD32_PIN(37, A, 3), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(40, A, 4), - __GD32_PIN(41, A, 5), - __GD32_PIN(42, A, 6), - __GD32_PIN(43, A, 7), - __GD32_PIN(44, C, 4), - __GD32_PIN(45, C, 5), - __GD32_PIN(46, B, 0), - __GD32_PIN(47, B, 1), - __GD32_PIN(48, B, 2), - __GD32_PIN(49, F, 11), - __GD32_PIN(50, F, 12), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(53, F, 13), - __GD32_PIN(54, F, 14), - __GD32_PIN(55, F, 15), - __GD32_PIN(56, G, 0), - __GD32_PIN(57, G, 1), - __GD32_PIN(58, E, 7), - __GD32_PIN(59, E, 8), - __GD32_PIN(60, E, 9), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(63, E, 10), - __GD32_PIN(64, E, 11), - __GD32_PIN(65, E, 12), - __GD32_PIN(66, E, 13), - __GD32_PIN(67, E, 14), - __GD32_PIN(68, E, 15), - __GD32_PIN(69, B, 10), - __GD32_PIN(70, B, 11), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(73, B, 12), - __GD32_PIN(74, B, 13), - __GD32_PIN(75, B, 14), - __GD32_PIN(76, B, 15), - __GD32_PIN(77, D, 8), - __GD32_PIN(78, D, 9), - __GD32_PIN(79, D, 10), - __GD32_PIN(80, D, 11), - __GD32_PIN(81, D, 12), - __GD32_PIN(82, D, 13), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(85, D, 14), - __GD32_PIN(86, D, 15), - __GD32_PIN(87, G, 2), - __GD32_PIN(88, G, 3), - __GD32_PIN(89, G, 4), - __GD32_PIN(90, G, 5), - __GD32_PIN(91, G, 6), - __GD32_PIN(92, G, 7), - __GD32_PIN(93, G, 8), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(96, C, 6), - __GD32_PIN(97, C, 7), - __GD32_PIN(98, C, 8), - __GD32_PIN(99, C, 9), - __GD32_PIN(100, A, 8), - __GD32_PIN(101, A, 9), - __GD32_PIN(102, A, 10), - __GD32_PIN(103, A, 11), - __GD32_PIN(104, A, 12), - __GD32_PIN(105, A, 13), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(109, A, 14), - __GD32_PIN(110, A, 15), - __GD32_PIN(111, C, 10), - __GD32_PIN(112, C, 11), - __GD32_PIN(113, C, 12), - __GD32_PIN(114, D, 0), - __GD32_PIN(115, D, 1), - __GD32_PIN(116, D, 2), - __GD32_PIN(117, D, 3), - __GD32_PIN(118, D, 4), - __GD32_PIN(119, D, 5), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(122, D, 6), - __GD32_PIN(123, D, 7), - __GD32_PIN(124, G, 9), - __GD32_PIN(125, G, 10), - __GD32_PIN(126, G, 11), - __GD32_PIN(127, G, 12), - __GD32_PIN(128, G, 13), - __GD32_PIN(129, G, 14), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(132, G, 15), - __GD32_PIN(133, B, 3), - __GD32_PIN(134, B, 4), - __GD32_PIN(135, B, 5), - __GD32_PIN(136, B, 6), - __GD32_PIN(137, B, 7), - __GD32_PIN_DEFAULT, - __GD32_PIN(139, B, 8), - __GD32_PIN(140, B, 9), - __GD32_PIN(141, E, 0), - __GD32_PIN(142, E, 1), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI5_9_IRQn}, - {GPIO_PIN_6, EXTI5_9_IRQn}, - {GPIO_PIN_7, EXTI5_9_IRQn}, - {GPIO_PIN_8, EXTI5_9_IRQn}, - {GPIO_PIN_9, EXTI5_9_IRQn}, - {GPIO_PIN_10, EXTI10_15_IRQn}, - {GPIO_PIN_11, EXTI10_15_IRQn}, - {GPIO_PIN_12, EXTI10_15_IRQn}, - {GPIO_PIN_13, EXTI10_15_IRQn}, - {GPIO_PIN_14, EXTI10_15_IRQn}, - {GPIO_PIN_15, EXTI10_15_IRQn}, -}; -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(rt_uint8_t pin) -{ - const struct pin_index *index; - - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - - return index; -}; - -void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) -{ - const struct pin_index *index; - rt_uint32_t pin_mode; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* GPIO Periph clock enable */ - rcu_periph_clock_enable(index->clk); - pin_mode = GPIO_MODE_OUT_PP; - - switch(mode) - { - case PIN_MODE_OUTPUT: - /* output setting */ - pin_mode = GPIO_MODE_OUT_PP; - break; - case PIN_MODE_OUTPUT_OD: - /* output setting: od. */ - pin_mode = GPIO_MODE_OUT_OD; - break; - case PIN_MODE_INPUT: - /* input setting: not pull. */ - pin_mode = GPIO_MODE_IN_FLOATING; - break; - case PIN_MODE_INPUT_PULLUP: - /* input setting: pull up. */ - pin_mode = GPIO_MODE_IPU; - break; - case PIN_MODE_INPUT_PULLDOWN: - /* input setting: pull down. */ - pin_mode = GPIO_MODE_IPD; - break; - default: - break; - } - - gpio_init(index->gpio_periph, pin_mode, GPIO_OSPEED_50MHZ, index->pin); -} - -void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) -{ - const struct pin_index *index; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); -} - -rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin) -{ - rt_int8_t value; - const struct pin_index *index; - - value = PIN_LOW; - - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - - value = gpio_input_bit_get(index->gpio_periph, index->pin); - - return value; -} - - -rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) -{ - rt_uint8_t i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { - return i; - } - } - return -1; -} -rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) -{ - rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; -rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == pin && - pin_irq_hdr_tab[hdr_index].hdr == hdr && - pin_irq_hdr_tab[hdr_index].mode == mode && - pin_irq_hdr_tab[hdr_index].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[hdr_index].pin != -1) - { - rt_hw_interrupt_enable(level); - return -RT_EFULL; - } - pin_irq_hdr_tab[hdr_index].pin = pin; - pin_irq_hdr_tab[hdr_index].hdr = hdr; - pin_irq_hdr_tab[hdr_index].mode = mode; - pin_irq_hdr_tab[hdr_index].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[hdr_index].pin = -1; - pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; - pin_irq_hdr_tab[hdr_index].mode = 0; - pin_irq_hdr_tab[hdr_index].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t hdr_index = -1; - exti_trig_type_enum trigger_mode; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - if (enabled == PIN_IRQ_ENABLE) - { - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - irqmap = &pin_irq_map[hdr_index]; - - switch (pin_irq_hdr_tab[hdr_index].mode) - { - case PIN_IRQ_MODE_RISING: - trigger_mode = EXTI_TRIG_RISING; - break; - case PIN_IRQ_MODE_FALLING: - trigger_mode = EXTI_TRIG_FALLING; - break; - case PIN_IRQ_MODE_RISING_FALLING: - trigger_mode = EXTI_TRIG_BOTH; - break; - default: - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - - rcu_periph_clock_enable(RCU_AF); - - /* enable and set interrupt priority */ - nvic_irq_enable(irqmap->irqno, 5U, 0U); - - /* connect EXTI line to GPIO pin */ - gpio_exti_source_select(index->port_src, index->pin_src); - - /* configure EXTI line */ - exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); - exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return -RT_EINVAL; - } - nvic_irq_disable(irqmap->irqno); - } - else - { - return -RT_EINVAL; - } - - return RT_EOK; -} -const static struct rt_pin_ops _gd32_pin_ops = -{ - gd32_pin_mode, - gd32_pin_write, - gd32_pin_read, - gd32_pin_attach_irq, - gd32_pin_detach_irq, - gd32_pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - - result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -rt_inline void pin_irq_hdr(int irqno) -{ - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) -{ - if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) - { - pin_irq_hdr(exti_line); - exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } -} -void EXTI0_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(0); - rt_interrupt_leave(); -} -void EXTI1_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(1); - rt_interrupt_leave(); -} -void EXTI2_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(2); - rt_interrupt_leave(); -} -void EXTI3_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(3); - rt_interrupt_leave(); -} -void EXTI4_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(4); - rt_interrupt_leave(); -} -void EXTI5_9_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(5); - GD32_GPIO_EXTI_IRQHandler(6); - GD32_GPIO_EXTI_IRQHandler(7); - GD32_GPIO_EXTI_IRQHandler(8); - GD32_GPIO_EXTI_IRQHandler(9); - rt_interrupt_leave(); -} -void EXTI10_15_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(10); - GD32_GPIO_EXTI_IRQHandler(11); - GD32_GPIO_EXTI_IRQHandler(12); - GD32_GPIO_EXTI_IRQHandler(13); - GD32_GPIO_EXTI_IRQHandler(14); - GD32_GPIO_EXTI_IRQHandler(15); - rt_interrupt_leave(); -} - -#endif diff --git a/bsp/gd32303e-eval/drivers/drv_gpio.h b/bsp/gd32303e-eval/drivers/drv_gpio.h deleted file mode 100644 index ae9bda7dce..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2015-01-05 Bernard the first version - */ -#ifndef GPIO_H__ -#define GPIO_H__ - - -#endif diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.c b/bsp/gd32303e-eval/drivers/drv_i2c.c deleted file mode 100644 index 29a1d84519..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_i2c.c +++ /dev/null @@ -1,374 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-05 tanek first implementation. - * 2018-04-19 misonyo Porting for gd32f30x - */ - -#include "drv_i2c.h" -#include -#include "gd32f30x.h" - -#ifdef RT_USING_I2C - -#include - -#define DBG_TAG "drv.I2C" -#ifdef RT_I2C_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif -#include - -#ifdef RT_USING_I2C_BITOPS - -/*user can change this*/ -#define I2C_BUS_NAME "i2c2" - -/*user should change this to adapt specific board*/ -#define I2C_SCL_PIN GPIO_PIN_4 -#define I2C_SCL_PORT GPIOE -#define I2C_SCL_CLK RCU_GPIOE -#define I2C_SDA_PIN GPIO_PIN_5 -#define I2C_SDA_PORT GPIOE -#define I2C_SDA_CLK RCU_GPIOE - -struct gd32_i2c_bit_data -{ - struct - { - rcu_periph_enum clk; - rt_uint32_t port; - rt_uint32_t pin; - }scl, sda; -}; - -static void gpio_set_sda(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - - if (state) - { - gpio_bit_set(bd->sda.port, bd->sda.pin); - } - else - { - gpio_bit_reset(bd->sda.port, bd->sda.pin); - } -} - -static void gpio_set_scl(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - if (state) - { - gpio_bit_set(bd->scl.port, bd->scl.pin); - } - else - { - gpio_bit_reset(bd->scl.port, bd->scl.pin); - } -} - -static rt_int32_t gpio_get_sda(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->sda.port, bd->sda.pin); -} - -static rt_int32_t gpio_get_scl(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->scl.port, bd->scl.pin); -} - -static void gpio_udelay(rt_uint32_t us) -{ - int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us); - while(i) - { - i--; - } -} - -static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd) -{ - rcu_periph_clock_enable(bd->sda.clk); - rcu_periph_clock_enable(bd->scl.clk); - gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin); - gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin); - - gpio_bit_set(bd->sda.port, bd->sda.pin); - gpio_bit_set(bd->scl.port, bd->scl.pin); -} - -#else /* use hardware i2c */ - -struct gd32_i2c_bus -{ - struct rt_i2c_bus_device parent; - rt_uint32_t i2c_periph; -}; - -static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - if(1 == data_byte){ - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - - /* while there is data to be read */ - while(data_byte) - { - /* wait until the RBNE bit is set and clear it */ - if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) - { - /* read a byte from the EEPROM */ - *p_buffer = i2c_data_receive(i2c_periph); - - /* point to the next location where the byte read will be saved */ - p_buffer++; - - /* decrement the read bytes counter */ - data_byte--; - if(1 == data_byte) - { - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - } - } - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - /* enable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_ENABLE); - - i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT); - - return 0; -} - -static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - /* wait until the transmit data buffer is empty */ - while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE)); - - /* while there is data to be read */ - while(data_byte) - { - i2c_data_transmit(i2c_periph, *p_buffer); - - /* point to the next byte to be written */ - p_buffer++; - - /* decrement the write bytes counter */ - data_byte --; - - /* wait until BTC bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC)); - } - - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - return 0; -} - -static rt_ssize_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) -{ - struct rt_i2c_msg *msg; - rt_uint32_t i; - rt_err_t ret = -RT_ERROR; - - struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus; - - for (i = 0; i < num; i++) - { - msg = &msgs[i]; - - if (msg->flags & RT_I2C_ADDR_10BIT) - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0); - } - else - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0); - } - if (msg->flags & RT_I2C_RD) - { - if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - else - { - if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - } - - ret = i; - -out: - LOG_E("send stop condition\n"); - - return ret; -} - -static const struct rt_i2c_bus_device_ops i2c_ops = -{ - gd32_i2c_xfer, - RT_NULL, - RT_NULL -}; - -#endif /* RT_USING_I2C_BITOPS */ - -int rt_hw_i2c_init(void) -{ -#ifdef RT_USING_I2C_BITOPS - { - static struct rt_i2c_bus_device i2c_device; - static const struct gd32_i2c_bit_data _i2c_bdata = - { - /* SCL */ - { I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN}, - /* SDA */ - { I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN}, - }; - - static const struct rt_i2c_bit_ops _i2c_bit_ops = - { - (void*)&_i2c_bdata, - gpio_set_sda, - gpio_set_scl, - gpio_get_sda, - gpio_get_scl, - gpio_udelay, - 1, - 100 - }; - - drv_i2c_gpio_init(&_i2c_bdata); - - i2c_device.priv = (void *)&_i2c_bit_ops; - rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); - } - -#else /* register hardware I2C */ - -#ifdef RT_USING_I2C0 -#define I2C0_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c0; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB6 to I2C0_SCL, PB7 to I2C0_SDA */ - gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_6 | GPIO_PIN_7); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C0); - /* configure I2C clock */ - i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2); - - i2c_enable(I2C0); - /* enable acknowledge */ - i2c_ack_config(I2C0,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c0.parent.ops = &i2c_ops; - gd32_i2c0.i2c_periph = I2C0; - rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0"); -#endif - -#ifdef RT_USING_I2C1 -#define I2C1_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c1; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB10 to I2C1_SCL, PB11 to I2C1_SDA */ - gpio_init(GPIOB, GPIO_MODE_AF_OD, GPIO_OSPEED_50MHZ, GPIO_PIN_10 | GPIO_PIN_11); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C1); - /* configure I2C clock */ - i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2); - - i2c_enable(I2C1); - /* enable acknowledge */ - i2c_ack_config(I2C1,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c1.parent.ops = &i2c_ops; - gd32_i2c1.i2c_periph = I2C1; - rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1"); -#endif - -#endif /* RT_USING_I2C_BITOPS */ - - return 0; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); - -#endif -/* end of i2c driver */ diff --git a/bsp/gd32303e-eval/drivers/drv_i2c.h b/bsp/gd32303e-eval/drivers/drv_i2c.h deleted file mode 100644 index c4b321594c..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_i2c.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-05 tanek first implementation. - */ - -#ifndef __DRV_I2C__ -#define __DRV_I2C__ - - -#endif diff --git a/bsp/gd32303e-eval/drivers/drv_soft_spi.c b/bsp/gd32303e-eval/drivers/drv_soft_spi.c deleted file mode 100644 index 7fb053d0d3..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_soft_spi.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-10-11 kyle first implementation. - */ - -#include "drv_soft_spi.h" -#include -#include - -#if defined(RT_USING_SPI) && defined(RT_USING_SPI_BITOPS) && defined(RT_USING_PIN) -#include -#include "spi-bit-ops.h" - -#define DBG_TAG "drv.SPI" -#ifdef RT_SPI_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_WARNING -#endif -#include - -#ifndef ITEM_NUM -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -#endif - -struct gd32_spi_bit_data -{ - struct - { - rcu_periph_enum clk; - rt_uint32_t port; - rt_uint32_t pin; - } sclk, mosi, miso; -}; - - -rt_inline FlagStatus GPIO_OUTPUT_BIT_GET(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -rt_inline void GPIO_BIT_RESET(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -rt_inline void GPIO_BIT_SET(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -rt_inline FlagStatus GPIO_INPUT_BIT_GET(uint32_t gpio_periph,uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -rt_inline void GPIO_INIT(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t temp_mode = 0U; - uint32_t reg = 0U; - - /* GPIO mode configuration */ - temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU)); - - /* GPIO speed configuration */ - if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){ - /* output mode max speed:10MHz,2MHz,50MHz */ - temp_mode |= (uint32_t)speed; - } - - /* configure the eight low port pins with GPIO_CTL0 */ - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL0(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL0 register */ - GPIO_CTL0(gpio_periph) = reg; - } - } - /* configure the eight high port pins with GPIO_CTL1 */ - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ - reg = GPIO_CTL1(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i - 8U); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i - 8U, temp_mode); - - /* set IPD or IPU */ - if(GPIO_MODE_IPD == mode){ - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin); - }else{ - /* set the corresponding OCTL bit */ - if(GPIO_MODE_IPU == mode){ - GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin); - } - } - /* set GPIO_CTL1 register */ - GPIO_CTL1(gpio_periph) = reg; - } - } -} - -#define GPIO_SET_OUTPUT(port, pin) GPIO_INIT(port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, pin) -#define GPIO_SET_INPUT(port, pin) GPIO_INIT(port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, pin) - - -static void gpio_tog_sclk(void *data) -{ - struct gd32_spi_bit_data *bd = data; - - if (GPIO_OUTPUT_BIT_GET(bd->sclk.port, bd->sclk.pin) == SET) - { - GPIO_BIT_RESET(bd->sclk.port, bd->sclk.pin); - } - else - { - GPIO_BIT_SET(bd->sclk.port, bd->sclk.pin); - } -} - -static void gpio_set_sclk(void *data, rt_int32_t state) -{ - struct gd32_spi_bit_data *bd = data; - - if (state) - { - GPIO_BIT_SET(bd->sclk.port, bd->sclk.pin); - } - else - { - GPIO_BIT_RESET(bd->sclk.port, bd->sclk.pin); - } -} - -static void gpio_set_mosi(void *data, rt_int32_t state) -{ - struct gd32_spi_bit_data *bd = data; - - if (state) - { - GPIO_BIT_SET(bd->mosi.port, bd->mosi.pin); - } - else - { - GPIO_BIT_RESET(bd->mosi.port, bd->mosi.pin); - } -} - -static void gpio_set_miso(void *data, rt_int32_t state) -{ - struct gd32_spi_bit_data *bd = data; - - if (state) - { - GPIO_BIT_SET(bd->miso.port, bd->miso.pin); - } - else - { - GPIO_BIT_RESET(bd->miso.port, bd->miso.pin); - } -} - -static rt_int32_t gpio_get_sclk(void *data) -{ - struct gd32_spi_bit_data *bd = data; - - return GPIO_INPUT_BIT_GET(bd->sclk.port, bd->sclk.pin); -} - -static rt_int32_t gpio_get_mosi(void *data) -{ - struct gd32_spi_bit_data *bd = data; - - return GPIO_INPUT_BIT_GET(bd->mosi.port, bd->mosi.pin); -} - -static rt_int32_t gpio_get_miso(void *data) -{ - struct gd32_spi_bit_data *bd = data; - - return GPIO_INPUT_BIT_GET(bd->miso.port, bd->miso.pin); -} - -static void gpio_dir_mosi(void *data, rt_int32_t state) -{ - struct gd32_spi_bit_data *bd = data; - - if (state) - { - GPIO_SET_INPUT(bd->mosi.port, bd->mosi.pin); - } - else - { - GPIO_SET_OUTPUT(bd->mosi.port, bd->mosi.pin); - } -} - -static void gpio_dir_miso(void *data, rt_int32_t state) -{ - struct gd32_spi_bit_data *bd = data; - - if (state) - { - GPIO_SET_INPUT(bd->miso.port, bd->miso.pin); - } - else - { - GPIO_SET_OUTPUT(bd->miso.port, bd->miso.pin); - } -} - -static void gpio_udelay(rt_uint32_t us) -{ - int i = ((rcu_clock_freq_get(CK_SYS) / 4000000) * us); - - while (i) - { - i--; - } -} - -static void soft_spi_gpio_init(const struct gd32_spi_bit_data *bd) -{ - rcu_periph_clock_enable(bd->sclk.clk); - rcu_periph_clock_enable(bd->mosi.clk); - rcu_periph_clock_enable(bd->miso.clk); - - gpio_init(bd->sclk.port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, bd->sclk.pin); - gpio_init(bd->mosi.port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, bd->mosi.pin); - gpio_init(bd->miso.port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, bd->miso.pin); - - GPIO_BIT_SET(bd->sclk.port, bd->sclk.pin); - GPIO_BIT_SET(bd->mosi.port, bd->mosi.pin); - GPIO_BIT_SET(bd->miso.port, bd->miso.pin); -} - -int rt_soft_spi_init(void) -{ - int result = 0; - - { - static const struct gd32_spi_bit_data spi1_bdata = - { - .sclk = { RCU_GPIOB, GPIOB, GPIO_PIN_13}, - .mosi = { RCU_GPIOB, GPIOB, GPIO_PIN_15}, - .miso = { RCU_GPIOB, GPIOB, GPIO_PIN_14}, - }; - static struct rt_spi_bit_ops spi1_bops = - { - .data = (void *)&spi1_bdata, - .tog_sclk = gpio_tog_sclk, - .set_sclk = gpio_set_sclk, - .set_mosi = gpio_set_mosi, - .set_miso = gpio_set_miso, - .get_sclk = gpio_get_sclk, - .get_mosi = gpio_get_mosi, - .get_miso = gpio_get_miso, - .dir_mosi = gpio_dir_mosi, - .dir_miso = gpio_dir_miso, - .udelay = gpio_udelay, - }; - struct rt_spi_bit_obj spi1_obj; - - soft_spi_gpio_init(&spi1_bdata); - rt_spi_bit_add_bus(&spi1_obj, "spi3", &spi1_bops); - } - - return result; -} -INIT_BOARD_EXPORT(rt_soft_spi_init); -#endif diff --git a/bsp/gd32303e-eval/drivers/drv_soft_spi.h b/bsp/gd32303e-eval/drivers/drv_soft_spi.h deleted file mode 100644 index be297e1c5e..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_soft_spi.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-10-11 kyle first implementation. - */ - -#ifndef __DRV_SOFT_SPI_H__ -#define __DRV_SOFT_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -int rt_soft_spi_init(void); - -#ifdef __cplusplus -} -#endif - -#endif // __DRV_SPI_H__ diff --git a/bsp/gd32303e-eval/drivers/drv_spi.c b/bsp/gd32303e-eval/drivers/drv_spi.c deleted file mode 100644 index 34e597bad6..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_spi.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-05 tanek first implementation. - * 2018-04-19 misonyo Porting for gd32f30x - */ - -#include "drv_spi.h" -#include "gd32f30x.h" -#include - -#if defined(RT_USING_SPI) && defined(RT_USING_PIN) -#include - -#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \ - !defined(RT_USING_SPI2) -#error "Please define at least one SPIx" -#endif - -/* #define DEBUG */ -#ifdef DEBUG -#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) -#else -#define DEBUG_PRINTF(...) -#endif - -/* private rt-thread spi ops function */ -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); - -static struct rt_spi_ops gd32_spi_ops = -{ - configure, - xfer -}; - -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) -{ - spi_parameter_struct spi_init_struct; - - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); - - if(configuration->data_width <= 8) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; - } - else if(configuration->data_width <= 16) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; - } - else - { - return -RT_EIO; - } - - { - rcu_clock_freq_enum spi_src; - rt_uint32_t spi_apb_clock; - rt_uint32_t max_hz; - - max_hz = configuration->max_hz; - - DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS)); - DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2)); - DEBUG_PRINTF("max freq: %d\n", max_hz); - - if (spi_periph == SPI1 || spi_periph == SPI2) - { - spi_src = CK_APB1; - } - else - { - spi_src = CK_APB2; - } - spi_apb_clock = rcu_clock_freq_get(spi_src); - - if(max_hz >= spi_apb_clock/2) - { - spi_init_struct.prescale = SPI_PSC_2; - } - else if (max_hz >= spi_apb_clock/4) - { - spi_init_struct.prescale = SPI_PSC_4; - } - else if (max_hz >= spi_apb_clock/8) - { - spi_init_struct.prescale = SPI_PSC_8; - } - else if (max_hz >= spi_apb_clock/16) - { - spi_init_struct.prescale = SPI_PSC_16; - } - else if (max_hz >= spi_apb_clock/32) - { - spi_init_struct.prescale = SPI_PSC_32; - } - else if (max_hz >= spi_apb_clock/64) - { - spi_init_struct.prescale = SPI_PSC_64; - } - else if (max_hz >= spi_apb_clock/128) - { - spi_init_struct.prescale = SPI_PSC_128; - } - else - { - /* min prescaler 256 */ - spi_init_struct.prescale = SPI_PSC_256; - } - } /* baudrate */ - - switch(configuration->mode & RT_SPI_MODE_3) - { - case RT_SPI_MODE_0: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - break; - case RT_SPI_MODE_1: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; - case RT_SPI_MODE_2: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; - case RT_SPI_MODE_3: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; - break; - } - - /* MSB or LSB */ - if(configuration->mode & RT_SPI_MSB) - { - spi_init_struct.endian = SPI_ENDIAN_MSB; - } - else - { - spi_init_struct.endian = SPI_ENDIAN_LSB; - } - - spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_init_struct.device_mode = SPI_MASTER; - spi_init_struct.nss = SPI_NSS_SOFT; - - spi_init(spi_periph, &spi_init_struct); - - spi_crc_off(spi_periph); - - spi_enable(spi_periph); - - return RT_EOK; -}; - -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) -{ - rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data; - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - struct rt_spi_configuration * config = &device->config; - - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - - /* take CS */ - if(message->cs_take) - { - rt_pin_write(gd32_cs_pin, PIN_LOW); - DEBUG_PRINTF("spi take cs\n"); - } - - { - if(config->data_width <= 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - DEBUG_PRINTF("spi poll transfer start: %d\n", size); - - while(size--) - { - rt_uint8_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - // Todo: replace register read/write by gd32f3 lib - //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - // Send the byte - spi_i2s_data_transmit(spi_periph, data); - - //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - // Get the received data - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - DEBUG_PRINTF("spi poll transfer finsh\n"); - } - else if(config->data_width <= 16) - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - while(size--) - { - rt_uint16_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - // Send the byte - spi_i2s_data_transmit(spi_periph, data); - - //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - // Get the received data - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - } - } - - /* release CS */ - if(message->cs_release) - { - rt_pin_write(gd32_cs_pin, PIN_HIGH); - DEBUG_PRINTF("spi release cs\n"); - } - - return message->length; -}; - -int gd32_hw_spi_init(void) -{ - int result = 0; -#ifdef RT_USING_SPI0 - static struct rt_spi_bus spi_bus0; - spi_bus0.parent.user_data = (void *)SPI0; - - result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_SPI0); - /* SPI0_SCK(PA5), SPI0_MISO(PA6) and SPI0_MOSI(PA7) GPIO pin configuration */ - gpio_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_7); - gpio_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_6); - -#endif -#ifdef RT_USING_SPI1 - static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; - - result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_SPI1); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI1_SCK(PB13), SPI1_MISO(PB14) and SPI1_MOSI(PB15) GPIO pin configuration */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_15); - gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_14); -#endif -#ifdef RT_USING_SPI2 - static struct rt_spi_bus spi_bus2; - spi_bus2.parent.user_data = (void *)SPI2; - - result = rt_spi_bus_register(&spi_bus2, "spi2", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_SPI2); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI2_SCK(PB3), SPI2_MISO(PB4) and SPI2_MOSI(PB5) GPIO pin configuration */ - gpio_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_3 | GPIO_PIN_5); - gpio_init(GPIOB, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, GPIO_PIN_4); -#endif - return result; -} -INIT_BOARD_EXPORT(gd32_hw_spi_init); -#endif diff --git a/bsp/gd32303e-eval/drivers/drv_spi.h b/bsp/gd32303e-eval/drivers/drv_spi.h deleted file mode 100644 index ba8e55916a..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_spi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-01 aozima first implementation. - */ - -#ifndef gd32F30X_SPI_H_INCLUDED -#define gd32F30X_SPI_H_INCLUDED - - -#endif // gd32F30X_SPI_H_INCLUDED diff --git a/bsp/gd32303e-eval/drivers/drv_spi_flash.c b/bsp/gd32303e-eval/drivers/drv_spi_flash.c deleted file mode 100644 index bf7a1310b1..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_spi_flash.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-01 aozima first implementation. - * 2018-03-30 misonyo porting to gd32f30x - */ -#include -#include -#include -#include "spi_flash.h" -#include "spi_flash_sfud.h" - -#define SPI_BUS_NAME "spi0" -#define SPI_DEVICE_NAME "spi01" -#define SPI_FLASH_DEVICE_NAME "gd25q" -#define GD25Q_SPI_CS_PIN 2 //PE3，在 drv_gpio.c 文件 pin_index pins[]中查到 PE3 ç¼–å·ä¸º 2 - -static int rt_hw_gd25q40_init(void) -{ - rt_err_t res; - static struct rt_spi_device spi_dev_gd25q; /* SPI设备对象 */ - static rt_base_t gd25q_cs_pin; /* SPI设备CS片选引脚 */ - - gd25q_cs_pin = GD25Q_SPI_CS_PIN; - - rt_pin_mode(GD25Q_SPI_CS_PIN, GPIO_MODE_OUT_PP); - - res = rt_spi_bus_attach_device(&spi_dev_gd25q, SPI_DEVICE_NAME, SPI_BUS_NAME, (void*)gd25q_cs_pin); - if (res != RT_EOK) - { - rt_kprintf("rt_spi_bus_attach_device() run failed!\n"); - return res; - } - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_gd25q40_init); - -static int rt_hw_spi_flash_with_sfud_init(void) -{ - if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_DEVICE_NAME, SPI_DEVICE_NAME)) - { - return -RT_ERROR; - } - - return RT_EOK; -} -INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); - -#ifdef RT_USING_DFS -#include - -int mnt_init(void) -{ - if (dfs_mount(SPI_FLASH_DEVICE_NAME, "/", "elm", 0, 0) == 0) - { - rt_kprintf("spi flash mount success !\n"); - } - else - { - rt_kprintf("spi flash mount failed!\n"); - } - - return 0; -} -MSH_CMD_EXPORT(mnt_init, mount spi flash to file system); -#endif diff --git a/bsp/gd32303e-eval/drivers/drv_usart.c b/bsp/gd32303e-eval/drivers/drv_usart.c deleted file mode 100644 index 07077f5cba..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_usart.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - * 2018-04-19 misonyo Porting for gd32f30x - */ - -#include -#include -#include -#include "gd32f30x.h" - -#ifdef RT_USING_SERIAL - -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) && \ - !defined(RT_USING_USART2) && !defined(RT_USING_UART3) && \ - !defined(RT_USING_UART4) -#error "Please define at least one UARTx" - -#endif - -#include - -/* GD32 uart driver */ -// Todo: compress uart info -struct gd32_uart -{ - uint32_t uart_periph; - IRQn_Type irqn; - rcu_periph_enum per_clk; - rcu_periph_enum tx_gpio_clk; - rcu_periph_enum rx_gpio_clk; - uint32_t tx_port; - uint16_t tx_pin; - uint32_t rx_port; - uint16_t rx_pin; - - struct rt_serial_device * serial; - char *device_name; -}; - -static void uart_isr(struct rt_serial_device *serial); - -#if defined(RT_USING_USART0) -struct rt_serial_device serial0; - -void USART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial0); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_USART0 */ - -#if defined(RT_USING_USART1) -struct rt_serial_device serial1; - -void USART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial1); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART1 */ - -#if defined(RT_USING_USART2) -struct rt_serial_device serial2; - -void USART2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial2); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART2 */ - -#if defined(RT_USING_UART3) -struct rt_serial_device serial3; - -void UART3_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial3); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART3 */ - -#if defined(RT_USING_UART4) -struct rt_serial_device serial4; - -void UART4_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial4); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* RT_USING_UART4 */ - -static const struct gd32_uart uarts[] = { - #ifdef RT_USING_USART0 - { - USART0, // uart peripheral index - USART0_IRQn, // uart iqrn - RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_PIN_9, // tx port, tx pin - GPIOA, GPIO_PIN_10, // rx port, rx pin - &serial0, - "uart0", - }, - #endif - - #ifdef RT_USING_USART1 - { - USART1, // uart peripheral index - USART1_IRQn, // uart iqrn - RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_PIN_2, // tx port, tx pin - GPIOA, GPIO_PIN_3, // rx port, rx pin - &serial1, - "uart1", - }, - #endif - - #ifdef RT_USING_USART2 - { - USART2, // uart peripheral index - USART2_IRQn, // uart iqrn - RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock - GPIOB, GPIO_PIN_10, // tx port, tx alternate, tx pin - GPIOB, GPIO_PIN_11, // rx port, rx alternate, rx pin - &serial2, - "uart2", - }, - #endif - - #ifdef RT_USING_UART3 - { - UART3, // uart peripheral index - UART3_IRQn, // uart iqrn - RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_PIN_10, // tx port, tx alternate, tx pin - GPIOC, GPIO_PIN_11, // rx port, rx alternate, rx pin - &serial3, - "uart3", - }, - #endif - - #ifdef RT_USING_UART4 - { - UART4, // uart peripheral index - UART4_IRQn, // uart iqrn - RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_PIN_12, // tx port, tx alternate, tx pin - GPIOD, GPIO_PIN_2, // rx port, rx alternate, rx pin - &serial4, - "uart4", - }, - #endif -}; - - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example: -* - Peripheral's clock enable -* - Peripheral's GPIO Configuration -* - NVIC configuration for UART interrupt request enable -* @param uart: UART handle pointer -* @retval None -*/ -void gd32_uart_gpio_init(struct gd32_uart *uart) -{ - /* enable USART clock */ - rcu_periph_clock_enable(uart->tx_gpio_clk); - rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); - - /* connect port to USARTx_Tx */ - gpio_init(uart->tx_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ - gpio_init(uart->rx_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, uart->rx_pin); - - NVIC_SetPriority(uart->irqn, 0); - NVIC_EnableIRQ(uart->irqn); -} - -static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = (struct gd32_uart *)serial->parent.user_data; - - gd32_uart_gpio_init(uart); - - usart_baudrate_set(uart->uart_periph, cfg->baud_rate); - - switch (cfg->data_bits) - { - case DATA_BITS_9: - usart_word_length_set(uart->uart_periph, USART_WL_9BIT); - break; - - default: - usart_word_length_set(uart->uart_periph, USART_WL_8BIT); - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT); - break; - default: - usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT); - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - usart_parity_config(uart->uart_periph, USART_PM_ODD); - break; - case PARITY_EVEN: - usart_parity_config(uart->uart_periph, USART_PM_EVEN); - break; - default: - usart_parity_config(uart->uart_periph, USART_PM_NONE); - break; - } - - usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE); - usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE); - usart_enable(uart->uart_periph); - - return RT_EOK; -} - -static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irqn); - /* disable interrupt */ - usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); - - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irqn); - /* enable interrupt */ - usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); - break; - } - - return RT_EOK; -} - -static int gd32_putc(struct rt_serial_device *serial, char ch) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - usart_data_transmit(uart->uart_periph, ch); - while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - - return 1; -} - -static int gd32_getc(struct rt_serial_device *serial) -{ - int ch; - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - ch = -1; - if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET) - ch = usart_data_receive(uart->uart_periph); - return ch; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) -{ - struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; - - RT_ASSERT(uart != RT_NULL); - - /* UART in mode Receiver */ - if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && - (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - /* Clear RXNE interrupt flag */ - usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE); - } -} - -static const struct rt_uart_ops gd32_uart_ops = -{ - gd32_configure, - gd32_control, - gd32_putc, - gd32_getc -}; - -int gd32_hw_usart_init(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - int i; - - for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) - { - uarts[i].serial->ops = &gd32_uart_ops; - uarts[i].serial->config = config; - - /* register UART device */ - rt_hw_serial_register(uarts[i].serial, - uarts[i].device_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&uarts[i]); - } - - return 0; -} -INIT_BOARD_EXPORT(gd32_hw_usart_init); -#endif diff --git a/bsp/gd32303e-eval/drivers/drv_usart.h b/bsp/gd32303e-eval/drivers/drv_usart.h deleted file mode 100644 index 4059092706..0000000000 --- a/bsp/gd32303e-eval/drivers/drv_usart.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - */ - -#ifndef __USART_H__ -#define __USART_H__ - - -#endif diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_eval.c b/bsp/gd32303e-eval/drivers/gd32f303e_eval.c deleted file mode 100644 index c8982455a2..0000000000 --- a/bsp/gd32303e-eval/drivers/gd32f303e_eval.c +++ /dev/null @@ -1,206 +0,0 @@ -/*! - \file gd32f303e_eval.c - \brief firmware functions to manage leds, keys, COM ports -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-05-19, V1.0.0, demo for GD32F30x -*/ - -#include -#include "gd32f303e_eval.h" - -/* private variables */ -static uint32_t GPIO_PORT[LEDn] = {LED2_GPIO_PORT, LED3_GPIO_PORT, - LED4_GPIO_PORT, LED5_GPIO_PORT}; -static uint32_t GPIO_PIN[LEDn] = {LED2_PIN, LED3_PIN, LED4_PIN, LED5_PIN}; - -static rcu_periph_enum COM_CLK[COMn] = {EVAL_COM1_CLK, EVAL_COM2_CLK}; -static uint32_t COM_TX_PIN[COMn] = {EVAL_COM1_TX_PIN, EVAL_COM2_TX_PIN}; -static uint32_t COM_RX_PIN[COMn] = {EVAL_COM1_RX_PIN, EVAL_COM2_RX_PIN}; -static uint32_t COM_GPIO_PORT[COMn] = {EVAL_COM1_GPIO_PORT, EVAL_COM2_GPIO_PORT}; -static rcu_periph_enum COM_GPIO_CLK[COMn] = {EVAL_COM1_GPIO_CLK, EVAL_COM2_GPIO_CLK}; - -static rcu_periph_enum GPIO_CLK[LEDn] = {LED2_GPIO_CLK, LED3_GPIO_CLK, - LED4_GPIO_CLK, LED5_GPIO_CLK}; - -static uint32_t KEY_PORT[KEYn] = {WAKEUP_KEY_GPIO_PORT, - TAMPER_KEY_GPIO_PORT, - USER_KEY1_GPIO_PORT, - USER_KEY2_GPIO_PORT}; -static uint32_t KEY_PIN[KEYn] = {WAKEUP_KEY_PIN, TAMPER_KEY_PIN,USER_KEY1_PIN,USER_KEY2_PIN}; -static rcu_periph_enum KEY_CLK[KEYn] = {WAKEUP_KEY_GPIO_CLK, - TAMPER_KEY_GPIO_CLK, - USER_KEY1_GPIO_CLK, - USER_KEY2_GPIO_CLK}; -static exti_line_enum KEY_EXTI_LINE[KEYn] = {WAKEUP_KEY_EXTI_LINE, - TAMPER_KEY_EXTI_LINE, - USER_KEY1_EXTI_LINE, - USER_KEY2_EXTI_LINE}; -static uint8_t KEY_PORT_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PORT_SOURCE, - TAMPER_KEY_EXTI_PORT_SOURCE, - USER_KEY1_EXTI_PORT_SOURCE, - USER_KEY2_EXTI_PORT_SOURCE}; -static uint8_t KEY_PIN_SOURCE[KEYn] = {WAKEUP_KEY_EXTI_PIN_SOURCE, - TAMPER_KEY_EXTI_PIN_SOURCE, - USER_KEY1_EXTI_PIN_SOURCE, - USER_KEY2_EXTI_PIN_SOURCE}; -static uint8_t KEY_IRQn[KEYn] = {WAKEUP_KEY_EXTI_IRQn, - TAMPER_KEY_EXTI_IRQn, - USER_KEY1_EXTI_IRQn, - USER_KEY2_EXTI_IRQn}; - -/*! - \brief configure led GPIO - \param[in] lednum: specify the led to be configured - \arg LED2 - \arg LED3 - \arg LED4 - \arg LED5 - \param[out] none - \retval none -*/ -void gd_eval_led_init (led_typedef_enum lednum) -{ - /* enable the led clock */ - rcu_periph_clock_enable(GPIO_CLK[lednum]); - /* configure led GPIO port */ - gpio_init(GPIO_PORT[lednum], GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ,GPIO_PIN[lednum]); - - GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; -} - -/*! - \brief turn on selected led - \param[in] lednum: specify the led to be turned on - \arg LED2 - \arg LED3 - \arg LED4 - \arg LED5 - \param[out] none - \retval none -*/ -void gd_eval_led_on(led_typedef_enum lednum) -{ - GPIO_BOP(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; -} - -/*! - \brief turn off selected led - \param[in] lednum: specify the led to be turned off - \arg LED2 - \arg LED3 - \arg LED4 - \arg LED5 - \param[out] none - \retval none -*/ -void gd_eval_led_off(led_typedef_enum lednum) -{ - GPIO_BC(GPIO_PORT[lednum]) = GPIO_PIN[lednum]; -} - -/*! - \brief toggle selected led - \param[in] lednum: specify the led to be toggled - \arg LED2 - \arg LED3 - \arg LED4 - \arg LED5 - \param[out] none - \retval none -*/ -void gd_eval_led_toggle(led_typedef_enum lednum) -{ - gpio_bit_write(GPIO_PORT[lednum], GPIO_PIN[lednum], - (bit_status)(1-gpio_input_bit_get(GPIO_PORT[lednum], GPIO_PIN[lednum]))); -} - -/*! - \brief configure key - \param[in] key_num: specify the key to be configured - \arg KEY_TAMPER: tamper key - \arg KEY_WAKEUP: wakeup key - \arg KEY_USER1: user key1 - \arg KEY_USER2: user key2 - \param[in] key_mode: specify button mode - \arg KEY_MODE_GPIO: key will be used as simple IO - \arg KEY_MODE_EXTI: key will be connected to EXTI line with interrupt - \param[out] none - \retval none -*/ -void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode) -{ - /* enable the key clock */ - rcu_periph_clock_enable(KEY_CLK[key_num]); - rcu_periph_clock_enable(RCU_AF); - - /* configure button pin as input */ - gpio_init(KEY_PORT[key_num], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, KEY_PIN[key_num]); - - if (key_mode == KEY_MODE_EXTI) { - /* enable and set key EXTI interrupt to the lowest priority */ - nvic_irq_enable(KEY_IRQn[key_num], 2U, 0U); - - /* connect key EXTI line to key GPIO pin */ - gpio_exti_source_select(KEY_PORT_SOURCE[key_num], KEY_PIN_SOURCE[key_num]); - - /* configure key EXTI line */ - exti_init(KEY_EXTI_LINE[key_num], EXTI_INTERRUPT, EXTI_TRIG_FALLING); - exti_interrupt_flag_clear(KEY_EXTI_LINE[key_num]); - } -} - -/*! - \brief return the selected key state - \param[in] key: specify the key to be checked - \arg KEY_TAMPER: tamper key - \arg KEY_WAKEUP: wakeup key - \arg KEY_USER1: user key - \arg KEY_USER2: user key2 - \param[out] none - \retval the key's GPIO pin value -*/ -uint8_t gd_eval_key_state_get(key_typedef_enum key) -{ - return gpio_input_bit_get(KEY_PORT[key], KEY_PIN[key]); -} - -/*! - \brief configure COM port - \param[in] com: COM on the board - \arg EVAL_COM1: COM1 on the board - \arg EVAL_COM2: COM2 on the board - \param[out] none - \retval none -*/ -void gd_eval_com_init(uint32_t com) -{ - uint32_t com_id = 0U; - if(EVAL_COM1 == com){ - com_id = 0U; - }else if(EVAL_COM2 == com){ - com_id = 1U; - } - - /* enable GPIO clock */ - rcu_periph_clock_enable(COM_GPIO_CLK[com_id]); - - /* enable USART clock */ - rcu_periph_clock_enable(COM_CLK[com_id]); - - /* connect port to USARTx_Tx */ - gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, COM_TX_PIN[com_id]); - - /* connect port to USARTx_Rx */ - gpio_init(COM_GPIO_PORT[com_id], GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, COM_RX_PIN[com_id]); - - /* USART configure */ - usart_deinit(com); - usart_baudrate_set(com, 115200U); - usart_receive_config(com, USART_RECEIVE_ENABLE); - usart_transmit_config(com, USART_TRANSMIT_ENABLE); - usart_enable(com); -} diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_eval.h b/bsp/gd32303e-eval/drivers/gd32f303e_eval.h deleted file mode 100644 index 932102cbd7..0000000000 --- a/bsp/gd32303e-eval/drivers/gd32f303e_eval.h +++ /dev/null @@ -1,137 +0,0 @@ -/*! - \file gd32f303e_eval.h - \brief definitions for GD32f303E_EVAL's leds, keys and COM ports hardware resources -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-05-19, V1.0.0, demo for GD32F30x -*/ - -#ifndef GD32F303E_EVAL_H -#define GD32F303E_EVAL_H - -#ifdef cplusplus - extern "C" { -#endif - -#include "gd32f30x.h" - -/* exported types */ -typedef enum -{ - LED2 = 0, - LED3 = 1, - LED4 = 2, - LED5 = 3 -} led_typedef_enum; - -typedef enum -{ - KEY_WAKEUP = 0, - KEY_TAMPER = 1, - KEY_USER1 = 2, - KEY_USER2 = 3 -} key_typedef_enum; - -typedef enum -{ - KEY_MODE_GPIO = 0, - KEY_MODE_EXTI = 1 -} keymode_typedef_enum; - -/* eval board low layer led */ -#define LEDn 4U - -#define LED2_PIN GPIO_PIN_0 -#define LED2_GPIO_PORT GPIOF -#define LED2_GPIO_CLK RCU_GPIOF - -#define LED3_PIN GPIO_PIN_1 -#define LED3_GPIO_PORT GPIOF -#define LED3_GPIO_CLK RCU_GPIOF - -#define LED4_PIN GPIO_PIN_2 -#define LED4_GPIO_PORT GPIOF -#define LED4_GPIO_CLK RCU_GPIOF - -#define LED5_PIN GPIO_PIN_3 -#define LED5_GPIO_PORT GPIOF -#define LED5_GPIO_CLK RCU_GPIOF - -#define COMn 2U - -#define EVAL_COM1 USART0 -#define EVAL_COM1_CLK RCU_USART0 -#define EVAL_COM1_TX_PIN GPIO_PIN_9 -#define EVAL_COM1_RX_PIN GPIO_PIN_10 -#define EVAL_COM1_GPIO_PORT GPIOA -#define EVAL_COM1_GPIO_CLK RCU_GPIOA - -#define EVAL_COM2 USART1 -#define EVAL_COM2_CLK RCU_USART1 -#define EVAL_COM2_TX_PIN GPIO_PIN_2 -#define EVAL_COM2_RX_PIN GPIO_PIN_3 -#define EVAL_COM2_GPIO_PORT GPIOA -#define EVAL_COM2_GPIO_CLK RCU_GPIOA - -#define KEYn 4U - -/* wakeup push-button */ -#define WAKEUP_KEY_PIN GPIO_PIN_0 -#define WAKEUP_KEY_GPIO_PORT GPIOA -#define WAKEUP_KEY_GPIO_CLK RCU_GPIOA -#define WAKEUP_KEY_EXTI_LINE EXTI_0 -#define WAKEUP_KEY_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOA -#define WAKEUP_KEY_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_0 -#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn - -/* tamper push-button */ -#define TAMPER_KEY_PIN GPIO_PIN_13 -#define TAMPER_KEY_GPIO_PORT GPIOC -#define TAMPER_KEY_GPIO_CLK RCU_GPIOC -#define TAMPER_KEY_EXTI_LINE EXTI_13 -#define TAMPER_KEY_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOC -#define TAMPER_KEY_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_13 -#define TAMPER_KEY_EXTI_IRQn EXTI10_15_IRQn - -/* user push-button */ -#define USER_KEY1_PIN GPIO_PIN_5 -#define USER_KEY1_GPIO_PORT GPIOF -#define USER_KEY1_GPIO_CLK RCU_GPIOF -#define USER_KEY1_EXTI_LINE EXTI_5 -#define USER_KEY1_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOF -#define USER_KEY1_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_5 -#define USER_KEY1_EXTI_IRQn EXTI5_9_IRQn - -/* user push-button */ -#define USER_KEY2_PIN GPIO_PIN_4 -#define USER_KEY2_GPIO_PORT GPIOF -#define USER_KEY2_GPIO_CLK RCU_GPIOF -#define USER_KEY2_EXTI_LINE EXTI_4 -#define USER_KEY2_EXTI_PORT_SOURCE GPIO_PORT_SOURCE_GPIOF -#define USER_KEY2_EXTI_PIN_SOURCE GPIO_PIN_SOURCE_4 -#define USER_KEY2_EXTI_IRQn EXTI4_IRQn - -/* function declarations */ -/* configure led GPIO */ -void gd_eval_led_init(led_typedef_enum lednum); -/* turn on selected led */ -void gd_eval_led_on(led_typedef_enum lednum); -/* turn off selected led */ -void gd_eval_led_off(led_typedef_enum lednum); -/* toggle the selected led */ -void gd_eval_led_toggle(led_typedef_enum lednum); -/* configure key */ -void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode); -/* return the selected key state */ -uint8_t gd_eval_key_state_get(key_typedef_enum key); -/* configure COM port */ -void gd_eval_com_init(uint32_t com); - -#ifdef cplusplus -} -#endif - -#endif /* GD32F303E_EVAL_H */ diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c deleted file mode 100644 index 3ca126e87e..0000000000 --- a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.c +++ /dev/null @@ -1,496 +0,0 @@ -/*! - \file gd32f303e_lcd_eval.c - \brief LCD driver functions -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-05-19, V1.0.0, demo for GD32F30x -*/ - -#include "gd32f30x.h" -#include "gd32f303e_lcd_eval.h" -#include "lcd_font.h" - -/*! - \brief lcd peripheral initialize - \param[in] none - \param[out] none - \retval none -*/ -void exmc_lcd_init(void) -{ - exmc_norsram_parameter_struct lcd_init_struct; - exmc_norsram_timing_parameter_struct lcd_timing_init_struct; - - /* EXMC clock enable */ - rcu_periph_clock_enable(RCU_EXMC); - - /* GPIO clock enable */ - rcu_periph_clock_enable(RCU_GPIOD); - rcu_periph_clock_enable(RCU_GPIOE); - rcu_periph_clock_enable(RCU_GPIOG); - - /* configure EXMC_D[0~15]*/ - /* PD14(EXMC_D0), PD15(EXMC_D1),PD0(EXMC_D2), PD1(EXMC_D3), PD8(EXMC_D13), PD9(EXMC_D14), PD10(EXMC_D15) */ - gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_8 | GPIO_PIN_9 | - GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); - - /* PE7(EXMC_D4), PE8(EXMC_D5), PE9(EXMC_D6), PE10(EXMC_D7), PE11(EXMC_D8), PE12(EXMC_D9), - PE13(EXMC_D10), PE14(EXMC_D11), PE15(EXMC_D12) */ - gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | - GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | - GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - - /* configure PE2(EXMC_A23) */ - gpio_init(GPIOE, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_2); - - /* configure NOE and NWE */ - gpio_init(GPIOD, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_4 | GPIO_PIN_5); - - /* configure EXMC NE1 */ - gpio_init(GPIOG, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); - - lcd_timing_init_struct.asyn_access_mode = EXMC_ACCESS_MODE_A; - lcd_timing_init_struct.syn_data_latency = EXMC_DATALAT_2_CLK; - lcd_timing_init_struct.syn_clk_division = EXMC_SYN_CLOCK_RATIO_DISABLE; - lcd_timing_init_struct.bus_latency = 2; - lcd_timing_init_struct.asyn_data_setuptime = 10; - lcd_timing_init_struct.asyn_address_holdtime = 2; - lcd_timing_init_struct.asyn_address_setuptime = 5; - - lcd_init_struct.norsram_region = EXMC_BANK0_NORSRAM_REGION1; - lcd_init_struct.write_mode = EXMC_ASYN_WRITE; - lcd_init_struct.extended_mode = DISABLE; - lcd_init_struct.asyn_wait = DISABLE; - lcd_init_struct.nwait_signal = DISABLE; - lcd_init_struct.memory_write = ENABLE; - lcd_init_struct.nwait_config = EXMC_NWAIT_CONFIG_BEFORE; - lcd_init_struct.wrap_burst_mode = DISABLE; - lcd_init_struct.nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - lcd_init_struct.burst_mode = DISABLE; - lcd_init_struct.databus_width = EXMC_NOR_DATABUS_WIDTH_16B; - lcd_init_struct.memory_type = EXMC_MEMORY_TYPE_SRAM; - lcd_init_struct.address_data_mux = DISABLE; - lcd_init_struct.read_write_timing = &lcd_timing_init_struct; - lcd_init_struct.write_timing = &lcd_timing_init_struct; - - exmc_norsram_init(&lcd_init_struct); - - exmc_norsram_enable(EXMC_BANK0_NORSRAM_REGION1); -} - - -/*! - \brief write data to the selected LCD register - \param[in] register_id: the selected register id - \param[in] value: the register value to be written - \param[out] none - \retval none -*/ - -void lcd_register_write(uint16_t register_id,uint16_t value) -{ - *(__IO uint16_t *) (BANK0_LCD_C)= register_id; - *(__IO uint16_t *) (BANK0_LCD_D)= value; -} - -/*! - \brief read the value of LCD register - \param[in] register_id: the register id - \param[out] none - \retval the register value -*/ -uint16_t lcd_register_read(uint8_t register_id) -{ - uint16_t data; - *(__IO uint16_t *) (BANK0_LCD_C)= register_id; - data = *(__IO uint16_t *) (BANK0_LCD_D); - return data; -} - -/*! - \brief write command to LCD register - \param[in] value: the register value to be written - \param[out] none - \retval none -*/ -void lcd_command_write(uint16_t value) -{ - /* write 16-bit index, then write reg */ - *(__IO uint16_t *) (BANK0_LCD_D) = value; -} - -/*! - \brief prepare to write to the LCD GRAM register(R22h) - \param[in] none - \param[out] none - \retval none -*/ -void lcd_gram_write_prepare(void) -{ - *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022; -} - -/*! - \brief write RGB code to the LCD GRAM register - \param[in] rgb_code: the pixel color in RGB mode (5-6-5) - \param[out] none - \retval none -*/ -void lcd_gram_write(uint16_t rgb_code) -{ - /* write 16-bit GRAM register */ - *(__IO uint16_t *) (BANK0_LCD_D) = rgb_code; -} - -/*! - \brief read data from GRAM - \param[in] none - \param[out] none - \retval GRAM value -*/ -uint16_t lcd_gram_read(void) -{ - uint16_t data; - - /* write GRAM register (R22h) */ - *(__IO uint16_t *) (BANK0_LCD_C) = 0x0022; - /* dummy read (invalid data) */ - *(__IO uint16_t *) (BANK0_LCD_D); - - data = *(__IO uint16_t *) (BANK0_LCD_D); - return data; -} - -/*! - \brief initialize the LCD - \param[in] none - \param[out] none - \retval none -*/ -void lcd_init(void) -{ - uint16_t i; - - if(1){ /*!< if(device_code == 0x8989) */ - lcd_register_write(0x0000,0x0001); - lcd_register_write(0x0003,0xA8A4); - lcd_register_write(0x000C,0x0000); - lcd_register_write(0x000D,0x080C); - lcd_register_write(0x000E,0x2B00); - lcd_register_write(0x001E,0x00B0); - lcd_register_write(0x0001,0x2B3F); - lcd_register_write(0x0002,0x0600); - lcd_register_write(0x0010,0x0000); - lcd_register_write(0x0011,0x6070); - lcd_register_write(0x0005,0x0000); - lcd_register_write(0x0006,0x0000); - lcd_register_write(0x0016,0xEF1C); - lcd_register_write(0x0017,0x0003); - lcd_register_write(0x0007,0x0233); - lcd_register_write(0x000B,0x0000); - lcd_register_write(0x000F,0x0000); - lcd_register_write(0x0041,0x0000); - lcd_register_write(0x0042,0x0000); - lcd_register_write(0x0048,0x0000); - lcd_register_write(0x0049,0x013F); - lcd_register_write(0x004A,0x0000); - lcd_register_write(0x004B,0x0000); - lcd_register_write(0x0044,0xEF00); - lcd_register_write(0x0045,0x0000); - lcd_register_write(0x0046,0x013F); - lcd_register_write(0x0030,0x0707); - lcd_register_write(0x0031,0x0204); - lcd_register_write(0x0032,0x0204); - lcd_register_write(0x0033,0x0502); - lcd_register_write(0x0034,0x0507); - lcd_register_write(0x0035,0x0204); - lcd_register_write(0x0036,0x0204); - lcd_register_write(0x0037,0x0502); - lcd_register_write(0x003A,0x0302); - lcd_register_write(0x003B,0x0302); - lcd_register_write(0x0023,0x0000); - lcd_register_write(0x0024,0x0000); - lcd_register_write(0x0025,0x8000); - lcd_register_write(0x004e,0); - lcd_register_write(0x004f,0); - }else{ - return; - } - - for(i=50000;i>0;i--); -} - -/*! - \brief set the cursor of LCD - \param[in] x: the row-coordinate - \param[in] y: the column-coordinate - \param[out] none - \retval none -*/ -void lcd_cursor_set(uint16_t x,uint16_t y) -{ - lcd_register_write(0x004e,x); - lcd_register_write(0x004f,y); - -} - -/*! - \brief clear the LCD screen to the specified color - \param[in] color: specified screen color - \param[out] none - \retval none -*/ -void lcd_clear(uint16_t color) -{ - uint32_t index=0; - lcd_cursor_set(0,0); - /* prepare to write GRAM */ - lcd_gram_write_prepare(); - for(index=0;index<76800;index++){ - *(__IO uint16_t *) (BANK0_LCD_D) = color; - } -} - -/*! - \brief set the point according to the specified position and color - \param[in] x: the row-coordinate - \param[in] y: the column-coordinate - \param[in] point: specified color of the point - \param[out] none - \retval none -*/ -void lcd_point_set(uint16_t x,uint16_t y,uint16_t point) -{ - if ((x > 240)||(y > 320)){ - return; - } - lcd_cursor_set(x,y); - lcd_gram_write_prepare(); - lcd_gram_write(point); -} - -/*! - \brief get point GRAM according to the specified position - \param[in] x: the row-coordinate - \param[in] y: the column-coordinate - \param[out] none - \retval GRAM value of point -*/ -uint16_t lcd_point_get(uint16_t x,uint16_t y) -{ - uint16_t data; - - if ((x > 240)||(y > 320)){ - return 0; - } - - lcd_cursor_set(x,y); - data = lcd_gram_read(); - - return data; -} - -/*! - \brief set window area - \param[in] start_x: the start position of row-coordinate - \param[in] start_y: the start position of column-coordinate - \param[in] end_x: the end position of row-coordinate - \param[in] end_y: the end position of column-coordinate - \param[out] none - \retval none -*/ -void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y) -{ - lcd_cursor_set(start_x, start_y); - - lcd_register_write(0x0050, start_x); - lcd_register_write(0x0052, start_y); - lcd_register_write(0x0051, end_x); - lcd_register_write(0x0053, end_y); -} - -/*! - \brief draw a horizontal line on LCD screen - \param[in] x: the row-coordinate - \param[in] start_y: the start column-coordinate - \param[in] end_y: the end column-coordinate - \param[in] color: specified color of the point - \param[in] width: line width - \param[out] none - \retval none -*/ - -void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width) -{ - uint16_t i, y; - - for (i = 0; i < width; i++) { - uint16_t sx = x + i; - - for (y = start_y; y < end_y; y++) { - lcd_point_set(sx, y, color); - } - } -} - -/*! - \brief draw a rectangle according to the specified position and color - \param[in] start_x: the start position of row-coordinate - \param[in] start_y: the start position of column-coordinate - \param[in] end_x: the end position of row-coordinate - \param[in] end_y: the end position of column-coordinate - \param[in] point: specified color of the point - \param[out] none - \retval none -*/ -void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point) -{ - uint16_t x,y; - x=start_x; - y=start_y; - /* draw four lines */ - for(x=start_x;xstart_x;x--){ - lcd_point_set(x,y,point); - } - for(y=end_y;y>start_y;y--){ - lcd_point_set(x,y,point); - } -} - -/*! - \brief fill the specified color to a rectangle - \param[in] start_x: the start position of row-coordinate - \param[in] start_y: the start position of column-coordinate - \param[in] end_x: the end position of row-coordinate - \param[in] end_y: the end position of column-coordinate - \param[in] color: specified color - \param[out] none - \retval none -*/ -void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color) -{ - uint16_t x, y; - x = start_x; - y = start_y; - - for (x = start_x; x < end_x; x++) { - for (y = start_y; y < end_y; y++) { - lcd_point_set(x, y, color); - } - } -} - -/*! - \brief draw a picture on LCD screen according to the specified position - \param[in] start_x: the start position of row-coordinate - \param[in] start_y: the start position of column-coordinate - \param[in] end_x: the end position of row-coordinate - \param[in] end_y: the end position of column-coordinate - \param[in] pic: the picture pointer - \param[out] none - \retval none -*/ -void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic) -{ - uint32_t i, total; - uint16_t *picturepointer = pic; - uint16_t x,y; - - x = start_x; - y = start_y; - - total = (end_x - start_x + 1) * (end_y - start_y + 1); - - for(i = 0; i < total; i ++){ - /* set point according to the specified position and color */ - lcd_point_set(x,y,*picturepointer++); - x++; - if(x > end_x){ - y++; - x = start_x; - } - } -} - -/*! - \brief display a char on LCD screen according to the specified position - \param[in] x: the start position of row-coordinate - \param[in] y: the start position of column-coordinate - \param[in] c: the char - \param[in] char_color: the color of char - \param[in] c_format: the struct of char format - font: CHAR_FONT_8_16 or CHAR_FONT_16_24 - direction: CHAR_DIRECTION_HORIZONTAL or CHAR_DIRECTION_VERTICAL - char_color: the color of char - bk_color: the color of backgroud - \param[out] none - \retval none -*/ -void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format) -{ - uint16_t i = 0, j = 0; - uint8_t temp_char = 0; - uint16_t temp_char_16 = 0; - - if(CHAR_FONT_8_16 == c_format.font){ /* 8x16 ASCII */ - for (i = 0; i < 16; i++) { - temp_char = ascii_8x16[((c - 0x20) * 16) + i]; - if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){ - for (j = 0; j < 8; j++) { - if (((temp_char >> (7 - j)) & 0x01) == 0x01) { - /* set point of char */ - lcd_point_set(x - i, y + j, c_format.char_color); - } else { - /* set point of background */ - lcd_point_set(x - i, y + j, c_format.bk_color); - } - } - }else{ - for (j = 0; j < 8; j++) { - if (((temp_char >> (7 - j)) & 0x01) == 0x01) { - /* set point of char */ - lcd_point_set(x + j, y + i, c_format.char_color); - } else { - /* set point of background */ - lcd_point_set(x + j, y + i, c_format.bk_color); - } - } - } - } - }else if(CHAR_FONT_16_24 == c_format.font){ /* 16x24 ASCII */ - for (i = 0; i < 24; i++) { - temp_char_16 = ASCII_Table_16x24[((c - 0x20) * 24) + i]; - if(CHAR_DIRECTION_HORIZONTAL == c_format.direction){ - for (j = 0; j < 16; j++) { - if (((temp_char_16 >> j) & 0x01) == 0x01) { - /* set point of char */ - lcd_point_set(x - i, y + j, c_format.char_color); - } else { - /* set point of background */ - lcd_point_set(x - i, y + j, c_format.bk_color); - } - } - }else{ - for (j = 0; j < 16; j++) { - if (((temp_char_16 >> j) & 0x01) == 0x01) { - /* set point of char */ - lcd_point_set(x + j, y + i, c_format.char_color); - } else { - /* set point of background */ - lcd_point_set(x + j, y + i, c_format.bk_color); - } - } - } - } - } -} diff --git a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h b/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h deleted file mode 100644 index db76bc17d5..0000000000 --- a/bsp/gd32303e-eval/drivers/gd32f303e_lcd_eval.h +++ /dev/null @@ -1,208 +0,0 @@ -/*! - \file gd32f303e_lcd_eval.h - \brief LCD driver header file -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-05-19, V1.0.0, demo for GD32F30x -*/ - -#ifndef GD32F303E_LCD_EVAL_H -#define GD32F303E_LCD_EVAL_H - -#include "gd32f30x.h" - -#define BANK0_LCD_D ((uint32_t)0x65000000) /*!< LCD data address */ -#define BANK0_LCD_C ((uint32_t)0x64000000) /*!< LCD register address */ - -/* LCD registers */ -#define R0 0x00 -#define R1 0x01 -#define R2 0x02 -#define R3 0x03 -#define R4 0x04 -#define R5 0x05 -#define R6 0x06 -#define R7 0x07 -#define R8 0x08 -#define R9 0x09 -#define R10 0x0A -#define R11 0x0B -#define R12 0x0C -#define R13 0x0D -#define R14 0x0E -#define R15 0x0F -#define R16 0x10 -#define R17 0x11 -#define R18 0x12 -#define R19 0x13 -#define R20 0x14 -#define R21 0x15 -#define R22 0x16 -#define R23 0x17 -#define R24 0x18 -#define R25 0x19 -#define R26 0x1A -#define R27 0x1B -#define R28 0x1C -#define R29 0x1D -#define R30 0x1E -#define R31 0x1F -#define R32 0x20 -#define R33 0x21 -#define R34 0x22 -#define R35 0x23 -#define R36 0x24 -#define R37 0x25 -#define R40 0x28 -#define R41 0x29 -#define R43 0x2B -#define R45 0x2D -#define R48 0x30 -#define R49 0x31 -#define R50 0x32 -#define R51 0x33 -#define R52 0x34 -#define R53 0x35 -#define R54 0x36 -#define R55 0x37 -#define R56 0x38 -#define R57 0x39 -#define R58 0x3A -#define R59 0x3B -#define R60 0x3C -#define R61 0x3D -#define R62 0x3E -#define R63 0x3F -#define R64 0x40 -#define R65 0x41 -#define R66 0x42 -#define R67 0x43 -#define R68 0x44 -#define R69 0x45 -#define R70 0x46 -#define R71 0x47 -#define R72 0x48 -#define R73 0x49 -#define R74 0x4A -#define R75 0x4B -#define R76 0x4C -#define R77 0x4D -#define R78 0x4E -#define R79 0x4F -#define R80 0x50 -#define R81 0x51 -#define R82 0x52 -#define R83 0x53 -#define R96 0x60 -#define R97 0x61 -#define R106 0x6A -#define R118 0x76 -#define R128 0x80 -#define R129 0x81 -#define R130 0x82 -#define R131 0x83 -#define R132 0x84 -#define R133 0x85 -#define R134 0x86 -#define R135 0x87 -#define R136 0x88 -#define R137 0x89 -#define R139 0x8B -#define R140 0x8C -#define R141 0x8D -#define R143 0x8F -#define R144 0x90 -#define R145 0x91 -#define R146 0x92 -#define R147 0x93 -#define R148 0x94 -#define R149 0x95 -#define R150 0x96 -#define R151 0x97 -#define R152 0x98 -#define R153 0x99 -#define R154 0x9A -#define R157 0x9D -#define R192 0xC0 -#define R193 0xC1 -#define R229 0xE5 - -/* LCD color */ -#define WHITE 0xFFFF -#define BLACK 0x0000 -#define GREY 0xF7DE -#define BLUE 0x001F -#define BLUE2 0x051F -#define RED 0xF800 -#define MAGENTA 0xF81F -#define GREEN 0x07E0 -#define CYAN 0x7FFF -#define YELLOW 0xFFE0 - -#define LINE0 0 -#define LINE1 24 -#define LINE2 48 -#define LINE3 72 -#define LINE4 96 -#define LINE5 120 -#define LINE6 144 -#define LINE7 168 -#define LINE8 192 -#define LINE9 216 - -/* char format struct definitions */ -typedef struct -{ - uint16_t font; /*!< the type of font */ - uint16_t direction; /*!< the direction of char */ - uint16_t char_color; /*!< the color of char */ - uint16_t bk_color; /*!< the color of backgroud */ -}char_format_struct; - -#define CHAR_FONT_8_16 ((uint16_t)0x0000U) /*!< the font of char is 8X16 */ -#define CHAR_FONT_16_24 ((uint16_t)0x0001U) /*!< the font of char is 16X24 */ - -#define CHAR_DIRECTION_HORIZONTAL ((uint16_t)0x0000U) /*!< character display direction is horizontal */ -#define CHAR_DIRECTION_VERTICAL ((uint16_t)0x0001U) /*!< character display direction is vertical */ - -/* lcd peripheral initialize */ -void exmc_lcd_init(void); -/* initize the LCD */ -void lcd_init(void); -/* write data to the selected LCD register */ -void lcd_register_write(uint16_t register_id,uint16_t value); -/* read the value of LCD register */ -uint16_t lcd_register_read(uint8_t register_id); -/* write command to LCD register */ -void lcd_command_write (uint16_t value); -/* prepare to write to the LCD GRAM */ -void lcd_gram_write_prepare(void); -/* write RGB code to the LCD GRAM register */ -void lcd_gram_write(uint16_t rgb_code); -/* read data from GRAM */ -uint16_t lcd_gram_read(void); -/* set the curson of LCD */ -void lcd_cursor_set(uint16_t x,uint16_t y); -/* clear the LCD screen to the specified color */ -void lcd_clear(uint16_t Color); -/* set the point according to the specified position and color */ -void lcd_point_set(uint16_t x,uint16_t y,uint16_t point); -/* get the point according to the specified position */ -uint16_t lcd_point_get(uint16_t x,uint16_t y); -/* set window area */ -void lcd_windows_set(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y); -/* draw a horizontal line on LCD screen */ -void lcd_hline_draw(uint16_t x,uint16_t start_y,uint16_t end_y,uint16_t color,uint16_t width); -/* draw a rectangle according to the specified position and color */ -void lcd_rectangle_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t point); -/* fill the specified color to a rectangle */ -void lcd_rectangle_fill(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t color); -/* draw a picture on LCD screen according to the specified position */ -void lcd_picture_draw(uint16_t start_x,uint16_t start_y,uint16_t end_x,uint16_t end_y,uint16_t *pic); -/* display a char on LCD screen according to the specified position */ -void lcd_char_display(uint16_t x,uint16_t y,uint8_t c,char_format_struct c_format); - -#endif /* GD32F303E_LCD_EVAL_H */ diff --git a/bsp/gd32303e-eval/drivers/gd32f30x_libopt.h b/bsp/gd32303e-eval/drivers/gd32f30x_libopt.h deleted file mode 100644 index c731ac8f98..0000000000 --- a/bsp/gd32303e-eval/drivers/gd32f30x_libopt.h +++ /dev/null @@ -1,42 +0,0 @@ -/*! - \file gd32f30x_libopt.h - \brief library optional for gd32f30x -*/ - -/* - Copyright (C) 2017 GigaDevice - - 2017-05-19, V1.0.0, demo for GD32F30x -*/ - -#ifndef GD32F30X_LIBOPT_H -#define GD32F30X_LIBOPT_H - -#include "gd32f30x_rcu.h" -#include "gd32f30x_adc.h" -#include "gd32f30x_can.h" -#include "gd32f30x_crc.h" -#include "gd32f30x_ctc.h" -#include "gd32f30x_dac.h" -#include "gd32f30x_dbg.h" -#include "gd32f30x_dma.h" -#include "gd32f30x_exti.h" -#include "gd32f30x_fmc.h" -#include "gd32f30x_fwdgt.h" -#include "gd32f30x_gpio.h" -#include "gd32f30x_i2c.h" -#include "gd32f30x_pmu.h" -#include "gd32f30x_bkp.h" -#include "gd32f30x_rtc.h" -#include "gd32f30x_sdio.h" -#include "gd32f30x_spi.h" -#include "gd32f30x_timer.h" -#include "gd32f30x_usart.h" -#include "gd32f30x_wwdgt.h" -#include "gd32f30x_misc.h" -#include "gd32f30x_exmc.h" -#ifdef GD32F30X_CL -#include "gd32f30x_enet.h" -#endif /* GD32F30X_CL */ - -#endif /* GD32F30X_LIBOPT_H */ diff --git a/bsp/gd32303e-eval/gd32_rom.icf b/bsp/gd32303e-eval/gd32_rom.icf deleted file mode 100644 index 27790e4197..0000000000 --- a/bsp/gd32303e-eval/gd32_rom.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807ffff; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -export symbol __ICFEDIT_region_RAM_end__; - -define symbol __region_RAM1_start__ = 0x10000000; -define symbol __region_RAM1_end__ = 0x1000FFFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; diff --git a/bsp/gd32303e-eval/gd32_rom.ld b/bsp/gd32303e-eval/gd32_rom.ld deleted file mode 100644 index a017d88f4d..0000000000 --- a/bsp/gd32303e-eval/gd32_rom.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linker script for GD32F30x with GNU ld - * bernard.xiong 2009-10-14 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 64KB sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/gd32303e-eval/gd32_rom.sct b/bsp/gd32303e-eval/gd32_rom.sct deleted file mode 100644 index abc5462a3f..0000000000 --- a/bsp/gd32303e-eval/gd32_rom.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x000080000 { ; load region size_region - ER_IROM1 0x08000000 0x000080000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/gd32303e-eval/project.ewd b/bsp/gd32303e-eval/project.ewd deleted file mode 100644 index 5f99340356..0000000000 --- a/bsp/gd32303e-eval/project.ewd +++ /dev/null @@ -1,2834 +0,0 @@ - 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### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f30x - 0x4 - ARM-ADS - - 16000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000 - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL010000 -FP0($$Device:GD32F303ZE$Flash\GD32F30x_HD.FLM)) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/gd32303e-eval/project.uvprojx b/bsp/gd32303e-eval/project.uvprojx deleted file mode 100644 index b8558d36fe..0000000000 --- a/bsp/gd32303e-eval/project.uvprojx +++ /dev/null @@ -1,1213 +0,0 @@ - - - 2.1 -
### uVision Project, (C) Keil Software
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0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x80000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - GD32F30X_HD, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__ - - ..\..\components\drivers\include;..\..\components\libc\posix\io\poll;..\..\components\libc\compilers\common\include;.;..\..\components\libc\posix\io\eventfd;..\..\components\libc\compilers\common\extension;..\..\components\drivers\spi\sfud\inc;..\..\libcpu\arm\cortex-m4;drivers;..\..\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\dfs\dfs_v1\include;Libraries\CMSIS;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\libc\posix\ipc;applications;..\..\components\drivers\include;..\..\components\dfs\dfs_v1\filesystems\elmfat;..\..\libcpu\arm\common;..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\components\dfs\dfs_v1\filesystems\devfs;Libraries\GD32F30x_standard_peripheral\Include;..\..\components\libc\posix\io\epoll;Libraries\CMSIS\GD\GD32F30x\Include;..\..\components\finsh - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Applications - - - main.c - 1 - applications\main.c - - - - - Compiler - - - syscall_mem.c - 1 - ..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\components\libc\compilers\common\cctype.c - - - - - cstdlib.c - 1 - ..\..\components\libc\compilers\common\cstdlib.c - - - - - cstring.c - 1 - ..\..\components\libc\compilers\common\cstring.c - - - - - ctime.c - 1 - ..\..\components\libc\compilers\common\ctime.c - - - - - cunistd.c - 1 - ..\..\components\libc\compilers\common\cunistd.c - - - - - cwchar.c - 1 - ..\..\components\libc\compilers\common\cwchar.c - - - - - CPU - - - div0.c - 1 - ..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\libcpu\arm\common\showmem.c - - - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S - - - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c - - - - - DeviceDrivers - - - device.c - 1 - ..\..\components\drivers\core\device.c - - - - - --c99 - - - - - - - - - - - - i2c_core.c - 1 - ..\..\components\drivers\i2c\i2c_core.c - - - - - --c99 - - - - - - - - - - - - i2c_dev.c - 1 - ..\..\components\drivers\i2c\i2c_dev.c - - - - - --c99 - - - - - - - - - - - - completion.c - 1 - ..\..\components\drivers\ipc\completion.c - - - - - --c99 - - - - - - - - - - - - dataqueue.c - 1 - ..\..\components\drivers\ipc\dataqueue.c - - - - - --c99 - - - - - - - - - - - - pipe.c - 1 - ..\..\components\drivers\ipc\pipe.c - - - - - --c99 - - - - - - - - - - - - ringblk_buf.c - 1 - ..\..\components\drivers\ipc\ringblk_buf.c - - - - - --c99 - - - - - - - - - - - - ringbuffer.c - 1 - ..\..\components\drivers\ipc\ringbuffer.c - - - - - --c99 - - - - - - - - - - - - waitqueue.c - 1 - ..\..\components\drivers\ipc\waitqueue.c - - - - - --c99 - - - - - - - - - - - - workqueue.c - 1 - ..\..\components\drivers\ipc\workqueue.c - - - - - --c99 - - - - - - - - - - - - pin.c - 1 - ..\..\components\drivers\misc\pin.c - - - - - --c99 - - - - - - - - - - - - serial.c - 1 - ..\..\components\drivers\serial\serial.c - - - - - --c99 - - - - - - - - - - - - sfud.c - 1 - ..\..\components\drivers\spi\sfud\src\sfud.c - - - - - --c99 - - - - - - - - - - - - spi_core.c - 1 - ..\..\components\drivers\spi\spi_core.c - - - - - --c99 - - - - - - - - - - - - spi_dev.c - 1 - ..\..\components\drivers\spi\spi_dev.c - - - - - --c99 - - - - - - - - - - - - spi_flash_sfud.c - 1 - ..\..\components\drivers\spi\spi_flash_sfud.c - - - - - --c99 - - - - - - - - - - - - Drivers - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_spi.c - 1 - drivers\drv_spi.c - - - - - drv_i2c.c - 1 - drivers\drv_i2c.c - - - - - drv_spi_flash.c - 1 - drivers\drv_spi_flash.c - - - - - drv_usart.c - 1 - drivers\drv_usart.c - - - - - board.c - 1 - drivers\board.c - - - - - Filesystem - - - devfs.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c - - - - - dfs_elm.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c - - - - - ff.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c - - - - - ffunicode.c - 1 - ..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c - - - - - dfs.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs.c - - - - - dfs_file.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_file.c - - - - - dfs_fs.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_fs.c - - - - - dfs_posix.c - 1 - ..\..\components\dfs\dfs_v1\src\dfs_posix.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - msh_parse.c - 1 - ..\..\components\finsh\msh_parse.c - - - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - msh_file.c - 1 - ..\..\components\finsh\msh_file.c - - - - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler_up.c - 1 - ..\..\src\scheduler_up.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - Libraries - - - gd32f30x_dac.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_dac.c - - - - - gd32f30x_usart.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_usart.c - - - - - gd32f30x_dma.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_dma.c - - - - - gd32f30x_timer.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_timer.c - - - - - gd32f30x_exmc.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_exmc.c - - - - - gd32f30x_enet.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_enet.c - - - - - gd32f30x_rcu.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_rcu.c - - - - - gd32f30x_i2c.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_i2c.c - - - - - gd32f30x_gpio.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_gpio.c - - - - - startup_gd32f30x_hd.s - 2 - Libraries\CMSIS\GD\GD32F30x\Source\ARM\startup_gd32f30x_hd.s - - - - - gd32f30x_misc.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_misc.c - - - - - gd32f30x_bkp.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_bkp.c - - - - - gd32f30x_fwdgt.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_fwdgt.c - - - - - gd32f30x_wwdgt.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_wwdgt.c - - - - - system_gd32f30x.c - 1 - Libraries\CMSIS\GD\GD32F30x\Source\system_gd32f30x.c - - - - - gd32f30x_sdio.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_sdio.c - - - - - gd32f30x_ctc.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_ctc.c - - - - - gd32f30x_crc.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_crc.c - - - - - gd32f30x_fmc.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_fmc.c - - - - - gd32f30x_exti.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_exti.c - - - - - gd32f30x_adc.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_adc.c - - - - - gd32f30x_rtc.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_rtc.c - - - - - gd32f30x_can.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_can.c - - - - - gd32f30x_dbg.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_dbg.c - - - - - gd32f30x_spi.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_spi.c - - - - - gd32f30x_pmu.c - 1 - Libraries\GD32F30x_standard_peripheral\Source\gd32f30x_pmu.c - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32303e-eval/rtconfig.h b/bsp/gd32303e-eval/rtconfig.h deleted file mode 100644 index 547dc72f01..0000000000 --- a/bsp/gd32303e-eval/rtconfig.h +++ /dev/null @@ -1,264 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 - -/* kservice optimization */ - -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FD_MAX 4 -#define RT_USING_DFS_V1 -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_0 -#define RT_DFS_ELM_USE_LFN 0 -#define RT_DFS_ELM_LFN_UNICODE_0 -#define RT_DFS_ELM_LFN_UNICODE 0 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 2 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096 -#define RT_DFS_ELM_REENTRANT -#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_I2C -#define RT_USING_PIN -#define RT_USING_SPI -#define RT_USING_SFUD -#define RT_SFUD_USING_FLASH_INFO_TABLE -#define RT_SFUD_SPI_MAX_HZ 50000000 - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* sensors drivers */ - - -/* touch drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -#define SOC_GD32303E -#define RT_USING_USART0 -#define RT_USING_USART1 -#define RT_USING_SPI0 -#define RT_USING_SPI1 -#define RT_USING_I2C0 - -#endif diff --git a/bsp/gd32303e-eval/rtconfig.py b/bsp/gd32303e-eval/rtconfig.py deleted file mode 100644 index 691c41e9a4..0000000000 --- a/bsp/gd32303e-eval/rtconfig.py +++ /dev/null @@ -1,126 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M4' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' - - LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - - EXEC_PATH += '/ARM/ARMCC/bin' - print(EXEC_PATH) - - CFLAGS += ' --c99' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config gd32_rom.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH += '/arm/bin/' - POST_ACTION = '' - diff --git a/bsp/gd32303e-eval/startcmd.bat b/bsp/gd32303e-eval/startcmd.bat deleted file mode 100644 index a03f9d44c3..0000000000 --- a/bsp/gd32303e-eval/startcmd.bat +++ /dev/null @@ -1 +0,0 @@ -start cmd.exe \ No newline at end of file diff --git a/bsp/gd32303e-eval/template.ewp b/bsp/gd32303e-eval/template.ewp deleted file mode 100644 index 716042958e..0000000000 --- a/bsp/gd32303e-eval/template.ewp +++ /dev/null @@ -1,1889 +0,0 @@ - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/gd32303e-eval/template.uvoptx b/bsp/gd32303e-eval/template.uvoptx deleted file mode 100644 index 8fc841b0e1..0000000000 --- a/bsp/gd32303e-eval/template.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f30x - 0x4 - ARM-ADS - - 16000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 0 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000 - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL010000 -FP0($$Device:GD32F303ZE$Flash\GD32F30x_HD.FLM)) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/gd32303e-eval/template.uvprojx b/bsp/gd32303e-eval/template.uvprojx deleted file mode 100644 index 9b0a830d22..0000000000 --- a/bsp/gd32303e-eval/template.uvprojx +++ /dev/null @@ -1,400 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread_gd32f30x - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 0 - - - GD32F303ZE - GigaDevice - GigaDevice.GD32F30x_DFP.1.0.1 - http://gd32mcu.21ic.com/data/documents/yingyongruanjian - IRAM(0x20000000-0x2000FFFF)IROM(0x08000000-0x0807FFFF) CLOCK(16000000) CPUTYPE("Cortex-M4") - - "Startup\GD\GD32F30x\startup_gd32f30x_hd.s" ("GD32F30x Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000) - 0 - gd32f30x.h - - - - - - - - - - SFD\GD\GD32F30x\GD32F30x_HD.SFR - 0 - 0 - - - - GD\GD32F30x\ - GD\GD32F30x\ - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-gd32f30x - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 1 - 0x8000000 - 0x80000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x80000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - applications;.;drivers;Libraries\CMSIS\GD\GD32F30x\Include;Libraries\CMSIS;Libraries\GD32F30x_standard_peripheral\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - --keep *.o(RTMSymTab) --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32350r-eval/.config b/bsp/gd32350r-eval/.config deleted file mode 100644 index f0837a11be..0000000000 --- a/bsp/gd32350r-eval/.config +++ /dev/null @@ -1,991 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_INIT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x50002 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -# CONFIG_RT_USING_DFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_KTIME is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# -CONFIG_SOC_GD32350R=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART1 is not set diff --git a/bsp/gd32350r-eval/EventRecorderStub.scvd b/bsp/gd32350r-eval/EventRecorderStub.scvd deleted file mode 100644 index 2956b29683..0000000000 --- a/bsp/gd32350r-eval/EventRecorderStub.scvd +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/bsp/gd32350r-eval/Kconfig b/bsp/gd32350r-eval/Kconfig deleted file mode 100644 index 907bfe3b87..0000000000 --- a/bsp/gd32350r-eval/Kconfig +++ /dev/null @@ -1,37 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -# you can change the RTT_ROOT default: "rt-thread" -# example : default "F:/git_repositories/rt-thread" - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_GD32350R - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -config BSP_USING_UART0 - bool "using uart0" - select RT_USING_SERIAL - default n -config BSP_USING_UART1 - bool "using uart1" - select RT_USING_SERIAL - default n diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h deleted file mode 100644 index 9121b966b6..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/gd32f3x0.h +++ /dev/null @@ -1,242 +0,0 @@ -/*! - \file gd32f3x0.h - \brief general definitions for gd32f3x0 - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_H -#define GD32F3X0_H - -#ifdef cplusplus - extern "C" { -#endif - -/* define GD32F3x0 */ -#if !defined (GD32F3x0) - #define GD32F3x0 -#endif /* define GD32F3x0 */ -#if !defined (GD32F3x0) - #error "Please select the target GD32F3x0 device used in your application (in gd32f3x0.h file)" -#endif /* undefine GD32F3x0 tip */ - -/* define GD32F3x0 device category */ -#if (!defined (GD32F330))&&(!defined (GD32F350)) - #error "Please select GD32F3x0 device category( GD32F330 or GD32F350 )" -#endif /* undefine GD32F330 or GD32F350 tip */ -#if (defined (GD32F330))&&(defined (GD32F350)) - #error "Please select one GD32F3x0 device category( GD32F330 or GD32F350 )" -#endif /* define GD32F330 and GD32F350 tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined (HXTAL_VALUE) -#define HXTAL_VALUE ((uint32_t)8000000) -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal RC oscillator for ADC in Hz */ -#if !defined (IRC28M_VALUE) -#define IRC28M_VALUE ((uint32_t)28000000) -#endif /* IRC28M_VALUE */ - -#if !defined (IRC48M_VALUE) -#define IRC48M_VALUE ((uint32_t)48000000) -#endif /* IRC48M_VALUE */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* GD32F3x0 firmware library version number V1.0 */ -#define __GD32F3x0_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __GD32F3x0_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32F3x0_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F3x0_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32F3x0_STDPERIPH_VERSION ((__GD32F3x0_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32F3x0_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32F3x0_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32F3x0_STDPERIPH_VERSION_RC)) - -/* configuration of the Cortex-M4 processor and core peripherals */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0U /*!< GD32F3x0 do not provide MPU */ -#define __NVIC_PRIO_BITS 4U /*!< GD32F3x0 uses 4 bits for the priority levels */ -#define __Vendor_SysTickConfig 0U /*!< set to 1 if different sysTick config is used */ -#define __FPU_PRESENT 1U /*!< FPU present */ - -/* define interrupt number */ -typedef enum IRQn -{ - /* Cortex-M4 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */ - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - RCU_CTC_IRQn = 2, /*!< RTC and CTC interrupt */ - FMC_IRQn = 3, /*!< FMC interrupt */ - RCU_IRQn = 4, /*!< RCU interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */ - TSI_IRQn = 8, /*!< TSI Interrupt */ - DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */ - DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */ - DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */ - ADC_CMP_IRQn = 12, /*!< ADC, CMP0 and CMP1 interrupts */ - TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 15, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 16, /*!< TIMER2 interrupt */ -#ifdef GD32F350 - TIMER5_DAC_IRQn = 17, /*!< TIMER5 and DAC interrupts */ -#endif /* GD32F350 */ - TIMER13_IRQn = 19, /*!< TIMER13 interrupt */ - TIMER14_IRQn = 20, /*!< TIMER14 interrupt */ - TIMER15_IRQn = 21, /*!< TIMER15 interrupt */ - TIMER16_IRQn = 22, /*!< TIMER16 interrupt */ - I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */ - I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */ - SPI0_IRQn = 25, /*!< SPI0 interrupt */ - SPI1_IRQn = 26, /*!< SPI1 interrupt */ - USART0_IRQn = 27, /*!< USART0 interrupt */ - USART1_IRQn = 28, /*!< USART1 interrupt */ -#ifdef GD32F350 - CEC_IRQn = 30, /*!< CEC interrupt */ -#endif /* GD32F350 */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - DMA_Channel5_6_IRQn = 48, /*!< DMA channel 5 and channel 6 interrupts */ -#ifdef GD32F350 - USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ - USBFS_IRQn = 67, /*!< USBFS global interrupt */ -#endif /* GD32F350 */ -} IRQn_Type; - -/* includes */ -#include "core_cm4.h" -#include "system_gd32f3x0.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ -/* SRAM and peripheral base bit-band region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */ -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ -#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ -#define CEC_BASE (APB1_BUS_BASE + 0x00007800U) /*!< CEC base address */ -#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ -/* advanced peripheral bus 2 memory map */ -#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ -#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ -/* advanced high performance bus 1 memory map */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ -#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ -#define TSI_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address */ -#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE0000U) /*!< USBFS base address */ -/* advanced high performance bus 2 memory map */ -#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ -/* option byte and debug memory map */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ - -/* define marco USE_STDPERIPH_DRIVER */ -#if !defined USE_STDPERIPH_DRIVER -#define USE_STDPERIPH_DRIVER -#endif -#ifdef USE_STDPERIPH_DRIVER -#include "gd32f3x0_libopt.h" -#endif /* USE_STDPERIPH_DRIVER */ - -#ifdef cplusplus -} -#endif -#endif diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h deleted file mode 100644 index c2e466587a..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Include/system_gd32f3x0.h +++ /dev/null @@ -1,58 +0,0 @@ -/*! - \file system_gd32f3x0.h - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for - GD32F3x0 Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32F3X0_H -#define SYSTEM_GD32F3X0_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit (void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32F3X0_H */ diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s deleted file mode 100644 index d9930d2455..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s +++ /dev/null @@ -1,318 +0,0 @@ -;/*! -; \file startup_gd32f3x0.s -; \brief start up file -; -; \version 2017-06-06, V1.0.0, firmware for GD32F3x0 -; \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -;*/ -; -;/* -; Copyright (c) 2019, GigaDevice Semiconductor Inc. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD RTC_IRQHandler ; 18:RTC through EXTI Line - DCD FMC_IRQHandler ; 19:FMC - DCD RCU_CTC_IRQHandler ; 20:RCU and CTC - DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 - DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 - DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 - DCD TSI_IRQHandler ; 24:TSI - DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 - DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 - DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 - DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator 0-1 - DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; 31:TIMER1 - DCD TIMER2_IRQHandler ; 32:TIMER2 - DCD TIMER5_DAC_IRQHandler ; 33:TIMER5 and DAC - DCD 0 ; Reserved - DCD TIMER13_IRQHandler ; 35:TIMER13 - DCD TIMER14_IRQHandler ; 36:TIMER14 - DCD TIMER15_IRQHandler ; 37:TIMER15 - DCD TIMER16_IRQHandler ; 38:TIMER16 - DCD I2C0_EV_IRQHandler ; 39:I2C0 Event - DCD I2C1_EV_IRQHandler ; 40:I2C1 Event - DCD SPI0_IRQHandler ; 41:SPI0 - DCD SPI1_IRQHandler ; 42:SPI1 - DCD USART0_IRQHandler ; 43:USART0 - DCD USART1_IRQHandler ; 44:USART1 - DCD 0 ; Reserved - DCD CEC_IRQHandler ; 46:CEC - DCD 0 ; Reserved - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD 0 ; Reserved - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA_Channel5_6_IRQHandler ; 64:DMA Channel5 and Channel6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD USBFS_IRQHandler ; 83:USBFS -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_CTC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSI_IRQHandler [WEAK] - EXPORT DMA_Channel0_IRQHandler [WEAK] - EXPORT DMA_Channel1_2_IRQHandler [WEAK] - EXPORT DMA_Channel3_4_IRQHandler [WEAK] - EXPORT ADC_CMP_IRQHandler [WEAK] - EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER5_DAC_IRQHandler [WEAK] - EXPORT TIMER13_IRQHandler [WEAK] - EXPORT TIMER14_IRQHandler [WEAK] - EXPORT TIMER15_IRQHandler [WEAK] - EXPORT TIMER16_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT USBFS_WKUP_IRQHandler [WEAK] - EXPORT DMA_Channel5_6_IRQHandler [WEAK] - EXPORT USBFS_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_CTC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSI_IRQHandler -DMA_Channel0_IRQHandler -DMA_Channel1_2_IRQHandler -DMA_Channel3_4_IRQHandler -ADC_CMP_IRQHandler -TIMER0_BRK_UP_TRG_COM_IRQHandler -TIMER0_Channel_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER5_DAC_IRQHandler -TIMER13_IRQHandler -TIMER14_IRQHandler -TIMER15_IRQHandler -TIMER16_IRQHandler -I2C0_EV_IRQHandler -I2C1_EV_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -CEC_IRQHandler -I2C0_ER_IRQHandler -I2C1_ER_IRQHandler -USBFS_WKUP_IRQHandler -DMA_Channel5_6_IRQHandler -USBFS_IRQHandler - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s deleted file mode 100644 index 2d7c70dc4a..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s +++ /dev/null @@ -1,366 +0,0 @@ -;/*! -; \file startup_gd32f3x0.s -; \brief start up file -; -; \version 2017-06-06, V1.0.0, firmware for GD32F3x0 -; \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -;*/ -; -;/* -; Copyright (c) 2019, GigaDevice Semiconductor Inc. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler - DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler - DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; Vector Number 16,Window watchdog timer - DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect - DCD RTC_IRQHandler ; Vector Number 18,RTC through EXTI Line - DCD FMC_IRQHandler ; Vector Number 19,FMC - DCD RCU_CTC_IRQHandler ; Vector Number 20,RCU and CTC - DCD EXTI0_1_IRQHandler ; Vector Number 21,EXTI Line 0 and EXTI Line 1 - DCD EXTI2_3_IRQHandler ; Vector Number 22,EXTI Line 2 and EXTI Line 3 - DCD EXTI4_15_IRQHandler ; Vector Number 23,EXTI Line 4 to EXTI Line 15 - DCD TSI_IRQHandler ; Vector Number 24,TSI - DCD DMA_Channel0_IRQHandler ; Vector Number 25,DMA Channel 0 - DCD DMA_Channel1_2_IRQHandler ; Vector Number 26,DMA Channel 1 and DMA Channel 2 - DCD DMA_Channel3_4_IRQHandler ; Vector Number 27,DMA Channel 3 and DMA Channel 4 - DCD ADC_CMP_IRQHandler ; Vector Number 28,ADC and Comparator 1-2 - DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; Vector Number 29,TIMER0 Break, Update, Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; Vector Number 30,TIMER0 Channel Capture Compare - DCD TIMER1_IRQHandler ; Vector Number 31,TIMER1 - DCD TIMER2_IRQHandler ; Vector Number 32,TIMER2 - DCD TIMER5_DAC_IRQHandler ; Vector Number 33,TIMER5 and DAC - DCD 0 ; Reserved - DCD TIMER13_IRQHandler ; Vector Number 35,TIMER13 - DCD TIMER14_IRQHandler ; Vector Number 36,TIMER14 - DCD TIMER15_IRQHandler ; Vector Number 37,TIMER15 - DCD TIMER16_IRQHandler ; Vector Number 38,TIMER16 - DCD I2C0_EV_IRQHandler ; Vector Number 39,I2C0 Event - DCD I2C1_EV_IRQHandler ; Vector Number 40,I2C1 Event - DCD SPI0_IRQHandler ; Vector Number 41,SPI0 - DCD SPI1_IRQHandler ; Vector Number 42,SPI1 - DCD USART0_IRQHandler ; Vector Number 43,USART0 - DCD USART1_IRQHandler ; Vector Number 44,USART1 - DCD 0 ; Reserved - DCD CEC_IRQHandler ; Vector Number 46,CEC - DCD 0 ; Reserved - DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error - DCD 0 ; Reserved - DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS Wakeup - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA_Channel5_6_IRQHandler ; Vector Number 64,DMA Channel5 and Channel6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD USBFS_IRQHandler ; Vector Number 83,USBFS - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_CTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_CTC_IRQHandler - B RCU_CTC_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK TSI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TSI_IRQHandler - B TSI_IRQHandler - - PUBWEAK DMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel0_IRQHandler - B DMA_Channel0_IRQHandler - - PUBWEAK DMA_Channel1_2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel1_2_IRQHandler - B DMA_Channel1_2_IRQHandler - - PUBWEAK DMA_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel3_4_IRQHandler - B DMA_Channel3_4_IRQHandler - - PUBWEAK ADC_CMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC_CMP_IRQHandler - B ADC_CMP_IRQHandler - - PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_UP_TRG_COM_IRQHandler - B TIMER0_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER5_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_DAC_IRQHandler - B TIMER5_DAC_IRQHandler - - PUBWEAK TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER13_IRQHandler - B TIMER13_IRQHandler - - PUBWEAK TIMER14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER14_IRQHandler - B TIMER14_IRQHandler - - PUBWEAK TIMER15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER15_IRQHandler - B TIMER15_IRQHandler - - PUBWEAK TIMER16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER16_IRQHandler - B TIMER16_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK USBFS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_WKUP_IRQHandler - B USBFS_WKUP_IRQHandler - - PUBWEAK DMA_Channel5_6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel5_6_IRQHandler - B DMA_Channel5_6_IRQHandler - - PUBWEAK USBFS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_IRQHandler - B USBFS_IRQHandler - - END diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c b/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c deleted file mode 100644 index d8bb8bc727..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c +++ /dev/null @@ -1,783 +0,0 @@ -/*! - \file system_gd32f3x0.c - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for - GD32F3x0 Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32f3x0.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ - -/* select a system clock by uncommenting the following line */ -#if defined (GD32F330) -//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) -//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2 (uint32_t)(72000000) -#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) -//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) -#endif /* GD32F330 */ - -#if defined (GD32F350) -//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) -//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) -//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) -//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) -//#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2 (uint32_t)(96000000) -//#define __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2 (uint32_t)(96000000) -#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) -//#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2 (uint32_t)(108000000) -#endif /* GD32F350 */ - -#define SEL_IRC8M 0x00 -#define SEL_HXTAL 0x01 -#define SEL_PLL 0x02 - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_8M_HXTAL -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; -static void system_clock_8m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; -static void system_clock_72m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2; -static void system_clock_72m_irc48m(void); - -#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL; -static void system_clock_84m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2; -static void system_clock_84m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; -static void system_clock_96m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2; -static void system_clock_96m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2; -static void system_clock_96m_irc48m(void); - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; -static void system_clock_108m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2; -static void system_clock_108m_irc8m(void); - -#else -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; -static void system_clock_8m_irc8m(void); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit (void) -{ -#if (defined(GD32F350)) - RCU_APB2EN = BIT(0); - CMP_CS |= (CMP_CS_CMP1MSEL | CMP_CS_CMP0MSEL); -#endif /* GD32F350 */ - - /* FPU settings */ -#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ -#endif - /* enable IRC8M */ - RCU_CTL0 |= RCU_CTL0_IRC8MEN; - while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ - } - /* reset RCU */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ - RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); -#if (defined(GD32F350)) - RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); - RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); -#endif /* GD32F350 */ - RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); - RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); - RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; - RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; - RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; - RCU_INT = 0x00000000U; - RCU_ADDINT = 0x00000000U; - - /* configure system clock */ - system_clock_config(); - -#ifdef VECT_TAB_SRAM - nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET); -#else - nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET); -#endif -} - -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_8M_HXTAL - system_clock_8m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) - system_clock_72m_irc48m(); -#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) - system_clock_84m_hxtal(); -#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) - system_clock_84m_irc8m(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) - system_clock_96m_hxtal(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) - system_clock_96m_irc8m(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) - system_clock_96m_irc48m(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) - system_clock_108m_hxtal(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) - system_clock_108m_irc8m(); -#else - system_clock_8m_irc8m(); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ -} - -#ifdef __SYSTEM_CLOCK_8M_HXTAL -/*! - \brief configure the system clock to 8M by HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL * 9 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL9); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) -/*! - \brief configure the system clock to 72M by PLL which selects IRC48M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc48m(void) -{ - /* enable IRC48M */ - RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN; - - /* wait until IRC48M is stable*/ - while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){ - } - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC48M/2) * 3 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL3); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) -/*! - \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_84m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL /2 * 21 = 84 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= RCU_PLL_PREDV2; - RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL21); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 84M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_84m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 21 = 84 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -/*! - \brief configure the system clock to 96M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL /2 * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= RCU_PLL_PREDV2; - RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL24); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 96M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL24); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2) -/*! - \brief configure the system clock to 96M by PLL which selects IRC48M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_irc48m(void) -{ - /* enable IRC48M */ - RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN; - - /* wait until IRC48M is stable*/ - while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){ - } - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC48M/2) * 4 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL4); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -/*! - \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL /2 * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= RCU_PLL_PREDV2; - RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL27); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 108M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#else -/*! - \brief configure the system clock to 8M by IRC8M - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select IRC8M as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; - - /* wait until IRC8M is selected as system clock */ - while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ - } -} -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate (void) -{ - uint32_t sws = 0U; - uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; - /* exponent of AHB clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* get the value of PLLMF[3:0] */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - pllmf4 = GET_BITS(RCU_CFG0, 27, 27); - pllmf5 = GET_BITS(RCU_CFG1, 31, 31); - /* high 16 bits */ - if(1U == pllmf4){ - pllmf += 17U; - }else{ - pllmf += 2U; - } - if(1U == pllmf5){ - pllmf += 31U; - } - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = GET_BITS(RCU_CFG0, 16, 16); - if(0U != pllsel){ - prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); - if(0U == pllpresel){ - SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf; - }else{ - SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf; - } - }else{ - SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - SystemCoreClock >>= clk_exp; -} diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4.h deleted file mode 100644 index d82841442c..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4.h +++ /dev/null @@ -1,1790 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4_simd.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4_simd.h deleted file mode 100644 index f9bceff1e5..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/core_cm4_simd.h +++ /dev/null @@ -1,697 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* not yet supported */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_SIMD_H */ diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cmFunc.h deleted file mode 100644 index 3c932e0d6e..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,616 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32350r-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32350r-eval/Libraries/CMSIS/core_cmInstr.h deleted file mode 100644 index 597e64df04..0000000000 --- a/bsp/gd32350r-eval/Libraries/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,618 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V3.01 - * @date 06. March 2012 - * - * @note - * Copyright (C) 2009-2012 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - - __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); - return(op1); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h deleted file mode 100644 index f184578579..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_adc.h +++ /dev/null @@ -1,365 +0,0 @@ -/*! - \file gd32f3x0_adc.h - \brief definitions for the ADC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_ADC_H -#define GD32F3X0_ADC_H - -#include "gd32f3x0.h" - -/* ADC definitions */ -#define ADC ADC_BASE - -/* registers definitions */ -#define ADC_STAT REG32(ADC + 0x00000000U) /*!< ADC status register */ -#define ADC_CTL0 REG32(ADC + 0x00000004U) /*!< ADC control register 0 */ -#define ADC_CTL1 REG32(ADC + 0x00000008U) /*!< ADC control register 1 */ -#define ADC_SAMPT0 REG32(ADC + 0x0000000CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1 REG32(ADC + 0x00000010U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0 REG32(ADC + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1 REG32(ADC + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2 REG32(ADC + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3 REG32(ADC + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT REG32(ADC + 0x00000024U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT REG32(ADC + 0x00000028U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1 REG32(ADC + 0x00000030U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2 REG32(ADC + 0x00000034U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ REG32(ADC + 0x00000038U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0 REG32(ADC + 0x0000003CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1 REG32(ADC + 0x00000040U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2 REG32(ADC + 0x00000044U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3 REG32(ADC + 0x00000048U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA REG32(ADC + 0x0000004CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL REG32(ADC + 0x00000080U) /*!< ADC oversampling control register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */ -#define ADC_CTL1_VBETEN BIT(24) /*!< VBAT enable */ - -/* ADC_SAMPTx x=0,1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..18) sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx x=0..2 */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */ - -/* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ - -/* constants definitions */ -/* ADC flag definitions */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */ - -/* ADC special function */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */ - -/* external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ -#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */ -#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - -/* external trigger select for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) -#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ -#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ -#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ -#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */ -#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* ADC data offset for inserted channel x*/ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC analog watchdog high threshold */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC analog watchdog low threshold */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC regular channel group length */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) - -/* ADC inserted channel group length */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) - -/* ADC resolution definitions */ -#define CTL0_DRES(regval) (BITS(24,25) & ((regval) << 24)) /*!< ADC resolution */ -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ - -/* ADC oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - -/* ADC oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -/* ADC triggered oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ - -/* ADC interrupt definitions */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* function declarations */ -/* reset ADC */ -void adc_deinit(void); -/* enable ADC interface */ -void adc_enable(void); -/* disable ADC interface */ -void adc_disable(void); - -/* ADC calibration and reset calibration */ -void adc_calibration_enable(void); -/* enable DMA request */ -void adc_dma_mode_enable(void); -/* disable DMA request */ -void adc_dma_mode_disable(void); - -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); -/* enable the vbat channel */ -void adc_vbat_enable(void); -/* disable the vbat channel */ -void adc_vbat_disable(void); - -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length); -/* configure ADC special function */ -void adc_special_function_config(uint32_t function, ControlStatus newvalue); - -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t data_alignment); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint8_t channel_group, uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); -/* enable ADC external trigger */ -void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue); -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint8_t channel_group); - -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(void); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint8_t inserted_channel); - -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t flag); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t flag); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t flag); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t interrupt); - -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint8_t channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint8_t channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(void); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); - -/* configure ADC resolution */ -void adc_resolution_config(uint32_t resolution); -/* configure ADC oversample mode */ -void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio); -/* enable ADC oversample mode */ -void adc_oversample_mode_enable(void); -/* disable ADC oversample mode */ -void adc_oversample_mode_disable(void); - -#endif /* GD32F3X0_ADC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h deleted file mode 100644 index 304c53437b..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cec.h +++ /dev/null @@ -1,250 +0,0 @@ -/*! - \file gd32f3x0_cec.h - \brief definitions for the CEC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifdef GD32F350 - -#ifndef GD32F3X0_CEC_H -#define GD32F3X0_CEC_H - -#include "gd32f3x0.h" - -/* CEC definitions */ -#define CEC CEC_BASE /*!< CEC base address */ - -/* registers definitions */ -#define CEC_CTL REG32(CEC + 0x00000000U) /*!< CEC control register */ -#define CEC_CFG REG32(CEC + 0x00000004U) /*!< CEC configuration register */ -#define CEC_TDATA REG32(CEC + 0x00000008U) /*!< CEC transmit data register */ -#define CEC_RDATA REG32(CEC + 0x0000000CU) /*!< CEC receive data register */ -#define CEC_INTF REG32(CEC + 0x00000010U) /*!< CEC interrupt flag Register */ -#define CEC_INTEN REG32(CEC + 0x00000014U) /*!< CEC interrupt enable register */ - -/* bits definitions */ -/* CEC_CTL */ -#define CEC_CTL_CECEN BIT(0) /*!< enable or disable HDMI-CEC controller bit */ -#define CEC_CTL_STAOM BIT(1) /*!< start of sending a message. */ -#define CEC_CTL_ENDOM BIT(2) /*!< ENDOM bit value in the next frame in Tx mode */ - -/* CEC_CFG */ -#define CEC_CFG_SFT BITS(0,2) /*!< signal free time */ -#define CEC_CFG_RTOL BIT(3) /*!< reception bit timing tolerance */ -#define CEC_CFG_BRES BIT(4) /*!< whether stop receive message when detected BRE */ -#define CEC_CFG_BREG BIT(5) /*!< generate Error-bit when detected BRE in singlecast */ -#define CEC_CFG_BPLEG BIT(6) /*!< generate Error-bit when detected BPLE in singlecast */ -#define CEC_CFG_BCNG BIT(7) /*!< do not generate Error-bit in broadcast message */ -#define CEC_CFG_SFTOPT BIT(8) /*!< the SFT start option bit */ -#define CEC_CFG_OWN_ADDRESS BITS(16,30) /*!< own address */ -#define CEC_CFG_LMEN BIT(31) /*!< listen mode enable bit */ - -/* CEC_TDATA */ -#define CEC_TDATA_TDATA BITS(0,7) /*!< Tx data register */ - -/* CEC_RDATA */ -#define CEC_RDATA_RDATA BITS(0,7) /*!< Rx data register */ - -/* CEC_INTF */ -#define CEC_INTF_BR BIT(0) /*!< Rx-byte data received */ -#define CEC_INTF_REND BIT(1) /*!< end of reception */ -#define CEC_INTF_RO BIT(2) /*!< Rx overrun */ -#define CEC_INTF_BRE BIT(3) /*!< bit rising error */ -#define CEC_INTF_BPSE BIT(4) /*!< short bit period error */ -#define CEC_INTF_BPLE BIT(5) /*!< long bit period error */ -#define CEC_INTF_RAE BIT(6) /*!< Rx ACK error */ -#define CEC_INTF_ARBF BIT(7) /*!< arbitration fail */ -#define CEC_INTF_TBR BIT(8) /*!< Tx-byte data request */ -#define CEC_INTF_TEND BIT(9) /*!< transmission successfully end */ -#define CEC_INTF_TU BIT(10) /*!< Tx data buffer underrun */ -#define CEC_INTF_TERR BIT(11) /*!< Tx-error */ -#define CEC_INTF_TAERR BIT(12) /*!< Tx ACK error flag */ - -/* CEC_INTEN */ -#define CEC_INTEN_BRIE BIT(0) /*!< BR interrupt enable */ -#define CEC_INTEN_RENDIE BIT(1) /*!< REND interrupt enable */ -#define CEC_INTEN_ROIE BIT(2) /*!< RO interrupt enable */ -#define CEC_INTEN_BREIE BIT(3) /*!< BRE interrupt enable. */ -#define CEC_INTEN_BPSEIE BIT(4) /*!< BPSE interrupt enable */ -#define CEC_INTEN_BPLEIE BIT(5) /*!< BPLE interrupt enable. */ -#define CEC_INTEN_RAEIE BIT(6) /*!< RAE interrupt enable */ -#define CEC_INTEN_ARBFIE BIT(7) /*!< ARBF interrupt enable */ -#define CEC_INTEN_TBRIE BIT(8) /*!< TBR interrupt enable */ -#define CEC_INTEN_TENDIE BIT(9) /*!< TEND interrupt enable */ -#define CEC_INTEN_TUIE BIT(10) /*!< TU interrupt enable */ -#define CEC_INTEN_TERRIE BIT(11) /*!< TE interrupt enable */ -#define CEC_INTEN_TAERRIE BIT(12) /*!< TAE interrupt enable */ - -/* constants definitions */ -/* signal free time */ -#define CFG_SFT(regval) (BITS(0, 2) & ((regval) << 0U)) -#define CEC_SFT_PROTOCOL_PERIOD CFG_SFT(0) /*!< the signal free time will perform as HDMI-CEC protocol description */ -#define CEC_SFT_1POINT5_PERIOD CFG_SFT(1) /*!< 1.5 nominal data bit periods */ -#define CEC_SFT_2POINT5_PERIOD CFG_SFT(2) /*!< 2.5 nominal data bit periods */ -#define CEC_SFT_3POINT5_PERIOD CFG_SFT(3) /*!< 3.5 nominal data bit periods */ -#define CEC_SFT_4POINT5_PERIOD CFG_SFT(4) /*!< 4.5 nominal data bit periods */ -#define CEC_SFT_5POINT5_PERIOD CFG_SFT(5) /*!< 5.5 nominal data bit periods */ -#define CEC_SFT_6POINT5_PERIOD CFG_SFT(6) /*!< 6.5 nominal data bit periods */ -#define CEC_SFT_7POINT5_PERIOD CFG_SFT(7) /*!< 7.5 nominal data bit periods */ - -/* signal free time start option */ -#define CEC_SFT_START_STAOM ((uint32_t)0x00000000U) /*!< signal free time counter starts counting when STAOM is asserted */ -#define CEC_SFT_START_LAST CEC_CFG_SFTOPT /*!< signal free time counter starts automatically after transmission/reception end */ - -/* own address */ -#define CEC_OWN_ADDRESS_CLEAR ((uint32_t)0x00000000U) /*!< own address is cleared */ -#define CEC_OWN_ADDRESS0 BIT(16) /*!< own address is 0 */ -#define CEC_OWN_ADDRESS1 BIT(17) /*!< own address is 1 */ -#define CEC_OWN_ADDRESS2 BIT(18) /*!< own address is 2 */ -#define CEC_OWN_ADDRESS3 BIT(19) /*!< own address is 3 */ -#define CEC_OWN_ADDRESS4 BIT(20) /*!< own address is 4 */ -#define CEC_OWN_ADDRESS5 BIT(21) /*!< own address is 5 */ -#define CEC_OWN_ADDRESS6 BIT(22) /*!< own address is 6 */ -#define CEC_OWN_ADDRESS7 BIT(23) /*!< own address is 7 */ -#define CEC_OWN_ADDRESS8 BIT(24) /*!< own address is 8 */ -#define CEC_OWN_ADDRESS9 BIT(25) /*!< own address is 9 */ -#define CEC_OWN_ADDRESS10 BIT(26) /*!< own address is 10 */ -#define CEC_OWN_ADDRESS11 BIT(27) /*!< own address is 11 */ -#define CEC_OWN_ADDRESS12 BIT(28) /*!< own address is 12 */ -#define CEC_OWN_ADDRESS13 BIT(29) /*!< own address is 13 */ -#define CEC_OWN_ADDRESS14 BIT(30) /*!< own address is 14 */ - -/* error-bit generate */ -#define CEC_BROADCAST_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< generate Error-bit in broadcast */ -#define CEC_BROADCAST_ERROR_BIT_OFF CEC_CFG_BCNG /*!< do not generate Error-bit in broadcast */ -#define CEC_LONG_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on long bit period error */ -#define CEC_LONG_PERIOD_ERROR_BIT_ON CEC_CFG_BPLEG /*!< do not generate Error-bit on long bit period error */ -#define CEC_RISING_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on bit rising error */ -#define CEC_RISING_PERIOD_ERROR_BIT_ON CEC_CFG_BREG /*!< do not generate Error-bit on bit rising error */ - -/* whether stop receive message when detected bit rising error */ -#define CEC_STOP_RISING_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< stop reception when detected bit rising error */ -#define CEC_STOP_RISING_ERROR_BIT_OFF ((uint32_t)0x00000001U) /*!< do not stop reception when detected bit rising error */ - -/* flag bits */ -#define CEC_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */ -#define CEC_FLAG_REND CEC_INTF_REND /*!< end of reception */ -#define CEC_FLAG_RO CEC_INTF_RO /*!< RX overrun */ -#define CEC_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */ -#define CEC_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */ -#define CEC_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */ -#define CEC_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */ -#define CEC_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */ -#define CEC_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */ -#define CEC_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */ -#define CEC_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */ -#define CEC_FLAG_TERR CEC_INTF_TERR /*!< TX-error */ -#define CEC_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */ - -/* interrupt flag bits */ -#define CEC_INT_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */ -#define CEC_INT_FLAG_REND CEC_INTF_REND /*!< end of reception */ -#define CEC_INT_FLAG_RO CEC_INTF_RO /*!< RX overrun */ -#define CEC_INT_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */ -#define CEC_INT_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */ -#define CEC_INT_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */ -#define CEC_INT_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */ -#define CEC_INT_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */ -#define CEC_INT_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */ -#define CEC_INT_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */ -#define CEC_INT_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */ -#define CEC_INT_FLAG_TERR CEC_INTF_TERR /*!< TX-error */ -#define CEC_INT_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */ - -/* interrupt enable bits */ -#define CEC_INT_BR CEC_INTEN_BRIE /*!< RBR interrupt enable */ -#define CEC_INT_REND CEC_INTEN_RENDIE /*!< REND interrupt enable */ -#define CEC_INT_RO CEC_INTEN_ROIE /*!< RO interrupt enable */ -#define CEC_INT_BRE CEC_INTEN_BREIE /*!< RBRE interrupt enable. */ -#define CEC_INT_BPSE CEC_INTEN_BPSEIE /*!< RSBPE interrupt enable */ -#define CEC_INT_BPLE CEC_INTEN_BPLEIE /*!< RLBPE interrupt enable. */ -#define CEC_INT_RAE CEC_INTEN_RAEIE /*!< RAE interrupt enable */ -#define CEC_INT_ARBF CEC_INTEN_ARBFIE /*!< ALRLST interrupt enable */ -#define CEC_INT_TBR CEC_INTEN_TBRIE /*!< TBR interrupt enable */ -#define CEC_INT_TEND CEC_INTEN_TENDIE /*!< TEND interrupt enable */ -#define CEC_INT_TU CEC_INTEN_TUIE /*!< TU interrupt enable */ -#define CEC_INT_TERR CEC_INTEN_TERRIE /*!< TE interrupt enable */ -#define CEC_INT_TAERR CEC_INTEN_TAERRIE /*!< TAE interrupt enable */ - -/* function declarations */ -/* reset HDMI-CEC controller */ -void cec_deinit(void); -/* configure signal free time,the signal free time counter start option,own address */ -void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address); -/* configure generate Error-bit, whether stop receive message when detected bit rising error */ -void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp); -/* enable HDMI-CEC controller */ -void cec_enable(void); -/* disable HDMI-CEC controller */ -void cec_disable(void); - -/* start CEC message transmission */ -void cec_transmission_start(void); -/* end CEC message transmission */ -void cec_transmission_end(void); -/* enable CEC listen mode */ -void cec_listen_mode_enable(void); -/* disable CEC listen mode */ -void cec_listen_mode_disable(void); -/* configure and clear own address */ -void cec_own_address_config(uint32_t address); -/* configure signal free time and the signal free time counter start option */ -void cec_sft_config(uint32_t sftmopt,uint32_t sft); -/* configure generate Error-bit when detected some abnormal situation or not */ -void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre); -/* whether stop receive message when detected bit rising error */ -void cec_stop_receive_bre_config(uint32_t rxbrestp); -/* enable reception bit timing tolerance */ -void cec_reception_tolerance_enable(void); -/* disable reception bit timing tolerance */ -void cec_reception_tolerance_disable(void); -/* send a data by the CEC peripheral */ -void cec_data_send(uint8_t data); -/* receive a data by the CEC peripheral */ -uint8_t cec_data_receive(void); - -/* enable interrupt */ -void cec_interrupt_enable(uint32_t flag); -/* disable interrupt */ -void cec_interrupt_disable(uint32_t flag); -/* get CEC status */ -FlagStatus cec_flag_get(uint32_t flag); -/* clear CEC status */ -void cec_flag_clear(uint32_t flag); -/* get CEC int flag and status */ -FlagStatus cec_interrupt_flag_get(uint32_t flag); -/* clear CEC int flag and status */ -void cec_interrupt_flag_clear(uint32_t flag); - -#endif /* GD32F3X0_CEC_H */ - -#endif /* GD32F350 */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h deleted file mode 100644 index 19f64e03e7..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_cmp.h +++ /dev/null @@ -1,219 +0,0 @@ -/*! - \file gd32f3x0_cmp.h - \brief definitions for the CMP - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_CMP_H -#define GD32F3X0_CMP_H - -#include "gd32f3x0.h" - -/* CMP definitions */ -#define CMP CMP_BASE /*!< CMP base address */ - -/* registers definitions */ -#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */ - -/* CMP_CS bits definitions */ -#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */ -#define CMP_CS_CMP0SW BIT(1) /*!< CMP0 switch */ -#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */ -#define CMP_CS_CMP0MSEL BITS(4,6) /*!< COMP0_M input selection */ -#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */ -#define CMP_CS_CMP0PL BIT(11) /*!< polarity of CMP0 output */ -#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */ -#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output */ -#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */ -#define CMP_CS_CMP1EN BIT(16) /*!< CMP1 enable */ -#define CMP_CS_CMP1M BITS(18,19) /*!< CMP1 mode */ -#define CMP_CS_CMP1MSEL BITS(20,22) /*!< CMP1_M input selection */ -#define CMP_CS_WNDEN BIT(23) /*!< window mode enable */ -#define CMP_CS_CMP1OSEL BITS(24,26) /*!< CMP1 output selection */ -#define CMP_CS_CMP1PL BIT(27) /*!< polarity of CMP1 output */ -#define CMP_CS_CMP1HST BITS(28,29) /*!< CMP1 hysteresis */ -#define CMP_CS_CMP1O BIT(30) /*!< CMP1 output */ -#define CMP_CS_CMP1LK BIT(31) /*!< CMP1 lock */ - -/* consts definitions */ -/* operating mode */ -typedef enum{ - CMP_HIGHSPEED = 0, /*!< high speed mode */ - CMP_MIDDLESPEED, /*!< medium speed mode */ - CMP_LOWSPEED, /*!< low speed mode */ - CMP_VERYLOWSPEED /*!< very-low speed mode */ -}operating_mode_enum; - -/* inverting input */ -typedef enum{ - CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ - CMP_1_2VREFINT, /*!< VREFINT /2 input */ - CMP_3_4VREFINT, /*!< VREFINT *3/4 input */ - CMP_VREFINT, /*!< VREFINT input */ - CMP_DAC, /*!< PA4 (DAC) input */ - CMP_PA5, /*!< PA5 input */ - CMP_PA_0_2 /*!< PA0 or PA2 input */ -}inverting_input_enum; - -/* hysteresis */ -typedef enum{ - CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ - CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ - CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ - CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ -}cmp_hysteresis_enum; - -/* output */ -typedef enum{ - CMP_OUTPUT_NONE = 0, /*!< output no selection */ - CMP_OUTPUT_TIMER0BKIN, /*!< TIMER 0 break input */ - CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */ - CMP_OUTPUT_TIMER0OCPRECLR, /*!< TIMER 0 OCPRE_CLR input */ - CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */ - CMP_OUTPUT_TIMER1OCPRECLR, /*!< TIMER 1 OCPRE_CLR input */ - CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */ - CMP_OUTPUT_TIMER2OCPRECLR /*!< TIMER 2 OCPRE_CLR input */ -}cmp_output_enum; - -/* CMP0 mode */ -#define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define CS_CMP0M_HIGHSPEED CS_CMP0M(0) /*!< CMP0 mode high speed */ -#define CS_CMP0M_MIDDLESPEED CS_CMP0M(1) /*!< CMP0 mode middle speed */ -#define CS_CMP0M_LOWSPEED CS_CMP0M(2) /*!< CMP0 mode low speed */ -#define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3) /*!< CMP0 mode very low speed */ - -/* comparator 0 inverting input */ -#define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */ -#define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */ -#define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */ -#define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */ -#define CS_CMP0MSEL_DAC CS_CMP0MSEL(4) /*!< CMP0 inverting input DAC*/ -#define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/ -#define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/ - -/* CMP0 output */ -#define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0) /*!< CMP0 output none */ -#define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1) /*!< CMP0 output TIMER 0 break input */ -#define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2) /*!< CMP0 output TIMER 0 channel 0 input capture */ -#define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3) /*!< CMP0 output TIMER 0 ocpreclear input */ -#define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4) /*!< CMP0 output TIMER 1 channel 3 input capture */ -#define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5) /*!< CMP0 output TIMER 1 ocpreclear input */ -#define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6) /*!< CMP0 output TIMER 2 channle 0 input capture */ -#define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7) /*!< CMP0 output TIMER 2 ocpreclear input */ - -/* CMP0 hysteresis */ -#define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */ -#define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */ -#define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2) /*!< CMP0 output middle hysteresis */ -#define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */ - -/* CMP1 mode */ -#define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18)) -#define CS_CMP1M_HIGHSPEED CS_CMP1M(0) /*!< CMP1 mode high speed */ -#define CS_CMP1M_MIDDLESPEED CS_CMP1M(1) /*!< CMP1 mode middle speed */ -#define CS_CMP1M_LOWSPEED CS_CMP1M(2) /*!< CMP1 mode low speed */ -#define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3) /*!< CMP1 mode very low speed */ - -/* CMP1 inverting input */ -#define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) -#define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */ -#define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */ -#define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */ -#define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */ -#define CS_CMP1MSEL_DAC CS_CMP1MSEL(4) /*!< CMP1 inverting input DAC */ -#define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5 */ -#define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2 */ - -/* CMP1 output */ -#define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0) /*!< CMP1 output none */ -#define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1) /*!< CMP1 output TIMER 0 break input */ -#define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2) /*!< CMP1 output TIMER 0 channel 0 input capture */ -#define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3) /*!< CMP1 output TIMER 0 ocpreclear input */ -#define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4) /*!< CMP1 output TIMER 1 channel 3 input capture */ -#define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5) /*!< CMP1 output TIMER 1 ocpreclear input */ -#define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6) /*!< CMP1 output TIMER 2 channle 0 input capture */ -#define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7) /*!< CMP1 output TIMER 2 ocpreclear input */ - -/* CMP1 hysteresis */ -#define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */ -#define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */ -#define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2) /*!< CMP1 output middle hysteresis */ -#define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */ - -/* comparator x definitions */ -#define CMP0 ((uint32_t)0x00000000) /*!< comparator 0 */ -#define CMP1 ((uint32_t)0x00000010) /*!< comparator 1 */ - -/* comparator output level */ -#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */ -#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */ - -/* output polarity of comparator */ -#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */ -#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */ - -/* function declarations */ - -/* initialization functions */ -/* CMP deinit */ -void cmp_deinit(void); -/* CMP mode init */ -void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis); -/* CMP output init */ -void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity); - -/* enable functions */ -/* enable CMP */ -void cmp_enable(uint32_t cmp_periph); -/* disable CMP */ -void cmp_disable(uint32_t cmp_periph); -/* enable CMP switch */ -void cmp_switch_enable(void); -/* disable CMP switch */ -void cmp_switch_disable(void); -/* enable the window mode */ -void cmp_window_enable(void); -/* disable the window mode */ -void cmp_window_disable(void); -/* lock the CMP */ -void cmp_lock_enable(uint32_t cmp_periph); - -/* output functions */ -/* get output level */ -uint32_t cmp_output_level_get(uint32_t cmp_periph); - -#endif /* GD32F3X0_CMP_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h deleted file mode 100644 index 398af82238..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_crc.h +++ /dev/null @@ -1,119 +0,0 @@ -/*! - \file gd32f3x0_crc.h - \brief definitions for the CRC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_CRC_H -#define GD32F3X0_CRC_H - -#include "gd32f3x0.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */ -#define CRC_IDATA REG32(CRC + 0x00000010U) /*!< CRC initialization data register */ -#define CRC_POLY REG32(CRC + 0x00000014U) /*!< CRC polynomial register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ -#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */ -#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */ -#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */ - -/* CRC_INIT */ -#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */ - -/* CRC_POLY */ -#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */ - -/* constants definitions */ -/* size of polynomial function */ -#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3)) -#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */ - -/* input data reverse function */ -#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5)) -#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */ -#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */ -#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */ -#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */ - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* enable the reverse operation of output data */ -void crc_reverse_output_data_enable(void); -/* disable the reverse operation of output data */ -void crc_reverse_output_data_disable(void); - -/* reset data register to the value of initializaiton data register */ -void crc_data_register_reset(void); -/* read the data register */ -uint32_t crc_data_register_read(void); - -/* read the free data register */ -uint8_t crc_free_data_register_read(void); -/* write the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* write the initial value register */ -void crc_init_data_register_write(uint32_t init_data); -/* configure the CRC input data function */ -void crc_input_data_reverse_config(uint32_t data_reverse); - -/* configure the CRC size of polynomial function */ -void crc_polynomial_size_set(uint32_t poly_size); -/* configure the CRC polynomial value function */ -void crc_polynomial_set(uint32_t poly); - -/* CRC calculate a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* CRC calculate a 32-bit data array */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32F3X0_CRC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h deleted file mode 100644 index 2c8ff14e08..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_ctc.h +++ /dev/null @@ -1,191 +0,0 @@ -/*! - \file gd32f3x0_ctc.h - \brief definitions for the CTC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_CTC_H -#define GD32F3X0_CTC_H - -#include "gd32f3x0.h" - -/* CTC definitions */ -#define CTC CTC_BASE - -/* registers definitions */ -#define CTC_CTL0 REG32(CTC + 0x00000000U) /*!< CTC control register 0 */ -#define CTC_CTL1 REG32(CTC + 0x00000004U) /*!< CTC control register 1 */ -#define CTC_STAT REG32(CTC + 0x00000008U) /*!< CTC status register */ -#define CTC_INTC REG32(CTC + 0x0000000CU) /*!< CTC interrupt clear register */ - -/* bits definitions */ -/* CTC_CTL0 */ -#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ -#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ -#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ -#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ -#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ -#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ -#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ -#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ - -/* CTC_CTL1 */ -#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ -#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ -#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ -#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ - -/* CTC_STAT */ -#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ -#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ -#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ -#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ -#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ -#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ -#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ -#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ -#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ - -/* CTC_INTC */ -#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ -#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ -#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ -#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ - -/* constants definitions */ -#define CTL0_TRIMVALUE(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) -#define CTL1_CKLIM(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) -#define GET_STAT_REFCAP(regval) GET_BITS((regval),16,31) -#define GET_CTL0_TRIMVALUE(regval) GET_BITS((regval),8,13) - -/* hardware automatically trim mode definitions */ -#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ -#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ - -/* reference signal source polarity definitions */ -#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ -#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ - -/* reference signal source selection definitions */ -#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ -#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ -#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFSSOF selected */ - -/* reference signal source prescaler definitions */ -#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ -#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ -#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ -#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ -#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ -#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ -#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ -#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ - -/* CTC interrupt enable definitions */ -#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ -#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ -#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ -#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ - -/* CTC interrupt source definitions */ -#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ -#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ -#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ -#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ -#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ - -/* CTC flag definitions */ -#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ -#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ -#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ -#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ -#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ - -/* function declarations */ -/* initialization functions */ -/* reset ctc clock trim controller */ -void ctc_deinit(void); -/* configure reference signal source polarity */ -void ctc_refsource_polarity_config(uint32_t polarity); -/* select reference signal source */ -void ctc_refsource_signal_select(uint32_t refs); -/* configure reference signal source prescaler */ -void ctc_refsource_prescaler_config(uint32_t prescaler); -/* configure clock trim base limit value */ -void ctc_clock_limit_value_config(uint8_t limit_value); -/* configure CTC counter reload value */ -void ctc_counter_reload_value_config(uint16_t reload_value); -/* enable CTC trim counter */ -void ctc_counter_enable(void); -/* disable CTC trim counter */ -void ctc_counter_disable(void); - -/* function configuration */ -/* configure the IRC48M trim value */ -void ctc_irc48m_trim_value_config(uint8_t trim_value); -/* generate software reference source sync pulse */ -void ctc_software_refsource_pulse_generate(void); -/* configure hardware automatically trim mode */ -void ctc_hardware_trim_mode_config(uint32_t hardmode); - -/* reading functions */ -/* read CTC counter capture value when reference sync pulse occurred */ -uint16_t ctc_counter_capture_value_read(void); -/* read CTC trim counter direction when reference sync pulse occurred */ -FlagStatus ctc_counter_direction_read(void); -/* read CTC counter reload value */ -uint16_t ctc_counter_reload_value_read(void); -/* read the IRC48M trim value */ -uint8_t ctc_irc48m_trim_value_read(void); - -/* interrupt & flag functions */ -/* enable the CTC interrupt */ -void ctc_interrupt_enable(uint32_t interrupt); -/* disable the CTC interrupt */ -void ctc_interrupt_disable(uint32_t interrupt); -/* get CTC flag */ -FlagStatus ctc_flag_get(uint32_t flag); -/* clear CTC flag */ -void ctc_flag_clear(uint32_t flag); -/* get CTC interrupt flag */ -FlagStatus ctc_interrupt_flag_get(uint32_t interrupt); -/* clear CTC interrupt flag */ -void ctc_interrupt_flag_clear(uint32_t interrupt); - -#endif /* GD32F3X0_CTC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h deleted file mode 100644 index 5975f7724c..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dac.h +++ /dev/null @@ -1,204 +0,0 @@ -/*! - \file gd32f3x0_dac.h - \brief definitions for the DAC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifdef GD32F350 -#ifndef GD32F3X0_DAC_H -#define GD32F3X0_DAC_H - -#include "gd32f3x0.h" - -/* DAC definitions */ -#define DAC DAC_BASE - -/* registers definitions */ -#define DAC_CTL REG32(DAC + (0x00000000U)) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + (0x00000004U)) /*!< DAC software trigger register */ -#define DAC_R12DH REG32(DAC + (0x00000008U)) /*!< DAC 12-bit right-aligned data holding register */ -#define DAC_L12DH REG32(DAC + (0x0000000CU)) /*!< DAC 12-bit left-aligned data holding register */ -#define DAC_R8DH REG32(DAC + (0x00000010U)) /*!< DAC 8-bit right-aligned data holding register */ -#define DAC_DO REG32(DAC + (0x0000002CU)) /*!< DAC output data register */ -#define DAC_STAT REG32(DAC + (0x00000034U)) /*!< DAC status register */ - -/* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN BIT(0) /*!< DAC enable/disable bit */ -#define DAC_CTL_DBOFF BIT(1) /*!< DAC output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN BIT(2) /*!< DAC trigger enable/disable bit */ -#define DAC_CTL_DTSEL BITS(3,5) /*!< DAC trigger source selection enable/disable bits */ -#define DAC_CTL_DWM BITS(6,7) /*!< DAC noise wave mode */ -#define DAC_CTL_DWBW BITS(8,11) /*!< DAC noise wave bit width */ -#define DAC_CTL_DDMAEN BIT(12) /*!< DAC DMA enable/disable bit */ -#define DAC_CTL_DDUDRIE BIT(13) /*!< DAC DMA underrun interrupt enable/disable bit */ - -/* DAC_SWT */ -#define DAC_SWT_SWTR BIT(0) /*!< DAC software trigger bit,cleared by hardware */ - -/* DAC_R12DH */ -#define DAC_R12DH_DAC_DH BITS(0,11) /*!< DAC 12-bit right-aligned data bits */ - -/* DAC_L12DH */ -#define DAC_L12DH_DAC_DH BITS(4,15) /*!< DAC 12-bit left-aligned data bits */ - -/* DAC_R8DH */ -#define DAC_R8DH_DAC_DH BITS(0,7) /*!< DAC 8-bit right-aligned data bits */ - -/* DAC_DO */ -#define DAC_DO_DAC_DO BITS(0,11) /*!< DAC 12-bit output data bits */ - -/* DAC_STAT */ -#define DAC_STAT_DDUDR BIT(13) /*!< DAC DMA underrun flag */ - -/* constants definitions */ -/* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ -#define DAC_TRIGGER_T14_TRGO CTL_DTSEL(3) /*!< TIMER14 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - -/* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - -/* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ - -/* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ - -/* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ - -/* function declarations */ -/* deinitialize DAC */ -void dac_deinit(void); - -/* enable DAC */ -void dac_enable(void); -/* disable DAC */ -void dac_disable(void); -/* enable DAC DMA */ -void dac_dma_enable(void); -/* disable DAC DMA */ -void dac_dma_disable(void); -/* enable DAC output buffer */ -void dac_output_buffer_enable(void); -/* disable DAC output buffer */ -void dac_output_buffer_disable(void); -/* enable DAC trigger */ -void dac_trigger_enable(void); -/* disable DAC trigger */ -void dac_trigger_disable(void); -/* enable DAC software trigger */ -void dac_software_trigger_enable(void); -/* disable DAC software trigger */ -void dac_software_trigger_disable(void); -/* enable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_enable(void); -/* disable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_disable(void); - -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t triggersource); -/* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t bit_width); -/* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t unmask_bits); -/* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t amplitude); -/* get the last data output value */ -uint16_t dac_output_value_get(void); - -/* get the specified DAC flag(DAC DMA underrun flag) */ -FlagStatus dac_flag_get(void); -/* clear the specified DAC flag(DAC DMA underrun flag) */ -void dac_flag_clear(void); -/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ -FlagStatus dac_interrupt_flag_get(void); -/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ -void dac_interrupt_flag_clear(void); - -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_align, uint16_t data); - -#endif /* GD32F3X0_DAC_H */ - -#endif /* GD32F350 */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h deleted file mode 100644 index 9492753345..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dbg.h +++ /dev/null @@ -1,128 +0,0 @@ -/*! - \file gd32f3x0_dbg.h - \brief definitions for the DBG - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_DBG_H -#define GD32F3X0_DBG_H - -#include "gd32f3x0.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */ -#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */ -#define DBG_CTL1 REG32(DBG + 0x00000008U) /*!< DBG control register 1 */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL0 */ -#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ -#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ -#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ -#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#ifdef GD32F350 -#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ -#endif /* GD32F350 */ -#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ - -/* DBG_CTL1 */ -#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ -#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */ -#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */ -#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */ - -/* constants definitions */ -#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* define the peripheral debug hold bit position and its register index offset */ -#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) -#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) -#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) - -/* register index */ -typedef enum -{ - DBG_IDX_CTL0 = 0x04U, /*!< DBG control register 0 offset */ - DBG_IDX_CTL1 = 0x08U, /*!< DBG control register 1 offset */ -}dbg_reg_idx; - -/* peripherals hold bit */ -typedef enum -{ - DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< debug FWDGT kept when core is halted */ - DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< debug WWDGT kept when core is halted */ - DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< hold TIMER2 counter when core is halted */ -#ifdef GD32F350 - DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< hold TIMER5 counter when core is halted */ -#endif /* GD32F350 */ - DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< hold TIMER13 counter when core is halted */ - DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< hold TIMER14 counter when core is halted */ - DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< hold TIMER15 counter when core is halted */ - DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< hold TIMER16 counter when core is halted */ - DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< hold I2C1 smbus when core is halted */ - DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ -}dbg_periph_enum; - -/* function declarations */ -/* deinitialize the DBG */ -void dbg_deinit(void); -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -#endif /* GD32F3X0_DBG_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h deleted file mode 100644 index 9c24dca1dd..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_dma.h +++ /dev/null @@ -1,273 +0,0 @@ -/*! - \file gd32f3x0_dma.h - \brief definitions for the DMA - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_DMA_H -#define GD32F3X0_DMA_H - -#include "gd32f3x0.h" - -/* DMA definitions */ -#define DMA DMA_BASE /*!< DMA base address */ - -/* registers definitions */ -#define DMA_INTF REG32(DMA + 0x00000000U) /*!< DMA interrupt flag register */ -#define DMA_INTC REG32(DMA + 0x00000004U) /*!< DMA interrupt flag clear register */ -#define DMA_CH0CTL REG32(DMA + 0x00000008U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT REG32(DMA + 0x0000000CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR REG32(DMA + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR REG32(DMA + 0x00000014U) /*!< DMA channel 0 memory base address register */ -#define DMA_CH1CTL REG32(DMA + 0x0000001CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT REG32(DMA + 0x00000020U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR REG32(DMA + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR REG32(DMA + 0x00000028U) /*!< DMA channel 1 memory base address register */ -#define DMA_CH2CTL REG32(DMA + 0x00000030U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT REG32(DMA + 0x00000034U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR REG32(DMA + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR REG32(DMA + 0x0000003CU) /*!< DMA channel 2 memory base address register */ -#define DMA_CH3CTL REG32(DMA + 0x00000044U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT REG32(DMA + 0x00000048U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR REG32(DMA + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR REG32(DMA + 0x00000050U) /*!< DMA channel 3 memory base address register */ -#define DMA_CH4CTL REG32(DMA + 0x00000058U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT REG32(DMA + 0x0000005CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR REG32(DMA + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR REG32(DMA + 0x00000064U) /*!< DMA channel 4 memory base address register */ -#define DMA_CH5CTL REG32(DMA + 0x0000006CU) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT REG32(DMA + 0x00000070U) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR REG32(DMA + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5MADDR REG32(DMA + 0x00000078U) /*!< DMA channel 5 memory base address register */ -#define DMA_CH6CTL REG32(DMA + 0x00000080U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT REG32(DMA + 0x00000084U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR REG32(DMA + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6MADDR REG32(DMA + 0x0000008CU) /*!< DMA channel 6 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL,x=0..6 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT,x=0..6 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR,x=0..6 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR,x=0..6 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA Channel0 */ - DMA_CH1, /*!< DMA Channel1 */ - DMA_CH2, /*!< DMA Channel2 */ - DMA_CH3, /*!< DMA Channel3 */ - DMA_CH4, /*!< DMA Channel4 */ - DMA_CH5, /*!< DMA Channel5 */ - DMA_CH6 /*!< DMA Channel6 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ -} dma_parameter_struct; - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) - -#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_CHCTL base address */ -#define DMA_CHXCTL_BASE (DMA + (uint32_t)0x00000008U) /*!< the base address of DMA channel CHXCTL register */ -#define DMA_CHXCNT_BASE (DMA + (uint32_t)0x0000000CU) /*!< the base address of DMA channel CHXCNT register */ -#define DMA_CHXPADDR_BASE (DMA + (uint32_t)0x00000010U) /*!< the base address of DMA channel CHXPADDR register */ -#define DMA_CHXMADDR_BASE (DMA + (uint32_t)0x00000014U) /*!< the base address of DMA channel CHXMADDR register */ - -/* DMA channel shift bit */ -#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT - -/* function declarations */ -/* deinitialize DMA a channel registers */ -void dma_deinit(dma_channel_enum channelx); -/* initialize the parameters of DMA struct with the default values */ -void dma_struct_para_init(dma_parameter_struct* init_struct); -/* initialize DMA channel */ -void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct); -/* enable DMA circulation mode */ -void dma_circulation_enable(dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(dma_channel_enum channelx); - -/* set DMA peripheral base address */ -void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); -/* set DMA memory base address */ -void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction); - -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); - -#endif /* GD32F3X0_DMA_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h deleted file mode 100644 index 3e17ff3c57..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_exti.h +++ /dev/null @@ -1,285 +0,0 @@ -/*! - \file gd32f3x0_exti.h - \brief definitions for the EXTI - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_EXTI_H -#define GD32F3X0_EXTI_H - -#include "gd32f3x0.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00000000U)/*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x00000004U)/*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x00000008U)/*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0000000CU)/*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x00000010U)/*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x00000014U)/*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ -#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ -#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ -#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ -#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ -#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */ -#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */ -#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */ -#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */ -#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ -#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ -#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ -#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ -#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ -#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */ -#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */ -#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */ -#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */ -#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ -#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ -#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ -#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ -#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ -#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ -#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ -#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ -#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ -#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ -#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ -#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum -{ - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ - EXTI_20 = BIT(20), /*!< EXTI line 20 */ - EXTI_21 = BIT(21), /*!< EXTI line 21 */ - EXTI_22 = BIT(22), /*!< EXTI line 22 */ - EXTI_23 = BIT(23), /*!< EXTI line 23 */ - EXTI_24 = BIT(24), /*!< EXTI line 24 */ - EXTI_25 = BIT(25), /*!< EXTI line 25 */ - EXTI_26 = BIT(26), /*!< EXTI line 26 */ - EXTI_27 = BIT(27), /*!< EXTI line 27 */ -}exti_line_enum; - -/* external interrupt and event */ -typedef enum -{ - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum -{ - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ -}exti_trig_type_enum; - -/* function declarations */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* initialize the EXTI, enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - -/* enable EXTI software interrupt event */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable EXTI software interrupt event */ -void exti_software_interrupt_disable(exti_line_enum linex); -/* get EXTI line x pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI line x pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI line x flag when the interrupt flag is set */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI line x pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); - -#endif /* GD32F3X0_EXTI_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h deleted file mode 100644 index 9e49e73dc9..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fmc.h +++ /dev/null @@ -1,258 +0,0 @@ -/*! - \file gd32f3x0_fmc.h - \brief definitions for the FMC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F3X0_FMC_H -#define GD32F3X0_FMC_H - -#include "gd32f3x0.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option byte base address */ - -/* registers definitions */ -#define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait state register */ -#define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status register */ -#define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC control register */ -#define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC address register */ -#define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC write protection register */ -#define FMC_WSEN REG32(FMC + 0x000000FCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32(FMC + 0x00000100U) /*!< FMC product ID register */ - -#define OB_SPC REG16(OB + 0x00000000U) /*!< option byte security protection value */ -#define OB_USER REG16(OB + 0x00000002U) /*!< option byte user value*/ -#define OB_DATA0 REG16(OB + 0x00000004U) /*!< option byte data bit[7:0] value*/ -#define OB_DATA1 REG16(OB + 0x00000006U) /*!< option byte data bit[15:8] value*/ -#define OB_WP0 REG16(OB + 0x00000008U) /*!< option byte write protection 0 */ -#define OB_WP1 REG16(OB + 0x0000000AU) /*!< option byte write protection 1 */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ - -/* FMC_KEY */ -#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT */ -#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */ -#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL */ -#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ -#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */ -#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */ -#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL_LK BIT(7) /*!< flash lock bit */ -#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ -#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */ - -/* FMC_ADDR */ -#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */ -#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */ -#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */ -#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */ -#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */ - -/* FMC_WSEN */ -#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ -#define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ - FMC_OB_HSPC /*!< option byte security protection code high */ -}fmc_state_enum; - -/* option byte parameter */ -typedef struct -{ - uint8_t spc; /*!< option byte parameter spc */ - uint8_t user; /*!< option byte parameter user */ - uint8_t data0; /*!< option byte parameter data0 */ - uint8_t data1; /*!< option byte parameter data1 */ - uint8_t wp0; /*!< option byte parameter wp0 */ - uint8_t wp1; /*!< option byte parameter wp1 */ -}ob_parm_struct; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* wait state counter value */ -#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */ -#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */ -#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */ - -/* read protect configure */ -#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ -#define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection, any value except 0xA5 or 0xCC */ -#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */ - -/* option byte write protection */ -#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ -#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ - -#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */ -#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */ -#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */ -#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */ -#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */ -#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */ - -/* option byte security protection level in FMC_OBSTAT register */ -#define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U) /*!< no security protection */ -#define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U) /*!< low security protection */ -#define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U) /*!< high security protection */ - -#define OB_USER_DEFAULT ((uint8_t)0xDFU) /*!< OB_USER default value */ - -/* option byte parameter address */ -#define OB_SPC_ADDR (uint32_t)(OB + 0x00000000U)/*!< option byte spc address */ -#define OB_USER_ADDR (uint32_t)(OB + 0x00000002U)/*!< option byte user address */ -#define OB_DATA_ADDR0 (uint32_t)(OB + 0x00000004U)/*!< option byte data address 0 */ -#define OB_DATA_ADDR1 (uint32_t)(OB + 0x00000006U)/*!< option byte data address 1 */ -#define OB_WP_ADDR0 (uint32_t)(OB + 0x00000008U)/*!< option byte wp address 0 */ -#define OB_WP_ADDR1 (uint32_t)(OB + 0x0000000AU)/*!< option byte wp address 1 */ - -/* FMC flags */ -#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ -#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ -#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ -#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ - -/* FMC interrupt enable */ -#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */ -#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */ - -/* FMC time out */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* set the wait state counter value */ -void fmc_wscnt_set(uint8_t wscnt); -/* fmc wait state enable */ -void fmc_wait_state_enable(void); -/* fmc wait state disable */ -void fmc_wait_state_disable(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); -/* FMC program a word at the corresponding address without erasing */ -fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* reload the option byte and generate a system reset */ -void ob_reset(void); -/* erase option byte */ -fmc_state_enum ob_erase(void); -/* enable option byte write protection (OB_WP) */ -fmc_state_enum ob_write_protection_enable(uint16_t ob_wp); -/* configure read out protect */ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte user */ -fmc_state_enum ob_user_write(uint8_t ob_user); -/* write the FMC option byte data */ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data); -/* get the FMC option byte OB_USER */ -uint8_t ob_user_get(void); -/* get the FMC option byte OB_DATA */ -uint16_t ob_data_get(void); -/* get the FMC option byte write protection */ -uint16_t ob_write_protection_get(void); -/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */ -uint32_t ob_obstat_plevel_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* get flag set or reset */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC pending flag */ -void fmc_flag_clear(uint32_t flag); -/* get interrupt flag set or reset */ -FlagStatus fmc_interrupt_flag_get(uint32_t flag); -/* clear the FMC interrupt pending flag */ -void fmc_interrupt_flag_clear(uint32_t flag); -/* return the FMC state */ -fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(uint32_t timeout); -/* get current option byte value */ -void ob_parm_get(ob_parm_struct *ob_parm); -/* modify the target option byte depending on the original value */ -void ob_value_modify(uint32_t address, uint16_t value,ob_parm_struct *ob_parm); - -#endif /* GD32F3X0_FMC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h deleted file mode 100644 index 8b2d9db64f..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_fwdgt.h +++ /dev/null @@ -1,124 +0,0 @@ -/*! - \file gd32f3x0_fwdgt.h - \brief definitions for the FWDGT - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F3X0_FWDGT_H -#define GD32F3X0_FWDGT_H - -#include "gd32f3x0.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE - -/* registers definitions */ -#define FWDGT_CTL REG32(FWDGT + 0x00000000U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32(FWDGT + 0x00000004U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32(FWDGT + 0x00000008U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32(FWDGT + 0x0000000CU) /*!< FWDGT status register */ -#define FWDGT_WND REG32(FWDGT + 0x00000010U) /*!< FWDGT window register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ -#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ - -/* FWDGT_WND */ -#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ - -/* constants definitions */ -/* FWDGT_CTL register value */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_CTL_CMD bit field */ - -/* FWDGT_PSC register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* FWDGT_RLD register value */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */ - -/* FWDGT_WND register value */ -#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ -#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* configure the free watchdog timer counter window value */ -ErrStatus fwdgt_window_value_config(uint16_t window_value); -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32F3X0_FWDGT_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h deleted file mode 100644 index 045accbd02..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_gpio.h +++ /dev/null @@ -1,408 +0,0 @@ -/*! - \file gd32f3x0_gpio.h - \brief definitions for the GPIO - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_GPIO_H -#define GD32F3X0_GPIO_H - -#include "gd32f3x0.h" - -/* GPIOx(x=A,B,C,D,F) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOF (GPIO_BASE + 0x00001400U) - -/* registers definitions */ -#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register */ -#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port output mode register */ -#define GPIO_OSPD0(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port output speed register 0 */ -#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port pull-up/pull-down register */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port bit operation register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x0000001CU) /*!< GPIO port configuration lock register */ -#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x00000020U) /*!< GPIO alternate function selected register 0 */ -#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x00000024U) /*!< GPIO alternate function selected register 1 */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000028U) /*!< GPIO bit clear register */ -#define GPIO_TG(gpiox) REG32((gpiox) + 0x0000002CU) /*!< GPIO port bit toggle register */ -#define GPIO_OSPD1(gpiox) REG32((gpiox) + 0x0000003CU) /*!< GPIO port output speed register 1 */ - -/* bits definitions */ -/* GPIO_CTL */ -#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ -#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ -#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ -#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ -#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ -#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ -#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ -#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ -#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ -#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ -#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ -#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ -#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ -#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ -#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ -#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_OMODE */ -#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ -#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ -#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ -#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ -#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ -#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ -#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ -#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ -#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ -#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ -#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ -#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ -#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ -#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ -#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ -#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ - -/* GPIO_OSPD0 */ -#define GPIO_OSPD0_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ -#define GPIO_OSPD0_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ -#define GPIO_OSPD0_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ -#define GPIO_OSPD0_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ -#define GPIO_OSPD0_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ -#define GPIO_OSPD0_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ -#define GPIO_OSPD0_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ -#define GPIO_OSPD0_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ -#define GPIO_OSPD0_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ -#define GPIO_OSPD0_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ -#define GPIO_OSPD0_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ -#define GPIO_OSPD0_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ -#define GPIO_OSPD0_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ -#define GPIO_OSPD0_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ -#define GPIO_OSPD0_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ -#define GPIO_OSPD0_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ - -/* GPIO_PUD */ -#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ -#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ -#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ -#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ -#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ -#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ -#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ -#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ -#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ -#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ -#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ -#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ -#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ -#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ -#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ -#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* GPIO_AFSEL0 */ -#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ -#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ -#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ -#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ -#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ -#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ -#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ -#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ - -/* GPIO_AFSEL1 */ -#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ -#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ -#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ -#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ -#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ -#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ -#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ -#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_TG */ -#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ -#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ -#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ -#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ -#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ -#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ -#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ -#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ -#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ -#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ -#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ -#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ -#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ -#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ -#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ -#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ - -/* GPIO_OSPD1 */ -#define GPIO_OSPD1_SPD0 BIT(0) /*!< set pin 0 very high output speed when OSPD0 is "11" */ -#define GPIO_OSPD1_SPD1 BIT(1) /*!< set pin 1 very high output speed when OSPD1 is "11" */ -#define GPIO_OSPD1_SPD2 BIT(2) /*!< set pin 2 very high output speed when OSPD2 is "11" */ -#define GPIO_OSPD1_SPD3 BIT(3) /*!< set pin 3 very high output speed when OSPD3 is "11" */ -#define GPIO_OSPD1_SPD4 BIT(4) /*!< set pin 4 very high output speed when OSPD4 is "11" */ -#define GPIO_OSPD1_SPD5 BIT(5) /*!< set pin 5 very high output speed when OSPD5 is "11" */ -#define GPIO_OSPD1_SPD6 BIT(6) /*!< set pin 6 very high output speed when OSPD6 is "11" */ -#define GPIO_OSPD1_SPD7 BIT(7) /*!< set pin 7 very high output speed when OSPD7 is "11" */ -#define GPIO_OSPD1_SPD8 BIT(8) /*!< set pin 8 very high output speed when OSPD8 is "11" */ -#define GPIO_OSPD1_SPD9 BIT(9) /*!< set pin 9 very high output speed when OSPD9 is "11" */ -#define GPIO_OSPD1_SPD10 BIT(10) /*!< set pin 10 very high output speed when OSPD10 is "11" */ -#define GPIO_OSPD1_SPD11 BIT(11) /*!< set pin 11 very high output speed when OSPD11 is "11" */ -#define GPIO_OSPD1_SPD12 BIT(12) /*!< set pin 12 very high output speed when OSPD12 is "11" */ -#define GPIO_OSPD1_SPD13 BIT(13) /*!< set pin 13 very high output speed when OSPD13 is "11" */ -#define GPIO_OSPD1_SPD14 BIT(14) /*!< set pin 14 very high output speed when OSPD14 is "11" */ -#define GPIO_OSPD1_SPD15 BIT(15) /*!< set pin 15 very high output speed when OSPD15 is "11" */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* output mode definitions */ -#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ -#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ -#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ -#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ - -/* pull-up/pull-down definitions */ -#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ -#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ -#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* GPIO mode configuration values */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) -#define GPIO_MODE_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) - -/* GPIO pull-up/pull-down values */ -#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) -#define GPIO_PUPD_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) - -/* GPIO output speed values */ -#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) -#define GPIO_OSPEED_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n)))) - -/* GPIO output type */ -#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ -#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ - -/* GPIO output max speed value */ -#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */ -#define GPIO_OSPEED_MAX ((uint32_t)0x0000FFFFU) /*!< GPIO very high output speed, max speed more than 50MHz */ - -/* GPIO alternate function values */ -#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) -#define GPIO_AFR_MASK(n) ((uint32_t)((uint32_t)0x0000000FU << (4U * (n)))) - -/* GPIO alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ -#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ -#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ -#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ -#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */ -#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */ -#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */ -#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* set GPIO mode */ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); -/* set GPIO output type and speed */ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* set GPIO alternate function */ -void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin); -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -/* toggle GPIO pin status */ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); -/* toggle GPIO port status */ -void gpio_port_toggle(uint32_t gpio_periph); - -#endif /* GD32F3X0_GPIO_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h deleted file mode 100644 index d37cc1cf38..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_i2c.h +++ /dev/null @@ -1,347 +0,0 @@ -/*! - \file gd32f3x0_i2c.h - \brief definitions for the I2C - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F3X0_I2C_H -#define GD32F3X0_I2C_H - -#include "gd32f3x0.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE+0x00000400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ -#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast-mode-plus configure register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ - -/* I2Cx_FMPCFG */ -#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET (0x00000014U) /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET (0x00000018U) /*!< STAT1 register offset */ -/* I2C flags */ -typedef enum -{ - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ -}i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ -}i2c_interrupt_flag_enum; - -/* I2C interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ -}i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - -/* fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode or fast mode plus */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C position of ACK and PEC when receiving */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* enable dual-address mode */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); -/* disable dual-address mode */ -void i2c_dualaddr_disable(uint32_t i2c_periph); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); - -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* whether to enable I2C PEC calculation or not */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* whether ARP is enabled under SMBus */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -#endif /* GD32F3X0_I2C_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h deleted file mode 100644 index 08586feda5..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_misc.h +++ /dev/null @@ -1,92 +0,0 @@ -/*! - \file gd32f3x0_misc.h - \brief definitions for the MISC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_MISC_H -#define GD32F3X0_MISC_H - -#include "gd32f3x0.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */ - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */ - -/* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */ -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */ -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */ - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ -/* set the priority group */ -void nvic_priority_group_set(uint32_t nvic_prigroup); - -/* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); -/* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32F3X0_MISC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h deleted file mode 100644 index 230180bf9c..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_pmu.h +++ /dev/null @@ -1,197 +0,0 @@ -/*! - \file gd32f3x0_pmu.h - \brief definitions for the PMU - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_PMU_H -#define GD32F3X0_PMU_H - -#include "gd32f3x0.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32(PMU + 0x00000000U) /*!< PMU control register */ -#define PMU_CS REG32(PMU + 0x00000004U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ -#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ -#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ -#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ -#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN4 BIT(12) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */ -#define PMU_CS_LDOVSRF BIT(15) /*!< LDO voltage select ready flag */ -#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ -#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ -#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - -/* PMU LDO output voltage select definitions */ -#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ -#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ -#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ - -/* PMU low-driver mode enable in deep-sleep mode */ -#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ -#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ - -/* PMU high-driver mode switch */ -#define PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U) /*!< no high-driver mode switch */ -#define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS /*!< high-driver mode switch */ - -/* PMU low-driver mode when use normal power LDO */ -#define PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U) /*!< normal-driver when use normal power LDO */ -#define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ - -/* PMU low-driver mode when use low power LDO */ -#define PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U) /*!< normal-driver when use low power LDO */ -#define PMU_LOWDR_LOWPWR PMU_CTL_LDLP /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU low power mode ready flag definitions */ -#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal-driver in deep-sleep mode */ -#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */ -#define PMU_FLAG_LDOVSR PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ -#define PMU_FLAG_HDR PMU_CS_HDRF /*!< high-driver ready flag */ -#define PMU_FLAG_HDSR PMU_CS_HDSRF /*!< high-driver switch ready flag */ -#define PMU_FLAG_LDR PMU_CS_LDRF /*!< low-driver mode ready flag */ - -/* PMU WKUP pin definitions */ -#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ -#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ -#define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4 /*!< WKUP Pin 4 (PC5) enable */ -#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ -#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* function configuration */ -/* reset PMU registers */ -void pmu_deinit(void); -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* select LDO output voltage */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* functions of low-driver mode and high-driver mode in deep-sleep mode */ -/* enable low-driver mode in deep-sleep mode */ -void pmu_lowdriver_mode_enable(void); -/* disable low-driver mode in deep-sleep mode */ -void pmu_lowdriver_mode_disable(void); -/* enable high-driver mode */ -void pmu_highdriver_mode_enable(void); -/* disable high-driver mode */ -void pmu_highdriver_mode_disable(void); -/* switch high-driver mode */ -void pmu_highdriver_switch_select(uint32_t highdr_switch); -/* in deep-sleep mode, low-driver mode when use low power LDO */ -void pmu_lowpower_driver_config(uint32_t mode); -/* in deep-sleep mode, low-driver mode when use normal power LDO */ -void pmu_normalpower_driver_config(uint32_t mode); - -/* set PMU mode */ -/* PMU work in sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work in deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work in standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(uint32_t wakeup_pin); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(uint32_t wakeup_pin); - -/* backup related functions */ -/* enable backup domain write */ -void pmu_backup_write_enable(void); -/* disable backup domain write */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag_clear); -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); - -#endif /* GD32F3X0_PMU_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h deleted file mode 100644 index b870b69db1..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rcu.h +++ /dev/null @@ -1,797 +0,0 @@ -/*! - \file gd32f3x0_rcu.h - \brief definitions for the RCU - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_RCU_H -#define GD32F3X0_RCU_H - -#include "gd32f3x0.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */ -#define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */ -#define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ -#define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */ -#define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */ -#define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */ -#define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */ -#define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< additional clock control register */ -#define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< additional clock interrupt register */ -#define RCU_ADDAPB1EN REG32(RCU + 0x000000F8U) /*!< APB1 additional enable register */ -#define RCU_ADDAPB1RST REG32(RCU + 0x000000FCU) /*!< APB1 additional reset register */ -#define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ -#define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ - -/* bits definitions */ -/* RCU_CTL0 */ -#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ - -/* RCU_CFG0 */ -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */ -#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */ -#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ -#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ -#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ -#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ - -/* RCU_INT */ -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */ -#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */ -#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */ -#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 timer reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ -#define RCU_APB1RST_CECRST BIT(30) /*!< HDMI CEC reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_USBFS BIT(12) /*!< USBFS clock enable */ -#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ -#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ -#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ -#define RCU_AHBEN_PDEN BIT(20) /*!< GPIO port D clock enable */ -#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ -#define RCU_AHBEN_TSIEN BIT(24) /*!< TSI clock enable */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */ -#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */ -#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */ -#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 timer clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC interface clock enable */ -#define RCU_APB1EN_CECEN BIT(30) /*!< HDMI CEC interface clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */ -#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -/* RCU_AHBRST */ -#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ -#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ -#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ -#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ -#define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */ -#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ -#define RCU_AHBRST_TSIRST BIT(24) /*!< TSI unit reset */ - -/* RCU_CFG1 */ -#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ -#define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source preselection */ -#define RCU_CFG1_PLLMF5 BIT(31) /*!< bit 5 of PLLMF */ - -/* RCU_CFG2 */ -#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ -#define RCU_CFG2_CECSEL BIT(6) /*!< CK_CEC clock source selection */ -#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ -#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */ -#define RCU_CFG2_USBFSPSC2 BIT(30) /*!< bit 2 of USBFSPSC */ -#define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */ - -/* RCU_CTL1 */ -#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */ -#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */ -#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */ -#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */ - -/* RCU_ADDCTL */ -#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48M clock selection */ -#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< IRC48M internal 48M RC oscillator enable */ -#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48M RC oscillator stabilization flag */ -#define RCU_ADDCTL_IRC48MCALIB BITS(24,31) /*!< internal 48M RC oscillator calibration value register */ - -/* RCU_ADDINT */ -#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ -#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< IRC48M stabilization interrupt enable */ -#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< IRC48M stabilization interrupt clear */ - -/* RCU_ADDAPB1EN */ -#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC unit clock enable */ - -/* RCU_ADDAPB1RST */ -#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC unit reset */ - -/* RCU_VKEY */ -#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & (uint32_t)0x0000001FU) -/* define the voltage key unlock value */ -#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) - -/* register index */ -typedef enum -{ - /* peripherals enable */ - IDX_AHBEN = ((uint32_t)0x00000014U), - IDX_APB2EN = ((uint32_t)0x00000018U), - IDX_APB1EN = ((uint32_t)0x0000001CU), - IDX_ADDAPB1EN = ((uint32_t)0x000000F8U), - /* peripherals reset */ - IDX_AHBRST = ((uint32_t)0x00000028U), - IDX_APB2RST = ((uint32_t)0x0000000CU), - IDX_APB1RST = ((uint32_t)0x00000010U), - IDX_ADDAPB1RST = ((uint32_t)0x000000FCU), - /* clock stabilization */ - IDX_CTL0 = ((uint32_t)0x00000000U), - IDX_BDCTL = ((uint32_t)0x00000020U), - IDX_CTL1 = ((uint32_t)0x00000034U), - IDX_ADDCTL = ((uint32_t)0x000000C0U), - /* peripheral reset */ - IDX_RSTSCK = ((uint32_t)0x00000024U), - /* clock stabilization and stuck interrupt */ - IDX_INT = ((uint32_t)0x00000008U), - IDX_ADDINT = ((uint32_t)0x000000CCU), - /* configuration register */ - IDX_CFG0 = ((uint32_t)0x00000004U), - IDX_CFG2 = ((uint32_t)0x00000030U) -}reg_idx; - -/* peripheral clock enable */ -typedef enum -{ - /* AHB peripherals */ - RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */ - RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */ - RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U), /*!< GPIOD clock */ - RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */ - RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U), /*!< TSI clock */ - - /* APB2 peripherals */ - RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */ - RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */ - RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */ - RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */ - RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */ - RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */ - - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */ - RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */ - RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */ - RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */ -#if defined(GD32F350) - RCU_DAC = RCU_REGIDX_BIT(IDX_APB1EN, 29U), /*!< DAC clock */ - RCU_CEC = RCU_REGIDX_BIT(IDX_APB1EN, 30U), /*!< CEC clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */ - RCU_USBFS = RCU_REGIDX_BIT(IDX_AHBEN, 12U), /*!< USBFS clock */ -#endif /* GD32F350 */ - RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U), /*!< RTC clock */ - - /* RCU_ADDAPB1EN */ - RCU_CTC = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U) /*!< CTC clock */ -}rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum -{ - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */ -}rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum -{ - /* AHB peripherals reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U), /*!< GPIOD reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */ - RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U), /*!< TSI reset */ - - /* APB2 peripherals reset */ - RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */ - RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */ - RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */ - RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */ - RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */ - RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */ - - /* APB1 peripherals reset */ - RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U), /*!< TIMER1 reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */ - RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */ - RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */ - RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */ -#if defined(GD32F350) - RCU_DACRST = RCU_REGIDX_BIT(IDX_APB1RST, 29U), /*!< DAC reset */ - RCU_CECRST = RCU_REGIDX_BIT(IDX_APB1RST, 30U), /*!< CEC reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ - RCU_USBFSRST = RCU_REGIDX_BIT(IDX_AHBRST, 12U), /*!< USBFS reset */ -#endif /* GD32F350 */ - /* RCU_ADDAPB1RST */ - RCU_CTCRST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U), /*!< CTC reset */ -}rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum -{ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */ - RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */ - RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 17U), /*!< IRC48M stabilization flags */ - - RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */ - RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */ -}rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */ - RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */ - RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 6U) /*!< IRC48M stabilization interrupt flag */ -}rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */ - RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDCTL, 22U) /*!< IRC48M stabilization interrupt flag clear */ -}rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum -{ - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */ - RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */ - RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 14U) /*!< IRC48M stabilization interrupt */ -}rcu_int_enum; - -/* ADC clock source */ -typedef enum -{ - RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */ - RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */ - RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */ - RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */ - RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */ - RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */ - RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */ - RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */ - RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */ - RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */ -}rcu_adc_clock_enum; - -/* oscillator types */ -typedef enum -{ - RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */ - RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */ - RCU_IRC48M = RCU_REGIDX_BIT(IDX_ADDCTL, 16U), /*!< IRC48M */ - RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */ -}rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum -{ - CK_SYS = 0U, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ - CK_ADC, /*!< ADC clock */ - CK_CEC, /*!< CEC clock */ - CK_USART /*!< USART clock */ -}rcu_clock_freq_enum; - -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC clock prescaler selection */ -#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) -#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ -#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ -#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ -#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< PLL clock source select IRC8M/2 */ -#define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL or IRC48M*/ - -/* PLL clock source preselection */ -#define RCU_PLLPRESEL_HXTAL ((uint32_t)0x00000000U) /*!< PLL clock source preselection HXTAL */ -#define RCU_PLLPRESEL_IRC48M RCU_CFG1_PLLPRESEL /*!< PLL clock source preselection IRC48M */ - -/* HXTAL or IRC48M divider for PLL source clock selection */ -#define RCU_PLLPREDV ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M clock selected */ -#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< (HXTAL or IRC48M) /2 clock selected */ - -/* PLL multiply factor */ -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ -#define RCU_PLL_MUL33 (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 33 */ -#define RCU_PLL_MUL34 (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 34 */ -#define RCU_PLL_MUL35 (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 35 */ -#define RCU_PLL_MUL36 (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 36 */ -#define RCU_PLL_MUL37 (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 37 */ -#define RCU_PLL_MUL38 (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 38 */ -#define RCU_PLL_MUL39 (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 39 */ -#define RCU_PLL_MUL40 (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 40 */ -#define RCU_PLL_MUL41 (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 41 */ -#define RCU_PLL_MUL42 (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 42 */ -#define RCU_PLL_MUL43 (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 43 */ -#define RCU_PLL_MUL44 (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 44 */ -#define RCU_PLL_MUL45 (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 45 */ -#define RCU_PLL_MUL46 (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 46 */ -#define RCU_PLL_MUL47 (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 47 */ -#define RCU_PLL_MUL48 (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 48 */ -#define RCU_PLL_MUL49 (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 49 */ -#define RCU_PLL_MUL50 (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 50 */ -#define RCU_PLL_MUL51 (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 51 */ -#define RCU_PLL_MUL52 (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 52 */ -#define RCU_PLL_MUL53 (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 53 */ -#define RCU_PLL_MUL54 (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 54 */ -#define RCU_PLL_MUL55 (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 55 */ -#define RCU_PLL_MUL56 (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 56 */ -#define RCU_PLL_MUL57 (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 57 */ -#define RCU_PLL_MUL58 (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 58 */ -#define RCU_PLL_MUL59 (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 59 */ -#define RCU_PLL_MUL60 (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 60 */ -#define RCU_PLL_MUL61 (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 61 */ -#define RCU_PLL_MUL62 (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 62 */ -#define RCU_PLL_MUL63 (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 63 */ -#define RCU_PLL_MUL64 (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 64 */ - -/* USBFS clock prescaler selection */ -#define CFG0_USBFSPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -#define RCU_USBFS_CKPLL_DIV1_5 CFG0_USBFSPSC(0) /*!< USBFS clock prescaler select CK_PLL/1.5 */ -#define RCU_USBFS_CKPLL_DIV1 CFG0_USBFSPSC(1) /*!< USBFS clock prescaler select CK_PLL */ -#define RCU_USBFS_CKPLL_DIV2_5 CFG0_USBFSPSC(2) /*!< USBFS clock prescaler select CK_PLL/2.5 */ -#define RCU_USBFS_CKPLL_DIV2 CFG0_USBFSPSC(3) /*!< USBFS clock prescaler select CK_PLL/2 */ -#define RCU_USBFS_CKPLL_DIV3 RCU_CFG2_USBFSPSC2 /*!< USBFS clock prescaler select CK_PLL/3 */ -#define RCU_USBFS_CKPLL_DIV3_5 (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2) /*!< USBFS clock prescaler select CK_PLL/3.5 */ - -/* CK_OUT clock source selection */ -#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ -#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */ -#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */ -#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ -#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ -#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */ -#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ -#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ -#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ - -/* CK_OUT divider */ -#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) -#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ -#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ -#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ -#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ -#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ -#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ -#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ -#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ - -/* CK_PLL divide by 1 or 2 for CK_OUT */ -#define RCU_PLLDV_CKPLL_DIV2 ((uint32_t)0x00000000U) /*!< CK_PLL divide by 2 for CK_OUT */ -#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ - -/* LXTAL drive capability */ -#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ -#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ -#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ -#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */ -#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ - -/* CK_HXTAL divider previous PLL */ -#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ -#define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ -#define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ -#define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ -#define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ -#define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ -#define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ -#define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ -#define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ -#define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ -#define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ -#define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ -#define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ -#define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ -#define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ -#define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ - -/* USART0 clock source selection */ -#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ -#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ -#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ -#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */ - -/* CEC clock source selection */ -#define RCU_CECSRC_IRC8M_DIV244 ((uint32_t)0x00000000U) /*!< CK_CEC clock source select IRC8M/244 */ -#define RCU_CECSRC_LXTAL RCU_CFG2_CECSEL /*!< CK_CEC clock source select LXTAL */ - -/* ADC clock source selection */ -#define RCU_ADCSRC_IRC28M ((uint32_t)0x00000000U) /*!< ADC clock source select */ -#define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ - -/* IRC28M clock divider for ADC */ -#define RCU_ADC_IRC28M_DIV2 ((uint32_t)0x00000000U) /*!< IRC28M/2 select to ADC clock */ -#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */ - -/* CK48M clock source selection */ -#define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ -#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ - -/* Deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ - -/* function declarations */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP */ -void rcu_bkp_reset_enable(void); -/* disable the BKP reset */ -void rcu_bkp_reset_disable(void); - -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the ADC clock source and prescaler selection */ -void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc); -/* configure the USBFS prescaler selection */ -void rcu_usbfs_clock_config(uint32_t ck_usbfs); -/* configure the CK_OUT clock source and divider */ -void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); - -/* configure the PLL clock source preselection */ -void rcu_pll_preselection_config(uint32_t pll_presel); -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -/* configure the USART clock source selection */ -void rcu_usart_clock_config(uint32_t ck_usart); -/* configure the CEC clock source selection */ -void rcu_cec_clock_config(uint32_t ck_cec); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -/* configure the CK48M clock selection */ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); -/* configure the HXTAL divider used as input of PLL */ -void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* wait until oscillator stabilization flags is SET */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); -/* set the IRC28M adjust value */ -void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval); -/* unlock the voltage key */ -void rcu_voltage_key_unlock(void); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32F3X0_RCU_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h deleted file mode 100644 index 767d90992d..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_rtc.h +++ /dev/null @@ -1,560 +0,0 @@ -/*! - \file gd32f3x0_rtc.h - \brief definitions for the RTC - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_RTC_H -#define GD32F3X0_RTC_H - -#include "gd32f3x0.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_TIME REG32(RTC + 0x00000000U) /*!< RTC time of day register */ -#define RTC_DATE REG32(RTC + 0x00000004U) /*!< RTC date register */ -#define RTC_CTL REG32(RTC + 0x00000008U) /*!< RTC control register */ -#define RTC_STAT REG32(RTC + 0x0000000CU) /*!< RTC status register */ -#define RTC_PSC REG32(RTC + 0x00000010U) /*!< RTC time prescaler register */ -#define RTC_ALRM0TD REG32(RTC + 0x0000001CU) /*!< RTC alarm 0 time and date register */ -#define RTC_WPK REG32(RTC + 0x00000024U) /*!< RTC write protection key register */ -#define RTC_SS REG32(RTC + 0x00000028U) /*!< RTC sub second register */ -#define RTC_SHIFTCTL REG32(RTC + 0x0000002CU) /*!< RTC shift function control register */ -#define RTC_TTS REG32(RTC + 0x00000030U) /*!< RTC time of timestamp register */ -#define RTC_DTS REG32(RTC + 0x00000034U) /*!< RTC date of timestamp register */ -#define RTC_SSTS REG32(RTC + 0x00000038U) /*!< RTC sub second of timestamp register */ -#define RTC_HRFC REG32(RTC + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */ -#define RTC_TAMP REG32(RTC + 0x00000040U) /*!< RTC tamper register */ -#define RTC_ALRM0SS REG32(RTC + 0x00000044U) /*!< RTC alarm 0 sub second register */ -#define RTC_BKP0 REG32(RTC + 0x00000050U) /*!< RTC backup 0 register */ -#define RTC_BKP1 REG32(RTC + 0x00000054U) /*!< RTC backup 1 register */ -#define RTC_BKP2 REG32(RTC + 0x00000058U) /*!< RTC backup 2 register */ -#define RTC_BKP3 REG32(RTC + 0x0000005CU) /*!< RTC backup 3 register */ -#define RTC_BKP4 REG32(RTC + 0x00000060U) /*!< RTC backup 4 register */ - -/* bits definitions */ -/* RTC_TIME */ -#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DATE */ -#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ -#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ -#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ - -/* RTC_CTL */ -#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ -#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ -#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ -#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ -#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */ -#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ -#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */ -#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ -#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ -#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ -#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ -#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ -#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ -#define RTC_CTL_OS BITS(21,22) /*!< output selection */ -#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ - -/* RTC_STAT */ -#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ -#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ -#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ -#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ -#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ -#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ -#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */ -#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ -#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ -#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ -#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ -#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */ - -/* RTC_PSC */ -#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ -#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ - -/* RTC_ALRM0TD */ -#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */ -#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */ -#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */ -#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */ -#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */ -#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */ -#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */ -#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ -#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */ -#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */ -#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */ - -/* RTC_WPK */ -#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ - -/* RTC_SS */ -#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ - -/* RTC_SHIFTCTL */ -#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ -#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ - -/* RTC_TTS */ -#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ -#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DTS */ -#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ - -/* RTC_SSTS */ -#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ - -/* RTC_HRFC */ -#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ -#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ - -/* RTC_TAMP */ -#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ -#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ -#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ -#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ -#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ -#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ -#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ -#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ -#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ -#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ -#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */ -#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */ -#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */ -#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */ -#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */ -#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */ - -/* RTC_ALRM0SS */ -#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */ -#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ - -/* RTC_BKP0 */ -#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP1 */ -#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP2 */ -#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP3 */ -#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP4 */ -#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ - -/* constants definitions */ -/* structure for initialization of the RTC */ -typedef struct -{ - uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ - uint8_t rtc_month; /*!< RTC month value */ - uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ - uint8_t rtc_day_of_week; /*!< RTC weekday value */ - uint8_t rtc_hour; /*!< RTC hour value */ - uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ - uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ - uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ - uint32_t rtc_am_pm; /*!< RTC AM/PM value */ - uint32_t rtc_display_format; /*!< RTC time notation */ -}rtc_parameter_struct; - -/* structure for RTC alarm configuration */ -typedef struct -{ - uint32_t rtc_alarm_mask; /*!< RTC alarm mask */ - uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */ - uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/ - uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */ - uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ - uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */ -}rtc_alarm_struct; - -/* structure for RTC time-stamp configuration */ -typedef struct -{ - uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */ - uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ - uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */ - uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */ - uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ - uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */ -}rtc_timestamp_struct; - -/* structure for RTC tamper configuration */ -typedef struct -{ - uint32_t rtc_tamper_source; /*!< RTC tamper source */ - uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */ - uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ - uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ - ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ - uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ - ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ -}rtc_tamper_struct; - -/* time register value */ -#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */ -#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ - -#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */ -#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ - -#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */ -#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ - -#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ -#define RTC_PM RTC_TIME_PM /*!< PM format */ - -/* date register value */ -#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */ -#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ - -#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */ -#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ -#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ -#define RTC_FEB ((uint8_t)0x02U) /*!< February */ -#define RTC_MAR ((uint8_t)0x03U) /*!< March */ -#define RTC_APR ((uint8_t)0x04U) /*!< April */ -#define RTC_MAY ((uint8_t)0x05U) /*!< May */ -#define RTC_JUN ((uint8_t)0x06U) /*!< June */ -#define RTC_JUL ((uint8_t)0x07U) /*!< July */ -#define RTC_AUG ((uint8_t)0x08U) /*!< August */ -#define RTC_SEP ((uint8_t)0x09U) /*!< September */ -#define RTC_OCT ((uint8_t)0x10U) /*!< October */ -#define RTC_NOV ((uint8_t)0x11U) /*!< November */ -#define RTC_DEC ((uint8_t)0x12U) /*!< December */ - -#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */ -#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ -#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */ -#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ -#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */ -#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */ -#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */ -#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ -#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ - -#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */ -#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ - -/* ctl register value */ -#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */ -#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ -#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */ - -#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ -#define RTC_CALIBRATION_1HZ RTC_CTL_COEN | RTC_CTL_COS /*!< calibration output of 1Hz is enable */ -#define RTC_ALARM_HIGH RTC_CTL_OS_ENABLE /*!< enable alarm flag output with high level */ -#define RTC_ALARM_LOW RTC_CTL_OS_ENABLE | RTC_CTL_OPOL /*!< enable alarm flag output with low level*/ - -#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ -#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ - -#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ -#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ - -/* psc register value */ -#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */ -#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ - -#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */ -#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ - -/* alrm0td register value */ -#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */ -#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */ - -#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */ -#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */ - -#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */ -#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */ - -#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */ -#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */ - -#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ -#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */ -#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */ -#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */ -#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */ -#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */ - -#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ -#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */ - -/* wpk register value */ -#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */ - -/* ss register value */ -#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */ - -/* shiftctl register value */ -#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ - -#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ -#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ - -/* tts register value */ -#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */ -#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ - -#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */ -#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ - -#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */ -#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ - -/* dts register value */ -#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */ -#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ - -#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */ -#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ - -#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */ -#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ - -/* ssts register value */ -#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */ - -/* hrfc register value */ -#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */ - -#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ - -#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ -#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ - -/* tamp register value */ -#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */ -#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ - -#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */ -#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ -#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ -#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ -#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ - -#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */ -#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ - -#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ -#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ - -#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ -#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ - -#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ - -#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ -#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */ - -/* alrm0ss register value */ -#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */ - -#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */ -#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */ -#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */ -#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */ -#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */ -#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */ -#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */ -#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */ -#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */ -#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */ -#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */ -#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */ -#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */ -#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */ -#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */ -#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */ -#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */ - -/* RTC interrupt source */ -#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ -#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */ -#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ - -/* write protect key */ -#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ -#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ -#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ - -/* registers reset value */ -#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ -#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ -#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ -#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ - -/* RTC timeout value */ -#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ -#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ -#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */ -#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ -#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ - -/* RTC flag */ -#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */ -#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */ -#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */ -#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */ -#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */ -#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ -#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ -#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ -#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */ -#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */ - -/* function declarations */ -/* reset most of the RTC registers */ -ErrStatus rtc_deinit(void); -/* initialize RTC registers */ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); -/* enter RTC init mode */ -ErrStatus rtc_init_mode_enter(void); -/* exit RTC init mode */ -void rtc_init_mode_exit(void); -/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ -ErrStatus rtc_register_sync_wait(void); - -/* get current time and date */ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); -/* get current subsecond value */ -uint32_t rtc_subsecond_get(void); - -/* configure RTC alarm */ -void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time); -/* configure subsecond of RTC alarm */ -void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond); -/* get RTC alarm */ -void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time); -/* get RTC alarm subsecond */ -uint32_t rtc_alarm_subsecond_get(void); -/* enable RTC alarm */ -void rtc_alarm_enable(void); -/* disable RTC alarm */ -ErrStatus rtc_alarm_disable(void); - -/* enable RTC time-stamp */ -void rtc_timestamp_enable(uint32_t edge); -/* disable RTC time-stamp */ -void rtc_timestamp_disable(void); -/* get RTC timestamp time and date */ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); -/* get RTC time-stamp subsecond */ -uint32_t rtc_timestamp_subsecond_get(void); - -/* enable RTC tamper */ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); -/* disable RTC tamper */ -void rtc_tamper_disable(uint32_t source); - -/* enable specified RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disble specified RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); -/* check specified flag */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear specified flag */ -void rtc_flag_clear(uint32_t flag); - -/* configure RTC alternate output source */ -void rtc_alter_output_config(uint32_t source, uint32_t mode); -/* configure RTC calibration register */ -ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); -/* ajust the daylight saving time by adding or substracting one hour from the current time */ -void rtc_hour_adjust(uint32_t operation); -/* ajust RTC second or subsecond value of current time */ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); -/* enable RTC bypass shadow registers function */ -void rtc_bypass_shadow_enable(void); -/* disable RTC bypass shadow registers function */ -void rtc_bypass_shadow_disable(void); -/* enable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_enable(void); -/* disable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_disable(void); - -#endif /* GD32F3X0_RTC_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h deleted file mode 100644 index c24aad66a4..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_spi.h +++ /dev/null @@ -1,368 +0,0 @@ -/*! - \file gd32f3x0_spi.h - \brief definitions for the SPI - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_SPI_H -#define GD32F3X0_SPI_H - -#include "gd32f3x0.h" - -/* SPIx(x=0,1) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only SPI1) */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ -#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error bit */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* SPI_QCTL(only for SPI1) */ -#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ -#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ -#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct -{ - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI frame size */ -#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ -#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -#ifdef GD32F350 -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ -#endif /* GD32F350 */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ - -/* SPI flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ - -#ifdef GD32F350 -/* I2S flag definitions */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ -#endif /* GD32F350 */ - -/* function declarations */ -/* SPI/I2S deinitialization and initialization functions */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); -/* initialize SPI parameter */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -#ifdef GD32F350 -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); -#endif /* GD32F350 */ - -/* NSS functions */ -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); - -/* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); - -/* SPI TI mode functions */ -/* enable SPI TI mode */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* disable SPI TI mode */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* SPI NSS pulse mode functions */ -/* enable SPI NSS pulse mode */ -void spi_nssp_mode_enable(uint32_t spi_periph); -/* disable SPI NSS pulse mode */ -void spi_nssp_mode_disable(uint32_t spi_periph); - -/* quad wire SPI functions */ -/* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); -/* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); -/* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); -/* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); - -/* flag and interrupt functions */ -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -#endif /* GD32F3X0_SPI_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h deleted file mode 100644 index 861d0bec8c..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_syscfg.h +++ /dev/null @@ -1,190 +0,0 @@ -/*! - \file gd32f3x0_syscfg.h - \brief definitions for the SYSCFG - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_SYSCFG_H -#define GD32F3X0_SYSCFG_H - -#include "gd32f3x0.h" - -/* SYSCFG definitions */ -#define SYSCFG SYSCFG_BASE - -/* registers definitions */ -#define SYSCFG_CFG0 REG32(SYSCFG + 0x00000000U) /*!< system configuration register 0 */ -#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x00000008U) /*!< EXTI sources selection register 0 */ -#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0000000CU) /*!< EXTI sources selection register 1 */ -#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x00000010U) /*!< EXTI sources selection register 2 */ -#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x00000014U) /*!< EXTI sources selection register 3 */ -#define SYSCFG_CFG2 REG32(SYSCFG + 0x00000018U) /*!< system configuration register 2 */ -#define SYSCFG_CPSCTL REG32(SYSCFG + 0x00000020U) /*!< system I/O compensation control register */ - -/* SYSCFG_CFG0 bits definitions */ -#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */ -#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */ -#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */ -#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */ -#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */ -#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */ -#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */ - -/* SYSCFG_EXTISS0 bits definitions */ -#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ - -/* SYSCFG_EXTISS1 bits definitions */ -#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ - -/* SYSCFG_EXTISS2 bits definitions */ -#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ - -/* SYSCFG_EXTISS3 bits definitions */ -#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ - -/* SYSCFG_CFG2 bits definitions */ -#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M4 with break input of TIMER0/14/15/16 */ -#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */ -#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */ -#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */ - -/* SYSCFG_CPSCTL bits definitions */ -#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ -#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ - -/* constants definitions */ -/* DMA remap definitions */ -#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */ -#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */ -#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */ -#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */ -#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */ - -/* high current definitions */ -#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */ -#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */ - -/* EXTI source select definition */ -#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ -#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ -#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ -#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ - -/* EXTI source select mask bits definition */ -#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ - -/* EXTI source select jumping step definition */ -#define EXTI_SS_JSTEP ((uint8_t)0x04U) /*!< EXTI source select jumping step */ - -/* EXTI source select moving step definition */ -#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ - -/* EXTI source port definitions */ -#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ -#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ -#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ -#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ -#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ - -/* EXTI source pin definitions */ -#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ -#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ -#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ -#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ -#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ -#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ -#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ -#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ -#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ -#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ -#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ -#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ -#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ -#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ -#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ -#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ - -/* lock definitions */ -#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ -#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */ -#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ - -/* SRAM parity check error flag definitions */ -#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */ - -/* I/O compensation cell enable/disable */ -#define SYSCFG_COMPENSATION(regval) (BIT(0) & ((uint32_t)(regval) << 0)) -#define SYSCFG_COMPENSATION_DISABLE SYSCFG_COMPENSATION(0) /*!< I/O compensation cell is power-down */ -#define SYSCFG_COMPENSATION_ENABLE SYSCFG_COMPENSATION(1) /*!< I/O compensation cell is enabled */ - -/* function declarations */ -/* deinit syscfg module */ -void syscfg_deinit(void); - -/* enable the DMA channels remapping */ -void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap); -/* disable the DMA channels remapping */ -void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap); - -/* enable PB9 high current capability */ -void syscfg_high_current_enable(void); -/* disable PB9 high current capability */ -void syscfg_high_current_disable(void); - -/* configure the GPIO pin as EXTI Line */ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); -/* connect TIMER0/14/15/16 break input to the selected parameter */ -void syscfg_lock_config(uint32_t syscfg_lock); - -/* check if the specified flag in SYSCFG_CFG2 is set or not */ -FlagStatus syscfg_flag_get(uint32_t syscfg_flag); -/* clear the flag in SYSCFG_CFG2 by writing 1 */ -void syscfg_flag_clear(uint32_t syscfg_flag); - -/* configure the I/O compensation cell */ -void syscfg_compensation_config(uint32_t syscfg_compensation); -/* check if the I/O compensation cell ready flag is set or not */ -FlagStatus syscfg_cps_rdy_flag_get(void); - -#endif /* GD32F3X0_SYSCFG_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h deleted file mode 100644 index b9e3cb9ed6..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_timer.h +++ /dev/null @@ -1,768 +0,0 @@ -/*! - \file gd32f3x0_timer.h - \brief definitions for the TIMER - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_TIMER_H -#define GD32F3X0_TIMER_H - -#include "gd32f3x0.h" - -/* TIMERx(x=0,1,2,5,13..16) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER1 (TIMER_BASE + 0x00000000U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#ifdef GD32F350 -#define TIMER5 (TIMER_BASE + 0x00001000U) -#endif -#define TIMER13 (TIMER_BASE + 0x00002000U) -#define TIMER14 (TIMER_BASE + 0x00014000U) -#define TIMER15 (TIMER_BASE + 0x00014400U) -#define TIMER16 (TIMER_BASE + 0x00014800U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00000000U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x00000004U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x00000008U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0000000CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x00000010U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x00000014U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x00000018U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x0000001CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x00000020U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x00000024U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x00000028U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x0000002CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x00000030U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x00000034U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x00000038U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x0000003CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x00000040U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x00000044U) /*!< TIMER complementary channel protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x00000048U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x0000004CU) /*!< TIMER DMA transfer buffer register */ -#define TIMER_IRMP(timerx) REG32((timerx) + 0x00000050U) /*!< TIMER channel input remap register */ -#define TIMER_CFG(timerx) REG32((timerx) + 0x000000FCU) /*!< TIMER configuration register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ -#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ -#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1) timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ -#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1) counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ -#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ -#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ -#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ -#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1) capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* TIMER_IRMP */ -#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */ - -/* TIMER_CFG */ -#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ -#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ - -/* constants definitions */ -/* TIMER init parameter struct definitions*/ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint16_t clockdivision; /*!< clock division value */ - uint32_t period; /*!< period value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions*/ -typedef struct -{ - uint32_t runoffstate; /*!< run mode off-state */ - uint32_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint32_t outputautostate; /*!< output automatic enable */ - uint32_t protectmode; /*!< complementary register protect control */ - uint32_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint32_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ -#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ -#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ -#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ -#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ -#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ -#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF - -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW ((uint8_t)0x00U) /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint8_t)0x01U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)0x0010U) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE ((uint8_t)0x00U) /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint8_t)0x01U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR ((uint8_t)0x00U) /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint8_t)0x01U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint32_t)0x00000800U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint32_t)0x00000000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)0x0400U) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)0x2000U) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)0x4000U) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)0x1000U) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..2,13..16)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..2,14)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..2)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..2)) */ - -/* channel enable state*/ -#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ - -/* channel complementary output enable state*/ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint8_t)0x00U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI ((uint8_t)0x01U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ - -/* timer input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* OCPRE clear source selection */ -#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */ -#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint8_t)0x00U) /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint8_t)0x01U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE ((uint8_t)0x00U) /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint8_t)0x01U) /*!< TIMER hall sensor mode disable */ - -/* timerx(x=0,1,2,13,14,15,16) write CHxVAL register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ - -/* the output value selection */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ -#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ - -/* timer13 channel 0 input remap */ -#define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) -#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0) /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */ -#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1) /*!< timer13 channel 0 input is connected to the RTCCLK */ -#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2) /*!< timer13 channel 0 input is connected to HXTAL/32 clock */ -#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3) /*!< timer13 channel 0 input is connected to CKOUTSEL */ - -/* function declarations */ -/* TIMER timebase*/ -/* deinit a TIMER */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct* initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a TIMER */ -void timer_enable(uint32_t timer_periph); -/* disable a TIMER */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph , uint32_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint8_t update); -/* OCPRE clear source selection */ -void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear); - -/* TIMER interrupt and flag*/ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -/* TIMER DMA and event*/ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode); - -/* TIMER master and slave */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); -/* configure TIMER channel remap function */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); - -/* TIMER configure */ -/* configure TIMER write CHxVAL register selection */ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); -/* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); - -#endif /* GD32F3X0_TIMER_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h deleted file mode 100644 index ec03a4bc8a..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_tsi.h +++ /dev/null @@ -1,396 +0,0 @@ -/*! - \file gd32f3x0_tsi.h - \brief definitions for the TSI - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_TSI_H -#define GD32F3X0_TSI_H - -#include "gd32f3x0.h" - -/* TSI definitions */ -#define TSI TSI_BASE /*!< TSI base address */ - -/* registers definitions */ -#define TSI_CTL0 REG32(TSI + 0x00000000U)/*!< TSI control register0 */ -#define TSI_INTEN REG32(TSI + 0x00000004U)/*!< TSI interrupt enable register */ -#define TSI_INTC REG32(TSI + 0x00000008U)/*!< TSI interrupt flag clear register */ -#define TSI_INTF REG32(TSI + 0x0000000CU)/*!< TSI interrupt flag register */ -#define TSI_PHM REG32(TSI + 0x00000010U)/*!< TSI pin hysteresis mode register */ -#define TSI_ASW REG32(TSI + 0x00000018U)/*!< TSI analog switch register */ -#define TSI_SAMPCFG REG32(TSI + 0x00000020U)/*!< TSI sample configuration register */ -#define TSI_CHCFG REG32(TSI + 0x00000028U)/*!< TSI channel configuration register */ -#define TSI_GCTL REG32(TSI + 0x00000030U)/*!< TSI group control register */ -#define TSI_G0CYCN REG32(TSI + 0x00000034U)/*!< TSI group 0 cycle number register */ -#define TSI_G1CYCN REG32(TSI + 0x00000038U)/*!< TSI group 1 cycle number register */ -#define TSI_G2CYCN REG32(TSI + 0x0000003CU)/*!< TSI group 2 cycle number register */ -#define TSI_G3CYCN REG32(TSI + 0x00000040U)/*!< TSI group 3 cycle number register */ -#define TSI_G4CYCN REG32(TSI + 0x00000044U)/*!< TSI group 4 cycle number register */ -#define TSI_G5CYCN REG32(TSI + 0x00000048U)/*!< TSI group 5 cycle number register */ -#define TSI_CTL1 REG32(TSI + 0x00000300U)/*!< TSI control registers1 */ - -/* bits definitions */ -/* TSI_CTL0 */ -#define TSI_CTL0_TSIEN BIT(0) /*!< TSI enable */ -#define TSI_CTL0_TSIS BIT(1) /*!< TSI start */ -#define TSI_CTL0_TRGMOD BIT(2) /*!< trigger mode selection */ -#define TSI_CTL0_EGSEL BIT(3) /*!< edge selection */ -#define TSI_CTL0_PINMOD BIT(4) /*!< pin mode */ -#define TSI_CTL0_MCN BITS(5,7) /*!< max cycle number of a sequence */ -#define TSI_CTL0_CTCDIV BITS(12,14) /*!< CTCLK clock division factor */ -#define TSI_CTL0_ECDIV BIT(15) /*!< ECCLK clock division factor */ -#define TSI_CTL0_ECEN BIT(16) /*!< extend charge state enable */ -#define TSI_CTL0_ECDT BITS(17,23) /*!< extend charge State maximum duration time */ -#define TSI_CTL0_CTDT BITS(24,27) /*!< charge transfer state duration time */ -#define TSI_CTL0_CDT BITS(28,31) /*!< charge state duration time */ - -/* TSI_INTEN */ -#define TSI_INTEN_CTCFIE BIT(0) /*!< charge transfer complete flag interrupt enable */ -#define TSI_INTEN_MNERRIE BIT(1) /*!< max cycle number error interrupt enable */ - -/* TSI_INTC */ -#define TSI_INTC_CCTCF BIT(0) /*!< clear charge transfer complete flag */ -#define TSI_INTC_CMNERR BIT(1) /*!< clear max cycle number error */ - -/* TSI_INTF */ -#define TSI_INTF_CTCF BIT(0) /*!< charge transfer complete flag */ -#define TSI_INTF_MNERR BIT(1) /*!< max cycle number error */ - -/* TSI_PHM */ -#define TSI_PHM_G0P0 BIT(0) /*!< pin G0P0 Schmitt trigger hysteresis state */ -#define TSI_PHM_G0P1 BIT(1) /*!< pin G0P1 Schmitt trigger hysteresis state */ -#define TSI_PHM_G0P2 BIT(2) /*!< pin G0P2 Schmitt trigger hysteresis state */ -#define TSI_PHM_G0P3 BIT(3) /*!< pin G0P3 Schmitt trigger hysteresis state */ -#define TSI_PHM_G1P0 BIT(4) /*!< pin G1P0 Schmitt trigger hysteresis state */ -#define TSI_PHM_G1P1 BIT(5) /*!< pin G1P1 Schmitt trigger hysteresis state */ -#define TSI_PHM_G1P2 BIT(6) /*!< pin G1P2 Schmitt trigger hysteresis state */ -#define TSI_PHM_G1P3 BIT(7) /*!< pin G1P3 Schmitt trigger hysteresis state */ -#define TSI_PHM_G2P0 BIT(8) /*!< pin G2P0 Schmitt trigger hysteresis state */ -#define TSI_PHM_G2P1 BIT(9) /*!< pin G2P1 Schmitt trigger hysteresis state */ -#define TSI_PHM_G2P2 BIT(10) /*!< pin G2P2 Schmitt trigger hysteresis state */ -#define TSI_PHM_G2P3 BIT(11) /*!< pin G2P3 Schmitt trigger hysteresis state */ -#define TSI_PHM_G3P0 BIT(12) /*!< pin G3P0 Schmitt trigger hysteresis state */ -#define TSI_PHM_G3P1 BIT(13) /*!< pin G3P1 Schmitt trigger hysteresis state */ -#define TSI_PHM_G3P2 BIT(14) /*!< pin G3P2 Schmitt trigger hysteresis state */ -#define TSI_PHM_G3P3 BIT(15) /*!< pin G3P3 Schmitt trigger hysteresis state */ -#define TSI_PHM_G4P0 BIT(16) /*!< pin G4P0 Schmitt trigger hysteresis state */ -#define TSI_PHM_G4P1 BIT(17) /*!< pin G4P1 Schmitt trigger hysteresis state */ -#define TSI_PHM_G4P2 BIT(18) /*!< pin G4P2 Schmitt trigger hysteresis state */ -#define TSI_PHM_G4P3 BIT(19) /*!< pin G4P3 Schmitt trigger hysteresis state */ -#define TSI_PHM_G5P0 BIT(20) /*!< pin G5P0 Schmitt trigger hysteresis state */ -#define TSI_PHM_G5P1 BIT(21) /*!< pin G5P1 Schmitt trigger hysteresis state */ -#define TSI_PHM_G5P2 BIT(22) /*!< pin G5P2 Schmitt trigger hysteresis state */ -#define TSI_PHM_G5P3 BIT(23) /*!< pin G5P3 Schmitt trigger hysteresis state */ - -/* TSI_ASW */ -#define TSI_ASW_G0P0 BIT(0) /*!< pin G0P0 analog switch state */ -#define TSI_ASW_G0P1 BIT(1) /*!< pin G0P1 analog switch state */ -#define TSI_ASW_G0P2 BIT(2) /*!< pin G0P2 analog switch state */ -#define TSI_ASW_G0P3 BIT(3) /*!< pin G0P3 analog switch state */ -#define TSI_ASW_G1P0 BIT(4) /*!< pin G1P0 analog switch state */ -#define TSI_ASW_G1P1 BIT(5) /*!< pin G1P1 analog switch state */ -#define TSI_ASW_G1P2 BIT(6) /*!< pin G1P2 analog switch state */ -#define TSI_ASW_G1P3 BIT(7) /*!< pin G1P3 analog switch state */ -#define TSI_ASW_G2P0 BIT(8) /*!< pin G2P0 analog switch state */ -#define TSI_ASW_G2P1 BIT(9) /*!< pin G2P1 analog switch state */ -#define TSI_ASW_G2P2 BIT(10) /*!< pin G2P2 analog switch state */ -#define TSI_ASW_G2P3 BIT(11) /*!< pin G2P3 analog switch state */ -#define TSI_ASW_G3P0 BIT(12) /*!< pin G3P0 analog switch state */ -#define TSI_ASW_G3P1 BIT(13) /*!< pin G3P1 analog switch state */ -#define TSI_ASW_G3P2 BIT(14) /*!< pin G3P2 analog switch state */ -#define TSI_ASW_G3P3 BIT(15) /*!< pin G3P3 analog switch state */ -#define TSI_ASW_G4P0 BIT(16) /*!< pin G4P0 analog switch state */ -#define TSI_ASW_G4P1 BIT(17) /*!< pin G4P1 analog switch state */ -#define TSI_ASW_G4P2 BIT(18) /*!< pin G4P2 analog switch state */ -#define TSI_ASW_G4P3 BIT(19) /*!< pin G4P3 analog switch state */ -#define TSI_ASW_G5P0 BIT(20) /*!< pin G5P0 analog switch state */ -#define TSI_ASW_G5P1 BIT(21) /*!< pin G5P1 analog switch state */ -#define TSI_ASW_G5P2 BIT(22) /*!< pin G5P2 analog switch state */ -#define TSI_ASW_G5P3 BIT(23) /*!< pin G5P3 analog switch state */ - -/* TSI_SAMPCFG */ -#define TSI_SAMPCFG_G0P0 BIT(0) /*!< pin G0P0 sample pin mode */ -#define TSI_SAMPCFG_G0P1 BIT(1) /*!< pin G0P1 sample pin mode */ -#define TSI_SAMPCFG_G0P2 BIT(2) /*!< pin G0P2 sample pin mode */ -#define TSI_SAMPCFG_G0P3 BIT(3) /*!< pin G0P3 sample pin mode */ -#define TSI_SAMPCFG_G1P0 BIT(4) /*!< pin G1P0 sample pin mode */ -#define TSI_SAMPCFG_G1P1 BIT(5) /*!< pin G1P1 sample pin mode */ -#define TSI_SAMPCFG_G1P2 BIT(6) /*!< pin G1P2 sample pin mode */ -#define TSI_SAMPCFG_G1P3 BIT(7) /*!< pin G1P3 sample pin mode */ -#define TSI_SAMPCFG_G2P0 BIT(8) /*!< pin G2P0 sample pin mode */ -#define TSI_SAMPCFG_G2P1 BIT(9) /*!< pin G2P1 sample pin mode */ -#define TSI_SAMPCFG_G2P2 BIT(10) /*!< pin G2P2 sample pin mode */ -#define TSI_SAMPCFG_G2P3 BIT(11) /*!< pin G2P3 sample pin mode */ -#define TSI_SAMPCFG_G3P0 BIT(12) /*!< pin G3P0 sample pin mode */ -#define TSI_SAMPCFG_G3P1 BIT(13) /*!< pin G3P1 sample pin mode */ -#define TSI_SAMPCFG_G3P2 BIT(14) /*!< pin G3P2 sample pin mode */ -#define TSI_SAMPCFG_G3P3 BIT(15) /*!< pin G3P3 sample pin mode */ -#define TSI_SAMPCFG_G4P0 BIT(16) /*!< pin G4P0 sample pin mode */ -#define TSI_SAMPCFG_G4P1 BIT(17) /*!< pin G4P1 sample pin mode */ -#define TSI_SAMPCFG_G4P2 BIT(18) /*!< pin G4P2 sample pin mode */ -#define TSI_SAMPCFG_G4P3 BIT(19) /*!< pin G4P3 sample pin mode */ -#define TSI_SAMPCFG_G5P0 BIT(20) /*!< pin G5P0 sample pin mode */ -#define TSI_SAMPCFG_G5P1 BIT(21) /*!< pin G5P1 sample pin mode */ -#define TSI_SAMPCFG_G5P2 BIT(22) /*!< pin G5P2 sample pin mode */ -#define TSI_SAMPCFG_G5P3 BIT(23) /*!< pin G5P3 sample pin mode */ - -/* TSI_CHCFG */ -#define TSI_CHCFG_G0P0 BIT(0) /*!< pin G0P0 channel pin mode */ -#define TSI_CHCFG_G0P1 BIT(1) /*!< pin G0P1 channel pin mode */ -#define TSI_CHCFG_G0P2 BIT(2) /*!< pin G0P2 channel pin mode */ -#define TSI_CHCFG_G0P3 BIT(3) /*!< pin G0P3 channel pin mode */ -#define TSI_CHCFG_G1P0 BIT(4) /*!< pin G1P0 channel pin mode */ -#define TSI_CHCFG_G1P1 BIT(5) /*!< pin G1P1 channel pin mode */ -#define TSI_CHCFG_G1P2 BIT(6) /*!< pin G1P2 channel pin mode */ -#define TSI_CHCFG_G1P3 BIT(7) /*!< pin G1P3 channel pin mode */ -#define TSI_CHCFG_G2P0 BIT(8) /*!< pin G2P0 channel pin mode */ -#define TSI_CHCFG_G2P1 BIT(9) /*!< pin G2P1 channel pin mode */ -#define TSI_CHCFG_G2P2 BIT(10) /*!< pin G2P2 channel pin mode */ -#define TSI_CHCFG_G2P3 BIT(11) /*!< pin G2P3 channel pin mode */ -#define TSI_CHCFG_G3P0 BIT(12) /*!< pin G3P0 channel pin mode */ -#define TSI_CHCFG_G3P1 BIT(13) /*!< pin G3P1 channel pin mode */ -#define TSI_CHCFG_G3P2 BIT(14) /*!< pin G3P2 channel pin mode */ -#define TSI_CHCFG_G3P3 BIT(15) /*!< pin G3P3 channel pin mode */ -#define TSI_CHCFG_G4P0 BIT(16) /*!< pin G4P0 channel pin mode */ -#define TSI_CHCFG_G4P1 BIT(17) /*!< pin G4P1 channel pin mode */ -#define TSI_CHCFG_G4P2 BIT(18) /*!< pin G4P2 channel pin mode */ -#define TSI_CHCFG_G4P3 BIT(19) /*!< pin G4P3 channel pin mode */ -#define TSI_CHCFG_G5P0 BIT(20) /*!< pin G5P0 channel pin mode */ -#define TSI_CHCFG_G5P1 BIT(21) /*!< pin G5P1 channel pin mode */ -#define TSI_CHCFG_G5P2 BIT(22) /*!< pin G5P2 channel pin mode */ -#define TSI_CHCFG_G5P3 BIT(23) /*!< pin G5P3 channel pin mode */ - -/* TSI_GCTL */ -#define TSI_GCTL_GE0 BIT(0) /*!< group0 enable */ -#define TSI_GCTL_GE1 BIT(1) /*!< group1 enable */ -#define TSI_GCTL_GE2 BIT(2) /*!< group2 enable */ -#define TSI_GCTL_GE3 BIT(3) /*!< group3 enable */ -#define TSI_GCTL_GE4 BIT(4) /*!< group4 enable */ -#define TSI_GCTL_GE5 BIT(5) /*!< group5 enable */ -#define TSI_GCTL_GC0 BIT(16) /*!< group0 complete */ -#define TSI_GCTL_GC1 BIT(17) /*!< group1 complete */ -#define TSI_GCTL_GC2 BIT(18) /*!< group2 complete */ -#define TSI_GCTL_GC3 BIT(19) /*!< group3 complete */ -#define TSI_GCTL_GC4 BIT(20) /*!< group4 complete */ -#define TSI_GCTL_GC5 BIT(21) /*!< group5 complete */ - -/* TSI_CTL1 */ -#define TSI_CTL1_CTCDIV BIT(24) /*!< CTCLK clock division factor */ -#define TSI_CTL1_ECDIV BITS(28,29) /*!< ECCLK clock division factor */ - -/* constants definitions */ -/* TSI interrupt enable bit */ -#define TSI_INT_CCTCF TSI_INTEN_CTCFIE /*!< charge transfer complete flag interrupt enable */ -#define TSI_INT_MNERR TSI_INTEN_MNERRIE /*!< max cycle number error interrupt enable */ - -/* I2C interrupt flags */ -#define TSI_INT_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ -#define TSI_INT_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ - -/* I2C interrupt clear flags */ -#define TSI_INT_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */ -#define TSI_INT_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */ - -/* I2C flags */ -#define TSI_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */ -#define TSI_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */ - -/* I2C clear flags */ -#define TSI_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */ -#define TSI_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */ - -/* CTCLK clock division factor */ -#define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */ -#define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */ -#define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */ -#define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */ -#define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */ -#define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */ -#define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */ -#define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */ -#define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */ -#define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */ -#define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */ -#define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */ -#define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */ -#define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */ -#define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */ -#define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */ - -/* charge transfer state duration Time */ -#define CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) -#define TSI_TRANSFER_1CTCLK CTL_CTDT(0) /*!< the duration time of transfer state is 1 CTCLK */ -#define TSI_TRANSFER_2CTCLK CTL_CTDT(1) /*!< the duration time of transfer state is 2 CTCLK */ -#define TSI_TRANSFER_3CTCLK CTL_CTDT(2) /*!< the duration time of transfer state is 3 CTCLK */ -#define TSI_TRANSFER_4CTCLK CTL_CTDT(3) /*!< the duration time of transfer state is 4 CTCLK */ -#define TSI_TRANSFER_5CTCLK CTL_CTDT(4) /*!< the duration time of transfer state is 5 CTCLK */ -#define TSI_TRANSFER_6CTCLK CTL_CTDT(5) /*!< the duration time of transfer state is 6 CTCLK */ -#define TSI_TRANSFER_7CTCLK CTL_CTDT(6) /*!< the duration time of transfer state is 7 CTCLK */ -#define TSI_TRANSFER_8CTCLK CTL_CTDT(7) /*!< the duration time of transfer state is 8 CTCLK */ -#define TSI_TRANSFER_9CTCLK CTL_CTDT(8) /*!< the duration time of transfer state is 9 CTCLK */ -#define TSI_TRANSFER_10CTCLK CTL_CTDT(9) /*!< the duration time of transfer state is 10 CTCLK */ -#define TSI_TRANSFER_11CTCLK CTL_CTDT(10) /*!< the duration time of transfer state is 11 CTCLK */ -#define TSI_TRANSFER_12CTCLK CTL_CTDT(11) /*!< the duration time of transfer state is 12 CTCLK */ -#define TSI_TRANSFER_13CTCLK CTL_CTDT(12) /*!< the duration time of transfer state is 13 CTCLK */ -#define TSI_TRANSFER_14CTCLK CTL_CTDT(13) /*!< the duration time of transfer state is 14 CTCLK */ -#define TSI_TRANSFER_15CTCLK CTL_CTDT(14) /*!< the duration time of transfer state is 15 CTCLK */ -#define TSI_TRANSFER_16CTCLK CTL_CTDT(15) /*!< the duration time of transfer state is 16 CTCLK */ - -/* charge state duration time */ -#define CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U)) -#define TSI_CHARGE_1CTCLK CTL_CDT(0) /*!< the duration time of charge state is 1 CTCLK */ -#define TSI_CHARGE_2CTCLK CTL_CDT(1) /*!< the duration time of charge state is 2 CTCLK */ -#define TSI_CHARGE_3CTCLK CTL_CDT(2) /*!< the duration time of charge state is 3 CTCLK */ -#define TSI_CHARGE_4CTCLK CTL_CDT(3) /*!< the duration time of charge state is 4 CTCLK */ -#define TSI_CHARGE_5CTCLK CTL_CDT(4) /*!< the duration time of charge state is 5 CTCLK */ -#define TSI_CHARGE_6CTCLK CTL_CDT(5) /*!< the duration time of charge state is 6 CTCLK */ -#define TSI_CHARGE_7CTCLK CTL_CDT(6) /*!< the duration time of charge state is 7 CTCLK */ -#define TSI_CHARGE_8CTCLK CTL_CDT(7) /*!< the duration time of charge state is 8 CTCLK */ -#define TSI_CHARGE_9CTCLK CTL_CDT(8) /*!< the duration time of charge state is 9 CTCLK */ -#define TSI_CHARGE_10CTCLK CTL_CDT(9) /*!< the duration time of charge state is 10 CTCLK */ -#define TSI_CHARGE_11CTCLK CTL_CDT(10) /*!< the duration time of charge state is 11 CTCLK */ -#define TSI_CHARGE_12CTCLK CTL_CDT(11) /*!< the duration time of charge state is 12 CTCLK */ -#define TSI_CHARGE_13CTCLK CTL_CDT(12) /*!< the duration time of charge state is 13 CTCLK */ -#define TSI_CHARGE_14CTCLK CTL_CDT(13) /*!< the duration time of charge state is 14 CTCLK */ -#define TSI_CHARGE_15CTCLK CTL_CDT(14) /*!< the duration time of charge state is 15 CTCLK */ -#define TSI_CHARGE_16CTCLK CTL_CDT(15) /*!< the duration time of charge state is 16 CTCLK */ - -/* max cycle number of a sequence */ -#define CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U)) -#define TSI_MAXNUM255 CTL_MCN(0) /*!< the max cycle number of a sequence is 255 */ -#define TSI_MAXNUM511 CTL_MCN(1) /*!< the max cycle number of a sequence is 511 */ -#define TSI_MAXNUM1023 CTL_MCN(2) /*!< the max cycle number of a sequence is 1023 */ -#define TSI_MAXNUM2047 CTL_MCN(3) /*!< the max cycle number of a sequence is 2047 */ -#define TSI_MAXNUM4095 CTL_MCN(4) /*!< the max cycle number of a sequence is 4095 */ -#define TSI_MAXNUM8191 CTL_MCN(5) /*!< the max cycle number of a sequence is 8191 */ -#define TSI_MAXNUM16383 CTL_MCN(6) /*!< the max cycle number of a sequence is 16383 */ - -/* ECCLK clock division factor */ -#define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */ -#define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */ -#define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */ -#define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */ -#define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */ -#define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */ -#define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */ -#define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */ - -/* extend charge state maximum duration time */ -#define TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */ - -/* hardware trigger mode */ -#define TSI_FALLING_TRIGGER 0x00U /*!< falling edge trigger TSI charge transfer sequence */ -#define TSI_RISING_TRIGGER 0x01U /*!< rising edge trigger TSI charge transfer sequence */ - -/* pin mode */ -#define TSI_OUTPUT_LOW 0x00U /*!< TSI pin will output low when IDLE */ -#define TSI_INPUT_FLOATING 0x01U /*!< TSI pin will keep input_floating when IDLE */ - -/* function declarations */ -/* reset TSI peripheral */ -void tsi_deinit(void); -/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */ -void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number); -/* enable TSI module */ -void tsi_enable(void); -/* disable TSI module */ -void tsi_disable(void); -/* enable sample pin */ -void tsi_sample_pin_enable(uint32_t sample); -/* disable sample pin */ -void tsi_sample_pin_disable(uint32_t sample); -/* enable channel pin */ -void tsi_channel_pin_enable(uint32_t channel); -/* disable channel pin */ -void tsi_channel_pin_disable(uint32_t channel); - -/* configure TSI triggering by software */ -void tsi_sofeware_mode_config(void); -/* start a charge-transfer sequence when TSI is in software trigger mode */ -void tsi_software_start(void); -/* stop a charge-transfer sequence when TSI is in software trigger mode */ -void tsi_software_stop(void); -/* configure TSI triggering by hardware */ -void tsi_hardware_mode_config(uint8_t trigger_edge); -/* configure TSI pin mode when charge-transfer sequence is IDLE */ -void tsi_pin_mode_config(uint8_t pin_mode); -/* configure extend charge state */ -void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration); - -/* configure charge plus and transfer plus */ -void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration); -/* configure the max cycle number of a charge-transfer sequence */ -void tsi_max_number_config(uint32_t max_number); -/* switch on hysteresis pin */ -void tsi_hysteresis_on(uint32_t group_pin); -/* switch off hysteresis pin */ -void tsi_hysteresis_off(uint32_t group_pin); -/* switch on analog pin */ -void tsi_analog_on(uint32_t group_pin); -/* switch off analog pin */ -void tsi_analog_off(uint32_t group_pin); - -/* enable TSI interrupt */ -void tsi_interrupt_enable(uint32_t source); -/* disable TSI interrupt */ -void tsi_interrupt_disable(uint32_t source); -/* clear interrupt flag */ -void tsi_interrupt_flag_clear(uint32_t flag); -/* get TSI interrupt flag */ -FlagStatus tsi_interrupt_flag_get(uint32_t flag); - -/* clear flag */ -void tsi_flag_clear(uint32_t flag); -/* get flag */ -FlagStatus tsi_flag_get(uint32_t flag); - -/* enbale group */ -void tsi_group_enable(uint32_t group); -/* disbale group */ -void tsi_group_disable(uint32_t group); -/* get group complete status */ -FlagStatus tsi_group_status_get(uint32_t group); -/* get the cycle number for group0 as soon as a charge-transfer sequence completes */ -uint16_t tsi_group0_cycle_get(void); -/* get the cycle number for group1 as soon as a charge-transfer sequence completes */ -uint16_t tsi_group1_cycle_get(void); -/* get the cycle number for group2 as soon as a charge-transfer sequence completes */ -uint16_t tsi_group2_cycle_get(void); -/* get the cycle number for group3 as soon as a charge-transfer sequence completes */ -uint16_t tsi_group3_cycle_get(void); -/* get the cycle number for group4 as soon as a charge-transfer sequence completes */ -uint16_t tsi_group4_cycle_get(void); -/* get the cycle number for group5 as soon as a charge-transfer sequence completes */ -uint16_t tsi_group5_cycle_get(void); - -#endif /* GD32F3X0_TSI_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h deleted file mode 100644 index fb06b818de..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_usart.h +++ /dev/null @@ -1,595 +0,0 @@ -/*! - \file gd32f3x0_usart.h - \brief definitions for the USART - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_USART_H -#define GD32F3X0_USART_H - -#include "gd32f3x0.h" - -/* USARTx(x=0,1) definitions */ -#define USART0 (USART_BASE + 0x0000F400U) -#define USART1 USART_BASE - -/* registers definitions */ -#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ -#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ -#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ -#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ -#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ -#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ -#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ -#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ -#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ -#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ - -/* bits definitions */ -/* USARTx_CTL0 */ -#define USART_CTL0_UEN BIT(0) /*!< USART enable */ -#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */ -#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */ -#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ -#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */ -#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */ -#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */ -#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ -#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ -#define USART_CTL1_CPH BIT(9) /*!< clock phase */ -#define USART_CTL1_CPL BIT(10) /*!< clock polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ -#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ -#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ -#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ -#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ -#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ -#define USART_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */ -#define USART_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */ -#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ -#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ -#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ -#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */ -#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ -#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */ -#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */ -#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ -#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ -#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ - -/* USARTx_CMD */ -#define USART_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */ -#define USART_CMD_SBKCMD BIT(1) /*!< send break command */ -#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ -#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ -#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ - -/* USARTx_STAT */ -#define USART_STAT_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ -#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT_TC BIT(6) /*!< transmission completed */ -#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ -#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ -#define USART_STAT_CTS BIT(10) /*!< CTS level */ -#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT_ABDE BIT(14) /*!< auto baudrate detection error */ -#define USART_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */ -#define USART_STAT_BSY BIT(16) /*!< busy flag */ -#define USART_STAT_AMF BIT(17) /*!< address match flag */ -#define USART_STAT_SBF BIT(18) /*!< send break flag */ -#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ -#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ -#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ -#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ - -/* USARTx_INTC */ -#define USART_INTC_PEC BIT(0) /*!< parity error clear */ -#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */ -#define USART_INTC_NEC BIT(2) /*!< noise detected clear */ -#define USART_INTC_OREC BIT(3) /*!< overrun error clear */ -#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */ -#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */ -#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */ -#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */ -#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */ -#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */ -#define USART_INTC_AMC BIT(17) /*!< address match clear */ -#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ - -/* USARTx_RDATA */ -#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ - -/* USARTx_TDATA */ -#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ - -/* USARTx_RFCS */ -#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ -#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */ -#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */ -#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ -#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ -#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ -#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ - -/* constants definitions */ - -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) - -/* register offset */ -#define USART_CTL0_REG_OFFSET (0x00000000U) /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET (0x00000008U) /*!< CTL2 register offset */ -#define USART_STAT_REG_OFFSET (0x0000001CU) /*!< STAT register offset */ -#define USART_RFCS_REG_OFFSET (0x000000D0U) /*!< RFCS register offset */ - -/* USART flags */ -typedef enum{ - /* flags in STAT register */ - USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ - USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ - USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode flag */ - USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ - USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ - USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ - USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */ - USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */ - USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ - USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ - USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ - /* flags in RFCS register */ - USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ - USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt flag */ - USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt flag */ - USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt flag */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt flag */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt flag */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< noise error interrupt flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< overrun error interrupt flag */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< frame error interrupt flag */ - /* interrupt flags in RFCS register */ - USART_INT_FLAG_RFFINT = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ - USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ - USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ - /* interrupt in RFCS register */ - USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ -}usart_interrupt_enum; - -/* USART invert configure */ -typedef enum { - /* data bit level inversion */ - USART_DINV_ENABLE, /*!< data bit level inversion */ - USART_DINV_DISABLE, /*!< data bit level not inversion */ - /* TX pin level inversion */ - USART_TXPIN_ENABLE, /*!< TX pin level inversion */ - USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ - /* RX pin level inversion */ - USART_RXPIN_ENABLE, /*!< RX pin level inversion */ - USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ - /* swap TX/RX pins */ - USART_SWAP_ENABLE, /*!< swap TX/RX pins */ - USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ -}usart_invert_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART oversample mode */ -#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ -#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ - -/* USART address detection mode */ -#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) -#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ -#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ - -/* USART last bit clock pulse */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART data is transmitted/received with the LSB/MSB first */ -#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) -#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ -#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ - -/* USART auto baud rate detection mode bits definitions */ -#define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) -#define USART_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */ -#define USART_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* DMA enable for reception */ -#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */ -#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */ - -/* DMA enable for transmission */ -#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */ -#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */ - -/* USART RTS hardware flow control configure */ -#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */ -#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */ - -/* USART CTS hardware flow control configure */ -#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */ -#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */ - -/* USART one sample bit method configure */ -#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ -#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ - -/* USART driver enable polarity mode */ -#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ -#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ - -/* USART wakeup mode from deep-sleep mode */ -#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ -#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ -#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); - -/* USART normal mode communication */ -/* data is transmitted/received with the LSB/MSB first */ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); -/* configure USART inverted */ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); -/* enable the USART overrun function */ -void usart_overrun_enable(uint32_t usart_periph); -/* disable the USART overrun function */ -void usart_overrun_disable(uint32_t usart_periph); -/* configure the USART oversample mode */ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); -/* configure sample bit method */ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); -/* enable receiver timeout */ -void usart_receiver_timeout_enable(uint32_t usart_periph); -/* disable receiver timeout */ -void usart_receiver_timeout_disable(uint32_t usart_periph); -/* configure receiver timeout threshold */ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* auto baud rate detection */ -/* enable auto baud rate detection */ -void usart_autobaud_detection_enable(uint32_t usart_periph); -/* disable auto baud rate detection */ -void usart_autobaud_detection_disable(uint32_t usart_periph); -/* configure auto baud rate detection mode */ -void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod); - -/* multi-processor communication */ -/* configure the address of the USART in wake up by address match mode */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* configure address detection mode */ -void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* enable LIN mode */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* disable LIN mode */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* configure LIN break frame length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); - -/* half-duplex communication */ -/* enable half-duplex mode */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* disable half-duplex mode */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* enable USART clock */ -void usart_clock_enable(uint32_t usart_periph); -/* disable USART clock */ -void usart_clock_disable(uint32_t usart_periph); -/* configure USART synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); -/* enable smartcard mode */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* disable smartcard mode */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* enable NACK in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* disable NACK in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* enable early NACK in smartcard mode */ -void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); -/* disable early NACK in smartcard mode */ -void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); -/* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler in USART IrDA low-power mode or SmartCard mode */ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* enable RS485 driver */ -void usart_rs485_driver_enable(uint32_t usart_periph); -/* disable RS485 driver */ -void usart_rs485_driver_disable(uint32_t usart_periph); -/* configure driver enable assertion time */ -void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); -/* configure driver enable de-assertion time */ -void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); -/* configure driver enable polarity mode */ -void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); - -/* USART DMA */ -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); -/* disable DMA on reception error */ -void usart_reception_error_dma_disable(uint32_t usart_periph); -/* enable DMA on reception error */ -void usart_reception_error_dma_enable(uint32_t usart_periph); - -/* enable USART to wakeup the mcu from deep-sleep mode */ -void usart_wakeup_enable(uint32_t usart_periph); -/* disable USART to wakeup the mcu from deep-sleep mode */ -void usart_wakeup_disable(uint32_t usart_periph); -/* configure the USART wakeup mode from deep-sleep mode */ -void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); -/* enable USART command */ -void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); - -/* USART receive FIFO */ -/* enable receive FIFO */ -void usart_receive_fifo_enable(uint32_t usart_periph); -/* disable receive FIFO */ -void usart_receive_fifo_disable(uint32_t usart_periph); -/* read receive FIFO counter number */ -uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); - -/* flag & interrupt functions */ -/* get flag in STAT/RFCS register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT register */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -/* clear USART interrupt flag */ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); - -#endif /* GD32F3X0_USART_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h deleted file mode 100644 index 9905fa75c1..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Include/gd32f3x0_wwdgt.h +++ /dev/null @@ -1,93 +0,0 @@ -/*! - \file gd32f3x0_wwdgt.h - \brief definitions for the WWDGT - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_WWDGT_H -#define GD32F3X0_WWDGT_H - -#include "gd32f3x0.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE - -/* registers definitions */ -#define WWDGT_CTL REG32(WWDGT + 0x00000000U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32(WWDGT + 0x00000004U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32(WWDGT + 0x00000008U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ - -/* constants definitions */ -/* WWDGT_CTL register value */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */ - -/* WWDGT_CFG register value */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */ - -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32F3X0_WWDGT_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c deleted file mode 100644 index 490f3f9663..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_adc.c +++ /dev/null @@ -1,869 +0,0 @@ -/*! - \file gd32f3x0_adc.c - \brief ADC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_adc.h" - -/*! - \brief reset ADC - \param[in] none - \param[out] none - \retval none -*/ -void adc_deinit(void) -{ - rcu_periph_reset_enable(RCU_ADCRST); - rcu_periph_reset_disable(RCU_ADCRST); -} - -/*! - \brief enable ADC interface - \param[in] none - \param[out] none - \retval none -*/ -void adc_enable(void) -{ - if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){ - ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] none - \param[out] none - \retval none -*/ -void adc_disable(void) -{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] none - \param[out] none - \retval none -*/ -void adc_calibration_enable(void) -{ - /* reset the selected ADC calibration register */ - ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while((ADC_CTL1 & ADC_CTL1_RSTCLB)){ - } - - /* enable ADC calibration process */ - ADC_CTL1 |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while((ADC_CTL1 & ADC_CTL1_CLB)){ - } -} - -/*! - \brief enable DMA request - \param[in] none - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(void) -{ - ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] none - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(void) -{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1 |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1 &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief enable the vbat channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_vbat_enable(void) -{ - /* enable the vbat channel */ - ADC_CTL1 |= ADC_CTL1_VBETEN; -} - -/*! - \brief disable the vbat channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_vbat_disable(void) -{ - /* disable the vbat channel */ - ADC_CTL1 &= ~ADC_CTL1_VBETEN; -} - -/*! - \brief configure ADC discontinuous mode - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel, the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length) -{ - ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure the number of conversions in discontinuous mode */ - ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U)); - ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - default: - break; - } -} - -/*! - \brief configure ADC special function - \param[in] function: the function to configure - one or more parameters can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t function, ControlStatus newvalue) -{ - if(newvalue){ - /* enable ADC scan mode */ - if(RESET != (function & ADC_SCAN_MODE)){ - ADC_CTL0 |= ADC_SCAN_MODE; - } - /* enable ADC inserted channel group convert automatically */ - if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ - ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO; - } - /* enable ADC continuous mode */ - if(RESET != (function & ADC_CONTINUOUS_MODE)){ - ADC_CTL1 |= ADC_CONTINUOUS_MODE; - } - }else{ - /* disable ADC scan mode */ - if(RESET != (function & ADC_SCAN_MODE)){ - ADC_CTL0 &= ~ADC_SCAN_MODE; - } - /* disable ADC inserted channel group convert automatically */ - if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ - ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO; - } - /* disable ADC continuous mode */ - if(RESET != (function & ADC_CONTINUOUS_MODE)){ - ADC_CTL1 &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: right alignment - \arg ADC_DATAALIGN_LEFT: left alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment){ - ADC_CTL1 |= ADC_CTL1_DAL; - }else{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint8_t channel_group, uint32_t length) -{ - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure the length of regular channel group */ - ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U)); - break; - case ADC_INSERTED_CHANNEL: - /* configure the length of inserted channel group */ - ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ |= ISQ_IL((uint32_t)(length-1U)); - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] rank: the regular group sequence rank, this parameter must be between 0 to 15 - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* configure ADC regular sequence */ - if(rank < 6U){ - rsq = ADC_RSQ2; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); - rsq |= ((uint32_t)channel << (5U*rank)); - ADC_RSQ2 = rsq; - }else if(rank < 12U){ - rsq = ADC_RSQ1; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); - rsq |= ((uint32_t)channel << (5U*(rank-6U))); - ADC_RSQ1 = rsq; - }else if(rank < 16U){ - rsq = ADC_RSQ0; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); - rsq |= ((uint32_t)channel << (5U*(rank-12U))); - ADC_RSQ0 = rsq; - }else{ - } - - /* configure ADC sampling time */ - if(channel < 10U){ - sampt = ADC_SAMPT1; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel))); - sampt |= (uint32_t)(sample_time << (3U*channel)); - ADC_SAMPT1 = sampt; - }else if(channel < 19U){ - sampt = ADC_SAMPT0; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U)))); - sampt |= (uint32_t)(sample_time << (3U*(channel-10U))); - ADC_SAMPT0 = sampt; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ , 20U , 21U); - - isq = ADC_ISQ; - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U))); - isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U)); - ADC_ISQ = isq; - - /* configure ADC sampling time */ - if(channel < 10U){ - sampt = ADC_SAMPT1; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel))); - sampt |= (uint32_t) sample_time << (3U*channel); - ADC_SAMPT1 = sampt; - }else if(channel < 19U){ - sampt = ADC_SAMPT0; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U)))); - sampt |= ((uint32_t)sample_time << (3U*(channel - 10U))); - ADC_SAMPT0 = sampt; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] inserted_channel: insert channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 - \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 - \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 - \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 - \param[in] offset: the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); - num = 3U - (inserted_length - inserted_channel); - - if(num <= 3U){ - /* calculate the offset of the register */ - num = num * 4U; - /* configure the offset of the selected channels */ - REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief enable or disable ADC external trigger - \param[in] channel_group: select the channel group - one or more parameters can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue) -{ - if(newvalue){ - /* external trigger enable for regular channel */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_ETERC; - } - /* external trigger enable for inserted channel */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_ETEIC; - } - }else{ - /* external trigger disable for regular channel */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1 &= ~ADC_CTL1_ETERC; - } - /* external trigger disable for inserted channel */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1 &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief configure ADC external trigger source - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected which is shown as below: - for regular channel: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select - \arg ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select - \arg ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select - \arg ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select - \arg ADC_EXTTRIG_REGULAR_T14_CH0: TIMER14 CH0 event select - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 - \arg ADC_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select - \arg ADC_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select - \arg ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select - \arg ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source) -{ - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - /* external trigger select for regular channel */ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1 |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* external trigger select for inserted channel */ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1 |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief enable ADC software trigger - \param[in] channel_group: select the channel group - one or more parameters can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint8_t channel_group) -{ - /* enable regular group channel software trigger */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_SWRCST; - } - /* enable inserted channel group software trigger */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(void) -{ - return ((uint16_t)ADC_RDATA); -} - -/*! - \brief read ADC inserted group data register - \param[in] inserted_channel: inserted channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 - \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 - \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 - \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - idata = ADC_IDATA0; - break; - case ADC_INSERTED_CHANNEL_1: - idata = ADC_IDATA1; - break; - case ADC_INSERTED_CHANNEL_2: - idata = ADC_IDATA2; - break; - case ADC_INSERTED_CHANNEL_3: - idata = ADC_IDATA3; - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief get the ADC flag bits - \param[in] flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t flag) -{ - FlagStatus reval = RESET; - - if(ADC_STAT & flag){ - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag - \param[in] flag: the adc flag - one or more parameters can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t flag) -{ - ADC_STAT &= ~((uint32_t)flag); -} - -/*! - \brief get the ADC interrupt flag - \param[in] flag: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t flag) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - - /* check the interrupt bits */ - switch(flag){ - case ADC_INT_FLAG_WDE: - state = ADC_STAT & ADC_STAT_WDE; - if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - state = ADC_STAT & ADC_STAT_EOC; - if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - state = ADC_STAT & ADC_STAT_EOIC; - if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear ADC interrupt flag - \param[in] flag: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t flag) -{ - ADC_STAT &= ~((uint32_t)flag); -} - -/*! - \brief enable ADC interrupt - \param[in] interrupt: the adc interrupt - one or more parameters can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t interrupt) -{ - /* enable analog watchdog interrupt */ - if(RESET != (interrupt & ADC_INT_WDE)){ - ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE; - } - - /* enable end of group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOC)){ - ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE; - } - - /* enable end of inserted group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOIC)){ - ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] interrupt: the adc interrupt flag - one or more parameters can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t interrupt) -{ - /* disable analog watchdog interrupt */ - if(RESET != (interrupt & ADC_INT_WDE)){ - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE; - } - - /* disable end of group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOC)){ - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE; - } - - /* disable end of inserted group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOIC)){ - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE; - } -} - -/*! - \brief configure ADC analog watchdog single channel - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint8_t channel) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - - ADC_CTL0 |= (uint32_t)channel; - ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint8_t channel_group) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - - /* select the group */ - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] none - \param[out] none - \retval none -*/ -void adc_watchdog_disable(void) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] low_threshold: analog watchdog low threshold,0..4095 - \param[in] high_threshold: analog watchdog high threshold,0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold) -{ - ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold); -} - -/*! - \brief configure ADC resolution - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t resolution) -{ - ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES); - ADC_CTL0 |= (uint32_t)resolution; -} - -/*! - \brief configure ADC oversample mode - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio) -{ - /* configure ADC oversampling mode */ - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ - ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ - ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); - } - - /* configure the shift and ratio */ - ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief enable ADC oversample mode - \param[in] none - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(void) -{ - ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN; -} - -/*! - \brief disable ADC oversample mode - \param[in] none - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(void) -{ - ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c deleted file mode 100644 index 42b0d50253..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cec.c +++ /dev/null @@ -1,499 +0,0 @@ -/*! - \file gd32f3x0_cec.c - \brief CEC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifdef GD32F350 - -#include "gd32f3x0_cec.h" - -/*! - \brief reset HDMI-CEC controller - \param[in] none - \param[out] none - \retval none -*/ -void cec_deinit(void) -{ - rcu_periph_reset_enable(RCU_CECRST); - rcu_periph_reset_disable(RCU_CECRST); -} - -/*! - \brief configure signal free time,the signal free time counter start option,own address - \param[in] sftmopt: signal free time counter start option - only one parameter can be selected which is shown as below: - \arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted - \arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end - \param[in] sft: signal free time - only one parameter can be selected which is shown as below: - \arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description - \arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods - \arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods - \arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods - \arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods - \arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods - \arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods - \arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods - \param[in] address: own address - only one parameter can be selected which is shown as below: - \arg CEC_OWN_ADDRESS_CLEAR: own address is cleared - \arg CEC_OWN_ADDRESSx(x=0..14): own address is x - \param[out] none - \retval none -*/ -void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address) -{ - uint32_t cfg; - cfg = CEC_CFG; - /* clear SFTMOPT bit,SFT[2:0] */ - cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT); - /* assign SFTMOPT bit,SFT[2:0] */ - cfg |= (sftmopt | sft); - CEC_CFG = cfg; - if(CEC_OWN_ADDRESS_CLEAR == address){ - CEC_CFG &= ~CEC_CFG_OWN_ADDRESS; - }else{ - CEC_CFG |= address; - } -} - -/*! - \brief configure generate Error-bit when detected some abnormal situation or not, - whether stop receive message when detected bit rising error - \param[in] broadcast: - only one parameter can be selected which is shown as below: - \arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast - \arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast - \param[in] singlecast_lbpe: - only one parameter can be selected which is shown as below: - \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error - \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error - \param[in] singlecast_bre: - only one parameter can be selected which is shown as below: - \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error - \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error - \param[in] rxbrestp: - only one parameter can be selected which is shown as below: - \arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error - \arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error - \param[out] none - \retval none -*/ -void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp) -{ - uint32_t cfg; - cfg = CEC_CFG; - /* clear BCNG bit, BPLEG bit, BREG bit */ - cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG); - /* assign BCNG bit, BPLEG bit, BREG bit */ - cfg |= (broadcast | singlecast_lbpe | singlecast_bre); - CEC_CFG = cfg; - if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){ - CEC_CFG |= CEC_CFG_BRES; - }else{ - CEC_CFG &= ~CEC_CFG_BRES; - } -} - -/*! - \brief enable HDMI-CEC controller - \param[in] none - \param[out] none - \retval none -*/ -void cec_enable(void) -{ - CEC_CTL |= CEC_CTL_CECEN; -} - -/*! - \brief disable HDMI-CEC controller - \param[in] none - \param[out] none - \retval none -*/ -void cec_disable(void) -{ - CEC_CTL &= ~CEC_CTL_CECEN; -} - -/*! - \brief start CEC message transmission - \param[in] none - \param[out] none - \retval none -*/ -void cec_transmission_start(void) -{ - CEC_CTL |= CEC_CTL_STAOM; -} - -/*! - \brief end CEC message transmission - \param[in] none - \param[out] none - \retval none -*/ -void cec_transmission_end(void) -{ - CEC_CTL |= CEC_CTL_ENDOM; -} - -/*! - \brief enable CEC listen mode. - \param[in] none - \param[out] none - \retval none -*/ -void cec_listen_mode_enable(void) -{ - CEC_CFG |= CEC_CFG_LMEN; -} - -/*! - \brief disable CEC listen mode. - \param[in] none - \param[out] none - \retval none -*/ -void cec_listen_mode_disable(void) -{ - CEC_CFG &= ~CEC_CFG_LMEN; -} - -/*! - \brief configure and clear own address.the controller can be configured to multiple own address - \param[in] address: own address - one or more parameters can be selected which are shown as below: - \arg CEC_OWN_ADDRESS_CLEAR: own address is cleared - \arg CEC_OWN_ADDRESSx(x=0..14): own address is x - \param[out] none - \retval none -*/ -void cec_own_address_config(uint32_t address) -{ - if(CEC_OWN_ADDRESS_CLEAR == address){ - CEC_CFG &= ~CEC_CFG_OWN_ADDRESS; - } else { - CEC_CFG |= address; - } -} - -/*! - \brief configure signal free time and the signal free time counter start option - \param[in] sftmopt: signal free time counter start option - only one parameter can be selected which is shown as below: - \arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted - \arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end - \param[in] sft: signal free time - only one parameter can be selected which is shown as below: - \arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description - \arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods - \arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods - \arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods - \arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods - \arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods - \arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods - \arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods - \param[out] none - \retval none -*/ -void cec_sft_config(uint32_t sftmopt, uint32_t sft) -{ - uint32_t cfg; - cfg = CEC_CFG; - /* clear SFTMOPT bit,SFT[2:0] */ - cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT); - /* assign SFTMOPT bit,SFT[2:0] */ - cfg |= (sftmopt | sft); - CEC_CFG = cfg; -} - -/*! - \brief configure generate Error-bit when detected some abnormal situation or not - \param[in] broadcast: - only one parameter can be selected which is shown as below: - \arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast - \arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast - \param[in] singlecast_lbpe: - only one parameter can be selected which is shown as below: - \arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error - \arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error - \param[in] singlecast_bre: - only one parameter can be selected which is shown as below: - \arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error - \arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error - \param[out] none - \retval none -*/ -void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre) -{ - uint32_t cfg; - cfg = CEC_CFG; - /* clear BCNG bit, RLBPEGEN bit, RBREGEN bit */ - cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG); - /* assign BCNG bit, RLBPEGEN bit, RBREGEN bit */ - cfg |= (broadcast | singlecast_lbpe | singlecast_bre); - CEC_CFG = cfg; -} - -/*! - \brief whether stop receive message when detected bit rising error - \param[in] rxbrestp: - only one parameter can be selected which is shown as below: - \arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error - \arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error - \param[out] none - \retval none -*/ -void cec_stop_receive_bre_config(uint32_t rxbrestp) -{ - if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){ - CEC_CFG |= CEC_CFG_BRES; - } else { - CEC_CFG &= ~CEC_CFG_BRES; - } -} - -/*! - \brief enable reception bit timing tolerance - \param[in] none - \param[out] none - \retval none -*/ -void cec_reception_tolerance_enable(void) -{ - CEC_CFG |= CEC_CFG_RTOL; -} - -/*! - \brief disable reception bit timing tolerance - \param[in] none - \param[out] none - \retval none -*/ -void cec_reception_tolerance_disable(void) -{ - CEC_CFG &= ~CEC_CFG_RTOL; -} - -/*! - \brief send a data by the CEC peripheral - \param[in] data: the data to transmit - \param[out] none - \retval none -*/ -void cec_data_send(uint8_t data) -{ - CEC_TDATA = (uint32_t)data; -} - -/*! - \brief receive a data by the CEC peripheral - \param[in] data: the data to receive - \param[out] none - \retval none -*/ -uint8_t cec_data_receive(void) -{ - return (uint8_t)CEC_RDATA; -} - - -/*! - \brief enable interrupt - \param[in] flag: specify which flag - one or more parameters can be selected which are shown as below: - \arg CEC_INT_BR: enable Rx-byte data received interrupt - \arg CEC_INT_REND: enable end of reception interrupt - \arg CEC_INT_RO: enable RX overrun interrupt - \arg CEC_INT_BRE: enable bit rising error interrupt - \arg CEC_INT_BPSE: enable short bit period error interrupt - \arg CEC_INT_BPLE: enable long bit period error interrupt - \arg CEC_INT_RAE: enable Rx ACK error interrupt - \arg CEC_INT_ARBF: enable arbitration lost interrupt - \arg CEC_INT_TBR: enable Tx-byte data request interrupt - \arg CEC_INT_TEND: enable transmission successfully end interrupt - \arg CEC_INT_TU: enable Tx data buffer underrun interrupt - \arg CEC_INT_TERR: enable Tx-error interrupt - \arg CEC_INT_TAERR: enable Tx ACK error interrupt - \param[out] none - \retval none -*/ -void cec_interrupt_enable(uint32_t flag) -{ - CEC_INTEN |= flag; -} - -/*! - \brief disable interrupt - \param[in] flag: specify which flag - one or more parameters can be selected which are shown as below: - \arg CEC_INT_BR: disable Rx-byte data received interrupt - \arg CEC_INT_REND: disable end of reception interrupt - \arg CEC_INT_RO: disable RX overrun interrupt - \arg CEC_INT_BRE: disable bit rising error interrupt - \arg CEC_INT_BPSE: disable short bit period error interrupt - \arg CEC_INT_BPLE: disable long bit period error interrupt - \arg CEC_INT_RAE: disable Rx ACK error interrupt - \arg CEC_INT_ARBF: disable arbitration lost interrupt - \arg CEC_INT_TBR: disable Tx-byte data request interrupt - \arg CEC_INT_TEND: disable transmission successfully end interrupt - \arg CEC_INT_TU: disable Tx data buffer underrun interrupt - \arg CEC_INT_TERR: disable Tx-error interrupt - \arg CEC_INT_TAERR: disable Tx ACK error interrupt - - \param[out] none - \retval none -*/ -void cec_interrupt_disable(uint32_t flag) -{ - CEC_INTEN &= ~flag; -} - - -/*! - \brief get CEC status - \param[in] flag: specify which flag - one or more parameters can be selected which are shown as below: - \arg CEC_FLAG_BR: Rx-byte data received - \arg CEC_FLAG_REND: end of reception - \arg CEC_FLAG_RO: RX overrun - \arg CEC_FLAG_BRE: bit rising error - \arg CEC_FLAG_BPSE: short bit period error - \arg CEC_FLAG_BPLE: long bit period error - \arg CEC_FLAG_RAE: Rx ACK error - \arg CEC_FLAG_ARBF: arbitration lost - \arg CEC_FLAG_TBR: Tx-byte data request - \arg CEC_FLAG_TEND: transmission successfully end - \arg CEC_FLAG_TU: Tx data buffer underrun - \arg CEC_FLAG_TERR: Tx-error - \arg CEC_FLAG_TAERR Tx ACK error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus cec_flag_get(uint32_t flag) -{ - if(CEC_INTF & flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CEC status - \param[in] flag: specify which flag - one or more parameters can be selected which are shown as below: - \arg CEC_FLAG_BR: Rx-byte data received - \arg CEC_FLAG_REND: end of reception - \arg CEC_FLAG_RO: RX overrun - \arg CEC_FLAG_BRE: bit rising error - \arg CEC_FLAG_BPSE: short bit period error - \arg CEC_FLAG_BPLE: long bit period error - \arg CEC_FLAG_RAE: Rx ACK error - \arg CEC_FLAG_ARBF: arbitration lost - \arg CEC_FLAG_TBR: Tx-byte data request - \arg CEC_FLAG_TEND: transmission successfully end - \arg CEC_FLAG_TU: Tx data buffer underrun - \arg CEC_FLAG_TERR: Tx-error - \arg CEC_FLAG_TAERR: Tx ACK error flag - - \param[out] none - \retval FlagStatus: SET or RESET -*/ -void cec_flag_clear(uint32_t flag) -{ - CEC_INTF |= flag; -} - -/*! - \brief get CEC int flag and status - \param[in] flag: specify which flag - one or more parameters can be selected which are shown as below: - \arg CEC_INT_FLAG_BR: Rx-byte data received - \arg CEC_INT_FLAG_REND: end of reception - \arg CEC_INT_FLAG_RO: RX overrun - \arg CEC_INT_FLAG_BRE: bit rising error - \arg CEC_INT_FLAG_BPSE: short bit period error - \arg CEC_INT_FLAG_BPLE: long bit period error - \arg CEC_INT_FLAG_RAE: Rx ACK error - \arg CEC_INT_FLAG_ARBF: arbitration lost - \arg CEC_INT_FLAG_TBR: Tx-byte data request - \arg CEC_INT_FLAG_TEND: transmission successfully end - \arg CEC_INT_FLAG_TU: Tx data buffer underrun - \arg CEC_INT_FLAG_TERR: Tx-error - \arg CEC_INT_FLAG_TAERR: Tx ACK error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus cec_interrupt_flag_get(uint32_t flag) -{ - uint32_t interrupt_enable = 0U,interrupt_flag = 0U; - interrupt_flag = (CEC_INTF & flag); - interrupt_enable = (CEC_INTEN & flag); - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CEC int flag and status - \param[in] flag: specify which flag - one or more parameters can be selected which are shown as below: - \arg CEC_INT_FLAG_BR: Rx-byte data received - \arg CEC_INT_FLAG_REND: end of reception - \arg CEC_INT_FLAG_RO: RX overrun - \arg CEC_INT_FLAG_BRE: bit rising error - \arg CEC_INT_FLAG_BPSE: short bit period error - \arg CEC_INT_FLAG_BPLE: long bit period error - \arg CEC_INT_FLAG_RAE: Rx ACK error - \arg CEC_INT_FLAG_ARBF: arbitration lost - \arg CEC_INT_FLAG_TBR: Tx-byte data request - \arg CEC_INT_FLAG_TEND: transmission successfully end - \arg CEC_INT_FLAG_TU: Tx data buffer underrun - \arg CEC_INT_FLAG_TERR: Tx-error - \arg CEC_INT_FLAG_TAERR: Tx ACK error flag - \param[out] none - \retval none -*/ -void cec_interrupt_flag_clear(uint32_t flag) -{ - CEC_INTF = flag; -} - - -#endif diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c deleted file mode 100644 index 2a5d6c7922..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_cmp.c +++ /dev/null @@ -1,255 +0,0 @@ -/*! - \file gd32f3x0_cmp.c - \brief CMP driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_cmp.h" - -/*! - \brief deinitialize comparator - \param[in] none - \param[out] none - \retval none -*/ -void cmp_deinit(void) -{ - CMP_CS = ((uint32_t)0x00000000U); -} - -/*! - \brief initialize comparator mode - \param[in] cmp_periph - \arg CMP0: comparator 0 - \arg CMP1: comparator 1 - \param[in] operating_mode - \arg CMP_HIGHSPEED: high speed mode - \arg CMP_MIDDLESPEED: medium speed mode - \arg CMP_LOWSPEED: low speed mode - \arg CMP_VERYLOWSPEED: very-low speed mode - \param[in] inverting_input - \arg CMP_1_4VREFINT: VREFINT *1/4 input - \arg CMP_1_2VREFINT: VREFINT *1/2 input - \arg CMP_3_4VREFINT: VREFINT *3/4 input - \arg CMP_VREFINT: VREFINT input - \arg CMP_DAC: PA4 (DAC) input - \arg CMP_PA5: PA5 input - \arg CMP_PA_0_2: PA0 or PA2 input - \param[in] hysteresis - \arg CMP_HYSTERESIS_NO: output no hysteresis - \arg CMP_HYSTERESIS_LOW: output low hysteresis - \arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis - \arg CMP_HYSTERESIS_HIGH: output high hysteresis - \param[out] none - \retval none -*/ -void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis) -{ - if(CMP0 == cmp_periph){ - /* initialize comparator 0 mode */ - CMP_CS &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST ); - CMP_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis); - }else{ - /* initialize comparator 1 mode */ - CMP_CS &= ~(uint32_t)(CMP_CS_CMP1M | CMP_CS_CMP1MSEL | CMP_CS_CMP1HST ); - CMP_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis); - } -} - -/*! - \brief initialize comparator output - \param[in] cmp_periph - \arg CMP0: comparator 0 - \arg CMP1: comparator 1 - \param[in] output_slection - \arg CMP_OUTPUT_NONE: output no selection - \arg CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input - \arg CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture - \arg CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input - \arg CMP_OUTPUT_TIMER1IC3: TIMER 1 channel3 input capture - \arg CMP_OUTPUT_TIMER1OCPRECLR: TIMER 1 OCPRE_CLR input - \arg CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture - \arg CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input - \param[in] output_polarity - \arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted - \arg CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted - \param[out] none - \retval none -*/ -void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity) -{ - /* initialize comparator 0 output */ - if(CMP0 == cmp_periph){ - CMP_CS &= ~(uint32_t)CMP_CS_CMP0OSEL; - CMP_CS |= CS_CMP0OSEL(output_slection); - /* output polarity */ - if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){ - CMP_CS |= CMP_CS_CMP0PL; - }else{ - CMP_CS &= ~CMP_CS_CMP0PL; - } - }else{ - /* initialize comparator 1 output */ - CMP_CS &= ~(uint32_t)CMP_CS_CMP1OSEL; - CMP_CS |= CS_CMP1OSEL(output_slection); - /* output polarity */ - if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){ - CMP_CS |= CMP_CS_CMP1PL; - }else{ - CMP_CS &= ~CMP_CS_CMP1PL; - } - } -} - -/*! - \brief enable comparator - \param[in] cmp_periph - \arg CMP0: comparator 0 - \arg CMP1: comparator 1 - \param[out] none - \retval none -*/ -void cmp_enable(uint32_t cmp_periph) -{ - if(CMP0 == cmp_periph){ - CMP_CS |= CMP_CS_CMP0EN; - }else{ - CMP_CS |= CMP_CS_CMP1EN; - } -} - -/*! - \brief disable comparator - \param[in] cmp_periph - \arg CMP0: comparator 0 - \arg CMP1: comparator 1 - \param[out] none - \retval none -*/ -void cmp_disable(uint32_t cmp_periph) -{ - if(CMP0 == cmp_periph){ - CMP_CS &= ~CMP_CS_CMP0EN; - }else{ - CMP_CS &= ~CMP_CS_CMP1EN; - } -} - -/*! - \brief enable comparator switch - \param[in] none - \param[out] none - \retval none -*/ -void cmp_switch_enable(void) -{ - CMP_CS |= CMP_CS_CMP0SW; -} - -/*! - \brief disable comparator switch - \param[in] none - \param[out] none - \retval none -*/ -void cmp_switch_disable(void) -{ - CMP_CS &= ~CMP_CS_CMP0SW; -} - -/*! - \brief enable the window mode - \param[in] none - \param[out] none - \retval none -*/ -void cmp_window_enable(void) -{ - CMP_CS |= CMP_CS_WNDEN; -} - -/*! - \brief disable the window mode - \param[in] none - \param[out] none - \retval none -*/ -void cmp_window_disable(void) -{ - CMP_CS &= ~CMP_CS_WNDEN; -} - -/*! - \brief lock the comparator - \param[in] cmp_periph - \arg CMP0: comparator 0 - \arg CMP1: comparator 1 - \param[out] none - \retval none -*/ -void cmp_lock_enable(uint32_t cmp_periph) -{ - if(CMP0 == cmp_periph){ - /* lock CMP0 */ - CMP_CS |= CMP_CS_CMP0LK; - }else{ - /* lock CMP1 */ - CMP_CS |= CMP_CS_CMP1LK; - } -} - -/*! - \brief get output level - \param[in] cmp_periph - \arg CMP0: comparator 0 - \arg CMP1: comparator 1 - \param[out] none - \retval the output level -*/ -uint32_t cmp_output_level_get(uint32_t cmp_periph) -{ - if(CMP0 == cmp_periph){ - /* get output level of CMP0 */ - if(CMP_CS & CMP_CS_CMP0O){ - return CMP_OUTPUTLEVEL_HIGH; - }else{ - return CMP_OUTPUTLEVEL_LOW; - } - }else{ - /* get output level of CMP1 */ - if(CMP_CS & CMP_CS_CMP1O){ - return CMP_OUTPUTLEVEL_HIGH; - }else{ - return CMP_OUTPUTLEVEL_LOW; - } - } -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c deleted file mode 100644 index 4166723b28..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_crc.c +++ /dev/null @@ -1,207 +0,0 @@ -/*! - \file gd32f3x0_crc.c - \brief CRC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_crc.h" - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_IDATA = (uint32_t)0xFFFFFFFFU; - CRC_DATA = (uint32_t)0xFFFFFFFFU; - CRC_FDATA = (uint32_t)0x00000000U; - CRC_POLY = (uint32_t)0x04C11DB7U; - CRC_CTL = CRC_CTL_RST; -} - -/*! - \brief enable the reverse operation of output data - \param[in] none - \param[out] none - \retval none -*/ -void crc_reverse_output_data_enable(void) -{ - CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); - CRC_CTL |= (uint32_t)CRC_CTL_REV_O; -} - -/*! - \brief disable the reverse operation of output data - \param[in] none - \param[out] none - \retval none -*/ -void crc_reverse_output_data_disable(void) -{ - CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); -} - -/*! - \brief reset data register to the value of initializaiton data register - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write the free data register - \param[in] free_data: specify 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief write the initializaiton data register - \param[in] init_data:specify 32-bit data - \param[out] none - \retval none -*/ -void crc_init_data_register_write(uint32_t init_data) -{ - CRC_IDATA = (uint32_t)init_data; -} - -/*! - \brief configure the CRC input data function - \param[in] data_reverse: specify input data reverse function - only one parameter can be selected which is shown as below: - \arg CRC_INPUT_DATA_NOT: input data is not reversed - \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits - \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits - \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits - \param[out] none - \retval none -*/ -void crc_input_data_reverse_config(uint32_t data_reverse) -{ - CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I); - CRC_CTL |= (uint32_t)data_reverse; -} - -/*! - \brief configure the CRC size of polynomial function - \param[in] poly_size: size of polynomial - only one parameter can be selected which is shown as below: - \arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation - \arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation - \arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation - \arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation - \param[out] none - \retval none -*/ -void crc_polynomial_size_set(uint32_t poly_size) -{ - CRC_CTL &= (uint32_t)(~(CRC_CTL_PS)); - CRC_CTL |= (uint32_t)poly_size; -} - -/*! - \brief configure the CRC polynomial value function - \param[in] poly: configurable polynomial value - \param[out] none - \retval none -*/ -void crc_polynomial_set(uint32_t poly) -{ - CRC_POLY &= (uint32_t)(~CRC_POLY_POLY); - CRC_POLY = poly; -} - -/*! - \brief CRC calculate a 32-bit data - \param[in] sdata: specify 32-bit data - \param[out] none - \retval 32-bit CRC calculate value -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return(CRC_DATA); -} - -/*! - \brief CRC calculate a 32-bit data array - \param[in] array: pointer to an array of 32 bit data words - \param[in] size: size of the array - \param[out] none - \retval 32-bit CRC calculate value -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for(index = 0U; index < size; index++){ - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c deleted file mode 100644 index c065ddb7e5..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_ctc.c +++ /dev/null @@ -1,382 +0,0 @@ -/*! - \file gd32f3x0_ctc.c - \brief CTC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_ctc.h" - -#define CTC_FLAG_MASK ((uint32_t)0x00000700U) - -/*! - \brief reset CTC clock trim controller - \param[in] none - \param[out] none - \retval none -*/ -void ctc_deinit(void) -{ - /* reset CTC */ - rcu_periph_reset_enable(RCU_CTCRST); - rcu_periph_reset_disable(RCU_CTCRST); -} - -/*! - \brief configure reference signal source polarity - \param[in] polarity: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge - \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge - \param[out] none - \retval none -*/ -void ctc_refsource_polarity_config(uint32_t polarity) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); - CTC_CTL1 |= (uint32_t)polarity; -} - -/*! - \brief select reference signal source - \param[in] refs: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_GPIO: GPIO is selected - \arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected - \arg CTC_REFSOURCE_USBSOF: USBSOF is selected - \param[out] none - \retval none -*/ -void ctc_refsource_signal_select(uint32_t refs) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); - CTC_CTL1 |= (uint32_t)refs; -} - -/*! - \brief configure reference signal source prescaler - \param[in] prescaler: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided - \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 - \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 - \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 - \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 - \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 - \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 - \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 - \param[out] none - \retval none -*/ -void ctc_refsource_prescaler_config(uint32_t prescaler) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); - CTC_CTL1 |= (uint32_t)prescaler; -} - -/*! - \brief configure clock trim base limit value - \param[in] limit_value: 8-bit clock trim base limit value - \arg 0x00-0xFF - \param[out] none - \retval none -*/ -void ctc_clock_limit_value_config(uint8_t limit_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); - CTC_CTL1 |= CTL1_CKLIM(limit_value); -} - -/*! - \brief configure CTC counter reload value - \param[in] reload_value: 16-bit CTC counter reload value - \arg 0x0000-0xFFFF - \param[out] none - \retval none -*/ -void ctc_counter_reload_value_config(uint16_t reload_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); - CTC_CTL1 |= (uint32_t)reload_value; -} - -/*! - \brief enable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_enable(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; -} - -/*! - \brief disable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_disable(void) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); -} - -/*! - \brief configure the IRC48M trim value - \param[in] trim_value: 8-bit IRC48M trim value - \arg 0x00-0x3F - \param[out] none - \retval none -*/ -void ctc_irc48m_trim_value_config(uint8_t trim_value) -{ - /* clear TRIMVALUE bits */ - CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); - /* set TRIMVALUE bits */ - CTC_CTL0 |= CTL0_TRIMVALUE(trim_value); -} - -/*! - \brief generate software reference source sync pulse - \param[in] none - \param[out] none - \retval none -*/ -void ctc_software_refsource_pulse_generate(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; -} - -/*! - \brief configure hardware automatically trim mode - \param[in] hardmode: - only one parameter can be selected which is shown as below: - \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable - \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable - \param[out] none - \retval none -*/ -void ctc_hardware_trim_mode_config(uint32_t hardmode) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); - CTC_CTL0 |= (uint32_t)hardmode; -} - -/*! - \brief read CTC counter capture value when reference sync pulse occurred - \param[in] none - \param[out] none - \retval the 16-bit CTC counter capture value -*/ -uint16_t ctc_counter_capture_value_read(void) -{ - uint16_t capture_value = 0U; - capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT); - return (capture_value); -} - -/*! - \brief read CTC trim counter direction when reference sync pulse occurred - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - \arg SET: CTC trim counter direction is down-counting - \arg RESET: CTC trim counter direction is up-counting -*/ -FlagStatus ctc_counter_direction_read(void) -{ - FlagStatus ret_status = RESET; - if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ - ret_status = SET; - } - return ret_status; -} - -/*! - \brief read CTC counter reload value - \param[in] none - \param[out] none - \retval the 16-bit CTC counter reload value -*/ -uint16_t ctc_counter_reload_value_read(void) -{ - uint16_t reload_value = 0U; - reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); - return (reload_value); -} - -/*! - \brief read the IRC48M trim value - \param[in] none - \param[out] none - \retval the 8-bit IRC48M trim value -*/ -uint8_t ctc_irc48m_trim_value_read(void) -{ - uint8_t trim_value = 0U; - trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0); - return (trim_value); -} - -/*! - \brief enable the CTC interrupt - \param[in] interrupt: CTC interrupt enable - one or more parameters can be selected which are shown as below: - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_enable(uint32_t interrupt) -{ - CTC_CTL0 |= (uint32_t)interrupt; -} - -/*! - \brief disable the CTC interrupt - \param[in] interrupt: CTC interrupt enable source - one or more parameters can be selected which are shown as below: - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_disable(uint32_t interrupt) -{ - CTC_CTL0 &= (uint32_t)(~(interrupt)); -} - -/*! - \brief get CTC flag - \param[in] flag: the CTC flag - only one parameter can be selected which is shown as below: - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_flag_get(uint32_t flag) -{ - FlagStatus ret_status = RESET; - - if(RESET != (CTC_STAT & flag)){ - ret_status = SET; - } - return ret_status; -} - -/*! - \brief clear CTC flag - \param[in] flag: the CTC flag - only one parameter can be selected which is shown as below: - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval none -*/ -void ctc_flag_clear(uint32_t flag) -{ - if(flag & CTC_FLAG_MASK){ - CTC_INTC |= CTC_INTC_ERRIC; - }else{ - CTC_INTC |= flag; - } -} - -/*! - \brief get CTC interrupt flag - \param[in] interrupt: the CTC interrupt flag - only one parameter can be selected which is shown as below: - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_interrupt_flag_get(uint32_t interrupt) -{ - uint32_t ctc_int = 0U, intenable = 0U; - FlagStatus ret_status = RESET; - - if(interrupt & CTC_FLAG_MASK){ - intenable = CTC_CTL0 & CTC_INT_ERR; - }else{ - intenable = CTC_CTL0 & interrupt; - } - ctc_int = CTC_STAT & interrupt; - - if(ctc_int && intenable){ - ret_status = SET; - } - return ret_status; -} - -/*! - \brief clear CTC interrupt flag - \param[in] interrupt: the CTC interrupt flag - only one parameter can be selected which is shown as below: - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval none -*/ -void ctc_interrupt_flag_clear(uint32_t interrupt) -{ - if(interrupt & CTC_FLAG_MASK){ - CTC_INTC |= CTC_INTC_ERRIC; - }else{ - CTC_INTC |= interrupt; - } -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c deleted file mode 100644 index 689118c41e..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dac.c +++ /dev/null @@ -1,387 +0,0 @@ -/*! - \file gd32f3x0_dac.c - \brief DAC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifdef GD32F350 -#include "gd32f3x0_dac.h" - -/*! - \brief deinitialize DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_deinit(void) -{ - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); -} - -/*! - \brief enable DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_enable(void) -{ - DAC_CTL |= DAC_CTL_DEN; -} - -/*! - \brief disable DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_disable(void) -{ - DAC_CTL &= ~DAC_CTL_DEN; -} - -/*! - \brief enable DAC DMA - \param[in] none - \param[out] none - \retval none -*/ -void dac_dma_enable(void) -{ - DAC_CTL |= DAC_CTL_DDMAEN; -} - -/*! - \brief disable DAC DMA - \param[in] none - \param[out] none - \retval none -*/ -void dac_dma_disable(void) -{ - DAC_CTL &= ~DAC_CTL_DDMAEN; -} - -/*! - \brief enable DAC output buffer - \param[in] none - \param[out] none - \retval none -*/ -void dac_output_buffer_enable(void) -{ - DAC_CTL &= ~DAC_CTL_DBOFF; -} - -/*! - \brief disable DAC output buffer - \param[in] none - \param[out] none - \retval none -*/ -void dac_output_buffer_disable(void) -{ - DAC_CTL |= DAC_CTL_DBOFF; -} - -/*! - \brief enable DAC trigger - \param[in] none - \param[out] none - \retval none -*/ -void dac_trigger_enable(void) -{ - DAC_CTL |= DAC_CTL_DTEN; -} - -/*! - \brief disable DAC trigger - \param[in] none - \param[out] none - \retval none -*/ -void dac_trigger_disable(void) -{ - DAC_CTL &= ~DAC_CTL_DTEN; -} - -/*! - \brief enable DAC software trigger - \param[in] none - \param[out] none - \retval none -*/ -void dac_software_trigger_enable(void) -{ - DAC_SWT |= DAC_SWT_SWTR; -} - -/*! - \brief disable DAC software trigger - \param[in] none - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(void) -{ - DAC_SWT &= ~DAC_SWT_SWTR; -} - -/*! - \brief enable DAC interrupt(DAC DMA underrun interrupt) - \param[in] none - \param[out] none - \retval none -*/ -void dac_interrupt_enable(void) -{ - DAC_CTL |= DAC_CTL_DDUDRIE; -} - -/*! - \brief disable DAC interrupt(DAC DMA underrun interrupt) - \param[in] none - \param[out] none - \retval none -*/ -void dac_interrupt_disable(void) -{ - DAC_CTL &= ~DAC_CTL_DDUDRIE; -} - -/*! - \brief set DAC tgigger source - \param[in] triggersource: external triggers of DAC - \arg DAC_TRIGGER_T1_TRGO: trigger source is TIMER1 TRGO - \arg DAC_TRIGGER_T2_TRGO: trigger source is TIMER2 TRGO - \arg DAC_TRIGGER_T5_TRGO: trigger source is TIMER5 TRGO - \arg DAC_TRIGGER_T14_TRGO: trigger source is TIMER14 TRGO - \arg DAC_TRIGGER_EXTI_9: trigger source is EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger - \param[out] none - \retval none -*/ -void dac_trigger_source_config(uint32_t triggersource) -{ - DAC_CTL &= ~DAC_CTL_DTSEL; - DAC_CTL |= triggersource; -} - -/*! - \brief configure DAC wave mode - \param[in] wave_mode - \arg DAC_WAVE_DISABLE: wave disable - \arg DAC_WAVE_MODE_LFSR: LFSR noise mode - \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode - \param[out] none - \retval none -*/ -void dac_wave_mode_config(uint32_t wave_mode) -{ - DAC_CTL &= ~DAC_CTL_DWM; - DAC_CTL |= wave_mode; -} - -/*! - \brief configure DAC wave bit width - \param[in] bit_width - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t bit_width) -{ - DAC_CTL &= ~DAC_CTL_DWBW; - DAC_CTL |= bit_width; -} - -/*! - \brief configure DAC LFSR noise mode - \param[in] unmask_bits - \arg DAC_LFSR_BIT0: unmask the LFSR bit0 - \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] - \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] - \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] - \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] - \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] - \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] - \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] - \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] - \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] - \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] - \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] - \param[out] none - \retval none -*/ -void dac_lfsr_noise_config(uint32_t unmask_bits) -{ - DAC_CTL &= ~DAC_CTL_DWBW; - DAC_CTL |= unmask_bits; -} - -/*! - \brief configure DAC triangle noise mode - \param[in] amplitude - \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 - \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 - \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 - \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 - \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 - \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 - \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 - \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 - \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 - \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 - \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 - \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 - \param[out] none - \retval none -*/ -void dac_triangle_noise_config(uint32_t amplitude) -{ - DAC_CTL &= ~DAC_CTL_DWBW; - DAC_CTL |= amplitude; -} - -/*! - \brief get DAC output value - \param[in] none - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(void) -{ - uint16_t data = 0U; - data = (uint16_t)DAC_DO; - return data; -} - -/*! - \brief get the specified DAC flag(DAC DMA underrun flag) - \param[in] none - \param[out] none - \retval the state of dac bit(SET or RESET) -*/ -FlagStatus dac_flag_get(void) -{ - /* check the DMA underrun flag */ - if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the specified DAC flag(DAC DMA underrun flag) - \param[in] none - \param[out] none - \retval none -*/ -void dac_flag_clear(void) -{ - DAC_STAT |= DAC_STAT_DDUDR; -} - -/*! - \brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) - \param[in] none - \param[out] none - \retval the state of DAC interrupt flag(SET or RESET) -*/ -FlagStatus dac_interrupt_flag_get(void) -{ - FlagStatus temp_flag = RESET; - uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; - /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ - ddudr_flag = DAC_STAT & DAC_STAT_DDUDR; - ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE; - if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ - temp_flag = SET; - } - return temp_flag; -} - -/*! - \brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) - \param[in] none - \param[out] none - \retval none -*/ -void dac_interrupt_flag_clear(void) -{ - DAC_STAT |= DAC_STAT_DDUDR; -} - -/*! - \brief set DAC data holding register value - \param[in] dac_align - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data: data to be loaded - \param[out] none - \retval none -*/ -void dac_data_set(uint32_t dac_align, uint16_t data) -{ - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - DAC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - DAC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - DAC_R8DH = data; - break; - default: - break; - } -} -#endif /* GD32F350 */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c deleted file mode 100644 index 1ff7928c80..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dbg.c +++ /dev/null @@ -1,131 +0,0 @@ -/*! - \file gd32f3x0_dbg.c - \brief DBG driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_dbg.h" - -#define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */ - -/*! - \brief deinitialize the DBG - \param[in] none - \param[out] none - \retval none -*/ -void dbg_deinit(void) -{ - DBG_CTL0 = DBG_RESET_VAL; - DBG_CTL1 = DBG_RESET_VAL; -} - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL0 |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL0 &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode - \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode - \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode - \arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode - \arg DBG_STANDBY_HOLD: keep debugger connection during standby mode - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c deleted file mode 100644 index 971a0b72b6..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_dma.c +++ /dev/null @@ -1,561 +0,0 @@ -/*! - \file gd32f3x0_dma.c - \brief DMA driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_dma.h" - -/*! - \brief deinitialize DMA a channel registers - \param[in] channelx: specify which DMA channel is deinitialized - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_deinit(dma_channel_enum channelx) -{ - /* disable DMA a channel */ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_struct_para_init(dma_parameter_struct* init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; - init_struct->number = 0U; - init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; - init_struct->priority = (uint32_t)DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA channel - \param[in] channelx: specify which DMA channel is initialized - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct) -{ - uint32_t ctl; - - dma_channel_disable(channelx); - - /* configure peripheral base address */ - DMA_CHPADDR(channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(channelx) = init_struct->memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width,channel priotity */ - ctl = DMA_CHCTL(channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); - DMA_CHCTL(channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; - }else{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_circulation_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_circulation_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_channel_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_channel_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] channelx: specify which DMA channel to set peripheral base address - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(dma_channel_enum channelx, uint32_t address) -{ - DMA_CHPADDR(channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] channelx: specify which DMA channel to set memory base address - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(dma_channel_enum channelx, uint32_t address) -{ - DMA_CHMADDR(channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] number: the number of remaining data to be transferred by the DMA - \param[out] none - \retval none -*/ -void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number) -{ - DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(dma_channel_enum channelx) -{ - return (uint32_t)DMA_CHCNT(channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] priority: priority level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief configure transfer data width of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] mwidth: transfer data width of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief configure transfer data width of peripheral - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] pwidth: transfer data width of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction) -{ - if(DMA_PERIPHERAL_TO_MEMORY == direction){ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){ - reval = SET; - }else{ - reval = RESET; - } - - return reval; -} - -/*! - \brief clear DMA a channel flag - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: transfer finish flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel - \arg DMA_INT_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch(flag){ - case DMA_INT_FLAG_FTF: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE; - break; - default: - break; - } - - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel interrupt flag - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: transfer finish flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel - \arg DMA_INT_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC |= DMA_FLAG_ADD(flag,channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] source: specify which interrupt to enable - only one parameter can be selected which is shown as below: - \arg DMA_INT_ERR: channel error interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_FTF: channel full transfer finish interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source) -{ - DMA_CHCTL(channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[in] source: specify which interrupt to disable - only one parameter can be selected which is shown as below: - \arg DMA_INT_ERR: channel error interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_FTF: channel full transfer finish interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source) -{ - DMA_CHCTL(channelx) &= ~source; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c deleted file mode 100644 index e14ed36472..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_exti.c +++ /dev/null @@ -1,253 +0,0 @@ -/*! - \file gd32f3x0_exti.c - \brief EXTI driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_exti.h" - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x0F940000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; -} - -/*! - \brief initialize the EXTI, enable the configuration of EXTI initialize - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19,21,22): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling trigger - \arg EXTI_TRIG_BOTH: rising and falling trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, \ - exti_mode_enum mode, \ - exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch(trig_type){ - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19,21,22): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19,21,22): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI line x pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19,21,22): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI line x pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19,21,22): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI line x flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19,21,22): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI line x pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..19,21,22): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c deleted file mode 100644 index e1341fa363..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fmc.c +++ /dev/null @@ -1,888 +0,0 @@ -/*! - \file gd32f3x0_fmc.c - \brief FMC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_fmc.h" - -/* FMC main memory programming functions */ - -/*! - \brief unlock the main FMC operation - it is better to used in pairs with fmc_lock - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL & FMC_CTL_LK))){ - /* write the FMC key */ - FMC_KEY = UNLOCK_KEY0; - FMC_KEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - it is better to used in pairs with fmc_unlock after an operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit*/ - FMC_CTL |= FMC_CTL_LK; -} - -/*! - \brief set the wait state counter value - \param[in] wscnt: wait state counter value - only one parameter can be selected which is shown as below: - \arg WS_WSCNT_0: 0 wait state added - \arg WS_WSCNT_1: 1 wait state added - \arg WS_WSCNT_2: 2 wait state added - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint8_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief fmc wait state enable - \param[in] none - \param[out] none - \retval none -*/ -void fmc_wait_state_enable(void) -{ - /* unlock the main flash */ - fmc_unlock(); - - /* set the WSEN bit in register FMC_WSEN */ - FMC_WSEN |= FMC_WSEN_WSEN; - - /* lock the main flash after operation */ - fmc_lock(); -} - -/*! - \brief fmc wait state disable - \param[in] none - \param[out] none - \retval none -*/ -void fmc_wait_state_disable(void) -{ - /* unlock the main flash */ - fmc_unlock(); - - /* reset the WSEN bit in register FMC_WSEN */ - FMC_WSEN &= ~FMC_WSEN_WSEN; - - /* lock the main flash after operation */ - fmc_lock(); -} - -/*! - \brief erase page - \param[in] page_address: target page start address - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start page erase */ - FMC_CTL |= FMC_CTL_PER; - FMC_ADDR = page_address; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PER bit */ - FMC_CTL &= ~FMC_CTL_PER; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start chip erase */ - FMC_CTL |= FMC_CTL_MER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the MER bit */ - FMC_CTL &= ~FMC_CTL_MER; - } - - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - - REG32(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a half word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - - REG16(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address without erasing - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - FMC_WSEN |= FMC_WSEN_BPEN; - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - - REG32(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/* FMC option bytes programming functions */ - -/*! - \brief unlock the option byte operation - it is better to used in pairs with ob_lock - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){ - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the option byte operation - it is better to used in pairs with ob_unlock after an operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWE bit */ - FMC_CTL &= ~FMC_CTL_OBWEN; -} - -/*! - \brief reload the option byte and generate a system reset - \param[in] none - \param[out] none - \retval none -*/ -void ob_reset(void) -{ - /* set the OBRLD bit */ - FMC_CTL |= FMC_CTL_OBRLD; -} - -/*! - \brief erase the option byte - programmer must ensure FMC & option byte are both unlocked before calling this function - \param[in] none - \param[out] none - \retval fmc_state -*/ -fmc_state_enum ob_erase(void) -{ - uint16_t fmc_spc; - - uint32_t fmc_plevel = ob_obstat_plevel_get(); - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* get the original option byte security protection code */ - if(OB_OBSTAT_PLEVEL_NO == fmc_plevel){ - fmc_spc = FMC_NSPC; - }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){ - fmc_spc = FMC_LSPC; - }else{ - fmc_spc = FMC_HSPC; - fmc_state = FMC_OB_HSPC; - } - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - - /* restore the last get option byte security protection code */ - OB_SPC = fmc_spc; - OB_USER = OB_USER_DEFAULT; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable option byte write protection(OB_WP) depending on current option byte - \param[in] ob_wp: write protection configuration data - setting the bit of ob_wp means enabling the corresponding sector write protection - \param[out] none - \retval fmc_state -*/ -fmc_state_enum ob_write_protection_enable(uint16_t ob_wp) -{ - uint8_t ob_wrp0, ob_wrp1; - ob_parm_struct ob_parm; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - ob_parm_get(&ob_parm); - ob_wp = (uint16_t)(~ob_wp); - ob_wrp0 = (uint8_t)(ob_wp & OB_LWP); - ob_wrp1 = (uint8_t)((ob_wp & OB_HWP) >> 8U); - - if(0xFFU == (uint8_t)OB_WP0){ - if (0xFFU == (uint8_t)OB_WP1){ - if(FMC_READY == fmc_state){ - /* set the OBPG bit*/ - FMC_CTL |= FMC_CTL_OBPG; - - if(0xFFU != ob_wrp0){ - OB_WP0 = ob_wrp0 ; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - - if((FMC_READY == fmc_state) && (0xFFU != ob_wrp1)){ - OB_WP1 = ob_wrp1 ; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - } - }else{ - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* enable the option bytes programming */ - FMC_CTL |= FMC_CTL_OBPG; - - ob_value_modify(OB_WP_ADDR0, ob_wp ,&ob_parm); - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection code - only one parameter can be selected which is shown as below: - \arg FMC_NSPC: no security protection - \arg FMC_LSPC: low security protection - \arg FMC_HSPC: high security protection - \param[out] none - \retval fmc_state -*/ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - ob_parm_struct ob_parm; - ob_parm_get(&ob_parm); - - /* the OB_SPC byte cannot be reprogrammed if protection level is high */ - if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){ - fmc_state = FMC_OB_HSPC; - } - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* enable the option bytes programming */ - FMC_CTL |= FMC_CTL_OBPG; - - ob_value_modify(OB_SPC_ADDR, (uint16_t)ob_spc ,&ob_parm); - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option byte depending on current option byte - \param[in] ob_user: user option byte - one or more parameters (bitwise AND) can be selected which are shown as below: - \arg OB_FWDGT_HW: hardware free watchdog timer - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \arg OB_BOOT1_SET_1: BOOT1 bit is 1 - \arg OB_VDDA_DISABLE: disable VDDA monitor - \arg OB_SRAM_PARITY_ENABLE: enable sram parity check - \param[out] none - \retval fmc_state -*/ -fmc_state_enum ob_user_write(uint8_t ob_user) -{ - /* check whether FMC is ready or not */ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - ob_parm_struct ob_parm; - ob_parm_get(&ob_parm); - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - - /* restore the last get option byte security protection code */ - ob_value_modify(OB_USER_ADDR, (uint16_t)ob_user, &ob_parm); - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC data option byte - \param[in] address: OB_DATA_ADDR0 or OB_DATA_ADDR1 - only one parameter can be selected which is shown as below: - \arg OB_DATA_ADDR0: option byte data address 0 - \arg OB_DATA_ADDR1: option byte data address 1 - \param[in] data: the byte to be programmed - \param[out] none - \retval fmc_state -*/ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - ob_parm_struct ob_parm; - ob_parm_get(&ob_parm); - if(0xFFU == REG8(address)) - { - if(FMC_READY == fmc_state){ - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - - REG16(address) = data ; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - }else{ - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* enable the option bytes programming */ - FMC_CTL |= FMC_CTL_OBPG; - - ob_value_modify(address, (uint16_t)data ,&ob_parm); - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get OB_USER in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_user -*/ -uint8_t ob_user_get(void) -{ - return (uint8_t)(FMC_OBSTAT >> 8U); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> 16U); -} - -/*! - \brief get the FMC option byte write protection (OB_WP) in register FMC_WP - \param[in] none - \param[out] none - \retval OB_WP -*/ -uint16_t ob_write_protection_get(void) -{ - return (uint16_t)(FMC_WP); -} - -/*! - \brief get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register - \param[in] none - \param[out] none - \retval the value of PLEVEL -*/ -uint32_t ob_obstat_plevel_get(void) -{ - return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1)); -} - -/* FMC interrupts and flags management functions */ -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - one or more parameters can be selected which are shown as below: - \arg FMC_INTEN_END: FMC end of operation interrupt - \arg FMC_INTEN_ERR: FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_CTL |= interrupt; -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - one or more parameters can be selected which are shown as below: - \arg FMC_INTEN_END: FMC end of operation interrupt - \arg FMC_INTEN_ERR: FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_CTL &= ~(uint32_t)interrupt; -} - -/*! - \brief get flag set or reset - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: FMC end of programming flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - FlagStatus status = RESET; - - if(FMC_STAT & flag){ - status = SET; - } - /* return the state of corresponding FMC flag */ - return status; -} - -/*! - \brief clear the FMC pending flag by writing 1 - \param[in] flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: fmc end of programming flag - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - /* clear the flags */ - FMC_STAT = flag; -} - -/*! - \brief get flag set or reset - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: FMC end of programming flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(uint32_t flag) -{ - FlagStatus status = RESET; - - if(FMC_STAT & flag){ - status = SET; - } - /* return the state of corresponding FMC flag */ - return status; -} - -/*! - \brief clear the FMC pending flag by writing 1 - \param[in] flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: fmc end of programming flag - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(uint32_t flag) -{ - /* clear the flags */ - FMC_STAT = flag; -} - -/*! - \brief get the FMC state - \param[in] none - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){ - fmc_state = FMC_PGERR; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC is ready or not - \param[in] timeout: timeout count - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get current option byte value - \param[in] ob_parm: pointer to option byte parameter struct - \param[out] ob_parm: pointer to option byte parameter struct - \retval none -*/ -void ob_parm_get(ob_parm_struct *ob_parm) -{ - /* get current option byte value */ - ob_parm->spc = (uint8_t)OB_SPC; - ob_parm->user = (uint8_t)OB_USER; - ob_parm->data0 = (uint8_t)OB_DATA0; - ob_parm->data1 = (uint8_t)OB_DATA1; - ob_parm->wp0 = (uint8_t)OB_WP0; - ob_parm->wp1 = (uint8_t)OB_WP1; -} - -/*! - \brief modify the target option byte depending on the original value - \param[in] address: target option byte address - \param[in] value: target option byte value - \param[in] ob_parm: pointer to option byte parameter struct - \param[out] none - \retval none -*/ -void ob_value_modify(uint32_t address, uint16_t value,ob_parm_struct *ob_parm) -{ - uint8_t spc, user, data0, data1, wp0, wp1; - /* store the original option bytes */ - spc = ob_parm->spc; - user = ob_parm->user; - data0 = ob_parm->data0; - data1 = ob_parm->data1; - wp0 = ob_parm->wp0; - wp1 = ob_parm->wp1; - - /* bring in the target option byte */ - if(OB_SPC_ADDR == address){ - spc = (uint8_t)value; - }else if(OB_DATA_ADDR0 == address){ - data0 = (uint8_t)value; - }else if(OB_DATA_ADDR1 == address){ - data1 = (uint8_t)value; - }else if(OB_USER_ADDR == address){ - user = user & (uint8_t)value; - }else{ - wp0 = wp0 & ((uint8_t) (value)); - wp1 = wp1 & ((uint8_t) (value >> 8U)); - } - /* basing on original value, modify the target option byte */ - OB_SPC = spc; - OB_USER = user; - if(0xFFU != data0){ - OB_DATA0 = data0; - } - if(0xFFU != data1){ - OB_DATA1 = data1; - } - if(0xFFU != wp0){ - OB_WP0 = wp0; - } - if(0xFFU != wp1){ - OB_WP1 = wp1; - } -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c deleted file mode 100644 index a3fcc3c564..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_fwdgt.c +++ /dev/null @@ -1,180 +0,0 @@ -/*! - \file gd32f3x0_fwdgt.c - \brief FWDGT driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_fwdgt.h" - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief configure the free watchdog timer counter window value - \param[in] window_value: specify window value(0x0000 - 0x0FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_window_value_config(uint16_t window_value) -{ - uint32_t time_index = FWDGT_WND_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_WND */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the WUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_WUD; - }while((--time_index > 0U) && (RESET != flag_status)); - - if (RESET != flag_status){ - return ERROR; - } - - FWDGT_WND = WND_WND(window_value); - - return SUCCESS; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && (RESET != flag_status)); - - if (RESET != flag_status){ - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && (RESET != flag_status)); - - if (RESET != flag_status){ - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(FWDGT_STAT & flag){ - return SET; - } - return RESET; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c deleted file mode 100644 index 6af393fe13..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_gpio.c +++ /dev/null @@ -1,424 +0,0 @@ -/*! - \file gd32f3x0_gpio.c - \brief GPIO driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_gpio.h" - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch(gpio_periph){ - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOD: - /* reset GPIOD */ - rcu_periph_reset_enable(RCU_GPIODRST); - rcu_periph_reset_disable(RCU_GPIODRST); - break; - case GPIOF: - /* reset GPIOF */ - rcu_periph_reset_enable(RCU_GPIOFRST); - rcu_periph_reset_disable(RCU_GPIOFRST); - break; - default: - break; - } -} - -/*! - \brief set GPIO mode - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] mode: gpio pin mode - only one parameter can be selected which is shown as below: - \arg GPIO_MODE_INPUT: input mode - \arg GPIO_MODE_OUTPUT: output mode - \arg GPIO_MODE_AF: alternate function mode - \arg GPIO_MODE_ANALOG: analog mode - \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor - only one parameter can be selected which is shown as below: - \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors - \arg GPIO_PUPD_PULLUP: with pull-up resistor - \arg GPIO_PUPD_PULLDOWN:with pull-down resistor - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) -{ - uint16_t i; - uint32_t ctl, pupd; - - ctl = GPIO_CTL(gpio_periph); - pupd = GPIO_PUD(gpio_periph); - - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin mode bits */ - ctl &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - ctl |= GPIO_MODE_SET(i, mode); - - /* clear the specified pin pupd bits */ - pupd &= ~GPIO_PUPD_MASK(i); - /* set the specified pin pupd bits */ - pupd |= GPIO_PUPD_SET(i, pull_up_down); - } - } - - GPIO_CTL(gpio_periph) = ctl; - GPIO_PUD(gpio_periph) = pupd; -} - -/*! - \brief set GPIO output type and speed - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] otype: gpio pin output mode - only one parameter can be selected which is shown as below: - \arg GPIO_OTYPE_PP: push pull mode - \arg GPIO_OTYPE_OD: open drain mode - \param[in] speed: gpio pin output max speed - only one parameter can be selected which is shown as below: - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \arg GPIO_OSPEED_MAX: GPIO very high output speed, max speed more than 50MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t ospeed0,ospeed1; - - if(GPIO_OTYPE_OD == otype){ - GPIO_OMODE(gpio_periph) |= (uint32_t)pin; - }else{ - GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); - } - - /* get the specified pin output speed bits value */ - ospeed0 = GPIO_OSPD0(gpio_periph); - - if(GPIO_OSPEED_MAX == speed){ - ospeed1 = GPIO_OSPD1(gpio_periph); - - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ - /* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15) - is "11" (output max speed 50MHz) */ - ospeed0 |= GPIO_OSPEED_SET(i,0x03); - ospeed1 |= (1U << i); - } - } - GPIO_OSPD0(gpio_periph) = ospeed0; - GPIO_OSPD1(gpio_periph) = ospeed1; - }else{ - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin output speed bits */ - ospeed0 &= ~GPIO_OSPEED_MASK(i); - /* set the specified pin output speed bits */ - ospeed0 |= GPIO_OSPEED_SET(i,speed); - } - } - GPIO_OSPD0(gpio_periph) = ospeed0; - } -} - -/*! - \brief set GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - only one parameter can be selected which is shown as below: - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if(RESET != bit_value){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] data: specify the value to be written to the port output control register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph, uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO all pins input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[out] none - \retval state of GPIO all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t)GPIO_ISTAT(gpio_periph); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO all pins output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[out] none - \retval state of GPIO all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return (uint16_t)GPIO_OCTL(gpio_periph); -} - -/*! - \brief set GPIO alternate function - \param[in] gpio_periph: GPIOx(x = A,B,C) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C) - \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet - only one parameter can be selected which is shown as below: - \arg GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, CEC, - IFRP, TSI, CTC, I2C0, I2C1, SWDIO, SWCLK - \arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1, IFRP, CEC - \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0 - \arg GPIO_AF_3: TSI, I2C0, TIMER14 - \arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13 - \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, USBFS, I2S0 - \arg GPIO_AF_6(port A,B only): CTC, SPI1 - \arg GPIO_AF_7(port A,B only): CMP0, CMP1 - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) -{ - uint16_t i; - uint32_t afrl, afrh; - - afrl = GPIO_AFSEL0(gpio_periph); - afrh = GPIO_AFSEL1(gpio_periph); - - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ - /* clear the specified pin alternate function bits */ - afrl &= ~GPIO_AFR_MASK(i); - afrl |= GPIO_AFR_SET(i,alt_func_num); - } - } - - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin alternate function bits */ - afrh &= ~GPIO_AFR_MASK(i - 8U); - afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); - } - } - - GPIO_AFSEL0(gpio_periph) = afrl; - GPIO_AFSEL1(gpio_periph) = afrh; -} - -/*! - \brief lock GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -/*! - \brief toggle GPIO pin status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_TG(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief toggle GPIO port status - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,F) - \param[out] none - \retval none -*/ -void gpio_port_toggle(uint32_t gpio_periph) -{ - GPIO_TG(gpio_periph) = 0x0000FFFFU; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c deleted file mode 100644 index 2f428b1881..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_i2c.c +++ /dev/null @@ -1,729 +0,0 @@ -/*! - \file gd32f3x0_i2c.c - \brief I2C driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x0000003FU) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ -#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch(i2c_periph){ - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - and fast mode plus (up to 1MHz) - \param[in] dutycyc: duty cycle in fast mode or fast mode plus - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) = I2CCLK_MAX; - }else if(risetime <= I2CCLK_MIN){ - I2C_RT(i2c_periph) = I2CCLK_MIN; - }else{ - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - }else if(400000U >= clkspeed){ - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if(0U == (clkc & I2C_CKCFG_CLKC)){ - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - }else{ - /* fast mode plus, the maximum SCL rise time is 120ns */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - /* enable fast mode */ - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - /* enable I2C fast mode plus */ - I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief configure I2C position of ACK and PEC when receiving - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ - addr = addr & I2C_TRANSMITTER; - }else{ - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief enable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: the second address in dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) -{ - /* configure address */ - addr = addr & I2C_ADDRESS2_MASK; - I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); -} - -/*! - \brief disable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_dualaddr_disable(uint32_t i2c_periph) -{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none -*/ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SS); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether to enable I2C PEC calculation or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none -*/ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether ARP is enabled under SMBus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] arpstate: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(I2C_FLAG_ADDSEND == flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: interrupt type - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ - intenable = 1U; - }else{ - intenable = 0U; - } - } - if((0U != flagstatus) && (0U != intenable)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - if(I2C_INT_FLAG_ADDSEND == int_flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} - diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c deleted file mode 100644 index d467c32b82..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_misc.c +++ /dev/null @@ -1,189 +0,0 @@ -/*! - \file gd32f3x0_misc.c - \brief MISC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_misc.h" - -/*! - \brief set the priority group - \param[in] nvic_prigroup: the NVIC priority group - only one parameter can be selected which is shown as below: - \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority - \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority - \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority - \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority - \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority - \param[out] none - \retval none -*/ -void nvic_priority_group_set(uint32_t nvic_prigroup) -{ - /* set the priority group value */ - SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; -} - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set - \param[in] nvic_irq_sub_priority: the subpriority needed to set - \param[out] none - \retval none -*/ -void nvic_irq_enable(uint8_t nvic_irq, - uint8_t nvic_irq_pre_priority, - uint8_t nvic_irq_sub_priority) -{ - uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; - - /* use the priority group value to get the temp_pre and the temp_sub */ - switch ((SCB->AIRCR) & (uint32_t)0x700U) { - case NVIC_PRIGROUP_PRE0_SUB4: - temp_pre = 0U; - temp_sub = 0x4U; - break; - case NVIC_PRIGROUP_PRE1_SUB3: - temp_pre = 1U; - temp_sub = 0x3U; - break; - case NVIC_PRIGROUP_PRE2_SUB2: - temp_pre = 2U; - temp_sub = 0x2U; - break; - case NVIC_PRIGROUP_PRE3_SUB1: - temp_pre = 3U; - temp_sub = 0x1U; - break; - case NVIC_PRIGROUP_PRE4_SUB0: - temp_pre = 4U; - temp_sub = 0x0U; - break; - default: - nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre = 2U; - temp_sub = 0x2U; - break; - } - - /* get the temp_priority to fill the NVIC->IP register */ - temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); - temp_priority = temp_priority << 0x04U; - NVIC->IP[nvic_irq] = (uint8_t)temp_priority; - - /* enable the selected IRQ */ - NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(uint8_t nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - only one parameter can be selected which is shown as below: - \arg NVIC_VECTTAB_RAM: RAM base address - \are NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - only one parameter can be selected which is shown as below: - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - only one parameter can be selected which is shown as below: - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - only one parameter can be selected which is shown as below: - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c deleted file mode 100644 index c537c600da..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_pmu.c +++ /dev/null @@ -1,407 +0,0 @@ -/*! - \file gd32f3x0_pmu.c - \brief PMU driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_pmu.h" - - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - only one parameter can be selected which is shown as below: - \arg PMU_LVDT_0: voltage threshold is 2.1V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.6V - \arg PMU_LVDT_4: voltage threshold is 2.7V - \arg PMU_LVDT_5: voltage threshold is 2.9V - \arg PMU_LVDT_6: voltage threshold is 3.0V - \arg PMU_LVDT_7: voltage threshold is 3.1V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief select LDO output voltage - these bits set by software when the main PLL closed - \param[in] ldo_output: - only one parameter can be selected which is shown as below: - \arg PMU_LDOVS_LOW: LDO output voltage low mode - \arg PMU_LDOVS_MID: LDO output voltage mid mode - \arg PMU_LDOVS_HIGH: LDO output voltage high mode - \param[out] none - \retval none -*/ -void pmu_ldo_output_select(uint32_t ldo_output) -{ - PMU_CTL &= ~PMU_CTL_LDOVS; - PMU_CTL |= ldo_output; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief enable low-driver mode in deep-sleep mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lowdriver_mode_enable(void) -{ - PMU_CTL &= ~PMU_CTL_LDEN; - PMU_CTL |= PMU_LOWDRIVER_ENABLE; -} - -/*! - \brief disable low-driver mode in deep-sleep mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lowdriver_mode_disable(void) -{ - PMU_CTL &= ~PMU_CTL_LDEN; - PMU_CTL |= PMU_LOWDRIVER_DISABLE; -} - -/*! - \brief enable high-driver mode - this bit set by software only when IRC8M or HXTAL used as system clock - \param[in] none - \param[out] none - \retval none -*/ -void pmu_highdriver_mode_enable(void) -{ - PMU_CTL |= PMU_CTL_HDEN; -} - -/*! - \brief disable high-driver mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_highdriver_mode_disable(void) -{ - PMU_CTL &= ~PMU_CTL_HDEN; -} - -/*! - \brief switch high-driver mode - this bit set by software only when IRC8M or HXTAL used as system clock - \param[in] highdr_switch: - only one parameter can be selected which is shown as below: - \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch - \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch - \param[out] none - \retval none -*/ -void pmu_highdriver_switch_select(uint32_t highdr_switch) -{ - /* wait for HDRF flag to be set */ - while(SET != pmu_flag_get(PMU_FLAG_HDR)){ - } - PMU_CTL &= ~PMU_CTL_HDS; - PMU_CTL |= highdr_switch; -} - -/*! - \brief low-driver mode when use low power LDO - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg PMU_NORMALDR_LOWPWR: normal-driver when use low power LDO - \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO - \param[out] none - \retval none -*/ -void pmu_lowpower_driver_config(uint32_t mode) -{ - PMU_CTL &= ~PMU_CTL_LDLP; - PMU_CTL |= mode; -} - -/*! - \brief low-driver mode when use normal power LDO - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg PMU_NORMALDR_NORMALPWR: normal-driver when use low power LDO - \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO - \param[out] none - \retval none -*/ -void pmu_normalpower_driver_config(uint32_t mode) -{ - PMU_CTL &= ~PMU_CTL_LDNP; - PMU_CTL |= mode; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo: - only one parameter can be selected which is shown as below: - \arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) -{ - static uint32_t reg_snap[ 4 ]; - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - reg_snap[ 0 ] = REG32( 0xE000E010U ); - reg_snap[ 1 ] = REG32( 0xE000E100U ); - reg_snap[ 2 ] = REG32( 0xE000E104U ); - reg_snap[ 3 ] = REG32( 0xE000E108U ); - - REG32( 0xE000E010U ) &= 0x00010004U; - REG32( 0xE000E180U ) = 0XB7FFEF19U; - REG32( 0xE000E184U ) = 0XFFFFFBFFU; - REG32( 0xE000E188U ) = 0xFFFFFFFFU; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ - __WFI(); - }else{ - __SEV(); - __WFE(); - __WFE(); - } - - REG32( 0xE000E010U ) = reg_snap[ 0 ] ; - REG32( 0xE000E100U ) = reg_snap[ 1 ] ; - REG32( 0xE000E104U ) = reg_snap[ 2 ] ; - REG32( 0xE000E108U ) = reg_snap[ 3 ] ; - - /* reset sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief enable wakeup pin - \param[in] wakeup_pin: - one or more parameters can be selected which are shown as below: - \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) - \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) - \arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) - \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) - \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(uint32_t wakeup_pin) -{ - PMU_CS |= wakeup_pin; -} - -/*! - \brief disable wakeup pin - \param[in] wakeup_pin: - one or more parameters can be selected which are shown as below: - \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) - \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) - \arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5) - \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) - \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(uint32_t wakeup_pin) -{ - PMU_CS &= ~(wakeup_pin); -} - -/*! - \brief enable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief clear flag bit - \param[in] flag_clear: - one or more parameters can be selected which are shown as below: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag_clear) -{ - if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){ - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - } - if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){ - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - } -} - -/*! - \brief get flag state - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \arg PMU_FLAG_LDOVSR: LDO voltage select ready flag - \arg PMU_FLAG_HDR: high-driver ready flag - \arg PMU_FLAG_HDSR: high-driver switch ready flag - \arg PMU_FLAG_LDR: low-driver mode ready flag - \param[out] none - \retval FlagStatus SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - FlagStatus ret_status = RESET; - - if(PMU_CS & flag){ - ret_status = SET; - } - - return ret_status; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c deleted file mode 100644 index 980092bd5f..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rcu.c +++ /dev/null @@ -1,1204 +0,0 @@ -/*! - \file gd32f3x0_rcu.c - \brief RCU driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_rcu.h" - -/* define clock source */ -#define SEL_IRC8M ((uint32_t)0x00000000U) -#define SEL_HXTAL ((uint32_t)0x00000001U) -#define SEL_PLL ((uint32_t)0x00000002U) - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL0 |= RCU_CTL0_IRC8MEN; - while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ - } - /* reset RCU */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ - RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); -#if (defined(GD32F350)) - RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); - RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); -#endif /* GD32F350 */ - RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); - RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); - RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; - RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; - RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; - RCU_INT = 0x00000000U; - RCU_ADDINT = 0x00000000U; -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock - \arg RCU_DMA: DMA clock - \arg RCU_CRC: CRC clock - \arg RCU_TSI: TSI clock - \arg RCU_CFGCMP: CFGCMP clock - \arg RCU_ADC: ADC clock - \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350) - \arg RCU_SPIx (x=0,1): SPI clock - \arg RCU_USARTx (x=0,1): USART clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_USBFS: USBFS clock (only for GD32F350) - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock (only for GD32F350) - \arg RCU_CEC: CEC clock (only for GD32F350) - \arg RCU_CTC: CTC clock - \arg RCU_RTC: RTC clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,F): GPIO ports clock - \arg RCU_DMA: DMA clock - \arg RCU_CRC: CRC clock - \arg RCU_TSI: TSI clock - \arg RCU_CFGCMP: CFGCMP clock - \arg RCU_ADC: ADC clock - \arg RCU_TIMERx (x=0,1,2,5,13,14,15,16): TIMER clock (RCU_TIMER5 only for GD32F350) - \arg RCU_SPIx (x=0,1): SPI clock - \arg RCU_USARTx (x=0,1): USART clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_USBFS: USBFS clock (only for GD32F350) - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock (only for GD32F350) - \arg RCU_CEC: CEC clock (only for GD32F350) - \arg RCU_CTC: CTC clock - \arg RCU_RTC: RTC clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports - \arg RCU_TSIRST: reset TSI - \arg RCU_CFGCMPRST: reset CFGCMP - \arg RCU_ADCRST: reset ADC - \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350) - \arg RCU_SPIxRST (x=0,1): reset SPI - \arg RCU_USARTxRST (x=0,1): reset USART - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_USBFSRST: reset USBFS (only for GD32F350) - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC (only for GD32F350) - \arg RCU_CECRST: reset CEC (only for GD32F350) - \arg RCU_CTCRST: reset CTC - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,F): reset GPIO ports - \arg RCU_TSIRST: reset TSI - \arg RCU_CFGCMPRST: reset CFGCMP - \arg RCU_ADCRST: reset ADC - \arg RCU_TIMERxRST (x=0,1,2,5,13,14,15,16): reset TIMER (RCU_TIMER5 only for GD32F350) - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1): reset USART - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_USBFSRST: reset USBFS (only for GD32F350) - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC (only for GD32F350) - \arg RCU_CECRST: reset CEC (only for GD32F350) - \arg RCU_CTCRST: reset CTC - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t cksys_source = 0U; - cksys_source = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - cksys_source &= ~RCU_CFG0_SCS; - RCU_CFG0 = (ck_sys | cksys_source); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - only one parameter can be selected which is shown as below: - \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t ahbpsc = 0U; - ahbpsc = RCU_CFG0; - /* reset the AHBPSC bits and set according to ck_ahb */ - ahbpsc &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (ck_ahb | ahbpsc); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t apb1psc = 0U; - apb1psc = RCU_CFG0; - /* reset the APB1PSC and set according to ck_apb1 */ - apb1psc &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (ck_apb1 | apb1psc); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t apb2psc = 0U; - apb2psc = RCU_CFG0; - /* reset the APB2PSC and set according to ck_apb2 */ - apb2psc &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (ck_apb2 | apb2psc); -} - -/*! - \brief configure the ADC clock prescaler selection - \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum - only one parameter can be selected which is shown as below: - \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC - \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC - \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC - \arg RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC - \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC - \arg RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC - \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC - \arg RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC - \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC - \arg RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc) -{ - /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */ - RCU_CFG0 &= ~RCU_CFG0_ADCPSC; - RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2); - - /* set the ADC clock according to ck_adc */ - switch(ck_adc){ - case RCU_ADCCK_IRC28M_DIV2: - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_IRC28M: - RCU_CFG2 |= RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV2: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV3: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV4: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV5: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV6: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV7: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV8: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV9: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - default: - break; - } -} - -/*! - \brief configure the USBFS clock prescaler selection - \param[in] ck_usbfs: USBFS clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_USBFS_CKPLL_DIV1_5: select CK_PLL/1.5 as CK_USBFS - \arg RCU_USBFS_CKPLL_DIV1: select CK_PLL as CK_USBFS - \arg RCU_USBFS_CKPLL_DIV2_5: select CK_PLL/2.5 as CK_USBFS - \arg RCU_USBFS_CKPLL_DIV2: select CK_PLL/2 as CK_USBFS - \arg RCU_USBFS_CKPLL_DIV3: select CK_PLL/3 as CK_USBFS - \arg RCU_USBFS_CKPLL_DIV3_5: select CK_PLL/3.5 as CK_USBFS - \param[out] none - \retval none -*/ -void rcu_usbfs_clock_config(uint32_t ck_usbfs) -{ - /* reset the USBFSPSC bits and set according to ck_usbfs */ - RCU_CFG0 &= ~RCU_CFG0_USBFSPSC; - RCU_CFG2 &= ~RCU_CFG2_USBFSPSC2; - - RCU_CFG0 |= (ck_usbfs & (~RCU_CFG2_USBFSPSC2)); - RCU_CFG2 |= (ck_usbfs & RCU_CFG2_USBFSPSC2); -} - -/*! - \brief configure the CK_OUT clock source and divider - \param[in] ckout_src: CK_OUT clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUTSRC_NONE: no clock selected - \arg RCU_CKOUTSRC_IRC28M: IRC28M selected - \arg RCU_CKOUTSRC_IRC40K: IRC40K selected - \arg RCU_CKOUTSRC_LXTAL: LXTAL selected - \arg RCU_CKOUTSRC_CKSYS: CKSYS selected - \arg RCU_CKOUTSRC_IRC8M: IRC8M selected - \arg RCU_CKOUTSRC_HXTAL: HXTAL selected - \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected - \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected - \param[in] ckout_div: CK_OUT divider - \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x - \param[out] none - \retval none -*/ -void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div) -{ - uint32_t ckout = 0U; - ckout = RCU_CFG0; - /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */ - ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 = (ckout | ckout_src | ckout_div); -} - -/*! - \brief configure the PLL clock source preselection - \param[in] pll_presel: PLL clock source preselection - only one parameter can be selected which is shown as below: - \arg RCU_PLLPRESEL_IRC48M: select IRC48M as PLL preselection clock - \arg RCU_PLLPRESEL_HXTAL: select HXTAL as PLL preselection clock - \param[out] none - \retval none -*/ -void rcu_pll_preselection_config(uint32_t pll_presel) -{ - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL); - RCU_CFG1 |= pll_presel; -} - -/*! - \brief configure the PLL clock source selection and PLL multiply factor - \param[in] pll_src: PLL clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock - \arg RCU_PLLSRC_HXTAL_IRC48M: select HXTAL or IRC48M as PLL source clock - \param[in] pll_mul: PLL multiply factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL_MULx(x=2..64): PLL source clock * x - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG1 &= ~(RCU_CFG1_PLLMF5); - RCU_CFG0 |= (pll_src | (pll_mul & (~RCU_CFG1_PLLMF5))); - RCU_CFG1 |= (pll_mul & RCU_CFG1_PLLMF5); -} - -/*! - \brief configure the USART clock source selection - \param[in] ck_usart: USART clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2 - \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS - \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL - \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M - \param[out] none - \retval none -*/ -void rcu_usart_clock_config(uint32_t ck_usart) -{ - /* reset the USART0SEL bits and set according to ck_usart */ - RCU_CFG2 &= ~RCU_CFG2_USART0SEL; - RCU_CFG2 |= ck_usart; -} - -/*! - \brief configure the CEC clock source selection - \param[in] ck_cec: CEC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CECSRC_IRC8M_DIV244: CK_CEC select CK_IRC8M/244 - \arg RCU_CECSRC_LXTAL: CK_CEC select CK_LXTAL - \param[out] none - \retval none -*/ -void rcu_cec_clock_config(uint32_t ck_cec) -{ - /* reset the CECSEL bit and set according to ck_cec */ - RCU_CFG2 &= ~RCU_CFG2_CECSEL; - RCU_CFG2 |= ck_cec; -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - /* reset the RTCSRC bits and set according to rtc_clock_source */ - RCU_BDCTL &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL |= rtc_clock_source; -} - -/*! - \brief configure the CK48M clock source selection - \param[in] ck48m_clock_source: CK48M clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock - \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock - \param[out] none - \retval none -*/ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) -{ - uint32_t reg; - - reg = RCU_ADDCTL; - /* reset the CK48MSEL bit and set according to ck48m_clock_source */ - reg &= ~RCU_ADDCTL_CK48MSEL; - RCU_ADDCTL = (reg | ck48m_clock_source); -} - -/*! - \brief configure the HXTAL divider used as input of PLL - \param[in] hxtal_prediv: HXTAL divider used as input of PLL - only one parameter can be selected which is shown as below: - \arg RCU_PLL_PREDVx(x=1..16): HXTAL or IRC48M divided x used as input of PLL - \param[out] none - \retval none -*/ -void rcu_hxtal_prediv_config(uint32_t hxtal_prediv) -{ - uint32_t prediv = 0U; - prediv = RCU_CFG1; - /* reset the HXTALPREDV bits and set according to hxtal_prediv */ - prediv &= ~RCU_CFG1_PREDV; - RCU_CFG1 = (prediv | hxtal_prediv); -} - -/*! - \brief configure the LXTAL drive capability - \param[in] lxtal_dricap: drive capability of LXTAL - only one parameter can be selected which is shown as below: - \arg RCU_LXTAL_LOWDRI: lower driving capability - \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability - \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability - \arg RCU_LXTAL_HIGHDRI: higher driving capability - \param[out] none - \retval none -*/ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) -{ - /* reset the LXTALDRI bits and set according to lxtal_dricap */ - RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI; - RCU_BDCTL |= lxtal_dricap; -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_V12RST: V12 domain power reset flag - \arg RCU_FLAG_OBLRST: option byte loader reset flag - \arg RCU_FLAG_EPRST: external pin reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable - \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief wait until oscillator stabilization flags is SET - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC48M: IRC48M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - switch(osci){ - case RCU_HXTAL: - /* wait until HXTAL is stabilization and osci_stat is not more than timeout */ - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ - reval = SUCCESS; - } - break; - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC28M stable */ - case RCU_IRC28M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){ - reval = SUCCESS; - } - break; - /* wait IRC48M stable */ - case RCU_IRC48M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ - reval = SUCCESS; - } - break; - - default: - break; - } - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC48M: IRC48M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC48M: IRC48M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - switch(osci){ - case RCU_HXTAL: - /* HXTALEN must be reset before enable the oscillator bypass mode */ - reg = RCU_CTL0; - RCU_CTL0 &= ~RCU_CTL0_HXTALEN; - RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS); - break; - case RCU_LXTAL: - /* LXTALEN must be reset before enable the oscillator bypass mode */ - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC28M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - switch(osci){ - case RCU_HXTAL: - /* HXTALEN must be reset before disable the oscillator bypass mode */ - reg = RCU_CTL0; - RCU_CTL0 &= ~RCU_CTL0_HXTALEN; - RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS)); - break; - case RCU_LXTAL: - /* LXTALEN must be reset before disable the oscillator bypass mode */ - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS)); - break; - case RCU_IRC8M: - case RCU_IRC28M: - case RCU_IRC48M: - case RCU_IRC40K: - case RCU_PLL_CK: - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL0 |= RCU_CTL0_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL0 &= ~RCU_CTL0_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) -{ - uint32_t adjust = 0U; - adjust = RCU_CTL0; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - adjust &= ~RCU_CTL0_IRC8MADJ; - RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3)); -} - -/*! - \brief set the IRC28M adjust value - \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval) -{ - uint32_t adjust = 0U; - adjust = RCU_CTL1; - /* reset the IRC28MADJ bits and set according to irc28m_adjval */ - adjust &= ~RCU_CTL1_IRC28MADJ; - RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3)); -} - -/*! - \brief unlock the voltage key - \param[in] none - \param[out] none - \retval none -*/ -void rcu_voltage_key_unlock(void) -{ - /* reset the KEY bits and set 0x1A2B3C4D */ - RCU_VKEY &= ~RCU_VKEY_KEY; - RCU_VKEY |= RCU_VKEY_UNLOCK; -} - -/*! - \brief set voltage in deep sleep mode - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V - \arg RCU_DEEPSLEEP_V_0_7: the core voltage is 0.7V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - /* reset the DSLPVS bits and set according to dsvol */ - RCU_DSV &= ~RCU_DSV_DSLPVS; - RCU_DSV |= dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \arg CK_ADC: ADC clock frequency - \arg CK_CEC: CEC clock frequency - \arg CK_USART: USART clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2, ADC, CEC or USRAT -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U; - uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U; - uint32_t adc_freq = 0U, cec_freq = 0U, usart_freq = 0U; - uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; - /* exponent of AHB, APB1 and APB2 clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* get the value of PLLMF[3:0] */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - pllmf4 = GET_BITS(RCU_CFG0, 27, 27); - pllmf5 = GET_BITS(RCU_CFG1, 31, 31); - /* high 16 bits */ - if(1U == pllmf4){ - pllmf += 17U; - }else{ - if(pllmf == 15U){ - pllmf += 1U; - }else{ - pllmf += 2U; - } - } - if(1U == pllmf5){ - pllmf += 31U; - } - - /* PLL clock source selection, HXTAL or IRC48M or IRC8M/2 */ - pllsel = GET_BITS(RCU_CFG0, 16, 16); - pllpresel = GET_BITS(RCU_CFG1, 30, 30); - if(0U != pllsel){ - prediv = (GET_BITS(RCU_CFG1,0, 3) + 1U); - if(0U == pllpresel){ - cksys_freq = (HXTAL_VALUE / prediv) * pllmf; - }else{ - cksys_freq = (IRC48M_VALUE / prediv) * pllmf; - } - }else{ - cksys_freq = (IRC8M_VALUE >> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock){ - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - case CK_ADC: - /* calculate ADC clock frequency */ - if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){ - if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){ - adc_freq = IRC28M_VALUE >> 1; - }else{ - adc_freq = IRC28M_VALUE; - } - }else{ - /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */ - adcps = GET_BITS(RCU_CFG0, 14, 15); - adcps2 = GET_BITS(RCU_CFG2, 31, 31); - switch(adcps){ - case 0: - if(0U == adcps2){ - adc_freq = apb2_freq / 2U; - }else{ - adc_freq = ahb_freq / 3U; - } - break; - case 1: - if(0U == adcps2){ - adc_freq = apb2_freq / 4U; - }else{ - adc_freq = ahb_freq / 5U; - } - break; - case 2: - if(0U == adcps2){ - adc_freq = apb2_freq / 6U; - }else{ - adc_freq = ahb_freq / 7U; - } - break; - case 3: - if(0U == adcps2){ - adc_freq = apb2_freq / 8U; - }else{ - adc_freq = ahb_freq / 9U; - } - break; - default: - break; - } - } - ck_freq = adc_freq; - break; - case CK_CEC: - /* calculate CEC clock frequency */ - if(RCU_CECSRC_LXTAL != (RCU_CFG2 & RCU_CFG2_CECSEL)){ - cec_freq = IRC8M_VALUE / 244U; - }else{ - cec_freq = LXTAL_VALUE; - } - ck_freq = cec_freq; - break; - case CK_USART: - /* calculate USART clock frequency */ - if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = apb2_freq; - }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = cksys_freq; - }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = LXTAL_VALUE; - }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = IRC8M_VALUE; - }else{ - } - ck_freq = usart_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c deleted file mode 100644 index 5b7a3f59e1..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_rtc.c +++ /dev/null @@ -1,966 +0,0 @@ -/*! - \file gd32f3x0_rtc.c - \brief RTC driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_rtc.h" - -/*! - \brief reset most of the RTC registers - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_deinit(void) -{ - ErrStatus error_status = ERROR; - - /* RTC_TAMP register is not under write protection */ - RTC_TAMP = RTC_REGISTER_RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* reset RTC_CTL register, this can be done without the init mode */ - RTC_CTL &= RTC_REGISTER_RESET; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. - in order to read calendar from shadow register, not the real registers being reset */ - RTC_TIME = RTC_REGISTER_RESET; - RTC_DATE = RTC_DATE_RESET; - - RTC_PSC = RTC_PSC_RESET; - - /* reset RTC_STAT register, also exit init mode. - at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ - RTC_STAT = RTC_STAT_RESET; - - /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */ - RTC_ALRM0TD = RTC_REGISTER_RESET; - RTC_ALRM0SS = RTC_REGISTER_RESET; - - /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ - RTC_SHIFTCTL = RTC_REGISTER_RESET; - RTC_HRFC = RTC_REGISTER_RESET; - - error_status = rtc_register_sync_wait(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief initialize RTC registers - \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - rtc_year: 0x0 - 0x99(BCD format) - rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_date: 0x1 - 0x31(BCD format) - rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - rtc_minute: 0x0 - 0x59(BCD format) - rtc_second: 0x0 - 0x59(BCD format) - rtc_factor_asyn: 0x0 - 0x7F - rtc_factor_syn: 0x0 - 0x7FFF - rtc_am_pm: RTC_AM, RTC_PM - rtc_display_format: RTC_24HOUR, RTC_12HOUR - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) -{ - ErrStatus error_status = ERROR; - uint32_t reg_time = 0x00U, reg_date = 0x00U; - - reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \ - DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \ - DATE_MON(rtc_initpara_struct->rtc_month) | \ - DATE_DAY(rtc_initpara_struct->rtc_date)); - - reg_time = (rtc_initpara_struct->rtc_am_pm| \ - TIME_HR(rtc_initpara_struct->rtc_hour) | \ - TIME_MN(rtc_initpara_struct->rtc_minute) | \ - TIME_SC(rtc_initpara_struct->rtc_second)); - - /* 1st: disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* 2nd: enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \ - PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn)); - - RTC_TIME = (uint32_t)reg_time; - RTC_DATE = (uint32_t)reg_date; - - RTC_CTL &= (uint32_t)(~RTC_CTL_CS); - RTC_CTL |= rtc_initpara_struct->rtc_display_format; - - /* 3rd: exit init mode */ - rtc_init_mode_exit(); - - /* 4th: wait the RSYNF flag to set */ - error_status = rtc_register_sync_wait(); - } - - /* 5th: enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enter RTC init mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init_mode_enter(void) -{ - uint32_t time_index = RTC_INITM_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - /* check whether it has been in init mode */ - if(RESET == (RTC_STAT & RTC_STAT_INITF)){ - RTC_STAT |= RTC_STAT_INITM; - - /* wait until the INITF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_INITF; - }while((--time_index > 0x00U) && (RESET == flag_status)); - - if(RESET != flag_status){ - error_status = SUCCESS; - } - }else{ - error_status = SUCCESS; - } - return error_status; -} - -/*! - \brief exit RTC init mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_init_mode_exit(void) -{ - RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); -} - -/*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow - registers are updated - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_register_sync_wait(void) -{ - volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - if(RESET == (RTC_CTL & RTC_CTL_BPSHAD)){ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* firstly clear RSYNF flag */ - RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); - - /* wait until RSYNF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_RSYNF; - }while((--time_index > 0x00U) && (RESET == flag_status)); - - if(RESET != flag_status){ - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - }else{ - error_status = SUCCESS; - } - - return error_status; -} - -/*! - \brief get current time and date - \param[in] none - \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - rtc_year: 0x0 - 0x99(BCD format) - rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_date: 0x1 - 0x31(BCD format) - rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - rtc_minute: 0x0 - 0x59(BCD format) - rtc_second: 0x0 - 0x59(BCD format) - rtc_factor_asyn: 0x0 - 0x7F - rtc_factor_syn: 0x0 - 0x7FFF - rtc_am_pm: RTC_AM, RTC_PM - rtc_display_format: RTC_24HOUR, RTC_12HOUR - \retval none -*/ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) -{ - uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U; - - temp_tr = (uint32_t)RTC_TIME; - temp_dr = (uint32_t)RTC_DATE; - temp_pscr = (uint32_t)RTC_PSC; - temp_ctlr = (uint32_t)RTC_CTL; - - /* get current time and construct rtc_parameter_struct structure */ - rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr); - rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr); - rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr); - rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); - rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr); - rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr); - rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr); - rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); - rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); - rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); -} - -/*! - \brief get current subsecond value - \param[in] none - \param[out] none - \retval current subsecond value -*/ -uint32_t rtc_subsecond_get(void) -{ - uint32_t reg = 0x00U; - /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ - reg = (uint32_t)RTC_SS; - /* read RTC_DATE to unlock the 3 shadow registers */ - (void) (RTC_DATE); - - return reg; -} - -/*! - \brief configure RTC alarm - \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_alarm_minute: 0x0 - 0x59(BCD format) - rtc_alarm_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \param[out] none - \retval none -*/ -void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time) -{ - uint32_t reg_alrm0td = 0x00U; - - reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \ - rtc_alarm_time->rtc_weekday_or_date | \ - rtc_alarm_time->rtc_am_pm | \ - ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \ - ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \ - ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \ - ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second)); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_ALRM0TD = (uint32_t)reg_alrm0td; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief configure subsecond of RTC alarm - \param[in] mask_subsecond: alarm subsecond mask - only one parameter can be selected which is shown as below: - \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration - \arg RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared - \arg RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared - \arg RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared - \arg RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared - \arg RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared - \arg RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared - \arg RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared - \arg RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared - \arg RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared - \arg RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared - \arg RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared - \arg RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared - \arg RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared - \arg RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared - \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared - \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) - \param[out] none - \retval none -*/ -void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_ALRM0SS = mask_subsecond | subsecond; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief get RTC alarm - \param[in] none - \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_alarm_minute: 0x0 - 0x59(BCD format) - rtc_alarm_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time) -{ - uint32_t reg_alrm0td = 0x00U; - - /* get the value of RTC_ALRM0TD register */ - reg_alrm0td = RTC_ALRM0TD; - - /* get alarm parameters and construct the rtc_alarm_struct structure */ - rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; - rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM); - rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS); - rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td); - rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td); - rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td); - rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td); -} - -/*! - \brief get RTC alarm subsecond - \param[in] none - \param[out] none - \retval RTC alarm subsecond value -*/ -uint32_t rtc_alarm_subsecond_get(void) -{ - return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); -} - -/*! - \brief enable RTC alarm - \param[in] none - \param[out] none - \retval none -*/ -void rtc_alarm_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= RTC_CTL_ALRM0EN; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC alarm - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_alarm_disable(void) -{ - volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the state of alarm */ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); - - /* wait until ALRM0WF flag to be set after the alarm is disabled */ - do{ - flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - }while((--time_index > 0x00U) && (RESET == flag_status)); - - if(RESET != flag_status){ - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC time-stamp - \param[in] edge: specify which edge to detect of time-stamp - only one parameter can be selected which is shown as below: - \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event - \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event - \param[out] none - \retval none -*/ -void rtc_timestamp_enable(uint32_t edge) -{ - uint32_t reg_ctl = 0x00U; - - /* clear the bits to be configured in RTC_CTL */ - reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); - - /* new configuration */ - reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL = (uint32_t)reg_ctl; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC time-stamp - \param[in] none - \param[out] none - \retval none -*/ -void rtc_timestamp_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the TSEN bit */ - RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief get RTC timestamp time and date - \param[in] none - \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains - parameters for RTC time-stamp configuration - members of the structure and the member values are shown as below: - rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_timestamp_date: 0x1 - 0x31(BCD format) - rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_timestamp_minute: 0x0 - 0x59(BCD format) - rtc_timestamp_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) -{ - uint32_t temp_tts = 0x00U, temp_dts = 0x00U; - - /* get the value of time_stamp registers */ - temp_tts = (uint32_t)RTC_TTS; - temp_dts = (uint32_t)RTC_DTS; - - /* get timestamp time and construct the rtc_timestamp_struct structure */ - rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); - rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); - rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); - rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); - rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); - rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); - rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); -} - -/*! - \brief get RTC time-stamp subsecond - \param[in] none - \param[out] none - \retval RTC time-stamp subsecond value -*/ -uint32_t rtc_timestamp_subsecond_get(void) -{ - return ((uint32_t)RTC_SSTS); -} - -/*! - \brief enable RTC tamper - \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains - parameters for RTC tamper configuration - members of the structure and the member values are shown as below: - rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 - rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING - RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH - rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S - rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, - RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, - RTC_FREQ_DIV512, RTC_FREQ_DIV256 - rtc_tamper_precharge_enable: DISABLE, ENABLE - rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C - rtc_tamper_with_timestamp: DISABLE, ENABLE - \param[out] none - \retval none -*/ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source); - - /* tamper filter must be used when the tamper source is voltage level detection */ - RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; - - /* the tamper source is voltage level detection */ - if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE ){ - RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); - - /* check if the tamper pin need precharge, if need, then configure the precharge time */ - if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable){ - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; - }else{ - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time); - } - - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency); - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter); - } - - RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - - if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp){ - /* the tamper event also cause a time-stamp event */ - RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; - } - - /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source)<< RTC_TAMPER_TRIGGER_POS); - } - /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source); -} - -/*! - \brief disable RTC tamper - \param[in] source: specify which tamper source to be disabled - only one parameter can be selected which is shown as below: - \arg RTC_TAMPER0 - \arg RTC_TAMPER1 - \param[out] none - \retval none -*/ -void rtc_tamper_disable(uint32_t source) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~source; - -} - -/*! - \brief enable specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be enabled - only one parameter can be selected which is shown as below: - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enable the interrupts in RTC_CTL register */ - RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* enable the interrupts in RTC_TAMP register */ - RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disble specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be disabled - only one parameter can be selected which is shown as below: - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* disable the interrupts in RTC_CTL register */ - RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* disable the interrupts in RTC_TAMP register */ - RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief check specified flag - \param[in] flag: specify which flag to check - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_RECALIBRATION: recalibration pending flag - \arg RTC_FLAG_TAMP1: tamper 1 event flag - \arg RTC_FLAG_TAMP0: tamper 0 event flag - \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag - \arg RTC_FLAG_TIMESTAMP: time-stamp event flag - \arg RTC_FLAG_ALARM0: alarm event flag - \arg RTC_FLAG_INIT: init mode event flag - \arg RTC_FLAG_RSYN: time and date registers synchronized event flag - \arg RTC_FLAG_YCM: year parameter configured event flag - \arg RTC_FLAG_SHIFT: shift operation pending flag - \arg RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - FlagStatus flag_state = RESET; - - if(RESET != (RTC_STAT & flag)){ - flag_state = SET; - } - return flag_state; -} - -/*! - \brief clear specified flag - \param[in] flag: specify which flag to clear - \arg RTC_FLAG_TAMP1: tamper 1 event flag - \arg RTC_FLAG_TAMP0: tamper 0 event flag - \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag - \arg RTC_FLAG_TIMESTAMP: time-stamp event flag - \arg RTC_FLAG_ALARM0: alarm event flag - \arg RTC_FLAG_RSYN: time and date registers synchronized event flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - RTC_STAT &= (uint32_t)(~flag); -} - -/*! - \brief configure rtc alternate output source - \param[in] source: specify signal to output - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal - \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 1Hz signal - \arg RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high - \arg RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low - \param[in] mode: specify the output pin (PC13) mode when output alarm signal - only one parameter can be selected which is shown as below: - \arg RTC_ALARM_OUTPUT_OD: open drain mode - \arg RTC_ALARM_OUTPUT_PP: push pull mode - \param[out] none - \retval none -*/ -void rtc_alter_output_config(uint32_t source, uint32_t mode) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS); - - RTC_CTL |= (uint32_t)(source); - - /* alarm output */ - if(RESET != (source & RTC_OS_ENABLE)){ - RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL); - RTC_TAMP |= (uint32_t)(mode); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - - -/*! - \brief configure RTC calibration register - \param[in] window: select calibration window - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz - \param[in] plus: add RTC clock or not - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock - \arg RTC_CALIBRATION_PLUS_RESET: no effect - \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) -{ - uint32_t time_index = RTC_HRFC_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a calibration operation is ongoing */ - do{ - flag_status = RTC_STAT & RTC_STAT_SCPF; - }while((--time_index > 0x00U) && (RESET != flag_status)); - - if(RESET == flag_status){ - RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief ajust the daylight saving time by adding or substracting one hour from the current time - \param[in] operation: hour ajustment operation - only one parameter can be selected which is shown as below: - \arg RTC_CTL_A1H: add one hour - \arg RTC_CTL_S1H: substract one hour - \param[out] none - \retval none -*/ -void rtc_hour_adjust(uint32_t operation) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= (uint32_t)(operation); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief ajust RTC second or subsecond value of current time - \param[in] add: add 1s to current time or not - only one parameter can be selected which is shown as below: - \arg RTC_SHIFT_ADD1S_RESET: no effect - \arg RTC_SHIFT_ADD1S_SET: add 1s to current time - \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) -{ - uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - uint32_t temp=0U; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a shift operation is ongoing */ - do{ - flag_status = RTC_STAT & RTC_STAT_SOPF; - }while((--time_index > 0x00U) && (RESET != flag_status)); - - temp = RTC_CTL & RTC_CTL_REFEN; - /* check if the function of reference clock detection is disabled */ - if((RESET == flag_status) && (RESET == temp)){ - RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); - error_status = rtc_register_sync_wait(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief enable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_enable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL |= (uint32_t)RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief disable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_disable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - - diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c deleted file mode 100644 index 3aa2f3deb3..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_spi.c +++ /dev/null @@ -1,792 +0,0 @@ -/*! - \file gd32f3x0_spi.c - \brief SPI driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_spi.h" - -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph){ - case SPI0: - /* reset SPI0 and I2S0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - default : - break; - } -} - -/*! - \brief initialize the parameters of SPI struct with the default values - \param[in] spi_struct: SPI parameter stuct - \param[out] none - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct* spi_struct) -{ - /* set the SPI struct with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; -} - -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval none -*/ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ - uint32_t reg = 0U; - reg = SPI_CTL0(spi_periph); - reg &= SPI_INIT_MASK; - - /* select SPI as master or slave */ - reg |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg |= spi_struct->trans_mode; - /* select SPI frame size */ - reg |= spi_struct->frame_size; - /* select SPI NSS use hardware or software */ - reg |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg |= spi_struct->endian; - /* select SPI polarity and phase */ - reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg |= spi_struct->prescale; - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg; - - /* select SPI mode */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - - -#ifdef GD32F350 -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPI0 - \param[in] mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg = 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPI0 - \param[in] audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; - - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout){ - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)){ - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - -/*! - \brief enable I2S - \param[in] spi_periph: SPI0 - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPI0 - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -#endif /* GD32F350 */ - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \param[out] none - \retval none -*/ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* confige SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= (uint32_t)frame_format; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - SPI_DATA(spi_periph) = (uint32_t)data; -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - return ((uint16_t)SPI_DATA(spi_periph)); -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set CRC polynomial - \param[in] spi_periph: SPIx(x=0,1) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1) - \param[in] crc: SPI crc value - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) -{ - if(SPI_CRC_TX == crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - -/*! - \brief enable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nssp_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; -} - -/*! - \brief disable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nssp_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); -} - -/*! - \brief enable quad wire SPI - \param[in] spi_periph: SPI1 - \param[out] none - \retval none -*/ -void qspi_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; -} - -/*! - \brief disable quad wire SPI - \param[in] spi_periph: SPI1 - \param[out] none - \retval none -*/ -void qspi_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); -} - -/*! - \brief enable quad wire SPI write - \param[in] spi_periph: SPI1 - \param[out] none - \retval none -*/ -void qspi_write_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); -} - -/*! - \brief enable quad wire SPI read - \param[in] spi_periph: SPI1 - \param[out] none - \retval none -*/ -void qspi_read_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; -} - -/*! - \brief enable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPI1 - \param[out] none - \retval none -*/ -void qspi_io23_output_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; -} - - /*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPI1 - \param[out] none - \retval none -*/ - void qspi_io23_output_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt flag status - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI/I2S format error interrupt */ - case SPI_I2S_INT_FLAG_FERR: - reg1 = reg1 & SPI_STAT_FERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - /*get SPI/I2S interrupt flag status */ - if((0U != reg1) && (0U != reg2)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[in] flag: SPI/I2S flag status - one or more parameters can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(RESET != (SPI_STAT(spi_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c deleted file mode 100644 index 7a4aef5fc6..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_syscfg.c +++ /dev/null @@ -1,227 +0,0 @@ -/*! - \file gd32f3x0_syscfg.c - \brief SYSCFG driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_syscfg.h" - -/*! - \brief reset the SYSCFG registers - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_deinit(void) -{ - rcu_periph_reset_enable(RCU_CFGCMPRST); - rcu_periph_reset_disable(RCU_CFGCMPRST); -} - -/*! - \brief enable the DMA channels remapping - \param[in] syscfg_dma_remap: specify the DMA channels to remap - one or more parameters can be selected which is shown as below: - \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) - \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) - \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) - \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) - \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 - \param[out] none - \retval none -*/ -void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap) -{ - SYSCFG_CFG0 |= syscfg_dma_remap; -} - -/*! - \brief disable the DMA channels remapping - \param[in] syscfg_dma_remap: specify the DMA channels to remap - one or more parameters can be selected which is shown as below: - \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) - \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) - \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) - \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) - \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 - \param[out] none - \retval none -*/ -void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap) -{ - SYSCFG_CFG0 &= ~syscfg_dma_remap; -} - -/*! - \brief enable PB9 high current capability - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_high_current_enable(void) -{ - SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE; -} - -/*! - \brief disable PB9 high current capability - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_high_current_disable(void) -{ - SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE; -} - -/*! - \brief configure the GPIO pin as EXTI Line - \param[in] exti_port: specify the GPIO port used in EXTI - only one parameter can be selected which is shown as below: - \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,F): EXTI GPIO port - \param[in] exti_pin: specify the EXTI line - only one parameter can be selected which is shown as below: - \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin - \param[out] none - \retval none -*/ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) -{ - uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); - uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); - - switch(exti_pin / EXTI_SS_JSTEP){ - case EXTISS0: - /* clear EXTI source line(0..3) */ - SYSCFG_EXTISS0 &= clear_exti_mask; - /* configure EXTI soure line(0..3) */ - SYSCFG_EXTISS0 |= config_exti_mask; - break; - case EXTISS1: - /* clear EXTI soure line(4..7) */ - SYSCFG_EXTISS1 &= clear_exti_mask; - /* configure EXTI soure line(4..7) */ - SYSCFG_EXTISS1 |= config_exti_mask; - break; - case EXTISS2: - /* clear EXTI soure line(8..11) */ - SYSCFG_EXTISS2 &= clear_exti_mask; - /* configure EXTI soure line(8..11) */ - SYSCFG_EXTISS2 |= config_exti_mask; - break; - case EXTISS3: - /* clear EXTI soure line(12..15) */ - SYSCFG_EXTISS3 &= clear_exti_mask; - /* configure EXTI soure line(12..15) */ - SYSCFG_EXTISS3 |= config_exti_mask; - break; - default: - break; - } -} - -/*! - \brief connect TIMER0/14/15/16 break input to the selected parameter - \param[in] syscfg_lock: Specify the parameter to be connected - one or more parameters can be selected which is shown as below: - \arg SYSCFG_LOCK_LOCKUP: Cortex-M4 lockup output connected to the break input - \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input - \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input - \param[out] none - \retval none -*/ -void syscfg_lock_config(uint32_t syscfg_lock) -{ - SYSCFG_CFG2 |= syscfg_lock; -} - -/*! - \brief check if the specified flag in SYSCFG_CFG2 is set or not. - \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check. - \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. - \param[out] none - \retval the syscfg_flag state returned (SET or RESET). - */ -FlagStatus syscfg_flag_get(uint32_t syscfg_flag) -{ - if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the flag in SYSCFG_CFG2 by writing 1. - \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear. - \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. - \param[out] none - \retval none -*/ -void syscfg_flag_clear(uint32_t syscfg_flag) -{ - SYSCFG_CFG2 |= (uint32_t) syscfg_flag; -} - -/*! - \brief configure the I/O compensation cell - \param[in] syscfg_compensation: specifies the I/O compensation cell mode - only one parameter can be selected which is shown as below: - \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled - \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled - \param[out] none - \retval none -*/ -void syscfg_compensation_config(uint32_t syscfg_compensation) -{ - uint32_t reg; - - reg = SYSCFG_CPSCTL; - /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */ - reg &= ~SYSCFG_CPSCTL_CPS_EN; - SYSCFG_CPSCTL = (reg | syscfg_compensation); -} - -/*! - \brief check if the I/O compensation cell ready flag is set or not - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus syscfg_cps_rdy_flag_get(void) -{ - if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){ - return SET; - }else{ - return RESET; - } -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c deleted file mode 100644 index 0e34c59618..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_timer.c +++ /dev/null @@ -1,2063 +0,0 @@ -/*! - \file gd32f3x0_timer.c - \brief TIMER driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#include "gd32f3x0_timer.h" - -/*! - \brief deinit a TIMER - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph){ - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER1: - /* reset TIMER1 */ - rcu_periph_reset_enable(RCU_TIMER1RST); - rcu_periph_reset_disable(RCU_TIMER1RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; -#ifdef GD32F350 - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; -#endif - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; - case TIMER14: - /* reset TIMER14 */ - rcu_periph_reset_enable(RCU_TIMER14RST); - rcu_periph_reset_disable(RCU_TIMER14RST); - break; - case TIMER15: - /* reset TIMER15 */ - rcu_periph_reset_enable(RCU_TIMER15RST); - rcu_periph_reset_disable(RCU_TIMER15RST); - break; - case TIMER16: - /* reset TIMER16 */ - rcu_periph_reset_enable(RCU_TIMER16RST); - rcu_periph_reset_disable(RCU_TIMER16RST); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct* initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[in] timer_initpara: init parameter struct - prescaler: prescaler value of the counter clock,0~65535 - alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN - period: counter auto reload value,(TIMER1 32 bit) - clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph) - || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; - } - - if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a TIMER - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a TIMER - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0..2) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0..2) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0..2) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[in] prescaler: prescaler value - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,15,16) - \param[in] repetition: the counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[in] autoreload: the counter auto-reload value - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[in] counter: the counter value - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph, uint32_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint8_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint8_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER OCPRE clear source selection - \param[in] timer_periph: TIMERx(x=0..2) - \param[in] ocpreclear: - only one parameter can be selected which is shown as below: - \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input - \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF - \param[out] none - \retval none -*/ -void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear) -{ - if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC; - }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..2,13..16) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..2,14) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..2) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..2) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..2,14) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source disable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt disable, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0..2,13..16) - \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0..2,14) - \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0..2) - \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0..2) - \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,14..16) - \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0..2,14) - \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..2,13..16) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..2,14) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..2) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..2) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0..2,14) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..2,13..16) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..2,14) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..2) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..2) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0..2,14) - \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2) - \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..2,13..16),TIMER5 just for GD32F350 - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..2,13..16) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..2,14) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..2) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..2) - \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0..2,14) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..2,13..16) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..2,14) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..2) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..2) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)flag); -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to enable - one or more parameters can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 - \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16) - \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14) - \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2) - \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2) - \arg TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14) - \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to disable - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0..2,14..16),TIMER5 just for GD32F350 - \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0..2,14..16) - \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0..2,14) - \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0..2) - \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0..2) - \arg TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14) - \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0..2,14) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0..2,14..16) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: TIMERx(x=0..2,14..16) - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..2,14) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..2) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..2,14) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..2) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..2) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..2,14..16) - \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB, TIMERx(x=0..2,14..16) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: please refer to the following parameters - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..2,13..16), TIMER5 just for GD32F350 - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..2,13..16) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..2,14) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..2) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..2) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..2,14) - \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| - ((uint32_t)(breakpara->ideloffstate))| - ((uint32_t)(breakpara->deadtime))| - ((uint32_t)(breakpara->breakpolarity))| - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode))| - ((uint32_t)(breakpara->breakstate))) ; -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief configure TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl){ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..2)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - - if(TIMER0 == timer_periph){ - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); - } - - if(TIMER14 == timer_periph){ - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - } - - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - - if(TIMER0 == timer_periph){ - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); - } - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(ocpara->outputstate << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - - if(TIMER0 == timer_periph){ - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); - } - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] pulse: channel output pulse value,0~65535 - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel2(TIMERx(x=1,2)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0)) - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P and CH3NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..2)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel){ - /* read TIMER channel 0 capture compare register value */ - case TIMER_CH_0: - count_value = TIMER_CH0CV(timer_periph); - break; - /* read TIMER channel 1 capture compare register value */ - case TIMER_CH_1: - count_value = TIMER_CH1CV(timer_periph); - break; - /* read TIMER channel 2 capture compare register value */ - case TIMER_CH_2: - count_value = TIMER_CH2CV(timer_periph); - break; - /* read TIMER channel 3 capture compare register value */ - case TIMER_CH_3: - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ - icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ - icpolarity = TIMER_IC_POLARITY_RISING; - } - - /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ - icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel){ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0..2) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint8_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2)) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..2,14)) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..2,14)) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..2,14)) - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..2)) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0..2,14),TIMER5 just for GD32F350 - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..2,14),TIMER5 just for GD32F350) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..2,14)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..2,14)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..2,14)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..2,14)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..2,14)) - \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..2)) - \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..2)) - \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..2)) - \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..2,14)) - \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..2,14)) - \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..2,14)) - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0..2,14)) - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint8_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0..2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..2) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, - uint16_t ic0polarity, uint16_t ic1polarity) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..2)) - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph, intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..2,14) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active high or rising edge active - \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active - \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, - uint16_t extpolarity, uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0..2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..2) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief configure TIMER channel remap function - \param[in] timer_periph: TIMERx(x=13) - \param[in] remap: - only one parameter can be selected which is shown as below: - \arg TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0) - \arg TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK - \arg TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock - \arg TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL - \param[out] none - \retval none -*/ -void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) -{ - TIMER_IRMP(timer_periph) = (uint32_t)remap; -} - -/*! - \brief configure TIMER write CHxVAL register selection - \param[in] timer_periph: TIMERx(x=0..2,13..16) - \param[in] ccsel: - only one parameter can be selected which is shown as below: - \arg TIMER_CHVSEL_DISABLE: no effect - \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored - \param[out] none - \retval none -*/ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) -{ - if(TIMER_CHVSEL_ENABLE == ccsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CHVSEL_DISABLE == ccsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER output value selection - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] outsel: - only one parameter can be selected which is shown as below: - \arg TIMER_OUTSEL_DISABLE: no effect - \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled - \param[out] none - \retval none -*/ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) -{ - if(TIMER_OUTSEL_ENABLE == outsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == outsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - }else{ - /* illegal parameters */ - } -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c deleted file mode 100644 index 5a0bf95fec..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_tsi.c +++ /dev/null @@ -1,686 +0,0 @@ -/*! - \file gd32f3x0_tsi.c - \brief TSI driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_tsi.h" - -/*! - \brief reset TSI peripheral - \param[in] none - \param[out] none - \retval none -*/ -void tsi_deinit(void) -{ - rcu_periph_reset_enable(RCU_TSIRST); - rcu_periph_reset_disable(RCU_TSIRST); -} - -/*! - \brief initialize TSI plus prescaler,charge plus,transfer plus,max cycle number - \param[in] prescaler: CTCLK clock division factor - only one parameter can be selected which is shown as below: - \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK - \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2 - \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4 - \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8 - \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16 - \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32 - \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64 - \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128 - \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256 - \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512 - \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024 - \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048 - \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096 - \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192 - \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384 - \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768 - \param[in] charge_duration: charge state duration time - only one parameter can be selected which is shown as below: - \arg TSI_CHARGE_1CTCLK(x=1..16): the duration time of charge state is x CTCLK - \param[in] transfer_duration: charge transfer state duration time - only one parameter can be selected which is shown as below: - \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK - \param[in] max_number: max cycle number - only one parameter can be selected which is shown as below: - \arg TSI_MAXNUM255: the max cycle number of a sequence is 255 - \arg TSI_MAXNUM511: the max cycle number of a sequence is 511 - \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023 - \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047 - \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095 - \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191 - \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383 - \param[out] none - \retval none -*/ -void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number) -{ - uint32_t ctl0,ctl1; - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - if(TSI_CTCDIV_DIV256 > prescaler){ - /* config TSI_CTL0 */ - ctl0 = TSI_CTL0; - /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ - ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN); - ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number); - TSI_CTL0 = ctl0; - - /* config TSI_CTL1 */ - ctl1 = TSI_CTL1; - ctl1 &= ~TSI_CTL1_CTCDIV; - TSI_CTL1 = ctl1; - }else{ - /* config TSI_CTL0 */ - ctl0 = TSI_CTL0; - prescaler &= ~0x08U; - /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ - ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT|TSI_CTL0_MCN); - ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration|max_number); - TSI_CTL0 = ctl0; - - /* config TSI_CTL1 */ - ctl1 = TSI_CTL1; - ctl1 |= TSI_CTL1_CTCDIV; - TSI_CTL1 = ctl1; - } - } -} - -/*! - \brief enable TSI module - \param[in] none - \param[out] none - \retval none -*/ -void tsi_enable(void) -{ - TSI_CTL0 |= TSI_CTL0_TSIEN; -} - -/*! - \brief disable TSI module - \param[in] none - \param[out] none - \retval none -*/ -void tsi_disable(void) -{ - TSI_CTL0 &= ~TSI_CTL0_TSIEN; -} - -/*! - \brief enable sample pin - \param[in] sample: sample pin - one or more parameters can be selected which are shown as below: - \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3):pin y of group x is sample pin - \param[out] none - \retval none -*/ -void tsi_sample_pin_enable(uint32_t sample) -{ - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - TSI_SAMPCFG |= sample; - } -} - -/*! - \brief disable sample pin - \param[in] sample: sample pin - one or more parameters can be selected which are shown as below: - \arg TSI_SAMPCFG_GxPy( x=0..5,y=0..3): pin y of group x is sample pin - \param[out] none - \retval none -*/ -void tsi_sample_pin_disable(uint32_t sample) -{ - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - TSI_SAMPCFG &= ~sample; - } -} - -/*! - \brief enable channel pin - \param[in] channel: channel pin - one or more parameters can be selected which are shown as below: - \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x - \param[out] none - \retval none -*/ -void tsi_channel_pin_enable(uint32_t channel) -{ - TSI_CHCFG |= channel; -} - -/*! - \brief disable channel pin - \param[in] channel: channel pin - one or more parameters can be selected which are shown as below: - \arg TSI_CHCFG_GxPy( x=0..5,y=0..3): pin y of group x - \param[out] none - \retval none -*/ -void tsi_channel_pin_disable(uint32_t channel) -{ - TSI_CHCFG &= ~channel; -} - -/*! - \brief configure TSI triggering by software - \param[in] none - \param[out] none - \retval none -*/ -void tsi_sofeware_mode_config(void) -{ - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - TSI_CTL0 &= ~TSI_CTL0_TRGMOD; - } -} - -/*! - \brief start a charge-transfer sequence when TSI is in software trigger mode - \param[in] none - \param[out] none - \retval none -*/ -void tsi_software_start(void) -{ - TSI_CTL0 |= TSI_CTL0_TSIS; -} - -/*! - \brief stop a charge-transfer sequence when TSI is in software trigger mode - \param[in] none - \param[out] none - \retval none -*/ -void tsi_software_stop(void) -{ - TSI_CTL0 &= ~TSI_CTL0_TSIS; -} - -/*! - \brief configure TSI triggering by hardware - \param[in] trigger_edge: the edge type in hardware trigger mode - only one parameter can be selected which is shown as below: - \arg TSI_FALLING_TRIGGER: falling edge trigger TSI charge transfer sequence - \arg TSI_RISING_TRIGGER: rising edge trigger TSI charge transfer sequence - \param[out] none - \retval none -*/ -void tsi_hardware_mode_config(uint8_t trigger_edge) -{ - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - /*enable hardware mode*/ - TSI_CTL0 |= TSI_CTL0_TRGMOD; - /*configure the edge type in hardware trigger mode*/ - if(TSI_FALLING_TRIGGER == trigger_edge){ - TSI_CTL0 &= ~TSI_CTL0_EGSEL; - }else{ - TSI_CTL0 |= TSI_CTL0_EGSEL; - } - } -} - -/*! - \brief configure TSI pin mode when charge-transfer sequence is IDLE - \param[in] pin_mode: pin mode when charge-transfer sequence is IDLE - only one parameter can be selected which is shown as below: - \arg TSI_OUTPUT_LOW: TSI pin will output low when IDLE - \arg TSI_INPUT_FLOATING: TSI pin will keep input_floating when IDLE - \param[out] none - \retval none -*/ -void tsi_pin_mode_config(uint8_t pin_mode) -{ - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - if(TSI_OUTPUT_LOW == pin_mode){ - TSI_CTL0 &= ~TSI_CTL0_PINMOD; - }else{ - TSI_CTL0 |= TSI_CTL0_PINMOD; - } - } -} - -/*! - \brief configure extend charge state - \param[in] extend: enable or disable extend charge state - only one parameter can be selected which is shown as below: - \arg ENABLE: enable extend charge state - \arg DISABLE: disable extend charge state - \param[in] prescaler: ECCLK clock division factor - only one parameter can be selected which is shown as below: - \arg TSI_EXTEND_DIV1: fECCLK = fHCLK - \arg TSI_EXTEND_DIV2: fECCLK = fHCLK/2 - \arg TSI_EXTEND_DIV3: fECCLK = fHCLK/3 - \arg TSI_EXTEND_DIV4: fECCLK = fHCLK/4 - \arg TSI_EXTEND_DIV5: fECCLK = fHCLK/5 - \arg TSI_EXTEND_DIV6: fECCLK = fHCLK/6 - \arg TSI_EXTEND_DIV7: fECCLK = fHCLK/7 - \arg TSI_EXTEND_DIV8: fECCLK = fHCLK/8 - \param[in] max_duration: value range 1...128,extend charge state maximum duration time is 1*tECCLK~128*tECCLK - \param[out] none - \retval none -*/ -void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration) -{ - uint32_t ctl0,ctl1; - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - if(DISABLE == extend){ - /*disable extend charge state*/ - TSI_CTL0 &= ~TSI_CTL0_ECEN; - }else{ - if(TSI_EXTEND_DIV3 > prescaler){ - /*configure extend charge state maximum duration time*/ - ctl0 = TSI_CTL0; - ctl0 &= ~TSI_CTL0_ECDT; - ctl0 |= TSI_EXTENDMAX((max_duration-1U)); - TSI_CTL0 = ctl0; - /*configure ECCLK clock division factor*/ - ctl0 = TSI_CTL0; - ctl0 &= ~TSI_CTL0_ECDIV; - ctl0 |= (uint32_t)prescaler<<15U; - TSI_CTL0 = ctl0; - /*enable extend charge state*/ - TSI_CTL0 |= TSI_CTL0_ECEN; - }else{ - /*configure extend charge state maximum duration time*/ - ctl0 = TSI_CTL0; - ctl0 &= ~TSI_CTL0_ECDT; - ctl0 |= TSI_EXTENDMAX((max_duration-1U)); - TSI_CTL0 = ctl0; - /*configure ECCLK clock division factor*/ - ctl0 = TSI_CTL0; - ctl0 &= ~TSI_CTL0_ECDIV; - ctl0 |= (prescaler & 0x01U)<<15U; - TSI_CTL0 = ctl0; - ctl1 = TSI_CTL1; - ctl1 &= ~TSI_CTL1_ECDIV; - ctl1 |= (prescaler & 0x06U)<<28U; - TSI_CTL1 = ctl1; - /*enable extend charge state*/ - TSI_CTL0 |= TSI_CTL0_ECEN; - } - } - } -} - -/*! - \brief configure charge plus and transfer plus - \param[in] prescaler: CTCLK clock division factor - only one parameter can be selected which is shown as below: - \arg TSI_CTCDIV_DIV1: fCTCLK = fHCLK - \arg TSI_CTCDIV_DIV2: fCTCLK = fHCLK/2 - \arg TSI_CTCDIV_DIV4: fCTCLK = fHCLK/4 - \arg TSI_CTCDIV_DIV8: fCTCLK = fHCLK/8 - \arg TSI_CTCDIV_DIV16: fCTCLK = fHCLK/16 - \arg TSI_CTCDIV_DIV32: fCTCLK = fHCLK/32 - \arg TSI_CTCDIV_DIV64: fCTCLK = fHCLK/64 - \arg TSI_CTCDIV_DIV128: fCTCLK = fHCLK/128 - \arg TSI_CTCDIV_DIV256: fCTCLK = fHCLK/256 - \arg TSI_CTCDIV_DIV512: fCTCLK = fHCLK/512 - \arg TSI_CTCDIV_DIV1024: fCTCLK = fHCLK/1024 - \arg TSI_CTCDIV_DIV2048: fCTCLK = fHCLK/2048 - \arg TSI_CTCDIV_DIV4096: fCTCLK = fHCLK/4096 - \arg TSI_CTCDIV_DIV8192: fCTCLK = fHCLK/8192 - \arg TSI_CTCDIV_DIV16384: fCTCLK = fHCLK/16384 - \arg TSI_CTCDIV_DIV32768: fCTCLK = fHCLK/32768 - \param[in] charge_duration: charge state duration time - only one parameter can be selected which is shown as below: - \arg TSI_CHARGE_xCTCLK(x=1..16): the duration time of charge state is x CTCLK - \param[in] transfer_duration: charge transfer state duration time - only one parameter can be selected which is shown as below: - \arg TSI_TRANSFER_xCTCLK(x=1..16): the duration time of transfer state is x CTCLK - \param[out] none - \retval none -*/ -void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration) -{ - uint32_t ctl0,ctl1; - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - if(TSI_CTCDIV_DIV256 > prescaler){ - /* config TSI_CTL0 */ - ctl0 = TSI_CTL0; - /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ - ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT); - ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration); - TSI_CTL0 = ctl0; - - /* config TSI_CTL1 */ - ctl1 = TSI_CTL1; - ctl1 &= ~TSI_CTL1_CTCDIV; - TSI_CTL1 = ctl1; - }else{ - /* config TSI_CTL */ - ctl0 = TSI_CTL0; - prescaler &= ~0x08U; - /*configure TSI clock division factor,charge state duration time,charge transfer state duration time */ - ctl0 &= ~(TSI_CTL0_CTCDIV|TSI_CTL0_CTDT|TSI_CTL0_CDT); - ctl0 |= ((prescaler<<12U)|charge_duration|transfer_duration); - TSI_CTL0 = ctl0; - - /* config TSI_CTL2 */ - ctl1 = TSI_CTL1; - ctl1 |= TSI_CTL1_CTCDIV; - TSI_CTL1 = ctl1; - } - } -} - -/*! - \brief configure the max cycle number of a charge-transfer sequence - \param[in] max_number: max cycle number - only one parameter can be selected which is shown as below: - \arg TSI_MAXNUM255: the max cycle number of a sequence is 255 - \arg TSI_MAXNUM511: the max cycle number of a sequence is 511 - \arg TSI_MAXNUM1023: the max cycle number of a sequence is 1023 - \arg TSI_MAXNUM2047: the max cycle number of a sequence is 2047 - \arg TSI_MAXNUM4095: the max cycle number of a sequence is 4095 - \arg TSI_MAXNUM8191: the max cycle number of a sequence is 8191 - \arg TSI_MAXNUM16383: the max cycle number of a sequence is 16383 - \param[out] none - \retval none -*/ -void tsi_max_number_config(uint32_t max_number) -{ - if(RESET == (TSI_CTL0 & TSI_CTL0_TSIS)){ - uint32_t maxnum; - maxnum = TSI_CTL0; - /*configure the max cycle number of a charge-transfer sequence*/ - maxnum &= ~TSI_CTL0_MCN; - maxnum |= max_number; - TSI_CTL0 = maxnum; - } -} - -/*! - \brief switch on hysteresis pin - \param[in] group_pin: select pin which will be switched on hysteresis - one or more parameters can be selected which are shown as below: - \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch on hysteresis - \param[out] none - \retval none -*/ -void tsi_hysteresis_on(uint32_t group_pin) -{ - TSI_PHM |= group_pin; -} - -/*! - \brief switch off hysteresis pin - \param[in] group_pin: select pin which will be switched off hysteresis - one or more parameters can be selected which are shown as below: - \arg TSI_PHM_GxPy(x=0..5,y=0..3): pin y of group x switch off hysteresis - \param[out] none - \retval none -*/ -void tsi_hysteresis_off(uint32_t group_pin) -{ - TSI_PHM &= ~group_pin; -} - -/*! - \brief switch on analog pin - \param[in] group_pin: select pin which will be switched on analog - one or more parameters can be selected which are shown as below: - \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch on analog - \param[out] none - \retval none -*/ -void tsi_analog_on(uint32_t group_pin) -{ - TSI_ASW |= group_pin; -} - -/*! - \brief switch off analog pin - \param[in] group_pin: select pin which will be switched off analog - one or more parameters can be selected which are shown as below: - \arg TSI_ASW_GxPy(x=0..5,y=0..3):pin y of group x switch off analog - \param[out] none - \retval none -*/ -void tsi_analog_off(uint32_t group_pin) -{ - TSI_ASW &= ~group_pin; -} - -/*! - \brief enable TSI interrupt - \param[in] source: select interrupt which will be enabled - only one parameter can be selected which is shown as below: - \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt enable - \arg TSI_INT_MNERR: max cycle number error interrupt enable - \param[out] none - \retval none -*/ -void tsi_interrupt_enable(uint32_t source) -{ - TSI_INTEN |= source; -} - -/*! - \brief disable TSI interrupt - \param[in] source: select interrupt which will be disabled - only one parameter can be selected which is shown as below: - \arg TSI_INT_CCTCF: charge-transfer complete flag interrupt disable - \arg TSI_INT_MNERR: max cycle number error interrupt disable - \param[out] none - \retval none -*/ -void tsi_interrupt_disable(uint32_t source) -{ - TSI_INTEN &= ~source; -} - -/*! - \brief clear TSI interrupt flag - \param[in] flag: select flag which will be cleared - only one parameter can be selected which is shown as below: - \arg TSI_INT_FLAG_CTCF_CLR: clear charge-transfer complete flag - \arg TSI_INT_FLAG_MNERR_CLR: clear max cycle number error - \param[out] none - \retval none -*/ -void tsi_interrupt_flag_clear(uint32_t flag) -{ - TSI_INTC |= flag; -} - -/*! - \brief get TSI interrupt flag - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg TSI_INT_FLAG_CTCF: charge-transfer complete flag - \arg TSI_INT_FLAG_MNERR: max Cycle Number Error - \param[out] none - \retval FlagStatus:SET or RESET -*/ -FlagStatus tsi_interrupt_flag_get(uint32_t flag) -{ - uint32_t interrupt_enable = 0U,interrupt_flag = 0U; - interrupt_flag = (TSI_INTF & flag); - interrupt_enable = (TSI_INTEN & flag); - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag - \param[in] flag: select flag which will be cleared - only one parameter can be selected which is shown as below: - \arg TSI_FLAG_CTCF_CLR: clear charge-transfer complete flag - \arg TSI_FLAG_MNERR_CLR: clear max cycle number error - \param[out] none - \retval none -*/ -void tsi_flag_clear(uint32_t flag) -{ - TSI_INTC |= flag; -} - -/*! - \brief get flag - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg TSI_FLAG_CTCF: charge-transfer complete flag - \arg TSI_FLAG_MNERR: max Cycle Number Error - \param[out] none - \retval FlagStatus:SET or RESET -*/ -FlagStatus tsi_flag_get(uint32_t flag) -{ - FlagStatus flag_status; - if(TSI_INTF & flag){ - flag_status = SET; - }else{ - flag_status = RESET; - } - return flag_status; -} - -/*! - \brief enbale group - \param[in] group: select group to be enabled - one or more parameters can be selected which are shown as below: - \arg TSI_GCTL_GEx(x=0..5): the x group will be enabled - \param[out] none - \retval none -*/ -void tsi_group_enable(uint32_t group) -{ - TSI_GCTL |= group; -} - -/*! - \brief disbale group - \param[in] group: select group to be disabled - one or more parameters can be selected which are shown as below: - \arg TSI_GCTL_GEx(x=0..5):the x group will be disabled - \param[out] none - \retval none -*/ -void tsi_group_disable(uint32_t group) -{ - TSI_GCTL &= ~group; -} - -/*! - \brief get group complete status - \param[in] group: select group - one or more parameters can be selected which are shown as below: - \arg TSI_GCTL_GCx(x=0..5): get the complete status of group x - \param[out] none - \retval FlagStatus: group complete status,SET or RESET -*/ -FlagStatus tsi_group_status_get(uint32_t group) -{ - FlagStatus flag_status; - if(TSI_GCTL & group){ - flag_status = SET; - }else{ - flag_status = RESET; - } - return flag_status; -} - -/*! - \brief get the cycle number for group0 as soon as a charge-transfer sequence completes - \param[in] none - \param[out] none - \retval group0 cycle number -*/ -uint16_t tsi_group0_cycle_get(void) -{ - return (uint16_t)TSI_G0CYCN; -} - -/*! - \brief get the cycle number for group1 as soon as a charge-transfer sequence completes - \param[in] none - \param[out] none - \retval group1 cycle number -*/ -uint16_t tsi_group1_cycle_get(void) -{ - return (uint16_t)TSI_G1CYCN; -} - -/*! - \brief get the cycle number for group2 as soon as a charge-transfer sequence completes - \param[in] none - \param[out] none - \retval group2 cycle number -*/ -uint16_t tsi_group2_cycle_get(void) -{ - return (uint16_t)TSI_G2CYCN; -} - -/*! - \brief get the cycle number for group3 as soon as a charge-transfer sequence completes - \param[in] none - \param[out] none - \retval group3 cycle number -*/ -uint16_t tsi_group3_cycle_get(void) -{ - return (uint16_t)TSI_G3CYCN; -} - -/*! - \brief get the cycle number for group4 as soon as a charge-transfer sequence completes - \param[in] none - \param[out] none - \retval group4 cycle number -*/ -uint16_t tsi_group4_cycle_get(void) -{ - return (uint16_t)TSI_G4CYCN; -} - -/*! - \brief get the cycle number for group5 as soon as a charge-transfer sequence completes - \param[in] none - \param[out] none - \retval group5 cycle number -*/ -uint16_t tsi_group5_cycle_get(void) -{ - return (uint16_t)TSI_G5CYCN; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c deleted file mode 100644 index f4dd5a4ca3..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_usart.c +++ /dev/null @@ -1,1308 +0,0 @@ -/*! - \file gd32f3x0_usart.c - \brief USART driver - - \version 2017-06-06 V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_usart.h" - -/* USART register bit offset */ -#define CTL1_ADDR_OFFSET ((uint32_t)24U) /* bit offset of ADDR in USART_CTL1 */ -#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ -#define CTL2_SCRTNUM_OFFSET ((uint32_t)17U) /* bit offset of SCRTNUM in USART_CTL2 */ -#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ -#define CTL0_DEA_OFFSET ((uint32_t)21U) /* bit offset of DEA in USART_CTL0 */ -#define CTL0_DED_OFFSET ((uint32_t)16U) /* bit offset of DED in USART_CTL0 */ - -/*! - \brief reset USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph){ - case USART0: - /* reset USART0 */ - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - /* reset USART1 */ - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; - switch(usart_periph){ - /* get clock frequency */ - case USART0: - /* get USART0 clock */ - uclk = rcu_clock_freq_get(CK_USART); - break; - case USART1: - /* get USART1 clock */ - uclk = rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ - /* oversampling by 8, configure the value of USART_BAUD */ - udiv = ((2U*uclk)+baudval/2U)/baudval; - intdiv = udiv & 0x0000fff0U; - fradiv = (udiv>>1U) & 0x00000007U; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - }else{ - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; - intdiv = udiv & 0x0000fff0U; - fradiv = udiv & 0x0000000fU; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1) - \param[in] paritycfg: USART parity configure - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5bit - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5bit - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - USART_CTL1(usart_periph) |= stblen; -} - -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - USART_CTL0(usart_periph) &= ~USART_CTL0_TEN; - /* configure transfer mode */ - USART_CTL0(usart_periph) |= txconfig; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - USART_CTL0(usart_periph) &= ~USART_CTL0_REN; - /* configure receiver mode */ - USART_CTL0(usart_periph) |= rxconfig; -} - -/*! - \brief data is transmitted/received with the LSB/MSB first - \param[in] usart_periph: USARTx(x=0,1) - \param[in] msbf: LSB/MSB - only one parameter can be selected which is shown as below: - \arg USART_MSBF_LSB: LSB first - \arg USART_MSBF_MSB: MSB first - \param[out] none - \retval none -*/ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* configure LSB or MSB first */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); - USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); -} - -/*! - \brief USART inverted configure - \param[in] usart_periph: USARTx(x=0,1) - \param[in] invertpara: refer to usart_invert_enum - only one parameter can be selected which is shown as below: - \arg USART_DINV_ENABLE: data bit level inversion - \arg USART_DINV_DISABLE: data bit level not inversion - \arg USART_TXPIN_ENABLE: TX pin level inversion - \arg USART_TXPIN_DISABLE: TX pin level not inversion - \arg USART_RXPIN_ENABLE: RX pin level inversion - \arg USART_RXPIN_DISABLE: RX pin level not inversion - \arg USART_SWAP_ENABLE: swap TX/RX pins - \arg USART_SWAP_DISABLE: not swap TX/RX pins - \param[out] none - \retval none -*/ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* inverted or not the specified signal */ - switch(invertpara){ - case USART_DINV_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_DINV; - break; - case USART_DINV_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); - break; - case USART_TXPIN_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_TINV; - break; - case USART_TXPIN_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); - break; - case USART_RXPIN_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_RINV; - break; - case USART_RXPIN_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); - break; - case USART_SWAP_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_STRP; - break; - case USART_SWAP_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP); - break; - default: - break; - } -} - -/*! - \brief enable the USART overrun function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_overrun_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* enable overrun function */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD); -} - -/*! - \brief disable the USART overrun function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_overrun_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* disable overrun function */ - USART_CTL2(usart_periph) |= USART_CTL2_OVRD; -} - -/*! - \brief configure the USART oversample mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] oversamp: oversample value - only one parameter can be selected which is shown as below: - \arg USART_OVSMOD_8: oversampling by 8 - \arg USART_OVSMOD_16: oversampling by 16 - \param[out] none - \retval none -*/ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear OVSMOD bit */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); - USART_CTL0(usart_periph) |= oversamp; -} - -/*! - \brief configure the sample bit method - \param[in] usart_periph: USARTx(x=0,1) - \param[in] osb: sample bit - only one parameter can be selected which is shown as below: - \arg USART_OSB_1BIT: 1 bit - \arg USART_OSB_3BIT: 3 bits - \param[out] none - \retval none -*/ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); - USART_CTL2(usart_periph) |= osb; -} - -/*! - \brief enable receiver timeout - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_RTEN; -} - -/*! - \brief disable receiver timeout - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN); -} - -/*! - \brief configure receiver timeout threshold - \param[in] usart_periph: USARTx(x=0) - \param[in] rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks - \param[out] none - \retval none -*/ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) -{ - USART_RT(usart_periph) &= ~(USART_RT_RT); - USART_RT(usart_periph) |= rtimeout; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data); -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); -} - -/*! - \brief enable auto baud rate detection - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_autobaud_detection_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_ABDEN; -} - -/*! - \brief disable auto baud rate detection - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_autobaud_detection_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN); -} - -/*! - \brief configure auto baud rate detection mode - \param[in] usart_periph: USARTx(x=0) - \param[in] abdmod: auto baud rate detection mode - only one parameter can be selected which is shown as below: - \arg USART_ABDM_FTOR: falling edge to rising edge measurement - \arg USART_ABDM_FTOF: falling edge to falling edge measurement - \param[out] none - \retval none -*/ -void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod) -{ - /* reset ABDM bits */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM); - USART_CTL1(usart_periph) |= abdmod; -} - -/*! - \brief address of the USART terminal - \param[in] usart_periph: USARTx(x=0,1) - \param[in] addr: 0x00-0xFF, address of USART terminal - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << CTL1_ADDR_OFFSET)); -} - -/*! - \brief configure the address of the USART in wake up by address match mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] addmod: address detection mode - only one parameter can be selected which is shown as below: - \arg USART_ADDM_4BIT: 4 bits - \arg USART_ADDM_FULLBIT: full bits - \param[out] none - \retval none -*/ -void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM); - USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod); -} - -/*! - \brief enable mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_MEN; -} - -/*! - \brief disable mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] wmethod: two methods be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mark - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief configure LIN break frame length - \param[in] usart_periph: USARTx(x=0) - \param[in] lblen: LIN break detection length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits break detection - \arg USART_LBLEN_11B: 11 bits break detection - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen); -} - -/*! - \brief enable half-duplex mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half-duplex mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable USART clock - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_clock_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable USART clock - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_clock_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1) - \param[in] clen: last bit clock pulse - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin - \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset USART_CTL1 CLEN,CPH,CPL bits */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - - USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen); - USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph); - USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl); -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[in] guat: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << GP_GUAT_OFFSET)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief enable early NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) |= USART_RFCS_ELNACK; -} - -/*! - \brief disable early NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK; -} - -/*! - \brief configure smartcard auto-retry number - \param[in] usart_periph: USARTx(x=0) - \param[in] scrtnum: 0x00000000-0x00000007, smartcard auto-retry number - \param[out] none - \retval none -*/ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM); - USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << CTL2_SCRTNUM_OFFSET)); -} - -/*! - \brief configure block length - \param[in] usart_periph: USARTx(x=0) - \param[in] bl: 0x00000000-0x000000FF - \param[out] none - \retval none -*/ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl) -{ - USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << RT_BL_OFFSET)); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode - \param[in] usart_periph: USARTx(x=0) - \param[in] psc: 0x00000000-0x000000FF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0) - \param[in] irlp: IrDA low-power or normal - only one parameter can be selected which is shown as below: - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1) - \param[in] rtsconfig: enable or disable RTS - only one parameter can be selected which is shown as below: - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); - USART_CTL2(usart_periph) |= rtsconfig; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1) - \param[in] ctsconfig: enable or disable CTS - only one parameter can be selected which is shown as below: - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN; - USART_CTL2(usart_periph) |= ctsconfig; -} - -/*! - \brief enable RS485 driver - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_rs485_driver_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_DEM; -} - -/*! - \brief disable RS485 driver - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_rs485_driver_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM); -} - -/*! - \brief configure driver enable assertion time - \param[in] usart_periph: USARTx(x=0,1) - \param[in] deatime: 0x00000000-0x0000001F - \param[out] none - \retval none -*/ -void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA); - USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << CTL0_DEA_OFFSET)); -} - -/*! - \brief configure driver enable de-assertion time - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dedtime: 0x00000000-0x0000001F - \param[out] none - \retval none -*/ -void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_DED); - USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << CTL0_DED_OFFSET)); -} - -/*! - \brief configure driver enable polarity mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dep: DE signal - only one parameter can be selected which is shown as below: - \arg USART_DEP_HIGH: DE signal is active high - \arg USART_DEP_LOW: DE signal is active low - \param[out] none - \retval none -*/ -void usart_depolarity_config(uint32_t usart_periph, uint32_t dep) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset DEP bit */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP); - USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep); -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dmacmd: enable or disable DMA for reception - only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - USART_CTL2(usart_periph) &= ~USART_CTL2_DENR; - /* configure DMA reception */ - USART_CTL2(usart_periph) |= dmacmd; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dmacmd: enable or disable DMA for transmission - only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - USART_CTL2(usart_periph) &= ~USART_CTL2_DENT; - /* configure DMA transmission */ - USART_CTL2(usart_periph) |= dmacmd; -} - -/*! - \brief disable DMA on reception error - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_reception_error_dma_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_DDRE; -} - -/*! - \brief enable DMA on reception error - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_reception_error_dma_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE); -} - -/*! - \brief enable USART to wakeup the mcu from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_wakeup_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UESM; -} - -/*! - \brief disable USART to wakeup the mcu from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_wakeup_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM); -} - -/*! - \brief configure the USART wakeup mode from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[in] wum: wakeup mode - only one parameter can be selected which is shown as below: - \arg USART_WUM_ADDR: WUF active on address match - \arg USART_WUM_STARTB: WUF active on start bit - \arg USART_WUM_RBNE: WUF active on RBNE - \param[out] none - \retval none -*/ -void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset WUM bit */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM); - USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum); -} - -/*! - \brief enable USART command - \param[in] usart_periph: USARTx(x=0,1) - \param[in] cmdtype: command type - only one parameter can be selected which is shown as below: - \arg USART_CMD_ABDCMD: auto baudrate detection command - \arg USART_CMD_SBKCMD: send break command - \arg USART_CMD_MMCMD: mute mode command - \arg USART_CMD_RXFCMD: receive data flush command - \arg USART_CMD_TXFCMD: transmit data flush request - \param[out] none - \retval none -*/ -void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype) -{ - USART_CMD(usart_periph) |= (cmdtype); -} - -/*! - \brief enable receive FIFO - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_receive_fifo_enable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) |= USART_RFCS_RFEN; -} - -/*! - \brief disable receive FIFO - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_receive_fifo_disable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN); -} - -/*! - \brief read receive FIFO counter number - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval receive FIFO counter number -*/ -uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph) -{ - return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U)); -} - -/*! - \brief get flag in STAT/CHC/RFCS register - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: flag type - only one parameter can be selected which is shown as below: - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_IDLE: idle line detected flag - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_TC: transmission completed - \arg USART_FLAG_TBE: transmit data register empty - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_CTS: CTS level - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_ABDE: auto baudrate detection error - \arg USART_FLAG_ABD: auto baudrate detection flag - \arg USART_FLAG_BSY: busy flag - \arg USART_FLAG_AM: address match flag - \arg USART_FLAG_SB: send break flag - \arg USART_FLAG_RWU: receiver wakeup from mute mode. - \arg USART_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_FLAG_TEA: transmit enable acknowledge flag - \arg USART_FLAG_REA: receive enable acknowledge flag - \arg USART_FLAG_EPERR: early parity error flag - \arg USART_FLAG_RFE: receive FIFO empty flag - \arg USART_FLAG_RFF: receive FIFO full flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART status - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: flag type - only one parameter can be selected which is shown as below: - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_NERR: noise detected flag - \arg USART_FLAG_ORERR: overrun error flag - \arg USART_FLAG_IDLE: idle line detected flag - \arg USART_FLAG_TC: transmission complete flag - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_AM: address match flag - \arg USART_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_FLAG_EPERR: early parity error flag - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1) - \param[in] interrupt: interrupt - only one parameter can be selected which is shown as below: - \arg USART_INT_IDLE: idle interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and - overrun error interrupt enable interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_TBE: transmit data register empty interrupt - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_AM: address match interrupt - \arg USART_INT_RT: receiver timeout interrupt - \arg USART_INT_EB: end of block interrupt - \arg USART_INT_LBD: LIN break detection interrupt - \arg USART_INT_ERR: error interrupt enable in multibuffer communication - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_WU: wakeup from deep-sleep mode interrupt - \arg USART_INT_RFF: receive FIFO full interrupt enable - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) -{ - USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1) - \param[in] interrupt: interrupt - only one parameter can be selected which is shown as below: - \arg USART_INT_IDLE: idle interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and - overrun error interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_TBE: transmit data register empty interrupt - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_AM: address match interrupt - \arg USART_INT_RT: receiver timeout interrupt - \arg USART_INT_EB: end of block interrupt - \arg USART_INT_LBD: LIN break detection interrupt - \arg USART_INT_ERR: error interrupt enable in multibuffer communication - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_WU: wakeup from deep-sleep mode interrupt - \arg USART_INT_RFF: receive FIFO full interrupt enable - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) -{ - USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1) - \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_EB: end of block interrupt and interrupt flag - \arg USART_INT_FLAG_RT: receiver timeout interrupt flag - \arg USART_INT_FLAG_AM: address match interrupt flag - \arg USART_INT_FLAG_PERR: parity error interrupt flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt flag - \arg USART_INT_FLAG_TC: transmission complete interrupt flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt flag - \arg USART_INT_FLAG_RBNE_ORERR: overrun error interrupt flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt flag - \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt flag - \arg USART_INT_FLAG_CTS: CTS interrupt flag - \arg USART_INT_FLAG_ERR_NERR: noise error interrupt flag - \arg USART_INT_FLAG_ERR_ORERR: overrun error interrupt flag - \arg USART_INT_FLAG_ERR_FERR: frame error interrupt flag - \arg USART_INT_FLAG_RFFINT: receive FIFO full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if(flagstatus && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART interrupt flag - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: USART interrupt flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_PERR: parity error interrupt flag - \arg USART_INT_FLAG_ERR_FERR: frame error interrupt flag - \arg USART_INT_FLAG_ERR_NERR: noise detected interrupt flag - \arg USART_INT_FLAG_RBNE_ORERR: overrun error interrupt flag - \arg USART_INT_FLAG_ERR_ORERR: overrun error interrupt flag - \arg USART_INT_FLAG_IDLE: idle line detected interrupt flag - \arg USART_INT_FLAG_TC: transmission complete interrupt flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt flag - \arg USART_INT_FLAG_CTS: CTS change interrupt flag - \arg USART_INT_FLAG_RT: receiver timeout interrupt flag - \arg USART_INT_FLAG_EB: end of block interrupt flag - \arg USART_INT_FLAG_AM: address match interrupt flag - \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt flag - \arg USART_INT_FLAG_RFFINT: receive FIFO full interrupt flag - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) -{ - if(USART_INT_FLAG_RFFINT == int_flag){ - USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT); - }else{ - USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(int_flag)); - } -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c deleted file mode 100644 index 10af2b5fb8..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_standard_peripheral/Source/gd32f3x0_wwdgt.c +++ /dev/null @@ -1,142 +0,0 @@ -/*! - \file gd32f3x0_wwdgt.c - \brief WWDGT driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f3x0_wwdgt.h" -#include "gd32f3x0_rcu.h" - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00 - 0x7F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - uint32_t reg = 0x0U; - - reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT); - reg |= (uint32_t)(CTL_CNT(counter_value)); - - WWDGT_CTL = (uint32_t)reg; -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F - \param[in] window: 0x00 - 0x7F - \param[in] prescaler: wwdgt prescaler value - only one parameter can be selected which is shown as below: - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - uint32_t reg_cfg = 0x0U, reg_ctl = 0x0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC)); - reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= (uint32_t)(CFG_WIN(window)); - reg_cfg |= (uint32_t)(prescaler); - reg_ctl |= (uint32_t)(CTL_CNT(counter)); - - WWDGT_CFG = (uint32_t)reg_cfg; - WWDGT_CTL = (uint32_t)reg_ctl; -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if(WWDGT_STAT & WWDGT_STAT_EWIF){ - return SET; - } - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF); -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_core.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_core.h deleted file mode 100644 index a3f6b5a005..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_core.h +++ /dev/null @@ -1,300 +0,0 @@ -/*! - \file usb_core.h - \brief USB core driver header file - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_CORE_H -#define USB_CORE_H - -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - -#define USB_MAX_EP0_SIZE 64U /* endpoint 0 max packet size */ -#define RX_MAX_DATA_LENGTH 512U /* host rx buffer max data length */ -#define HC_MAX_PACKET_COUNT 140U /* host channel max packet count */ - -#define USB_MAX_DEV_EPCOUNT USBFS_MAX_DEV_EPCOUNT -#define USB_MAX_FIFOS (USBFS_MAX_HOST_CHANNELCOUNT * 2U - 1U) - -/* USB core status */ -typedef enum -{ - USB_OK = 0, /* USB core OK status */ - USB_FAIL /* USB core fail status */ -}usb_status_enum; - -/* USB host channel status */ -typedef enum -{ - HC_IDLE = 0, /* USB host channel idle status */ - HC_XF, /* USB host channel transfer status */ - HC_HALTED, /* USB host channel halted status */ - HC_NAK, /* USB host channel nak status */ - HC_NYET, /* USB host channel nyet status */ - HC_STALL, /* USB host channel stall status */ - HC_TRACERR, /* USB host channel tracerr status */ - HC_BBERR, /* USB host channel bberr status */ - HC_DTGERR, /* USB host channel dtgerr status */ -}hc_status_enum; - -/* USB URB(USB request block) state */ -typedef enum -{ - URB_IDLE = 0, /* USB URB idle status */ - URB_DONE, /* USB URB done status */ - URB_NOTREADY, /* USB URB notready status */ - URB_ERROR, /* USB URB error status */ - URB_STALL, /* USB URB stall status */ - URB_PING /* USB URB ping status */ -}urb_state_enum; - -/* USB core configuration */ -typedef struct -{ - uint8_t core_id; /* USB core id */ - uint8_t core_speed; /* USB core speed */ - uint8_t phy_interface; /* USB PHY interface */ - uint8_t host_channel_num; /* USB host channel number */ - uint8_t dev_endp_num; /* USB device endpoint number */ - uint8_t sof_output; /* USB SOF output */ - uint8_t low_power; /* USB low power */ - uint16_t max_packet_size; /* USB max packet size */ - uint16_t max_fifo_size; /* USB fifo size */ -}usb_core_cfgs_struct; - -typedef enum -{ - USBD_OK = 0, /* USB device ok status */ - USBD_BUSY, /* USB device busy status */ - USBD_FAIL, /* USB device fail stauts */ -}usbd_status_enum; - -/* USB control transfer state */ -typedef enum -{ - USB_CTRL_IDLE = 0, /* USB control transfer idle state */ - USB_CTRL_SETUP, /* USB control transfer setup state */ - USB_CTRL_DATA_IN, /* USB control transfer data in state */ - USB_CTRL_DATA_OUT, /* USB control transfer data out state */ - USB_CTRL_STATUS_IN, /* USB control transfer status in state*/ - USB_CTRL_STATUS_OUT, /* USB control transfer status out state */ - USB_CTRL_STALL /* USB control transfer stall state */ -}usbd_control_state_enum; - -/* USB transfer direction */ -typedef enum -{ - USB_RX = 0, /* receive direction type value */ - USB_TX /* transmit direction type value */ -}usb_dir_enum; - -/* USB endpoint in device mode */ -typedef struct -{ - uint8_t endp_type; /* USB endpoint type */ - uint8_t endp_frame; /* USB endpoint frame */ - uint32_t endp_mps; /* USB endpoint max packet size */ - - /* Transaction level variables */ - uint8_t *xfer_buff; /* USB transfer buffer */ - uint32_t xfer_len; /* USB transfer length */ - uint32_t xfer_count; /* USB transfer count */ - - uint32_t dma_addr; /* USBHS can use DMA */ -}usb_ep_struct; - -/* USB device standard request */ -typedef struct -{ - uint8_t bmRequestType; /* USB device request type */ - uint8_t bRequest; /* USB device request */ - uint16_t wValue; /* USB device request value */ - uint16_t wIndex; /* USB device request index */ - uint16_t wLength; /* USB device request length */ -}usb_device_req_struct; - -/* USB core device driver */ -typedef struct -{ - uint8_t config_num; /* USB configuration number */ - __IO uint8_t status; /* USB status */ - uint8_t ctl_status; /* USB control status */ - uint8_t prev_status; /* USB previous status */ - uint8_t connection_status; /* USB connection status */ - uint32_t remote_wakeup; /* USB remote wakeup */ - - /* transfer level variables */ - uint32_t remain_len; /* USB remain length */ - uint32_t sum_len; /* USB sum length */ - uint32_t ctl_len; /* USB control length */ - uint8_t setup_packet[8 * 3]; /* USB setup packet */ - - usb_ep_struct in_ep[USB_MAX_DEV_EPCOUNT]; /* USB IN endpoint */ - usb_ep_struct out_ep[USB_MAX_DEV_EPCOUNT]; /* USB OUT endpoint */ - - uint8_t *dev_desc; /* device descriptor */ - uint8_t *config_desc; /* configuration descriptor */ - uint8_t* *strings; /* configuration strings */ - - /* device class handler */ - uint8_t (*class_init) (void *pudev, uint8_t config_index); /* device class initialize */ - uint8_t (*class_deinit) (void *pudev, uint8_t config_index); /* device class deinitialize */ - uint8_t (*class_req_handler) (void *pudev, usb_device_req_struct *req); /* device request handler */ - uint8_t (*class_data_handler) (void *pudev, usb_dir_enum rx_tx, uint8_t ep_num); /* device data handler */ -}dcd_dev_struct; - -/* USB core host mode channel */ -typedef struct -{ - uint8_t dev_addr; /* device address */ - uint8_t dev_speed; /* device speed */ - uint8_t DPID; /* endpoint transfer data pid */ - uint8_t endp_id; /* endpoint number */ - uint8_t endp_in; /* endpoint in */ - uint8_t endp_type; /* endpoint type */ - uint16_t endp_mps; /* endpoint max pactet size */ - uint16_t info; /* channel information */ - - uint8_t *xfer_buff; /* transfer buffer */ - uint32_t xfer_len; /* transfer length */ - uint32_t xfer_count; /* trasnfer count */ - - uint32_t err_count; /* USB transfer error count */ - - hc_status_enum status; /* channel status */ - urb_state_enum urb_state; /* URB state */ - - uint8_t data_tg_in; /* data in toggle */ - uint8_t data_tg_out; /* data out toggle */ -}usb_hostchannel_struct; - -/* USB core host driver */ -typedef struct -{ - uint8_t rx_buffer[RX_MAX_DATA_LENGTH]; /* rx buffer */ - uint8_t connect_status; /* device connect status */ - usb_hostchannel_struct host_channel[USB_MAX_FIFOS]; /* host channel */ - void (*vbus_drive) (void *pudev, uint8_t state); /* the vbus driver function */ -}hcd_dev_struct; - -#ifdef USE_OTG_MODE - -/* USB core OTG-mode driver */ -typedef struct -{ - uint8_t OTG_State; /* OTG state */ - uint8_t OTG_PrevState; /* OTG previous state */ - uint8_t OTG_Mode; /* OTG mode */ -}otg_dev_struct; - -#endif /* USE_OTG_MODE */ - -/* USB core driver */ -typedef struct -{ - usb_core_cfgs_struct cfg; - -#ifdef USE_DEVICE_MODE - dcd_dev_struct dev; -#endif /* USE_DEVICE_MODE */ - -#ifdef USE_HOST_MODE - hcd_dev_struct host; -#endif /* USE_HOST_MODE */ - -#ifdef USE_OTG_MODE - otg_dev_struct otg; -#endif /* USE_OTG_MODE */ - - void (*udelay) (const uint32_t usec); - void (*mdelay) (const uint32_t msec); -}usb_core_handle_struct; - -/* function declarations */ - -/* global APIs */ -/* initializes the USB controller registers and prepares the core device mode or host mode operation */ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev); -/* initialize core parameters */ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* read a packet from the Rx FIFO associated with the endpoint */ -void* usb_fifo_read (uint8_t *dest, uint16_t len); -/* write a packet into the Tx FIFO associated with the endpoint */ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len); -/* flush a Tx FIFO or all Tx FIFOs */ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num); -/* flush the entire Rx FIFO */ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev); -/* set operation mode (host or device) */ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode); - -/* host APIs */ -#ifdef USE_HOST_MODE - -/* initializes USB core for host mode */ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev); -/* enables the host mode interrupts */ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev); -/* initialize host channel */ -usb_status_enum usb_hostchannel_init (usb_core_handle_struct *pudev, uint8_t hc_num); -/* halt channel */ -usb_status_enum usb_hostchannel_halt (usb_core_handle_struct *pudev, uint8_t hc_num); -/* prepare host channel for transferring packets */ -usb_status_enum usb_hostchannel_startxfer (usb_core_handle_struct *pudev, uint8_t hc_num); -/* reset host port */ -uint32_t usb_port_reset (usb_core_handle_struct *pudev); -/* control the VBUS to power */ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state); -/* stop the USB host and clean up fifos */ -void usb_host_stop (usb_core_handle_struct *pudev); - -#endif /* USE_HOST_MODE */ - -/* device APIs */ -#ifdef USE_DEVICE_MODE - -/* initialize USB core registers for device mode */ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev); -/* configures endpoint 0 to receive SETUP packets */ -void usb_ep0_startout (usb_core_handle_struct *pudev); -/* active remote wakeup signalling */ -void usb_remotewakeup_active (usb_core_handle_struct *pudev); -/* active USB core clock */ -void usb_clock_ungate (usb_core_handle_struct *pudev); -/* stop the device and clean up fifos */ -void usb_device_stop (usb_core_handle_struct *pudev); - -#endif /* USE_DEVICE_MODE */ - -#endif /* USB_CORE_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_defines.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_defines.h deleted file mode 100644 index 19b419bd19..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_defines.h +++ /dev/null @@ -1,124 +0,0 @@ -/*! - \file usb_defines.h - \brief USB core defines - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_DEFINES_H -#define USB_DEFINES_H - -#include "usb_conf.h" - -#ifndef NULL - #define NULL (void *)0 /*!< USB null marco value*/ -#endif /* NULL */ - -#define USB_CORE_SPEED_HIGH 0U /* USB core speed is high-speed */ -#define USB_CORE_SPEED_FULL 1U /* USB core speed is full-speed */ - -#define USBFS_MAX_PACKET_SIZE 64U /* USBFS max packet size */ -#define USBFS_MAX_HOST_CHANNELCOUNT 8U /* USBFS host channel count */ -#define USBFS_MAX_DEV_EPCOUNT 4U /* USBFS device endpoint count */ -#define USBFS_MAX_FIFO_WORDLEN 320U /* USBFS max fifo size in words */ - -#define USBHS_MAX_PACKET_SIZE 512U /* USBHS max packet size */ -#define USBHS_MAX_HOST_CHANNELCOUNT 12U /* USBHS host channel count */ -#define USBHS_MAX_DEV_EPCOUNT 6U /* USBHS device endpoint count */ -#define USBHS_MAX_FIFO_WORDLEN 1280U /* USBHS max fifo size in words */ - -#define USB_CORE_ULPI_PHY 1U /* USB core use external ULPI PHY */ -#define USB_CORE_EMBEDDED_PHY 2U /* USB core use embedded PHY */ - -#define DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0U /* USB enumerate speed use high-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1U /* USB enumerate speed use full-speed PHY clock in 30MHz or 60MHz */ -#define DSTAT_ENUMSPD_LS_PHY_6MHZ 2U /* USB enumerate speed use low-speed PHY clock in 6MHz */ -#define DSTAT_ENUMSPD_FS_PHY_48MHZ 3U /* USB enumerate speed use full-speed PHY clock in 48MHz */ - -#define GRSTATR_RPCKST_IN 2U /* IN data packet received */ -#define GRSTATR_RPCKST_IN_XFER_COMP 3U /* IN transfer completed (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_DATA_TOGGLE_ERR 5U /* data toggle error (generates an interrupt if poped) */ -#define GRSTATR_RPCKST_CH_HALTED 7U /* channel halted (generates an interrupt if poped) */ - -#define DEVICE_MODE 0U /* USB core in device mode */ -#define HOST_MODE 1U /* USB core in host mode */ -#define OTG_MODE 2U /* USB core in OTG mode */ - -#define USB_EPTYPE_CTRL 0U /* USB control endpoint type */ -#define USB_EPTYPE_ISOC 1U /* USB synchronous endpoint type */ -#define USB_EPTYPE_BULK 2U /* USB bulk endpoint type */ -#define USB_EPTYPE_INTR 3U /* USB interrupt endpoint type */ -#define USB_EPTYPE_MASK 3U /* USB endpoint type mask */ - -#define RXSTAT_GOUT_NAK 1U /* global OUT NAK (triggers an interrupt) */ -#define RXSTAT_DATA_UPDT 2U /* OUT data packet received */ -#define RXSTAT_XFER_COMP 3U /* OUT transfer completed (triggers an interrupt) */ -#define RXSTAT_SETUP_COMP 4U /* SETUP transaction completed (triggers an interrupt) */ -#define RXSTAT_SETUP_UPDT 6U /* SETUP data packet received */ - -#define DPID_DATA0 0U /* device endpoint data PID is DATA0 */ -#define DPID_DATA1 2U /* device endpoint data PID is DATA1 */ -#define DPID_DATA2 1U /* device endpoint data PID is DATA2 */ -#define DPID_MDATA 3U /* device endpoint data PID is MDATA */ - -#define HC_PID_DATA0 0U /* host channel data PID is DATA0 */ -#define HC_PID_DATA2 1U /* host channel data PID is DATA2 */ -#define HC_PID_DATA1 2U /* host channel data PID is DATA1 */ -#define HC_PID_SETUP 3U /* host channel data PID is SETUP */ - -#define HPRT_PRTSPD_HIGH_SPEED 0U /* host port speed use high speed */ -#define HPRT_PRTSPD_FULL_SPEED 1U /* host port speed use full speed */ -#define HPRT_PRTSPD_LOW_SPEED 2U /* host port speed use low speed */ - -#define HCTLR_30_60_MHZ 0U /* USB PHY(ULPI) clock is 60MHz */ -#define HCTLR_48_MHZ 1U /* USB PHY(embedded full-speed) clock is 48MHz */ -#define HCTLR_6_MHZ 2U /* USB PHY(embedded low-speed) clock is 6MHz */ - -#define HCCHAR_CTRL 0U /* control channel type */ -#define HCCHAR_ISOC 1U /* synchronous channel type */ -#define HCCHAR_BULK 2U /* bulk channel type */ -#define HCCHAR_INTR 3U /* interrupt channel type */ - -typedef enum -{ - USB_HS_CORE_ID = 0, - USB_FS_CORE_ID = 1 -}usb_core_id_enum; - -typedef enum -{ - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}usb_speed_enum; - -#endif /* USB_DEFINES_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_regs.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_regs.h deleted file mode 100644 index 2d414a58e2..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_regs.h +++ /dev/null @@ -1,589 +0,0 @@ -/*! - \file usb_regs.h - \brief USB FS cell registers definition and handle macros - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_REGS_H -#define USB_REGS_H - -#include "usb_conf.h" - -#define USBFS USBFS_BASE /*!< base address of USBFS registers */ - -/* registers location definitions */ -#define LOCATE_DIEPTFLEN(x) (0x104U + 4U * ((x) - 1U)) /*!< locate device IN endpoint-x (x = 1..3) transfer length registers */ -#define LOCATE_HCHCTL(x) (0x500U + 0x20U * (x)) /*!< locate host channel-x control registers */ -#define LOCATE_HCHINTF(x) (0x508U + 0x20U * (x)) /*!< locate host channel-x interrupt flag registers */ -#define LOCATE_HCHINTEN(x) (0x50CU + 0x20U * (x)) /*!< locate host channel-x interrupt enable registers */ -#define LOCATE_HCHLEN(x) (0x510U + 0x20U * (x)) /*!< locate host channel-x transfer length registers */ -#define LOCATE_DIEPCTL(x) (0x900U + 0x20U * (x)) /*!< locate device IN endpoint-x control registers */ -#define LOCATE_DOEPCTL(x) (0xB00U + 0x20U * (x)) /*!< locate device OUT endpoint-x control registers */ -#define LOCATE_DIEPINTF(x) (0x908U + 0x20U * (x)) /*!< locate device IN endpoint-x interrupt flag registers */ -#define LOCATE_DOEPINTF(x) (0xB08U + 0x20U * (x)) /*!< locate device OUT endpoint-x interrupt flag registers */ -#define LOCATE_DIEPLEN(x) (0x910U + 0x20U * (x)) /*!< locate device IN endpoint-x transfer length registers */ -#define LOCATE_DOEPLEN(x) (0xB10U + 0x20U * (x)) /*!< locate device OUT endpoint-x transfer length registers */ -#define LOCATE_DIEPxTFSTAT(x) (0x918U + 0x20U * (x)) /*!< locate Device IN endpoint-x transmit FIFO status register */ -#define LOCATE_FIFO(x) (((x) + 1U) << 12U) /*!< locate FIFO-x memory */ - -/* registers definitions */ -#define USB_GOTGCS REG32(((USBFS) + 0x00000000U)) /*!< global OTG control and status register */ -#define USB_GOTGINTF REG32(((USBFS) + 0x00000004U)) /*!< global OTG interrupt flag register */ -#define USB_GAHBCS REG32(((USBFS) + 0x00000008U)) /*!< global AHB control and status register */ -#define USB_GUSBCS REG32(((USBFS) + 0x0000000CU)) /*!< global USB control and status register */ -#define USB_GRSTCTL REG32(((USBFS) + 0x00000010U)) /*!< global reset control register */ -#define USB_GINTF REG32(((USBFS) + 0x00000014U)) /*!< global interrupt flag register */ -#define USB_GINTEN REG32(((USBFS) + 0x00000018U)) /*!< global interrupt enable register */ -#define USB_GRSTATR REG32(((USBFS) + 0x0000001CU)) /*!< global receive status read register */ -#define USB_GRSTATP REG32(((USBFS) + 0x00000020U)) /*!< global receive status read and pop register */ -#define USB_GRFLEN REG32(((USBFS) + 0x00000024U)) /*!< global receive FIFO length register */ -#define USB_HNPTFLEN REG32(((USBFS) + 0x00000028U)) /*!< host non-periodic transmit FIFO length register */ -#define USB_DIEP0TFLEN REG32(((USBFS) + 0x00000028U)) /*!< device IN endpoint 0 transmit FIFO length register */ -#define USB_HNPTFQSTAT REG32(((USBFS) + 0x0000002CU)) /*!< host non-periodic transmint FIFO/queue status register */ -#define USB_GCCFG REG32(((USBFS) + 0x00000038U)) /*!< global core configuration register */ -#define USB_CID REG32(((USBFS) + 0x0000003CU)) /*!< core id register */ -#define USB_HPTFLEN REG32(((USBFS) + 0x00000100U)) /*!< host periodic transmit FIFO length register */ -#define USB_DIEPxTFLEN(x) REG32(((USBFS) + LOCATE_DIEPTFLEN(x))) /*!< device IN endpoint transmit FIFO length register */ - -#define USB_HCTL REG32(((USBFS) + 0x00000400U)) /*!< host control register */ -#define USB_HFT REG32(((USBFS) + 0x00000404U)) /*!< host frame interval register */ -#define USB_HFINFR REG32(((USBFS) + 0x00000408U)) /*!< host frame information remaining register */ -#define USB_HPTFQSTAT REG32(((USBFS) + 0x00000410U)) /*!< host periodic transmit FIFO/queue status register */ -#define USB_HACHINT REG32(((USBFS) + 0x00000414U)) /*!< host all channels interrupt register */ -#define USB_HACHINTEN REG32(((USBFS) + 0x00000418U)) /*!< host all channels interrupt enable register */ -#define USB_HPCS REG32(((USBFS) + 0x00000440U)) /*!< host port control and status register */ -#define USB_HCHxCTL(x) REG32(((USBFS) + LOCATE_HCHCTL(x))) /*!< host channel-x control register */ -#define USB_HCHxINTF(x) REG32(((USBFS) + LOCATE_HCHINTF(x))) /*!< host channel-x interrupt flag register */ -#define USB_HCHxINTEN(x) REG32(((USBFS) + LOCATE_HCHINTEN(x))) /*!< host channel-x interrupt enable register */ -#define USB_HCHxLEN(x) REG32(((USBFS) + LOCATE_HCHLEN(x))) /*!< host channel-x tranfer length register */ - -#define USB_DCFG REG32(((USBFS) + 0x00000800U)) /*!< device configuration register */ -#define USB_DCTL REG32(((USBFS) + 0x00000804U)) /*!< device control register */ -#define USB_DSTAT REG32(((USBFS) + 0x00000808U)) /*!< device status register */ -#define USB_DIEPINTEN REG32(((USBFS) + 0x00000810U)) /*!< device IN endpoint common interrupt enable register */ -#define USB_DOEPINTEN REG32(((USBFS) + 0x00000814U)) /*!< device OUT endpoint common interrupt enable register */ -#define USB_DAEPINT REG32(((USBFS) + 0x00000818U)) /*!< device all endpoints interrupt register */ -#define USB_DAEPINTEN REG32(((USBFS) + 0x0000081CU)) /*!< device all endpoints interrupt enable register */ -#define USB_DVBUSDT REG32(((USBFS) + 0x00000828U)) /*!< device vbus discharge time register */ -#define USB_DVBUSPT REG32(((USBFS) + 0x0000082CU)) /*!< device vbus pulsing time register */ -#define USB_DIEPFEINTEN REG32(((USBFS) + 0x00000834U)) /*!< device IN endpoint FIFO empty interrupt enable register */ -#define USB_DEP1INT REG32(((USBFS) + 0x00000838U)) /*!< device endpoint 1 interrupt register */ -#define USB_DEP1INTEN REG32(((USBFS) + 0x0000083CU)) /*!< device endpoint 1 interrupt enable register */ -#define USB_DIEP1INTEN REG32(((USBFS) + 0x00000844U)) /*!< device IN endpoint 1 interrupt enable register */ -#define USB_DOEP1INTEN REG32(((USBFS) + 0x00000884U)) /*!< device OUT endpoint 1 interrupt enable register */ -#define USB_DIEP0CTL REG32(((USBFS) + 0x00000900U)) /*!< device IN endpoint 0 control register */ -#define USB_DIEP0LEN REG32(((USBFS) + 0x00000910U)) /*!< device IN endpoint 0 transfer length register */ -#define USB_DOEP0CTL REG32(((USBFS) + 0x00000B00U)) /*!< device OUT endpoint 0 control register */ -#define USB_DOEP0LEN REG32(((USBFS) + 0x00000B10U)) /*!< device OUT endpoint 0 transfer length register */ -#define USB_DIEPxCTL(x) REG32(((USBFS) + LOCATE_DIEPCTL(x))) /*!< device IN endpoint-x control register */ -#define USB_DOEPxCTL(x) REG32(((USBFS) + LOCATE_DOEPCTL(x))) /*!< device OUT endpoint-x control register */ -#define USB_DIEPxINTF(x) REG32(((USBFS) + LOCATE_DIEPINTF(x))) /*!< device IN endpoint-x interrupt flag register */ -#define USB_DOEPxINTF(x) REG32(((USBFS) + LOCATE_DOEPINTF(x))) /*!< device OUT endpoint-x interrupt flag register */ -#define USB_DIEPxLEN(x) REG32(((USBFS) + LOCATE_DIEPLEN(x))) /*!< device IN endpoint-x transfer length register */ -#define USB_DOEPxLEN(x) REG32(((USBFS) + LOCATE_DOEPLEN(x))) /*!< device OUT endpoint-x transfer length register */ -#define USB_DIEPxTFSTAT(x) REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x)))/*!< device IN endpoint-x transmit FIFO status register */ - -#define USB_PWRCLKCTL REG32(((USBFS) + 0x0E00U)) /*!< power and clock register */ - -#define USB_FIFO(x) (®32(((USBFS) + LOCATE_FIFO(x)))) /*!< FIFO memory */ - -/* global OTG control and status register bits definitions */ -#define GOTGCS_BSV BIT(19) /*!< B-Session Valid */ -#define GOTGCS_ASV BIT(18) /*!< A-session valid */ -#define GOTGCS_DI BIT(17) /*!< debounce interval */ -#define GOTGCS_IDPS BIT(16) /*!< id pin status */ -#define GOTGCS_DHNPEN BIT(11) /*!< device HNP enable */ -#define GOTGCS_HHNPEN BIT(10) /*!< host HNP enable */ -#define GOTGCS_HNPREQ BIT(9) /*!< HNP request */ -#define GOTGCS_HNPS BIT(8) /*!< HNP successes */ -#define GOTGCS_SRPREQ BIT(1) /*!< SRP request */ -#define GOTGCS_SRPS BIT(0) /*!< SRP successes */ - -/* global OTG interrupt flag register bits definitions */ -#define GOTGINTF_DF BIT(19) /*!< debounce finish */ -#define GOTGINTF_ADTO BIT(18) /*!< A-device timeout */ -#define GOTGINTF_HNPDET BIT(17) /*!< host negotiation request detected */ -#define GOTGINTF_HNPEND BIT(9) /*!< HNP end */ -#define GOTGINTF_SRPEND BIT(8) /*!< SRP end */ -#define GOTGINTF_SESEND BIT(2) /*!< session end */ - -/* global AHB control and status register bits definitions */ -#define GAHBCS_PTXFTH BIT(8) /*!< periodic Tx FIFO threshold */ -#define GAHBCS_TXFTH BIT(7) /*!< tx FIFO threshold */ -#define GAHBCS_GINTEN BIT(0) /*!< global interrupt enable */ - -/* global USB control and status register bits definitions */ -#define GUSBCS_FDM BIT(30) /*!< force device mode */ -#define GUSBCS_FHM BIT(29) /*!< force host mode */ -#define GUSBCS_UTT BITS(10, 13) /*!< USB turnaround time */ -#define GUSBCS_HNPCEN BIT(9) /*!< HNP capability enable */ -#define GUSBCS_SRPCEN BIT(8) /*!< SRP capability enable */ -#define GUSBCS_TOC BITS(0, 2) /*!< timeout calibration */ - -/* global reset control register bits definitions */ -#define GRSTCTL_TXFNUM BITS(6, 10) /*!< tx FIFO number */ -#define GRSTCTL_TXFF BIT(5) /*!< tx FIFO flush */ -#define GRSTCTL_RXFF BIT(4) /*!< rx FIFO flush */ -#define GRSTCTL_HFCRST BIT(2) /*!< host frame counter reset */ -#define GRSTCTL_HCSRST BIT(1) /*!< HCLK soft reset */ -#define GRSTCTL_CSRST BIT(0) /*!< core soft reset */ - -/* global interrupt flag register bits definitions */ -#define GINTF_WKUPIF BIT(31) /*!< wakeup interrupt flag */ -#define GINTF_SESIF BIT(30) /*!< session interrupt flag */ -#define GINTF_DISCIF BIT(29) /*!< disconnect interrupt flag */ -#define GINTF_IDPSC BIT(28) /*!< id pin status change */ -#define GINTF_PTXFEIF BIT(26) /*!< periodic tx FIFO empty interrupt flag */ -#define GINTF_HCIF BIT(25) /*!< host channels interrupt flag */ -#define GINTF_HPIF BIT(24) /*!< host port interrupt flag */ -#define GINTF_PXNCIF BIT(21) /*!< periodic transfer not complete interrupt flag */ -#define GINTF_ISOONCIF BIT(21) /*!< isochronous OUT transfer not complete interrupt flag */ -#define GINTF_ISOINCIF BIT(20) /*!< isochronous IN transfer not complete interrupt flag */ -#define GINTF_OEPIF BIT(19) /*!< OUT endpoint interrupt flag */ -#define GINTF_IEPIF BIT(18) /*!< IN endpoint interrupt flag */ -#define GINTF_EOPFIF BIT(15) /*!< end of periodic frame interrupt flag */ -#define GINTF_ISOOPDIF BIT(14) /*!< isochronous OUT packet dropped interrupt flag */ -#define GINTF_ENUMF BIT(13) /*!< enumeration finished */ -#define GINTF_RST BIT(12) /*!< USB reset */ -#define GINTF_SP BIT(11) /*!< USB suspend */ -#define GINTF_ESP BIT(10) /*!< early suspend */ -#define GINTF_GONAK BIT(7) /*!< global OUT NAK effective */ -#define GINTF_GNPINAK BIT(6) /*!< global IN non-periodic NAK effective */ -#define GINTF_NPTXFEIF BIT(5) /*!< non-periodic tx FIFO empty interrupt flag */ -#define GINTF_RXFNEIF BIT(4) /*!< rx FIFO non-empty interrupt flag */ -#define GINTF_SOF BIT(3) /*!< start of frame */ -#define GINTF_OTGIF BIT(2) /*!< OTG interrupt flag */ -#define GINTF_MFIF BIT(1) /*!< mode fault interrupt flag */ -#define GINTF_COPM BIT(0) /*!< current operation mode */ - -/* global interrupt enable register bits definitions */ -#define GINTEN_WKUPIE BIT(31) /*!< wakeup interrupt enable */ -#define GINTEN_SESIE BIT(30) /*!< session interrupt enable */ -#define GINTEN_DISCIE BIT(29) /*!< disconnect interrupt enable */ -#define GINTEN_IDPSCIE BIT(28) /*!< id pin status change interrupt enable */ -#define GINTEN_PTXFEIE BIT(26) /*!< periodic tx FIFO empty interrupt enable */ -#define GINTEN_HCIE BIT(25) /*!< host channels interrupt enable */ -#define GINTEN_HPIE BIT(24) /*!< host port interrupt enable */ -#define GINTEN_PXNCIE BIT(21) /*!< periodic transfer not complete interrupt enable */ -#define GINTEN_ISOONCIE BIT(21) /*!< isochronous OUT transfer not complete interrupt enable */ -#define GINTEN_ISOINCIE BIT(20) /*!< isochronous IN transfer not complete interrupt enable */ -#define GINTEN_OEPIE BIT(19) /*!< OUT endpoints interrupt enable */ -#define GINTEN_IEPIE BIT(18) /*!< IN endpoints interrupt enable */ -#define GINTEN_EOPFIE BIT(15) /*!< end of periodic frame interrupt enable */ -#define GINTEN_ISOOPDIE BIT(14) /*!< isochronous OUT packet dropped interrupt enable */ -#define GINTEN_ENUMFIE BIT(13) /*!< enumeration finish enable */ -#define GINTEN_RSTIE BIT(12) /*!< USB reset interrupt enable */ -#define GINTEN_SPIE BIT(11) /*!< USB suspend interrupt enable */ -#define GINTEN_ESPIE BIT(10) /*!< early suspend interrupt enable */ -#define GINTEN_GONAKIE BIT(7) /*!< global OUT NAK effective interrupt enable */ -#define GINTEN_GNPINAKIE BIT(6) /*!< global non-periodic IN NAK effective interrupt enable */ -#define GINTEN_NPTXFEIE BIT(5) /*!< non-periodic Tx FIFO empty interrupt enable */ -#define GINTEN_RXFNEIE BIT(4) /*!< receive FIFO non-empty interrupt enable */ -#define GINTEN_SOFIE BIT(3) /*!< start of frame interrupt enable */ -#define GINTEN_OTGIE BIT(2) /*!< OTG interrupt enable */ -#define GINTEN_MFIE BIT(1) /*!< mode fault interrupt enable */ - -/* global receive status read and pop register bits definitions */ -#define GRSTATRP_RPCKST BITS(17, 20) /*!< received packet status */ -#define GRSTATRP_DPID BITS(15, 16) /*!< data PID */ -#define GRSTATRP_BCOUNT BITS(4, 14) /*!< byte count */ -#define GRSTATRP_CNUM BITS(0, 3) /*!< channel number */ -#define GRSTATRP_EPNUM BITS(0, 3) /*!< endpoint number */ - -/* global receive FIFO length register bits definitions */ -#define GRFLEN_RXFD BITS(0, 15) /*!< rx FIFO depth */ - -/* host non-periodic transmit FIFO length register bits definitions */ -#define HNPTFLEN_HNPTXFD BITS(16, 31) /*!< non-periodic Tx FIFO depth */ -#define HNPTFLEN_HNPTXRSAR BITS(0, 15) /*!< non-periodic Tx RAM start address */ - -/* IN endpoint 0 transmit FIFO length register bits definitions */ -#define DIEP0TFLEN_IEP0TXFD BITS(16, 31) /*!< IN Endpoint 0 Tx FIFO depth */ -#define DIEP0TFLEN_IEP0TXRSAR BITS(0, 15) /*!< IN Endpoint 0 TX RAM start address */ - -/* host non-periodic transmit FIFO/queue status register bits definitions */ -#define HNPTFQSTAT_NPTXRQTOP BITS(24, 30) /*!< top entry of the non-periodic Tx request queue */ -#define HNPTFQSTAT_NPTXRQS BITS(16, 23) /*!< non-periodic Tx request queue space */ -#define HNPTFQSTAT_NPTXFS BITS(0, 15) /*!< non-periodic Tx FIFO space */ -#define HNPTFQSTAT_CNUM BITS(27, 30) /*!< channel number*/ -#define HNPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HNPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HNPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* global core configuration register bits definitions */ -#define GCCFG_VBUSIG BIT(21) /*!< vbus ignored */ -#define GCCFG_SOFOEN BIT(20) /*!< SOF output enable */ -#define GCCFG_VBUSBCEN BIT(19) /*!< the VBUS B-device comparer enable */ -#define GCCFG_VBUSACEN BIT(18) /*!< the VBUS A-device comparer enable */ -#define GCCFG_PWRON BIT(16) /*!< power on */ - -/* core ID register bits definitions */ -#define CID_CID BITS(0, 31) /*!< core ID */ - -/* host periodic transmit FIFO length register bits definitions */ -#define HPTFLEN_HPTXFD BITS(16, 31) /*!< host periodic Tx FIFO depth */ -#define HPTFLEN_HPTXFSAR BITS(0, 15) /*!< host periodic Tx RAM start address */ - -/* device IN endpoint transmit FIFO length register bits definitions */ -#define DIEPTFLEN_IEPTXFD BITS(16, 31) /*!< IN endpoint Tx FIFO x depth */ -#define DIEPTFLEN_IEPTXRSAR BITS(0, 15) /*!< IN endpoint FIFOx Tx x RAM start address */ - -/* host control register bits definitions */ -#define HCTL_CLKSEL BITS(0, 1) /*!< clock select for USB clock */ - -/* host frame interval register bits definitions */ -#define HFT_FRI BITS(0, 15) /*!< frame interval */ - -/* host frame information remaining register bits definitions */ -#define HFINFR_FRT BITS(16, 31) /*!< frame remaining time */ -#define HFINFR_FRNUM BITS(0, 15) /*!< frame number */ - -/* host periodic transmit FIFO/queue status register bits definitions */ -#define HPTFQSTAT_PTXREQT BITS(24, 31) /*!< top entry of the periodic Tx request queue */ -#define HPTFQSTAT_PTXREQS BITS(16, 23) /*!< periodic Tx request queue space */ -#define HPTFQSTAT_PTXFS BITS(0, 15) /*!< periodic Tx FIFO space */ -#define HPTFQSTAT_OEFRM BIT(31) /*!< odd/eveb frame */ -#define HPTFQSTAT_CNUM BITS(27, 30) /*!< channel number */ -#define HPTFQSTAT_EPNUM BITS(27, 30) /*!< endpoint number */ -#define HPTFQSTAT_TYPE BITS(25, 26) /*!< token type */ -#define HPTFQSTAT_TMF BIT(24) /*!< terminate flag */ - -/* host all channels interrupt register bits definitions */ -#define HACHINT_HACHINT BITS(0, 7) /*!< host all channel interrupts */ - -/* host all channels interrupt enable register bits definitions */ -#define HACHINTEN_CINTEN BITS(0, 7) /*!< channel interrupt enable */ - -/* host port control and status register bits definitions */ -#define HPCS_PS BITS(17, 18) /*!< port speed */ -#define HPCS_PP BIT(12) /*!< port power */ -#define HPCS_PLST BITS(10, 11) /*!< port line status */ -#define HPCS_PRST BIT(8) /*!< port reset */ -#define HPCS_PSP BIT(7) /*!< port suspend */ -#define HPCS_PREM BIT(6) /*!< port resume */ -#define HPCS_PEDC BIT(3) /*!< port enable/disable change */ -#define HPCS_PE BIT(2) /*!< port enable */ -#define HPCS_PCD BIT(1) /*!< port connect detected */ -#define HPCS_PCST BIT(0) /*!< port connect status */ - -/* host channel-x control register bits definitions */ -#define HCHCTL_CEN BIT(31) /*!< channel enable */ -#define HCHCTL_CDIS BIT(30) /*!< channel disable */ -#define HCHCTL_ODDFRM BIT(29) /*!< odd frame */ -#define HCHCTL_DAR BITS(22, 28) /*!< device address */ -#define HCHCTL_MPC BITS(20, 21) /*!< multiple packet count */ -#define HCHCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define HCHCTL_LSD BIT(17) /*!< low-speed device */ -#define HCHCTL_EPDIR BIT(15) /*!< endpoint direction */ -#define HCHCTL_EPNUM BITS(11, 14) /*!< endpoint number */ -#define HCHCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* host channel-x interrupt flag register bits definitions */ -#define HCHINTF_DTER BIT(10) /*!< data toggle error */ -#define HCHINTF_REQOVR BIT(9) /*!< request queue overrun */ -#define HCHINTF_BBER BIT(8) /*!< babble error */ -#define HCHINTF_USBER BIT(7) /*!< USB bus Error */ -#define HCHINTF_NYET BIT(6) /*!< NYET */ -#define HCHINTF_ACK BIT(5) /*!< ACK */ -#define HCHINTF_NAK BIT(4) /*!< NAK */ -#define HCHINTF_STALL BIT(3) /*!< STALL */ -#define HCHINTF_CH BIT(1) /*!< channel halted */ -#define HCHINTF_TF BIT(0) /*!< transfer finished */ - -/* host channel-x interrupt enable register bits definitions */ -#define HCHINTEN_DTERIE BIT(10) /*!< data toggle error interrupt enable */ -#define HCHINTEN_REQOVRIE BIT(9) /*!< request queue overrun interrupt enable */ -#define HCHINTEN_BBERIE BIT(8) /*!< babble error interrupt enable */ -#define HCHINTEN_USBERIE BIT(7) /*!< USB bus error interrupt enable */ -#define HCHINTEN_NYETIE BIT(6) /*!< NYET interrupt enable */ -#define HCHINTEN_ACKIE BIT(5) /*!< ACK interrupt enable */ -#define HCHINTEN_NAKIE BIT(4) /*!< NAK interrupt enable */ -#define HCHINTEN_STALLIE BIT(3) /*!< STALL interrupt enable */ -#define HCHINTEN_CHIE BIT(1) /*!< channel halted interrupt enable */ -#define HCHINTEN_TFIE BIT(0) /*!< transfer finished interrupt enable */ - -/* host channel-x transfer length register bits definitions */ -#define HCHLEN_DPID BITS(29, 30) /*!< data PID */ -#define HCHLEN_PCNT BITS(19, 28) /*!< packet count */ -#define HCHLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device control and status registers */ -/* device configuration registers bits definitions */ -#define DCFG_EOPFT BITS(11, 12) /*!< end of periodic frame time */ -#define DCFG_DAR BITS(4, 10) /*!< device address */ -#define DCFG_NZLSOH BIT(2) /*!< non-zero-length status OUT handshake */ -#define DCFG_DS BITS(0, 1) /*!< device speed */ - -/* device control registers bits definitions */ -#define DCTL_POIF BIT(11) /*!< power-on initialization finished */ -#define DCTL_CGONAK BIT(10) /*!< clear global OUT NAK */ -#define DCTL_SGONAK BIT(9) /*!< set global OUT NAK */ -#define DCTL_CGINAK BIT(8) /*!< clear global IN NAK */ -#define DCTL_SGINAK BIT(7) /*!< set global IN NAK */ -#define DCTL_GONS BIT(3) /*!< global OUT NAK status */ -#define DCTL_GINS BIT(2) /*!< global IN NAK status */ -#define DCTL_SD BIT(1) /*!< soft disconnect */ -#define DCTL_RWKUP BIT(0) /*!< remote wakeup */ - -/* device status registers bits definitions */ -#define DSTAT_FNRSOF BITS(8, 21) /*!< the frame number of the received SOF. */ -#define DSTAT_ES BITS(1, 2) /*!< enumerated speed */ -#define DSTAT_SPST BIT(0) /*!< suspend status */ - -/* device IN endpoint common interrupt enable registers bits definitions */ -#define DIEPINTEN_TXFEEN BIT(7) /*!< transmit FIFO empty interrupt enable bit */ -#define DIEPINTEN_IEPNEEN BIT(6) /*!< IN endpoint NAK effective interrupt enable bit */ -#define DIEPINTEN_EPTXFUDEN BIT(4) /*!< endpoint Tx FIFO underrun interrupt enable bit */ -#define DIEPINTEN_CITOEN BIT(3) /*!< control In Timeout interrupt enable bit */ -#define DIEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DIEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device OUT endpoint common interrupt enable registers bits definitions */ -#define DOEPINTEN_BTBSTPEN BIT(6) /*!< back-to-back SETUP packets interrupt enable bit */ -#define DOEPINTEN_EPRXFOVREN BIT(4) /*!< endpoint Rx FIFO overrun interrupt enable bit */ -#define DOEPINTEN_STPFEN BIT(3) /*!< SETUP phase finished interrupt enable bit */ -#define DOEPINTEN_EPDISEN BIT(1) /*!< endpoint disabled interrupt enable bit */ -#define DOEPINTEN_TFEN BIT(0) /*!< transfer finished interrupt enable bit */ - -/* device all endpoints interrupt registers bits definitions */ -#define DAEPINT_OEPITB BITS(16, 21) /*!< device all OUT endpoint interrupt bits */ -#define DAEPINT_IEPITB BITS(0, 5) /*!< device all IN endpoint interrupt bits */ - -/* device all endpoints interrupt enable registers bits definitions */ -#define DAEPINTEN_OEPIE BITS(16, 21) /*!< OUT endpoint interrupt enable */ -#define DAEPINTEN_IEPIE BITS(0, 3) /*!< IN endpoint interrupt enable */ - -/* device Vbus discharge time registers bits definitions */ -#define DVBUSDT_DVBUSDT BITS(0, 15) /*!< device VBUS discharge time */ - -/* device Vbus pulsing time registers bits definitions */ -#define DVBUSPT_DVBUSPT BITS(0, 11) /*!< device VBUS pulsing time */ - -/* device IN endpoint FIFO empty interrupt enable register bits definitions */ -#define DIEPFEINTEN_IEPTXFEIE BITS(0, 3) /*!< IN endpoint Tx FIFO empty interrupt enable bits */ - -/* device endpoint 0 control register bits definitions */ -#define DEP0CTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEP0CTL_EPD BIT(30) /*!< endpoint disable */ -#define DEP0CTL_SNAK BIT(27) /*!< set NAK */ -#define DEP0CTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEP0CTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEP0CTL_STALL BIT(21) /*!< STALL handshake */ -#define DEP0CTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEP0CTL_NAKS BIT(17) /*!< NAK status */ -#define DEP0CTL_EPACT BIT(15) /*!< endpoint active */ -#define DEP0CTL_MPL BITS(0, 1) /*!< maximum packet length */ - -/* device endpoint x control register bits definitions */ -#define DEPCTL_EPEN BIT(31) /*!< endpoint enable */ -#define DEPCTL_EPD BIT(30) /*!< endpoint disable */ -#define DEPCTL_SODDFRM BIT(29) /*!< set odd frame */ -#define DEPCTL_SD1PID BIT(29) /*!< set DATA1 PID */ -#define DEPCTL_SEVNFRM BIT(28) /*!< set even frame */ -#define DEPCTL_SD0PID BIT(28) /*!< set DATA0 PID */ -#define DEPCTL_SNAK BIT(27) /*!< set NAK */ -#define DEPCTL_CNAK BIT(26) /*!< clear NAK */ -#define DIEPCTL_TXFNUM BITS(22, 25) /*!< tx FIFO number */ -#define DEPCTL_STALL BIT(21) /*!< STALL handshake */ -#define DEPCTL_EPTYPE BITS(18, 19) /*!< endpoint type */ -#define DEPCTL_NAKS BIT(17) /*!< NAK status */ -#define DEPCTL_EOFRM BIT(16) /*!< even/odd frame */ -#define DEPCTL_DPID BIT(16) /*!< endpoint data PID */ -#define DEPCTL_EPACT BIT(15) /*!< endpoint active */ -#define DEPCTL_MPL BITS(0, 10) /*!< maximum packet length */ - -/* device IN endpoint-x interrupt flag register bits definitions */ -#define DIEPINTF_TXFE BIT(7) /*!< transmit FIFO empty */ -#define DIEPINTF_IEPNE BIT(6) /*!< IN endpoint NAK effective */ -#define DIEPINTF_EPTXFUD BIT(4) /*!< endpoint Tx FIFO underrun */ -#define DIEPINTF_CITO BIT(3) /*!< control In Timeout interrupt */ -#define DIEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DIEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device OUT endpoint-x interrupt flag register bits definitions */ -#define DOEPINTF_BTBSTP BIT(6) /*!< back-to-back SETUP packets */ -#define DOEPINTF_EPRXFOVR BIT(4) /*!< endpoint Rx FIFO overrun */ -#define DOEPINTF_STPF BIT(3) /*!< SETUP phase finished */ -#define DOEPINTF_EPDIS BIT(1) /*!< endpoint disabled */ -#define DOEPINTF_TF BIT(0) /*!< transfer finished */ - -/* device IN endpoint 0 transfer length register bits definitions */ -#define DIEP0LEN_PCNT BITS(19, 20) /*!< packet count */ -#define DIEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device OUT endpoint 0 transfer length register bits definitions */ -#define DOEP0LEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -#define DOEP0LEN_PCNT BIT(19) /*!< packet count */ -#define DOEP0LEN_TLEN BITS(0, 6) /*!< transfer length */ - -/* device OUT endpoint-x transfer length register bits definitions */ -#define DOEPLEN_RXDPID BITS(29, 30) /*!< received data PID */ -#define DOEPLEN_STPCNT BITS(29, 30) /*!< SETUP packet count */ -#define DIEPLEN_MCNT BITS(29, 30) /*!< multi count */ -#define DEPLEN_PCNT BITS(19, 28) /*!< packet count */ -#define DEPLEN_TLEN BITS(0, 18) /*!< transfer length */ - -/* device IN endpoint-x transmit FIFO status register bits definitions */ -#define DIEPTFSTAT_IEPTFS BITS(0, 15) /*!< IN endpoint¡¯s Tx FIFO space remaining */ - -/* USB power and clock registers bits definition */ -#define PWRCLKCTL_SHCLK BIT(1) /*!< stop HCLK */ -#define PWRCLKCTL_SUCLK BIT(0) /*!< stop the USB clock */ - -/* register options defines */ -#define DCFG_DEVSPEED(regval) (DCFG_DS & ((regval) << 0U)) /*!< device speed configuration */ - -#define USB_SPEED_EXP_HIGH DCFG_DEVSPEED(0U) /*!< device external PHY high speed */ -#define USB_SPEED_EXP_FULL DCFG_DEVSPEED(1U) /*!< device external PHY full speed */ -#define USB_SPEED_INP_FULL DCFG_DEVSPEED(3U) /*!< device internal PHY full speed */ - -#define GAHBCS_TFEL(regval) (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */ - -#define TXFIFO_EMPTY_HALF GAHBCS_TFEL(0U) /*!< Tx FIFO half empty */ -#define TXFIFO_EMPTY GAHBCS_TFEL(1U) /*!< Tx FIFO completely empty */ - -#define GAHBCS_DMAINCR(regval) (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/ - -#define DMA_INCR0 GAHBCS_DMAINCR(0U) /*!< single burst type used by DMA*/ -#define DMA_INCR1 GAHBCS_DMAINCR(1U) /*!< 4-beat incrementing burst type used by DMA*/ -#define DMA_INCR4 GAHBCS_DMAINCR(3U) /*!< 8-beat incrementing burst type used by DMA*/ -#define DMA_INCR8 GAHBCS_DMAINCR(5U) /*!< 16-beat incrementing burst type used by DMA*/ -#define DMA_INCR16 GAHBCS_DMAINCR(7U) /*!< 32-beat incrementing burst type used by DMA*/ - -#define DCFG_PFRI(regval) (DCFG_EOPFT & ((regval) << 11U)) /*!< end of periodic frame time configuration */ - -#define FRAME_INTERVAL_80 DCFG_PFRI(0U) /*!< 80% of the frame time */ -#define FRAME_INTERVAL_85 DCFG_PFRI(1U) /*!< 85% of the frame time */ -#define FRAME_INTERVAL_90 DCFG_PFRI(2U) /*!< 90% of the frame time */ -#define FRAME_INTERVAL_95 DCFG_PFRI(3U) /*!< 95% of the frame time */ - -#define DEP0_MPL(regval) (DEP0CTL_MPL & ((regval) << 0U)) /*!< maximum packet length configuration */ - -#define EP0MPL_64 DEP0_MPL(0U) /*!< maximum packet length 64 bytes */ -#define EP0MPL_32 DEP0_MPL(1U) /*!< maximum packet length 32 bytes */ -#define EP0MPL_16 DEP0_MPL(2U) /*!< maximum packet length 16 bytes */ -#define EP0MPL_8 DEP0_MPL(3U) /*!< maximum packet length 8 bytes */ - -/* endpoints address */ - -/* first bit is direction(0 for Rx and 1 for Tx) */ -#define EP0_OUT ((uint8_t)0x00U) /*!< endpoint out 0 */ -#define EP0_IN ((uint8_t)0x80U) /*!< endpoint in 0 */ -#define EP1_OUT ((uint8_t)0x01U) /*!< endpoint out 1 */ -#define EP1_IN ((uint8_t)0x81U) /*!< endpoint in 1 */ -#define EP2_OUT ((uint8_t)0x02U) /*!< endpoint out 2 */ -#define EP2_IN ((uint8_t)0x82U) /*!< endpoint in 2 */ -#define EP3_OUT ((uint8_t)0x03U) /*!< endpoint out 3 */ -#define EP3_IN ((uint8_t)0x83U) /*!< endpoint in 3 */ - -/* enable global interrupt */ -#define USB_GLOBAL_INT_ENABLE() (USB_GAHBCS |= GAHBCS_GINTEN) - -/* disable global interrupt */ -#define USB_GLOBAL_INT_DISABLE() (USB_GAHBCS &= ~GAHBCS_GINTEN) - -/* get current operation mode */ -#define USB_CURRENT_MODE_GET() (USB_GINTF & GINTF_COPM) - -/* read global interrupt flag */ -#define USB_CORE_INTR_READ(x) \ -do { \ - uint32_t global_intf = USB_GINTF; \ - (x) = global_intf & USB_GINTEN; \ -} while(0) - -/* read global interrupt flag */ -#define USB_DAOEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t out_ep_intb = DAEPINT_OEPITB; \ - (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \ -} while(0) - -/* read out endpoint-x interrupt flag */ -#define USB_DOEP_INTR_READ(x, EpID) \ -do { \ - uint32_t out_epintf = USB_DOEPxINTF(EpID); \ - (x) = out_epintf & USB_DOEPINTEN; \ -} while(0) - -/* read all in endpoint interrupt flag */ -#define USB_DAIEP_INTR_READ(x) \ -do { \ - uint32_t dev_all_ep_inten = USB_DAEPINTEN; \ - uint32_t dev_all_ep_int = USB_DAEPINT; \ - uint32_t in_ep_intb = DAEPINT_IEPITB; \ - (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \ -} while(0) - - -/* read in endpoint-x interrupt flag */ -#define USB_DIEP_INTR_READ(x, EpID) \ -do { \ - uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \ - uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \ - uint32_t dev_inep_inten = USB_DIEPINTEN; \ - (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \ -} while(0) - -/* generate remote wakup signal */ -#define USB_REMOTE_WAKEUP_SET() (USB_DCTL |= DCTL_RWKUP) - -/* no remote wakup signal generate */ -#define USB_REMOTE_WAKEUP_RESET() (USB_DCTL &= ~DCTL_RWKUP) - -/* generate soft disconnect */ -#define USB_SOFT_DISCONNECT_ENABLE() (USB_DCTL |= DCTL_SD) - -/* no soft disconnect generate */ -#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD) - -/* set device address */ -#define USB_SET_DEVADDR(DevAddr) (USB_DCFG |= (DevAddr) << 4U) - -/* check whether frame is even */ -#define USB_EVEN_FRAME() (!(USB_HFINFR & 0x01U)) - -/* read port status */ -#define USB_PORT_READ() (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC)) - -/* usb clock initialize */ -#define USB_FSLSCLOCK_INIT(ClockFreq) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq)) - -/* get usb current speed */ -#define USB_CURRENT_SPEED_GET() ((USB_HPCS & HPCS_PS) >> 17) - -/* get usb current frame */ -#define USB_CURRENT_FRAME_GET() (USB_HFINFR & 0xFFFFU) - -#endif /* USB_REGS_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_std.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_std.h deleted file mode 100644 index 5871882ed3..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usb_std.h +++ /dev/null @@ -1,212 +0,0 @@ -/*! - \file usb_std.h - \brief USB 2.0 standard defines - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USB_STD_H -#define USB_STD_H - -#include "usb_conf.h" - -#define USB_DEV_QUALIFIER_DESC_LEN 0x0AU /*!< USB device qualifier descriptor length */ -#define USB_DEV_DESC_LEN 0x12U /*!< USB device descriptor length */ -#define USB_CFG_DESC_LEN 0x09U /*!< USB device configuration descriptor length */ -#define USB_IF_DESC_LEN 0x09U /*!< USB device interface descriptor length */ -#define USB_EP_DESC_LEN 0x07U /*!< USB device endpoint descriptor length */ -#define USB_OTG_DESC_LEN 0x03U /*!< USB device OTG descriptor length */ - -/* bit 7 of bmRequestType: data phase transfer direction */ -#define USB_DIR_MASK 0x80U /*!< USB transfer direction mask */ -#define USB_DIR_OUT 0x00U /*!< USB transfer OUT direction */ -#define USB_DIR_IN 0x80U /*!< USB transfer IN direction */ - -/* bit 6..5 of bmRequestType: request type */ -#define USB_STANDARD_REQ 0x00U /*!< USB standard request */ -#define USB_CLASS_REQ 0x20U /*!< USB class request */ -#define USB_VENDOR_REQ 0x40U /*!< USB vebdor request */ -#define USB_REQ_MASK 0x60U /*!< USB request mask */ - -/* bit 4..0 of bmRequestType: recipient type */ -#define USB_REQTYPE_DEVICE 0x00U /*!< USB device request type */ -#define USB_REQTYPE_INTERFACE 0x01U /*!< USB interface request type*/ -#define USB_REQTYPE_ENDPOINT 0x02U /*!< USB endpoint request type*/ -#define USB_REQTYPE_MASK 0x03U /*!< USB request type mask*/ - -/* bRequest value */ -#define USBREQ_GET_STATUS 0x00U /*!< USB get status request*/ -#define USBREQ_CLEAR_FEATURE 0x01U /*!< USB clear feature request*/ -#define USBREQ_SET_FEATURE 0x03U /*!< USB set feature request*/ -#define USBREQ_SET_ADDRESS 0x05U /*!< USB set address request*/ -#define USBREQ_GET_DESCRIPTOR 0x06U /*!< USB get descriptor request*/ -#define USBREQ_SET_DESCRIPTOR 0x07U /*!< USB set descriptor request*/ -#define USBREQ_GET_CONFIGURATION 0x08U /*!< USB get configuration request*/ -#define USBREQ_SET_CONFIGURATION 0x09U /*!< USB set configuration request*/ -#define USBREQ_GET_INTERFACE 0x0AU /*!< USB get interface request*/ -#define USBREQ_SET_INTERFACE 0x0BU /*!< USB set interface request*/ -#define USBREQ_SYNCH_FRAME 0x0CU /*!< USB synchronize frame request*/ - -/* descriptor types of usb specifications */ -#define USB_DESCTYPE_DEVICE 0x01U /*!< USB device descriptor type*/ -#define USB_DESCTYPE_CONFIGURATION 0x02U /*!< USB configuration descriptor type*/ -#define USB_DESCTYPE_STRING 0x03U /*!< USB string descriptor type*/ -#define USB_DESCTYPE_INTERFACE 0x04U /*!< USB interface descriptor type*/ -#define USB_DESCTYPE_ENDPOINT 0x05U /*!< USB endpoint descriptor type*/ -#define USB_DESCTYPE_DEVICE_QUALIFIER 0x06U /*!< USB device qualtfier descriptor type*/ -#define USB_DESCTYPE_OTHER_SPEED_CONFIGURATION 0x07U /*!< USB other speed configuration descriptor type*/ -#define USB_DESCTYPE_INTERFACE_POWER 0x08U /*!< USB interface power descriptor type*/ - -#define USB_DESCTYPE_HID 0x21U /*!< USB HID descriptor type*/ -#define USB_DESCTYPE_HID_REPORT 0x22U /*!< USB HID report descriptor type*/ - -#define USB_DEVDESC_SIZE 18U /*!< USB device descriptor size*/ -#define USB_CFGDESC_SIZE 9U /*!< USB configure descriptor size*/ -#define USB_INTDESC_SIZE 9U /*!< USB interface descriptor size*/ -#define USB_EPDESC_SIZE 7U /*!< USB endpoint descriptor size*/ - -/* descriptor type and descriptor index */ -/* use the following values when USB host need to get descriptor */ -#define USB_DEVDESC ((USB_DESCTYPE_DEVICE << 8U) & 0xFF00U) /*!< USB device operation marco */ -#define USB_CFGDESC ((USB_DESCTYPE_CONFIGURATION << 8U) & 0xFF00U) /*!< USB configuration operation marco */ -#define USB_STRDESC ((USB_DESCTYPE_STRING << 8U) & 0xFF00U) /*!< USB string operation marco */ -#define USB_INTDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB interface operation marco */ -#define USB_EPDESC ((USB_DESCTYPE_INTERFACE << 8U) & 0xFF00U) /*!< USB endpoint operation marco */ -#define USB_DEVQUADESC ((USB_DESCTYPE_DEVICE_QUALIFIER << 8U) & 0xFF00U) /*!< USB device qualifier operation marco */ -#define USB_OSPCFGDESC ((USB_DESCTYPE_OTHER_SPEED_CONFIGURATION << 8U) & 0xFF00U) /*!< USB other speed configuration operation marco */ -#define USB_INTPWRDESC ((USB_DESCTYPE_INTERFACE_POWER << 8U) & 0xFF00U) /*!< USB interface power operation marco */ -#define USB_HIDREPDESC ((USB_DESCTYPE_HID_REPORT << 8U) & 0xFF00U) /*!< USB HID report operation marco */ -#define USB_HIDDESC ((USB_DESCTYPE_HID << 8U) & 0xFF00U) /*!< USB HID operation marco */ - -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (uint16_t)(((uint16_t)(*(((uint8_t *)(addr)) + 1U))) << 8U)) - -/* supported classes */ -#define USB_MSC_CLASS 0x08U /*!< USB MSC class*/ -#define USB_HID_CLASS 0x03U /*!< USB HID class*/ - -/* interface descriptor field values for hid boot protocol */ -#define HID_BOOT_CODE 0x01U /*!< USB HID boot code*/ -#define HID_KEYBRD_BOOT_CODE 0x01U /*!< USB HID keyboard boot code*/ -#define HID_MOUSE_BOOT_CODE 0x02U /*!< USB HID mouse boot code*/ - -/* as per usb specs 9.2.6.4 :standard request with data request timeout: 5sec - standard request with no data stage timeout : 50ms */ -#define DATA_STAGE_TIMEOUT 5000U /*!< USB data stage timeout*/ -#define NODATA_STAGE_TIMEOUT 50U /*!< USB no data stage timeout*/ - -#define USBH_CFG_DESC_SET_SIZE (USB_CFGDESC_SIZE + USB_INTDESC_SIZE \ - + (USBH_MAX_EP_NUM * USB_EPDESC_SIZE)) /*!< USB host set configuration descriptor size */ - -#pragma pack(1) - -typedef union -{ - uint8_t data[8]; - - struct _setup_packet_struct - { - uint8_t bmRequestType; /*!< type of request */ - uint8_t bRequest; /*!< request of setup packet */ - uint16_t wValue; /*!< value of setup packet */ - uint16_t wIndex; /*!< index of setup packet */ - uint16_t wLength; /*!< length of setup packet */ - } b; -}usb_setup_union; - -typedef struct -{ - uint8_t bLength; /*!< size of the descriptor */ - uint8_t bDescriptorType; /*!< type of the descriptor */ -} usb_descriptor_header_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t bcdUSB; /*!< BCD of the supported USB specification */ - uint8_t bDeviceClass; /*!< USB device class */ - uint8_t bDeviceSubClass; /*!< USB device subclass */ - uint8_t bDeviceProtocol; /*!< USB device protocol */ - uint8_t bMaxPacketSize0; /*!< size of the control (address 0) endpoint's bank in bytes */ - uint16_t idVendor; /*!< vendor ID for the USB product */ - uint16_t idProduct; /*!< unique product ID for the USB product */ - uint16_t bcdDevice; /*!< product release (version) number */ - uint8_t iManufacturer; /*!< string index for the manufacturer's name */ - uint8_t iProduct; /*!< string index for the product name/details */ - uint8_t iSerialNumber; /*!< string index for the product's globally unique hexadecimal serial number */ - uint8_t bNumberConfigurations; /*!< total number of configurations supported by the device */ -} usb_descriptor_device_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint16_t wTotalLength; /*!< size of the configuration descriptor header,and all sub descriptors inside the configuration */ - uint8_t bNumInterfaces; /*!< total number of interfaces in the configuration */ - uint8_t bConfigurationValue; /*!< configuration index of the current configuration */ - uint8_t iConfiguration; /*!< index of a string descriptor describing the configuration */ - uint8_t bmAttributes; /*!< configuration attributes */ - uint8_t bMaxPower; /*!< maximum power consumption of the device while in the current configuration */ -} usb_descriptor_configuration_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size */ - - uint8_t bInterfaceNumber; /*!< index of the interface in the current configuration */ - uint8_t bAlternateSetting; /*!< alternate setting for the interface number */ - uint8_t bNumEndpoints; /*!< total number of endpoints in the interface */ - uint8_t bInterfaceClass; /*!< interface class ID */ - uint8_t bInterfaceSubClass; /*!< interface subclass ID */ - uint8_t bInterfaceProtocol; /*!< interface protocol ID */ - uint8_t iInterface; /*!< index of the string descriptor describing the interface */ -} usb_descriptor_interface_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - - uint8_t bEndpointAddress; /*!< logical address of the endpoint */ - uint8_t bmAttributes; /*!< endpoint attributes */ - uint16_t wMaxPacketSize; /*!< size of the endpoint bank, in bytes */ - uint8_t bInterval; /*!< polling interval in milliseconds for the endpoint if it is an INTERRUPT or ISOCHRONOUS type */ -} usb_descriptor_endpoint_struct; - -typedef struct -{ - usb_descriptor_header_struct Header; /*!< descriptor header, including type and size. */ - uint16_t wLANGID; /*!< LANGID code */ -}usb_descriptor_language_id_struct; - -#pragma pack() - -#endif /* USB_STD_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_core.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_core.h deleted file mode 100644 index 91e69eb724..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_core.h +++ /dev/null @@ -1,77 +0,0 @@ -/*! - \file usbd_core.h - \brief USB device mode core driver header file - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_CORE_H -#define USBD_CORE_H - -#include "usbd_conf.h" -#include "usb_core.h" -#include "usbd_std.h" - -/* device status */ -#define USB_STATUS_DEFAULT 1U /* default status */ -#define USB_STATUS_ADDRESSED 2U /* addressed status */ -#define USB_STATUS_CONFIGURED 3U /* configured status */ -#define USB_STATUS_SUSPENDED 4U /* suspended status */ - -/* function declarations */ -/* initailizes the USB device-mode handler stack */ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* endpoint initialization */ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc); -/* endpoint deinitialize */ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* endpoint prepare to receive data */ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len); -/* endpoint prepare to transmit data */ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len); -/* transmit data on the control channel */ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* receive data on the control channel */ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len); -/* transmit status on the control channel */ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev); -/* receive status on the control channel */ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev); -/* set an endpoint to STALL status */ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* clear endpoint stalled status */ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* flushes the FIFOs */ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* get the received data length */ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num); - -#endif /* USBD_CORE_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_int.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_int.h deleted file mode 100644 index b2b8d99e88..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_int.h +++ /dev/null @@ -1,53 +0,0 @@ -/*! - \file usbd_int.h - \brief USB device mode interrupt handler header file - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_INT_H -#define USBD_INT_H - -#include "usbd_core.h" - -typedef struct -{ - uint8_t (*SOF) (usb_core_handle_struct *pudev); -}usbd_int_cb_struct; - -extern usbd_int_cb_struct *usbd_int_fops; - -/* function declarations */ -/* USB device-mode interrupts global service routine handler */ -uint32_t usbd_isr (usb_core_handle_struct *pudev); - -#endif /* USBD_INT_H */ - diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_std.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_std.h deleted file mode 100644 index d968082a1a..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbd_std.h +++ /dev/null @@ -1,94 +0,0 @@ -/*! - \file usbd_std.h - \brief USB 2.0 standard defines - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBD_STD_H -#define USBD_STD_H - -#include "usb_std.h" -#include "usbd_core.h" -#include "usbd_conf.h" -#include - -#define USBD_LANGID_STR_IDX 0x00U /*!< USB language ID string index*/ -#define USBD_MFC_STR_IDX 0x01U /*!< USB manufacturer string index*/ -#define USBD_PRODUCT_STR_IDX 0x02U /*!< USB product string index*/ -#define USBD_SERIAL_STR_IDX 0x03U /*!< USB serial string index*/ -#define USBD_CONFIG_STR_IDX 0x04U /*!< USB configuration string index*/ -#define USBD_INTERFACE_STR_IDX 0x05U /*!< USB interface string index*/ - -#define USB_STATUS_REMOTE_WAKEUP 0x02U /*!< USB remote wakeup status*/ -#define USB_STATUS_SELF_POWERED 0x01U /*!< USB self power status*/ - -#define USB_FEATURE_ENDP_HALT 0x00U /*!< USB halt endpoint feature*/ -#define USB_FEATURE_REMOTE_WAKEUP 0x01U /*!< USB remote wakeup feature*/ -#define USB_FEATURE_TEST_MODE 0x02U /*!< USB test mode feature*/ - -#define ENG_LANGID 0x0409U /*!< USB english language id*/ -#define CHN_LANGID 0x0804U /*!< USB chinese language id*/ - -#define USB_DEVICE_DESC_SIZE 0x12U /*!< USB device descriptor size*/ - -#define LOWBYTE(x) ((uint8_t)((x) & 0x00FFU)) /*!< USB lowbyte operation marco*/ -#define HIGHBYTE(x) ((uint8_t)(((x) & 0xFF00U) >> 8U)) /*!< USB highbyte operation marco*/ - -#define USB_MIN(a, b) (((a) < (b)) ? (a) : (b)) /*!< USB minimum operation marco*/ - -#define WIDE_STRING(string) _WIDE_STRING(string) -#define _WIDE_STRING(string) L##string - -#define USBD_STRING_DESC(string) \ - (uint8_t *)&(struct { \ - uint8_t _len; \ - uint8_t _type; \ - wchar_t _data[sizeof(string)]; \ - }) { \ - sizeof(WIDE_STRING(string)) + 2U - 2U, \ - USB_DESCTYPE_STRING, \ - WIDE_STRING(string) \ - } - -#define IS_NOT_EP0(ep_addr) (((ep_addr) != 0x00U) && ((ep_addr) != 0x80U)) - -/* function declarations */ -/* USB device setup transaction*/ -usbd_status_enum usbd_setup_transaction (usb_core_handle_struct *pudev); -/* USB device out transaction*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device in transaction*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num); -/* USB device enum error handle*/ -void usbd_enum_error (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -#endif /* USBD_STD_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_core.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_core.h deleted file mode 100644 index f2b16fc179..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_core.h +++ /dev/null @@ -1,307 +0,0 @@ -/*! - \file usbh_core.h - \brief header file for usbh_core.c - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_CORE_H -#define USBH_CORE_H - -#include "usbh_conf.h" -#include "usb_std.h" -#include "usb_core.h" - -#define MSC_CLASS 0x08 /*!< the MSC class define */ -#define HID_CLASS 0x03 /*!< the HID class define */ -#define MSC_PROTOCOL 0x50 /*!< the MSC protocal define */ -#define CBI_PROTOCOL 0x01 /*!< the CBI protocal define */ - -#define USBH_DEVICE_ADDRESS_DEFAULT 0U /*!< the default device address define */ -#define USBH_DEVICE_ADDRESS 1U /*!< the device address define */ -#define USBH_MAX_ERROR_COUNT 2U /*!< the max error count define */ - -#define HOST_USER_SELECT_CONFIGURATION 1U /*!< the user select configuration define */ -#define HOST_USER_CLASS_ACTIVE 2U /*!< the user class active define */ -#define HOST_USER_CLASS_SELECTED 3U /*!< the user class selected define */ -#define HOST_USER_CONNECTION 4U /*!< the user connecttion define */ -#define HOST_USER_DISCONNECTION 5U /*!< the user disconnection define */ -#define HOST_USER_UNRECOVERED_ERROR 6U /*!< the user unrecovered error define */ - -#define MAX_USBH_STATE_STACK_DEEP 4 /*!< the max state stack deep define */ -#define MAX_USBH_STATE_TABLE_NUM 10U /*!< the max state table number */ - -#define HOST_FSM_ID 0U /*!< the host state table id */ -#define ENUM_FSM_ID 1U /*!< the enum state table id */ -#define CMD_FSM_ID 2U /*!< the cmd state table id */ -#define CTRL_FSM_ID 3U /*!< the ctrl state table id */ -#define CLASS_REQ_FSM_ID 4U /*!< the class req state table id */ -#define CLASS_FSM_ID 5U /*!< the class state table id */ - -#define UP_STATE 100U /*!< up state define */ -#define GO_TO_UP_STATE_EVENT 100U /*!< go to up state event define */ - -#define HOST_HANDLE_TABLE_SIZE 9U /*!< the host handle table size define */ - -/* the enum of host state */ -typedef enum -{ - HOST_IDLE = 0, /* the host idle state definition */ - HOST_DEV_ATTACHED, /* the host device attached state definition */ - HOST_DEV_DETACHED, /* the host device detached state definition */ - HOST_DETECT_DEV_SPEED, /* the host detect device speed state definition */ - HOST_ENUMERATION, /* the host enumeration state definition */ - HOST_CLASS_REQUEST, /* the host class request state definition */ - HOST_CLASS, /* the host class state definition */ - HOST_USER_INPUT, /* the host user input state definition */ - HOST_SUSPENDED, /* the host suspended state definition */ - HOST_ERROR /* the host error state definition */ -}host_state_enum; - -/* the enum of host event */ -typedef enum -{ - HOST_EVENT_ATTACHED = 0, /* the host attached event */ - HOST_EVENT_ENUM, /* the host enum event */ - HOST_EVENT_USER_INPUT, /* the host user input event */ - HOST_EVENT_CLASS_REQ, /* the host class request event */ - HOST_EVENT_CLASS, /* the host class event */ - HOST_EVENT_ERROR, /* the host error event */ - HOST_EVENT_DEV_DETACHED, /* the host device detached event */ - HOST_EVENT_IDLE /* the host idle event */ -}host_event_enum; - -/* the enum of enum state */ -typedef enum -{ - ENUM_IDLE = 0, /* the enum idle state definition */ - ENUM_SET_ADDR, /* the enum set address state definition */ - ENUM_GET_FULL_DEV_DESC, /* the enum get full device descripter state definition */ - ENUM_GET_CFG_DESC, /* the enum get configuration descripter state definition */ - ENUM_GET_FULL_CFG_DESC, /* the enum get full configuration descripter state definition */ - ENUM_GET_MFC_STRING_DESC, /* the enum get MFC string descripter state definition */ - ENUM_GET_PRODUCT_STRING_DESC, /* the enum get product string descripter state definition */ - ENUM_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string descripter state definition */ - ENUM_SET_CONFIGURATION, /* the enum set congiguration state definition */ - ENUM_DEV_CONFIGURED /* the enum device configuration state definition */ -}enum_state_enum; - -/* the enum of ctrl state */ -typedef enum -{ - CTRL_IDLE = 0, /* the ctrl idle state definition */ - CTRL_SETUP, /* the ctrl setup state definition */ - CTRL_DATA, /* the ctrl data state definition */ - CTRL_STATUS, /* the ctrl status state definition */ - CTRL_ERROR, /* the ctrl error state definition */ - CTRL_STALLED, /* the ctrl stalled state definition */ - CTRL_COMPLETE /* the ctrl complete state definition */ -}ctrl_state_enum; - -/* the enum of host status */ -typedef enum -{ - USBH_OK = 0, /* the usbh ok status definition */ - USBH_BUSY, /* the usbh busy status definition */ - USBH_FAIL, /* the usbh fail status definition */ - USBH_NOT_SUPPORTED, /* the usbh not supported status definition */ - USBH_UNRECOVERED_ERROR, /* the usbh unrecovered error status definition */ - USBH_SPEED_UNKNOWN_ERROR, /* the usbh speed unknown error status definition */ - USBH_APPLY_DEINIT /* the usbh apply deinit status definition */ -}usbh_status_enum; - -/* the state of user action */ -typedef enum -{ - USBH_USER_NO_RESP = 0, /* the user no response */ - USBH_USER_RESP_OK = 1, /* the user response ok */ -}usbh_user_status_enum; - -/* control transfer information */ -typedef struct -{ - uint8_t hc_in_num; /* the host in channel number */ - uint8_t hc_out_num; /* the host out channel number */ - uint8_t ep0_size; /* the endpoint 0 max packet size */ - uint8_t error_count; /* the error count */ - uint16_t length; /* the length */ - uint16_t timer; /* the timer */ - uint8_t *buff; /* the buffer */ - usb_setup_union setup; /* the setup packet */ -}usbh_ctrl_struct; - -/* device property */ -typedef struct -{ - uint8_t address; /* the device address */ - uint8_t speed; /* the device speed */ - usb_descriptor_device_struct dev_desc; /* the device descripter */ - usb_descriptor_configuration_struct cfg_desc; /* the configuration descripter */ - usb_descriptor_interface_struct itf_desc[USBH_MAX_INTERFACES_NUM]; /* the interface descripter */ - usb_descriptor_endpoint_struct ep_desc[USBH_MAX_INTERFACES_NUM][USBH_MAX_EP_NUM]; /* the endpoint descripter */ -}usbh_device_struct; - -/* user callbacks */ -typedef struct -{ - void (*init) (void); /* the user callback init function */ - void (*deinit) (void); /* the user callback deinit function */ - void (*device_connected) (void); /* the user callback device connected function */ - void (*device_reset) (void); /* the user callback device reset function */ - void (*device_disconnected) (void); /* the user callback device disconnected function */ - void (*over_current_detected) (void); /* the user callback over current detected function */ - void (*device_speed_detected) (uint8_t device_speed); /* the user callback device speed detected function */ - void (*device_desc_available) (void *devDesc); /* the user callback device descrpiter available function */ - void (*device_address_set) (void); /* the user callback set device address function */ - - void (*configuration_desc_available)(usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct *ep_desc); - /* the configuration descripter available function */ - - void (*manufacturer_string) (void *mfc_string); /* the user callback manufacturer string function */ - void (*product_string) (void *prod_string); /* the user callback product string function */ - void (*serial_num_string) (void *serial_string); /* the user callback serial number string function */ - void (*enumeration_finish) (void); /* the user callback enumeration finish function */ - usbh_user_status_enum (*user_input) (void); /* the user callback user input function */ - int (*user_application) (usb_core_handle_struct *pudev, uint8_t id); - /* the user callback user appliction function */ - void (*device_not_supported) (void); /* the user callback device not supported function */ - void (*unrecovered_error) (void); /* the user callback unrecovered error function */ -}usbh_user_callback_struct; - -/* the backup state struct */ -typedef struct -{ - host_state_enum host_backup_state; /* the host backup state */ - enum_state_enum enum_backup_state; /* the enum backup state */ - ctrl_state_enum ctrl_backup_state; /* the ctrl backup state */ - uint8_t class_req_backup_state;/* the class request backup state */ - uint8_t class_backup_state; /* the class backup state */ -} backup_state_struct; - -/* host information */ -typedef struct -{ - backup_state_struct usbh_backup_state; /* the usbh backup state variable */ - usbh_ctrl_struct control; /* the control struct variable */ - usbh_device_struct device; /* the device struct variable */ - usbh_user_callback_struct *usr_cb; /* the user callback function */ - usbh_status_enum (*class_init) (usb_core_handle_struct *pudev, void *phost); /* the class init function */ - void (*class_deinit) (usb_core_handle_struct *pudev, void *phost); /* the class deinit function */ -}usbh_host_struct; - -/* the action function definition */ -typedef usbh_status_enum (*ACT_FUN) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void* pustate); - -/* the state table struct */ -typedef struct -{ - uint8_t cur_state; /* the current state */ - uint8_t cur_event; /* the current event */ - uint8_t next_state; /* the next state */ - ACT_FUN event_action_fun; /* the event action function entry */ -} state_table_struct; - -/* the state stack struct */ -typedef struct -{ - uint8_t state; /* the state in state stack */ - state_table_struct* table; /* the table in state stack */ - uint8_t table_size; /* the table size in state stack */ -} usbh_state_stack_struct; - -/* the state regist table struct */ -typedef struct -{ - uint8_t id; /* the id of the state table */ - state_table_struct* table; /* the table entry to regist */ - uint8_t table_size; /* the table size to regist */ -} usbh_state_regist_table_struct; - -/* the state handle struct */ -typedef struct -{ - uint8_t usbh_current_state; /* current state */ - uint8_t usbh_current_state_table_size; /* current state table size */ - state_table_struct* usbh_current_state_table; /* current state table */ - - usbh_state_stack_struct stack[MAX_USBH_STATE_STACK_DEEP]; /* the stack of state table */ - int8_t usbh_current_state_stack_top; /* the current state top */ - - usbh_state_regist_table_struct usbh_regist_state_table[MAX_USBH_STATE_TABLE_NUM]; /* the array of regist state table */ - uint8_t usbh_regist_state_table_num; /* the number of regist state table */ -} usbh_state_handle_struct; - -/* function declarations */ -/* the host core driver function */ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* initialize the host portion of the driver */ -uint32_t hcd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id); -/* check if the device is connected */ -uint32_t hcd_is_device_connected (usb_core_handle_struct *pudev); -/* this function returns the last URBstate */ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* this function returns the last URBstate */ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num); -/* de-initialize host */ -usbh_status_enum usbh_deinit (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate); - -/* the state core driver function */ -/* state core driver init */ -void scd_init (usbh_state_handle_struct* pustate); -/* state core driver table regist */ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size); -/* state core driver begin */ -void scd_begin (usbh_state_handle_struct* pustate, uint8_t table_id); -/* state core driver move state */ -void scd_state_move (usbh_state_handle_struct* pustate, uint8_t state); -/* state core driver event handle */ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state); -/* state core driver table push */ -void scd_table_push (usbh_state_handle_struct* pustate); -/* state core driver table pop */ -void scd_table_pop (usbh_state_handle_struct* pustate); -/* the function is only used to state move */ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* the function to the up state */ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -#endif /* USBH_CORE_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h deleted file mode 100644 index 19534dc518..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_ctrl.h +++ /dev/null @@ -1,69 +0,0 @@ -/*! - \file usbh_ctrl.h - \brief header file for usbh_ctrl.c - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_CTRL_H -#define USBH_CTRL_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -#define CTRL_HANDLE_TABLE_SIZE 13U /*!< the ctrl handle table size define */ - -extern state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE]; -extern uint8_t ctrl_polling_handle_flag; - -/* the enum of CTRL event */ -typedef enum -{ - CTRL_EVENT_IDLE = 0, /* the ctrl idle event */ - CTRL_EVENT_SETUP, /* the ctrl setup event */ - CTRL_EVENT_DATA, /* the ctrl data event */ - CTRL_EVENT_STATUS, /* the ctrl status event */ - CTRL_EVENT_COMPLETE, /* the ctrl complete event */ - CTRL_EVENT_ERROR, /* the ctrl error event */ - CTRL_EVENT_STALLED, /* the ctrl stalled event */ -}ctrl_event_enum; - -/* function declarations */ -/* the polling function of control transfer state handle */ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* send datas from the host channel */ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num, uint16_t len); -/* send the setup packet to the device */ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num); -/* this function prepare a hc and start a transfer */ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num); - -#endif /* USBH_CTRL_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_hcs.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_hcs.h deleted file mode 100644 index 6e566e6ff7..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_hcs.h +++ /dev/null @@ -1,70 +0,0 @@ -/*! - \file usbh_hcs.h - \brief header file for usbh_hcs.c - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_HCS_H -#define USBH_HCS_H - -#include "usbh_core.h" - -#define HC_MAX 8U - -#define HC_OK 0x0000U -#define HC_USED 0x8000U -#define HC_ERROR 0xFFFFU -#define HC_USED_MASK 0x7FFFU - -/* function declarations */ -/* allocate a new channel for the pipe */ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr); -/* free all usb host channel */ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev); -/* free the usb host channel */ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index); -/* open a channel */ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); -/* modify a channel */ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps); - -#endif /* USBH_HCS_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_int.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_int.h deleted file mode 100644 index b5fe3bb951..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_int.h +++ /dev/null @@ -1,54 +0,0 @@ -/*! - \file usbh_int.h - \brief USB host mode interrupt handler header file - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_INT_H -#define USBH_INT_H - -#include "usb_core.h" - -typedef struct -{ - uint8_t (*sof) (usb_core_handle_struct *pudev); - uint8_t (*device_connected) (usb_core_handle_struct *pudev); - uint8_t (*device_disconnected) (usb_core_handle_struct *pudev); -}usbh_hcd_int_cb_struct; - -extern usbh_hcd_int_cb_struct *usbh_hcd_int_fops; - -/* function declarations */ -/* handle global host interrupt */ -uint32_t usbh_isr (usb_core_handle_struct *pudev); - -#endif /* USBH_INT_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_std.h b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_std.h deleted file mode 100644 index 48bc65c785..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Include/usbh_std.h +++ /dev/null @@ -1,98 +0,0 @@ -/*! - \file usbh_std.h - \brief header file for usbh_std.c - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef USBH_STD_H -#define USBH_STD_H - -#include "usbh_core.h" -#include "usbh_usr.h" - -/* standard feature selector for clear feature command */ -#define FEATURE_SELECTOR_ENDPOINT 0x00U -#define FEATURE_SELECTOR_DEVICE 0x01U - -#define USBH_SETUP_PACKET_SIZE 8U /* setup packet size */ -#define ENUM_HANDLE_TABLE_SIZE 10U /* enumerate handle table size */ - -extern uint8_t usbh_cfg_desc[512]; -extern uint8_t enum_polling_handle_flag; -extern state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE]; - -typedef enum -{ - ENUN_EVENT_IDLE = 0, /* the enum idle event */ - ENUM_EVENT_SET_ADDR, /* the enum set address event */ - ENUN_EVENT_GET_FULL_DEV_DESC, /* the enum get full device descripter event */ - ENUN_EVENT_GET_CFG_DESC, /* the enum get congiguration descripter event */ - ENUN_EVENT_GET_FULL_CFG_DESC, /* the enum get full configuration descripter event */ - ENUN_EVENT_GET_MFC_STRING_DESC, /* the enum get MFC string descripter event */ - ENUN_EVENT_GET_PRODUCT_STRING_DESC, /* the enum get product string event */ - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, /* the enum get serialnum string event */ - ENUN_EVENT_SET_CONFIGURATION, /* the enum set configuration event */ - ENUN_EVENT_DEV_CONFIGURED /* the enum device configured event */ -}enum_event_enum; - -/* function declarations */ -/* the polling function of enumeration state */ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -/* get descriptor in usb host enumeration stage */ -void usbh_enum_desc_get (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len); -/* set address in usb host enumeration stage */ -void usbh_enum_addr_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint8_t device_address); -/* set configuration in usb host enumeration stage */ -void usbh_enum_cfg_set (usb_core_handle_struct *pudev, usbh_host_struct *puhost, uint16_t cfg_idx); -/* parse the device descriptor */ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len); -/* parse the configuration descriptor */ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len); -/* parse the interface descriptor */ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf); -/* parse the endpoint descriptor */ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf); -/* parse the string descriptor */ -void usbh_string_desc_parse (uint8_t *psrc, uint8_t *pdest, uint16_t len); -/* get the next descriptor header */ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr); - -#endif /* USBH_STD_H */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c deleted file mode 100644 index 0ebd5ddea2..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/system_gd32f3x0.c +++ /dev/null @@ -1,665 +0,0 @@ -/*! - \file system_gd32f3x0.c - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for - GD32F3x0 Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32f3x0.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -/* select a system clock by uncommenting the following line */ -#if defined (GD32F330) -//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) -//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) -#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) -//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) -#endif /* GD32F330 */ - -#if defined (GD32F350) -//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) -//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000) -//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000) -//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) -#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2 (uint32_t)(96000000) -//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) -//#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2 (uint32_t)(108000000) -#endif /* GD32F350 */ - -#define SEL_IRC8M 0x00 -#define SEL_HXTAL 0x01 -#define SEL_PLL 0x02 - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_8M_HXTAL -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; -static void system_clock_8m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; -static void system_clock_72m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL; -static void system_clock_84m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2; -static void system_clock_84m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; -static void system_clock_96m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2; -static void system_clock_96m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; -static void system_clock_108m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2; -static void system_clock_108m_irc8m(void); - -#else -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; -static void system_clock_8m_irc8m(void); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit (void) -{ - /* enable IRC8M */ - RCU_CTL0 |= RCU_CTL0_IRC8MEN; - while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ - } - /* reset RCU */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ - RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); -#if (defined(GD32F350)) - RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC); - RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2); -#endif /* GD32F350 */ - RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); - RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL); - RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; - RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; - RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN; - RCU_INT = 0x00000000U; - RCU_ADDINT = 0x00000000U; - /* configure system clock */ - system_clock_config(); -} - -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_8M_HXTAL - system_clock_8m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) - system_clock_84m_hxtal(); -#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) - system_clock_84m_irc8m(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) - system_clock_96m_hxtal(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) - system_clock_96m_irc8m(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) - system_clock_108m_hxtal(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) - system_clock_108m_irc8m(); -#else - system_clock_8m_irc8m(); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ -} - -#ifdef __SYSTEM_CLOCK_8M_HXTAL -/*! - \brief configure the system clock to 8M by HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL * 9 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL9); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL) -/*! - \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_84m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL /2 * 21 = 84 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= RCU_PLL_PREDV2; - RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL21); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 84M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_84m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 21 = 84 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -/*! - \brief configure the system clock to 96M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL /2 * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= RCU_PLL_PREDV2; - RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL24); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 96M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL24); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -/*! - \brief configure the system clock to 84M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - return; - } - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* PLL = HXTAL /2 * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5); - RCU_CFG1 |= RCU_PLL_PREDV2; - RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL27); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 108M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - /* PLL = (IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#else -/*! - \brief configure the system clock to 8M by IRC8M - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select IRC8M as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; - - /* wait until IRC8M is selected as system clock */ - while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ - } -} -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate (void) -{ - uint32_t sws = 0U; - uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; - /* exponent of AHB clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* get the value of PLLMF[3:0] */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - pllmf4 = GET_BITS(RCU_CFG0, 27, 27); - pllmf5 = GET_BITS(RCU_CFG1, 31, 31); - /* high 16 bits */ - if(1U == pllmf4){ - pllmf += 17U; - }else{ - pllmf += 2U; - } - if(1U == pllmf5){ - pllmf += 31U; - } - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = GET_BITS(RCU_CFG0, 16, 16); - if(0U != pllsel){ - prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); - if(0U == pllpresel){ - SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf; - }else{ - SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf; - } - }else{ - SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - SystemCoreClock >>= clk_exp; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usb_core.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usb_core.c deleted file mode 100644 index 336645e746..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usb_core.c +++ /dev/null @@ -1,959 +0,0 @@ -/*! - \file usb_core.c - \brief USB core driver which can operate in host-mode and device-mode - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usb_core.h" - -static void usb_commonint_enable (usb_core_handle_struct *pudev); -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev); - -/*! - \brief enable the commmon interrupts which are used in both device and host modes - \param[in] pudev: pointer to selected usb device - \param[out] none - \retval none -*/ -static void usb_commonint_enable (usb_core_handle_struct *pudev) -{ -#ifndef USE_OTG_MODE - - /* clear any pending USB interrupts */ - USB_GOTGINTF = 0xFFFFFFFFU; - -#endif /* USE_OTG_MODE */ - - /* enable the usb wakeup and suspend interrupts */ - USB_GINTEN = GINTEN_WKUPIE | GINTEN_SPIE; - -#ifdef USE_OTG_MODE - - /* enable the OTG interrupts, session interrrupts and connector ID pin interrupt */ - USB_GINTEN |= GINTEN_OTGIE | GINTEN_SESIE | GINTEN_CIDPSCIE; - -#endif /* USE_OTG_MODE */ -} - -/*! - \brief soft reset of the OTG_FS core - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -static usb_status_enum usb_core_reset (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - /* enable core soft reset */ - USB_GRSTCTL |= GRSTCTL_CSRST; - - /* wait for the core to be soft reset */ - do { - if (++count > 200000U) { - break; - } - } while (1U == (USB_GRSTCTL & GRSTCTL_CSRST)); - - /* wait for addtional 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief write a packet into the Tx FIFO associated with the endpoint - \param[in] src: pointer to source buffer - \param[in] chep_num: channel or endpoint identifier which is in (0..3) - \param[in] len: packet length - \param[out] none - \retval operation status -*/ -usb_status_enum usb_fifo_write (uint8_t *src, uint8_t chep_num, uint16_t len) -{ - uint32_t count32b = 0U, i = 0U; - __IO uint32_t *fifo = USB_FIFO(chep_num); - - count32b = (len + 3U) / 4U; - - for (i = 0U; i < count32b; i++) { - *fifo = *((__packed uint32_t *)src); - - src += 4U; - } - - return USB_OK; -} - -/*! - \brief read a packet from the Rx FIFO associated with the endpoint - \param[in] dest: pointer to destination buffer - \param[in] len: packet length - \param[out] none - \retval void type pointer -*/ -void *usb_fifo_read (uint8_t *dest, uint16_t len) -{ - uint32_t i = 0U; - uint32_t count32b = (len + 3U) / 4U; - - __IO uint32_t *fifo = USB_FIFO(0U); - - for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)dest = *fifo; - - dest += 4U; - } - - return ((void *)dest); -} - -/*! - \brief initialize core parameters - \param[in] pudev: pointer to usb device - \param[in] core_id: USB core id - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_select (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* at startup the core is in FS mode */ - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - /* initialize the core parameters */ - if (USB_FS_CORE_ID == core_id) { - - pudev->cfg.core_id = USB_FS_CORE_ID; - - /* set the host channel numbers */ - pudev->cfg.host_channel_num = USBFS_MAX_HOST_CHANNELCOUNT; - - /* set the device endpoint numbers */ - pudev->cfg.dev_endp_num = USBFS_MAX_DEV_EPCOUNT; - - /* fifo size is in terms of DWORD */ - pudev->cfg.max_fifo_size = USBFS_MAX_FIFO_WORDLEN; - - /* OTG_FS core use embedded physical layer */ - pudev->cfg.phy_interface = USB_CORE_EMBEDDED_PHY; - - #ifdef USBFS_SOF_OUTPUT_ENABLED - pudev->cfg.sof_output = 1U; - #endif /* USBFS_SOF_OUTPUT_ENABLED */ - - #ifdef USBFS_LOW_PWR_MGMT_SUPPORT - pudev->cfg.low_power = 1U; - #endif /* USBFS_LOW_PWR_MGMT_SUPPORT */ - } - - return USB_OK; -} - -/*! - \brief initializes the USB controller registers and - prepares the core device mode or host mode operation - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_core_init (usb_core_handle_struct *pudev) -{ - /* soft reset the core */ - usb_core_reset(pudev); - - /* active the transceiver and enable vbus sensing */ - USB_GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; - - /* set Tx FIFO empty level to half empty mode */ - USB_GAHBCS &= ~GAHBCS_TXFTH | TXFIFO_EMPTY_HALF; - -#ifndef VBUS_SENSING_ENABLED - USB_GCCFG |= GCCFG_VBUSIG; -#endif /* VBUS_SENSING_ENABLED */ - - if(pudev->cfg.sof_output){ - USB_GCCFG |= GCCFG_SOFOEN; - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - -#ifdef USE_OTG_MODE - /* enable OTG features */ - USB_GUSBCS |= GUSBCS_HNPCAP | GUSBCS_SRPCAP; - USB_OTG_EnableCommonInt(pudev); - -#endif /* USE_OTG_MODE */ - - return USB_OK; -} - -/*! - \brief flush a Tx FIFO or all Tx FIFOs - \param[in] pudev: pointer to usb device - \param[in] fifo_num: FIFO number which is in (0..3) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_txfifo_flush (usb_core_handle_struct *pudev, uint8_t fifo_num) -{ - uint32_t count = 0U; - - USB_GRSTCTL &= ~GRSTCTL_TXFNUM; - USB_GRSTCTL = ((uint32_t)fifo_num << 6U) | GRSTCTL_TXFF; - - /* wait for Tx FIFO flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_TXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief flush the entire Rx FIFO - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_rxfifo_flush (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - - USB_GRSTCTL = GRSTCTL_RXFF; - - /* wait for Rx FIFO flush bit is set */ - do { - if (++count > 200000U) { - break; - } - } while (USB_GRSTCTL & GRSTCTL_RXFF); - - /* wait for 3 PHY clocks */ - if (NULL != pudev->udelay) { - pudev->udelay(3U); - } - - return USB_OK; -} - -/*! - \brief set operation mode (host or device) - \param[in] pudev: pointer to usb device - \param[in] mode: operation mode which need to set - \arg HOST_MODE - \arg DEVICE_MODE - \param[out] none - \retval operation status -*/ -usb_status_enum usb_mode_set (usb_core_handle_struct *pudev, uint8_t mode) -{ - if (HOST_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FDM; - USB_GUSBCS |= GUSBCS_FHM; - } else if (DEVICE_MODE == mode) { - USB_GUSBCS &= ~GUSBCS_FHM; - USB_GUSBCS |= GUSBCS_FDM; - } else { - /* no operation */ - } - - if (NULL != pudev->mdelay) { - pudev->mdelay(50U); - } - - return USB_OK; -} - -#ifdef USE_HOST_MODE - -/*! - \brief initializes USB core for host mode - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i = 0U; - __IO uint32_t nptxfifolen = 0U; - __IO uint32_t ptxfifolen = 0U; - -#ifdef USE_OTG_MODE - __IO uint32_t otgctl = 0; -#endif /* USE_OTG_MODE */ - - /* restart the PHY clock */ - USB_PWRCLKCTL = 0U; - - /* initialize host configuration register */ - if (USB_CORE_ULPI_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_30_60_MHZ); - } else { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - - /* configure data FIFO sizes */ - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set Rx FIFO size */ - USB_GRFLEN = USBFS_RX_FIFO_SIZE; - - /* set non-periodic Tx FIFO size and address */ - nptxfifolen &= ~HNPTFLEN_HNPTXRSAR; - nptxfifolen |= USBFS_RX_FIFO_SIZE; - nptxfifolen &= ~HNPTFLEN_HNPTXFD; - nptxfifolen |= USBFS_HTX_NPFIFO_SIZE << 16; - USB_HNPTFLEN = nptxfifolen; - - /* set periodic Tx FIFO size and address */ - ptxfifolen &= ~HPTFLEN_HPTXFSAR; - ptxfifolen |= USBFS_RX_FIFO_SIZE + USBFS_HTX_PFIFO_SIZE; - ptxfifolen &= ~HPTFLEN_HPTXFD; - ptxfifolen |= USBFS_HTX_PFIFO_SIZE << 16; - USB_HPTFLEN = ptxfifolen; - } - -#ifdef USE_OTG_MODE - - /* clear Host Set HNP Enable bit in the USB OTG Control Register */ - otgctl |= GOTGCS_HHNPEN; - USB_GOTGCS &= ~otgctl; - USB_GOTGCS |= 0; - -#endif /* USE_OTG_MODE */ - - /* make sure the FIFOs are flushed */ - - /* flush all Tx FIFOs in device or host mode */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush the entire Rx FIFO */ - usb_rxfifo_flush(pudev); - - /* clear all pending host channel interrupts */ - USB_HACHINTEN &= ~HACHINTEN_CINTEN; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxINTEN(i) = 0U; - USB_HCHxINTF(i) = 0xFFFFFFFFU; - } - -#ifndef USE_OTG_MODE - usb_vbus_drive(pudev, 1U); -#endif /* USE_OTG_MODE */ - - usb_hostint_enable(pudev); - - return USB_OK; -} - -/*! - \brief control the VBUS to power - \param[in] pudev: pointer to selected usb host - \param[in] state: VBUS state - \param[out] none - \retval none -*/ -void usb_vbus_drive (usb_core_handle_struct *pudev, uint8_t state) -{ - __IO uint32_t host_port = 0U; - - /* enable or disable the external charge pump */ - if ((void *)0 != pudev->host.vbus_drive) { - pudev->host.vbus_drive(pudev, state); - } - - /* turn on the host port power. */ - host_port = USB_PORT_READ(); - - if ((0U == (host_port & HPCS_PP)) && (1U == state)) { - host_port |= HPCS_PP; - } else if ((1U == (host_port & HPCS_PP)) && (0U == state)) { - host_port &= ~HPCS_PP; - } else { - /* no operation */ - } - - USB_HPCS = host_port; - - if (NULL != pudev->mdelay) { - pudev->mdelay(200U); - } -} - -/*! - \brief enables the host mode interrupts - \param[in] pudev: pointer to selected usb host - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostint_enable (usb_core_handle_struct *pudev) -{ - uint32_t gintf = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xFFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - gintf |= GINTF_RXFNEIF; - - /* enable host_mode-related interrupts */ - gintf |= GINTF_HPIF | GINTF_HCIF | GINTF_DISCIF | GINTF_SOF | GINTF_ISOONCIF; - - USB_GINTEN &= ~gintf; - USB_GINTEN |= gintf; - - return USB_OK; -} - -/*! - \brief reset host port - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint32_t usb_port_reset (usb_core_handle_struct *pudev) -{ - USB_HPCS = USB_PORT_READ() | HPCS_PRST; - - if (NULL != pudev->mdelay) { - pudev->mdelay(100U); - } - - USB_HPCS &= ~HPCS_PRST; - - if (NULL != pudev->mdelay) { - pudev->mdelay(20U); - } - - return USB_OK; -} - -/*! - \brief initialize host channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_init(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t is_low_speed = 0U; - __IO uint32_t chinten = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* clear old interrupt conditions for this host channel */ - USB_HCHxINTF((uint16_t)hc_num) = 0xFFFFFFFFU; - - /* enable channel interrupts required for this transfer */ - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE \ - | HCHINTEN_DTERIE | HCHINTEN_NAKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } else { - chinten |= HCHINTEN_NYETIE; - } - break; - - case USB_EPTYPE_INTR: - chinten |= HCHINTEN_TFIE | HCHINTEN_STALLIE | HCHINTEN_USBERIE | HCHINTEN_DTERIE \ - | HCHINTEN_NAKIE | HCHINTEN_REQOVRIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_BBERIE; - } - break; - - case USB_EPTYPE_ISOC: - chinten |= HCHINTEN_TFIE | HCHINTEN_REQOVRIE | HCHINTEN_ACKIE; - - if (puhc->endp_in) { - chinten |= HCHINTEN_USBERIE | HCHINTEN_BBERIE; - } - break; - - default: - break; - } - - USB_HCHxINTEN((uint16_t)hc_num) = chinten; - - /* enable the top level host channel interrupt */ - USB_HACHINTEN |= 1U << hc_num; - - /* make sure host channel interrupts are enabled */ - USB_GINTEN |= GINTEN_HCIE; - - /* program the hcctlr register */ - chctl = 0U; - - if (HPRT_PRTSPD_LOW_SPEED == puhc->dev_speed) { - is_low_speed = 1U; - } - - chctl |= (uint32_t)puhc->dev_addr << 22U; - chctl |= (uint32_t)puhc->endp_type << 18U; - chctl |= (uint32_t)puhc->endp_id << 11U; - chctl |= (uint32_t)puhc->endp_in << 15U; - chctl |= (uint32_t)is_low_speed << 17U; - chctl |= puhc->endp_mps; - - if (HCCHAR_INTR == puhc->endp_type) { - chctl |= HCHCTL_ODDFRM; - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief prepare host channel for transferring packets - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_startxfer(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint16_t dword_len = 0U; - uint16_t packet_num = 0U; - - __IO uint32_t chxlen = 0U; - __IO uint32_t chctl = 0U; - - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - /* compute the expected number of packets associated to the transfer */ - if (puhc->xfer_len > 0U) { - packet_num = ((uint16_t)puhc->xfer_len + puhc->endp_mps - 1U) / puhc->endp_mps; - - if (packet_num > HC_MAX_PACKET_COUNT) { - packet_num = HC_MAX_PACKET_COUNT; - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - } else { - packet_num = 1U; - } - - if (puhc->endp_in) { - puhc->xfer_len = (uint32_t)(packet_num) * (uint32_t)(puhc->endp_mps); - } - - /* initialize the host channel length register */ - chxlen &= ~HCHLEN_TLEN; - chxlen |= puhc->xfer_len; - chxlen &= ~HCHLEN_PCNT; - chxlen |= (uint32_t)packet_num << 19; - chxlen &= ~HCHLEN_DPID; - chxlen |= (uint32_t)(puhc->DPID) << 29; - USB_HCHxLEN((uint16_t)hc_num) = (uint32_t)chxlen; - - /* set host channel enable */ - chctl = USB_HCHxCTL((uint16_t)hc_num); - - if (1 == USB_EVEN_FRAME()) { - chctl |= HCHCTL_ODDFRM; - } else { - chctl &= ~HCHCTL_ODDFRM; - } - - chctl |= HCHCTL_CEN; - chctl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - if ((0U == puhc->endp_in) && (puhc->xfer_len > 0U)) { - dword_len = (uint16_t)(puhc->xfer_len + 3U) / 4U; - - switch (puhc->endp_type) { - /* non-periodic transfer */ - case USB_EPTYPE_CTRL: - case USB_EPTYPE_BULK: - /* check if there is enough space in fifo space */ - if (dword_len > (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - /* need to process data in non-periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_NPTXFEIE; - } - break; - - /* periodic transfer */ - case USB_EPTYPE_INTR: - case USB_EPTYPE_ISOC: - /* check if there is enough space in FIFO space */ - if (dword_len > (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - /* need to process data in periodic transfer fifo empty interrupt */ - USB_GINTEN |= GINTEN_PTXFEIE; - } - break; - - default: - break; - } - - /* write packet into the Tx FIFO. */ - usb_fifo_write(puhc->xfer_buff, hc_num, (uint16_t)puhc->xfer_len); - } - - return USB_OK; -} - -/*! - \brief halt channel - \param[in] pudev: pointer to usb device - \param[in] hc_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -usb_status_enum usb_hostchannel_halt(usb_core_handle_struct *pudev, uint8_t hc_num) -{ - uint8_t endp_type = 0U; - __IO uint32_t chctl = USB_HCHxCTL((uint16_t)hc_num); - - chctl |= HCHCTL_CEN | HCHCTL_CDIS; - - endp_type = (uint8_t)((chctl & HCHCTL_EPTYPE) >> 18U); - - /* check for space in the request queue to issue the halt. */ - if ((HCCHAR_CTRL == endp_type) || (HCCHAR_BULK == endp_type)) { - if (0U == (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } else { - if (0U == (USB_HPTFQSTAT & HPTFQSTAT_PTXFS)) { - chctl &= ~HCHCTL_CEN; - } - } - - USB_HCHxCTL((uint16_t)hc_num) = chctl; - - return USB_OK; -} - -/*! - \brief stop the USB host and clean up fifos - \param[in] none - \param[out] none - \retval none -*/ -void usb_host_stop(usb_core_handle_struct *pudev) -{ - uint32_t i; - - /* disable all host channel interrupt */ - USB_HACHINTEN = 0U; - USB_HACHINT = 0xFFFFFFFFU; - - /* flush out any leftover queued requests */ - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - USB_HCHxCTL(i) |= HCHCTL_CEN | HCHCTL_CDIS | HCHCTL_EPDIR; - } - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} - -#endif /* USE_HOST_MODE */ - - -#ifdef USE_DEVICE_MODE - -/* USB endpoint Tx FIFO size */ -static uint16_t USBFS_TX_FIFO_SIZE[USBFS_MAX_DEV_EPCOUNT] = -{ - (uint16_t)TX0_FIFO_FS_SIZE, - (uint16_t)TX1_FIFO_FS_SIZE, - (uint16_t)TX2_FIFO_FS_SIZE, - (uint16_t)TX3_FIFO_FS_SIZE -}; - -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev); - -/*! - \brief initialize USB core registers for device mode - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -usb_status_enum usb_devcore_init (usb_core_handle_struct *pudev) -{ - uint32_t i, ram_address = 0U; - __IO uint32_t devinep0intf = USB_DIEP0TFLEN; - __IO uint32_t devinepintf = 0U; - - /* restart the Phy Clock (Maybe don't need to...) */ - USB_PWRCLKCTL = 0U; - - /* config periodic frmae interval to default */ - USB_DCFG &= ~DCFG_EOPFT; - USB_DCFG |= FRAME_INTERVAL_80; - - if (USB_FS_CORE_ID == pudev->cfg.core_id) { - /* set full speed PHY */ - USB_DCFG &= ~DCFG_DS; - USB_DCFG |= USB_SPEED_INP_FULL; - - /* set Rx FIFO size */ - USB_GRFLEN &= ~GRFLEN_RXFD; - USB_GRFLEN |= (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 0 Tx FIFO length and RAM address */ - devinep0intf &= ~DIEP0TFLEN_IEP0TXFD; - devinep0intf |= (uint32_t)TX0_FIFO_FS_SIZE << 16; - devinep0intf &= ~DIEP0TFLEN_IEP0TXRSAR; - devinep0intf |= (uint32_t)RX_FIFO_FS_SIZE; - - USB_DIEP0TFLEN = devinep0intf; - - ram_address = (uint32_t)RX_FIFO_FS_SIZE; - - /* set endpoint 1 to 3's Tx FIFO length and RAM address */ - for (i = 1U; i < USBFS_MAX_DEV_EPCOUNT; i++) { - ram_address += USBFS_TX_FIFO_SIZE[i - 1U]; - - devinepintf &= ~DIEPTFLEN_IEPTXFD; - devinepintf |= (uint32_t)USBFS_TX_FIFO_SIZE[i] << 16U; - devinepintf &= ~DIEPTFLEN_IEPTXRSAR; - devinepintf |= ram_address; - - USB_DIEPxTFLEN(i) = devinepintf; - } - } - - /* make sure all FIFOs are flushed */ - - /* flush all Tx FIFOs */ - usb_txfifo_flush(pudev, 0x10U); - - /* flush entire Rx FIFO */ - usb_rxfifo_flush(pudev); - - /* clear all pending device interrupts */ - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - USB_DAEPINTEN = 0U; - - /* configure all IN/OUT endpoints */ - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - if (USB_DIEPxCTL(i) & DEPCTL_EPEN) { - USB_DIEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DIEPxCTL(i) = 0U; - } - - if (USB_DOEPxCTL(i) & DEPCTL_EPEN) { - USB_DOEPxCTL(i) |= DEPCTL_EPD | DEPCTL_SNAK; - } else { - USB_DOEPxCTL(i) = 0U; - } - - /* set IN/OUT endpoint transfer length to 0 */ - USB_DIEPxLEN(i) = 0U; - USB_DOEPxLEN(i) = 0U; - - /* clear all pending IN/OUT endpoints interrupts */ - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - usb_devint_enable(pudev); - - return USB_OK; -} - -/*! - \brief enable the device mode interrupts - \param[in] pudev: pointer to usb device - \param[out] none - \retval status -*/ -static usb_status_enum usb_devint_enable(usb_core_handle_struct *pudev) -{ - uint32_t int_mask = 0U; - - /* disable all interrupts */ - USB_GINTEN = 0U; - - /* clear any pending interrupts */ - USB_GINTF = 0xBFFFFFFFU; - - /* enable the common interrupts */ - usb_commonint_enable(pudev); - - int_mask = GINTEN_RXFNEIE; - - /* enable device_mode-related interrupts */ - int_mask |= GINTEN_SPIE | GINTEN_RSTIE | GINTEN_ENUMFIE \ - | GINTEN_IEPIE | GINTEN_OEPIE | GINTEN_SOFIE | GINTEN_ISOONCIE \ - | GINTEN_ISOINCIE; - -#ifdef VBUS_SENSING_ENABLED - int_mask |= GINTEN_SESIE | GINTEN_OTGIE; -#endif /* VBUS_SENSING_ENABLED */ - - USB_GINTEN &= ~int_mask; - USB_GINTEN |= int_mask; - - return USB_OK; -} - -/*! - \brief configures endpoint 0 to receive SETUP packets - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_ep0_startout(usb_core_handle_struct *pudev) -{ - __IO uint32_t ep0len = 0U; - - /* set OUT endpoint 0 receive length to 24 bytes */ - ep0len &= ~DOEP0LEN_TLEN; - ep0len |= 8U * 3U; - - /* set OUT endpoint 0 receive length to 1 packet */ - ep0len &= ~DOEP0LEN_PCNT; - ep0len |= 1U << 19; - - /* set SETUP packet count to 3 */ - ep0len &= ~DOEP0LEN_STPCNT; - ep0len |= 3U << 29; - - USB_DOEPxLEN(0U) = ep0len; -} - -/*! - \brief active remote wakeup signalling - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_remotewakeup_active(usb_core_handle_struct *pudev) -{ - __IO uint32_t power_clock; - - if (pudev->dev.remote_wakeup) { - if (1U == (USB_DSTAT & DSTAT_SPST)) { - if (pudev->cfg.low_power) { - /* ungate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - - /* active remote wakeup signaling */ - USB_DCTL |= DCTL_RWKUP; - - if (pudev->mdelay != (void *)0) { - pudev->mdelay(5U); - } - - USB_DCTL &= ~DCTL_RWKUP; - } - } -} - -/*! - \brief active USB core clock - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_clock_ungate(usb_core_handle_struct *pudev) -{ - if (pudev->cfg.low_power) { - __IO uint32_t power_clock; - - if (1U == (USB_DSTAT & DSTAT_SPST)) { - /* un-gate USB core clock */ - power_clock = USB_PWRCLKCTL; - power_clock &= ~PWRCLKCTL_SHCLK; - power_clock &= ~PWRCLKCTL_SUCLK; - - USB_PWRCLKCTL = power_clock; - } - } -} - -/*! - \brief stop the device and clean up fifos - \param[in] pudev: pointer to usb device - \param[out] none - \retval none -*/ -void usb_device_stop (usb_core_handle_struct *pudev) -{ - uint32_t i; - - pudev->dev.status = 1U; - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF(i) = 0xFFU; - USB_DOEPxINTF(i) = 0xFFU; - } - - USB_DIEPINTEN = 0U; - USB_DOEPINTEN = 0U; - USB_DAEPINTEN = 0U; - USB_DAEPINT = 0xFFFFFFFFU; - - /* flush the FIFO */ - usb_rxfifo_flush(pudev); - usb_txfifo_flush(pudev, 0x10U); -} -#endif /* USE_DEVICE_MODE */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_core.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_core.c deleted file mode 100644 index 0bf5841e15..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_core.c +++ /dev/null @@ -1,500 +0,0 @@ -/*! - \file usbd_core.c - \brief USB device mode core driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_core.h" -#include "usbd_std.h" - -/*! - \brief initailizes the USB device-mode handler stack - \param[in] pudev: pointer to usb device instance - \param[in] core_id: USB core ID - \param[out] none - \retval none -*/ -void usbd_init (usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - /* select USB core */ - usb_core_select (pudev, core_id); - - pudev->dev.status = USB_STATUS_DEFAULT; - - /* disable USB global interrupt */ - USB_GLOBAL_INT_DISABLE(); - - /* init the core (common init.) */ - usb_core_init(pudev); - - /* force device mode*/ - usb_mode_set(pudev, DEVICE_MODE); - - /* set device disconnect */ - USB_SOFT_DISCONNECT_ENABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* init device */ - usb_devcore_init(pudev); - - /* set device Connect */ - USB_SOFT_DISCONNECT_DISABLE(); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(3U); - } - - /* enable USB global interrupt */ - USB_GLOBAL_INT_ENABLE(); -} - -/*! - \brief endpoint initialization - \param[in] pudev: pointer to usb device instance - \param[in] ep_desc: pointer to usb endpoint descriptor - \param[out] none - \retval none -*/ -void usbd_ep_init (usb_core_handle_struct *pudev, const usb_descriptor_endpoint_struct *ep_desc) -{ - usb_ep_struct *ep; - usb_dir_enum ep_dir; - - uint32_t devepinten = 0U; - uint32_t devepctl = 0U; - - uint8_t ep_num = ep_desc->bEndpointAddress & 0x7FU; - uint8_t ep_type = ep_desc->bmAttributes & USB_EPTYPE_MASK; - uint16_t ep_mps = ep_desc->wMaxPacketSize; - - if (ep_desc->bEndpointAddress >> 7) { - ep = &pudev->dev.in_ep[ep_num]; - - devepinten |= 1U << ep_num; - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - ep_dir = USB_TX; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepinten |= (1U << ep_num) << 16; - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - ep_dir = USB_RX; - } - - /* if the endpoint is not active, need change the endpoint control register */ - if (!(devepctl & DEPCTL_EPACT)) { - devepctl &= ~DEPCTL_MPL; - devepctl |= ep_mps; - - devepctl &= ~DEPCTL_EPTYPE; - devepctl |= (uint32_t)ep_type << 18; - - if (USB_TX == ep_dir) { - devepctl &= ~DIEPCTL_TXFNUM; - devepctl |= (uint32_t)ep_num << 22; - } - - devepctl |= DEPCTL_SD0PID; - devepctl |= DEPCTL_EPACT; - } - - if (USB_TX == ep_dir) { - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else if (USB_RX == ep_dir) { - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* no operation */ - } - - ep->endp_mps = ep_mps; - ep->endp_type = ep_type; - - /* enable the interrupts for this endpoint */ - USB_DAEPINTEN |= devepinten; -} - -/*! - \brief endpoint deinitialize - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_deinit (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint32_t devepinten = 0U; - uint8_t ep_num = ep_addr & 0x7FU; - - if (ep_addr >> 7) { - devepinten |= 1U << ep_num; - - USB_DIEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } else { - devepinten |= (1U << ep_num) << 16U; - - USB_DOEPxCTL((uint16_t)ep_num) &= ~DEPCTL_EPACT; - } - - /* disable the interrupts for this endpoint */ - USB_DAEPINTEN &= ~devepinten; -} - -/*! - \brief endpoint prepare to receive data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] buf_len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_rx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - uint32_t devepctl = 0U, devepxlen = 0U; - - ep = &pudev->dev.out_ep[ep_num]; - - /* setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - devepxlen = USB_DOEPxLEN((uint16_t)ep_num); - - devepxlen &= ~DEPLEN_TLEN; - devepxlen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - - if (0U == ep_num) { - /* set the transfer length to max packet size */ - devepxlen |= ep->endp_mps; - - /* set the transfer packet count to 1 */ - devepxlen |= 1U << 19U; - } else { - /* configure the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - devepxlen |= ((ep->xfer_len + ep->endp_mps - 1U) / ep->endp_mps) << 19U; - devepxlen |= ((devepxlen & DEPLEN_PCNT) >> 19U) * ep->endp_mps; - } - } - - USB_DOEPxLEN((uint16_t)ep_num) = devepxlen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (ep->endp_frame) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; -} - -/*! - \brief endpoint prepare to transmit data - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval none -*/ -void usbd_ep_tx (usb_core_handle_struct *pudev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - __IO uint32_t deveplen = 0U; - - ep = &pudev->dev.in_ep[ep_num]; - - /* setup and start the transfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0U; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - deveplen = USB_DIEPxLEN((uint16_t)ep_num); - - /* clear transfer length to 0 */ - deveplen &= ~DEPLEN_TLEN; - - /* clear transfer packet to 0 */ - deveplen &= ~DEPLEN_PCNT; - - /* zero length packet */ - if (0U == ep->xfer_len) { - /* set transfer packet count to 1 */ - deveplen |= 1U << 19U; - } else { - if (0U == ep_num) { - if (ep->xfer_len > ep->endp_mps) { - ep->xfer_len = ep->endp_mps; - } - - deveplen |= 1U << 19U; - } else { - deveplen |= ((ep->xfer_len - 1U + ep->endp_mps) / ep->endp_mps) << 19U; - } - - /* configure the transfer size and packet count as follows: - * xfersize = N * maxpacket + short_packet - * pktcnt = N + (short_packet exist ? 1 : 0) - */ - deveplen |= ep->xfer_len; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - deveplen |= DIEPLEN_MCNT & (1U << 29U); - } - } - - USB_DIEPxLEN((uint16_t)ep_num) = deveplen; - - if (USB_EPTYPE_ISOC == ep->endp_type) { - if (0U == (((USB_DSTAT & DSTAT_FNRSOF) >> 8U) & 0x1U)) { - devepctl |= DEPCTL_SODDFRM; - } else { - devepctl |= DEPCTL_SEVNFRM; - } - } - - /* enable the endpoint and clear the NAK */ - devepctl |= DEPCTL_EPEN | DEPCTL_CNAK; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - - if (USB_EPTYPE_ISOC != ep->endp_type) { - /* enable the Tx FIFO empty interrupt for this endpoint */ - if (ep->xfer_len > 0U) { - USB_DIEPFEINTEN |= 1U << ep_num; - } - } else { - usb_fifo_write(ep->xfer_buff, ep_num, (uint16_t)ep->xfer_len); - } -} - -/*! - \brief transmit data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctltx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - usbd_status_enum ret = USBD_OK; - - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_IN; - - usbd_ep_tx (pudev, 0U, pbuf, (uint32_t)len); - - return ret; -} - -/*! - \brief receive data on the control channel - \param[in] pudev: pointer to usb device instance - \param[in] pbuf: pointer to buffer - \param[in] len: buffer length - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlrx (usb_core_handle_struct *pudev, uint8_t *pbuf, uint16_t len) -{ - pudev->dev.sum_len = len; - pudev->dev.remain_len = len; - pudev->dev.ctl_status = USB_CTRL_DATA_OUT; - - usbd_ep_rx (pudev, 0U, pbuf, len); - - return USBD_OK; -} - -/*! - \brief transmit status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_tx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_IN; - - usbd_ep_tx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief receive status on the control channel - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval usb device operation status -*/ -usbd_status_enum usbd_ctlstatus_rx (usb_core_handle_struct *pudev) -{ - pudev->dev.ctl_status = USB_CTRL_STATUS_OUT; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - - usb_ep0_startout(pudev); - - return USBD_OK; -} - -/*! - \brief set an endpoint to STALL status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if (ep_addr >> 7U) { - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* set the endpoint disable bit */ - if (devepctl & DEPCTL_EPEN) { - devepctl |= DEPCTL_EPD; - } - - /* set the endpoint stall bit */ - devepctl |= DEPCTL_STALL; - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - /* set the endpoint stall bit */ - USB_DOEPxCTL((uint16_t)ep_num) |= DEPCTL_STALL; - } -} - -/*! - \brief clear endpoint stalled status - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_clear_stall (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - usb_ep_struct *ep; - uint8_t ep_num = ep_addr & 0x7FU; - __IO uint32_t devepctl = 0U; - - if(ep_addr >> 7){ - ep = &pudev->dev.in_ep[ep_num]; - - devepctl = USB_DIEPxCTL((uint16_t)ep_num); - - /* clear the IN endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DIEPxCTL((uint16_t)ep_num) = devepctl; - } else { - ep = &pudev->dev.out_ep[ep_num]; - - devepctl = USB_DOEPxCTL((uint16_t)ep_num); - - /* clear the OUT endpoint stall bits */ - devepctl &= ~DEPCTL_STALL; - - if ((USB_EPTYPE_INTR == ep->endp_type) || (USB_EPTYPE_BULK == ep->endp_type)) { - devepctl |= DEPCTL_SEVNFRM; - } - - USB_DOEPxCTL((uint16_t)ep_num) = devepctl; - } -} - -/*! - \brief flushes the FIFOs - \param[in] pudev: pointer to usb device instance - \param[in] ep_addr: endpoint address - \param[out] none - \retval none -*/ -void usbd_ep_fifo_flush (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - if (ep_addr >> 7) { - usb_txfifo_flush(pudev, ep_addr & 0x7FU); - } else { - usb_rxfifo_flush(pudev); - } -} - -/*! - \brief get the received data length - \param[in] pudev: pointer to usb device instance - \param[in] ep_num: endpoint identifier which is in (0..3) - \param[out] none - \retval received data length -*/ -uint16_t usbd_rxcount_get (usb_core_handle_struct *pudev, uint8_t ep_num) -{ - return (uint16_t)pudev->dev.out_ep[ep_num].xfer_count; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_int.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_int.c deleted file mode 100644 index 970cf812ad..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_int.c +++ /dev/null @@ -1,662 +0,0 @@ -/*! - \file usbd_int.c - \brief USB device mode interrupt routines - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_int.h" -#include "usbd_std.h" - -/* interrupt handlers */ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_inep (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_suspend (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_reset (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_enumfinish (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isoinincomplete (usb_core_handle_struct *pudev); -static uint32_t usbd_intf_isooutincomplete (usb_core_handle_struct *pudev); - -static uint32_t usbd_emptytxfifo_write (usb_core_handle_struct *pudev, uint8_t ep_num); - -#ifdef VBUS_SENSING_ENABLED - - static uint32_t usbd_intf_otg (usb_core_handle_struct *pudev); - static uint32_t usbd_intf_sessionrequest (usb_core_handle_struct *pudev); - -#endif /* VBUS_SENSING_ENABLED */ - -static usb_speed_enum USB_SPEED[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_HIGH, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = USB_SPEED_FULL, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = USB_SPEED_LOW -}; - -static const uint8_t EP0_MAXLEN[4] = { - [DSTAT_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_FS_PHY_48MHZ] = EP0MPL_64, - [DSTAT_ENUMSPD_LS_PHY_6MHZ] = EP0MPL_8 -}; - -/*! - \brief USB device-mode interrupts global service routine handler - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbd_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_status = 0U, gintf = USB_GINTF, ginten = USB_GINTEN; - - /* ensure the core is in device mode */ - if (DEVICE_MODE == USB_CURRENT_MODE_GET()) { - int_status = gintf & ginten; - - /* there are no interrupts, avoid spurious interrupt */ - if (!int_status) { - return 0U; - } - - /* OUT endpoints interrupts */ - if (int_status & GINTF_OEPIF) { - retval |= usbd_intf_outep(pudev); - } - - /* IN endpoints interrupts */ - if (int_status & GINTF_IEPIF) { - retval |= usbd_intf_inep(pudev); - } - - /* mode mismatch interrupt */ - if (int_status & GINTF_MFIF) { - /* clear interrupt */ - USB_GINTF = GINTF_MFIF; - } - - /* early suspend interrupt */ - if (int_status & GINTF_ESP) { - retval |= usbd_intf_earlysuspend(pudev); - } - - /* suspend interrupt */ - if (int_status & GINTF_SP) { - retval |= usbd_intf_suspend(pudev); - } - - /* wakeup interrupt */ - if (int_status & GINTF_WKUPIF) { - retval |= usbd_intf_resume(pudev); - } - - /* start of frame interrupt */ - if (int_status & GINTF_SOF) { - retval |= usbd_intf_sof(pudev); - } - - /* reveive fifo not empty interrupt */ - if (int_status & GINTF_RXFNEIF) { - retval |= usbd_intf_rxfifo(pudev); - } - - /* USB reset interrupt */ - if (int_status & GINTF_RST) { - retval |= usbd_intf_reset(pudev); - } - - /* enumeration has been finished interrupt */ - if (int_status & GINTF_ENUMF) { - retval |= usbd_intf_enumfinish(pudev); - } - - /* incomplete synchronization in transfer interrupt*/ - if (int_status & GINTF_ISOINCIF) { - retval |= usbd_intf_isoinincomplete(pudev); - } - - /* incomplete synchronization out transfer interrupt*/ - if (int_status & GINTF_ISOONCIF) { - retval |= usbd_intf_isooutincomplete(pudev); - } - -#ifdef VBUS_SENSING_ENABLED - - /* session request interrupt */ - if (int_status & GINTF_SESIF) { - retval |= usbd_intf_sessionrequest(pudev); - } - - /* OTG mode interrupt */ - if (int_status & GINTF_OTGIF) { - retval |= usbd_intf_otg(pudev); - } -#endif /* VBUS_SENSING_ENABLED */ - } - - return retval; -} - -/*! - \brief indicates that an OUT endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_outep (usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t out_endp_intr = 0U; - - /* read in the device interrupt bits */ - USB_DAOEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DOEP_INTR_READ(out_endp_intr, (uint16_t)endp_num); - - /* transfer complete interrupt */ - if (out_endp_intr & DOEPINTF_TF) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_TF; - - /* data receive is completed */ - usbd_out_transaction(pudev, endp_num); - } - - /* endpoint disable interrupt */ - if (out_endp_intr & DOEPINTF_EPDIS) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_EPDIS; - } - - /* setup phase finished interrupt (just for control endpoints) */ - if (out_endp_intr & DOEPINTF_STPF) { - /* setup phase is completed */ - usbd_setup_transaction(pudev); - - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_STPF; - } - - /* back to back setup packets received */ - if (out_endp_intr & DOEPINTF_BTBSTP) { - USB_DOEPxINTF((uint16_t)endp_num) = DOEPINTF_BTBSTP; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that an IN endpoint has a pending interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_inep(usb_core_handle_struct *pudev) -{ - uint8_t endp_num = 0U; - uint32_t endp_intr = 0U; - - __IO uint32_t in_endp_intr = 0U; - - /* get all in endpoints which have interrupts */ - USB_DAIEP_INTR_READ(endp_intr); - - while (endp_intr) { - if (endp_intr & 0x1U) { - USB_DIEP_INTR_READ(in_endp_intr, (uint16_t)endp_num); - - if (in_endp_intr & DIEPINTF_TF) { - /* disable the fifo empty interrupt for the endpoint */ - USB_DIEPFEINTEN &= ~(0x1U << endp_num); - - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TF; - - /* data transmittion is completed */ - usbd_in_transaction(pudev, endp_num); - } - - if (in_endp_intr & DIEPINTF_CITO) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_CITO; - } - - if (in_endp_intr & DIEPINTF_IEPNE) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_IEPNE; - } - - if (in_endp_intr & DIEPINTF_EPDIS) { - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_EPDIS; - } - - if (in_endp_intr & DIEPINTF_TXFE) { - usbd_emptytxfifo_write(pudev, endp_num); - USB_DIEPxINTF((uint16_t)endp_num) = DIEPINTF_TXFE; - } - } - - endp_num ++; - endp_intr >>= 1; - } - - return 1U; -} - -/*! - \brief indicates that early SUSPEND state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_earlysuspend (usb_core_handle_struct *pudev) -{ - USB_GINTEN &= ~GINTEN_ESPIE; - USB_GINTF = GINTF_ESP; - - return 1U; -} - -/*! - \brief indicates that SUSPEND state has been detected on the USB - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_suspend(usb_core_handle_struct *pudev) -{ - __IO uint8_t low_power = pudev->cfg.low_power; - __IO uint8_t suspend = (uint8_t)(USB_DSTAT & DSTAT_SPST); - __IO uint8_t is_configured = (pudev->dev.status == USB_STATUS_CONFIGURED)? 1U : 0U; - - pudev->dev.prev_status = pudev->dev.status; - pudev->dev.status = USB_STATUS_SUSPENDED; - - if (low_power && suspend && is_configured) { - /* switch-off the otg clocks */ - USB_PWRCLKCTL |= PWRCLKCTL_SUCLK | PWRCLKCTL_SHCLK; - - /* enter DEEP_SLEEP mode with LDO in low power mode */ - pmu_to_deepsleepmode(PMU_LDO_LOWPOWER, WFI_CMD); - } - - /* clear interrupt */ - USB_GINTF = GINTF_SP; - - return 1U; -} - -/*! - \brief indicates that the USB controller has detected a resume or remote Wake-up sequence - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_resume (usb_core_handle_struct *pudev) -{ - pudev->dev.status = pudev->dev.prev_status; - pudev->dev.status = USB_STATUS_CONFIGURED; - - /* clear interrupt */ - USB_GINTF = GINTF_WKUPIF; - - return 1U; -} - -/*! - \brief handle the SOF interrupts - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_sof(usb_core_handle_struct *pudev) -{ - if (NULL != usbd_int_fops) { - usbd_int_fops->SOF(pudev); - } - - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle the Rx status queue level interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbd_intf_rxfifo (usb_core_handle_struct *pudev) -{ - usb_ep_struct *ep; - uint8_t data_pid = 0U, endp_num = 0U; - uint32_t bcount = 0U, packet_num = 0U; - - /* get the status from the top of the fifo (must be read to a variable) */ - __IO uint32_t rx_status = USB_GRSTATP; - - /* disable the rx fifo non-empty interrupt */ - USB_GINTEN &= ~GINTEN_RXFNEIE; - - endp_num = (uint8_t)(rx_status & GRSTATRP_EPNUM); - bcount = (rx_status & GRSTATRP_BCOUNT) >> 4U; - data_pid = (uint8_t)((rx_status & GRSTATRP_DPID) >> 15U); - - /* ensure no-DMA mode can work */ - packet_num = USB_DOEPxLEN((uint16_t)endp_num) & DEPLEN_PCNT; - if ((1U == endp_num) && (0U == packet_num)) { - uint32_t devepctl = USB_DOEPxCTL((uint16_t)endp_num); - - devepctl |= DEPCTL_SNAK; - devepctl &= ~DEPCTL_EPEN; - devepctl &= ~DEPCTL_EPD; - - USB_DOEPxCTL((uint16_t)endp_num) = devepctl; - } - - ep = &pudev->dev.out_ep[endp_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17U) { - case RXSTAT_GOUT_NAK: - break; - case RXSTAT_DATA_UPDT: - if (bcount > 0U) { - usb_fifo_read(ep->xfer_buff, (uint16_t)bcount); - ep->xfer_buff += bcount; - ep->xfer_count += bcount; - } - break; - case RXSTAT_XFER_COMP: - break; - case RXSTAT_SETUP_COMP: - break; - case RXSTAT_SETUP_UPDT: - if ((0U == endp_num) && (8U == bcount) && (DPID_DATA0 == data_pid)) { - /* copy the setup packet received in fifo into the setup buffer in ram */ - usb_fifo_read(pudev->dev.setup_packet, 8U); - - ep->xfer_count += bcount; - } - break; - default: - break; - } - - /* enable the Rx fifo non-empty interrupt */ - USB_GINTEN |= GINTEN_RXFNEIE; - - return 1U; -} - -/*! - \brief handle USB reset interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_reset(usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - usb_ep_struct *ep; - - /* clear the remote wakeup signaling */ - USB_DCTL &= ~DCTL_RWKUP; - - /* flush the tx fifo */ - usb_txfifo_flush(pudev, 0U); - - for (i = 0U; i < pudev->cfg.dev_endp_num; i++) { - USB_DIEPxINTF((uint16_t)i) = 0xFFU; - USB_DOEPxINTF((uint16_t)i) = 0xFFU; - } - - /* clear all pending device endpoint interrupts */ - USB_DAEPINT = 0xFFFFFFFFU; - - /* enable endpoint 0 interrupts */ - USB_DAEPINTEN &= ~DAEPINTEN_OEPIE; - USB_DAEPINTEN &= ~DAEPINTEN_IEPIE; - USB_DAEPINTEN = (1U << 16) | 1U; - - /* enable out endpoint interrupts */ - USB_DOEPINTEN = DOEPINTEN_STPFEN | DOEPINTEN_TFEN | DOEPINTEN_EPDISEN; - - /* enable in endpoint interrupts */ - USB_DIEPINTEN = DIEPINTEN_TFEN | DIEPINTEN_CITOEN | DIEPINTEN_EPDISEN; - - /* reset device address */ - USB_DCFG &= ~DCFG_DAR; - USB_DCFG |= 0U << 4U; - - /* configure endpoint 0 to receive setup packets */ - usb_ep0_startout(pudev); - - /* clear usb reset interrupt */ - USB_GINTF = GINTF_RST; - - /* open EP0 IN */ - ep = &pudev->dev.in_ep[0]; - - USB_DIEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DIEPxCTL(0U) &= ~DEPCTL_EPTYPE; - USB_DIEPxCTL(0U) &= ~DIEPCTL_TXFNUM; - - if (!(USB_DIEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DIEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DIEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DIEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - /* open EP0 OUT */ - ep = &pudev->dev.out_ep[0]; - - USB_DOEPxCTL(0U) &= ~DEP0CTL_MPL; - USB_DOEPxCTL(0U) &= ~DEPCTL_EPTYPE; - - if (!(USB_DOEPxCTL(0U) & DEP0CTL_EPACT)) { - USB_DOEPxCTL(0U) |= USB_MAX_EP0_SIZE; - USB_DOEPxCTL(0U) |= (USB_EPTYPE_CTRL << 18U); - USB_DOEPxCTL(0U) |= DEP0CTL_EPACT; - } - - ep->endp_mps = USB_MAX_EP0_SIZE; - ep->endp_type = USB_EPTYPE_CTRL; - - pudev->dev.status = USB_STATUS_DEFAULT; - - return 1U; -} - -/*! - \brief handle enumeration finish interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_enumfinish(usb_core_handle_struct *pudev) -{ - uint8_t enum_speed = (uint8_t)((USB_DSTAT & DSTAT_ES) >> 1U); - - /* set the max packet size of devie in endpoint based on the enumeration speed */ - USB_DIEPxCTL(0U) |= EP0_MAXLEN[enum_speed]; - - /* clear global IN NAK */ - USB_DCTL &= ~DCTL_CGINAK; - USB_DCTL |= DCTL_CGINAK; - - /* set USB turn-around time based on device speed and PHY interface */ - if (USB_SPEED_HIGH == USB_SPEED[enum_speed]) { - pudev->cfg.core_speed = USB_CORE_SPEED_HIGH; - pudev->cfg.max_packet_size = USBHS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x09U << 10; - } else { - pudev->cfg.core_speed = USB_CORE_SPEED_FULL; - pudev->cfg.max_packet_size = USBFS_MAX_PACKET_SIZE; - - USB_GUSBCS &= ~GUSBCS_UTT; - USB_GUSBCS |= 0x05U << 10; - } - - /* clear interrupt */ - USB_GINTF = GINTF_ENUMF; - - return 1U; -} - -/*! - \brief handle the ISO IN incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isoinincomplete(usb_core_handle_struct *pudev) -{ -// USBD_DCD_INT_fops->IsoINIncomplete (pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_ISOINCIF; - - return 1U; -} - -/*! - \brief handle the ISO OUT incomplete interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_isooutincomplete(usb_core_handle_struct *pudev) -{ -// USBD_DCD_INT_fops->IsoOUTIncomplete (pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_ISOONCIF; - - return 1U; -} - -/*! - \brief check FIFO for the next packet to be loaded - \param[in] pudev: pointer to usb device instance - \param[in] ep_id: endpoint identifier which is in (0..3) - \param[out] none - \retval status -*/ -static uint32_t usbd_emptytxfifo_write(usb_core_handle_struct *pudev, uint8_t ep_num) -{ - uint32_t len = 0U, word_len = 0U, fifo_empty_mask = 0U; - usb_ep_struct *ep; - - ep = &pudev->dev.in_ep[ep_num]; - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - while (((USB_DIEPxTFSTAT((uint16_t)ep_num) & DIEPTFSTAT_IEPTFS) > word_len) && - (ep->xfer_count < ep->xfer_len)) { - /* write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->endp_mps) { - len = ep->endp_mps; - } - - word_len = (len + 3U) / 4U; - - usb_fifo_write (ep->xfer_buff, ep_num, (uint16_t)len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - if(ep->xfer_len == ep->xfer_count) { - fifo_empty_mask = 0x1U << ep_num; - USB_DIEPFEINTEN &= ~fifo_empty_mask; - } - } - - return 1U; -} - -#ifdef VBUS_SENSING_ENABLED - -/*! - \brief indicates that the USB_OTG controller has detected a connection - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_sessionrequest(usb_core_handle_struct *pudev) -{ - pudev->dev.connection_status = 1U; - - /* clear the interrupt bit */ - USB_GINTF = GINTF_SESIF; - - return 1; -} - -/*! - \brief indicates that the USB_OTG controller has detected an OTG event - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval status -*/ -static uint32_t usbd_intf_otg(usb_core_handle_struct *pudev) -{ - if (USB_GOTGINTF & GOTGINTF_SESEND) { - pudev->dev.class_deinit(pudev, 0); - pudev->dev.connection_status = 0; - } - - /* clear OTG interrupt */ - USB_GOTGINTF |= GOTGINTF_SESEND; - - return 1; -} - -#endif /* VBUS_SENSING_ENABLED */ diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_std.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_std.c deleted file mode 100644 index 9bdba6a2c0..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbd_std.c +++ /dev/null @@ -1,718 +0,0 @@ -/*! - \file usbd_std.c - \brief USB 2.0 standard handler driver - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbd_std.h" -#include "usb_core.h" - -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req); -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req); - -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen); - -static void (*StandardDeviceRequest[])(usb_core_handle_struct *pudev, usb_device_req_struct *req) = -{ - usbd_getstatus, - usbd_clrfeature, - usbd_reserved, - usbd_setfeature, - usbd_reserved, - usbd_setaddress, - usbd_getdescriptor, - usbd_setdescriptor, - usbd_getconfig, - usbd_setconfig, - usbd_getinterface, - usbd_setinterface, - usbd_synchframe, -}; - -/* get standard descriptor handler */ -static uint8_t* (*standard_descriptor_get[])(usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) = -{ - usbd_device_descriptor_get, - usbd_configuration_descriptor_get, - usbd_string_descriptor_get -}; - -/*! - \brief USB setup stage processing - \param[in] pudev: pointer to USB device instance - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_setup_transaction(usb_core_handle_struct *pudev) -{ - usb_device_req_struct req; - - usbd_setup_request_parse(pudev, &req); - - switch (req.bmRequestType & USB_REQ_MASK) { - /* standard device request */ - case USB_STANDARD_REQ: - usbd_standard_request(pudev, &req); - break; - /* device class request */ - case USB_CLASS_REQ: - usbd_device_class_request(pudev, &req); - break; - /* vendor defined request */ - case USB_VENDOR_REQ: - usbd_vendor_request(pudev, &req); - break; - default: - usbd_ep_stall(pudev, req.bmRequestType & 0x80U); - break; - } - - return USBD_OK; -} - -/*! - \brief data out stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_out_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.out_ep[0]; - - if (USB_CTRL_DATA_OUT == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_rx (pudev, - 0U, - ep->xfer_buff, - (uint16_t)USB_MIN(pudev->dev.remain_len, ep->endp_mps)); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, 0U); - } - - usbd_ctlstatus_tx(pudev); - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_RX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief data in stage processing - \param[in] pudev: pointer to USB device instance - \param[in] ep_id: endpoint identifier(0..7) - \param[out] none - \retval USB device operation status -*/ -usbd_status_enum usbd_in_transaction (usb_core_handle_struct *pudev, uint8_t endp_num) -{ - usb_ep_struct *ep; - - if (0U == endp_num) { - ep = &pudev->dev.in_ep[0]; - - if (USB_CTRL_DATA_IN == pudev->dev.ctl_status) { - if (pudev->dev.remain_len > ep->endp_mps) { - pudev->dev.remain_len -= ep->endp_mps; - - usbd_ep_tx (pudev, 0U, ep->xfer_buff, pudev->dev.remain_len); - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - /* last packet is MPS multiple, so send ZLP packet */ - if ((pudev->dev.sum_len % ep->endp_mps == 0U) && - (pudev->dev.sum_len >= ep->endp_mps) && - (pudev->dev.sum_len < pudev->dev.ctl_len)) { - usbd_ep_tx (pudev, 0U, NULL, 0U); - pudev->dev.ctl_len = 0U; - - usbd_ep_rx (pudev, 0U, NULL, 0U); - } else { - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, 0U); - } - - usbd_ctlstatus_rx(pudev); - } - } - } - } else if (USB_STATUS_CONFIGURED == pudev->dev.status) { - pudev->dev.class_data_handler(pudev, USB_TX, endp_num); - } else { - /* no operation */ - } - - return USBD_OK; -} - -/*! - \brief handle USB standard device request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_standard_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* call device request handle function */ - (*StandardDeviceRequest[req->bRequest])(pudev, req); - - return USBD_OK; -} - -/*! - \brief handle USB device class request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device class request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_device_class_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_status_enum ret = USBD_OK; - - switch (pudev->dev.status) { - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - ret = (usbd_status_enum)(pudev->dev.class_req_handler(pudev, req)); - - if ((0U == req->wLength) && (USBD_OK == ret)) { - /* no data stage */ - usbd_ctlstatus_tx(pudev); - } - } else { - usbd_enum_error(pudev, req); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - - return ret; -} - -/*! - \brief handle USB vendor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB vendor request - \param[out] none - \retval USB device operation status -*/ -static usbd_status_enum usbd_vendor_request (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* added by user... */ - - return USBD_OK; -} - -/*! - \brief no operation, just for reserved - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_reserved (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no operation... */ -} - -/*! - \brief get the device descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_device_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.dev_desc[0]; - - return pudev->dev.dev_desc; -} - -/*! - \brief get the configuration descriptor - \brief[in] index: no use - \param[in] none - \param[out] pLen: data length pointer - \retval descriptor buffer pointer -*/ -static uint8_t* usbd_configuration_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - *pLen = pudev->dev.config_desc[2]; - - return pudev->dev.config_desc; -} - -/*! - \brief get string descriptor - \param[in] index: string descriptor index - \param[in] pLen: pointer to string length - \param[out] none - \retval none -*/ -static uint8_t* usbd_string_descriptor_get (usb_core_handle_struct *pudev, uint8_t index, uint16_t *pLen) -{ - uint8_t *desc = pudev->dev.strings[index]; - - *pLen = desc[0]; - - return desc; -} - -/*! - \brief handle Get_Status request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getstatus (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ -} - -/*! - \brief handle USB Clear_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: USB device request - \param[out] none - \retval none -*/ -static void usbd_clrfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - - switch (req->bmRequestType & USB_REQTYPE_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 0U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } - break; - - default: - usbd_enum_error(pudev, req); - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - ep_addr = LOWBYTE(req->wIndex); - - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_clear_stall(pudev, ep_addr); - - pudev->dev.class_req_handler(pudev, req); - } - } - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Feature request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setfeature (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t ep_addr = 0U; - __IO uint32_t DctlrStatus; - - switch (req->bmRequestType & USB_REQ_MASK) { - case USB_REQTYPE_DEVICE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_REMOTE_WAKEUP == req->wValue) { - pudev->dev.remote_wakeup = 1U; - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - } else if ((req->wValue == USB_FEATURE_TEST_MODE) && - (0U == (req->wIndex & 0xFFU))) { - DctlrStatus = USB_DCTL; - - usbd_ctlstatus_tx(pudev); - } else { - /* no operation */ - } - break; - default: - break; - } - break; - case USB_REQTYPE_INTERFACE: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_enum_error(pudev, req); - break; - case USB_STATUS_CONFIGURED: - if (LOWBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) { - /* no operation */ - } else { - usbd_enum_error(pudev, req); - } - break; - default: - break; - } - break; - case USB_REQTYPE_ENDPOINT: - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - break; - case USB_STATUS_CONFIGURED: - if (USB_FEATURE_ENDP_HALT == req->wValue) { - if (IS_NOT_EP0(ep_addr)) { - usbd_ep_stall(pudev, ep_addr); - } - } - pudev->dev.class_req_handler(pudev, req); - - usbd_ctlstatus_tx(pudev); - break; - default: - break; - } - break; - default: - usbd_enum_error(pudev, req); - break; - } -} - -/*! - \brief handle USB Set_Address request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setaddress (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t DevAddr; - - if ((0U == req->wIndex) && (0U == req->wLength)) { - DevAddr = (uint8_t)(req->wValue) & 0x7FU; - - if (USB_STATUS_CONFIGURED == pudev->dev.status) { - usbd_enum_error(pudev, req); - } else { - USB_SET_DEVADDR((uint32_t)DevAddr); - - usbd_ctlstatus_tx(pudev); - - if (0U != DevAddr) { - pudev->dev.status = USB_STATUS_ADDRESSED; - } else { - pudev->dev.status = USB_STATUS_DEFAULT; - } - } - } else { - usbd_enum_error(pudev, req); - } -} - -/*! - \brief handle USB Get_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - if (USB_REQTYPE_DEVICE == (req->bmRequestType & USB_REQTYPE_MASK)) { - uint8_t desc_type = (uint8_t)(req->wValue >> 8); - uint8_t desc_index = (uint8_t)(req->wValue) & 0xFFU; - - if ((desc_type <= 0x03U) && (desc_index <= 0x05U)) { - uint16_t len; - uint8_t *pbuf; - - /* call corresponding descriptor get function */ - pbuf = standard_descriptor_get[desc_type - 1U](pudev, desc_index, &len); - - if ((0U != len) && (0U != req->wLength)) { - len = USB_MIN(len, req->wLength); - - if ((1U == desc_type) && (64U == req->wLength)) { - len = 8U; - } - - usbd_ctltx(pudev, pbuf, len); - } - } else { - usbd_enum_error(pudev, req); - } - } else if (USB_REQTYPE_INTERFACE == (req->bmRequestType & USB_REQTYPE_MASK)) { - pudev->dev.class_req_handler(pudev, req); - } else { - /* no operation */ - } -} - -/*! - \brief handle USB Set_Descriptor request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setdescriptor (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief handle USB Get_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint32_t USBD_default_config = 0U; - - if (1U != req->wLength) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - usbd_ctltx(pudev, (uint8_t *)&USBD_default_config, 1U); - break; - case USB_STATUS_CONFIGURED: - usbd_ctltx(pudev, &pudev->dev.config_num, 1U); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Set_Configuration request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setconfig (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM) { - usbd_enum_error(pudev, req); - } else { - switch (pudev->dev.status) { - case USB_STATUS_ADDRESSED: - if (cfgidx) { - pudev->dev.config_num = cfgidx; - pudev->dev.status = USB_STATUS_CONFIGURED; - pudev->dev.class_init(pudev, cfgidx); - } - - usbd_ctlstatus_tx(pudev); - break; - case USB_STATUS_CONFIGURED: - if (0U == cfgidx) { - pudev->dev.status = USB_STATUS_ADDRESSED; - pudev->dev.config_num = cfgidx; - pudev->dev.class_deinit(pudev, cfgidx); - } else if (cfgidx != pudev->dev.config_num) { - /* clear old configuration */ - pudev->dev.class_deinit(pudev, pudev->dev.config_num); - - /* set new configuration */ - pudev->dev.config_num = cfgidx; - pudev->dev.class_init(pudev, cfgidx); - } else { - /* no operation */ - } - - usbd_ctlstatus_tx(pudev); - break; - default: - usbd_enum_error(pudev, req); - break; - } - } -} - -/*! - \brief handle USB Get_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_getinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB Set_Interface request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setinterface (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - pudev->dev.class_req_handler(pudev, req); -} - -/*! - \brief handle USB SynchFrame request - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_synchframe (usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - /* no handle... */ -} - -/*! - \brief decode setup data packet - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -static void usbd_setup_request_parse(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - uint8_t *psetup = pudev->dev.setup_packet; - - req->bmRequestType = *psetup; - req->bRequest = *(uint8_t *)(psetup + 1U); - req->wValue = SWAPBYTE (psetup + 2U); - req->wIndex = SWAPBYTE (psetup + 4U); - req->wLength = SWAPBYTE (psetup + 6U); - - pudev->dev.ctl_len = req->wLength; -} - -/*! - \brief handle USB low level error event - \param[in] pudev: pointer to USB device instance - \param[in] req: pointer to USB device request - \param[out] none - \retval none -*/ -void usbd_enum_error(usb_core_handle_struct *pudev, usb_device_req_struct *req) -{ - usbd_ep_stall(pudev, 0x80U); - usbd_ep_stall(pudev, 0x00U); - usb_ep0_startout(pudev); -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_core.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_core.c deleted file mode 100644 index d717e87b21..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_core.c +++ /dev/null @@ -1,734 +0,0 @@ -/*! - \file usbh_core.c - \brief this file implements the functions for the core state machine process - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_hcs.h" -#include "usbh_core.h" -#include "usbh_int.h" -#include "stdio.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" -#include "usb_core.h" - -extern class_polling_fun_cb_struct class_polling_cb; - -uint8_t usbh_sof (usb_core_handle_struct *pudev); -uint8_t usbh_connected (usb_core_handle_struct *pudev); -uint8_t usbh_disconnected (usb_core_handle_struct *pudev); - -usbh_hcd_int_cb_struct usbh_hcd_int_cb = -{ - usbh_sof, - usbh_connected, - usbh_disconnected, -}; - -usbh_hcd_int_cb_struct *usbh_hcd_int_fops = &usbh_hcd_int_cb; -extern usbh_state_handle_struct usbh_state_core; - -static void host_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_attached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_dev_detached_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_enum_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_request_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_class_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_user_input_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_suspended_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void host_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate); - -/* the host state handle function array */ -void (*host_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - host_idle_handle, - host_dev_attached_handle, - host_dev_detached_handle, - host_detect_dev_speed_handle, - host_enum_handle, - host_class_request_handle, - host_class_handle, - host_user_input_handle, - host_suspended_handle, - host_error_handle, -}; - -/* the host state handle table */ -state_table_struct host_handle_table[HOST_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {HOST_IDLE, HOST_EVENT_ATTACHED, HOST_DEV_ATTACHED, only_state_move }, - {HOST_DEV_ATTACHED, HOST_EVENT_ENUM, HOST_ENUMERATION, only_state_move }, - {HOST_ENUMERATION, HOST_EVENT_USER_INPUT, HOST_USER_INPUT, only_state_move }, - {HOST_USER_INPUT, HOST_EVENT_CLASS_REQ, HOST_CLASS_REQUEST, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_CLASS, HOST_CLASS, only_state_move }, - {HOST_CLASS, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, - {HOST_ERROR, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_DEV_DETACHED, HOST_EVENT_IDLE, HOST_IDLE, only_state_move }, - {HOST_CLASS_REQUEST, HOST_EVENT_ERROR, HOST_ERROR, only_state_move }, -}; - -/*! - \brief the polling function of HOST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum host_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_state_handle_struct *p_state = (usbh_state_handle_struct *)pustate; - - scd_begin(p_state, HOST_FSM_ID); - - if (-1 == p_state->usbh_current_state_stack_top) { - uint8_t cur_state = p_state->usbh_current_state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != cur_state)) { - if (HOST_DEV_DETACHED != cur_state) { - p_state->usbh_current_state = HOST_DEV_DETACHED; - cur_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[cur_state](pudev, puhost, p_state); - } else { - uint8_t stack0_state = p_state->stack[0].state; - - if ((0U == hcd_is_device_connected(pudev)) && (HOST_IDLE != stack0_state)) { - if (HOST_DEV_DETACHED != stack0_state) { - p_state->stack[0].state = HOST_DEV_DETACHED; - stack0_state = HOST_DEV_DETACHED; - p_state->usbh_current_state = HOST_DEV_DETACHED; - } - } - - host_state_handle[stack0_state](pudev, puhost, p_state); - } - - return USBH_OK; -} - -/*! - \brief the handle function of HOST_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (hcd_is_device_connected(pudev)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ATTACHED, pustate->usbh_current_state); - - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } -} - -/*! - \brief the handle function of HOST_DEV_ATTACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_attached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usr_cb->device_connected(); - puhost->control.hc_out_num = usbh_channel_alloc(pudev, 0x00U); - puhost->control.hc_in_num = usbh_channel_alloc(pudev, 0x80U); - - /* reset usb device */ - if (0U == usb_port_reset(pudev)) { - puhost->usr_cb->device_reset(); - - /* wait for USB USBH_ISR_PrtEnDisableChange() - * host is now ready to start the enumeration - */ - puhost->device.speed = (uint8_t)USB_CURRENT_SPEED_GET(); - puhost->usr_cb->device_speed_detected(puhost->device.speed); - - /* open IN control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_in_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - /* open OUT control pipes */ - usbh_channel_open (pudev, - puhost->control.hc_out_num, - puhost->device.address, - puhost->device.speed, - USB_EPTYPE_CTRL, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_ENUM, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_ENUMERATION state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_enum_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == enum_state_polling_fun(pudev, puhost, pustate)) { - puhost->usr_cb->enumeration_finish(); - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_USER_INPUT, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_USER_INPUT state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_user_input_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_USER_RESP_OK == puhost->usr_cb->user_input()) { - if (USBH_OK == (puhost->class_init(pudev, puhost))) { - scd_event_handle(pudev, - puhost, - pustate, - HOST_EVENT_CLASS_REQ, - pustate->usbh_current_state); - } - } -} - -/*! - \brief the handle function of HOST_CLASS_REQUEST state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_request_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - if (USBH_OK == class_req_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_CLASS, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of HOST_CLASS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_class_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - class_state_polling_fun(pudev, puhost, pustate); -} - -/*! - \brief the handle function of HOST_SUSPENDED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_suspended_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief the handle function of HOST_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* re-initilaize host for new enumeration */ - usbh_deinit (pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DEV_DETACHED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_dev_detached_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* manage user disconnect operations*/ - puhost->usr_cb->device_disconnected(); - - /* re-initilaize host for new enumeration */ - usbh_deinit(pudev, puhost,&usbh_state_core); - puhost->usr_cb->deinit(); - puhost->class_deinit(pudev, &puhost->device); - usbh_allchannel_dealloc(pudev); - scd_event_handle(pudev, puhost, pustate, HOST_EVENT_IDLE, pustate->usbh_current_state); -} - -/*! - \brief the handle function of HOST_DETECT_DEV_SPEED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void host_detect_dev_speed_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - /* no operation */ -} - -/*! - \brief usb connect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_connected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 1U; - - return 0U; -} - -/*! - \brief usb disconnect callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_disconnected (usb_core_handle_struct *pudev) -{ - pudev->host.connect_status = 0U; - - return 0U; -} - -/*! - \brief usb sof callback function from the interrupt. - \param[in] pudev: pointer to usb device - \param[out] none - \retval operation status -*/ -uint8_t usbh_sof (usb_core_handle_struct *pudev) -{ - /* this callback could be used to implement a scheduler process */ - return 0U; -} - -/*! - \brief initialize the host portion of the driver. - \param[in] pudev: pointer to usb device - \param[in] core_id: usb otg core identifier(high-speed or full-speed) - \param[out] none - \retval operation status -*/ -uint32_t hcd_init(usb_core_handle_struct *pudev, usb_core_id_enum core_id) -{ - pudev->host.connect_status = 0U; - - pudev->host.host_channel[0].endp_mps = 8U; - - usb_core_select(pudev, core_id); - -#ifndef DUAL_ROLE_MODE_ENABLED - - USB_GLOBAL_INT_DISABLE(); - - usb_core_init(pudev); - - /* force host mode*/ - usb_mode_set(pudev, HOST_MODE); - - usb_hostcore_init(pudev); - - USB_GLOBAL_INT_ENABLE(); - -#endif - - return 0U; -} - -/*! - \brief check if the device is connected. - \param[in] pudev: pointer to usb device - \param[out] none - \retval device connection status. 1 -> connected and 0 -> disconnected -*/ -uint32_t hcd_is_device_connected(usb_core_handle_struct *pudev) -{ - return (uint32_t)(pudev->host.connect_status); -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval urb_state_enum -*/ -urb_state_enum hcd_urb_state_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].urb_state; -} - -/*! - \brief this function returns the last URBstate - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval No. of data bytes transferred -*/ -uint32_t hcd_xfer_count_get (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - return pudev->host.host_channel[channel_num].xfer_count; -} - -/*! - \brief de-initialize host - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[out] none - \retval host status -*/ -usbh_status_enum usbh_deinit(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate) -{ - /* software init */ - - puhost->control.ep0_size = USB_MAX_EP0_SIZE; - - puhost->device.address = USBH_DEVICE_ADDRESS_DEFAULT; - puhost->device.speed = HPRT_PRTSPD_FULL_SPEED; - - usbh_channel_free(pudev, puhost->control.hc_in_num); - usbh_channel_free(pudev, puhost->control.hc_out_num); - - scd_init(pustate); - scd_table_regist(pustate, host_handle_table, HOST_FSM_ID, HOST_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, enum_handle_table, ENUM_FSM_ID, ENUM_HANDLE_TABLE_SIZE); - scd_table_regist(pustate, ctrl_handle_table, CTRL_FSM_ID, CTRL_HANDLE_TABLE_SIZE); - - scd_begin(pustate,HOST_FSM_ID); - scd_state_move(pustate, HOST_IDLE); - - return USBH_OK; -} - -/*! - \brief state core driver init - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_init(usbh_state_handle_struct* pustate) -{ - /* init the state core */ - pustate->usbh_current_state = 0U; - pustate->usbh_current_state_table = NULL; - pustate->usbh_current_state_table_size = 0U; - - pustate->usbh_current_state_stack_top = -1; - pustate->stack->state = 0U; - pustate->stack->table_size = 0U; - pustate->stack->table = NULL; - - pustate->usbh_regist_state_table_num = 0U; - pustate->usbh_regist_state_table->table = NULL; - pustate->usbh_regist_state_table->table_size = 0U; - pustate->usbh_regist_state_table->id = 0U; - - /* init the control and the enumeration polling handle flag */ - ctrl_polling_handle_flag = 0U; - enum_polling_handle_flag = 0U; -} - -/*! - \brief state core driver table regist - \param[in] pustate: pointer to usb state driver - \param[in] pstate_table: pointer to the table to regist - \param[in] table_id: the id of the table to regist - \param[in] current_table_size: the size of the current table to regist - \param[out] none - \retval none -*/ -void scd_table_regist (usbh_state_handle_struct* pustate, - state_table_struct* pstate_table, - uint8_t table_id, - uint8_t current_table_size) -{ - usbh_state_regist_table_struct *cur_state_reg_table; - - cur_state_reg_table = &pustate->usbh_regist_state_table[pustate->usbh_regist_state_table_num]; - - cur_state_reg_table->id = table_id; - cur_state_reg_table->table = pstate_table; - cur_state_reg_table->table_size = current_table_size; - - pustate->usbh_regist_state_table_num++; -} - -/*! - \brief state core driver begin - \param[in] pustate: pointer to usb state driver - \param[in] table_id: the id of the table to begin - \param[out] none - \retval none -*/ -void scd_begin(usbh_state_handle_struct* pustate, uint8_t table_id) -{ - uint8_t i = 0U, table_num = pustate->usbh_regist_state_table_num; - usbh_state_regist_table_struct *cur_state_reg_table; - - for (i = 0U; i < table_num; i++) { - cur_state_reg_table = &pustate->usbh_regist_state_table[i]; - - if (table_id == cur_state_reg_table->id) { - pustate->usbh_current_state_table = cur_state_reg_table->table; - pustate->usbh_current_state_table_size = cur_state_reg_table->table_size; - break; - } - } -} - -/*! - \brief state core driver move state - \param[in] pustate: pointer to usb state driver - \param[in] state: the state to move - \param[out] none - \retval none -*/ -void scd_state_move(usbh_state_handle_struct* pustate, uint8_t state) -{ - pustate->usbh_current_state = state; -} - -/*! - \brief state core driver event handle - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[in] event: the current event - \param[in] state: the current state - \param[out] none - \retval host status -*/ -usbh_status_enum scd_event_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct* pustate, - uint8_t event, - uint8_t state) -{ - uint8_t i = 0U; - ACT_FUN event_act_fun = NULL; - state_table_struct *backup_state_t = pustate->usbh_current_state_table; - state_table_struct *executive_state_table = pustate->usbh_current_state_table; - - /* look up the table to find the action function */ - for (i = 0U; i < pustate->usbh_current_state_table_size; i++) { - if (state == executive_state_table->cur_state) { - if (event == executive_state_table->cur_event) { - state = executive_state_table->next_state; - event_act_fun = executive_state_table->event_action_fun; - break; - } else { - executive_state_table++; - } - } else { - executive_state_table++; - } - } - - pustate->usbh_current_state_table = backup_state_t; - - /* if the action function is not NULL, execute the action function */ - if (event_act_fun) { - if (event_act_fun == &only_state_move) { - pustate->usbh_current_state = state; - } else { - return event_act_fun(pudev, puhost, pustate); - } - } - - return USBH_BUSY; -} - -/*! - \brief state core driver table push - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_push(usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - if (pustate->usbh_current_state_stack_top < MAX_USBH_STATE_STACK_DEEP) { - pustate->usbh_current_state_stack_top++; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - /* put the current state table into the state stack */ - top_state_element->state = pustate->usbh_current_state; - top_state_element->table = pustate->usbh_current_state_table; - top_state_element->table_size = pustate->usbh_current_state_table_size; - } -} - -/*! - \brief state core driver table pop - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -void scd_table_pop (usbh_state_handle_struct* pustate) -{ - usbh_state_stack_struct *top_state_element; - - top_state_element = &pustate->stack[pustate->usbh_current_state_stack_top]; - - if (pustate->usbh_current_state_stack_top > -1) { - /* get the current state table from the state stack */ - pustate->usbh_current_state = top_state_element->state; - pustate->usbh_current_state_table = top_state_element->table; - pustate->usbh_current_state_table_size = top_state_element->table_size; - pustate->usbh_current_state_stack_top--; - } -} -/*! - \brief the polling function of class req state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_req_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_req_polling(pudev, puhost, pustate); -} - -/*! - \brief the polling function of class state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval host status -*/ -static usbh_status_enum class_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return class_polling_cb.class_polling(pudev, puhost, pustate); -} - -/*! - \brief the function is only used to state move - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum only_state_move (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - return USBH_OK; -} - -/*! - \brief the function to the up state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum goto_up_state_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - scd_table_pop((usbh_state_handle_struct *)pustate); - - return USBH_OK; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c deleted file mode 100644 index c40df945f3..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_ctrl.c +++ /dev/null @@ -1,636 +0,0 @@ -/*! - \file usbh_ctrl.c - \brief this file implements the functions for the control transmit process - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_core.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t ctrl_polling_handle_flag = 0U; -uint8_t ctrl_setup_wait_flag = 0U; -uint8_t ctrl_data_wait_flag = 0U; -uint8_t ctrl_status_wait_flag = 0U; - -static uint16_t timeout = 0U; - -static void ctrl_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_setup_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_data_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_status_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_error_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void ctrl_complete_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the ctrl state handle function array */ -void (*ctrl_state_handle[]) (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) = -{ - ctrl_idle_handle, - ctrl_setup_handle, - ctrl_data_handle, - ctrl_status_handle, - ctrl_error_handle, - ctrl_stalled_handle, - ctrl_complete_handle, -}; - -/* the ctrl state handle table */ -state_table_struct ctrl_handle_table[CTRL_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {CTRL_IDLE, CTRL_EVENT_SETUP, CTRL_SETUP, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_DATA, CTRL_DATA, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_SETUP, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STATUS, CTRL_STATUS, only_state_move }, - {CTRL_DATA, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_DATA, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_COMPLETE, CTRL_COMPLETE, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_ERROR, CTRL_ERROR, only_state_move }, - {CTRL_STATUS, CTRL_EVENT_STALLED, CTRL_STALLED, only_state_move }, - {CTRL_ERROR, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_STALLED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, - {CTRL_COMPLETE, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of CTRL state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -usbh_status_enum ctrl_state_polling_fun (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - - p_state = (usbh_state_handle_struct *)pustate; - - /* if first enter this function, begin the ctrl state */ - if (0U == ctrl_polling_handle_flag) { - ctrl_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, CTRL_IDLE); - } - - /* base on the current state to handle the ctrl state */ - scd_begin(p_state, CTRL_FSM_ID); - ctrl_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - - /* determine the control transfer whether to complete */ - switch (puhost->usbh_backup_state.ctrl_backup_state) { - case CTRL_COMPLETE: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_OK; - break; - case CTRL_STALLED: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_NOT_SUPPORTED; - break; - case CTRL_ERROR: - ctrl_polling_handle_flag = 0U; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - exe_state = USBH_FAIL; - break; - default: - exe_state = USBH_BUSY; - break; - } - - return exe_state; -} - -/*! - \brief the handle function of CTRL_IDLE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_idle_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_IDLE; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_SETUP state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_setup_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_SETUP; - - if (0U == ctrl_setup_wait_flag) { - ctrl_setup_wait_flag = 1U; - - /* send a setup packet */ - usbh_ctltx_setup (pudev, - puhost->control.setup.data, - puhost->control.hc_out_num); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - /* case setup packet sent successfully */ - if (URB_DONE == urb_status) { - /* check if there is a data stage */ - if (0U != puhost->control.setup.b.wLength) { - ctrl_setup_wait_flag = 0U; - timeout = DATA_STAGE_TIMEOUT; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_DATA, pustate->usbh_current_state); - /* no data stage */ - } else { - timeout = NODATA_STAGE_TIMEOUT; - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - } - - /* set the delay timer to enable timeout for data stage completion */ - puhost->control.timer = (uint16_t)USB_CURRENT_FRAME_GET(); - } else if (URB_ERROR == urb_status) { - ctrl_setup_wait_flag = 0U; - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_ERROR, pustate->usbh_current_state); - } else { - /* no operation */ - } - } -} - -/*! - \brief the handle function of CTRL_DATA state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_data_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - puhost->usbh_backup_state.ctrl_backup_state = CTRL_DATA; - - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_IN == direction) { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* issue an IN token */ - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_in_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - /* check is data packet transfered successfully */ - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_data_wait_flag = 0U; - - /* timeout for IN transfer */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - if (0U == ctrl_data_wait_flag) { - ctrl_data_wait_flag = 1U; - - /* start DATA out transfer (only one DATA packet)*/ - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out = 1U; - - usbh_xfer(pudev, - puhost->control.buff, - puhost->control.hc_out_num, - puhost->control.length); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_data_wait_flag = 0U; - - /* if the setup pkt is sent successful, then change the state */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STATUS, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_data_wait_flag = 0U; - - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* nack received from device */ - ctrl_data_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_data_wait_flag = 0U; - - /* device error */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_STATUS state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_status_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint8_t direction; - urb_state_enum urb_status = URB_IDLE; - - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STATUS; - - /* get the transfer direction in the data state, but the transfer direction in the status state is opposite */ - direction = (puhost->control.setup.b.bmRequestType & USB_DIR_MASK); - - if (USB_DIR_OUT == direction) { - /* handle status in */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_in_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_in_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status*/ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - case URB_STALL: - ctrl_status_wait_flag = 0U; - - /* handle URB_STALL status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_STALLED, - pustate->usbh_current_state); - break; - default: - if (((uint16_t)USB_CURRENT_FRAME_GET() - puhost->control.timer) > timeout) { - ctrl_status_wait_flag = 0U; - - /* handle timeout */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - } - break; - } - } - } else { - /* handle status out */ - if (0U == ctrl_status_wait_flag) { - ctrl_status_wait_flag = 1U; - pudev->host.host_channel[puhost->control.hc_out_num].data_tg_out ^= 1U; - usbh_xfer (pudev, 0U, puhost->control.hc_out_num, 0U); - } else { - urb_status = hcd_urb_state_get(pudev, puhost->control.hc_out_num); - - switch (urb_status) { - case URB_DONE: - ctrl_status_wait_flag = 0U; - - /* handle URB_DONE status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_COMPLETE, - pustate->usbh_current_state); - break; - case URB_NOTREADY: - /* handle URB_NOTREADY status */ - ctrl_status_wait_flag = 0U; - break; - case URB_ERROR: - ctrl_status_wait_flag = 0U; - - /* handle URB_ERROR status */ - scd_event_handle(pudev, - puhost, - pustate, - CTRL_EVENT_ERROR, - pustate->usbh_current_state); - break; - default: - break; - } - } - } -} - -/*! - \brief the handle function of CTRL_ERROR state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_error_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_ERROR; - - if (++puhost->control.error_count <= USBH_MAX_ERROR_COUNT) { - /* do the transmission again, starting from SETUP Packet */ - scd_event_handle(pudev, puhost, pustate, CTRL_EVENT_SETUP, pustate->usbh_current_state); - } else { - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of CTRL_STALLED state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_stalled_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_STALLED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief the handle function of CTRL_COMPLETE state - \param[in] pudev: pointer to usb device - \param[in] puhost: pointer to usb host - \param[in] pustate: pointer to usb state driver - \param[out] none - \retval none -*/ -static void ctrl_complete_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.ctrl_backup_state = CTRL_COMPLETE; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief send datas from the host channel - \param[in] pudev: pointer to usb device - \param[in] buf: data buffer address to send datas - \param[in] hc_num: the number of the host channel - \param[in] len: length of the send data - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_xfer (usb_core_handle_struct *pudev, - uint8_t *buf, - uint8_t hc_num, - uint16_t len) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->xfer_buff = buf; - puhc->xfer_len = len; - - switch (puhc->endp_type) { - case USB_EPTYPE_CTRL: - if (0U == puhc->endp_in) { - if (0U == len) { - /* for status out stage, length = 0, status out pid = 1 */ - puhc->data_tg_out = 1U; - } - - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - puhc->DPID = HC_PID_DATA1; - } - break; - - case USB_EPTYPE_ISOC: - puhc->DPID = HC_PID_DATA0; - break; - - case USB_EPTYPE_BULK: - if (0U == puhc->endp_in) { - /* set the data toggle bit as per the flag */ - if (0U == puhc->data_tg_out) { - /* put the pid 0 */ - puhc->DPID = HC_PID_DATA0; - } else { - /* put the pid 1 */ - puhc->DPID = HC_PID_DATA1; - } - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - } - break; - - case USB_EPTYPE_INTR: - if (0U == puhc->endp_in) { - if (0U == puhc->data_tg_out) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_out ^= 1U; - } else { - if (0U == puhc->data_tg_in) { - puhc->DPID = HC_PID_DATA0; - } else { - puhc->DPID = HC_PID_DATA1; - } - - /* toggle data pid */ - puhc->data_tg_in ^= 1U; - } - break; - - default: - break; - } - - hcd_submit_request (pudev, hc_num); - - return USBH_OK; -} - -/*! - \brief send the setup packet to the device - \param[in] pudev: pointer to usb device - \param[in] buf: buffer pointer from which the data will be send to device - \param[in] hc_num: host channel number - \param[out] none - \retval host operation status -*/ -usbh_status_enum usbh_ctltx_setup (usb_core_handle_struct *pudev, uint8_t *buf, uint8_t hc_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[hc_num]; - - puhc->DPID = HC_PID_SETUP; - puhc->xfer_buff = buf; - puhc->xfer_len = USBH_SETUP_PACKET_SIZE; - - return (usbh_status_enum)hcd_submit_request (pudev, hc_num); -} - -/*! - \brief this function prepare a hc and start a transfer - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint32_t hcd_submit_request (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - puhc->urb_state = URB_IDLE; - puhc->xfer_count = 0U; - - return (uint32_t)usb_hostchannel_startxfer(pudev, channel_num); -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_hcs.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_hcs.c deleted file mode 100644 index 801cb5069e..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_hcs.c +++ /dev/null @@ -1,182 +0,0 @@ -/*! - \file usbh_hcs.c - \brief this file implements functions for opening and closing host channels - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_hcs.h" - -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev); - -/*! - \brief open a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_open (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - uint16_t channel_info = puhc->info; - - puhc->endp_id = (uint8_t)channel_info & 0x7FU; - puhc->endp_in = (uint8_t)(channel_info & 0x80U) >> 7; - puhc->endp_type = ep_type; - puhc->endp_mps = ep_mps; - puhc->dev_addr = dev_addr; - puhc->dev_speed = dev_speed; - - puhc->data_tg_in = 0U; - puhc->data_tg_out = 0U; - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief modify a channel - \param[in] pudev: pointer to usb device - \param[in] channel_num: host channel number which is in (0..7) - \param[in] dev_addr: USB Device address allocated to attached device - \param[in] dev_speed: USB device speed (Full speed/Low speed) - \param[in] ep_type: endpoint type (bulk/int/ctl) - \param[in] ep_mps: max packet size - \param[out] none - \retval operation status -*/ -uint8_t usbh_channel_modify (usb_core_handle_struct *pudev, - uint8_t channel_num, - uint8_t dev_addr, - uint8_t dev_speed, - uint8_t ep_type, - uint16_t ep_mps) -{ - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - if (0U != dev_addr) { - puhc->dev_addr = dev_addr; - } - - if ((puhc->endp_mps != ep_mps) && (0U != ep_mps)) { - puhc->endp_mps = ep_mps; - } - - if ((puhc->dev_speed != dev_speed) && (0U != dev_speed)) { - puhc->dev_speed = dev_speed; - } - - usb_hostchannel_init(pudev, channel_num); - - return (uint8_t)HC_OK; -} - -/*! - \brief allocate a new channel for the pipe - \param[in] pudev: pointer to usb device - \param[in] ep_addr: endpoint for which the channel to be allocated - \param[out] none - \retval host channel number -*/ -uint8_t usbh_channel_alloc (usb_core_handle_struct *pudev, uint8_t ep_addr) -{ - uint16_t hc_num = usbh_freechannel_get(pudev); - - if ((uint16_t)HC_ERROR != hc_num) { - pudev->host.host_channel[hc_num].info = HC_USED | ep_addr; - } - - return (uint8_t)hc_num; -} - -/*! - \brief free the usb host channel - \param[in] pudev: pointer to usb device - \param[in] index: channel number to be freed which is in (0..7) - \param[out] none - \retval host operation status -*/ -uint8_t usbh_channel_free (usb_core_handle_struct *pudev, uint8_t index) -{ - if (index < HC_MAX) { - pudev->host.host_channel[index].info &= HC_USED_MASK; - } - - return USBH_OK; -} - -/*! - \brief free all usb host channel - \param[in] pudev: pointer to usb device - \param[out] none - \retval host operation status -*/ -uint8_t usbh_allchannel_dealloc (usb_core_handle_struct *pudev) -{ - uint8_t index; - - for (index = 2U; index < HC_MAX; index ++) { - pudev->host.host_channel[index].info = 0U; - } - - return USBH_OK; -} - -/*! - \brief get a free channel number for allocation to a device endpoint - \param[in] pudev: pointer to usb device - \param[out] none - \retval free channel number -*/ -static uint16_t usbh_freechannel_get (usb_core_handle_struct *pudev) -{ - uint8_t index = 0U; - - for (index = 0U; index < HC_MAX; index++) { - if (0U == (pudev->host.host_channel[index].info & HC_USED)) { - return (uint16_t)index; - } - } - - return HC_ERROR; -} - diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_int.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_int.c deleted file mode 100644 index 0d7c8c043a..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_int.c +++ /dev/null @@ -1,609 +0,0 @@ -/*! - \file usbh_int.c - \brief USB host mode interrupt handler file - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usb_core.h" -#include "usb_defines.h" -#include "usbh_int.h" - -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num); -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev); -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev); - -/*! - \brief handle global host interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -uint32_t usbh_isr (usb_core_handle_struct *pudev) -{ - uint32_t retval = 0U; - uint32_t int_flag = 0U; - - /* check if host mode */ - if (USB_CURRENT_MODE_GET() == HOST_MODE) { - USB_CORE_INTR_READ(int_flag); - - if (!int_flag) { - return 0U; - } - - /* start of frame interrupt handle */ - if (int_flag & GINTF_SOF) { - retval |= usbh_intf_sof (pudev); - } - - /* Rx FIFO non-empty interrupt handle */ - if (int_flag & GINTF_RXFNEIF) { - retval |= usbh_intf_rxfifo_noempty (pudev); - } - - /* Non-Periodic Tx FIFO empty interrupt hanlde */ - if (int_flag & GINTF_NPTXFEIF) { - retval |= usbh_intf_nptxfifo_empty (pudev); - } - - /* periodic Tx FIFO empty interrupt handle */ - if (int_flag & GINTF_PTXFEIF) { - retval |= usbh_intf_ptxfifo_empty (pudev); - } - - /* host channels interrupt handle */ - if (int_flag & GINTF_HCIF) { - retval |= usbh_intf_hc (pudev); - } - - /* host port interrupt handle */ - if (int_flag & GINTF_HPIF) { - retval |= usbh_intf_port (pudev); - } - - /* disconnect interrupt handle */ - if (int_flag & GINTF_DISCIF) { - retval |= usbh_intf_disconnect (pudev); - } - - /* isochronous IN transfer not complete interrupt handle */ - if (int_flag & GINTF_ISOONCIF) { - retval |= usbh_intf_iso_incomplete_xfer (pudev); - } - } - - return retval; -} - -/*! - \brief handle the start-of-frame interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_sof (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->sof(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_SOF; - - return 1U; -} - -/*! - \brief handle all host channels interrupt in host mode - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc (usb_core_handle_struct *pudev) -{ - uint8_t i = 0U; - uint32_t retval = 0U; - - for (i = 0U; i < pudev->cfg.host_channel_num; i++) { - if ((USB_HACHINT & HACHINT_HACHINT) & ((uint32_t)1U << i)) { - if ((USB_HCHxCTL((uint16_t)i) & HCHCTL_EPDIR) >> 15U) { - retval |= usbh_intf_hc_in (pudev, i); - } else { - retval |= usbh_intf_hc_out (pudev, i); - } - } - } - - return retval; -} - -/*! - \brief handle the disconnect interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_disconnect (usb_core_handle_struct *pudev) -{ - usbh_hcd_int_fops->device_disconnected(pudev); - - /* clear interrupt */ - USB_GINTF = GINTF_DISCIF; - - return 1U; -} - -/*! - \brief handle the non-periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_nptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HNPTFQSTAT & HNPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HNPTFQSTAT & HNPTFQSTAT_NPTXFS) * 4U; - - if (len > puhc->xfer_len) { - /* last packet */ - len = (uint16_t)puhc->xfer_len; - - USB_GINTEN &= ~GINTF_NPTXFEIF; - - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the periodic tx fifo empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_ptxfifo_empty (usb_core_handle_struct *pudev) -{ - uint8_t channel_num = 0U; - uint32_t dword_len = 0U, len = 0U; - usb_hostchannel_struct *puhc; - - channel_num = (uint8_t)((USB_HPTFQSTAT & HPTFQSTAT_CNUM) >> 27U); - puhc = &pudev->host.host_channel[channel_num]; - dword_len = (puhc->xfer_len + 3U) / 4U; - - while (((USB_HPTFQSTAT & HPTFQSTAT_PTXFS) > dword_len) && (0U != puhc->xfer_len)) { - len = (USB_HPTFQSTAT & HPTFQSTAT_PTXFS) * 4U; - - if (len > puhc->xfer_len) { - len = puhc->xfer_len; - - /* last packet */ - USB_GINTEN &= ~GINTF_PTXFEIF; - } - - dword_len = (puhc->xfer_len + 3U) / 4U; - usb_fifo_write (puhc->xfer_buff, channel_num, (uint16_t)len); - - puhc->xfer_buff += len; - puhc->xfer_len -= len; - puhc->xfer_count += len; - } - - return 1U; -} - -/*! - \brief handle the host port interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_port (usb_core_handle_struct *pudev) -{ - uint8_t port_speed = 0U; - uint8_t port_reset = 0U; - uint32_t retval = 0U; - __IO uint32_t hostportdup = USB_HPCS; - - /* clear the interrupt bits in gintsts */ - hostportdup &= ~HPCS_PE; - hostportdup &= ~HPCS_PCD; - hostportdup &= ~HPCS_PEDC; - - /* port connect detected */ - if (USB_HPCS & HPCS_PCD) { - hostportdup |= HPCS_PCD; - usbh_hcd_int_fops->device_connected(pudev); - retval |= 1U; - } - - /* port enable changed */ - if (USB_HPCS & HPCS_PEDC) { - hostportdup |= HPCS_PEDC; - - if (USB_HPCS & HPCS_PE) { - port_speed = (uint8_t)((USB_HPCS & HPCS_PS) >> 17U); - - if (HPRT_PRTSPD_LOW_SPEED == port_speed) { - USB_HFT = 6000U; - - if (HCTLR_6_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_6_MHZ); - } - port_reset = 1U; - } - } else if(HPRT_PRTSPD_FULL_SPEED == port_speed) { - USB_HFT = 48000U; - - if (HCTLR_48_MHZ != (USB_HCTL & HCTL_CLKSEL)) { - if (USB_CORE_EMBEDDED_PHY == pudev->cfg.phy_interface) { - USB_FSLSCLOCK_INIT(HCTLR_48_MHZ); - } - port_reset = 1U; - } - } else { - /* for high speed device and others */ - port_reset = 1U; - } - } - } - - if (port_reset) { - usb_port_reset(pudev); - } - - /* clear port interrupts */ - USB_HPCS = hostportdup; - - return retval; -} - -/*! - \brief handle the OUT channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_out (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint32_t channel_intr = USB_HCHxINTF((uint16_t)channel_num); - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - channel_intr &= USB_HCHxINTEN((uint16_t)channel_num); - - if (channel_intr & HCHINTF_ACK) { - if (URB_PING == puhc->urb_state) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channel_intr & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channel_intr & HCHINTF_TF) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - puhc->status = HC_XF; - } else if (channel_intr & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - usb_hostchannel_halt(pudev, channel_num); - puhc->status = HC_STALL; - } else if (channel_intr & HCHINTF_NAK) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_NAK; - } else if (channel_intr & HCHINTF_USBER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->err_count ++; - puhc->status = HC_TRACERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channel_intr & HCHINTF_NYET) { - puhc->err_count = 0U; - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_NYET; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NYET; - } else if (channel_intr & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - puhc->status= HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else if (channel_intr & HCHINTF_CH) { - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - - if (USB_EPTYPE_BULK == ((USB_HCHxCTL((uint16_t)channel_num) & HCHCTL_EPTYPE) >> 18)) { - puhc->data_tg_out ^= 1U; - } - break; - case HC_NAK: - puhc->urb_state = URB_NOTREADY; - break; - case HC_NYET: - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - case HC_TRACERR: - if (3U == puhc->err_count) { - puhc->urb_state = URB_ERROR; - puhc->err_count = 0U; - } - break; - default: - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the IN channel interrupt - \param[in] pudev: pointer to usb device instance - \param[in] channel_num: host channel number which is in (0..7) - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_hc_in (usb_core_handle_struct *pudev, uint8_t channel_num) -{ - uint8_t endp_type = 0U; - usb_hostchannel_struct *puhc = &pudev->host.host_channel[channel_num]; - - uint32_t channle_intf = USB_HCHxINTF((uint16_t)channel_num); - __IO uint32_t channel_ctrl = USB_HCHxCTL((uint16_t)channel_num); - - channle_intf &= USB_HCHxINTEN((uint16_t)channel_num); - - endp_type = (uint8_t)((channel_ctrl & HCHCTL_EPTYPE) >> 18U); - - if (channle_intf & HCHINTF_ACK) { - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_ACK; - } else if (channle_intf & HCHINTF_STALL) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - puhc->status = HC_STALL; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_STALL; - - /* NOTE: When there is a 'stall', reset also nak, - else, the pudev->host.status = HC_STALL - will be overwritten by 'nak' in code below */ - channle_intf &= ~HCHINTF_NAK; - - usb_hostchannel_halt(pudev, channel_num); - } else if (channle_intf & HCHINTF_DTER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->status = HC_DTGERR; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_DTER; - } else { - /* no operation */ - } - - if (channle_intf & HCHINTF_REQOVR) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_REQOVR; - } else if (channle_intf & HCHINTF_TF) { - puhc->status = HC_XF; - puhc->err_count = 0U; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_TF; - - if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - puhc->data_tg_in ^= 1U; - } else if (USB_EPTYPE_INTR == endp_type) { - channel_ctrl |= HCHCTL_ODDFRM; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - puhc->urb_state = URB_DONE; - } else { - /* no operation */ - } - } else if (channle_intf & HCHINTF_CH) { - USB_HCHxINTEN((uint16_t)channel_num) &= ~HCHINTEN_CHIE; - - switch (puhc->status) { - case HC_XF: - puhc->urb_state = URB_DONE; - break; - case HC_TRACERR: - case HC_DTGERR: - puhc->err_count = 0U; - puhc->urb_state = URB_ERROR; - break; - case HC_STALL: - puhc->urb_state = URB_STALL; - break; - default: - if (USB_EPTYPE_INTR == endp_type) { - puhc->data_tg_in ^= 1U; - } - break; - } - - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_CH; - } else if (channle_intf & HCHINTF_USBER) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - (puhc->err_count)++; - puhc->status = HC_TRACERR; - usb_hostchannel_halt(pudev, channel_num); - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_USBER; - } else if (channle_intf & HCHINTF_NAK) { - if (USB_EPTYPE_INTR == endp_type) { - USB_HCHxINTEN((uint16_t)channel_num) |= HCHINTEN_CHIE; - usb_hostchannel_halt(pudev, channel_num); - } else if ((USB_EPTYPE_CTRL == endp_type) || (USB_EPTYPE_BULK == endp_type)) { - /* re-activate the channel */ - channel_ctrl |= HCHCTL_CEN; - channel_ctrl &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = channel_ctrl; - } else { - /* no operation */ - } - - puhc->status = HC_NAK; - USB_HCHxINTF((uint16_t)channel_num) = HCHINTF_NAK; - } else { - /* no operation */ - } - - return 1U; -} - -/*! - \brief handle the rx fifo non-empty interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_rxfifo_noempty (usb_core_handle_struct *pudev) -{ - uint32_t count = 0U; - __IO uint8_t channel_num = 0U; - __IO uint32_t rx_status = 0U; - uint32_t usbh_ch_ctl_reg = 0U; - usb_hostchannel_struct *puhc; - - /* disable the Rx status queue level interrupt */ - USB_GINTEN &= ~GINTF_RXFNEIF; - - rx_status = USB_GRSTATP; - channel_num = (uint8_t)(rx_status & GRSTATRP_CNUM); - puhc = &pudev->host.host_channel[channel_num]; - - switch ((rx_status & GRSTATRP_RPCKST) >> 17) { - case GRSTATR_RPCKST_IN: - count = (rx_status & GRSTATRP_BCOUNT) >> 4; - - /* read the data into the host buffer. */ - if ((count > 0U) && (puhc->xfer_buff != (void *)0)) { - usb_fifo_read(puhc->xfer_buff, (uint16_t)count); - - /* manage multiple Xfer */ - puhc->xfer_buff += count; - puhc->xfer_count += count; - - if (USB_HCHxLEN((uint16_t)channel_num) & HCHLEN_PCNT) { - /* re-activate the channel when more packets are expected */ - usbh_ch_ctl_reg = USB_HCHxCTL((uint16_t)channel_num); - usbh_ch_ctl_reg |= HCHCTL_CEN; - usbh_ch_ctl_reg &= ~HCHCTL_CDIS; - USB_HCHxCTL((uint16_t)channel_num) = usbh_ch_ctl_reg; - } - } - break; - case GRSTATR_RPCKST_IN_XFER_COMP: - break; - case GRSTATR_RPCKST_DATA_TOGGLE_ERR: - count = (rx_status & GRSTATRP_BCOUNT) >> 4; - - while (count > 0) { - rx_status = USB_GRSTATP; - count--; - } - break; - case GRSTATR_RPCKST_CH_HALTED: - break; - default: - break; - } - - /* enable the Rx status queue level interrupt */ - USB_GINTEN |= GINTF_RXFNEIF; - - return 1U; -} - -/*! - \brief handle the incomplete periodic transfer interrupt - \param[in] pudev: pointer to usb device instance - \param[out] none - \retval operation status -*/ -static uint32_t usbh_intf_iso_incomplete_xfer (usb_core_handle_struct *pudev) -{ - __IO uint32_t gint_flag = 0U; - - gint_flag = USB_HCHxCTL(0U); - USB_HCHxCTL(0U) = 0U; - - gint_flag = 0U; - - /* clear interrupt */ - gint_flag |= GINTF_ISOONCIF; - USB_GINTF = gint_flag; - - return 1U; -} diff --git a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_std.c b/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_std.c deleted file mode 100644 index 04adcfabc6..0000000000 --- a/bsp/gd32350r-eval/Libraries/GD32F3x0_usbfs_driver/Source/usbh_std.c +++ /dev/null @@ -1,831 +0,0 @@ -/*! - \file usbh_std.c - \brief USB 2.0 standard function definition - - \version 2017-06-06, V1.0.0, firmware for GD32F3x0 - \version 2019-06-01, V2.0.0, firmware for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "usbh_core.h" -#include "usbh_usr.h" -#include "usbh_std.h" -#include "usbh_ctrl.h" - -uint8_t local_buffer[64]; -uint8_t usbh_cfg_desc[512]; -uint8_t enum_polling_handle_flag = 0U; - -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_addr_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate); - -/* the enumeration state handle function array */ -void (*enum_state_handle[]) (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) = -{ - enum_idle_handle, - enum_set_addr_handle, - enum_get_full_dev_desc_handle, - enum_get_cfg_desc_handle, - enum_get_full_cfg_desc_handle, - enum_get_mfc_string_desc_handle, - enum_get_product_string_desc_handle, - enum_get_serialnum_string_desc_handle, - enum_set_configuration_handle, - enum_dev_configured_handle, -}; - -/* the enumeration state handle table */ -state_table_struct enum_handle_table[ENUM_HANDLE_TABLE_SIZE] = -{ - /* the current state the current event the next state the event function */ - {ENUM_IDLE, ENUM_EVENT_SET_ADDR, ENUM_SET_ADDR, only_state_move }, - {ENUM_SET_ADDR, ENUN_EVENT_GET_FULL_DEV_DESC, ENUM_GET_FULL_DEV_DESC, only_state_move }, - {ENUM_GET_FULL_DEV_DESC, ENUN_EVENT_GET_CFG_DESC, ENUM_GET_CFG_DESC, only_state_move }, - {ENUM_GET_CFG_DESC, ENUN_EVENT_GET_FULL_CFG_DESC, ENUM_GET_FULL_CFG_DESC, only_state_move }, - {ENUM_GET_FULL_CFG_DESC, ENUN_EVENT_GET_MFC_STRING_DESC, ENUM_GET_MFC_STRING_DESC, only_state_move }, - {ENUM_GET_MFC_STRING_DESC, ENUN_EVENT_GET_PRODUCT_STRING_DESC, ENUM_GET_PRODUCT_STRING_DESC, only_state_move }, - {ENUM_GET_PRODUCT_STRING_DESC, ENUN_EVENT_GET_SERIALNUM_STRING_DESC, ENUM_GET_SERIALNUM_STRING_DESC, only_state_move }, - {ENUM_GET_SERIALNUM_STRING_DESC, ENUN_EVENT_SET_CONFIGURATION, ENUM_SET_CONFIGURATION, only_state_move }, - {ENUM_SET_CONFIGURATION, ENUN_EVENT_DEV_CONFIGURED, ENUM_DEV_CONFIGURED, only_state_move }, - {ENUM_DEV_CONFIGURED, GO_TO_UP_STATE_EVENT, UP_STATE, goto_up_state_fun }, -}; - -/*! - \brief the polling function of enumeration state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval usb host status -*/ -usbh_status_enum enum_state_polling_fun (usb_core_handle_struct *pudev, usbh_host_struct *puhost, void *pustate) -{ - usbh_status_enum exe_state = USBH_BUSY; - usbh_state_handle_struct *p_state; - p_state = (usbh_state_handle_struct *)pustate; - - if (0U == enum_polling_handle_flag) { - enum_polling_handle_flag = 1U; - scd_table_push(p_state); - scd_state_move(p_state, ENUM_IDLE); - } - - /* start the enumeration state handle */ - scd_begin(p_state,ENUM_FSM_ID); - - if (0 == p_state->usbh_current_state_stack_top) { - enum_state_handle[p_state->usbh_current_state](pudev, puhost, p_state); - } else { - enum_state_handle[p_state->stack[1].state](pudev, puhost, p_state); - } - - /* determine the enumeration whether to complete */ - if (ENUM_DEV_CONFIGURED == puhost->usbh_backup_state.enum_backup_state) { - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - enum_polling_handle_flag = 0U; - exe_state = USBH_OK; - } - - return exe_state; -} - -/*! - \brief the handle function of ENUM_IDLE state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_idle_handle (usb_core_handle_struct *pudev, usbh_host_struct *puhost, usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_IDLE; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - 8U); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, 8U); - puhost->control.ep0_size = puhost->device.dev_desc.bMaxPacketSize0; - - /* issue reset */ - usb_port_reset(pudev); - - /* modify control channels configuration for maxpacket size */ - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - 0U, - 0U, - 0U, - (uint16_t)puhost->control.ep0_size); - - scd_event_handle(pudev, - puhost, - pustate, - ENUM_EVENT_SET_ADDR, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_DEV_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_dev_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_DEV_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_DEVDESC, - USB_DEVDESC_SIZE); - } - - if(USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_device_desc_parse(&puhost->device.dev_desc, pudev->host.rx_buffer, USB_DEVDESC_SIZE); - puhost->usr_cb->device_desc_available(&puhost->device.dev_desc); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_ADDR state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_addr_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_ADDR; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_addr_set(pudev, puhost,USBH_DEVICE_ADDRESS); - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(100U); - } - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - if ((void *)0 != pudev->mdelay) { - pudev->mdelay(2U); - } - puhost->device.address = USBH_DEVICE_ADDRESS; - - /* user callback for device address assigned */ - puhost->usr_cb->device_address_set(); - - /* modify control channels to update device address */ - usbh_channel_modify (pudev, - puhost->control.hc_in_num, - puhost->device.address, - 0U, - 0U, - 0U); - - usbh_channel_modify (pudev, - puhost->control.hc_out_num, - puhost->device.address, - 0U, - 0U, - 0U); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_DEV_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, - USB_CFGDESC_SIZE); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < USB_CFGDESC_SIZE; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - USB_CFGDESC_SIZE); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_FULL_CFG_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_FULL_CFG_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_full_cfg_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - - uint16_t index = 0U; - - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_FULL_CFG_DESC; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get (pudev, puhost, pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_CFGDESC, puhost->device.cfg_desc.wTotalLength); - } - - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - /* save configuration descriptor for class parsing usage */ - for (; index < puhost->device.cfg_desc.wTotalLength; index ++) { - usbh_cfg_desc[index] = pudev->host.rx_buffer[index]; - } - - /* commands successfully sent and response received */ - usbh_cfg_desc_parse (&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc, - pudev->host.rx_buffer, - puhost->device.cfg_desc.wTotalLength); - - /* User callback for configuration descriptors available */ - puhost->usr_cb->configuration_desc_available(&puhost->device.cfg_desc, - puhost->device.itf_desc, - puhost->device.ep_desc[0]); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_MFC_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_MFC_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_mfc_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_MFC_STRING_DESC; - - if (0U != puhost->device.dev_desc.iManufacturer) { - if(CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iManufacturer, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - puhost->usr_cb->manufacturer_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_PRODUCT_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->manufacturer_string("N/A"); - scd_state_move((usbh_state_handle_struct *)pustate, ENUM_GET_PRODUCT_STRING_DESC); - } -} - -/*! - \brief the handle function of ENUM_GET_PRODUCT_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_product_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_PRODUCT_STRING_DESC; - - if (0U != puhost->device.dev_desc.iProduct) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iProduct, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->product_string(local_buffer); - - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->product_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_GET_SERIALNUM_STRING_DESC, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_GET_SERIALNUM_STRING_DESC state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_get_serialnum_string_desc_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_GET_SERIALNUM_STRING_DESC; - - if (0U != puhost->device.dev_desc.iSerialNumber) { - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state) { - usbh_enum_desc_get(pudev, - puhost, - pudev->host.rx_buffer, - USB_REQTYPE_DEVICE | USB_STANDARD_REQ, - USB_STRDESC | puhost->device.dev_desc.iSerialNumber, - 0xffU); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)){ - usbh_string_desc_parse(pudev->host.rx_buffer, local_buffer, 0xffU); - - /* user callback for product string */ - puhost->usr_cb->serial_num_string(local_buffer); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } - } else { - puhost->usr_cb->serial_num_string("N/A"); - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_SET_CONFIGURATION, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_SET_CONFIGURATION state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_set_configuration_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_SET_CONFIGURATION; - - if (CTRL_IDLE == puhost->usbh_backup_state.ctrl_backup_state ) { - usbh_enum_cfg_set(pudev, puhost, (uint16_t)puhost->device.cfg_desc.bConfigurationValue); - } - - if (USBH_OK == ctrl_state_polling_fun(pudev, puhost, pustate)) { - scd_event_handle(pudev, - puhost, - pustate, - ENUN_EVENT_DEV_CONFIGURED, - pustate->usbh_current_state); - } -} - -/*! - \brief the handle function of ENUM_DEV_CONFIGURED state - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] pustate: pointer to USB state driver - \param[out] none - \retval none -*/ -static void enum_dev_configured_handle (usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - usbh_state_handle_struct *pustate) -{ - puhost->usbh_backup_state.enum_backup_state = ENUM_DEV_CONFIGURED; - scd_event_handle(pudev, puhost, pustate, GO_TO_UP_STATE_EVENT, pustate->usbh_current_state); -} - -/*! - \brief get descriptor in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] buf: buffer to store the descriptor - \param[in] ReqType: descriptor type - \param[in] ValueIdx: wValue for the GetDescriptr request - \param[in] Len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_enum_desc_get(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t *buf, - uint8_t req_type, - uint16_t value_idx, - uint16_t len) -{ - usb_setup_union *pSetup = &(puhost->control.setup); - - pSetup->b.bmRequestType = USB_DIR_IN | req_type; - pSetup->b.bRequest = USBREQ_GET_DESCRIPTOR; - pSetup->b.wValue = value_idx; - - if (USB_STRDESC == (value_idx & 0xff00U)){ - pSetup->b.wIndex = 0x0409U; - } else { - pSetup->b.wIndex = 0U; - } - - pSetup->b.wLength = len; - - puhost->control.buff = buf; - puhost->control.length = len; - -} - -/*! - \brief set address in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] device_address: the device address - \param[out] none - \retval none -*/ -void usbh_enum_addr_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint8_t device_address) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_ADDRESS; - p_setup->b.wValue = (uint16_t)device_address; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0U; - puhost->control.length = 0U; -} - -/*! - \brief set configuration in usb host enumeration stage - \param[in] pudev: pointer to USB device - \param[in] puhost: pointer to USB host - \param[in] cfg_idx: the index of the configuration - \param[out] none - \retval none -*/ -void usbh_enum_cfg_set(usb_core_handle_struct *pudev, - usbh_host_struct *puhost, - uint16_t cfg_idx) -{ - usb_setup_union *p_setup = &(puhost->control.setup); - - p_setup->b.bmRequestType = USB_DIR_OUT | USB_REQTYPE_DEVICE | USB_STANDARD_REQ; - p_setup->b.bRequest = USBREQ_SET_CONFIGURATION; - p_setup->b.wValue = cfg_idx; - p_setup->b.wIndex = 0U; - p_setup->b.wLength = 0U; - puhost->control.buff = 0; - puhost->control.length = 0U; -} - -/*! - \brief parse the device descriptor - \param[in] dev_desc: device_descriptor destinaton address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_device_desc_parse (usb_descriptor_device_struct *dev_desc, uint8_t *buf, uint16_t len) -{ - dev_desc->Header.bLength = *(uint8_t *)(buf + 0); - dev_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - dev_desc->bcdUSB = SWAPBYTE(buf + 2); - dev_desc->bDeviceClass = *(uint8_t *)(buf + 4); - dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5); - dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6); - dev_desc->bMaxPacketSize0 = *(uint8_t *)(buf + 7); - - if (len > 8U){ - /* for 1st time after device connection, host may issue only 8 bytes for device descriptor length */ - dev_desc->idVendor = SWAPBYTE(buf + 8); - dev_desc->idProduct = SWAPBYTE(buf + 10); - dev_desc->bcdDevice = SWAPBYTE(buf + 12); - dev_desc->iManufacturer = *(uint8_t *)(buf + 14); - dev_desc->iProduct = *(uint8_t *)(buf + 15); - dev_desc->iSerialNumber = *(uint8_t *)(buf + 16); - dev_desc->bNumberConfigurations = *(uint8_t *)(buf + 17); - } -} - -/*! - \brief parse the configuration descriptor - \param[in] cfg_desc: configuration descriptor address - \param[in] itf_desc: interface descriptor address - \param[in] ep_desc: endpoint descriptor address - \param[in] buf: buffer where the source descriptor is available - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_cfg_desc_parse (usb_descriptor_configuration_struct *cfg_desc, - usb_descriptor_interface_struct *itf_desc, - usb_descriptor_endpoint_struct ep_desc[][USBH_MAX_EP_NUM], - uint8_t *buf, - uint16_t len) -{ - usb_descriptor_interface_struct *pitf = NULL; - usb_descriptor_interface_struct temp_pitf; - usb_descriptor_endpoint_struct *pep = NULL; - usb_descriptor_header_struct *pdesc = (usb_descriptor_header_struct *)buf; - - uint8_t itf_ix = 0U; - uint8_t ep_ix = 0U; - uint16_t ptr = 0U; - static uint8_t prev_itf = 0U; - static uint16_t prev_ep_size = 0U; - - /* parse configuration descriptor */ - cfg_desc->Header.bLength = *(uint8_t *)(buf + 0); - cfg_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - cfg_desc->wTotalLength = SWAPBYTE(buf + 2); - cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4); - cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5); - cfg_desc->iConfiguration = *(uint8_t *)(buf + 6); - cfg_desc->bmAttributes = *(uint8_t *)(buf + 7); - cfg_desc->bMaxPower = *(uint8_t *)(buf + 8); - - if (len > USB_CFGDESC_SIZE) { - ptr = USB_CFG_DESC_LEN; - - if (cfg_desc->bNumInterfaces <= USBH_MAX_INTERFACES_NUM) { - pitf = (usb_descriptor_interface_struct *)0; - - for (; ptr < cfg_desc->wTotalLength; ) { - pdesc = usbh_next_desc_get((uint8_t *)pdesc, &ptr); - - if (USB_DESCTYPE_INTERFACE == pdesc->bDescriptorType) { - itf_ix = *((uint8_t *)pdesc + 2U); - pitf = &itf_desc[itf_ix]; - - if (*((uint8_t *)pdesc + 3U) < 3U) { - usbh_interface_desc_parse (&temp_pitf, (uint8_t *)pdesc); - - /* parse endpoint descriptors relative to the current interface */ - if (temp_pitf.bNumEndpoints <= USBH_MAX_EP_NUM) { - for (ep_ix = 0U; ep_ix < temp_pitf.bNumEndpoints;) { - pdesc = usbh_next_desc_get((void* )pdesc, &ptr); - - if (USB_DESCTYPE_ENDPOINT == pdesc->bDescriptorType) { - pep = &ep_desc[itf_ix][ep_ix]; - - if (prev_itf != itf_ix) { - prev_itf = itf_ix; - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } else { - if (prev_ep_size > SWAPBYTE((uint8_t *)pdesc + 4)) { - break; - } else { - usbh_interface_desc_parse (pitf, (uint8_t *)&temp_pitf); - } - } - - usbh_endpoint_desc_parse (pep, (uint8_t *)pdesc); - prev_ep_size = SWAPBYTE((uint8_t *)pdesc + 4); - ep_ix++; - } - } - } - } - } - } - } - - prev_ep_size = 0U; - prev_itf = 0U; - } -} - -/*! - \brief parse the interface descriptor - \param[in] itf_desc: interface descriptor destination - \param[in] buf: buffer where the descriptor data is available - \param[out] none - \retval none -*/ -void usbh_interface_desc_parse (usb_descriptor_interface_struct *itf_desc, uint8_t *buf) -{ - itf_desc->Header.bLength = *(uint8_t *)(buf + 0); - itf_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - itf_desc->bInterfaceNumber = *(uint8_t *)(buf + 2); - itf_desc->bAlternateSetting = *(uint8_t *)(buf + 3); - itf_desc->bNumEndpoints = *(uint8_t *)(buf + 4); - itf_desc->bInterfaceClass = *(uint8_t *)(buf + 5); - itf_desc->bInterfaceSubClass = *(uint8_t *)(buf + 6); - itf_desc->bInterfaceProtocol = *(uint8_t *)(buf + 7); - itf_desc->iInterface = *(uint8_t *)(buf + 8); -} - -/*! - \brief parse the endpoint descriptor - \param[in] ep_desc: endpoint descriptor destination address - \param[in] buf: buffer where the parsed descriptor stored - \param[out] none - \retval none -*/ -void usbh_endpoint_desc_parse (usb_descriptor_endpoint_struct *ep_desc, uint8_t *buf) -{ - ep_desc->Header.bLength = *(uint8_t *)(buf + 0); - ep_desc->Header.bDescriptorType = *(uint8_t *)(buf + 1); - ep_desc->bEndpointAddress = *(uint8_t *)(buf + 2); - ep_desc->bmAttributes = *(uint8_t *)(buf + 3); - ep_desc->wMaxPacketSize = SWAPBYTE(buf + 4); - ep_desc->bInterval = *(uint8_t *)(buf + 6); -} - -/*! - \brief parse the string descriptor - \param[in] psrc: source pointer containing the descriptor data - \param[in] pdest: destination address pointer - \param[in] len: length of the descriptor - \param[out] none - \retval none -*/ -void usbh_string_desc_parse (uint8_t* psrc, uint8_t* pdest, uint16_t len) -{ - uint16_t strlength; - uint16_t idx; - - /* the unicode string descriptor is not null-terminated. the string length is - computed by substracting two from the value of the first byte of the descriptor. - */ - - /* check which is lower size, the size of string or the length of bytes read from the device */ - - if (USB_DESCTYPE_STRING == psrc[1]){ - /* make sure the descriptor is string type */ - - /* psrc[0] contains size of descriptor, subtract 2 to get the length of string */ - strlength = ((((uint16_t)psrc[0] - 2U) <= len) ? ((uint16_t)psrc[0] - 2U) : len); - psrc += 2; /* adjust the offset ignoring the string len and descriptor type */ - - for (idx = 0U; idx < strlength; idx += 2U) { - /* copy only the string and ignore the unicode id, hence add the src */ - *pdest = psrc[idx]; - pdest++; - } - - *pdest = 0U; /* mark end of string */ - } -} - -/*! - \brief get the next descriptor header - \param[in] pbuf: pointer to buffer where the cfg descriptor is available - \param[in] ptr: data popinter inside the configuration descriptor - \param[out] none - \retval next descriptor header -*/ -usb_descriptor_header_struct *usbh_next_desc_get (uint8_t *pbuf, uint16_t *ptr) -{ - uint8_t len = ((usb_descriptor_header_struct *)pbuf)->bLength; - - usb_descriptor_header_struct *pnext; - - *ptr += len; - - pnext = (usb_descriptor_header_struct *)((uint8_t *)pbuf + len); - - return(pnext); -} - diff --git a/bsp/gd32350r-eval/Libraries/SConscript b/bsp/gd32350r-eval/Libraries/SConscript deleted file mode 100644 index a1a55b196f..0000000000 --- a/bsp/gd32350r-eval/Libraries/SConscript +++ /dev/null @@ -1,33 +0,0 @@ -import rtconfig -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. - -src = Glob('GD32F3x0_standard_peripheral/Source/*.c') -src += [cwd + '/CMSIS/GD/GD32F3x0/Source/system_gd32f3x0.c'] - -#add for startup script -if rtconfig.PLATFORM in ['gcc']: - src += [cwd + '/CMSIS/GD/GD32F3x0/Source/GCC/startup_gd32f3x0.S'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [cwd + '/CMSIS/GD/GD32F3x0/Source/ARM/startup_gd32f3x0.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += [cwd + '/CMSIS/GD/GD32F3x0/Source/IAR/startup_gd32f3x0.s'] - -path = [ - cwd + '/CMSIS/GD/GD32F3x0/Include', - cwd + '/CMSIS', - cwd + '/GD32F3x0_standard_peripheral/Include',] - -if GetDepend(['RT_USING_BSP_USB']): - path += [cwd + '/GD32F4xx_usb_driver/Include'] - src += [cwd + '/GD32F4xx_usb_driver/Source'] - -CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F350'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/gd32350r-eval/README.md b/bsp/gd32350r-eval/README.md deleted file mode 100644 index 8f2a434511..0000000000 --- a/bsp/gd32350r-eval/README.md +++ /dev/null @@ -1,55 +0,0 @@ -# GD32350R-EVAL - -## 简介 - -GD32350R-EVAL是-兆易创新推出的一款GD32F350系列的评估æ¿ï¼Œæ¿è½½èµ„æºä¸»è¦å¦‚下： - -| 硬件 | æè¿° | -| --------- | ------------- | -| èŠ¯ç‰‡åž‹å· | GD32F350R8T6 | -| CPU | ARM Cortex M4 | -| 主频 | 108M | -| 片内SRAM | 16K | -| 片内FLASH | 64K | - -## 编译说明 - -GD32450Z-EVALæ¿çº§åŒ…支æŒMDK5å¼€å‘环境以下是具体版本信æ¯ï¼š - -| IDE/编译器 | 已测试版本 | -| ---------- | ---------- | -| MDK5 | MDK524a | - -## 烧写åŠæ‰§è¡Œ - -供电方å¼ï¼šå¼€å‘æ¿ä½¿ç”¨ Mini USB 接å£æˆ–者 DC-005 连接器æä¾› 5V 电æºã€‚ - -下载程åºï¼šä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿éœ€è¦ä¸€å¥— JLink 或者使用 GD-Link 工具。 - -串å£è¿žæŽ¥ï¼šä½¿ç”¨ä¸²å£çº¿è¿žæŽ¥åˆ°COM1(UART0)，或者使用USB转TTL模å—连接PA9(MCU TX)å’ŒPA10(MCU RX)。 - -### è¿è¡Œç»“æžœ - -如果编译 & 烧写无误，当å¤ä½è®¾å¤‡åŽï¼Œä¼šåœ¨ä¸²å£ä¸Šçœ‹åˆ°RT-Threadçš„å¯åŠ¨logoä¿¡æ¯ï¼š - -```bash - \ | / -- RT - Thread Operating System - / | \ 4.0.4 build Jun 21 2021 - 2006 - 2021 Copyright by rt-thread team - - - -msh > -``` -## 驱动支æŒæƒ…况åŠè®¡åˆ’ - -| 驱动 | 支æŒæƒ…况 | 备注 | -| --------- | -------- | :------------------------: | -| UART | æ”¯æŒ | UART0~1 | -| GPIO | æ”¯æŒ | ALL | - -## è”ç³»äººä¿¡æ¯ - -维护人：[RiceChen](https://gitee.com/RiceChen0) -邮箱：980307037@qq.com diff --git a/bsp/gd32350r-eval/SConscript b/bsp/gd32350r-eval/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/gd32350r-eval/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32350r-eval/SConstruct b/bsp/gd32350r-eval/SConstruct deleted file mode 100644 index 644ffee2ae..0000000000 --- a/bsp/gd32350r-eval/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread-gd32f3x0.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32350r-eval/applications/SConscript b/bsp/gd32350r-eval/applications/SConscript deleted file mode 100644 index 9bb9abae89..0000000000 --- a/bsp/gd32350r-eval/applications/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -from building import * -import os - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -list = os.listdir(cwd) -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - group = group + SConscript(os.path.join(item, 'SConscript')) - -Return('group') diff --git a/bsp/gd32350r-eval/applications/main.c b/bsp/gd32350r-eval/applications/main.c deleted file mode 100644 index 3aa60cf2b2..0000000000 --- a/bsp/gd32350r-eval/applications/main.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-06-21 RiceChen the first version - */ - -#include -#include -#include "rtdevice.h" - -int main(void) -{ - rt_kprintf("\n\n\n"); - - return 0; -} diff --git a/bsp/gd32350r-eval/drivers/SConscript b/bsp/gd32350r-eval/drivers/SConscript deleted file mode 100644 index f40845bdf7..0000000000 --- a/bsp/gd32350r-eval/drivers/SConscript +++ /dev/null @@ -1,24 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drivers. -src = Split(""" -board.c -""") - -CPPPATH = [cwd] - -# add pin drivers. -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -# add uart drivers. -if GetDepend('RT_USING_SERIAL'): - src += ['drv_usart.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32350r-eval/drivers/board.c b/bsp/gd32350r-eval/drivers/board.c deleted file mode 100644 index e07bbfc45c..0000000000 --- a/bsp/gd32350r-eval/drivers/board.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - */ -#include -#include -#include - -#include -#include -#include - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while (1) - { - } - /* USER CODE END Error_Handler */ -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -char heap[1024 *16]; -/** - * This function will initial GD32 board. - */ -void rt_hw_board_init() -{ - /* NVIC Configuration */ -#define NVIC_VTOR_MASK 0x3FFFFF80 -#ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); -#else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); -#endif - - SystemClock_Config(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef BSP_USING_SDRAM - rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); -#else - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/gd32350r-eval/drivers/board.h b/bsp/gd32350r-eval/drivers/board.h deleted file mode 100644 index 05d3c7e972..0000000000 --- a/bsp/gd32350r-eval/drivers/board.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include - -#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */ -#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#ifdef __ICCARM__ -// Use *.icf ram symbal, to avoid hardcode. -extern char __ICFEDIT_region_RAM_end__; -#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ -#else -#define GD32_SRAM_SIZE 16 -#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) -#endif - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif - -#define HEAP_END GD32_SRAM_END - -#endif - -//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32350r-eval/drivers/drv_gpio.c b/bsp/gd32350r-eval/drivers/drv_gpio.c deleted file mode 100644 index a748a0a7d4..0000000000 --- a/bsp/gd32350r-eval/drivers/drv_gpio.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-06-20 RiceChen the first version - */ - -#include -#include - -#ifdef RT_USING_PIN - -#include "drv_gpio.h" - -static const struct pin_index pins[] = -{ - GD32_PIN(1, A, 0), - GD32_PIN(2, A, 1), - GD32_PIN(3, A, 2), - GD32_PIN(4, A, 3), - GD32_PIN(5, A, 4), - GD32_PIN(6, A, 5), - GD32_PIN(7, A, 6), - GD32_PIN(8, A, 7), - GD32_PIN(9, A, 8), - GD32_PIN(10, A, 9), - GD32_PIN(11, A, 10), - GD32_PIN(12, A, 11), - GD32_PIN(13, A, 12), - GD32_PIN(14, A, 13), - GD32_PIN(15, A, 14), - GD32_PIN(16, A, 15), - GD32_PIN(17, B, 0), - GD32_PIN(18, B, 1), - GD32_PIN(19, B, 2), - GD32_PIN(20, B, 3), - GD32_PIN(21, B, 4), - GD32_PIN(22, B, 5), - GD32_PIN(23, B, 6), - GD32_PIN(24, B, 7), - GD32_PIN(25, B, 8), - GD32_PIN(26, B, 9), - GD32_PIN(27, B, 10), - GD32_PIN(28, B, 11), - GD32_PIN(29, B, 12), - GD32_PIN(30, B, 13), - GD32_PIN(31, B, 14), - GD32_PIN(32, B, 15), - GD32_PIN(33, C, 0), - GD32_PIN(34, C, 1), - GD32_PIN(35, C, 2), - GD32_PIN(36, C, 3), - GD32_PIN(37, C, 4), - GD32_PIN(38, C, 5), - GD32_PIN(39, C, 6), - GD32_PIN(40, C, 7), - GD32_PIN(41, C, 8), - GD32_PIN(42, C, 9), - GD32_PIN(43, C, 10), - GD32_PIN(44, C, 11), - GD32_PIN(45, C, 12), - GD32_PIN(46, C, 13), - GD32_PIN(47, C, 14), - GD32_PIN(48, C, 15), - GD32_PIN(51, D, 2), - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN(65, F, 0), - GD32_PIN(66, F, 1), - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN(69, F, 4), - GD32_PIN(70, F, 5), - GD32_PIN(71, F, 6), - GD32_PIN(72, F, 7), - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, - GD32_PIN_DEFAULT, -}; - -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_1_IRQn}, - {GPIO_PIN_1, EXTI0_1_IRQn}, - {GPIO_PIN_2, EXTI2_3_IRQn}, - {GPIO_PIN_3, EXTI2_3_IRQn}, - {GPIO_PIN_4, EXTI4_15_IRQn}, - {GPIO_PIN_5, EXTI4_15_IRQn}, - {GPIO_PIN_6, EXTI4_15_IRQn}, - {GPIO_PIN_7, EXTI4_15_IRQn}, - {GPIO_PIN_8, EXTI4_15_IRQn}, - {GPIO_PIN_9, EXTI4_15_IRQn}, - {GPIO_PIN_10, EXTI4_15_IRQn}, - {GPIO_PIN_11, EXTI4_15_IRQn}, - {GPIO_PIN_12, EXTI4_15_IRQn}, - {GPIO_PIN_13, EXTI4_15_IRQn}, - {GPIO_PIN_14, EXTI4_15_IRQn}, - {GPIO_PIN_15, EXTI4_15_IRQn}, -}; - -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(rt_uint8_t pin) -{ - const struct pin_index *index; - - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - - return index; -}; - -void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) -{ - const struct pin_index *index = RT_NULL; - rt_uint32_t pin_mode = 0, pin_pupd = 0, pin_odpp = 0; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* GPIO Periph clock enable */ - rcu_periph_clock_enable(index->clk); - pin_mode = GPIO_MODE_OUTPUT; - - switch(mode) - { - case PIN_MODE_OUTPUT: - /* output setting */ - pin_mode = GPIO_MODE_OUTPUT; - pin_pupd = GPIO_PUPD_NONE; - pin_odpp = GPIO_OTYPE_PP; - break; - case PIN_MODE_OUTPUT_OD: - /* output setting: od. */ - pin_mode = GPIO_MODE_OUTPUT; - pin_pupd = GPIO_PUPD_NONE; - pin_odpp = GPIO_OTYPE_OD; - break; - case PIN_MODE_INPUT: - /* input setting: not pull. */ - pin_mode = GPIO_MODE_INPUT; - pin_pupd = GPIO_PUPD_PULLUP | GPIO_PUPD_PULLDOWN; - break; - case PIN_MODE_INPUT_PULLUP: - /* input setting: pull up. */ - pin_mode = GPIO_MODE_INPUT; - pin_pupd = GPIO_PUPD_PULLUP; - break; - case PIN_MODE_INPUT_PULLDOWN: - /* input setting: pull down. */ - pin_mode = GPIO_MODE_INPUT; - pin_pupd = GPIO_PUPD_PULLDOWN; - break; - default: - break; - } - - gpio_mode_set(index->gpio_periph, pin_mode, pin_pupd, index->pin); - if(pin_mode == GPIO_MODE_OUTPUT) - { - gpio_output_options_set(index->gpio_periph, pin_odpp, GPIO_OSPEED_50MHZ, index->pin); - } -} - -void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) -{ - const struct pin_index *index = RT_NULL; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); -} - -rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin) -{ - rt_int8_t value = PIN_LOW; - const struct pin_index *index = RT_NULL; - - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - - value = gpio_input_bit_get(index->gpio_periph, index->pin); - return value; -} - -rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) -{ - rt_uint8_t i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { - return i; - } - } - return -1; -} - -rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) -{ - rt_int32_t map_index = bit2bitno(pinbit); - if (map_index < 0 || map_index >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[map_index]; -}; - -rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index = RT_NULL; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == pin && - pin_irq_hdr_tab[hdr_index].hdr == hdr && - pin_irq_hdr_tab[hdr_index].mode == mode && - pin_irq_hdr_tab[hdr_index].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[hdr_index].pin != -1) - { - rt_hw_interrupt_enable(level); - return -RT_EFULL; - } - pin_irq_hdr_tab[hdr_index].pin = pin; - pin_irq_hdr_tab[hdr_index].hdr = hdr; - pin_irq_hdr_tab[hdr_index].mode = mode; - pin_irq_hdr_tab[hdr_index].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin) -{ - const struct pin_index *index = RT_NULL; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[hdr_index].pin = -1; - pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; - pin_irq_hdr_tab[hdr_index].mode = 0; - pin_irq_hdr_tab[hdr_index].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t hdr_index = -1; - exti_trig_type_enum trigger_mode; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - - if (enabled == PIN_IRQ_ENABLE) - { - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - - irqmap = &pin_irq_map[hdr_index]; - - switch (pin_irq_hdr_tab[hdr_index].mode) - { - case PIN_IRQ_MODE_RISING: - trigger_mode = EXTI_TRIG_RISING; - break; - case PIN_IRQ_MODE_FALLING: - trigger_mode = EXTI_TRIG_FALLING; - break; - case PIN_IRQ_MODE_RISING_FALLING: - trigger_mode = EXTI_TRIG_BOTH; - break; - default: - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - - rcu_periph_clock_enable(RCU_CFGCMP); - - /* enable and set interrupt priority */ - nvic_irq_enable(irqmap->irqno, 5U, 0U); - - /* connect EXTI line to GPIO pin */ - syscfg_exti_line_config(index->port_src, index->pin_src); - - /* configure EXTI line */ - exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); - exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return -RT_EINVAL; - } - nvic_irq_disable(irqmap->irqno); - } - else - { - return -RT_EINVAL; - } - - return RT_EOK; -} - -const static struct rt_pin_ops gd32_pin_ops = -{ - gd32_pin_mode, - gd32_pin_write, - gd32_pin_read, - gd32_pin_attach_irq, - gd32_pin_detach_irq, - gd32_pin_irq_enable, - RT_NULL, -}; - -rt_inline void pin_irq_hdr(int irqno) -{ - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) -{ - if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) - { - pin_irq_hdr(exti_line); - exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } -} - -void EXTI0_1_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(0); - GD32_GPIO_EXTI_IRQHandler(1); - rt_interrupt_leave(); -} - -void EXTI2_3_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(2); - GD32_GPIO_EXTI_IRQHandler(3); - rt_interrupt_leave(); -} - -void EXTI4_15_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(4); - GD32_GPIO_EXTI_IRQHandler(5); - GD32_GPIO_EXTI_IRQHandler(6); - GD32_GPIO_EXTI_IRQHandler(7); - GD32_GPIO_EXTI_IRQHandler(8); - GD32_GPIO_EXTI_IRQHandler(9); - GD32_GPIO_EXTI_IRQHandler(10); - GD32_GPIO_EXTI_IRQHandler(11); - GD32_GPIO_EXTI_IRQHandler(12); - GD32_GPIO_EXTI_IRQHandler(13); - GD32_GPIO_EXTI_IRQHandler(14); - GD32_GPIO_EXTI_IRQHandler(15); - rt_interrupt_leave(); -} - -int rt_hw_pin_init(void) -{ - int result; - - result = rt_device_pin_register("pin", &gd32_pin_ops, RT_NULL); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -#endif diff --git a/bsp/gd32350r-eval/drivers/drv_gpio.h b/bsp/gd32350r-eval/drivers/drv_gpio.h deleted file mode 100644 index f3e750970d..0000000000 --- a/bsp/gd32350r-eval/drivers/drv_gpio.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-06-20 RiceChen the first version - */ - -#ifndef __DRV_GPIO_H__ -#define __DRV_GPIO_H__ - -#include "gd32f3x0.h" -#include "gd32f3x0_exti.h" - -#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \ - GPIO##port, GPIO_PIN_##pin, \ - EXTI_SOURCE_GPIO##port, \ - EXTI_SOURCE_PIN##pin} -#define GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} - -struct pin_index -{ - rt_int16_t index; - rcu_periph_enum clk; - rt_uint32_t gpio_periph; - rt_uint32_t pin; - rt_uint8_t port_src; - rt_uint8_t pin_src; -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; - -#endif diff --git a/bsp/gd32350r-eval/drivers/drv_usart.c b/bsp/gd32350r-eval/drivers/drv_usart.c deleted file mode 100644 index 254b24a093..0000000000 --- a/bsp/gd32350r-eval/drivers/drv_usart.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-06-21 RiceChen the first version - */ - - -#include - -#ifdef RT_USING_SERIAL - -#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) -#error "Please define at least one UARTx" -#endif - -#include "drv_usart.h" - -static struct gd32_usart_config usart_config[] = -{ -#ifdef BSP_USING_UART0 - UART0_BUS_CONFIG, -#endif -#ifdef BSP_USING_UART1 - UART1_BUS_CONFIG, -#endif -}; - -static struct gd32_usart_bus usart_obj[sizeof(usart_config) / sizeof(usart_config[0])]; - -void gd32_usart_gpio_init(struct gd32_usart_bus *bus) -{ - rcu_periph_clock_enable(bus->config->per_clk); - rcu_periph_clock_enable(bus->config->tx_gpio_clk); - rcu_periph_clock_enable(bus->config->rx_gpio_clk); - - gpio_af_set(bus->config->tx_port, GPIO_AF_1, bus->config->tx_pin); - gpio_af_set(bus->config->rx_port, GPIO_AF_1, bus->config->rx_pin); - - gpio_mode_set(bus->config->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, bus->config->tx_pin); - gpio_output_options_set(bus->config->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, bus->config->tx_pin); - - gpio_mode_set(bus->config->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, bus->config->rx_pin); - gpio_output_options_set(bus->config->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, bus->config->rx_pin); - - NVIC_SetPriority(bus->config->irqn, 0); - NVIC_EnableIRQ(bus->config->irqn); - usart_deinit(bus->config->periph); -} - -rt_err_t gd32_usart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct gd32_usart_bus *bus = RT_NULL; - - bus = (struct gd32_usart_bus *)serial->parent.user_data; - - gd32_usart_gpio_init(bus); - - usart_baudrate_set(bus->config->periph, cfg->baud_rate); - - switch (cfg->data_bits) - { - case DATA_BITS_9: - usart_word_length_set(bus->config->periph, USART_WL_9BIT); - break; - - default: - usart_word_length_set(bus->config->periph, USART_WL_8BIT); - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - usart_stop_bit_set(bus->config->periph, USART_STB_2BIT); - break; - default: - usart_stop_bit_set(bus->config->periph, USART_STB_1BIT); - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - usart_parity_config(bus->config->periph, USART_PM_ODD); - break; - case PARITY_EVEN: - usart_parity_config(bus->config->periph, USART_PM_EVEN); - break; - default: - usart_parity_config(bus->config->periph, USART_PM_NONE); - break; - } - - usart_receive_config(bus->config->periph, USART_RECEIVE_ENABLE); - usart_transmit_config(bus->config->periph, USART_TRANSMIT_ENABLE); - usart_enable(bus->config->periph); - - return RT_EOK; -} - -rt_err_t gd32_usart_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct gd32_usart_bus *bus = RT_NULL; - - bus = (struct gd32_usart_bus *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(bus->config->irqn); - /* disable interrupt */ - usart_interrupt_disable(bus->config->periph, USART_INT_RBNE); - - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(bus->config->irqn); - /* enable interrupt */ - usart_interrupt_enable(bus->config->periph, USART_INT_RBNE); - break; - } - - return RT_EOK; -} - -int gd32_usart_putc(struct rt_serial_device *serial, char c) -{ - struct gd32_usart_bus *bus = RT_NULL; - - bus = (struct gd32_usart_bus *)serial->parent.user_data; - - usart_data_transmit(bus->config->periph, c); - while((usart_flag_get(bus->config->periph, USART_FLAG_TC) == RESET)); - - return 1; -} - -int gd32_usart_getc(struct rt_serial_device *serial) -{ - int ch; - struct gd32_usart_bus *bus = RT_NULL; - - bus = (struct gd32_usart_bus *)serial->parent.user_data; - - ch = -1; - if (usart_flag_get(bus->config->periph, USART_FLAG_RBNE) != RESET) - ch = usart_data_receive(bus->config->periph); - return ch; -} - -rt_size_t gd32_usart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) -{ - return RT_EOK; -} - -static struct rt_uart_ops usart_ops = -{ - gd32_usart_configure, - gd32_usart_control, - gd32_usart_putc, - gd32_usart_getc, - gd32_usart_dma_transmit, -}; - -static void uart_isr(rt_uint32_t periph) -{ - int obj_num = 0; - struct gd32_usart_bus *bus = RT_NULL; - - obj_num = sizeof(usart_config) / sizeof(usart_config[0]); - - for(int i = 0; i < obj_num; i++) - { - if(usart_obj[i].config->periph == periph) - { - bus = &usart_obj[i]; - break; - } - } - - if(bus != RT_NULL) - { - if ((usart_interrupt_flag_get(bus->config->periph, USART_INT_FLAG_RBNE) != RESET) && - (usart_flag_get(bus->config->periph, USART_FLAG_RBNE) != RESET)) - { - rt_hw_serial_isr(&bus->serial, RT_SERIAL_EVENT_RX_IND); - /* Clear RXNE interrupt flag */ - usart_flag_clear(bus->config->periph, USART_FLAG_RBNE); - } - } -} - -#ifdef BSP_USING_UART0 -void USART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(USART0); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -#ifdef BSP_USING_UART1 -void USART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(USART1); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -int rt_hw_usart_init(void) -{ - int obj_num = 0; - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - - obj_num = sizeof(usart_config) / sizeof(usart_config[0]); - - for(int i = 0; i < obj_num; i++) - { - usart_obj[i].serial.ops = &usart_ops; - usart_obj[i].serial.config = config; - usart_obj[i].config = &usart_config[i]; - - /* register UART device */ - rt_hw_serial_register(&usart_obj[i].serial, - usart_obj[i].config->dev_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&usart_obj[i]); - } - - return RT_EOK; -} -INIT_BOARD_EXPORT(rt_hw_usart_init); - -#endif diff --git a/bsp/gd32350r-eval/drivers/drv_usart.h b/bsp/gd32350r-eval/drivers/drv_usart.h deleted file mode 100644 index 10561646a7..0000000000 --- a/bsp/gd32350r-eval/drivers/drv_usart.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-06-20 RiceChen the first version - */ - -#ifndef __DRV_USART_H__ -#define __DRV_USART_H__ - -#include -#include -#include "gd32f3x0.h" -#include "gd32f3x0_usart.h" -#include "gd32f3x0_exti.h" - -struct gd32_usart_config -{ - char *dev_name; - rt_uint32_t periph; - IRQn_Type irqn; - rcu_periph_enum per_clk; - rcu_periph_enum tx_gpio_clk; - rcu_periph_enum rx_gpio_clk; - rt_uint32_t tx_port; - rt_uint32_t tx_pin; - rt_uint32_t rx_port; - rt_uint32_t rx_pin; -}; - -struct gd32_usart_bus -{ - struct rt_serial_device serial; - struct gd32_usart_config *config; -}; - -#ifdef BSP_USING_UART0 -#define UART0_BUS_CONFIG \ - { \ - .dev_name = "uart0", \ - .periph = USART0, \ - .irqn = USART0_IRQn, \ - .per_clk = RCU_USART0, \ - .tx_gpio_clk = RCU_GPIOA, \ - .rx_gpio_clk = RCU_GPIOA, \ - .tx_port = GPIOA, \ - .tx_pin = GPIO_PIN_9, \ - .rx_port = GPIOA, \ - .rx_pin = GPIO_PIN_10, \ - } -#endif /* BSP_USING_UART0 */ - -#ifdef BSP_USING_UART1 -#define UART1_BUS_CONFIG \ - { \ - .dev_name = "uart1", \ - .periph = USART1, \ - .irqn = USART1_IRQn, \ - .per_clk = RCU_USART1, \ - .tx_gpio_clk = RCU_GPIOA, \ - .rx_gpio_clk = RCU_GPIOA, \ - .tx_port = GPIOA, \ - .tx_pin = GPIO_PIN_2, \ - .rx_port = GPIOA, \ - .rx_pin = GPIO_PIN_3, \ - } -#endif /* BSP_USING_UART1 */ - -#endif diff --git a/bsp/gd32350r-eval/drivers/gd32f3x0_libopt.h b/bsp/gd32350r-eval/drivers/gd32f3x0_libopt.h deleted file mode 100644 index 7192e4fb12..0000000000 --- a/bsp/gd32350r-eval/drivers/gd32f3x0_libopt.h +++ /dev/null @@ -1,66 +0,0 @@ -/*! - \file gd32f3x0_libopt.h - \brief library optional for gd32f3x0 - - \version 2017-06-28, V1.0.0, demo for GD32F3x0 - \version 2019-06-01, V2.0.0, demo for GD32F3x0 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F3X0_LIBOPT_H -#define GD32F3X0_LIBOPT_H - -#include "gd32f3x0_adc.h" -#include "gd32f3x0_crc.h" -#include "gd32f3x0_ctc.h" -#include "gd32f3x0_dbg.h" -#include "gd32f3x0_dma.h" -#include "gd32f3x0_exti.h" -#include "gd32f3x0_fmc.h" -#include "gd32f3x0_gpio.h" -#include "gd32f3x0_syscfg.h" -#include "gd32f3x0_i2c.h" -#include "gd32f3x0_fwdgt.h" -#include "gd32f3x0_pmu.h" -#include "gd32f3x0_rcu.h" -#include "gd32f3x0_rtc.h" -#include "gd32f3x0_spi.h" -#include "gd32f3x0_timer.h" -#include "gd32f3x0_usart.h" -#include "gd32f3x0_wwdgt.h" -#include "gd32f3x0_misc.h" -#include "gd32f3x0_tsi.h" - -#ifdef GD32F350 -#include "gd32f3x0_cec.h" -#include "gd32f3x0_cmp.h" -#include "gd32f3x0_dac.h" -#endif /* GD32F350 */ - -#endif /* GD32F3X0_LIBOPT_H */ diff --git a/bsp/gd32350r-eval/gd32_rom.icf b/bsp/gd32350r-eval/gd32_rom.icf deleted file mode 100644 index 80461d6dfa..0000000000 --- a/bsp/gd32350r-eval/gd32_rom.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x082FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -export symbol __ICFEDIT_region_RAM_end__; - -define symbol __region_RAM1_start__ = 0x10000000; -define symbol __region_RAM1_end__ = 0x1000FFFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; diff --git a/bsp/gd32350r-eval/gd32_rom.ld b/bsp/gd32350r-eval/gd32_rom.ld deleted file mode 100644 index ec1c65c34e..0000000000 --- a/bsp/gd32350r-eval/gd32_rom.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linker script for GD32F4xx with GNU ld - * bernard.xiong 2009-10-14 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 3072k /* 3072KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/gd32350r-eval/gd32_rom.sct b/bsp/gd32350r-eval/gd32_rom.sct deleted file mode 100644 index a4fc4f2765..0000000000 --- a/bsp/gd32350r-eval/gd32_rom.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00200000 { ; load region size_region - ER_IROM1 0x08000000 0x00200000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00004000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/gd32350r-eval/project.uvoptx b/bsp/gd32350r-eval/project.uvoptx deleted file mode 100644 index 96b3c092db..0000000000 --- a/bsp/gd32350r-eval/project.uvoptx +++ /dev/null @@ -1,190 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f30x - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - CMSIS_AGDI - -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0.FLM -FS08000000 -FL020000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F3x0 -FL010000 -FS08000000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM) - - - 0 - JL2CM3 - -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/gd32350r-eval/project.uvprojx b/bsp/gd32350r-eval/project.uvprojx deleted file mode 100644 index 94e5527266..0000000000 --- a/bsp/gd32350r-eval/project.uvprojx +++ /dev/null @@ -1,886 +0,0 @@ - - - 2.1 -
### uVision Project, (C) Keil Software
- - - rt-thread_gd32f30x - 0x4 - ARM-ADS - 0 - - - GD32F350R8 - GigaDevice - GigaDevice.GD32F3x0_DFP.2.0.0 - http://gd32mcu.21ic.com/data/documents/yingyongruanjian/ - IRAM(0x20000000,0x04000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0 -FS08000000 -FL010000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM)) - 0 - $$Device:GD32F350R8$Device\Include\gd32f3x0.h - - - - - - - - - - $$Device:GD32F350R8$SVD\GD32F3x0.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-gd32f3x0 - 1 - 0 - 1 - 1 - 0 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 1 - 0x8000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x20000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, USE_STDPERIPH_DRIVER, RT_USING_LIBC, GD32F350, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__ - - ..\..\libcpu\arm\cortex-m4;drivers;..\..\include;..\..\components\libc\compilers\common\extension;..\..\components\drivers\include;Libraries\CMSIS\GD\GD32F3x0\Include;Libraries\GD32F3x0_standard_peripheral\Include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\libc\posix\ipc;..\..\libcpu\arm\common;..\..\components\libc\compilers\common\extension\fcntl\octal;Libraries\CMSIS;..\..\components\finsh;..\..\components\libc\posix\io\epoll;..\..\components\libc\compilers\common\include;..\..\components\libc\posix\io\eventfd;applications;..\..\components\libc\posix\io\poll;..\..\components\drivers\include;. - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - .\gd32_rom.ld - - - - - - - - - - - Applications - - - main.c - 1 - applications\main.c - - - - - Compiler - - - syscall_mem.c - 1 - ..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\components\libc\compilers\common\cctype.c - - - - - cstdlib.c - 1 - ..\..\components\libc\compilers\common\cstdlib.c - - - - - cstring.c - 1 - ..\..\components\libc\compilers\common\cstring.c - - - - - ctime.c - 1 - ..\..\components\libc\compilers\common\ctime.c - - - - - cunistd.c - 1 - ..\..\components\libc\compilers\common\cunistd.c - - - - - cwchar.c - 1 - ..\..\components\libc\compilers\common\cwchar.c - - - - - CPU - - - div0.c - 1 - ..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\libcpu\arm\common\showmem.c - - - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S - - - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c - - - - - DeviceDrivers - - - device.c - 1 - ..\..\components\drivers\core\device.c - - - - - completion.c - 1 - ..\..\components\drivers\ipc\completion.c - - - - - dataqueue.c - 1 - ..\..\components\drivers\ipc\dataqueue.c - - - - - pipe.c - 1 - ..\..\components\drivers\ipc\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\components\drivers\ipc\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\components\drivers\ipc\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\components\drivers\ipc\waitqueue.c - - - - - workqueue.c - 1 - ..\..\components\drivers\ipc\workqueue.c - - - - - pin.c - 1 - ..\..\components\drivers\misc\pin.c - - - - - serial.c - 1 - ..\..\components\drivers\serial\serial.c - - - - - Drivers - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_usart.c - 1 - drivers\drv_usart.c - - - - - board.c - 1 - drivers\board.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - msh_parse.c - 1 - ..\..\components\finsh\msh_parse.c - - - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler_up.c - 1 - ..\..\src\scheduler_up.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - Libraries - - - system_gd32f3x0.c - 1 - Libraries\CMSIS\GD\GD32F3x0\Source\system_gd32f3x0.c - - - - - gd32f3x0_pmu.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_pmu.c - - - - - gd32f3x0_crc.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_crc.c - - - - - gd32f3x0_spi.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_spi.c - - - - - gd32f3x0_dbg.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_dbg.c - - - - - startup_gd32f3x0.s - 2 - Libraries\CMSIS\GD\GD32F3x0\Source\ARM\startup_gd32f3x0.s - - - - - gd32f3x0_gpio.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_gpio.c - - - - - gd32f3x0_dac.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_dac.c - - - - - gd32f3x0_ctc.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_ctc.c - - - - - gd32f3x0_dma.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_dma.c - - - - - gd32f3x0_fwdgt.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_fwdgt.c - - - - - gd32f3x0_adc.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_adc.c - - - - - gd32f3x0_i2c.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_i2c.c - - - - - gd32f3x0_syscfg.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_syscfg.c - - - - - gd32f3x0_fmc.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_fmc.c - - - - - gd32f3x0_usart.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_usart.c - - - - - gd32f3x0_exti.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_exti.c - - - - - gd32f3x0_timer.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_timer.c - - - - - gd32f3x0_misc.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_misc.c - - - - - gd32f3x0_cec.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_cec.c - - - - - gd32f3x0_cmp.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_cmp.c - - - - - gd32f3x0_tsi.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_tsi.c - - - - - gd32f3x0_rtc.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_rtc.c - - - - - gd32f3x0_wwdgt.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_wwdgt.c - - - - - gd32f3x0_rcu.c - 1 - Libraries\GD32F3x0_standard_peripheral\Source\gd32f3x0_rcu.c - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32350r-eval/rtconfig.h b/bsp/gd32350r-eval/rtconfig.h deleted file mode 100644 index 737af029ec..0000000000 --- a/bsp/gd32350r-eval/rtconfig.h +++ /dev/null @@ -1,235 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 - -/* kservice optimization */ - -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" -#define RT_VER_NUM 0x50002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* sensors drivers */ - - -/* touch drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -#define SOC_GD32350R -#define BSP_USING_UART0 - -#endif diff --git a/bsp/gd32350r-eval/rtconfig.py b/bsp/gd32350r-eval/rtconfig.py deleted file mode 100644 index 62a01d8186..0000000000 --- a/bsp/gd32350r-eval/rtconfig.py +++ /dev/null @@ -1,126 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu=cortex-m4.fp' - CFLAGS = DEVICE + ' --apcs=interwork --cpu Cortex-M4.fp' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - CFLAGS += ' --c99' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D USE_STDPERIPH_DRIVER' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config gd32_rom.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH += '/arm/bin/' - POST_ACTION = '' diff --git a/bsp/gd32350r-eval/template.uvoptx b/bsp/gd32350r-eval/template.uvoptx deleted file mode 100644 index 96b3c092db..0000000000 --- a/bsp/gd32350r-eval/template.uvoptx +++ /dev/null @@ -1,190 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f30x - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - CMSIS_AGDI - -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0.FLM -FS08000000 -FL020000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0GD32F3x0 -FL010000 -FS08000000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM) - - - 0 - JL2CM3 - -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/gd32350r-eval/template.uvprojx b/bsp/gd32350r-eval/template.uvprojx deleted file mode 100644 index 101d86a955..0000000000 --- a/bsp/gd32350r-eval/template.uvprojx +++ /dev/null @@ -1,401 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread_gd32f30x - 0x4 - ARM-ADS - 0 - - - GD32F350R8 - GigaDevice - GigaDevice.GD32F3x0_DFP.2.0.0 - http://gd32mcu.21ic.com/data/documents/yingyongruanjian/ - IRAM(0x20000000,0x04000) IROM(0x08000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F3x0 -FS08000000 -FL010000 -FP0($$Device:GD32F350R8$Flash\GD32F3x0.FLM)) - 0 - $$Device:GD32F350R8$Device\Include\gd32f3x0.h - - - - - - - - - - $$Device:GD32F350R8$SVD\GD32F3x0.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-gd32f3x0 - 1 - 0 - 1 - 1 - 0 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 1 - 0x8000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x20000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - .\gd32_rom.ld - - - - - - - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32450z-eval/.config b/bsp/gd32450z-eval/.config deleted file mode 100644 index 2e98cbcd6b..0000000000 --- a/bsp/gd32450z-eval/.config +++ /dev/null @@ -1,1120 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_INIT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50002 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=16 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=4 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -CONFIG_RT_DFS_ELM_USE_LFN_0=y -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set -CONFIG_RT_DFS_ELM_USE_LFN=0 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_MQUEUE is not set -# CONFIG_RT_USING_DFS_NFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 -CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_KTIME is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -CONFIG_RT_USING_POSIX_FS=y -# CONFIG_RT_USING_POSIX_DEVIO is not set -# CONFIG_RT_USING_POSIX_STDIO is not set -CONFIG_RT_USING_POSIX_POLL=y -CONFIG_RT_USING_POSIX_SELECT=y -# CONFIG_RT_USING_POSIX_EVENTFD is not set -# CONFIG_RT_USING_POSIX_TIMERFD is not set -# CONFIG_RT_USING_POSIX_SOCKET is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set -# CONFIG_RT_USING_POSIX_MMAN is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -CONFIG_RT_USING_SAL=y -CONFIG_SAL_INTERNET_CHECK=y - -# -# Docking with protocol stacks -# -CONFIG_SAL_USING_LWIP=y -# CONFIG_SAL_USING_AT is not set -# CONFIG_SAL_USING_TLS is not set -CONFIG_SAL_USING_POSIX=y -# CONFIG_SAL_USING_AF_UNIX is not set -CONFIG_RT_USING_NETDEV=y -CONFIG_NETDEV_USING_IFCONFIG=y -CONFIG_NETDEV_USING_PING=y -CONFIG_NETDEV_USING_NETSTAT=y -CONFIG_NETDEV_USING_AUTO_DEFAULT=y -# CONFIG_NETDEV_USING_IPV6 is not set -CONFIG_NETDEV_IPV4=1 -CONFIG_NETDEV_IPV6=0 -# CONFIG_NETDEV_IPV6_SCOPES is not set -CONFIG_RT_USING_LWIP=y -# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set -# CONFIG_RT_USING_LWIP141 is not set -CONFIG_RT_USING_LWIP203=y -# CONFIG_RT_USING_LWIP212 is not set -# CONFIG_RT_USING_LWIP_LATEST is not set -CONFIG_RT_USING_LWIP_VER_NUM=0x20003 -# CONFIG_RT_USING_LWIP_IPV6 is not set -CONFIG_RT_LWIP_MEM_ALIGNMENT=4 -CONFIG_RT_LWIP_IGMP=y -CONFIG_RT_LWIP_ICMP=y -# CONFIG_RT_LWIP_SNMP is not set -CONFIG_RT_LWIP_DNS=y -CONFIG_RT_LWIP_DHCP=y -CONFIG_IP_SOF_BROADCAST=1 -CONFIG_IP_SOF_BROADCAST_RECV=1 - -# -# Static IPv4 Address -# -CONFIG_RT_LWIP_IPADDR="192.168.1.30" -CONFIG_RT_LWIP_GWADDR="192.168.1.1" -CONFIG_RT_LWIP_MSKADDR="255.255.255.0" -CONFIG_RT_LWIP_UDP=y -CONFIG_RT_LWIP_TCP=y -CONFIG_RT_LWIP_RAW=y -# CONFIG_RT_LWIP_PPP is not set -CONFIG_RT_MEMP_NUM_NETCONN=8 -CONFIG_RT_LWIP_PBUF_NUM=16 -CONFIG_RT_LWIP_RAW_PCB_NUM=4 -CONFIG_RT_LWIP_UDP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_PCB_NUM=4 -CONFIG_RT_LWIP_TCP_SEG_NUM=40 -CONFIG_RT_LWIP_TCP_SND_BUF=8196 -CONFIG_RT_LWIP_TCP_WND=8196 -CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 -CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 -CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 -# CONFIG_LWIP_NO_RX_THREAD is not set -# CONFIG_LWIP_NO_TX_THREAD is not set -CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 -CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 -CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 -# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set -CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 -CONFIG_LWIP_NETIF_LINK_CALLBACK=1 -CONFIG_SO_REUSE=1 -CONFIG_LWIP_SO_RCVTIMEO=1 -CONFIG_LWIP_SO_SNDTIMEO=1 -CONFIG_LWIP_SO_RCVBUF=1 -CONFIG_LWIP_SO_LINGER=0 -# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set -CONFIG_LWIP_NETIF_LOOPBACK=0 -# CONFIG_RT_LWIP_STATS is not set -# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set -CONFIG_RT_LWIP_USING_PING=y -# CONFIG_LWIP_USING_DHCPD is not set -# CONFIG_RT_LWIP_DEBUG is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# -CONFIG_SOC_GD32450Z=y -CONFIG_BSP_USING_SDRAM=y -CONFIG_BSP_USING_UART0=y -# CONFIG_BSP_USING_UART1 is not set -# CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_UART4 is not set -# CONFIG_BSP_USING_UART5 is not set -# CONFIG_BSP_USING_LPUART1 is not set diff --git a/bsp/gd32450z-eval/Kconfig b/bsp/gd32450z-eval/Kconfig deleted file mode 100644 index 6f30da0203..0000000000 --- a/bsp/gd32450z-eval/Kconfig +++ /dev/null @@ -1,61 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -# you can change the RTT_ROOT default: "rt-thread" -# example : default "F:/git_repositories/rt-thread" - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_GD32450Z - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -config BSP_USING_SDRAM - bool "Using sdram" - default y - -config BSP_USING_UART0 - bool "using uart0" - select RT_USING_SERIAL - default n -config BSP_USING_UART1 - bool "using uart1" - select RT_USING_SERIAL - default n -config BSP_USING_UART2 - bool "using uart2" - select RT_USING_SERIAL - default y -config BSP_USING_UART3 - bool "using uart3" - select RT_USING_SERIAL - default n -config BSP_USING_UART4 - bool "using uart4" - select RT_USING_SERIAL - default n -config BSP_USING_UART5 - bool "using uart5" - select RT_USING_SERIAL - default n -config BSP_USING_LPUART1 - bool "using lpuart1" - select RT_USING_SERIAL - default n diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h deleted file mode 100644 index a901975bbd..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h +++ /dev/null @@ -1,366 +0,0 @@ -/*! - \file gd32f4xx.h - \brief general definitions for GD32F4xx - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_H -#define GD32F4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* define GD32F4xx */ -#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) - /* #define GD32F450 */ - /* #define GD32F405 */ - /* #define GD32F407 */ -#endif /* define GD32F4xx */ - -#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) - #error "Please select the target GD32F4xx device in gd32f4xx.h file" -#endif /* undefine GD32F4xx tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined (HXTAL_VALUE) -#define HXTAL_VALUE ((uint32_t)25000000) -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ -#if !defined (IRC16M_VALUE) -#define IRC16M_VALUE ((uint32_t)16000000) -#endif /* internal 16MHz RC oscillator value */ - -/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */ -#if !defined (IRC16M_STARTUP_TIMEOUT) -#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 16MHz RC oscillator startup timeout */ - -/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ -#if !defined (IRC32K_VALUE) -#define IRC32K_VALUE ((uint32_t)32000) -#endif /* internal 32KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* I2S external clock in selection */ -//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U - -/* GD32F4xx firmware library version number V1.0 */ -#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ -#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32F4xx_STDPERIPH_VERSION_RC)) - -/* configuration of the cortex-M4 processor and core peripherals */ -#define __CM4_REV 0x0001 /*!< core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */ -#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */ -#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ -/* define interrupt number */ -typedef enum IRQn -{ - /* cortex-M4 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */ - BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */ - UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */ - SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */ - PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */ - SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */ - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */ - RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */ - FMC_IRQn = 4, /*!< FMC interrupt */ - RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ - EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ - EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ - EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ - EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ - EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */ - DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */ - DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ - DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ - DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ - DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ - DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ - ADC_IRQn = 18, /*!< ADC interrupt */ - CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ - CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ - CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ - CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ - EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */ - TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */ - TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */ - TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ - TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 30, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ - SPI0_IRQn = 35, /*!< SPI0 interrupt */ - SPI1_IRQn = 36, /*!< SPI1 interrupt */ - USART0_IRQn = 37, /*!< USART0 interrupt */ - USART1_IRQn = 38, /*!< USART1 interrupt */ - USART2_IRQn = 39, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ - USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */ - TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */ - TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */ - TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */ - TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ - DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */ - -#if defined (GD32F450) - EXMC_IRQn = 48, /*!< EXMC interrupt */ - SDIO_IRQn = 49, /*!< SDIO interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ - SPI2_IRQn = 51, /*!< SPI2 interrupt */ - UART3_IRQn = 52, /*!< UART3 interrupt */ - UART4_IRQn = 53, /*!< UART4 interrupt */ - TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ - TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ - ENET_IRQn = 61, /*!< ENET interrupt */ - ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS interrupt */ - DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ - DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ - DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ - USART5_IRQn = 71, /*!< USART5 interrupt */ - I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ - I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ - USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ - USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ - USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ - USBHS_IRQn = 77, /*!< USBHS interrupt */ - DCI_IRQn = 78, /*!< DCI interrupt */ - TRNG_IRQn = 80, /*!< TRNG interrupt */ - FPU_IRQn = 81, /*!< FPU interrupt */ - UART6_IRQn = 82, /*!< UART6 interrupt */ - UART7_IRQn = 83, /*!< UART7 interrupt */ - SPI3_IRQn = 84, /*!< SPI3 interrupt */ - SPI4_IRQn = 85, /*!< SPI4 interrupt */ - SPI5_IRQn = 86, /*!< SPI5 interrupt */ - TLI_IRQn = 88, /*!< TLI interrupt */ - TLI_ER_IRQn = 89, /*!< TLI error interrupt */ - IPA_IRQn = 90, /*!< IPA interrupt */ -#endif /* GD32F450 */ - -#if defined (GD32F405) - SDIO_IRQn = 49, /*!< SDIO interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ - SPI2_IRQn = 51, /*!< SPI2 interrupt */ - UART3_IRQn = 52, /*!< UART3 interrupt */ - UART4_IRQn = 53, /*!< UART4 interrupt */ - TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ - TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS interrupt */ - DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ - DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ - DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ - USART5_IRQn = 71, /*!< USART5 interrupt */ - I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ - I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ - USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */ - USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ - USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ - USBHS_IRQn = 77, /*!< USBHS interrupt */ - DCI_IRQn = 78, /*!< DCI interrupt */ - TRNG_IRQn = 80, /*!< TRNG interrupt */ - FPU_IRQn = 81, /*!< FPU interrupt */ -#endif /* GD32F405 */ - -#if defined (GD32F407) - EXMC_IRQn = 48, /*!< EXMC interrupt */ - SDIO_IRQn = 49, /*!< SDIO interrupt */ - TIMER4_IRQn = 50, /*!< TIMER4 interrupt */ - SPI2_IRQn = 51, /*!< SPI2 interrupt */ - UART3_IRQn = 52, /*!< UART3 interrupt */ - UART4_IRQn = 53, /*!< UART4 interrupt */ - TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */ - TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ - DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */ - DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */ - DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */ - DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */ - DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */ - ENET_IRQn = 61, /*!< ENET interrupt */ - ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */ - CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 67, /*!< USBFS interrupt */ - DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */ - DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */ - DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */ - USART5_IRQn = 71, /*!< USART5 interrupt */ - I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */ - I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */ - USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */ - USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */ - USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */ - USBHS_IRQn = 77, /*!< USBHS interrupt */ - DCI_IRQn = 78, /*!< DCI interrupt */ - TRNG_IRQn = 80, /*!< TRNG interrupt */ - FPU_IRQn = 81, /*!< FPU interrupt */ -#endif /* GD32F407 */ - -} IRQn_Type; - -/* includes */ -#include "core_cm4.h" -#include "system_gd32f4xx.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */ -#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ - -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ -#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */ - -/* EXMC memory map */ -#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ - -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ -#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ -#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */ - -/* advanced peripheral bus 2 memory map */ -#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */ -#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */ -#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */ -/* advanced high performance bus 1 memory map */ -#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */ -#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */ -#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */ -#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */ -#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */ - -/* advanced high performance bus 2 memory map */ -#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */ -#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */ -#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */ -/* option byte and debug memory map */ -#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ - -/* define marco USE_STDPERIPH_DRIVER */ -#if !defined USE_STDPERIPH_DRIVER -#define USE_STDPERIPH_DRIVER -#endif -#ifdef USE_STDPERIPH_DRIVER -#include "gd32f4xx_libopt.h" -#endif /* USE_STDPERIPH_DRIVER */ - -#ifdef cplusplus -} -#endif -#endif diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/system_gd32f4xx.h b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/system_gd32f4xx.h deleted file mode 100644 index ab8e80e7e9..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Include/system_gd32f4xx.h +++ /dev/null @@ -1,58 +0,0 @@ -/*! - \file system_gd32f4xx.h - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for - GD32F4xx Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32F4XX_H -#define SYSTEM_GD32F4XX_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit (void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32F4XX_H */ diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s deleted file mode 100644 index ba5c4c7399..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/ARM/startup_gd32f4xx.s +++ /dev/null @@ -1,428 +0,0 @@ -;/*! -; \file startup_gd32f4xx.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2016 GigaDevice - -; 2016-08-15, V1.0.0, firmware for GD32F4xx -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect - DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC_IRQHandler ; 34:ADC - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10 - DCD TIMER0_CC_IRQHandler ; 43:TIMER0 Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13 - DCD TIMER7_CC_IRQHandler ; 62:TIMER7 Capture Compare - DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD ENET_IRQHandler ; 77:Ethernet - DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 - DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 - DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 - DCD USART5_IRQHandler ; 87:USART5 - DCD I2C2_EV_IRQHandler ; 88:I2C2 Event - DCD I2C2_ER_IRQHandler ; 89:I2C2 Error - DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out - DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in - DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line - DCD USBHS_IRQHandler ; 93:USBHS - DCD DCI_IRQHandler ; 94:DCI - DCD 0 ; 95:Reserved - DCD TRNG_IRQHandler ; 96:TRNG - DCD FPU_IRQHandler ; 97:FPU - DCD UART6_IRQHandler ; 98:UART6 - DCD UART7_IRQHandler ; 99:UART7 - DCD SPI3_IRQHandler ; 100:SPI3 - DCD SPI4_IRQHandler ; 101:SPI4 - DCD SPI5_IRQHandler ; 102:SPI5 - DCD 0 ; 103:Reserved - DCD TLI_IRQHandler ; 104:TLI - DCD TLI_ER_IRQHandler ; 105:TLI Error - DCD IPA_IRQHandler ; 106:IPA - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT TAMPER_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_CTC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA0_Channel0_IRQHandler [WEAK] - EXPORT DMA0_Channel1_IRQHandler [WEAK] - EXPORT DMA0_Channel2_IRQHandler [WEAK] - EXPORT DMA0_Channel3_IRQHandler [WEAK] - EXPORT DMA0_Channel4_IRQHandler [WEAK] - EXPORT DMA0_Channel5_IRQHandler [WEAK] - EXPORT DMA0_Channel6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN0_TX_IRQHandler [WEAK] - EXPORT CAN0_RX0_IRQHandler [WEAK] - EXPORT CAN0_RX1_IRQHandler [WEAK] - EXPORT CAN0_EWMC_IRQHandler [WEAK] - EXPORT EXTI5_9_IRQHandler [WEAK] - EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK] - EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK] - EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK] - EXPORT TIMER0_CC_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI10_15_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT USBFS_WKUP_IRQHandler [WEAK] - EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK] - EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK] - EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK] - EXPORT TIMER7_CC_IRQHandler [WEAK] - EXPORT DMA0_Channel7_IRQHandler [WEAK] - EXPORT EXMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIMER4_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT TIMER5_DAC_IRQHandler [WEAK] - EXPORT TIMER6_IRQHandler [WEAK] - EXPORT DMA1_Channel0_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_IRQHandler [WEAK] - EXPORT DMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_IRQHandler [WEAK] - EXPORT ENET_IRQHandler [WEAK] - EXPORT ENET_WKUP_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_EWMC_IRQHandler [WEAK] - EXPORT USBFS_IRQHandler [WEAK] - EXPORT DMA1_Channel5_IRQHandler [WEAK] - EXPORT DMA1_Channel6_IRQHandler [WEAK] - EXPORT DMA1_Channel7_IRQHandler [WEAK] - EXPORT USART5_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT USBHS_EP1_Out_IRQHandler [WEAK] - EXPORT USBHS_EP1_In_IRQHandler [WEAK] - EXPORT USBHS_WKUP_IRQHandler [WEAK] - EXPORT USBHS_IRQHandler [WEAK] - EXPORT DCI_IRQHandler [WEAK] - EXPORT TRNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART6_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT TLI_IRQHandler [WEAK] - EXPORT TLI_ER_IRQHandler [WEAK] - EXPORT IPA_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -TAMPER_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FMC_IRQHandler -RCU_CTC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA0_Channel0_IRQHandler -DMA0_Channel1_IRQHandler -DMA0_Channel2_IRQHandler -DMA0_Channel3_IRQHandler -DMA0_Channel4_IRQHandler -DMA0_Channel5_IRQHandler -DMA0_Channel6_IRQHandler -ADC_IRQHandler -CAN0_TX_IRQHandler -CAN0_RX0_IRQHandler -CAN0_RX1_IRQHandler -CAN0_EWMC_IRQHandler -EXTI5_9_IRQHandler -TIMER0_BRK_TIMER8_IRQHandler -TIMER0_UP_TIMER9_IRQHandler -TIMER0_TRG_CMT_TIMER10_IRQHandler -TIMER0_CC_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -I2C0_EV_IRQHandler -I2C0_ER_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI10_15_IRQHandler -RTC_Alarm_IRQHandler -USBFS_WKUP_IRQHandler -TIMER7_BRK_TIMER11_IRQHandler -TIMER7_UP_TIMER12_IRQHandler -TIMER7_TRG_CMT_TIMER13_IRQHandler -TIMER7_CC_IRQHandler -DMA0_Channel7_IRQHandler -EXMC_IRQHandler -SDIO_IRQHandler -TIMER4_IRQHandler -SPI2_IRQHandler -UART3_IRQHandler -UART4_IRQHandler -TIMER5_DAC_IRQHandler -TIMER6_IRQHandler -DMA1_Channel0_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_IRQHandler -DMA1_Channel3_IRQHandler -DMA1_Channel4_IRQHandler -ENET_IRQHandler -ENET_WKUP_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_EWMC_IRQHandler -USBFS_IRQHandler -DMA1_Channel5_IRQHandler -DMA1_Channel6_IRQHandler -DMA1_Channel7_IRQHandler -USART5_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -USBHS_EP1_Out_IRQHandler -USBHS_EP1_In_IRQHandler -USBHS_WKUP_IRQHandler -USBHS_IRQHandler -DCI_IRQHandler -TRNG_IRQHandler -FPU_IRQHandler -UART6_IRQHandler -UART7_IRQHandler -SPI3_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -TLI_IRQHandler -TLI_ER_IRQHandler -IPA_IRQHandler - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S deleted file mode 100644 index 2e53748e25..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/GCC/startup_gd32f4xx.S +++ /dev/null @@ -1,317 +0,0 @@ -;/* -; * Copyright (c) 2006-2021, RT-Thread Development Team -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Change Logs: -; * Date Author Notes -; * 2018-05-22 tanek first implementation -; */ - -.syntax unified -.cpu cortex-m4 -.fpu softvfp -.thumb - -.global g_pfnVectors -.global Default_Handler - - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - -g_pfnVectors: - .word _estack // Top of Stack - .word Reset_Handler // Reset Handler - .word NMI_Handler // NMI Handler - .word HardFault_Handler // Hard Fault Handler - .word MemManage_Handler // MPU Fault Handler - .word BusFault_Handler // Bus Fault Handler - .word UsageFault_Handler // Usage Fault Handler - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word 0 // Reserved - .word SVC_Handler // SVCall Handler - .word DebugMon_Handler // Debug Monitor Handler - .word 0 // Reserved - .word PendSV_Handler // PendSV Handler - .word SysTick_Handler // SysTick Handler - - // external interrupts handler - .word WWDGT_IRQHandler // 16:Window Watchdog Timer - .word LVD_IRQHandler // 17:LVD through EXTI Line detect - .word TAMPER_STAMP_IRQHandler // 18:Tamper and TimeStamp through EXTI Line detect - .word RTC_WKUP_IRQHandler // 19:RTC Wakeup through EXTI Line - .word FMC_IRQHandler // 20:FMC - .word RCU_CTC_IRQHandler // 21:RCU and CTC - .word EXTI0_IRQHandler // 22:EXTI Line 0 - .word EXTI1_IRQHandler // 23:EXTI Line 1 - .word EXTI2_IRQHandler // 24:EXTI Line 2 - .word EXTI3_IRQHandler // 25:EXTI Line 3 - .word EXTI4_IRQHandler // 26:EXTI Line 4 - .word DMA0_Channel0_IRQHandler // 27:DMA0 Channel0 - .word DMA0_Channel1_IRQHandler // 28:DMA0 Channel1 - .word DMA0_Channel2_IRQHandler // 29:DMA0 Channel2 - .word DMA0_Channel3_IRQHandler // 30:DMA0 Channel3 - .word DMA0_Channel4_IRQHandler // 31:DMA0 Channel4 - .word DMA0_Channel5_IRQHandler // 32:DMA0 Channel5 - .word DMA0_Channel6_IRQHandler // 33:DMA0 Channel6 - .word ADC_IRQHandler // 34:ADC - .word CAN0_TX_IRQHandler // 35:CAN0 TX - .word CAN0_RX0_IRQHandler // 36:CAN0 RX0 - .word CAN0_RX1_IRQHandler // 37:CAN0 RX1 - .word CAN0_EWMC_IRQHandler // 38:CAN0 EWMC - .word EXTI5_9_IRQHandler // 39:EXTI5 to EXTI9 - .word TIMER0_BRK_TIMER8_IRQHandler // 40:TIMER0 Break and TIMER8 - .word TIMER0_UP_TIMER9_IRQHandler // 41:TIMER0 Update and TIMER9 - .word TIMER0_TRG_CMT_TIMER10_IRQHandler // 42:TIMER0 Trigger and Commutation and TIMER10 - .word TIMER0_CC_IRQHandler // 43:TIMER0 Capture Compare - .word TIMER1_IRQHandler // 44:TIMER1 - .word TIMER2_IRQHandler // 45:TIMER2 - .word TIMER3_IRQHandler // 46:TIMER3 - .word I2C0_EV_IRQHandler // 47:I2C0 Event - .word I2C0_ER_IRQHandler // 48:I2C0 Error - .word I2C1_EV_IRQHandler // 49:I2C1 Event - .word I2C1_ER_IRQHandler // 50:I2C1 Error - .word SPI0_IRQHandler // 51:SPI0 - .word SPI1_IRQHandler // 52:SPI1 - .word USART0_IRQHandler // 53:USART0 - .word USART1_IRQHandler // 54:USART1 - .word USART2_IRQHandler // 55:USART2 - .word EXTI10_15_IRQHandler // 56:EXTI10 to EXTI15 - .word RTC_Alarm_IRQHandler // 57:RTC Alarm - .word USBFS_WKUP_IRQHandler // 58:USBFS Wakeup - .word TIMER7_BRK_TIMER11_IRQHandler // 59:TIMER7 Break and TIMER11 - .word TIMER7_UP_TIMER12_IRQHandler // 60:TIMER7 Update and TIMER12 - .word TIMER7_TRG_CMT_TIMER13_IRQHandler // 61:TIMER7 Trigger and Commutation and TIMER13 - .word TIMER7_CC_IRQHandler // 62:TIMER7 Capture Compare - .word DMA0_Channel7_IRQHandler // 63:DMA0 Channel7 - .word EXMC_IRQHandler // 64:EXMC - .word SDIO_IRQHandler // 65:SDIO - .word TIMER4_IRQHandler // 66:TIMER4 - .word SPI2_IRQHandler // 67:SPI2 - .word UART3_IRQHandler // 68:UART3 - .word UART4_IRQHandler // 69:UART4 - .word TIMER5_DAC_IRQHandler // 70:TIMER5 and DAC0 DAC1 Underrun error - .word TIMER6_IRQHandler // 71:TIMER6 - .word DMA1_Channel0_IRQHandler // 72:DMA1 Channel0 - .word DMA1_Channel1_IRQHandler // 73:DMA1 Channel1 - .word DMA1_Channel2_IRQHandler // 74:DMA1 Channel2 - .word DMA1_Channel3_IRQHandler // 75:DMA1 Channel3 - .word DMA1_Channel4_IRQHandler // 76:DMA1 Channel4 - .word ENET_IRQHandler // 77:Ethernet - .word ENET_WKUP_IRQHandler // 78:Ethernet Wakeup through EXTI Line - .word CAN1_TX_IRQHandler // 79:CAN1 TX - .word CAN1_RX0_IRQHandler // 80:CAN1 RX0 - .word CAN1_RX1_IRQHandler // 81:CAN1 RX1 - .word CAN1_EWMC_IRQHandler // 82:CAN1 EWMC - .word USBFS_IRQHandler // 83:USBFS - .word DMA1_Channel5_IRQHandler // 84:DMA1 Channel5 - .word DMA1_Channel6_IRQHandler // 85:DMA1 Channel6 - .word DMA1_Channel7_IRQHandler // 86:DMA1 Channel7 - .word USART5_IRQHandler // 87:USART5 - .word I2C2_EV_IRQHandler // 88:I2C2 Event - .word I2C2_ER_IRQHandler // 89:I2C2 Error - .word USBHS_EP1_Out_IRQHandler // 90:USBHS Endpoint 1 Out - .word USBHS_EP1_In_IRQHandler // 91:USBHS Endpoint 1 in - .word USBHS_WKUP_IRQHandler // 92:USBHS Wakeup through EXTI Line - .word USBHS_IRQHandler // 93:USBHS - .word DCI_IRQHandler // 94:DCI - .word 0 // 95:Reserved - .word TRNG_IRQHandler // 96:TRNG - .word FPU_IRQHandler // 97:FPU - .word UART6_IRQHandler // 98:UART6 - .word UART7_IRQHandler // 99:UART7 - .word SPI3_IRQHandler // 100:SPI3 - .word SPI4_IRQHandler // 101:SPI4 - .word SPI5_IRQHandler // 102:SPI5 - .word 0 // 103:Reserved - .word TLI_IRQHandler // 104:TLI - .word TLI_ER_IRQHandler // 105:TLI Error - .word IPA_IRQHandler // 106:IPA - - .size g_pfnVectors, .-g_pfnVectors - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r1, =_sidata - ldr r2, =_sdata - ldr r3, =_edata - - subs r3, r2 - ble fill_bss_start - -loop_copy_data: - subs r3, #4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt loop_copy_data - -fill_bss_start: - ldr r1, =__bss_start - ldr r2, =__bss_end - movs r0, 0 - subs r2, r1 - ble startup_enter - -loop_fill_bss: - subs r2, #4 - str r0, [r1, r2] - bgt loop_fill_bss - -startup_enter: - bl SystemInit - bl entry - - /* Exception Handlers */ - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - b . - .size NMI_Handler, . - NMI_Handler - - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - b . - .size MemManage_Handler, . - MemManage_Handler - - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - b . - .size BusFault_Handler, . - BusFault_Handler - - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - b . - .size UsageFault_Handler, . - UsageFault_Handler - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - b . - .size SVC_Handler, . - SVC_Handler - - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - b . - .size DebugMon_Handler, . - DebugMon_Handler - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - b . - .size PendSV_Handler, . - PendSV_Handler - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - b . - .size SysTick_Handler, . - SysTick_Handler - - /* IQR Handler */ - .section .text.Default_Handler,"ax",%progbits - .type Default_Handler, %function -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ WWDGT_IRQHandler - IRQ LVD_IRQHandler - IRQ TAMPER_STAMP_IRQHandler - IRQ RTC_WKUP_IRQHandler - IRQ FMC_IRQHandler - IRQ RCU_CTC_IRQHandler - IRQ EXTI0_IRQHandler - IRQ EXTI1_IRQHandler - IRQ EXTI2_IRQHandler - IRQ EXTI3_IRQHandler - IRQ EXTI4_IRQHandler - IRQ DMA0_Channel0_IRQHandler - IRQ DMA0_Channel1_IRQHandler - IRQ DMA0_Channel2_IRQHandler - IRQ DMA0_Channel3_IRQHandler - IRQ DMA0_Channel4_IRQHandler - IRQ DMA0_Channel5_IRQHandler - IRQ DMA0_Channel6_IRQHandler - IRQ ADC_IRQHandler - IRQ CAN0_TX_IRQHandler - IRQ CAN0_RX0_IRQHandler - IRQ CAN0_RX1_IRQHandler - IRQ CAN0_EWMC_IRQHandler - IRQ EXTI5_9_IRQHandler - IRQ TIMER0_BRK_TIMER8_IRQHandler - IRQ TIMER0_UP_TIMER9_IRQHandler - IRQ TIMER0_TRG_CMT_TIMER10_IRQHandler - IRQ TIMER0_CC_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ TIMER3_IRQHandler - IRQ I2C0_EV_IRQHandler - IRQ I2C0_ER_IRQHandler - IRQ I2C1_EV_IRQHandler - IRQ I2C1_ER_IRQHandler - IRQ SPI0_IRQHandler - IRQ SPI1_IRQHandler - IRQ USART0_IRQHandler - IRQ USART1_IRQHandler - IRQ USART2_IRQHandler - IRQ EXTI10_15_IRQHandler - IRQ RTC_Alarm_IRQHandler - IRQ USBFS_WKUP_IRQHandler - IRQ TIMER7_BRK_TIMER11_IRQHandler - IRQ TIMER7_UP_TIMER12_IRQHandler - IRQ TIMER7_TRG_CMT_TIMER13_IRQHandler - IRQ TIMER7_CC_IRQHandler - IRQ DMA0_Channel7_IRQHandler - IRQ EXMC_IRQHandler - IRQ SDIO_IRQHandler - IRQ TIMER4_IRQHandler - IRQ SPI2_IRQHandler - IRQ UART3_IRQHandler - IRQ UART4_IRQHandler - IRQ TIMER5_DAC_IRQHandler - IRQ TIMER6_IRQHandler - IRQ DMA1_Channel0_IRQHandler - IRQ DMA1_Channel1_IRQHandler - IRQ DMA1_Channel2_IRQHandler - IRQ DMA1_Channel3_IRQHandler - IRQ DMA1_Channel4_IRQHandler - IRQ ENET_IRQHandler - IRQ ENET_WKUP_IRQHandler - IRQ CAN1_TX_IRQHandler - IRQ CAN1_RX0_IRQHandler - IRQ CAN1_RX1_IRQHandler - IRQ CAN1_EWMC_IRQHandler - IRQ USBFS_IRQHandler - IRQ DMA1_Channel5_IRQHandler - IRQ DMA1_Channel6_IRQHandler - IRQ DMA1_Channel7_IRQHandler - IRQ USART5_IRQHandler - IRQ I2C2_EV_IRQHandler - IRQ I2C2_ER_IRQHandler - IRQ USBHS_EP1_Out_IRQHandler - IRQ USBHS_EP1_In_IRQHandler - IRQ USBHS_WKUP_IRQHandler - IRQ USBHS_IRQHandler - IRQ DCI_IRQHandler - IRQ TRNG_IRQHandler - IRQ FPU_IRQHandler - IRQ UART6_IRQHandler - IRQ UART7_IRQHandler - IRQ SPI3_IRQHandler - IRQ SPI4_IRQHandler - IRQ SPI5_IRQHandler - IRQ TLI_IRQHandler - IRQ TLI_ER_IRQHandler - IRQ IPA_IRQHandler diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s deleted file mode 100644 index af94881cdf..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/IAR/startup_gd32f4xx.s +++ /dev/null @@ -1,641 +0,0 @@ -;/*! -; \file startup_gd32f4xx.s -; \brief start up file -;*/ - -;/* -; Copyright (C) 2016 GigaDevice - -; 2016-08-15, V1.0.0, firmware for GD32F4xx - -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler - DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler - DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect - DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line - DCD FMC_IRQHandler ; 20:FMC - DCD RCU_CTC_IRQHandler ; 21:RCU and CTC - DCD EXTI0_IRQHandler ; 22:EXTI Line 0 - DCD EXTI1_IRQHandler ; 23:EXTI Line 1 - DCD EXTI2_IRQHandler ; 24:EXTI Line 2 - DCD EXTI3_IRQHandler ; 25:EXTI Line 3 - DCD EXTI4_IRQHandler ; 26:EXTI Line 4 - DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0 - DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1 - DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2 - DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3 - DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4 - DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5 - DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6 - DCD ADC_IRQHandler ; 34:ADC - DCD CAN0_TX_IRQHandler ; 35:CAN0 TX - DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0 - DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1 - DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC - DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9 - DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8 - DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9 - DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10 - DCD TIMER0_CC_IRQHandler ; 43:TIMER0 Capture Compare - DCD TIMER1_IRQHandler ; 44:TIMER1 - DCD TIMER2_IRQHandler ; 45:TIMER2 - DCD TIMER3_IRQHandler ; 46:TIMER3 - DCD I2C0_EV_IRQHandler ; 47:I2C0 Event - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD I2C1_EV_IRQHandler ; 49:I2C1 Event - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - DCD SPI0_IRQHandler ; 51:SPI0 - DCD SPI1_IRQHandler ; 52:SPI1 - DCD USART0_IRQHandler ; 53:USART0 - DCD USART1_IRQHandler ; 54:USART1 - DCD USART2_IRQHandler ; 55:USART2 - DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15 - DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm - DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup - DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11 - DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12 - DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13 - DCD TIMER7_CC_IRQHandler ; 62:TIMER7 Capture Compare - DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7 - DCD EXMC_IRQHandler ; 64:EXMC - DCD SDIO_IRQHandler ; 65:SDIO - DCD TIMER4_IRQHandler ; 66:TIMER4 - DCD SPI2_IRQHandler ; 67:SPI2 - DCD UART3_IRQHandler ; 68:UART3 - DCD UART4_IRQHandler ; 69:UART4 - DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error - DCD TIMER6_IRQHandler ; 71:TIMER6 - DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0 - DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1 - DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2 - DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3 - DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4 - DCD ENET_IRQHandler ; 77:Ethernet - DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line - DCD CAN1_TX_IRQHandler ; 79:CAN1 TX - DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1 - DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC - DCD USBFS_IRQHandler ; 83:USBFS - DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5 - DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6 - DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7 - DCD USART5_IRQHandler ; 87:USART5 - DCD I2C2_EV_IRQHandler ; 88:I2C2 Event - DCD I2C2_ER_IRQHandler ; 89:I2C2 Error - DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out - DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in - DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line - DCD USBHS_IRQHandler ; 93:USBHS - DCD DCI_IRQHandler ; 94:DCI - DCD 0 ; 95:Reserved - DCD TRNG_IRQHandler ; 96:TRNG - DCD FPU_IRQHandler ; 97:FPU - DCD UART6_IRQHandler ; 98:UART6 - DCD UART7_IRQHandler ; 99:UART7 - DCD SPI3_IRQHandler ; 100:SPI3 - DCD SPI4_IRQHandler ; 101:SPI4 - DCD SPI5_IRQHandler ; 102:SPI5 - DCD 0 ; 103:Reserved - DCD TLI_IRQHandler ; 104:TLI - DCD TLI_ER_IRQHandler ; 105:TLI Error - DCD IPA_IRQHandler ; 106:IPA - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK TAMPER_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMPER_STAMP_IRQHandler - B TAMPER_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_CTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_CTC_IRQHandler - B RCU_CTC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA0_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel0_IRQHandler - B DMA0_Channel0_IRQHandler - - PUBWEAK DMA0_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel1_IRQHandler - B DMA0_Channel1_IRQHandler - - PUBWEAK DMA0_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel2_IRQHandler - B DMA0_Channel2_IRQHandler - - PUBWEAK DMA0_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel3_IRQHandler - B DMA0_Channel3_IRQHandler - - PUBWEAK DMA0_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel4_IRQHandler - B DMA0_Channel4_IRQHandler - - PUBWEAK DMA0_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel5_IRQHandler - B DMA0_Channel5_IRQHandler - - PUBWEAK DMA0_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel6_IRQHandler - B DMA0_Channel6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN0_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_TX_IRQHandler - B CAN0_TX_IRQHandler - - PUBWEAK CAN0_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX0_IRQHandler - B CAN0_RX0_IRQHandler - - PUBWEAK CAN0_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_RX1_IRQHandler - B CAN0_RX1_IRQHandler - - PUBWEAK CAN0_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN0_EWMC_IRQHandler - B CAN0_EWMC_IRQHandler - - PUBWEAK EXTI5_9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI5_9_IRQHandler - B EXTI5_9_IRQHandler - - PUBWEAK TIMER0_BRK_TIMER8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_TIMER8_IRQHandler - B TIMER0_BRK_TIMER8_IRQHandler - - PUBWEAK TIMER0_UP_TIMER9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_UP_TIMER9_IRQHandler - B TIMER0_UP_TIMER9_IRQHandler - - PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_TRG_CMT_TIMER10_IRQHandler - B TIMER0_TRG_CMT_TIMER10_IRQHandler - - PUBWEAK TIMER0_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_CC_IRQHandler - B TIMER0_CC_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI10_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI10_15_IRQHandler - B EXTI10_15_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK USBFS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_WKUP_IRQHandler - B USBFS_WKUP_IRQHandler - - PUBWEAK TIMER7_BRK_TIMER11_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_BRK_TIMER11_IRQHandler - B TIMER7_BRK_TIMER11_IRQHandler - - PUBWEAK TIMER7_UP_TIMER12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_UP_TIMER12_IRQHandler - B TIMER7_UP_TIMER12_IRQHandler - - PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_TRG_CMT_TIMER13_IRQHandler - B TIMER7_TRG_CMT_TIMER13_IRQHandler - - PUBWEAK TIMER7_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER7_CC_IRQHandler - B TIMER7_CC_IRQHandler - - PUBWEAK DMA0_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA0_Channel7_IRQHandler - B DMA0_Channel7_IRQHandler - - PUBWEAK EXMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXMC_IRQHandler - B EXMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIMER4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER4_IRQHandler - B TIMER4_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK TIMER5_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_DAC_IRQHandler - B TIMER5_DAC_IRQHandler - - PUBWEAK TIMER6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER6_IRQHandler - B TIMER6_IRQHandler - - PUBWEAK DMA1_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel0_IRQHandler - B DMA1_Channel0_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK ENET_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_IRQHandler - B ENET_IRQHandler - - PUBWEAK ENET_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ENET_WKUP_IRQHandler - B ENET_WKUP_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_EWMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CAN1_EWMC_IRQHandler - B CAN1_EWMC_IRQHandler - - PUBWEAK USBFS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBFS_IRQHandler - B USBFS_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK USART5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART5_IRQHandler - B USART5_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK USBHS_EP1_Out_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBHS_EP1_Out_IRQHandler - B USBHS_EP1_Out_IRQHandler - - PUBWEAK USBHS_EP1_In_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBHS_EP1_In_IRQHandler - B USBHS_EP1_In_IRQHandler - - PUBWEAK USBHS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBHS_WKUP_IRQHandler - B USBHS_WKUP_IRQHandler - - PUBWEAK USBHS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USBHS_IRQHandler - B USBHS_IRQHandler - - PUBWEAK DCI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DCI_IRQHandler - B DCI_IRQHandler - - PUBWEAK TRNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TRNG_IRQHandler - B TRNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK UART6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART6_IRQHandler - B UART6_IRQHandler - - PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI4_IRQHandler - B SPI4_IRQHandler - - PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler - - PUBWEAK TLI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TLI_IRQHandler - B TLI_IRQHandler - - PUBWEAK TLI_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TLI_ER_IRQHandler - B TLI_ER_IRQHandler - - PUBWEAK IPA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -IPA_IRQHandler - B IPA_IRQHandler - END \ No newline at end of file diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c b/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c deleted file mode 100644 index 2ea97ae3f8..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/GD/GD32F4xx/Source/system_gd32f4xx.c +++ /dev/null @@ -1,916 +0,0 @@ -/*! - \file system_gd32f4xx.c - \brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for - GD32F4xx Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32f4xx.h" - -/* system frequency define */ -#define __IRC16M (IRC16M_VALUE) /* internal 16 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC16M) /* main oscillator frequency */ - -/* select a system clock by uncommenting the following line */ -//#define __SYSTEM_CLOCK_IRC16M (uint32_t)(__IRC16M) -//#define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL) -//#define __SYSTEM_CLOCK_120M_PLL_IRC16M (uint32_t)(120000000) -//#define __SYSTEM_CLOCK_120M_PLL_8M_HXTAL (uint32_t)(120000000) -//#define __SYSTEM_CLOCK_120M_PLL_25M_HXTAL (uint32_t)(120000000) -//#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000) -//#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000) -//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000) -//#define __SYSTEM_CLOCK_200M_PLL_IRC16M (uint32_t)(200000000) -//#define __SYSTEM_CLOCK_200M_PLL_8M_HXTAL (uint32_t)(200000000) -#define __SYSTEM_CLOCK_200M_PLL_25M_HXTAL (uint32_t)(200000000) - -#define SEL_IRC16M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLLP 0x02U -#define RCU_MODIFY {volatile uint32_t i; \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ - for(i=0;i<50000;i++);} - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_IRC16M -uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC16M; -static void system_clock_16m_irc16m(void); -#elif defined (__SYSTEM_CLOCK_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; -static void system_clock_hxtal(void); -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC16M; -static void system_clock_120m_irc16m(void); -#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_8M_HXTAL; -static void system_clock_120m_8m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_25M_HXTAL; -static void system_clock_120m_25m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_IRC16M; -static void system_clock_168m_irc16m(void); -#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_8M_HXTAL; -static void system_clock_168m_8m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_168M_PLL_25M_HXTAL; -static void system_clock_168m_25m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_IRC16M; -static void system_clock_200m_irc16m(void); -#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_8M_HXTAL; -static void system_clock_200m_8m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_200M_PLL_25M_HXTAL; -static void system_clock_200m_25m_hxtal(void); - -#endif /* __SYSTEM_CLOCK_IRC16M */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit (void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - /* Reset the RCU clock configuration to the default reset state ------------*/ - /* Set IRC16MEN bit */ - RCU_CTL |= RCU_CTL_IRC16MEN; - - RCU_MODIFY - - /* Reset CFG0 register */ - RCU_CFG0 = 0x00000000U; - - /* Reset HXTALEN, CKMEN and PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN); - - /* Reset PLLCFGR register */ - RCU_PLL = 0x24003010U; - - /* Reset HSEBYP bit */ - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - - /* Disable all interrupts */ - RCU_INT = 0x00000000U; - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - system_clock_config(); -} -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_IRC16M - system_clock_16m_irc16m(); -#elif defined (__SYSTEM_CLOCK_HXTAL) - system_clock_hxtal(); -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) - system_clock_120m_irc16m(); -#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) - system_clock_120m_8m_hxtal(); -#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) - system_clock_120m_25m_hxtal(); -#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) - system_clock_168m_irc16m(); -#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) - system_clock_168m_8m_hxtal(); -#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) - system_clock_168m_25m_hxtal(); -#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) - system_clock_200m_irc16m(); -#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) - system_clock_200m_8m_hxtal(); -#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) - system_clock_200m_25m_hxtal(); -#endif /* __SYSTEM_CLOCK_IRC16M */ -} - -#ifdef __SYSTEM_CLOCK_IRC16M -/*! - \brief configure the system clock to 16M by IRC16M - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_16m_irc16m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC16M */ - RCU_CTL |= RCU_CTL_IRC16MEN; - - /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select IRC16M as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_IRC16M; - - /* wait until IRC16M is selected as system clock */ - while(0 != (RCU_CFG0 & RCU_SCSS_IRC16M)){ - } -} - -#elif defined (__SYSTEM_CLOCK_HXTAL) -/*! - \brief configure the system clock to HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC16M) -/*! - \brief configure the system clock to 120M by PLL which selects IRC16M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_irc16m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC16M */ - RCU_CTL |= RCU_CTL_IRC16MEN; - - /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* IRC16M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 16, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ - RCU_PLL = (16U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_IRC16M) | (5U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 120 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_120M_PLL_8M_HXTAL) -/*! - \brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_8m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 8, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ - RCU_PLL = (8U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_HXTAL) | (5U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 120 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_120M_PLL_25M_HXTAL) -/*! - \brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_120m_25m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 25, PLL_N = 240, PLL_P = 2, PLL_Q = 5 */ - RCU_PLL = (25U | (240U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_HXTAL) | (5U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 120 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_168M_PLL_IRC16M) -/*! - \brief configure the system clock to 168M by PLL which selects IRC16M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_168m_irc16m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC16M */ - RCU_CTL |= RCU_CTL_IRC16MEN; - - /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* IRC16M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 16, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ - RCU_PLL = (16U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_IRC16M) | (7U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 168 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_168M_PLL_8M_HXTAL) -/*! - \brief configure the system clock to 168M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_168m_8m_hxtal(void) -{ - uint32_t timeout = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - while((0U == (RCU_CTL & RCU_CTL_HXTALSTB)) && (HXTAL_STARTUP_TIMEOUT != timeout++)){ - } - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 8, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ - RCU_PLL = (8U | (336 << 6U) | (((2 >> 1U) -1U) << 16U) | - (RCU_PLLSRC_HXTAL) | (7 << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 168 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_168M_PLL_25M_HXTAL) -/*! - \brief configure the system clock to 168M by PLL which selects HXTAL(25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_168m_25m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 25, PLL_N = 336, PLL_P = 2, PLL_Q = 7 */ - RCU_PLL = (25U | (336U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_HXTAL) | (7U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 168 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_200M_PLL_IRC16M) -/*! - \brief configure the system clock to 200M by PLL which selects IRC16M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_200m_irc16m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC16M */ - RCU_CTL |= RCU_CTL_IRC16MEN; - - /* wait until IRC16M is stable or the startup time is longer than IRC16M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC16MSTB); - }while((0U == stab_flag) && (IRC16M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC16MSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* IRC16M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 16, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ - RCU_PLL = (16U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_IRC16M) | (9U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 200 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_200M_PLL_8M_HXTAL) -/*! - \brief configure the system clock to 200M by PLL which selects HXTAL(8M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_200m_8m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 8, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ - RCU_PLL = (8U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_HXTAL) | (9U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 200 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#elif defined (__SYSTEM_CLOCK_200M_PLL_25M_HXTAL) -/*! - \brief configure the system clock to 200M by PLL which selects HXTAL(25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_200m_25m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - RCU_APB1EN |= RCU_APB1EN_PMUEN; - PMU_CTL |= PMU_CTL_LDOVS; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/2 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV2; - /* APB1 = AHB/4 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV4; - - /* Configure the main PLL, PSC = 25, PLL_N = 400, PLL_P = 2, PLL_Q = 9 */ - RCU_PLL = (25U | (400U << 6U) | (((2U >> 1U) - 1U) << 16U) | - (RCU_PLLSRC_HXTAL) | (9U << 24U)); - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* Enable the high-drive to extend the clock frequency to 200 Mhz */ - PMU_CTL |= PMU_CTL_HDEN; - while(0U == (PMU_CS & PMU_CS_HDRF)){ - } - - /* select the high-drive mode */ - PMU_CTL |= PMU_CTL_HDS; - while(0U == (PMU_CS & PMU_CS_HDSRF)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLLP; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLLP)){ - } -} - -#endif /* __SYSTEM_CLOCK_IRC16M */ -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate (void) -{ - uint32_t sws; - uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - - /* exponent of AHB, APB1 and APB2 clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC16M is selected as CK_SYS */ - case SEL_IRC16M: - SystemCoreClock = IRC16M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - /* PLLP is selected as CK_SYS */ - case SEL_PLLP: - /* get the value of PLLPSC[5:0] */ - pllpsc = GET_BITS(RCU_PLL, 0U, 5U); - plln = GET_BITS(RCU_PLL, 6U, 14U); - pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = (RCU_PLL & RCU_PLL_PLLSEL); - if (RCU_PLLSRC_HXTAL == pllsel) { - ck_src = HXTAL_VALUE; - } else { - ck_src = IRC16M_VALUE; - } - SystemCoreClock = ((ck_src / pllpsc) * plln)/pllp; - break; - /* IRC16M is selected as CK_SYS */ - default: - SystemCoreClock = IRC16M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - SystemCoreClock = SystemCoreClock >> clk_exp; -} diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h deleted file mode 100644 index e3cd89f728..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4.h +++ /dev/null @@ -1,1790 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4_simd.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4_simd.h deleted file mode 100644 index f9bceff1e5..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cm4_simd.h +++ /dev/null @@ -1,697 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.30 - * @date 17. February 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* not yet supported */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_SIMD_H */ diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h deleted file mode 100644 index 834bd17645..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,664 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmInstr.h b/bsp/gd32450z-eval/Libraries/CMSIS/core_cmInstr.h deleted file mode 100644 index fca425c51d..0000000000 --- a/bsp/gd32450z-eval/Libraries/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,916 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero - return(result); -} -#endif - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero -#endif - return(result); -} - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h deleted file mode 100644 index 4f6020a50a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_adc.h +++ /dev/null @@ -1,515 +0,0 @@ -/*! - \file gd32f4xx_adc.h - \brief definitions for the ADC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_ADC_H -#define GD32F4XX_ADC_H - -#include "gd32f4xx.h" - -/* ADC definitions */ -#define ADC0 ADC_BASE -#define ADC1 (ADC_BASE + 0x100U) -#define ADC2 (ADC_BASE + 0x200U) - -/* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ -#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */ -#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */ -#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization regular data register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ -#define ADC_STAT_ROVF BIT(5) /*!< regular data register overflow */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ -#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */ -#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted group */ -#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */ -#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for regular group */ -#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for regular channels */ -#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of regular channels */ - -/* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ - -/* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ - -/* ADC_SSTAT */ -#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */ -#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */ -#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */ -#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */ -#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */ -#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */ -#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */ -#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */ -#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */ -#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */ -#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */ -#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */ -#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */ -#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */ -#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */ -#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */ -#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */ -#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */ - -/* ADC_SYNCCTL */ -#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */ -#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */ -#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */ -#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */ -#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */ -#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */ -#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */ - -/* ADC_SYNCDATA */ -#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< regular data1 in ADC synchronization mode */ -#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< regular data2 in ADC synchronization mode */ - -/* constants definitions */ -/* ADC status flag */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ -#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - -/* ADC special function definitions */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* temperature sensor channel, internal reference voltage channel, VBAT channel */ -#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */ -#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */ - -/* ADC synchronization mode */ -#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel & inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel & trigger rotation mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode. ADC2 works independently */ -#define ADC_DAUL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */ -#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined regular parallel & inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined regular parallel & trigger rotation mode */ -#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */ -#define ADC_ALL_REGULAL_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in regular parallel mode */ -#define ADC_ALL_REGULAL_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */ -#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */ - -/* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ - -/* external trigger mode for regular and inserted channel */ -#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */ -#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */ -#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */ -#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */ - -/* ADC external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */ -#define ADC_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */ -#define ADC_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */ -#define ADC_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */ - -/* ADC external trigger select for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) -#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */ -#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */ -#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */ -#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */ -#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */ -#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */ -#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */ - -/* ADC channel sample time */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */ -#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */ -#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */ -#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */ -#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */ -#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */ -#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */ -#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */ - -/* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - -/* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - -/* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - -/* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - -/* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - -/* adc_ovsampctl register value */ -/* ADC resolution */ -#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */ -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ - -/* oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - -/* oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -/* triggered Oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ -#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ - -/* ADC interrupt flag */ -#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted group conversion interrupt */ -#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< regular data register overflow */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ -#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< regular data register overflow */ - -/* configure the ADC clock for all the ADCs */ -#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */ -#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */ -#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */ -#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */ -#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */ -#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */ -#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */ -#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */ - -/* ADC synchronization delay */ -#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */ -#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */ -#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */ -#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */ -#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */ -#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */ -#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */ -#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */ -#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */ -#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */ -#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */ -#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */ -#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */ -#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */ -#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */ -#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */ - -/* ADC synchronization DMA mode selection */ -#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */ -#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */ -#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */ - -/* end of conversion mode */ -#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of regular conversions, the EOC bit is set */ -#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each regular conversion, the EOC bit is set */ - -/* function declarations */ -/* initialization config */ -/* reset ADC */ -void adc_deinit(void); -/* configure the ADC clock for all the ADCs */ -void adc_clock_config(uint32_t prescaler); -/* enable or disable ADC special function */ -void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); -/* enable ADC interface */ -void adc_enable(uint32_t adc_periph); -/* disable ADC interface */ -void adc_disable(uint32_t adc_periph); -/* ADC calibration and reset calibration */ -void adc_calibration_enable(uint32_t adc_periph); -/* configure temperature sensor and internal reference voltage channel or VBAT channel function */ -void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue); -/* configure ADC resolution */ -void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); -/* configure ADC oversample mode */ -void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio); -/* enable ADC oversample mode */ -void adc_oversample_mode_enable(uint32_t adc_periph); -/* disable ADC oversample mode */ -void adc_oversample_mode_disable(uint32_t adc_periph); - -/* DMA config */ -/* enable DMA request */ -void adc_dma_mode_enable(uint32_t adc_periph); -/* disable DMA request */ -void adc_dma_mode_disable(uint32_t adc_periph); -/* when DMA=1, the DMA engine issues a request at end of each regular conversion */ -void adc_dma_request_after_last_enable(uint32_t adc_periph); -/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */ -void adc_dma_request_after_last_disable(uint32_t adc_periph); - -/* regular group and inserted group config */ -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source); -/* enable ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); -/* configure end of conversion mode */ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection); - -/* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); - -/* watchdog config */ -/* disable ADC analog watchdog single channel */ -void adc_watchdog_single_channel_disable(uint32_t adc_periph ); -/* enable ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); - -/* interrupt & flag functions */ -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag); -/* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); -/* get the bit state of ADCx software inserted channel start conversion */ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); - -/* ADC synchronization */ -/* configure the ADC sync mode */ -void adc_sync_mode_config(uint32_t sync_mode); -/* configure the delay between 2 sampling phases in ADC sync modes */ -void adc_sync_delay_config(uint32_t sample_delay); -/* configure ADC sync DMA mode selection */ -void adc_sync_dma_config(uint32_t dma_mode ); -/* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */ -void adc_sync_dma_request_after_last_enable(void); -/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */ -void adc_sync_dma_request_after_last_disable(void); -/* read ADC sync regular data register */ -uint32_t adc_sync_regular_data_read(void); - -#endif /* GD32F4XX_ADC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h deleted file mode 100644 index 7310f63a75..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_can.h +++ /dev/null @@ -1,753 +0,0 @@ -/*! - \file gd32f4xx_can.h - \brief definitions for the CAN - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-11-27, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_CAN_H -#define GD32F4XX_CAN_H - -#include "gd32f4xx.h" - -/* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ - -/* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ - -/* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ - -/* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ - -/* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ - -/* bits definitions */ -/* CAN_CTL */ -#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ -#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ -#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ -#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ -#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ -#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ -#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ -#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ -#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ -#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ - -/* CAN_STAT */ -#define CAN_STAT_IWS BIT(0) /*!< initial working state */ -#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ -#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ -#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ -#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ -#define CAN_STAT_TS BIT(8) /*!< transmitting state */ -#define CAN_STAT_RS BIT(9) /*!< receiving state */ -#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ -#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ - -/* CAN_TSTAT */ -#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ -#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ -#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ -#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ -#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ -#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ -#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ -#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ -#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ -#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ -#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ -#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ -#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ -#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ -#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ -#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ -#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ -#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ -#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ -#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ -#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - -/* CAN_RFIFO0 */ -#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ -#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ -#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - -/* CAN_RFIFO1 */ -#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ -#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ -#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ - -/* CAN_INTEN */ -#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ -#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ -#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ -#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ -#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ -#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ -#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ -#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ -#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ - -/* CAN_ERR */ -#define CAN_ERR_WERR BIT(0) /*!< warning error */ -#define CAN_ERR_PERR BIT(1) /*!< passive error */ -#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ -#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ -#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ -#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ - -/* CAN_BT */ -#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ -#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ -#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ -#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ -#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ -#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - -/* CAN_TMIx */ -#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ -#define CAN_TMI_FT BIT(1) /*!< frame type */ -#define CAN_TMI_FF BIT(2) /*!< frame format */ -#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_TMPx */ -#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ -#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_TMDATA0x */ -#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ -#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ -#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ -#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ - -/* CAN_TMDATA1x */ -#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ -#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ -#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ -#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ - -/* CAN_RFIFOMIx */ -#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ -#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ -#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_RFIFOMPx */ -#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ -#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ -#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_RFIFOMDATA0x */ -#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ -#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ -#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ -#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ - -/* CAN_RFIFOMDATA1x */ -#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ -#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ -#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ -#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ - -/* CAN_FCTL */ -#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ -#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ - -/* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ - -/* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ - -/* CAN_FAFIFO */ -#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ - -/* CAN_FW */ -#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ - -/* CAN_FxDATAy */ -#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ - -/* consts definitions */ -/* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) -#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ -#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ -#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ -#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ -#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ - -/* CAN flags */ -typedef enum -{ - /* flags in STAT register */ - CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ - CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ - CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ - CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ - CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ - CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ - CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ - CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ - CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ - /* flags in TSTAT register */ - CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ - CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ - CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ - CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ - CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ - CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ - CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ - CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ - CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ - CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ - CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ - /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ - /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ - /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -}can_flag_enum; - -/* CAN interrupt flags */ -typedef enum -{ - /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ - /* interrupt flags in TSTAT register */ - CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ - CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ - CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ - CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ - CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ - /* interrupt flags in ERR register */ - CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ - CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ - CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ - CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ -}can_interrupt_flag_enum; - -/* CAN initiliaze parameters struct */ -typedef struct -{ - uint8_t working_mode; /*!< CAN working mode */ - uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ - uint8_t time_segment_1; /*!< time segment 1 */ - uint8_t time_segment_2; /*!< time segment 2 */ - ControlStatus time_triggered; /*!< time triggered communication mode */ - ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ - ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ - ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ - ControlStatus trans_fifo_order; /*!< transmit FIFO order */ - uint16_t prescaler; /*!< baudrate prescaler */ -}can_parameter_struct; - -/* CAN transmit message struct */ -typedef struct -{ - uint32_t tx_sfid; /*!< standard format frame identifier */ - uint32_t tx_efid; /*!< extended format frame identifier */ - uint8_t tx_ff; /*!< format of frame, standard or extended format */ - uint8_t tx_ft; /*!< type of frame, data or remote */ - uint8_t tx_dlen; /*!< data length */ - uint8_t tx_data[8]; /*!< transmit data */ -}can_trasnmit_message_struct; - -/* CAN receive message struct */ -typedef struct -{ - uint32_t rx_sfid; /*!< standard format frame identifier */ - uint32_t rx_efid; /*!< extended format frame identifier */ - uint8_t rx_ff; /*!< format of frame, standard or extended format */ - uint8_t rx_ft; /*!< type of frame, data or remote */ - uint8_t rx_dlen; /*!< data length */ - uint8_t rx_data[8]; /*!< receive data */ - uint8_t rx_fi; /*!< filtering index */ -} can_receive_message_struct; - -/* CAN filter parameters struct */ -typedef struct -{ - uint16_t filter_list_high; /*!< filter list number high bits*/ - uint16_t filter_list_low; /*!< filter list number low bits */ - uint16_t filter_mask_high; /*!< filter mask number high bits */ - uint16_t filter_mask_low; /*!< filter mask number low bits */ - uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ - uint16_t filter_number; /*!< filter number */ - uint16_t filter_mode; /*!< filter mode, list or mask */ - uint16_t filter_bits; /*!< filter scale */ - ControlStatus filter_enable; /*!< filter work or not */ -}can_filter_parameter_struct; - -/* CAN errors */ -typedef enum -{ - CAN_ERROR_NONE = 0, /*!< no error */ - CAN_ERROR_FILL, /*!< fill error */ - CAN_ERROR_FORMATE, /*!< format error */ - CAN_ERROR_ACK, /*!< ACK error */ - CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ - CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ - CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG, /*!< software configure */ -}can_error_enum; - -/* transmit states */ -typedef enum -{ - CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ -}can_transmit_state_enum; - -typedef enum -{ - CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ - CAN_FILTER_STRUCT, /* CAN filter parameters struct */ - CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ - CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -}can_struct_type_enum; - -/* CAN baudrate prescaler*/ -#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) - -/* CAN bit segment 1*/ -#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) - -/* CAN bit segment 2*/ -#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) - -/* CAN resynchronization jump width*/ -#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) - -/* CAN communication mode*/ -#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) - -/* CAN FDATA high 16 bits */ -#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) - -/* CAN FDATA low 16 bits */ -#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) - -/* CAN1 filter start bank_number*/ -#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) - -/* CAN transmit mailbox extended identifier*/ -#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) - -/* CAN transmit mailbox standard identifier*/ -#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) - -/* transmit data byte 0 */ -#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 1 */ -#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 2 */ -#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 3 */ -#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* transmit data byte 4 */ -#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 5 */ -#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 6 */ -#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 7 */ -#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* receive mailbox extended identifier*/ -#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) - -/* receive mailbox standrad identifier*/ -#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) - -/* receive data length */ -#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) - -/* the index of the filter by which the frame is passed */ -#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) - -/* receive data byte 0 */ -#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) - -/* receive data byte 1 */ -#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) - -/* receive data byte 2 */ -#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) - -/* receive data byte 3 */ -#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) - -/* receive data byte 4 */ -#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) - -/* receive data byte 5 */ -#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) - -/* receive data byte 6 */ -#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) - -/* receive data byte 7 */ -#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) - -/* error number */ -#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) - -/* transmit error count */ -#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) - -/* receive error count */ -#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) - -/* CAN errors */ -#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ - -#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ - -/* CAN communication mode */ -#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ -#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ -#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ -#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ - -/* CAN resynchronisation jump width */ -#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ - -/* CAN time segment 1 */ -#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ -#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ -#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ -#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ -#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ -#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ -#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ -#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ -#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ - -/* CAN time segment 2 */ -#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ - -/* CAN mailbox number */ -#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ -#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ -#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ -#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ - -/* CAN frame format */ -#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ -#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ - -/* CAN receive fifo */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ - -/* frame number of receive fifo */ -#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ - -#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ -#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ - -/* CAN working mode */ -#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ -#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ -#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ - -/* filter bits */ -#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ -#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ - -/* filter mode */ -#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ -#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ - -/* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ - -/* frame type */ -#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ -#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ - -/* CAN timeout */ -#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ - -/* interrupt enable bits */ -#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ -#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ -#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ -#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ -#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ -#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ -#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ -#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ -#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ -#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ - -/* function declarations */ -/* deinitialize CAN */ -void can_deinit(uint32_t can_periph); -/* initialize CAN struct */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct); -/* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); -/* set can1 fliter start bank number */ -void can1_filter_start_bank(uint8_t start_bank); -/* enable functions */ -/* CAN debug freeze enable */ -void can_debug_freeze_enable(uint32_t can_periph); -/* CAN debug freeze disable */ -void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time trigger mode enable */ -void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time trigger mode disable */ -void can_time_trigger_mode_disable(uint32_t can_periph); - -/* transmit functions */ -/* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); -/* get CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); -/* stop CAN transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); -/* CAN release fifo */ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive message length */ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); -/* CAN working mode */ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); -/* CAN wakeup from sleep mode */ -ErrStatus can_wakeup(uint32_t can_periph); - -/* CAN get error */ -can_error_enum can_error_get(uint32_t can_periph); -/* get CAN receive error number */ -uint8_t can_receive_error_number_get(uint32_t can_periph); -/* get CAN transmit error number */ -uint8_t can_transmit_error_number_get(uint32_t can_periph); - -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* CAN get flag state */ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); -/* CAN clear flag state */ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag); -/* CAN get interrupt flag state */ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); -/* CAN clear interrupt flag state */ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); - -#endif /* GD32F4XX_CAN_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h deleted file mode 100644 index 01f2c6bc3f..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_crc.h +++ /dev/null @@ -1,80 +0,0 @@ -/*! - \file gd32f4xx_crc.h - \brief definitions for the CRC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_CRC_H -#define GD32F4XX_CRC_H - -#include "gd32f4xx.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ - - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ -void crc_data_register_reset(void); -/* read the value of the data register */ -uint32_t crc_data_register_read(void); - -/* read the value of the free data register */ -uint8_t crc_free_data_register_read(void); -/* write data to the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* calculate the CRC value of a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* calculate the CRC value of an array of 32-bit values */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32F4XX_CRC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h deleted file mode 100644 index 00e4e7f298..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ctc.h +++ /dev/null @@ -1,192 +0,0 @@ -/*! - \file gd32f4xx_ctc.h - \brief definitions for the CTC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_CTC_H -#define GD32F4XX_CTC_H - -#include "gd32f4xx.h" - -/* CTC definitions */ -#define CTC CTC_BASE - -/* registers definitions */ -#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */ -#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */ -#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */ -#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */ - -/* bits definitions */ -/* CTC_CTL0 */ -#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */ -#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */ -#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */ -#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */ -#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */ -#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */ -#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */ -#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */ - -/* CTC_CTL1 */ -#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */ -#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */ -#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */ -#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */ -#define CTC_CTL1_USBSOFSEL BIT(30) /*!< USBFS or USBHS SOF signal selection */ -#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */ - -/* CTC_STAT */ -#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */ -#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */ -#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */ -#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */ -#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */ -#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */ -#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */ -#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */ -#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */ - -/* CTC_INTC */ -#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */ -#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */ -#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */ -#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */ - -/* constants definitions */ -/* hardware automatically trim mode definitions */ -#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/ -#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/ - -/* reference signal source polarity definitions */ -#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/ -#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/ - -/* USBFS or USBHS SOF signal selection definitions */ -#define CTC_USBSOFSEL_USBHS CTC_CTL1_USBSOFSEL /*!< USBHS SOF signal is selected*/ -#define CTC_USBSOFSEL_USBFS ((uint32_t)0x00000000U) /*!< USBFS SOF signal is selected*/ - -/* reference signal source selection definitions */ -#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */ -#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */ -#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBSOF is selected */ - -/* reference signal source prescaler definitions */ -#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */ -#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */ -#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */ -#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */ -#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */ -#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */ -#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */ -#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */ - -/* CTC interrupt enable definitions */ -#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */ -#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */ -#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */ -#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */ - -/* CTC interrupt source definitions */ -#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */ -#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */ -#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */ -#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */ -#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */ - -/* CTC flag definitions */ -#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */ -#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */ -#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */ -#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */ -#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */ -#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */ -#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */ - -/* function declarations */ -/* reset ctc clock trim controller */ -void ctc_deinit(void); -/* enable CTC trim counter */ -void ctc_counter_enable(void); -/* disable CTC trim counter */ -void ctc_counter_disable(void); - -/* configure the IRC48M trim value */ -void ctc_irc48m_trim_value_config(uint8_t trim_value); -/* generate software reference source sync pulse */ -void ctc_software_refsource_pulse_generate(void); -/* configure hardware automatically trim mode */ -void ctc_hardware_trim_mode_config(uint32_t hardmode); - -/* configure reference signal source polarity */ -void ctc_refsource_polarity_config(uint32_t polarity); -/* select USBFS or USBHS SOF signal */ -void ctc_usbsof_signal_select(uint32_t usbsof); -/* select reference signal source */ -void ctc_refsource_signal_select(uint32_t refs); -/* configure reference signal source prescaler */ -void ctc_refsource_prescaler_config(uint32_t prescaler); -/* configure clock trim base limit value */ -void ctc_clock_limit_value_config(uint8_t limit_value); -/* configure CTC counter reload value */ -void ctc_counter_reload_value_config(uint16_t reload_value); - -/* read CTC counter capture value when reference sync pulse occurred */ -uint16_t ctc_counter_capture_value_read(void); -/* read CTC trim counter direction when reference sync pulse occurred */ -FlagStatus ctc_counter_direction_read(void); -/* read CTC counter reload value */ -uint16_t ctc_counter_reload_value_read(void); -/* read the IRC48M trim value */ -uint8_t ctc_irc48m_trim_value_read(void); - -/* interrupt & flag functions */ -/* enable the CTC interrupt */ -void ctc_interrupt_enable(uint32_t interrupt); -/* disable the CTC interrupt */ -void ctc_interrupt_disable(uint32_t interrupt); -/* get CTC interrupt flag */ -FlagStatus ctc_interrupt_flag_get(uint32_t int_flag); -/* clear CTC interrupt flag */ -void ctc_interrupt_flag_clear(uint32_t int_flag); -/* get CTC flag */ -FlagStatus ctc_flag_get(uint32_t flag); -/* clear CTC flag */ -void ctc_flag_clear(uint32_t flag); - -#endif /* GD32F4XX_CTC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h deleted file mode 100644 index 573fb31336..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dac.h +++ /dev/null @@ -1,270 +0,0 @@ -/*! - \file gd32f4xx_dac.h - \brief definitions for the DAC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_DAC_H -#define GD32F4XX_DAC_H - -#include "gd32f4xx.h" - -/* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 0U -#define DAC1 1U - -/* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ -#define DAC_STAT REG32(DAC + 0x34U) /*!< DAC status register */ - -/* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DDUDRIE0 BIT(13) /*!< DAC0 DMA underrun interrupt enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ -#define DAC_CTL_DDUDRIE1 BIT(29) /*!< DAC1 DMA underrun interrupt enable/disable bit */ - -/* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - -/* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - -/* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - -/* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - -/* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - -/* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - -/* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - -/* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - -/* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - -/* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - -/* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ - -/* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ - -/* DAC_STAT */ -#define DAC_STAT_DDUDR0 BIT(13) /*!< DAC0 DMA underrun flag */ -#define DAC_STAT_DDUDR1 BIT(29) /*!< DAC1 DMA underrun flag */ - -/* constants definitions */ -/* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - -/* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - -/* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ - -/* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ - -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ - -/* function declarations */ -/* initialization functions */ -/* deinitialize DAC */ -void dac_deinit(void); -/* enable DAC */ -void dac_enable(uint32_t dac_periph); -/* disable DAC */ -void dac_disable(uint32_t dac_periph); -/* enable DAC DMA */ -void dac_dma_enable(uint32_t dac_periph); -/* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); -/* enable DAC output buffer */ -void dac_output_buffer_enable(uint32_t dac_periph); -/* disable DAC output buffer */ -void dac_output_buffer_disable(uint32_t dac_periph); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); - -/* DAC trigger configuration */ -/* enable DAC trigger */ -void dac_trigger_enable(uint32_t dac_periph); -/* disable DAC trigger */ -void dac_trigger_disable(uint32_t dac_periph); -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); -/* enable DAC software trigger */ -void dac_software_trigger_enable(uint32_t dac_periph); -/* disable DAC software trigger */ -void dac_software_trigger_disable(uint32_t dac_periph); - -/* DAC wave mode configuration */ -/* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); -/* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); -/* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); - -/* DAC concurrent mode configuration */ -/* enable DAC concurrent mode */ -void dac_concurrent_enable(void); -/* disable DAC concurrent mode */ -void dac_concurrent_disable(void); -/* enable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_enable(void); -/* disable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_disable(void); -/* enable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_enable(void); -/* disable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_disable(void); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); -/* enable DAC concurrent interrupt */ -void dac_concurrent_interrupt_enable(void); -/* disable DAC concurrent interrupt */ -void dac_concurrent_interrupt_disable(void); - -/* DAC interrupt configuration */ -/* enable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_enable(uint32_t dac_periph); -/* disable DAC interrupt(DAC DMA underrun interrupt) */ -void dac_interrupt_disable(uint32_t dac_periph); -/* get the specified DAC flag(DAC DMA underrun flag) */ -FlagStatus dac_flag_get(uint32_t dac_periph); -/* clear the specified DAC flag(DAC DMA underrun flag) */ -void dac_flag_clear(uint32_t dac_periph); -/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ -FlagStatus dac_interrupt_flag_get(uint32_t dac_periph); -/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */ -void dac_interrupt_flag_clear(uint32_t dac_periph); - -#endif /* GD32F4XX_DAC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h deleted file mode 100644 index fde91597f7..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dbg.h +++ /dev/null @@ -1,161 +0,0 @@ -/*! - \file gd32f4xx_dbg.h - \brief definitions for the DBG - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_DBG_H -#define GD32F4XX_DBG_H - -#include "gd32f4xx.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ -#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */ -#define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL0 */ -#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ -#define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ - -/* DBG_CTL1 */ -#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */ -#define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */ -#define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */ -#define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */ -#define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */ -#define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */ -#define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */ -#define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */ -#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ -#define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */ -#define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */ -#define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */ - -/* DBG_CTL2 */ -#define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */ -#define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */ -#define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */ -#define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */ -#define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */ - -/* constants definitions */ -#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* define the peripheral debug hold bit position and its register index offset */ -#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) -#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) -#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register index */ -enum dbg_reg_idx -{ - DBG_IDX_CTL0 = 0x04U, - DBG_IDX_CTL1 = 0x08U, - DBG_IDX_CTL2 = 0x0CU -}; - -typedef enum -{ - DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */ - DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */ - DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */ - DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */ - DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */ - DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */ - DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */ - DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */ - DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */ - DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */ - DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */ - DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */ - DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */ - DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */ - DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */ - DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */ -}dbg_periph_enum; - -#define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) -#define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ -#define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ -#define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ -#define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ - -/* function declarations */ -/* deinitialize the DBG */ -void dbg_deinit(void); -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -/* enable trace pin assignment */ -void dbg_trace_pin_enable(void); -/* disable trace pin assignment */ -void dbg_trace_pin_disable(void); -/* set trace pin mode */ -void dbg_trace_pin_mode_set(uint32_t trace_mode); - -#endif /* GD32F4XX_DBG_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h deleted file mode 100644 index 4986d5afd4..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dci.h +++ /dev/null @@ -1,238 +0,0 @@ -/*! - \file gd32f4xx_dci.h - \brief definitions for the DCI - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_DCI_H -#define GD32F4XX_DCI_H - -#include "gd32f4xx.h" - -/* DCI definitions */ -#define DCI DCI_BASE - -/* registers definitions */ -#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */ -#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */ -#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */ -#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */ -#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */ -#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */ -#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */ -#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */ -#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */ -#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */ -#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */ - -/* bits definitions */ -/* DCI_CTL */ -#define DCI_CTL_CAP BIT(0) /*!< capture enable */ -#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */ -#define DCI_CTL_WDEN BIT(2) /*!< window enable */ -#define DCI_CTL_JM BIT(3) /*!< JPEG mode */ -#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */ -#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */ -#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */ -#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */ -#define DCI_CTL_FR BITS(8,9) /*!< frame rate */ -#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */ -#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */ - -/* DCI_STAT0 */ -#define DCI_STAT0_HS BIT(0) /*!< HS line status */ -#define DCI_STAT0_VS BIT(1) /*!< VS line status */ -#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */ - -/* DCI_STAT1 */ -#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */ -#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */ -#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */ -#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */ -#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */ - -/* DCI_INTEN */ -#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */ -#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */ -#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */ -#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */ -#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */ - -/* DCI_INTF */ -#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */ -#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */ -#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */ -#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */ -#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */ - -/* DCI_INTC */ -#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */ -#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */ -#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */ -#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */ -#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */ - -/* DCI_SC */ -#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */ -#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */ -#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */ -#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */ - -/* DCI_SCUNMSK */ -#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */ -#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */ -#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */ -#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */ - -/* DCI_CWSPOS */ -#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */ -#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */ - -/* DCI_CWSZ */ -#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */ -#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */ - -/* constants definitions */ -/* DCI parameter structure definitions */ -typedef struct -{ - uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */ - uint32_t clock_polarity; /*!< clock polarity selection */ - uint32_t hsync_polarity; /*!< horizontal polarity selection */ - uint32_t vsync_polarity; /*!< vertical polarity selection */ - uint32_t frame_rate; /*!< frame capture rate */ - uint32_t interface_format; /*!< digital camera interface format */ -}dci_parameter_struct; - -#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */ -#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */ - -#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */ -#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */ - -#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ -#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */ - -#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */ -#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/ - -#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U)) -#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */ -#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */ -#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */ - -#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U)) -#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */ -#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */ -#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */ -#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */ - -/* DCI interrupt constants definitions */ -#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */ -#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */ -#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */ -#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */ -#define DCI_INT_EL BIT(4) /*!< end of line interrupt */ - -/* DCI interrupt flag definitions */ -#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */ -#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */ -#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */ -#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */ -#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */ - -/* DCI flag definitions */ -#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */ -#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */ -#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */ -#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */ -#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */ -#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */ -#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */ -#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */ - -/* function declarations */ -/* initialization functions */ -/* DCI deinit */ -void dci_deinit(void); -/* initialize DCI registers */ -void dci_init(dci_parameter_struct* dci_struct); - -/* enable DCI function */ -void dci_enable(void); -/* disable DCI function */ -void dci_disable(void); -/* enable DCI capture */ -void dci_capture_enable(void); -/* disable DCI capture */ -void dci_capture_disable(void); -/* enable DCI jpeg mode */ -void dci_jpeg_enable(void); -/* disable DCI jpeg mode */ -void dci_jpeg_disable(void); - -/* function configuration */ -/* enable cropping window function */ -void dci_crop_window_enable(void); -/* disable cropping window function */ -void dci_crop_window_disable(void); -/* configure DCI cropping window */ -void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height); - -/* enable embedded synchronous mode */ -void dci_embedded_sync_enable(void); -/* disable embedded synchronous mode */ -void dci_embedded_sync_disable(void); -/* configure synchronous codes in embedded synchronous mode */ -void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); -/* configure synchronous codes unmask in embedded synchronous mode */ -void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end); - -/* read DCI data register */ -uint32_t dci_data_read(void); - -/* interrupt & flag functions */ -/* get specified flag */ -FlagStatus dci_flag_get(uint32_t flag); -/* enable specified DCI interrupt */ -void dci_interrupt_enable(uint32_t interrupt); -/* disable specified DCI interrupt */ -void dci_interrupt_disable(uint32_t interrupt); - - -/* get specified interrupt flag */ -FlagStatus dci_interrupt_flag_get(uint32_t int_flag); -/* clear specified interrupt flag */ -void dci_interrupt_flag_clear(uint32_t int_flag); - -#endif /* GD32F4XX_DCI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h deleted file mode 100644 index cac70b85eb..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_dma.h +++ /dev/null @@ -1,428 +0,0 @@ -/*! - \file gd32f4xx_dma.c - \brief definitions for the DMA - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_DMA_H -#define GD32F4XX_DMA_H - -#include "gd32f4xx.h" - -/* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ - -/* registers definitions */ -#define DMA_INTF0(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register 0 */ -#define DMA_INTF1(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag register 1 */ -#define DMA_INTC0(dmax) REG32((dmax) + 0x08U) /*!< DMA interrupt flag clear register 0 */ -#define DMA_INTC1(dmax) REG32((dmax) + 0x0CU) /*!< DMA interrupt flag clear register 1 */ - -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x18U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 0 memory 0 base address register */ -#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 0 memory 1 base address register */ -#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 0 FIFO control register */ - -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x2CU) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 1 memory 0 base address register */ -#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 1 memory 1 base address register */ -#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 1 FIFO control register */ - -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x40U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 2 memory 0 base address register */ -#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 2 memory 1 base address register */ -#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x54U) /*!< DMA channel 2 FIFO control register */ - -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 3 memory 0 base address register */ -#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x68U) /*!< DMA channel 3 memory 1 base address register */ -#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 3 FIFO control register */ - -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x7CU) /*!< DMA channel 4 memory 0 base address register */ -#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 4 memory 1 base address register */ -#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 4 FIFO control register */ - -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x90U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x94U) /*!< DMA channel 5 memory 0 base address register */ -#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x98U) /*!< DMA channel 5 memory 1 base address register */ -#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x9CU) /*!< DMA channel 5 FIFO control register */ - -#define DMA_CH6CTL(dmax) REG32((dmax) + 0xA0U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0xA4U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0xA8U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0xACU) /*!< DMA channel 6 memory 0 base address register */ -#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0xB0U) /*!< DMA channel 6 memory 1 base address register */ -#define DMA_CH6FCTL(dmax) REG32((dmax) + 0xB4U) /*!< DMA channel 6 FIFO control register */ - -#define DMA_CH7CTL(dmax) REG32((dmax) + 0xB8U) /*!< DMA channel 7 control register */ -#define DMA_CH7CNT(dmax) REG32((dmax) + 0xBCU) /*!< DMA channel 7 counter register */ -#define DMA_CH7PADDR(dmax) REG32((dmax) + 0xC0U) /*!< DMA channel 7 peripheral base address register */ -#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0xC4U) /*!< DMA channel 7 memory 0 base address register */ -#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0xC8U) /*!< DMA channel 7 memory 1 base address register */ -#define DMA_CH7FCTL(dmax) REG32((dmax) + 0xCCU) /*!< DMA channel 7 FIFO control register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_FEEIF BIT(0) /*!< FIFO error and exception flag */ -#define DMA_INTF_SDEIF BIT(2) /*!< single data mode exception flag */ -#define DMA_INTF_TAEIF BIT(3) /*!< transfer access error flag */ -#define DMA_INTF_HTFIF BIT(4) /*!< half transfer finish flag */ -#define DMA_INTF_FTFIF BIT(5) /*!< full transger finish flag */ - -/* DMA_INTC */ -#define DMA_INTC_FEEIFC BIT(0) /*!< clear FIFO error and exception flag */ -#define DMA_INTC_SDEIFC BIT(2) /*!< clear single data mode exception flag */ -#define DMA_INTC_TAEIFC BIT(3) /*!< clear single data mode exception flag */ -#define DMA_INTC_HTFIFC BIT(4) /*!< clear half transfer finish flag */ -#define DMA_INTC_FTFIFC BIT(5) /*!< clear full transger finish flag */ - -/* DMA_CHxCTL,x=0..7 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ -#define DMA_CHXCTL_SDEIE BIT(1) /*!< enable bit for channel x single data mode exception interrupt */ -#define DMA_CHXCTL_TAEIE BIT(2) /*!< enable bit for channel x tranfer access error interrupt */ -#define DMA_CHXCTL_HTFIE BIT(3) /*!< enable bit for channel x half transfer finish interrupt */ -#define DMA_CHXCTL_FTFIE BIT(4) /*!< enable bit for channel x full transfer finish interrupt */ -#define DMA_CHXCTL_TFCS BIT(5) /*!< transfer flow controller select */ -#define DMA_CHXCTL_TM BITS(6,7) /*!< transfer mode */ -#define DMA_CHXCTL_CMEN BIT(8) /*!< circulation mode */ -#define DMA_CHXCTL_PNAGA BIT(9) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(10) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(11,12) /*!< transfer width of peipheral */ -#define DMA_CHXCTL_MWIDTH BITS(13,14) /*!< transfer width of memory */ -#define DMA_CHXCTL_PAIF BIT(15) /*!< peripheral address increment fixed */ -#define DMA_CHXCTL_PRIO BITS(16,17) /*!< priority level */ -#define DMA_CHXCTL_SBMEN BIT(18) /*!< switch-buffer mode enable */ -#define DMA_CHXCTL_MBS BIT(19) /*!< memory buffer select */ -#define DMA_CHXCTL_PBURST BITS(21,22) /*!< transfer burst type of peripheral */ -#define DMA_CHXCTL_MBURST BITS(23,24) /*!< transfer burst type of memory */ -#define DMA_CHXCTL_PERIEN BITS(25,27) /*!< peripheral enable */ - -/* DMA_CHxCNT,x=0..7 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR,x=0..7 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxM0ADDR,x=0..7 */ -#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */ - -/* DMA_CHxM1ADDR,x=0..7 */ -#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */ - -/* DMA_CHxFCTL,x=0..7 */ -#define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */ -#define DMA_CHXFCTL_MDMEN BIT(2) /*!< multi-data mode enable */ -#define DMA_CHXFCTL_FCNT BITS(3,5) /*!< FIFO counter */ -#define DMA_CHXFCTL_FEEIE BIT(7) /*!< FIFO exception interrupt enable */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA Channel 0 */ - DMA_CH1, /*!< DMA Channel 1 */ - DMA_CH2, /*!< DMA Channel 2 */ - DMA_CH3, /*!< DMA Channel 3 */ - DMA_CH4, /*!< DMA Channel 4 */ - DMA_CH5, /*!< DMA Channel 5 */ - DMA_CH6, /*!< DMA Channel 6 */ - DMA_CH7 /*!< DMA Channel 7 */ -} dma_channel_enum; - -/* DMA peripheral select */ -typedef enum -{ - DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */ - DMA_SUBPERI1, /*!< DMA Peripheral 1 */ - DMA_SUBPERI2, /*!< DMA Peripheral 2 */ - DMA_SUBPERI3, /*!< DMA Peripheral 3 */ - DMA_SUBPERI4, /*!< DMA Peripheral 4 */ - DMA_SUBPERI5, /*!< DMA Peripheral 5 */ - DMA_SUBPERI6, /*!< DMA Peripheral 6 */ - DMA_SUBPERI7 /*!< DMA Peripheral 7 */ -} dma_subperipheral_enum; - -/* DMA multidata mode initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t periph_inc; /*!< peripheral increasing mode */ - - uint32_t memory0_addr; /*!< memory 0 base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t memory_inc; /*!< memory increasing mode */ - - uint32_t memory_burst_width; /*!< multi data mode enable */ - uint32_t periph_burst_width; /*!< multi data mode enable */ - uint32_t critical_value; /*!< FIFO critical */ - - uint32_t circular_mode; /*!< DMA circular mode */ - uint32_t direction; /*!< channel data transfer direction */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ -}dma_multi_data_parameter_struct; - -/* DMA singledata mode initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_inc; /*!< peripheral increasing mode */ - - uint32_t memory0_addr; /*!< memory 0 base address */ - uint32_t memory_inc; /*!< memory increasing mode */ - - uint32_t periph_memory_width; /*!< transfer data size of peripheral */ - - uint32_t circular_mode; /*!< DMA circular mode */ - uint32_t direction; /*!< channel data transfer direction */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ -} dma_single_data_parameter_struct; - -#define DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /*!< DMA channel flag shift */ - -/* DMA_register address */ -#define DMA_CHCTL(dma,channel) REG32(((dma) + 0x10U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(dma,channel) REG32(((dma) + 0x18U) + 0x18U*(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHM0ADDR(dma,channel) REG32(((dma) + 0x1CU) + 0x18U*(channel)) /*!< the address of DMA channel CHXM0ADDR register */ -#define DMA_CHM1ADDR(dma,channel) REG32(((dma) + 0x20U) + 0x18U*(channel)) /*!< the address of DMA channel CHXM1ADDR register */ -#define DMA_CHFCTL(dma,channel) REG32(((dma) + 0x24U) + 0x18U*(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* peripheral select */ -#define CHCTL_PERIEN(regval) (BITS(25,27) & ((uint32_t)(regval) << 25)) -#define DMA_PERIPH_0_SELECT CHCTL_PERIEN(0) /*!< peripheral 0 select */ -#define DMA_PERIPH_1_SELECT CHCTL_PERIEN(1) /*!< peripheral 1 select */ -#define DMA_PERIPH_2_SELECT CHCTL_PERIEN(2) /*!< peripheral 2 select */ -#define DMA_PERIPH_3_SELECT CHCTL_PERIEN(3) /*!< peripheral 3 select */ -#define DMA_PERIPH_4_SELECT CHCTL_PERIEN(4) /*!< peripheral 4 select */ -#define DMA_PERIPH_5_SELECT CHCTL_PERIEN(5) /*!< peripheral 5 select */ -#define DMA_PERIPH_6_SELECT CHCTL_PERIEN(6) /*!< peripheral 6 select */ -#define DMA_PERIPH_7_SELECT CHCTL_PERIEN(7) /*!< peripheral 7 select */ - -/* burst type of memory */ -#define CHCTL_MBURST(regval) (BITS(23,24) & ((uint32_t)(regval) << 23)) -#define DMA_MEMORY_BURST_SINGLE CHCTL_MBURST(0) /*!< single burst */ -#define DMA_MEMORY_BURST_4_BEAT CHCTL_MBURST(1) /*!< 4-beat burst */ -#define DMA_MEMORY_BURST_8_BEAT CHCTL_MBURST(2) /*!< 8-beat burst */ -#define DMA_MEMORY_BURST_16_BEAT CHCTL_MBURST(3) /*!< 16-beat burst */ - -/* burst type of peripheral */ -#define CHCTL_PBURST(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) -#define DMA_PERIPH_BURST_SINGLE CHCTL_PBURST(0) /*!< single burst */ -#define DMA_PERIPH_BURST_4_BEAT CHCTL_PBURST(1) /*!< 4-beat burst */ -#define DMA_PERIPH_BURST_8_BEAT CHCTL_PBURST(2) /*!< 8-beat burst */ -#define DMA_PERIPH_BURST_16_BEAT CHCTL_PBURST(3) /*!< 16-beat burst */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ - -/* transfer data width of memory */ -#define CHCTL_MWIDTH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data width of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data width of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data width of memory is 32-bit */ - -/* transfer data width of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -#define DMA_PERIPH_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data width of peripheral is 8-bit */ -#define DMA_PERIPH_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data width of peripheral is 16-bit */ -#define DMA_PERIPH_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data width of peripheral is 32-bit */ - -/* channel transfer mode */ -#define CHCTL_TM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DMA_PERIPH_TO_MEMORY CHCTL_TM(0) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPH CHCTL_TM(1) /*!< read from memory and write to peripheral */ -#define DMA_MEMORY_TO_MEMORY CHCTL_TM(2) /*!< read from memory and write to memory */ - -/* FIFO counter critical value */ -#define CHFCTL_FCCV(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DMA_FIFO_1_WORD CHFCTL_FCCV(0) /*!< critical value 1 word */ -#define DMA_FIFO_2_WORD CHFCTL_FCCV(1) /*!< critical value 2 word */ -#define DMA_FIFO_3_WORD CHFCTL_FCCV(2) /*!< critical value 3 word */ -#define DMA_FIFO_4_WORD CHFCTL_FCCV(3) /*!< critical value 4 word */ - -/* memory select */ -#define DMA_MEMORY_0 ((uint32_t)0x00000000U) /*!< select memory 0 */ -#define DMA_MEMORY_1 ((uint32_t)0x00000001U) /*!< select memory 1 */ - -/* DMA circular mode */ -#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000000U) /*!< circular mode enable */ -#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000001U) /*!< circular mode disable */ - -/* DMA flow controller select */ -#define DMA_FLOW_CONTROLLER_DMA ((uint32_t)0x00000000U) /*!< DMA is the flow controler */ -#define DMA_FLOW_CONTROLLER_PERI ((uint32_t)0x00000001U) /*!< peripheral is the flow controler */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_FIX ((uint32_t)0x00000002U) /*!< next address of peripheral is increasing fixed */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */ - -/* FIFO status */ -#define DMA_FIFO_STATUS_NODATA ((uint32_t)0x00000000U) /*!< the data in the FIFO less than 1 word */ -#define DMA_FIFO_STATUS_1_WORD ((uint32_t)0x00000001U) /*!< the data in the FIFO more than 1 word, less than 2 words */ -#define DMA_FIFO_STATUS_2_WORD ((uint32_t)0x00000002U) /*!< the data in the FIFO more than 2 word, less than 3 words */ -#define DMA_FIFO_STATUS_3_WORD ((uint32_t)0x00000003U) /*!< the data in the FIFO more than 3 word, less than 4 words */ -#define DMA_FIFO_STATUS_EMPTY ((uint32_t)0x00000004U) /*!< the data in the FIFO is empty */ -#define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */ - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */ -#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXFCTL register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ -#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ -#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ - -/* flag bits */ -#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */ -#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */ -#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */ - - -/* function declarations */ -/* DMA deinitialization and initialization functions */ -/* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); -/* initialize the DMA single data mode parameters struct with the default values */ -void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct); -/* initialize the DMA multi data mode parameters struct with the default values */ -void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct); -/* DMA single data mode initialize */ -void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct); -/* DMA multi data mode initialize */ -void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct); - -/* DMA configuration functions */ -/* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set DMA Memory base address */ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address); - -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); - -/* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); - -/* configure transfer burst beats of memory */ -void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat); -/* configure transfer burst beats of peripheral */ -void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat); -/* configure transfer data size of memory */ -void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize); -/* configure transfer data size of peripheral */ -void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize); - -/* configure next address increasement algorithm of memory */ -void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); -/* configure next address increasement algorithm of peripheral */ -void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm); - -/* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); - -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); - -/* DMA switch buffer mode config */ -void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select); -/* DMA using memory get */ -uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx); - -/* DMA channel peripheral select */ -void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph); -/* DMA flow controller configure */ -void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller); -/* DMA flow controller enable */ -void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue); -/* DMA FIFO status get */ -uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx); - -/* flag and interrupt functions */ -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); -/* clear DMA a channel flag */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt); -/* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); - -#endif /* GD32F4XX_DMA_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h deleted file mode 100644 index 1dfc880d37..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_enet.h +++ /dev/null @@ -1,1680 +0,0 @@ -/*! - \file gd32f4xx_enet.h - \brief definitions for the ENET - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_ENET_H -#define GD32F4XX_ENET_H - -#include "gd32f4xx.h" -#include - -#define IF_USE_EXTERNPHY_LIB 0 -#if (1 == IF_USE_EXTERNPHY_LIB) -#include "phy.h" -#endif - -#ifndef ENET_RXBUF_NUM -#define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ -#endif - -#ifndef ENET_TXBUF_NUM -#define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ -#endif - -#ifndef ENET_RXBUF_SIZE -#define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ -#endif - -#ifndef ENET_TXBUF_SIZE -#define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ -#endif - -//#define SELECT_DESCRIPTORS_ENHANCED_MODE - -//#define USE_DELAY - -#ifndef _PHY_H_ -#define DP83848 0 -#define LAN8700 1 -#define PHY_TYPE DP83848 - -#define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ - -/* PHY read write timeouts */ -#define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ -#define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ - -/* PHY delay */ -#define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ -#define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ - -/* PHY register address */ -#define PHY_REG_BCR 0U /*!< tranceiver basic control register */ -#define PHY_REG_BSR 1U /*!< tranceiver basic status register */ - -/* PHY basic control register */ -#define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ - -/* PHY basic status register */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ - -#if(PHY_TYPE == LAN8700) -#define PHY_SR 31U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ -#elif(PHY_TYPE == DP83848) -#define PHY_SR 16U /*!< tranceiver status register */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ -#endif /* PHY_TYPE */ - -#endif /* _PHY_H_ */ - - -/* ENET definitions */ -#define ENET ENET_BASE - -/* registers definitions */ -#define ENET_MAC_CFG REG32((ENET) + 0x0000U) /*!< ethernet MAC configuration register */ -#define ENET_MAC_FRMF REG32((ENET) + 0x0004U) /*!< ethernet MAC frame filter register */ -#define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ -#define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ -#define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ -#define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */ -#define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ -#define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ -#define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ -#define ENET_MAC_WUM REG32((ENET) + 0x002CU) /*!< ethernet MAC wakeup management register */ -#define ENET_MAC_DBG REG32((ENET) + 0x0034U) /*!< ethernet MAC debug register */ -#define ENET_MAC_INTF REG32((ENET) + 0x0038U) /*!< ethernet MAC interrupt flag register */ -#define ENET_MAC_INTMSK REG32((ENET) + 0x003CU) /*!< ethernet MAC interrupt mask register */ -#define ENET_MAC_ADDR0H REG32((ENET) + 0x0040U) /*!< ethernet MAC address 0 high register */ -#define ENET_MAC_ADDR0L REG32((ENET) + 0x0044U) /*!< ethernet MAC address 0 low register */ -#define ENET_MAC_ADDR1H REG32((ENET) + 0x0048U) /*!< ethernet MAC address 1 high register */ -#define ENET_MAC_ADDR1L REG32((ENET) + 0x004CU) /*!< ethernet MAC address 1 low register */ -#define ENET_MAC_ADDT2H REG32((ENET) + 0x0050U) /*!< ethernet MAC address 2 high register */ -#define ENET_MAC_ADDR2L REG32((ENET) + 0x0054U) /*!< ethernet MAC address 2 low register */ -#define ENET_MAC_ADDR3H REG32((ENET) + 0x0058U) /*!< ethernet MAC address 3 high register */ -#define ENET_MAC_ADDR3L REG32((ENET) + 0x005CU) /*!< ethernet MAC address 3 low register */ -#define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ - -#define ENET_MSC_CTL REG32((ENET) + 0x0100U) /*!< ethernet MSC control register */ -#define ENET_MSC_RINTF REG32((ENET) + 0x0104U) /*!< ethernet MSC receive interrupt flag register */ -#define ENET_MSC_TINTF REG32((ENET) + 0x0108U) /*!< ethernet MSC transmit interrupt flag register */ -#define ENET_MSC_RINTMSK REG32((ENET) + 0x010CU) /*!< ethernet MSC receive interrupt mask register */ -#define ENET_MSC_TINTMSK REG32((ENET) + 0x0110U) /*!< ethernet MSC transmit interrupt mask register */ -#define ENET_MSC_SCCNT REG32((ENET) + 0x014CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ -#define ENET_MSC_MSCCNT REG32((ENET) + 0x0150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ -#define ENET_MSC_TGFCNT REG32((ENET) + 0x0168U) /*!< ethernet MSC transmitted good frames counter register */ -#define ENET_MSC_RFCECNT REG32((ENET) + 0x0194U) /*!< ethernet MSC received frames with CRC error counter register */ -#define ENET_MSC_RFAECNT REG32((ENET) + 0x0198U) /*!< ethernet MSC received frames with alignment error counter register */ -#define ENET_MSC_RGUFCNT REG32((ENET) + 0x01C4U) /*!< ethernet MSC received good unicast frames counter register */ - -#define ENET_PTP_TSCTL REG32((ENET) + 0x0700U) /*!< ethernet PTP time stamp control register */ -#define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ -#define ENET_PTP_TSH REG32((ENET) + 0x0708U) /*!< ethernet PTP time stamp high register */ -#define ENET_PTP_TSL REG32((ENET) + 0x070CU) /*!< ethernet PTP time stamp low register */ -#define ENET_PTP_TSUH REG32((ENET) + 0x0710U) /*!< ethernet PTP time stamp update high register */ -#define ENET_PTP_TSUL REG32((ENET) + 0x0714U) /*!< ethernet PTP time stamp update low register */ -#define ENET_PTP_TSADDEND REG32((ENET) + 0x0718U) /*!< ethernet PTP time stamp addend register */ -#define ENET_PTP_ETH REG32((ENET) + 0x071CU) /*!< ethernet PTP expected time high register */ -#define ENET_PTP_ETL REG32((ENET) + 0x0720U) /*!< ethernet PTP expected time low register */ -#define ENET_PTP_TSF REG32((ENET) + 0x0728U) /*!< ethernet PTP time stamp flag register */ -#define ENET_PTP_PPSCTL REG32((ENET) + 0x072CU) /*!< ethernet PTP PPS control register */ - -#define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ -#define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ -#define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ -#define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ -#define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ -#define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ -#define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ -#define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ -#define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ -#define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ -#define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ -#define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ -#define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ -#define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ - -/* bits definitions */ -/* ENET_MAC_CFG */ -#define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ -#define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ -#define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ -#define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ -#define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ -#define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ -#define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ -#define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ -#define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ -#define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ -#define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ -#define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ -#define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ -#define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ -#define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ -#define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ - -/* ENET_MAC_FRMF */ -#define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ -#define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ -#define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ -#define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ -#define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ -#define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ -#define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ -#define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ -#define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ -#define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ -#define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ - -/* ENET_MAC_HLH */ -#define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ - -/* ENET_MAC_HLL */ -#define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ - -/* ENET_MAC_PHY_CTL */ -#define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ -#define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ -#define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ -#define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ -#define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ - -/* ENET_MAC_PHY_DATA */ -#define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ - -/* ENET_MAC_FCTL */ -#define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ -#define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ -#define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ -#define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ -#define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ -#define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ -#define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ - -/* ENET_MAC_VLT */ -#define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ -#define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ - -/* ENET_MAC_RWFF */ -#define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ - -/* ENET_MAC_WUM */ -#define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ -#define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ -#define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ -#define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ -#define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ -#define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ -#define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ - -/* ENET_MAC_DBG */ -#define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ -#define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ -#define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ -#define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ -#define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ -#define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ -#define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ -#define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ -#define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ -#define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ -#define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ -#define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ - -/* ENET_MAC_INTF */ -#define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ -#define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ -#define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ -#define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ -#define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ - -/* ENET_MAC_INTMSK */ -#define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ -#define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ - -/* ENET_MAC_ADDR0H */ -#define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ -#define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ - -/* ENET_MAC_ADDR0L */ -#define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ - -/* ENET_MAC_ADDR1H */ -#define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ -#define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR1L */ -#define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ - -/* ENET_MAC_ADDR2H */ -#define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ -#define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR2L */ -#define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ - -/* ENET_MAC_ADDR3H */ -#define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ -#define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ -#define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ -#define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ - -/* ENET_MAC_ADDR3L */ -#define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ - -/* ENET_MAC_FCTH */ -#define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ -#define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ - -/* ENET_MSC_CTL */ -#define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ -#define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ -#define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ -#define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ -#define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */ -#define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */ - -/* ENET_MSC_RINTF */ -#define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ -#define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ -#define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ - -/* ENET_MSC_TINTF */ -#define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ -#define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ -#define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ - -/* ENET_MSC_RINTMSK */ -#define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ -#define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ -#define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ - -/* ENET_MSC_TINTMSK */ -#define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ -#define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ - -/* ENET_MSC_SCCNT */ -#define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ - -/* ENET_MSC_MSCCNT */ -#define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ - -/* ENET_MSC_TGFCNT */ -#define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ - -/* ENET_MSC_RFCECNT */ -#define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ - -/* ENET_MSC_RFAECNT */ -#define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ - -/* ENET_MSC_RGUFCNT */ -#define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ - -/* ENET_PTP_TSCTL */ -#define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ - -#define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ -#define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ -#define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ -#define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ -#define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ -#define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ -#define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */ -#define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */ -#define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */ -#define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */ -#define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */ -#define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ -#define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ -#define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ -#define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ -#define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ - -/* ENET_PTP_SSINC */ -#define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ - -/* ENET_PTP_TSH */ -#define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ - -/* ENET_PTP_TSL */ -#define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ -#define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ - -/* ENET_PTP_TSUH */ -#define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ - -/* ENET_PTP_TSUL */ -#define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ -#define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ - -/* ENET_PTP_TSADDAND */ -#define ENET_PTP_TSADDAND_TMSA BITS(0,31) /*!< timestamp addend */ - -/* ENET_PTP_ETH */ -#define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ - -/* ENET_PTP_ETL */ -#define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ - -/* ENET_PTP_TSF */ -#define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ -#define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ - -/* ENET_PTP_PPSCTL */ -#define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ - -/* ENET_DMA_BCTL */ -#define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ -#define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ -#define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ -#define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ -#define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ -#define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ -#define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ -#define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ -#define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ -#define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ -#define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ -#define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ - -/* ENET_DMA_TPEN */ -#define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ - -/* ENET_DMA_RPEN */ -#define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ - -/* ENET_DMA_RDTADDR */ -#define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ - -/* ENET_DMA_TDTADDR */ -#define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ - -/* ENET_DMA_STAT */ -#define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ -#define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ -#define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ -#define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ -#define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ -#define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ -#define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ -#define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ -#define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ -#define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ -#define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ -#define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ -#define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ -#define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ -#define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ -#define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ -#define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ -#define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ -#define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ -#define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ -#define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ - -/* ENET_DMA_CTL */ -#define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ -#define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ -#define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ -#define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ -#define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ -#define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ -#define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ -#define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ -#define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ -#define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ -#define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ -#define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ - -/* ENET_DMA_INTEN */ -#define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ -#define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ -#define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ -#define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ -#define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ -#define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ -#define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ -#define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ -#define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ -#define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ -#define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ -#define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ -#define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ -#define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ - -/* ENET_DMA_MFBOCNT */ -#define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ -#define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ - -/* ENET_DMA_RSWDC */ -#define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ - -/* ENET_DMA_CTDADDR */ -#define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ - -/* ENET_DMA_CRDADDR */ -#define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ - -/* ENET_DMA_CTBADDR */ -#define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ - -/* ENET_DMA_CRBADDR */ -#define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ - -/* ENET DMA Tx descriptor TDES0 */ -#define ENET_TDES0_DB BIT(0) /*!< deferred */ -#define ENET_TDES0_UFE BIT(1) /*!< underflow error */ -#define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ -#define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ -#define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ -#define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ -#define ENET_TDES0_LCO BIT(9) /*!< late collision */ -#define ENET_TDES0_NCA BIT(10) /*!< no carrier */ -#define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ -#define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ -#define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ -#define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ -#define ENET_TDES0_ES BIT(15) /*!< error summary */ -#define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ -#define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ -#define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ -#define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ -#define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ -#define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ -#define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ -#define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ -#define ENET_TDES0_FSG BIT(28) /*!< first segment */ -#define ENET_TDES0_LSG BIT(29) /*!< last segment */ -#define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ -#define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ - -/* ENET DMA Tx descriptor TDES1 */ -#define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ -#define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ - -/* ENET DMA Tx descriptor TDES2 */ -#define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ - -/* ENET DMA Tx descriptor TDES3 */ -#define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/* ENET DMA Tx descriptor TDES6 */ -#define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ - -/* ENET DMA Tx descriptor TDES7 */ -#define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* ENET DMA Rx descriptor RDES0 */ -#define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ -#define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */ -#define ENET_RDES0_CERR BIT(1) /*!< CRC error */ -#define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ -#define ENET_RDES0_RERR BIT(3) /*!< receive error */ -#define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ -#define ENET_RDES0_FRMT BIT(5) /*!< frame type */ -#define ENET_RDES0_LCO BIT(6) /*!< late collision */ -#define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ -#define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ -#define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ -#define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ -#define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ -#define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ -#define ENET_RDES0_LERR BIT(12) /*!< length error */ -#define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ -#define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ -#define ENET_RDES0_ERRS BIT(15) /*!< error summary */ -#define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ -#define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ -#define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ - -/* ENET DMA Rx descriptor RDES1 */ -#define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ -#define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ -#define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ -#define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ -#define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ - -/* ENET DMA Rx descriptor RDES2 */ -#define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ - -/* ENET DMA Rx descriptor RDES3 */ -#define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/* ENET DMA Rx descriptor RDES4 */ -#define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ -#define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ -#define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ -#define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ -#define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ -#define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ -#define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ -#define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ -#define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ - -/* ENET DMA Rx descriptor RDES6 */ -#define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ - -/* ENET DMA Rx descriptor RDES7 */ -#define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* constants definitions */ -/* define bit position and its register index offset */ -#define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph) >> 6))) -#define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* ENET clock range judgement */ -#define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) - -/* define MAC address configuration and reference address */ -#define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) -#define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) -#define ENET_ADDRH_BASE ((ENET) + 0x40U) -#define ENET_ADDRL_BASE ((ENET) + 0x44U) -#define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) - -/* register offset */ -#define MAC_FCTL_REG_OFFSET ((uint16_t)0x0018U) /*!< MAC flow control register offset */ -#define MAC_WUM_REG_OFFSET ((uint16_t)0x002CU) /*!< MAC wakeup management register offset */ -#define MAC_INTF_REG_OFFSET ((uint16_t)0x0038U) /*!< MAC interrupt flag register offset */ -#define MAC_INTMSK_REG_OFFSET ((uint16_t)0x003CU) /*!< MAC interrupt mask register offset */ - -#define MSC_RINTF_REG_OFFSET ((uint16_t)0x0104U) /*!< MSC receive interrupt flag register offset */ -#define MSC_TINTF_REG_OFFSET ((uint16_t)0x0108U) /*!< MSC transmit interrupt flag register offset */ -#define MSC_RINTMSK_REG_OFFSET ((uint16_t)0x010CU) /*!< MSC receive interrupt mask register offset */ -#define MSC_TINTMSK_REG_OFFSET ((uint16_t)0x0110U) /*!< MSC transmit interrupt mask register offset */ -#define MSC_SCCNT_REG_OFFSET ((uint16_t)0x014CU) /*!< MSC transmitted good frames after a single collision counter register offset */ -#define MSC_MSCCNT_REG_OFFSET ((uint16_t)0x0150U) /*!< MSC transmitted good frames after more than a single collision counter register offset */ -#define MSC_TGFCNT_REG_OFFSET ((uint16_t)0x0168U) /*!< MSC transmitted good frames counter register offset */ -#define MSC_RFCECNT_REG_OFFSET ((uint16_t)0x0194U) /*!< MSC received frames with CRC error counter register offset */ -#define MSC_RFAECNT_REG_OFFSET ((uint16_t)0x0198U) /*!< MSC received frames with alignment error counter register offset */ -#define MSC_RGUFCNT_REG_OFFSET ((uint16_t)0x01C4U) /*!< MSC received good unicast frames counter register offset */ - -#define PTP_TSF_REG_OFFSET ((uint16_t)0x0728U) /*!< PTP time stamp flag register offset */ - -#define DMA_STAT_REG_OFFSET ((uint16_t)0x1014U) /*!< DMA status register offset */ -#define DMA_INTEN_REG_OFFSET ((uint16_t)0x101CU) /*!< DMA interrupt enable register offset */ -#define DMA_TDTADDR_REG_OFFSET ((uint16_t)0x1010U) /*!< DMA transmit descriptor table address register offset */ -#define DMA_CTDADDR_REG_OFFSET ((uint16_t)0x1048U) /*!< DMA current transmit descriptor address register */ -#define DMA_CTBADDR_REG_OFFSET ((uint16_t)0x1050U) /*!< DMA current transmit buffer address register */ -#define DMA_RDTADDR_REG_OFFSET ((uint16_t)0x100CU) /*!< DMA receive descriptor table address register */ -#define DMA_CRDADDR_REG_OFFSET ((uint16_t)0x104CU) /*!< DMA current receive descriptor address register */ -#define DMA_CRBADDR_REG_OFFSET ((uint16_t)0x1054U) /*!< DMA current receive buffer address register */ - -/* ENET status flag get */ -typedef enum -{ - /* ENET_MAC_WUM register */ - ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ - ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ - /* ENET_MAC_FCTL register */ - ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ - /* ENET_MAC_INTF register */ - ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_PTP_TSF register */ - ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ - ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ - ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ - ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ - ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_flag_enum; - -/* ENET stutus flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_flag_clear_enum; - -/* ENET interrupt enable/disable */ -typedef enum -{ - /* ENET_MAC_INTMSK register */ - ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ - ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ - /* ENET_MSC_RINTMSK register */ - ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ - ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ - ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ - /* ENET_MSC_TINTMSK register */ - ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ - ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ - ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ - /* ENET_DMA_INTEN register */ - ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ - ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ - ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ - ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ - ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ - ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ - ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ - ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ - ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ - ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ - ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ - ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ - ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ - ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ - ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ -}enet_int_enum; - -/* ENET interrupt flag get */ -typedef enum -{ - /* ENET_MAC_INTF register */ - ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ - ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ - ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ - ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ - ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ - /* ENET_MSC_RINTF register */ - ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ - ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ - ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ - /* ENET_MSC_TINTF register */ - ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ - ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ - ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ - ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ - ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ - ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ -}enet_int_flag_enum; - -/* ENET interrupt flag clear */ -typedef enum -{ - /* ENET_DMA_STAT register */ - ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ - ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ - ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ - ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ - ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ - ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ - ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ - ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ - ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ - ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ - ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ - ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ - ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ - ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ - ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ -}enet_int_flag_clear_enum; - -/* current RX/TX descriptor/buffer/descriptor table address get */ -typedef enum -{ - ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ - ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ - ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ - ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ - ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ - ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ -}enet_desc_reg_enum; - -/* MAC statistics counter get */ -typedef enum -{ - ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ - ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ - ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ - ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ - ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ - ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ -}enet_msc_counter_enum; - -/* function option, used for ENET initialization */ -typedef enum -{ - FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ - DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ - DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ - DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ - STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ - DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ - VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ - FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ - HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ - HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ - FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ - HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ - TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ - INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ -}enet_option_enum; - -/* phy mode and mac loopback configurations */ -typedef enum -{ - ENET_AUTO_NEGOTIATION = 0x01U, /*!< PHY auto negotiation */ - ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ - ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ - ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ - ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ - ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ -}enet_mediamode_enum; - -/* IP frame checksum function */ -typedef enum -{ - ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ - ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ - ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped */ -}enet_chksumconf_enum; - -/* received frame filter function */ -typedef enum -{ - ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ - ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ - ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ - ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ -}enet_frmrecept_enum; - -/* register group value get */ -typedef enum -{ - ALL_MAC_REG = 0U, /*!< MAC register group */ - ALL_MSC_REG = 22U, /*!< MSC register group */ - ALL_PTP_REG = 33U, /*!< PTP register group */ - ALL_DMA_REG = 44U, /*!< DMA register group */ -}enet_registers_type_enum; - -/* dma direction select */ -typedef enum -{ - ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ - ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ -}enet_dmadirection_enum; - -/* PHY operation direction select */ -typedef enum -{ - ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ - ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ -}enet_phydirection_enum; - -/* register operation direction select */ -typedef enum -{ - ENET_REG_READ, /*!< read register */ - ENET_REG_WRITE /*!< write register */ -}enet_regdirection_enum; - -/* ENET MAC addresses */ -typedef enum -{ - ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ - ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ - ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ - ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ -}enet_macaddress_enum; - -/* descriptor information */ -typedef enum -{ - TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ - TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ - RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ - RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ - RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ - RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ -}enet_descstate_enum; - -/* MSC counters preset mode */ -typedef enum -{ - ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ - ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ - ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ -}enet_msc_preset_enum; - -typedef enum{ - ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ - ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ - ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ - ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ - ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ - ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ - ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ - ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ - ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ - ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ - ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ - ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)), /*!< version 2 */ - ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ - ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)), /*!< only event type messages are taken snapshot */ - ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ - ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)), /*!< snapshot is only take for master node message */ - ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ -}enet_ptp_function_enum; - -/* structure for initialization of the ENET */ -typedef struct -{ - uint32_t option_enable; /*!< select which function to configure */ - uint32_t forward_frame; /*!< frame forward related parameters */ - uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ - uint32_t dma_maxburst; /*!< DMA max burst related parameters */ - uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ - uint32_t store_forward_mode; /*!< store forward mode related parameters */ - uint32_t dma_function; /*!< DMA control related parameters */ - uint32_t vlan_config; /*!< VLAN tag related parameters */ - uint32_t flow_control; /*!< flow control related parameters */ - uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ - uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ - uint32_t framesfilter_mode; /*!< frame filter control related parameters */ - uint32_t halfduplex_param; /*!< halfduplex related parameters */ - uint32_t timer_config; /*!< frame timer related parameters */ - uint32_t interframegap; /*!< inter frame gap related parameters */ -}enet_initpara_struct; - -/* structure for ENET DMA desciptors */ -typedef struct -{ - uint32_t status; /*!< status */ - uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ - uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ - uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE - uint32_t extended_status; /*!< extended status */ - uint32_t reserved; /*!< reserved */ - uint32_t timestamp_low; /*!< timestamp low */ - uint32_t timestamp_high; /*!< timestamp high */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -} enet_descriptors_struct; - -/* structure of PTP system time */ -typedef struct -{ - uint32_t second; /*!< second of system time */ - uint32_t subsecond; /*!< subsecond of system time */ - uint32_t sign; /*!< sign of system time */ -}enet_ptp_systime_struct; - -/* mac_cfg register value */ -#define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ -#define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ -#define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ -#define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ -#define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ - -#define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ -#define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ -#define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ -#define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ -#define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ -#define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ -#define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ -#define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ -#define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ - -#define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ -#define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ -#define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */ - -#define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ -#define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ - -#define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ -#define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ - -#define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ -#define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ - -#define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ -#define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ - -#define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ -#define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ - -#define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ -#define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ - -#define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ -#define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ - -#define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ -#define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ - -#define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ -#define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ - -#define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ -#define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ -#define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ - -#define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ -#define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ - -/* mac_frmf register value */ -#define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ -#define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ -#define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ -#define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ -#define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ - -#define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ -#define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ - -#define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ -#define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ -#define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ -#define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ -#define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ - -#define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ -#define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ - -#define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ -#define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ - -#define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ -#define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ - -#define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ -#define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ -#define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ -#define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ -#define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ -#define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ -#define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ - -#define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ -#define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ -#define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ -#define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ - -/* mac_phy_ctl register value */ -#define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ -#define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ -#define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */ -#define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ -#define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= HCLK/102 */ - -#define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ - -#define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ - -/* mac_phy_data register value */ -#define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ - -/* mac_fctl register value */ -#define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ -#define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ -#define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ -#define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ -#define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ - -#define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ -#define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ - -#define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ -#define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ - -#define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ -#define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ -#define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ - -#define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ -#define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ - -#define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ -#define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ - -#define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ -/* mac_vlt register value */ -#define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ - -#define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ -#define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ - -/* mac_wum register value */ -#define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ -#define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ -#define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ -#define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ -#define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ -#define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ -#define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ - -/* mac_dbg register value */ -#define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ -#define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ -#define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ -#define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ -#define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ -#define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ -#define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ -#define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ -#define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ -#define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ -#define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ -#define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ - -#define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */ - -#define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */ - -#define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */ - -#define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */ - -#define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ - -/* mac_addr0h register value */ -#define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ - -/* mac_addrxh register value, x = 1,2,3 */ -#define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ - -#define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ -#define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ -#define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ -#define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ -#define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ - -#define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ -#define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ - -/* mac_fcth register value */ -#define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0))<<8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ -#define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ -#define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ -#define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ -#define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ -#define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ -#define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ -#define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ - -#define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4))<<8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ -#define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ -#define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ -#define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ -#define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ - -/* msc_ctl register value */ -#define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ -#define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ -#define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ - -/* ptp_tsctl register value */ -#define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ -#define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ -#define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */ -#define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */ -#define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */ -#define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */ -#define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ - -/* ptp_ssinc register value */ -#define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ - -/* ptp_tsl register value */ -#define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ - -#define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ -#define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ - -#define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ - -/* ptp_tsul register value */ -#define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ - -#define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ -#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ - -/* ptp_ppsctl register value */ -#define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ -#define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ -#define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ -#define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ -#define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */ -#define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */ -#define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */ -#define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */ -#define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */ -#define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */ -#define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */ -#define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */ -#define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */ -#define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */ -#define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */ -#define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */ -#define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ - -/* dma_bctl register value */ -#define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ -#define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ - -#define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ -#define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ - -#define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ -#define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ -#define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ -#define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ -#define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ -#define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ -#define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ -#define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ -#define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ - -#define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ -#define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ -#define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ -#define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ -#define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ -#define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ - -#define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ -#define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ - -#define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ -#define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ -#define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ -#define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ -#define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ -#define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ -#define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ -#define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ -#define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ -#define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ -#define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ -#define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ - -#define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ -#define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ - -#define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ -#define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ - -#define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */ -#define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */ - -/* dma_stat register value */ -#define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ -#define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ -#define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ -#define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ -#define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ -#define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ -#define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ - -#define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ -#define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ -#define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ -#define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ -#define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ -#define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ -#define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ - -#define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ -#define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ -#define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ -#define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ - -/* dma_ctl register value */ -#define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ -#define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ -#define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ -#define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ - -#define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ -#define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ -#define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ -#define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ -#define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ -#define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ -#define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ -#define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ -#define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ - -#define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ -#define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ - -#define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ -#define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ - -#define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ -#define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ -#define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ - -#define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ -#define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ - -#define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF<<2) /*!< all frame received with error except runt error are forwarded to memory */ -#define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ -#define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF<<2) /*!< the function that all frame received with error except runt error are forwarded to memory */ - -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF<<2) /*!< forward undersized good frames */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ -#define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF<<2) /*!< the function that forwarding undersized good frames */ - -#define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ -#define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ -#define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ -/* dma_mfbocnt register value */ -#define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ - -#define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ - -/* dma_rswdc register value */ -#define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ - -/* dma tx descriptor tdes0 register value */ -#define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ -#define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ - -#define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ -#define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ -#define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ -#define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ -#define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ - -/* dma tx descriptor tdes1 register value */ -#define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ - -#define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ - -/* dma rx descriptor rdes0 register value */ -#define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ -#define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ - -/* dma rx descriptor rdes1 register value */ -#define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ -#define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ - -#define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ - -#define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ - -/* dma rx descriptor rdes4 register value */ -#define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ -#define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ - -#define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ -#define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ - -/* ENET register mask value */ -#define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ -#define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ -#define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ -#define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ -#define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000020U) /*!< TxDMA enhanced descriptor size */ -#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000020U) /*!< RxDMA enhanced descriptor size */ -#else -#define ETH_DMATXDESC_SIZE ((uint32_t)0x00000010U) /*!< TxDMA descriptor size */ -#define ETH_DMARXDESC_SIZE ((uint32_t)0x00000010U) /*!< RxDMA descriptor size */ -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* ENET remote wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ - -/* ENET frame size */ -#define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ - -/* ENET delay timeout */ -#define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ -#define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ - - - -/* function declarations */ -/* main function */ -/* deinitialize the ENET, and reset structure parameters for ENET initialization */ -void enet_deinit(void); -/* configure the parameters which are usually less cared for initialization */ -void enet_initpara_config(enet_option_enum option, uint32_t para); -/* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); -/* reset all core internal registers located in CLK_TX and CLK_RX */ -ErrStatus enet_software_reset(void); -/* check receive frame valid and return frame size */ -uint32_t enet_rxframe_size_get(void); -/* initialize the dma tx/rx descriptors's parameters in chain mode */ -void enet_descriptors_chain_init(enet_dmadirection_enum direction); -/* initialize the dma tx/rx descriptors's parameters in ring mode */ -void enet_descriptors_ring_init(enet_dmadirection_enum direction); -/* handle current received frame data to application buffer */ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); -/* handle current received frame but without data copy to application buffer */ -#define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) -/* handle application buffer data to transmit it */ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); -/* handle current transmit frame but without data copy from application buffer */ -#define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) -/* configure the transmit IP frame checksum offload calculation and insertion */ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); -/* ENET Tx and Rx function enable (include MAC and DMA module) */ -void enet_enable(void); -/* ENET Tx and Rx function disable (include MAC and DMA module) */ -void enet_disable(void); -/* configure MAC address */ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); -/* get MAC address */ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); - -/* get the ENET MAC/MSC/PTP/DMA status flag */ -FlagStatus enet_flag_get(enet_flag_enum enet_flag); -/* clear the ENET DMA status flag */ -void enet_flag_clear(enet_flag_clear_enum enet_flag); -/* enable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_enable(enet_int_enum enet_int); -/* disable ENET MAC/MSC/DMA interrupt */ -void enet_interrupt_disable(enet_int_enum enet_int); -/* get ENET MAC/MSC/DMA interrupt flag */ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); -/* clear ENET DMA interrupt flag */ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); - -/* MAC function */ -/* ENET Tx function enable (include MAC and DMA module) */ -void enet_tx_enable(void); -/* ENET Tx function disable (include MAC and DMA module) */ -void enet_tx_disable(void); -/* ENET Rx function enable (include MAC and DMA module) */ -void enet_rx_enable(void); -/* ENET Rx function disable (include MAC and DMA module) */ -void enet_rx_disable(void); -/* put registers value into the application buffer */ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); -/* get the enet debug status from the debug register */ -uint32_t enet_debug_status_get(uint32_t mac_debug); -/* enable the MAC address filter */ -void enet_address_filter_enable(enet_macaddress_enum mac_addr); -/* disable the MAC address filter */ -void enet_address_filter_disable(enet_macaddress_enum mac_addr); -/* configure the MAC address filter */ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); -/* PHY interface configuration (configure SMI clock and reset PHY chip) */ -ErrStatus enet_phy_config(void); -/* write to/read from a PHY register */ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); -/* enable the loopback function of phy chip */ -ErrStatus enet_phyloopback_enable(void); -/* disable the loopback function of phy chip */ -ErrStatus enet_phyloopback_disable(void); -/* enable ENET forward feature */ -void enet_forward_feature_enable(uint32_t feature); -/* disable ENET forward feature */ -void enet_forward_feature_disable(uint32_t feature); -/* enable ENET fliter feature */ -void enet_fliter_feature_enable(uint32_t feature); -/* disable ENET fliter feature */ -void enet_fliter_feature_disable(uint32_t feature); - -/* flow control function */ -/* generate the pause frame, ENET will send pause frame after enable transmit flow control */ -ErrStatus enet_pauseframe_generate(void); -/* configure the pause frame detect type */ -void enet_pauseframe_detect_config(uint32_t detect); -/* configure the pause frame parameters */ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); -/* configure the threshold of the flow control(deactive and active threshold) */ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); -/* enable ENET flow control feature */ -void enet_flowcontrol_feature_enable(uint32_t feature); -/* disable ENET flow control feature */ -void enet_flowcontrol_feature_disable(uint32_t feature); - -/* DMA function */ -/* get the dma transmit/receive process state */ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); -/* poll the dma transmission/reception enable */ -void enet_dmaprocess_resume(enet_dmadirection_enum direction); -/* check and recover the Rx process */ -void enet_rxprocess_check_recovery(void); -/* flush the ENET transmit fifo, and wait until the flush operation completes */ -ErrStatus enet_txfifo_flush(void); -/* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); -/* get the Tx or Rx descriptor information */ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); -/* get the number of missed frames during receiving */ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); - -/* descriptor function */ -/* get the bit flag of ENET dma descriptor */ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); -/* set the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); -/* clear the bit flag of ENET dma tx descriptor */ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ -void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); -/* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ -void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time); -/* drop current receive frame */ -void enet_rxframe_drop(void); -/* enable DMA feature */ -void enet_dma_feature_enable(uint32_t feature); -/* disable DMA feature */ -void enet_dma_feature_disable(uint32_t feature); - - -/* special enhanced mode function */ -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/* get the bit of extended status flag in ENET DMA descriptor */ -uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); -/* configure descriptor to work in enhanced mode */ -void enet_desc_select_enhanced_mode(void); -/* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */ -void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction); -/* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */ -void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction); -/* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */ -ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); -/* handle current received frame but without data copy to application buffer in PTP enhanced mode */ -#define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr)) -/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */ -ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); -/* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */ -#define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr)) - -#else - -/* configure descriptor to work in normal mode */ -void enet_desc_select_normal_mode(void); -/* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); -/* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); -/* handle current received frame but without data copy to application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) -/* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); -/* handle current transmit frame but without data copy from application buffer in PTP normal mode */ -#define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) - -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/* WUM function */ -/* wakeup frame filter register pointer reset */ -void enet_wum_filter_register_pointer_reset(void); -/* set the remote wakeup frame registers */ -void enet_wum_filter_config(uint32_t pdata[]); -/* enable wakeup management features */ -void enet_wum_feature_enable(uint32_t feature); -/* disable wakeup management features */ -void enet_wum_feature_disable(uint32_t feature); - -/* MSC function */ -/* reset the MAC statistics counters */ -void enet_msc_counters_reset(void); -/* enable the MAC statistics counter features */ -void enet_msc_feature_enable(uint32_t feature); -/* disable the MAC statistics counter features */ -void enet_msc_feature_disable(uint32_t feature); -/* configure MAC statistics counters preset mode */ -void enet_msc_counters_preset_config(enet_msc_preset_enum mode); -/* get MAC statistics counter */ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); - -/* PTP function */ -/* enable the PTP features */ -void enet_ptp_feature_enable(uint32_t feature); -/* disable the PTP features */ -void enet_ptp_feature_disable(uint32_t feature); -/* configure the PTP timestamp function */ -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); -/* configure the PTP system time subsecond increment value */ -void enet_ptp_subsecond_increment_config(uint32_t subsecond); -/* adjusting the PTP clock frequency only in fine update mode */ -void enet_ptp_timestamp_addend_config(uint32_t add); -/* initializing or adding/subtracting to second of the PTP system time */ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); -/* configure the PTP expected target time */ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); -/* get the PTP current system time */ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); -/* configure the PPS output frequency */ -void enet_ptp_pps_output_frequency_config(uint32_t freq); - - -/* internal function */ -/* reset the ENET initpara struct, call it before using enet_initpara_config() */ -void enet_initpara_reset(void); - - -#endif /* GD32F4XX_ENET_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h deleted file mode 100644 index 94baf2f6f3..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exmc.h +++ /dev/null @@ -1,809 +0,0 @@ -/*! - \file gd32f4xx_exmc.h - \brief definitions for the EXMC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_EXMC_H -#define GD32F4XX_EXMC_H - -#include "gd32f4xx.h" - -/* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ -#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ -#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ -#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ -#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ - -/* registers definitions */ -/* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */ - -#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */ -#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */ -#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */ - -#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */ -#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */ -#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */ - -#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */ -#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */ -#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */ - -/* NAND/PC card */ -#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */ -#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */ -#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */ -#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */ -#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ - -#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */ -#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */ -#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */ -#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */ -#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */ - -#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */ -#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */ -#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */ -#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */ -#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */ - -/* SDRAM */ -#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */ -#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */ - -#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */ -#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */ - -#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ -#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ -#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ -#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ - -/* SQPI PSRAM */ -#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ -#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ -#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ -#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ -#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ - -/* bits definitions */ -/* EXMC_SNCTLx,x=0..3 */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ -#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */ -#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ -#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */ -#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock config */ - -/* EXMC_SNTCFGx,x=0..3 */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ -#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ -#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* EXMC_SNWTCFGx,x=0..3 */ -#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ -#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ -#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ -#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ -#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ - -/* EXMC_NPCTLx,x=1..3 */ -#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ -#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ -#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ -#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ -#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ -#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ -#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ -#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ - -/* EXMC_NPINTENx,x=1..3 */ -#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ -#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ -#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ -#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ -#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ -#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ -#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ - -/* EXMC_NPCTCFGx,x=1..3 */ -#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ -#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ -#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ -#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ - -/* EXMC_NPATCFGx,x=1..3 */ -#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ -#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ -#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ -#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ - -/* EXMC_PIOTCFG3 */ -#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ -#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ -#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ -#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ - -/* EXMC_NECCx,x=1..2 */ -#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ - -/* EXMC_SDCTLx,x=0..1 */ -#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ -#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ -#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ -#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ -#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ -#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ -#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ -#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */ -#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ - -/* EXMC_SDTCFGx,x=0..1 */ -#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ -#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ -#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ -#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ -#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ -#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ -#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ - -/* EXMC_SDCMD */ -#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ -#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */ -#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */ -#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ -#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ - -/* EXMC_SDARI */ -#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ -#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ -#define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ - -/* EXMC_SDSTAT */ -#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ -#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */ -#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */ -#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ - -/* EXMC_SDRSCTL */ -#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ -#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ -#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ - -/* EXMC_SINIT */ -#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ -#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ -#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ -#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ - -/* EXMC_SRCMD */ -#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ -#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ -#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ -#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ - -/* EXMC_SWCMD */ -#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */ -#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */ -#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */ -#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */ - -/* EXMC_SIDL */ -#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ - -/* EXMC_SIDH */ -#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ - -/* constants definitions */ -/* EXMC NOR/SRAM timing initialize structure */ -typedef struct -{ - uint32_t asyn_access_mode; /*!< asynchronous access mode */ - uint32_t syn_data_latency; /*!< configure the data latency */ - uint32_t syn_clk_division; /*!< configure the clock divide ratio */ - uint32_t bus_latency; /*!< configure the bus latency */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */ - uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */ -}exmc_norsram_timing_parameter_struct; - -/* EXMC NOR/SRAM initialize structure */ -typedef struct -{ - uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ - uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ - uint32_t extended_mode; /*!< enable or disable the extended mode */ - uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ - uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ - uint32_t memory_write; /*!< enable or disable the write operation */ - uint32_t nwait_config; /*!< NWAIT signal configuration */ - uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ - uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ - uint32_t burst_mode; /*!< enable or disable the burst mode */ - uint32_t databus_width; /*!< specifies the databus width of external memory */ - uint32_t memory_type; /*!< specifies the type of external memory */ - uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing - parameters for read if the extendedmode is used. */ - exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ -}exmc_norsram_parameter_struct; - -/* EXMC NAND/PC card timing initialize struct */ -typedef struct -{ - uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ - uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ - uint32_t waittime; /*!< configure the minimum wait time */ - uint32_t setuptime; /*!< configure the address setup time */ -}exmc_nand_pccard_timing_parameter_struct; - -/* EXMC NAND initialize struct */ -typedef struct -{ - uint32_t nand_bank; /*!< select the bank of NAND */ - uint32_t ecc_size; /*!< the page size for the ECC calculation */ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ - uint32_t databus_width; /*!< the NAND flash databus width */ - uint32_t wait_feature; /*!< enable or disable the wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ -}exmc_nand_parameter_struct; - -/* EXMC PC card initialize struct */ -typedef struct -{ - uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ - uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ - uint32_t wait_feature; /*!< enable or disable the wait feature */ - exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */ - exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */ - exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ -}exmc_pccard_parameter_struct; - -/* EXMC SDRAM timing initialize struct */ -typedef struct -{ - uint32_t row_to_column_delay; /*!< configure the row to column delay */ - uint32_t row_precharge_delay; /*!< configure the row precharge delay */ - uint32_t write_recovery_delay; /*!< configure the write recovery delay */ - uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ - uint32_t row_address_select_delay; /*!< configure the row address select delay */ - uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */ - uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ -}exmc_sdram_timing_parameter_struct; - -/* EXMC SDRAM initialize struct */ -typedef struct -{ - uint32_t sdram_device; /*!< device of SDRAM */ - uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ - uint32_t brust_read_switch; /*!< enable or disable the burst read */ - uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ - uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ - uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ - uint32_t internal_bank_number; /*!< the number of internal bank */ - uint32_t data_width; /*!< the databus width of SDRAM memory */ - uint32_t row_address_width; /*!< the bit width of a row address */ - uint32_t column_address_width; /*!< the bit width of a column address */ - exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */ -}exmc_sdram_parameter_struct; - -/* EXMC SDRAM command initialize struct */ -typedef struct -{ - uint32_t mode_register_content; /*!< the SDRAM mode register content */ - uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */ - uint32_t bank_select; /*!< the bank which command will be sent to */ - uint32_t command; /*!< the commands that will be sent to SDRAM */ -}exmc_sdram_command_parameter_struct; - -/* EXMC SQPISRAM initialize struct */ -typedef struct{ - uint32_t sample_polarity; /*!< read data sample polarity */ - uint32_t id_length; /*!< SPI PSRAM ID length */ - uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */ - uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */ -}exmc_sqpipsram_parameter_struct; - -/* EXMC_register address */ -#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ -#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ -#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ - -#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */ -#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */ -#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */ -#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */ -#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */ - -#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */ -#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */ - -/* CRAM page size */ -#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) -#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ -#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ -#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ -#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ -#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ - -/* NOR bank memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ - -/* NOR bank memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - -/* asynchronous access mode */ -#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) -#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ -#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ -#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ -#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ - -/* data latency for NOR flash */ -#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ -#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ -#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ -#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */ -#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */ -#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */ -#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */ -#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */ -#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */ -#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */ -#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */ -#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */ -#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */ -#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */ -#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */ -#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ - -/* synchronous clock divide ratio */ -#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) -#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ -#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ - -/* ECC size */ -#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ -#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ -#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ -#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */ -#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */ -#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ - -/* ALE to RE delay */ -#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) -#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ -#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ -#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ -#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ -#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ -#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ -#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ -#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ -#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ -#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ -#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ -#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ -#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ -#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ -#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ -#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ - -/* CLE to RE delay */ -#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) -#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ -#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ -#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ -#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ -#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ -#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ -#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ -#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ -#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ -#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ -#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ -#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ -#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ -#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ -#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ -#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ - -/* NAND bank memory data bus width */ -#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ -#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ - -/* SDRAM pipeline delay */ -#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) -#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ -#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ -#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ - -/* SDRAM clock configuration */ -#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) -#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ -#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ -#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ - -/* CAS latency */ -#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) -#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ -#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ -#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ - -/* SDRAM data bus width */ -#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ -#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ -#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ - -/* SDRAM row address bit width */ -#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ -#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ -#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ - -/* SDRAM column address bit width */ -#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ -#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ -#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ -#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ - -/* SDRAM number of successive auto-refresh */ -#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ -#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ -#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ - -/* SDRAM command select */ -#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ -#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ -#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ -#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ -#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ -#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ -#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ - -/* SDRAM the delayed sample clock of read data */ -#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ -#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ -#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ -#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ -#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ -#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ -#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ -#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ -#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ -#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ -#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ -#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ -#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ -#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ -#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ -#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ - -/* SPI PSRAM ID length */ -#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) -#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ -#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ - -/* SPI PSRAM bit number of address phase */ -#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) -#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ -#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ - -/* SPI PSRAM bit number of command phase */ -#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ -#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ - -/* SPI PSRAM read command mode */ -#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ -#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ - -/* SPI PSRAM write command mode */ -#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ -#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ - -/* EXMC NOR/SRAM bank region definition */ -#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ -#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ -#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ -#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ - -/* EXMC consecutive clock */ -#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ -#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */ - -/* EXMC NOR/SRAM write mode */ -#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ -#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ - -/* EXMC NWAIT signal configuration */ -#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ -#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ - -/* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ - -/* EXMC NAND/PC card bank definition */ -#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */ -#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */ -#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */ - -/* EXMC SDRAM bank definition */ -#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ -#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ - -/* EXMC SDRAM internal banks */ -#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ -#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ - -/* SDRAM device0 select */ -#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device0 unselect */ -#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< SDRAM device0 select */ - -/* SDRAM device1 select */ -#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< SDRAM device1 unselect */ -#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< SDRAM device1 select */ - -/* SDRAM device status */ -#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ -#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ -#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ - -/* sample cycle of read data */ -#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ -#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ - -/* read data sample polarity */ -#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ -#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */ - -/* SQPI SRAM command flag */ -#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ -#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ - -/* EXMC flag bits */ -#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ -#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ -#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ -#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ -#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ -#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ - -/* EXMC interrupt flag bits */ -#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */ -#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */ -#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */ -#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */ - -/* function declarations */ -/* initialization functions */ -/* NOR/SRAM */ -/* deinitialize EXMC NOR/SRAM region */ -void exmc_norsram_deinit(uint32_t exmc_norsram_region); -/* initialize exmc_norsram_parameter_struct with the default values */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* initialize EXMC NOR/SRAM region */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* enable EXMC NOR/SRAM region */ -void exmc_norsram_enable(uint32_t exmc_norsram_region); -/* disable EXMC NOR/SRAM region */ -void exmc_norsram_disable(uint32_t exmc_norsram_region); -/* NAND */ -/* deinitialize EXMC NAND bank */ -void exmc_nand_deinit(uint32_t exmc_nand_bank); -/* initialize exmc_norsram_parameter_struct with the default values */ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* initialize EXMC NAND bank */ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); -/* enable EXMC NAND bank */ -void exmc_nand_enable(uint32_t exmc_nand_bank); -/* disable EXMC NAND bank */ -void exmc_nand_disable(uint32_t exmc_nand_bank); -/* PC card */ -/* deinitialize EXMC PC card bank */ -void exmc_pccard_deinit(void); -/* initialize exmc_pccard_parameter_struct with the default values */ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* initialize EXMC PC card bank */ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); -/* enable EXMC PC card bank */ -void exmc_pccard_enable(void); -/* disable EXMC PC card bank */ -void exmc_pccard_disable(void); -/* SDRAM */ -/* deinitialize EXMC SDRAM device */ -void exmc_sdram_deinit(uint32_t exmc_sdram_device); -/* initialize exmc_sdram_parameter_struct with the default values */ -void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); -/* initialize EXMC SDRAM device */ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); -/* SQPIPSRAM */ -/* deinitialize EXMC SQPIPSRAM */ -void exmc_sqpipsram_deinit(void); -/* initialize exmc_sqpipsram_parameter_struct with the default values */ -void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); -/* initialize EXMC SQPIPSRAM */ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); - -/* function configuration */ -/* NOR/SRAM */ -/* configure consecutive clock */ -void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); -/* configure CRAM page size */ -void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); -/* NAND */ -/* enable or disable the EXMC NAND ECC function */ -void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); -/* get the EXMC ECC value */ -uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); -/* SDRAM */ -/* enable or disable read sample */ -void exmc_sdram_readsample_enable(ControlStatus newvalue); -/* configure the delayed sample clock of read data */ -void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); -/* configure the SDRAM memory command */ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct); -/* set auto-refresh interval */ -void exmc_sdram_refresh_count_set(uint32_t exmc_count); -/* set the number of successive auto-refresh command */ -void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); -/* config the write protection function */ -void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); -/* get the status of SDRAM device0 or device1 */ -uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); -/* SQPIPSRAM */ -/* set the read command */ -void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code); -/* set the write command */ -void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code); -/* send SPI read ID command */ -void exmc_sqpipsram_read_id_command_send(void); -/* send SPI special command which does not have address and data phase */ -void exmc_sqpipsram_write_cmd_send(void); -/* get the EXMC SPI ID low data */ -uint32_t exmc_sqpipsram_low_id_get(void); -/* get the EXMC SPI ID high data */ -uint32_t exmc_sqpipsram_high_id_get(void); -/* get the bit value of EXMC send write command bit or read ID command */ -FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag); - -/* interrupt & flag functions */ -/* enable EXMC interrupt */ -void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt); -/* disable EXMC interrupt */ -void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt); -/* get EXMC flag status */ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); -/* clear EXMC flag status */ -void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); -/* get EXMC interrupt flag */ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt); -/* clear EXMC interrupt flag */ -void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt); - -#endif /* GD32F4XX_EXMC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h deleted file mode 100644 index 3c2a27149d..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_exti.h +++ /dev/null @@ -1,277 +0,0 @@ -/*! - \file gd32f4xx_exti.h - \brief definitions for the EXTI - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_EXTI_H -#define GD32F4XX_EXTI_H - -#include "gd32f4xx.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ -#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ -#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ -#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ -#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ -#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ -#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ -#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ -#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ -#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ -#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */ -#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ -#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ -#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ -#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */ -#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ -#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ -#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ -#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */ -#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ -#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ -#define EXTI_PD_PD20 BIT(20) /*!< interrupt/event pending status from line 20 */ -#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ -#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum -{ - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ - EXTI_20 = BIT(20), /*!< EXTI line 20 */ - EXTI_21 = BIT(21), /*!< EXTI line 21 */ - EXTI_22 = BIT(22), /*!< EXTI line 22 */ -}exti_line_enum; - -/* external interrupt and event */ -typedef enum -{ - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum -{ - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ - EXTI_TRIG_NONE /*!< none EXTI edge trigger */ -}exti_trig_type_enum; - -/* function declarations */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); -/* EXTI software interrupt event enable */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* EXTI software interrupt event disable */ -void exti_software_interrupt_disable(exti_line_enum linex); - -/* interrupt & flag functions */ -/* get EXTI lines pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); - -#endif /* GD32F4XX_EXTI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h deleted file mode 100644 index 9b1b82c083..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fmc.h +++ /dev/null @@ -1,383 +0,0 @@ -/*! - \file gd32f4xx_fmc.h - \brief definitions for the FMC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F4XX_FMC_H -#define GD32F4XX_FMC_H - -#include "gd32f4xx.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option byte base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x0000U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x0004U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x0008U) /*!< FMC option byte unlock key register */ -#define FMC_STAT REG32((FMC) + 0x000CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x0010U) /*!< FMC control register */ -#define FMC_OBCTL0 REG32((FMC) + 0x0014U) /*!< FMC option byte control register 0 */ -#define FMC_OBCTL1 REG32((FMC) + 0x0018U) /*!< FMC option byte control register 1 */ -#define FMC_WSEN REG32((FMC) + 0x00FCU) /*!< FMC wait state enable register */ -#define FMC_PID REG32((FMC) + 0x0100U) /*!< FMC product ID register */ - -#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */ -#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/ -#define OB_SPC REG32((OB) + 0x00010001U) /*!< option byte security protection value */ -#define OB_WP0 REG32((OB) + 0x00010008U) /*!< option byte write protection 0 */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WC_WSCNT BITS(0,3) /*!< wait state counter */ - -/* FMC_KEY */ -#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option byte key bits */ - -/* FMC_STAT */ -#define FMC_STAT_END BIT(0) /*!< end of operation flag bit */ -#define FMC_STAT_OPERR BIT(1) /*!< flash operation error flag bit */ -#define FMC_STAT_WPERR BIT(4) /*!< erase/Program protection error flag bit */ -#define FMC_STAT_PGMERR BIT(6) /*!< program size not match error flag bit */ -#define FMC_STAT_PGSERR BIT(7) /*!< program sequence error flag bit */ -#define FMC_STAT_RDDERR BIT(8) /*!< read D-bus protection error flag bit */ -#define FMC_STAT_BUSY BIT(16) /*!< flash busy flag bit */ - -/* FMC_CTL */ -#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ -#define FMC_CTL_SER BIT(1) /*!< main flash sector erase command bit */ -#define FMC_CTL_MER0 BIT(2) /*!< main flash mass erase for bank0 command bit */ -#define FMC_CTL_SN BITS(3,7) /*!< select which sector number to be erased */ -#define FMC_CTL_PSZ BITS(8,9) /*!< program size bit */ -#define FMC_CTL_MER1 BIT(15) /*!< main flash mass erase for bank1 command bit */ -#define FMC_CTL_START BIT(16) /*!< send erase command to FMC bit */ -#define FMC_CTL_ENDIE BIT(24) /*!< end of operation interrupt enable bit */ -#define FMC_CTL_ERRIE BIT(25) /*!< error interrupt enable bit */ -#define FMC_CTL_LK BIT(31) /*!< FMC_CTL lock bit */ - -/* FMC_OBCTL0 */ -#define FMC_OBCTL0_OB_LK BIT(0) /*!< FMC_OBCTL0 lock bit */ -#define FMC_OBCTL0_OB_START BIT(1) /*!< send option byte change command to FMC bit */ -#define FMC_OBCTL0_BOR_TH BITS(2,3) /*!< option byte BOR threshold value */ -#define FMC_OBCTL0_BB BIT(4) /*!< option byte boot bank value */ -#define FMC_OBCTL0_NWDG_HW BIT(5) /*!< option byte watchdog value */ -#define FMC_OBCTL0_NRST_DPSLP BIT(6) /*!< option byte deepsleep reset value */ -#define FMC_OBCTL0_NRST_STDBY BIT(7) /*!< option byte standby reset value */ -#define FMC_OBCTL0_SPC BITS(8,15) /*!< option byte Security Protection code */ -#define FMC_OBCTL0_WP0 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ -#define FMC_OBCTL0_DBS BIT(30) /*!< double banks or single bank selection when flash size is 1M bytes */ -#define FMC_OBCTL0_DRP BIT(31) /*!< D-bus read protection bit */ - -/* FMC_OBCTL1 */ -#define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */ - -/* FMC_WSEN */ -#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_RDDERR, /*!< read D-bus protection error */ - FMC_PGSERR, /*!< program sequence error */ - FMC_PGMERR, /*!< program size not match error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_OPERR, /*!< operation error */ - FMC_PGERR, /*!< program error */ -}fmc_state_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */ -#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */ - -/* option byte write protection */ -#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ -#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ - -/* FMC wait state counter */ -#define WC_WSCNT(regval) (BITS(0,3) & ((uint32_t)(regval))) -#define WS_WSCNT_0 WC_WSCNT(0) /*!< FMC 0 wait */ -#define WS_WSCNT_1 WC_WSCNT(1) /*!< FMC 1 wait */ -#define WS_WSCNT_2 WC_WSCNT(2) /*!< FMC 2 wait */ -#define WS_WSCNT_3 WC_WSCNT(3) /*!< FMC 3 wait */ -#define WS_WSCNT_4 WC_WSCNT(4) /*!< FMC 4 wait */ -#define WS_WSCNT_5 WC_WSCNT(5) /*!< FMC 5 wait */ -#define WS_WSCNT_6 WC_WSCNT(6) /*!< FMC 6 wait */ -#define WS_WSCNT_7 WC_WSCNT(7) /*!< FMC 7 wait */ -#define WS_WSCNT_8 WC_WSCNT(8) /*!< FMC 8 wait */ -#define WS_WSCNT_9 WC_WSCNT(9) /*!< FMC 9 wait */ -#define WS_WSCNT_10 WC_WSCNT(10) /*!< FMC 10 wait */ -#define WS_WSCNT_11 WC_WSCNT(11) /*!< FMC 11 wait */ -#define WS_WSCNT_12 WC_WSCNT(12) /*!< FMC 12 wait */ -#define WS_WSCNT_13 WC_WSCNT(13) /*!< FMC 13 wait */ -#define WS_WSCNT_14 WC_WSCNT(14) /*!< FMC 14 wait */ -#define WS_WSCNT_15 WC_WSCNT(15) /*!< FMC 15 wait */ - -/* option byte BOR threshold value */ -#define OBCTL0_BOR_TH(regval) (BITS(2,3) & ((uint32_t)(regval))<< 2) -#define OB_BOR_TH_VALUE3 OBCTL0_BOR_TH(0) /*!< BOR threshold value 3 */ -#define OB_BOR_TH_VALUE2 OBCTL0_BOR_TH(1) /*!< BOR threshold value 2 */ -#define OB_BOR_TH_VALUE1 OBCTL0_BOR_TH(2) /*!< BOR threshold value 1 */ -#define OB_BOR_TH_OFF OBCTL0_BOR_TH(3) /*!< no BOR function */ - -/* option byte boot bank value */ -#define OBCTL0_BB(regval) (BIT(4) & ((uint32_t)(regval)<<4)) -#define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */ -#define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */ - -/* option byte software/hardware free watch dog timer */ -#define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5) -#define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */ -#define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */ - -/* option byte reset or not entering deep sleep mode */ -#define OBCTL0_NRST_DPSLP(regval) (BIT(6) & ((uint32_t)(regval))<< 6) -#define OB_DEEPSLEEP_NRST OBCTL0_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */ -#define OB_DEEPSLEEP_RST OBCTL0_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */ - -/* option byte reset or not entering standby mode */ -#define OBCTL0_NRST_STDBY(regval) (BIT(7) & ((uint32_t)(regval))<< 7) -#define OB_STDBY_NRST OBCTL0_NRST_STDBY(1) /*!< no reset when entering deepsleep mode */ -#define OB_STDBY_RST OBCTL0_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */ - -/* read protect configure */ -#define FMC_NSPC ((uint8_t)0xAAU) /*!< no security protection */ -#define FMC_LSPC ((uint8_t)0xABU) /*!< low security protection */ -#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */ - -/* option bytes write protection */ -#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ -#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ -#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ -#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ -#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ -#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ -#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ -#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ -#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ -#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ -#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ -#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */ -#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */ - -/* option bytes D-bus read protection */ -#define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */ -#define OB_DRP_1 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 1 */ -#define OB_DRP_2 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 2 */ -#define OB_DRP_3 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 3 */ -#define OB_DRP_4 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 4 */ -#define OB_DRP_5 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 5 */ -#define OB_DRP_6 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 6 */ -#define OB_DRP_7 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 7 */ -#define OB_DRP_8 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 8 */ -#define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */ -#define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */ -#define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */ -#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */ -#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */ -#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */ -#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */ -#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */ -#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */ -#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */ -#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */ -#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */ -#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */ -#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */ -#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */ - -/* double banks or single bank selection when flash size is 1M bytes */ -#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval)<<30)) -#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */ -#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */ - -/* option bytes D-bus read protection mode */ -#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval)<<31)) -#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */ -#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */ - -/* FMC sectors */ -#define CTL_SN(regval) (BITS(3,7) & ((uint32_t)(regval))<< 3) -#define CTL_SECTOR_NUMBER_0 CTL_SN(0) /*!< sector 0 */ -#define CTL_SECTOR_NUMBER_1 CTL_SN(1) /*!< sector 1 */ -#define CTL_SECTOR_NUMBER_2 CTL_SN(2) /*!< sector 2 */ -#define CTL_SECTOR_NUMBER_3 CTL_SN(3) /*!< sector 3 */ -#define CTL_SECTOR_NUMBER_4 CTL_SN(4) /*!< sector 4 */ -#define CTL_SECTOR_NUMBER_5 CTL_SN(5) /*!< sector 5 */ -#define CTL_SECTOR_NUMBER_6 CTL_SN(6) /*!< sector 6 */ -#define CTL_SECTOR_NUMBER_7 CTL_SN(7) /*!< sector 7 */ -#define CTL_SECTOR_NUMBER_8 CTL_SN(8) /*!< sector 8 */ -#define CTL_SECTOR_NUMBER_9 CTL_SN(9) /*!< sector 9 */ -#define CTL_SECTOR_NUMBER_10 CTL_SN(10) /*!< sector 10 */ -#define CTL_SECTOR_NUMBER_11 CTL_SN(11) /*!< sector 11 */ -#define CTL_SECTOR_NUMBER_24 CTL_SN(12) /*!< sector 24 */ -#define CTL_SECTOR_NUMBER_25 CTL_SN(13) /*!< sector 25 */ -#define CTL_SECTOR_NUMBER_26 CTL_SN(14) /*!< sector 26 */ -#define CTL_SECTOR_NUMBER_27 CTL_SN(15) /*!< sector 27 */ -#define CTL_SECTOR_NUMBER_12 CTL_SN(16) /*!< sector 12 */ -#define CTL_SECTOR_NUMBER_13 CTL_SN(17) /*!< sector 13 */ -#define CTL_SECTOR_NUMBER_14 CTL_SN(18) /*!< sector 14 */ -#define CTL_SECTOR_NUMBER_15 CTL_SN(19) /*!< sector 15 */ -#define CTL_SECTOR_NUMBER_16 CTL_SN(20) /*!< sector 16 */ -#define CTL_SECTOR_NUMBER_17 CTL_SN(21) /*!< sector 17 */ -#define CTL_SECTOR_NUMBER_18 CTL_SN(22) /*!< sector 18 */ -#define CTL_SECTOR_NUMBER_19 CTL_SN(23) /*!< sector 19 */ -#define CTL_SECTOR_NUMBER_20 CTL_SN(24) /*!< sector 20 */ -#define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */ -#define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */ -#define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */ - - -/* FMC program size */ -#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8) -#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */ -#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */ -#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */ - -/* FMC interrupt enable */ -#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */ -#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */ - -/* FMC flags */ -#define FMC_FLAG_END ((uint32_t)0x00000001U) /*!< FMC end of operation flag bit */ -#define FMC_FLAG_OPERR ((uint32_t)0x00000002U) /*!< FMC operation error flag bit */ -#define FMC_FLAG_WPERR ((uint32_t)0x00000010U) /*!< FMC erase/program protection error flag bit */ -#define FMC_FLAG_PGMERR ((uint32_t)0x00000040U) /*!< FMC program size not match error flag bit */ -#define FMC_FLAG_PGSERR ((uint32_t)0x00000080U) /*!< FMC program sequence error flag bit */ -#define FMC_FLAG_RDDERR ((uint32_t)0x00000100U) /*!< FMC read D-bus protection error flag bit */ -#define FMC_FLAG_BUSY ((uint32_t)0x00010000U) /*!< FMC busy flag */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* set the FMC wait state counter */ -void fmc_wscnt_set(uint32_t wscnt); -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* FMC erase sector */ -fmc_state_enum fmc_sector_erase(uint32_t fmc_sector); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC erase whole bank0 */ -fmc_state_enum fmc_bank0_erase(void); -/* FMC erase whole bank1 */ -fmc_state_enum fmc_bank1_erase(void); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); -/* FMC program a byte at the corresponding address */ -fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* send option byte change command */ -void ob_start(void); -/* erase option byte */ -void ob_erase(void); -/* enable write protect */ -void ob_write_protection_enable(uint32_t ob_wp); -/* disable write protect */ -void ob_write_protection_disable(uint32_t ob_wp); -/* enable erase/program protection and D-bus read protection */ -void ob_drp_enable(uint32_t ob_drp); -/* disable erase/program protection and D-bus read protection */ -void ob_drp_disable(uint32_t ob_drp); -/* set the option byte security protection level */ -void ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte user */ -void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby); -/* option byte BOR threshold value */ -void ob_user_bor_threshold(uint32_t ob_bor_th); -/* configure the boot mode */ -void ob_boot_mode_config(uint32_t boot_mode); -/* get the FMC option byte user */ -uint8_t ob_user_get(void); -/* get the FMC option byte write protection */ -uint16_t ob_write_protection0_get(void); -/* get the FMC option byte write protection */ -uint16_t ob_write_protection1_get(void); -/* get the FMC erase/program protection and D-bus read protection option bytes value */ -uint16_t ob_drp0_get(void); -/* get the FMC erase/program protection and D-bus read protection option bytes value */ -uint16_t ob_drp1_get(void); -/* get option byte security protection code value */ -FlagStatus ob_spc_get(void); -/* get the FMC threshold value */ -uint8_t ob_user_bor_threshold_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t fmc_int); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t fmc_int); -/* get flag set or reset */ -FlagStatus fmc_flag_get(uint32_t fmc_flag); -/* clear the FMC pending flag */ -void fmc_flag_clear(uint32_t fmc_flag); -/* return the FMC state */ -fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(void); - -#endif /* GD32F4XX_FMC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h deleted file mode 100644 index ebee04b637..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_fwdgt.h +++ /dev/null @@ -1,106 +0,0 @@ -/*! - \file gd32f4xx_fwdgt.h - \brief definitions for the FWDGT - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_FWDGT_H -#define GD32F4XX_FWDGT_H - -#include "gd32f4xx.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ - -/* constants definitions */ -/* psc register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32F4XX_FWDGT_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h deleted file mode 100644 index 81da899427..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_gpio.h +++ /dev/null @@ -1,408 +0,0 @@ -/*! - \file gd32f4xx_gpio.h - \brief definitions for the GPIO - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_GPIO_H -#define GD32F4XX_GPIO_H - -#include "gd32f4xx.h" - -/* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOE (GPIO_BASE + 0x00001000U) -#define GPIOF (GPIO_BASE + 0x00001400U) -#define GPIOG (GPIO_BASE + 0x00001800U) -#define GPIOH (GPIO_BASE + 0x00001C00U) -#define GPIOI (GPIO_BASE + 0x00002000U) - -/* registers definitions */ -#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */ -#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */ -#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */ -#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ -#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ -#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */ -#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */ - -/* bits definitions */ -/* GPIO_CTL */ -#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ -#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ -#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ -#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ -#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ -#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ -#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ -#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ -#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ -#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ -#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ -#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ -#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ -#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ -#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ -#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_OMODE */ -#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ -#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ -#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ -#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ -#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ -#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ -#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ -#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ -#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ -#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ -#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ -#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ -#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ -#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ -#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ -#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ - -/* GPIO_OSPD */ -#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ -#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ -#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ -#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ -#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ -#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ -#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ -#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ -#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ -#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ -#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ -#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ -#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ -#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ -#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ -#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ - -/* GPIO_PUD */ -#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ -#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ -#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ -#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ -#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ -#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ -#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ -#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ -#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ -#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ -#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ -#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ -#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ -#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ -#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ -#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* GPIO_AFSEL0 */ -#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ -#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ -#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ -#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ -#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ -#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ -#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ -#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ - -/* GPIO_AFSEL1 */ -#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ -#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ -#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ -#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ -#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ -#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ -#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ -#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_TG */ -#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ -#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ -#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ -#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ -#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ -#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ -#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ -#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ -#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ -#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ -#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ -#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ -#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ -#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ -#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ -#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* output mode definitions */ -#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ -#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ -#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ -#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ - -/* pull-up/ pull-down definitions */ -#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ -#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ -#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* GPIO mode configuration values */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) -#define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) - -/* GPIO pull-up/ pull-down values */ -#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) -#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) - -/* GPIO output speed values */ -#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) -#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) - -/* GPIO output type */ -#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ -#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ - -/* GPIO output max speed level */ -#define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */ -#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */ -#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */ -#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */ - -/* GPIO output max speed value */ -#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */ -#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */ -#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */ -#define GPIO_OSPEED_200MHZ GPIO_OSPEED_LEVEL3 /*!< output max speed 200MHz */ - -/* GPIO alternate function values */ -#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) -#define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) - -/* GPIO alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ -#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ -#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ -#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ -#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */ -#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */ -#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */ -#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */ -#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */ -#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */ -#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */ -#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */ -#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */ -#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */ -#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */ -#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* set GPIO mode */ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); -/* set GPIO output type and speed */ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* set GPIO alternate function */ -void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin); -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -/* toggle GPIO pin status */ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); -/* toggle GPIO port status */ -void gpio_port_toggle(uint32_t gpio_periph); - -#endif /* GD32F4XX_GPIO_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h deleted file mode 100644 index 121e42f497..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_i2c.h +++ /dev/null @@ -1,422 +0,0 @@ -/*! - \file gd32f4xx_i2c.h - \brief definitions for the I2C - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-04-16, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F4XX_I2C_H -#define GD32F4XX_I2C_H - -#include "gd32f4xx.h" - -/* I2Cx(x=0,1,2) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ -#define I2C2 (I2C_BASE+0x800U) /*!< I2C2 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0 */ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register 1 */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ -#define I2C_FCTL(i2cx) REG32((i2cx) + 0x24U) /*!< I2C filter control register */ -#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ - -/* I2Cx_FCTL */ -#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */ -#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */ - -/* I2Cx_SAMCS */ -#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ -#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ -#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ -#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ -#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ -#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ -#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ -#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ -#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */ -#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */ -#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */ - -/* constants definitions */ - -/* the digital noise filter can filter spikes's length */ -typedef enum { - I2C_DF_DISABLE, /*!< disable digital noise filter */ - I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */ - I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */ - I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */ - I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */ - I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */ - I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */ - I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */ - I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */ - I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */ - I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */ - I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */ - I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */ - I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */ - I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */ - I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */ -}i2c_digital_filter_enum; - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ - -/* I2C flags */ -typedef enum -{ - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TRS = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ - /* flags in SAMCS register */ - I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ - I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ - I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ - I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ -}i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ - /* interrupt flags in SAMCS register */ - I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ - I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ - I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ - I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ -}i2c_interrupt_flag_enum; - -/* I2C interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ - /* interrupt in SAMCS register */ - I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ - I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ - I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ - I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */ -}i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP is enabled */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP is disabled */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* enable dual-address mode */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); -/* disable dual-address mode */ -void i2c_dualaddr_disable(uint32_t i2c_periph); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); - -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* I2C analog noise filter disable */ -void i2c_analog_noise_filter_disable(uint32_t i2c_periph); -/* I2C analog noise filter enable */ -void i2c_analog_noise_filter_enable(uint32_t i2c_periph); -/* digital noise filter */ -void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara); - -/* enable SAM_V interface */ -void i2c_sam_enable(uint32_t i2c_periph); -/* disable SAM_V interface */ -void i2c_sam_disable(uint32_t i2c_periph); -/* enable SAM_V interface timeout detect */ -void i2c_sam_timeout_enable(uint32_t i2c_periph); -/* disable SAM_V interface timeout detect */ -void i2c_sam_timeout_disable(uint32_t i2c_periph); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); - -#endif /* GD32F4XX_I2C_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h deleted file mode 100644 index d9ae8ce33a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_ipa.h +++ /dev/null @@ -1,384 +0,0 @@ -/*! - \file gd32f4xx_ipa.h - \brief definitions for the IPA - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_IPA_H -#define GD32F4XX_IPA_H - -#include "gd32f4xx.h" - -/* TLI definitions */ -#define IPA IPA_BASE /*!< IPA base address */ - -/* bits definitions */ -/* registers definitions */ -#define IPA_CTL REG32(IPA + 0x00U) /*!< IPA control register */ -#define IPA_INTF REG32(IPA + 0x04U) /*!< IPA interrupt flag register */ -#define IPA_INTC REG32(IPA + 0x08U) /*!< IPA interrupt flag clear register */ -#define IPA_FMADDR REG32(IPA + 0x0CU) /*!< IPA foreground memory base address register */ -#define IPA_FLOFF REG32(IPA + 0x10U) /*!< IPA foreground line offset register */ -#define IPA_BMADDR REG32(IPA + 0x14U) /*!< IPA background memory base address register */ -#define IPA_BLOFF REG32(IPA + 0x18U) /*!< IPA background line offset register */ -#define IPA_FPCTL REG32(IPA + 0x1CU) /*!< IPA foreground pixel control register */ -#define IPA_FPV REG32(IPA + 0x20U) /*!< IPA foreground pixel value register */ -#define IPA_BPCTL REG32(IPA + 0x24U) /*!< IPA background pixel control register */ -#define IPA_BPV REG32(IPA + 0x28U) /*!< IPA background pixel value register */ -#define IPA_FLMADDR REG32(IPA + 0x2CU) /*!< IPA foreground LUT memory base address register */ -#define IPA_BLMADDR REG32(IPA + 0x30U) /*!< IPA background LUT memory base address register */ -#define IPA_DPCTL REG32(IPA + 0x34U) /*!< IPA destination pixel control register */ -#define IPA_DPV REG32(IPA + 0x38U) /*!< IPA destination pixel value register */ -#define IPA_DMADDR REG32(IPA + 0x3CU) /*!< IPA destination memory base address register */ -#define IPA_DLOFF REG32(IPA + 0x40U) /*!< IPA destination line offset register */ -#define IPA_IMS REG32(IPA + 0x44U) /*!< IPA image size register */ -#define IPA_LM REG32(IPA + 0x48U) /*!< IPA line mark register */ -#define IPA_ITCTL REG32(IPA + 0x4CU) /*!< IPA inter-timer control register */ - -/* IPA_CTL */ -#define IPA_CTL_TEN BIT(0) /*!< transfer enable */ -#define IPA_CTL_THU BIT(1) /*!< transfer hang up */ -#define IPA_CTL_TST BIT(2) /*!< transfer stop */ -#define IPA_CTL_TAEIE BIT(8) /*!< enable bit for transfer access error interrupt */ -#define IPA_CTL_FTFIE BIT(9) /*!< enable bit for full transfer finish interrup */ -#define IPA_CTL_TLMIE BIT(10) /*!< enable bit for transfer line mark interrupt */ -#define IPA_CTL_LACIE BIT(11) /*!< enable bit for LUT access conflict interrupt */ -#define IPA_CTL_LLFIE BIT(12) /*!< enable bit for LUT loading finish interrupt */ -#define IPA_CTL_WCFIE BIT(13) /*!< enable bit for wrong configuration interrupt */ -#define IPA_CTL_PFCM BITS(16,17) /*!< pixel format convert mode */ - -/* IPA_INTF */ -#define IPA_INTF_TAEIF BIT(0) /*!< transfer access error interrupt flag */ -#define IPA_INTF_FTFIF BIT(1) /*!< full transfer finish interrupt flag */ -#define IPA_INTF_TLMIF BIT(2) /*!< transfer line mark interrupt flag */ -#define IPA_INTF_LACIF BIT(3) /*!< LUT access conflict interrupt flag */ -#define IPA_INTF_LLFIF BIT(4) /*!< LUT loading finish interrupt flag */ -#define IPA_INTF_WCFIF BIT(5) /*!< wrong configuration interrupt flag */ - -/* IPA_INTC */ -#define IPA_INTC_TAEIFC BIT(0) /*!< clear bit for transfer access error interrupt flag */ -#define IPA_INTC_FTFIFC BIT(1) /*!< clear bit for full transfer finish interrupt flag */ -#define IPA_INTC_TLMIFC BIT(2) /*!< clear bit for transfer line mark interrupt flag */ -#define IPA_INTC_LACIFC BIT(3) /*!< clear bit for LUT access conflict interrupt flag */ -#define IPA_INTC_LLFIFC BIT(4) /*!< clear bit for LUT loading finish interrupt flag */ -#define IPA_INTC_WCFIFC BIT(5) /*!< clear bit for wrong configuration interrupt flag */ - -/* IPA_FMADDR */ -#define IPA_FMADDR_FMADDR BITS(0,31) /*!< foreground memory base address */ - -/* IPA_FLOFF */ -#define IPA_FLOFF_FLOFF BITS(0,13) /*!< foreground line offset */ - -/* IPA_BMADDR */ -#define IPA_BMADDR_BMADDR BITS(0,31) /*!< background memory base address */ - -/* IPA_BLOFF */ -#define IPA_BLOFF_BLOFF BITS(0,13) /*!< background line offset */ - -/* IPA_FPCTL */ -#define IPA_FPCTL_FPF BITS(0,3) /*!< foreground pixel format */ -#define IPA_FPCTL_FLPF BIT(4) /*!< foreground LUT pixel format */ -#define IPA_FPCTL_FLLEN BIT(5) /*!< foreground LUT loading enable */ -#define IPA_FPCTL_FCNP BITS(8,15) /*!< foreground LUT number of pixel */ -#define IPA_FPCTL_FAVCA BITS(16,17) /*!< foreground alpha value calculation algorithm */ -#define IPA_FPCTL_FPDAV BITS(24,31) /*!< foreground pre- defined alpha value */ - -/* IPA_FPV */ -#define IPA_FPV_FPDBV BITS(0,7) /*!< foreground pre-defined red value */ -#define IPA_FPV_FPDGV BITS(8,15) /*!< foreground pre-defined green value */ -#define IPA_FPV_FPDRV BITS(16,23) /*!< foreground pre-defined red value */ - -/* IPA_BPCTL */ -#define IPA_BPCTL_BPF BITS(0,3) /*!< background pixel format */ -#define IPA_BPCTL_BLPF BIT(4) /*!< background LUT pixel format */ -#define IPA_BPCTL_BLLEN BIT(5) /*!< background LUT loading enable */ -#define IPA_BPCTL_BCNP BITS(8,15) /*!< background LUT number of pixel */ -#define IPA_BPCTL_BAVCA BITS(16,17) /*!< background alpha value calculation algorithm */ -#define IPA_BPCTL_BPDAV BITS(24,31) /*!< background pre- defined alpha value */ - -/* IPA_BPV */ -#define IPA_BPV_BPDBV BITS(0,7) /*!< background pre-defined blue value */ -#define IPA_BPV_BPDGV BITS(8,15) /*!< background pre-defined green value */ -#define IPA_BPV_BPDRV BITS(16,23) /*!< background pre-defined red value */ - -/* IPA_FLMADDR */ -#define IPA_FLMADDR_FLMADDR BITS(0,31) /*!< foreground LUT memory base address */ - -/* IPA_BLMADDR */ -#define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */ - -/* IPA_DPCTL */ -#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */ - -/* IPA_DPV */ -/* destination pixel format ARGB8888 */ -#define IPA_DPV_DPDBV_0 BITS(0,7) /*!< destination pre-defined blue value */ -#define IPA_DPV_DPDGV_0 BITS(8,15) /*!< destination pre-defined green value */ -#define IPA_DPV_DPDRV_0 BITS(16,23) /*!< destination pre-defined red value */ -#define IPA_DPV_DPDAV_0 BITS(24,31) /*!< destination pre-defined alpha value */ - -/* destination pixel format RGB8888 */ -#define IPA_DPV_DPDBV_1 BITS(0,7) /*!< destination pre-defined blue value */ -#define IPA_DPV_DPDGV_1 BITS(8,15) /*!< destination pre-defined green value */ -#define IPA_DPV_DPDRV_1 BITS(16,23) /*!< destination pre-defined red value */ - -/* destination pixel format RGB565 */ -#define IPA_DPV_DPDBV_2 BITS(0,4) /*!< destination pre-defined blue value */ -#define IPA_DPV_DPDGV_2 BITS(5,10) /*!< destination pre-defined green value */ -#define IPA_DPV_DPDRV_2 BITS(11,15) /*!< destination pre-defined red value */ - -/* destination pixel format ARGB1555 */ -#define IPA_DPV_DPDBV_3 BITS(0,4) /*!< destination pre-defined blue value */ -#define IPA_DPV_DPDGV_3 BITS(5,9) /*!< destination pre-defined green value */ -#define IPA_DPV_DPDRV_3 BITS(10,14) /*!< destination pre-defined red value */ -#define IPA_DPV_DPDAV_3 BIT(15) /*!< destination pre-defined alpha value */ - -/* destination pixel format ARGB4444 */ -#define IPA_DPV_DPDBV_4 BITS(0,3) /*!< destination pre-defined blue value */ -#define IPA_DPV_DPDGV_4 BITS(4,7) /*!< destination pre-defined green value */ -#define IPA_DPV_DPDRV_4 BITS(8,11) /*!< destination pre-defined red value */ -#define IPA_DPV_DPDAV_4 BITS(12,15) /*!< destination pre-defined alpha value */ - -/* IPA_DMADDR */ -#define IPA_DMADDR_DMADDR BITS(0,31) /*!< destination memory base address */ - -/* IPA_DLOFF */ -#define IPA_DLOFF_DLOFF BITS(0,13) /*!< destination line offset */ - -/* IPA_IMS */ -#define IPA_IMS_HEIGHT BITS(0,15) /*!< height of the image to be processed */ -#define IPA_IMS_WIDTH BITS(16,29) /*!< width of the image to be processed */ - -/* IPA_LM */ -#define IPA_LM_LM BITS(0,15) /*!< line mark */ - -/* IPA_ITCTL */ -#define IPA_ITCTL_ITEN BIT(0) /*!< inter-timer enable */ -#define IPA_ITCTL_NCCI BITS(8,15) /*!< number of clock cycles interval */ - - -/* constants definitions */ -/* IPA foreground parameter struct definitions */ -typedef struct -{ - uint32_t foreground_memaddr; /*!< foreground memory base address */ - uint32_t foreground_lineoff; /*!< foreground line offset */ - uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */ - uint32_t foreground_alpha_algorithm; /*!< foreground alpha value calculation algorithm */ - uint32_t foreground_pf; /*!< foreground pixel format */ - uint32_t foreground_prered; /*!< foreground pre-defined red value */ - uint32_t foreground_pregreen; /*!< foreground pre-defined green value */ - uint32_t foreground_preblue; /*!< foreground pre-defined blue value */ -}ipa_foreground_parameter_struct; - -/* IPA background parameter struct definitions */ -typedef struct -{ - uint32_t background_memaddr; /*!< background memory base address */ - uint32_t background_lineoff; /*!< background line offset */ - uint32_t background_prealpha; /*!< background pre-defined alpha value */ - uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */ - uint32_t background_pf; /*!< background pixel format */ - uint32_t background_prered; /*!< background pre-defined red value */ - uint32_t background_pregreen; /*!< background pre-defined green value */ - uint32_t background_preblue; /*!< background pre-defined blue value */ -}ipa_background_parameter_struct; - -/* IPA destination parameter struct definitions */ -typedef struct -{ - uint32_t destination_memaddr; /*!< destination memory base address */ - uint32_t destination_lineoff; /*!< destination line offset */ - uint32_t destination_prealpha; /*!< destination pre-defined alpha value */ - uint32_t destination_pf; /*!< destination pixel format */ - uint32_t destination_prered; /*!< destination pre-defined red value */ - uint32_t destination_pregreen; /*!< destination pre-defined green value */ - uint32_t destination_preblue; /*!< destination pre-defined blue value */ - uint32_t image_width; /*!< width of the image to be processed */ - uint32_t image_height; /*!< height of the image to be processed */ -}ipa_destination_parameter_struct; - -/* destination pixel format */ -typedef enum -{ - IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */ - IPA_DPF_RGB888, /*!< destination pixel format RGB888 */ - IPA_DPF_RGB565, /*!< destination pixel format RGB565 */ - IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */ - IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */ -} ipa_dpf_enum; - -/* LUT pixel format */ -#define IPA_LUT_PF_ARGB8888 ((uint8_t)0x00U) /*!< LUT pixel format ARGB8888 */ -#define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */ - -/* Inter-timer */ -#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */ -#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */ - -/* IPA pixel format convert mode */ -#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */ -#define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */ -#define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */ -#define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */ - -/* foreground alpha value calculation algorithm */ -#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */ -#define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */ -#define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */ - -/* background alpha value calculation algorithm */ -#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */ -#define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */ -#define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */ - -/* foreground pixel format */ -#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) -#define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */ -#define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */ -#define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */ -#define FOREGROUND_PPF_ARG1555 FPCTL_PPF(3) /*!< foreground pixel format ARGB1555 */ -#define FOREGROUND_PPF_ARGB4444 FPCTL_PPF(4) /*!< foreground pixel format ARGB4444 */ -#define FOREGROUND_PPF_L8 FPCTL_PPF(5) /*!< foreground pixel format L8 */ -#define FOREGROUND_PPF_AL44 FPCTL_PPF(6) /*!< foreground pixel format AL44 */ -#define FOREGROUND_PPF_AL88 FPCTL_PPF(7) /*!< foreground pixel format AL88 */ -#define FOREGROUND_PPF_L4 FPCTL_PPF(8) /*!< foreground pixel format L4 */ -#define FOREGROUND_PPF_A8 FPCTL_PPF(9) /*!< foreground pixel format A8 */ -#define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */ - -/* background pixel format */ -#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval))) -#define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */ -#define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */ -#define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */ -#define BACKGROUND_PPF_ARG1555 BPCTL_PPF(3) /*!< background pixel format ARGB1555 */ -#define BACKGROUND_PPF_ARGB4444 BPCTL_PPF(4) /*!< background pixel format ARGB4444 */ -#define BACKGROUND_PPF_L8 BPCTL_PPF(5) /*!< background pixel format L8 */ -#define BACKGROUND_PPF_AL44 BPCTL_PPF(6) /*!< background pixel format AL44 */ -#define BACKGROUND_PPF_AL88 BPCTL_PPF(7) /*!< background pixel format AL88 */ -#define BACKGROUND_PPF_L4 BPCTL_PPF(8) /*!< background pixel format L4 */ -#define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */ -#define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */ - -/* IPA flags */ -#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ -#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ -#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ -#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ -#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ -#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ - -/* IPA interrupt enable or disable */ -#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */ -#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */ -#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */ -#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */ -#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */ -#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */ - -/* IPA interrupt flags */ -#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */ -#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */ -#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */ -#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */ -#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */ -#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */ - -/* function declarations */ -/* functions enable or disable, pixel format convert mode set */ -/* deinitialize IPA */ -void ipa_deinit(void); -/* enable IPA transfer */ -void ipa_transfer_enable(void); -/* enable IPA transfer hang up */ -void ipa_transfer_hangup_enable(void); -/* disable IPA transfer hang up */ -void ipa_transfer_hangup_disable(void); -/* enable IPA transfer stop */ -void ipa_transfer_stop_enable(void); -/* disable IPA transfer stop */ -void ipa_transfer_stop_disable(void); -/* enable IPA foreground LUT loading */ -void ipa_foreground_lut_loading_enable(void); -/* enable IPA background LUT loading */ -void ipa_background_lut_loading_enable(void); -/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */ -void ipa_pixel_format_convert_mode_set(uint32_t pfcm); - -/* structure initialization, foreground, background, destination and LUT initialization */ -/* initialize the structure of IPA foreground parameter struct with the default values, it is - suggested that call this function after an ipa_foreground_parameter_struct structure is defined */ -void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct); -/* initialize foreground parameters */ -void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct); -/* initialize the structure of IPA background parameter struct with the default values, it is - suggested that call this function after an ipa_background_parameter_struct structure is defined */ -void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct); -/* initialize background parameters */ -void ipa_background_init(ipa_background_parameter_struct* background_struct); -/* initialize the structure of IPA destination parameter struct with the default values, it is - suggested that call this function after an ipa_destination_parameter_struct structure is defined */ -void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct); -/* initialize destination parameters */ -void ipa_destination_init(ipa_destination_parameter_struct* destination_struct); -/* initialize IPA foreground LUT parameters */ -void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr); -/* initialize IPA background LUT parameters */ -void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr); - -/* configuration functions */ -/* configure IPA line mark */ -void ipa_line_mark_config(uint16_t line_num); -/* inter-timer enable or disable */ -void ipa_inter_timer_config(uint8_t timer_cfg); -/* configure the number of clock cycles interval */ -void ipa_interval_clock_num_config(uint8_t clk_num); - -/* flag and interrupt functions */ -/* get IPA flag status in IPA_INTF register */ -FlagStatus ipa_flag_get(uint32_t flag); -/* clear IPA flag in IPA_INTF register */ -void ipa_flag_clear(uint32_t flag); -/* enable IPA interrupt */ -void ipa_interrupt_enable(uint32_t int_flag); -/* disable IPA interrupt */ -void ipa_interrupt_disable(uint32_t int_flag); -/* get IPA interrupt flag */ -FlagStatus ipa_interrupt_flag_get(uint32_t int_flag); -/* clear IPA interrupt flag */ -void ipa_interrupt_flag_clear(uint32_t int_flag); - -#endif /* GD32F4XX_IPA_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h deleted file mode 100644 index 4be9181ed8..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_iref.h +++ /dev/null @@ -1,186 +0,0 @@ -/*! - \file gd32f4xx_iref.h - \brief definitions for the IREF - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_IREF_H -#define GD32F4XX_IREF_H - -#include "gd32f4xx.h" - -/* IREF definitions */ -#define IREF IREF_BASE /*!< IREF base address */ - -/* registers definitions */ -#define IREF_CTL REG32(IREF + 0x300U) /*!< IREF control register */ - -/* bits definitions */ -/* IREF_CTL */ -#define IREF_CTL_CSDT BITS(0,5) /*!< current step data */ -#define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */ -#define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */ -#define IREF_CTL_SSEL BIT(14) /*!< step selection */ -#define IREF_CTL_CREN BIT(15) /*!< current reference enable */ - -/* constants definitions */ -/* IREF current precision trim */ -#define CTL_CPT(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) -#define IREF_CUR_PRECISION_TRIM_0 CTL_CPT(0) /*!< IREF current precision trim 0 */ -#define IREF_CUR_PRECISION_TRIM_1 CTL_CPT(1) /*!< IREF current precision trim 1 */ -#define IREF_CUR_PRECISION_TRIM_2 CTL_CPT(2) /*!< IREF current precision trim 2 */ -#define IREF_CUR_PRECISION_TRIM_3 CTL_CPT(3) /*!< IREF current precision trim 3 */ -#define IREF_CUR_PRECISION_TRIM_4 CTL_CPT(4) /*!< IREF current precision trim 4 */ -#define IREF_CUR_PRECISION_TRIM_5 CTL_CPT(5) /*!< IREF current precision trim 5 */ -#define IREF_CUR_PRECISION_TRIM_6 CTL_CPT(6) /*!< IREF current precision trim 6 */ -#define IREF_CUR_PRECISION_TRIM_7 CTL_CPT(7) /*!< IREF current precision trim 7 */ -#define IREF_CUR_PRECISION_TRIM_8 CTL_CPT(8) /*!< IREF current precision trim 8 */ -#define IREF_CUR_PRECISION_TRIM_9 CTL_CPT(9) /*!< IREF current precision trim 9 */ -#define IREF_CUR_PRECISION_TRIM_10 CTL_CPT(10) /*!< IREF current precision trim 10 */ -#define IREF_CUR_PRECISION_TRIM_11 CTL_CPT(11) /*!< IREF current precision trim 11 */ -#define IREF_CUR_PRECISION_TRIM_12 CTL_CPT(12) /*!< IREF current precision trim 12 */ -#define IREF_CUR_PRECISION_TRIM_13 CTL_CPT(13) /*!< IREF current precision trim 13 */ -#define IREF_CUR_PRECISION_TRIM_14 CTL_CPT(14) /*!< IREF current precision trim 14 */ -#define IREF_CUR_PRECISION_TRIM_15 CTL_CPT(15) /*!< IREF current precision trim 15 */ -#define IREF_CUR_PRECISION_TRIM_16 CTL_CPT(16) /*!< IREF current precision trim 16 */ -#define IREF_CUR_PRECISION_TRIM_17 CTL_CPT(17) /*!< IREF current precision trim 17 */ -#define IREF_CUR_PRECISION_TRIM_18 CTL_CPT(18) /*!< IREF current precision trim 18 */ -#define IREF_CUR_PRECISION_TRIM_19 CTL_CPT(19) /*!< IREF current precision trim 19 */ -#define IREF_CUR_PRECISION_TRIM_20 CTL_CPT(20) /*!< IREF current precision trim 20 */ -#define IREF_CUR_PRECISION_TRIM_21 CTL_CPT(21) /*!< IREF current precision trim 21 */ -#define IREF_CUR_PRECISION_TRIM_22 CTL_CPT(22) /*!< IREF current precision trim 22 */ -#define IREF_CUR_PRECISION_TRIM_23 CTL_CPT(23) /*!< IREF current precision trim 23 */ -#define IREF_CUR_PRECISION_TRIM_24 CTL_CPT(24) /*!< IREF current precision trim 24 */ -#define IREF_CUR_PRECISION_TRIM_25 CTL_CPT(25) /*!< IREF current precision trim 25 */ -#define IREF_CUR_PRECISION_TRIM_26 CTL_CPT(26) /*!< IREF current precision trim 26 */ -#define IREF_CUR_PRECISION_TRIM_27 CTL_CPT(27) /*!< IREF current precision trim 27 */ -#define IREF_CUR_PRECISION_TRIM_28 CTL_CPT(28) /*!< IREF current precision trim 28 */ -#define IREF_CUR_PRECISION_TRIM_29 CTL_CPT(29) /*!< IREF current precision trim 29 */ -#define IREF_CUR_PRECISION_TRIM_30 CTL_CPT(30) /*!< IREF current precision trim 30 */ -#define IREF_CUR_PRECISION_TRIM_31 CTL_CPT(31) /*!< IREF current precision trim 31 */ - -/* IREF current step */ -#define CTL_CSDT(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) -#define IREF_CUR_STEP_DATA_0 CTL_CSDT(0) /*!< IREF current step data 0 */ -#define IREF_CUR_STEP_DATA_1 CTL_CSDT(1) /*!< IREF current step data 1 */ -#define IREF_CUR_STEP_DATA_2 CTL_CSDT(2) /*!< IREF current step data 2 */ -#define IREF_CUR_STEP_DATA_3 CTL_CSDT(3) /*!< IREF current step data 3 */ -#define IREF_CUR_STEP_DATA_4 CTL_CSDT(4) /*!< IREF current step data 4 */ -#define IREF_CUR_STEP_DATA_5 CTL_CSDT(5) /*!< IREF current step data 5 */ -#define IREF_CUR_STEP_DATA_6 CTL_CSDT(6) /*!< IREF current step data 6 */ -#define IREF_CUR_STEP_DATA_7 CTL_CSDT(7) /*!< IREF current step data 7 */ -#define IREF_CUR_STEP_DATA_8 CTL_CSDT(8) /*!< IREF current step data 8 */ -#define IREF_CUR_STEP_DATA_9 CTL_CSDT(9) /*!< IREF current step data 9 */ -#define IREF_CUR_STEP_DATA_10 CTL_CSDT(10) /*!< IREF current step data 10 */ -#define IREF_CUR_STEP_DATA_11 CTL_CSDT(11) /*!< IREF current step data 11 */ -#define IREF_CUR_STEP_DATA_12 CTL_CSDT(12) /*!< IREF current step data 12 */ -#define IREF_CUR_STEP_DATA_13 CTL_CSDT(13) /*!< IREF current step data 13 */ -#define IREF_CUR_STEP_DATA_14 CTL_CSDT(14) /*!< IREF current step data 14 */ -#define IREF_CUR_STEP_DATA_15 CTL_CSDT(15) /*!< IREF current step data 15 */ -#define IREF_CUR_STEP_DATA_16 CTL_CSDT(16) /*!< IREF current step data 16 */ -#define IREF_CUR_STEP_DATA_17 CTL_CSDT(17) /*!< IREF current step data 17 */ -#define IREF_CUR_STEP_DATA_18 CTL_CSDT(18) /*!< IREF current step data 18 */ -#define IREF_CUR_STEP_DATA_19 CTL_CSDT(19) /*!< IREF current step data 19 */ -#define IREF_CUR_STEP_DATA_20 CTL_CSDT(20) /*!< IREF current step data 20 */ -#define IREF_CUR_STEP_DATA_21 CTL_CSDT(21) /*!< IREF current step data 21 */ -#define IREF_CUR_STEP_DATA_22 CTL_CSDT(22) /*!< IREF current step data 22 */ -#define IREF_CUR_STEP_DATA_23 CTL_CSDT(23) /*!< IREF current step data 23 */ -#define IREF_CUR_STEP_DATA_24 CTL_CSDT(24) /*!< IREF current step data 24 */ -#define IREF_CUR_STEP_DATA_25 CTL_CSDT(25) /*!< IREF current step data 25 */ -#define IREF_CUR_STEP_DATA_26 CTL_CSDT(26) /*!< IREF current step data 26 */ -#define IREF_CUR_STEP_DATA_27 CTL_CSDT(27) /*!< IREF current step data 27 */ -#define IREF_CUR_STEP_DATA_28 CTL_CSDT(28) /*!< IREF current step data 28 */ -#define IREF_CUR_STEP_DATA_29 CTL_CSDT(29) /*!< IREF current step data 29 */ -#define IREF_CUR_STEP_DATA_30 CTL_CSDT(30) /*!< IREF current step data 30 */ -#define IREF_CUR_STEP_DATA_31 CTL_CSDT(31) /*!< IREF current step data 31 */ -#define IREF_CUR_STEP_DATA_32 CTL_CSDT(32) /*!< IREF current step data 32 */ -#define IREF_CUR_STEP_DATA_33 CTL_CSDT(33) /*!< IREF current step data 33 */ -#define IREF_CUR_STEP_DATA_34 CTL_CSDT(34) /*!< IREF current step data 34 */ -#define IREF_CUR_STEP_DATA_35 CTL_CSDT(35) /*!< IREF current step data 35 */ -#define IREF_CUR_STEP_DATA_36 CTL_CSDT(36) /*!< IREF current step data 36 */ -#define IREF_CUR_STEP_DATA_37 CTL_CSDT(37) /*!< IREF current step data 37 */ -#define IREF_CUR_STEP_DATA_38 CTL_CSDT(38) /*!< IREF current step data 38 */ -#define IREF_CUR_STEP_DATA_39 CTL_CSDT(39) /*!< IREF current step data 39 */ -#define IREF_CUR_STEP_DATA_40 CTL_CSDT(40) /*!< IREF current step data 40 */ -#define IREF_CUR_STEP_DATA_41 CTL_CSDT(41) /*!< IREF current step data 41 */ -#define IREF_CUR_STEP_DATA_42 CTL_CSDT(42) /*!< IREF current step data 42 */ -#define IREF_CUR_STEP_DATA_43 CTL_CSDT(43) /*!< IREF current step data 43 */ -#define IREF_CUR_STEP_DATA_44 CTL_CSDT(44) /*!< IREF current step data 44 */ -#define IREF_CUR_STEP_DATA_45 CTL_CSDT(45) /*!< IREF current step data 45 */ -#define IREF_CUR_STEP_DATA_46 CTL_CSDT(46) /*!< IREF current step data 46 */ -#define IREF_CUR_STEP_DATA_47 CTL_CSDT(47) /*!< IREF current step data 47 */ -#define IREF_CUR_STEP_DATA_48 CTL_CSDT(48) /*!< IREF current step data 48 */ -#define IREF_CUR_STEP_DATA_49 CTL_CSDT(49) /*!< IREF current step data 49 */ -#define IREF_CUR_STEP_DATA_50 CTL_CSDT(50) /*!< IREF current step data 50 */ -#define IREF_CUR_STEP_DATA_51 CTL_CSDT(51) /*!< IREF current step data 51 */ -#define IREF_CUR_STEP_DATA_52 CTL_CSDT(52) /*!< IREF current step data 52 */ -#define IREF_CUR_STEP_DATA_53 CTL_CSDT(53) /*!< IREF current step data 53 */ -#define IREF_CUR_STEP_DATA_54 CTL_CSDT(54) /*!< IREF current step data 54 */ -#define IREF_CUR_STEP_DATA_55 CTL_CSDT(55) /*!< IREF current step data 54 */ -#define IREF_CUR_STEP_DATA_56 CTL_CSDT(56) /*!< IREF current step data 54 */ -#define IREF_CUR_STEP_DATA_57 CTL_CSDT(57) /*!< IREF current step data 57 */ -#define IREF_CUR_STEP_DATA_58 CTL_CSDT(58) /*!< IREF current step data 58 */ -#define IREF_CUR_STEP_DATA_59 CTL_CSDT(59) /*!< IREF current step data 59 */ -#define IREF_CUR_STEP_DATA_60 CTL_CSDT(60) /*!< IREF current step data 60 */ -#define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */ -#define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */ -#define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */ - -/* IREF mode selection */ -#define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14)) -#define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */ -#define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */ - -/* IREF sink current mode*/ -#define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */ -#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */ - -/* function declarations */ -/* deinit IREF */ -void iref_deinit(void); -/* enable IREF */ -void iref_enable(void); -/* disable IREF */ -void iref_disable(void); - -/* set IREF mode*/ -void iref_mode_set(uint32_t step); -/* set IREF sink current mode*/ -void iref_sink_set(uint32_t sinkmode); -/* set IREF current precision trim value */ -void iref_precision_trim_value_set(uint32_t precisiontrim); -/* set IREF step data*/ -void iref_step_data_config(uint32_t stepdata); - -#endif /* GD32F4XX_IREF_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h deleted file mode 100644 index 21ae664c14..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_misc.h +++ /dev/null @@ -1,93 +0,0 @@ -/*! - \file gd32f4xx_misc.h - \brief definitions for the MISC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_MISC_H -#define GD32F4XX_MISC_H - -#include "gd32f4xx.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* priority group - define the pre-emption priority and the subpriority */ -#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ -#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ -#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ -#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ -#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ -/* set the priority group */ -void nvic_priority_group_set(uint32_t nvic_prigroup); - -/* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); -/* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32F4XX_MISC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h deleted file mode 100644 index f19b1cb2ec..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_pmu.h +++ /dev/null @@ -1,199 +0,0 @@ -/*! - \file gd32f4xx_pmu.h - \brief definitions for the PMU - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F4XX_PMU_H -#define GD32F4XX_PMU_H - -#include "gd32f4xx.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ -#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ -#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ -#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ -#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ -#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ -#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ -#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ -#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ -#define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - -/* PMU LDO output voltage select definitions */ -#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ -#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ -#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ - -/* PMU low-driver mode enable in deep-sleep mode */ -#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ -#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ - -/* PMU high-driver mode switch */ -#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) -#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ -#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ - -/* PMU low-driver mode when use low power LDO */ -#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) -#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ -#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ - -/* PMU low-driver mode when use normal power LDO */ -#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) -#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ -#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ - -/* PMU low power mode ready flag definitions */ -#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) -#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ -#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ - -/* PMU backup SRAM LDO on or off */ -#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9)) -#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ -#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ -#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ -#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ -#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ -#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ -#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU register */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* LDO output voltage select */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* PMU lvd disable */ -void pmu_lvd_disable(void); - -/* functions of low-driver mode and high-driver mode in deep-sleep mode */ -/* high-driver mode switch */ -void pmu_highdriver_switch_select(uint32_t highdr_switch); -/* high-driver mode enable */ -void pmu_highdriver_mode_enable(void); -/* high-driver mode disable */ -void pmu_highdriver_mode_disable(void); -/* low-driver mode enable in deep-sleep mode */ -void pmu_low_driver_mode_enable(uint32_t lowdr_mode); -/* in deep-sleep mode, low-driver mode when use low power LDO */ -void pmu_lowdriver_lowpower_config(uint32_t mode); -/* in deep-sleep mode, low-driver mode when use normal power LDO */ -void pmu_lowdriver_normalpower_config(uint32_t mode); - -/* set PMU mode */ -/* PMU work at sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* PMU wakeup pin enable */ -void pmu_wakeup_pin_enable(void); -/* PMU wakeup pin disable */ -void pmu_wakeup_pin_disable(void); - -/* backup related functions */ -/* backup SRAM LDO on */ -void pmu_backup_ldo_config(uint32_t bkp_ldo); -/* backup domain write enable */ -void pmu_backup_write_enable(void); -/* backup domain write disable */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* reset flag bit */ -void pmu_flag_reset(uint32_t flag_reset); -/* get flag status */ -FlagStatus pmu_flag_get(uint32_t pmu_flag); - -#endif /* GD32F4XX_PMU_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h deleted file mode 100644 index 0445df4eb0..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rcu.h +++ /dev/null @@ -1,1179 +0,0 @@ -/*! - \file gd32f4xx_rcu.h - \brief definitions for the RCU - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_RCU_H -#define GD32F4XX_RCU_H - -#include "gd32f4xx.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_PLL REG32(RCU + 0x04U) /*!< PLL register */ -#define RCU_CFG0 REG32(RCU + 0x08U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x0CU) /*!< clock interrupt register */ -#define RCU_AHB1RST REG32(RCU + 0x10U) /*!< AHB1 reset register */ -#define RCU_AHB2RST REG32(RCU + 0x14U) /*!< AHB2 reset register */ -#define RCU_AHB3RST REG32(RCU + 0x18U) /*!< AHB3 reset register */ -#define RCU_APB1RST REG32(RCU + 0x20U) /*!< APB1 reset register */ -#define RCU_APB2RST REG32(RCU + 0x24U) /*!< APB2 reset register */ -#define RCU_AHB1EN REG32(RCU + 0x30U) /*!< AHB1 enable register */ -#define RCU_AHB2EN REG32(RCU + 0x34U) /*!< AHB2 enable register */ -#define RCU_AHB3EN REG32(RCU + 0x38U) /*!< AHB3 enable register */ -#define RCU_APB1EN REG32(RCU + 0x40U) /*!< APB1 enable register */ -#define RCU_APB2EN REG32(RCU + 0x44U) /*!< APB2 enable register */ -#define RCU_AHB1SPEN REG32(RCU + 0x50U) /*!< AHB1 sleep mode enable register */ -#define RCU_AHB2SPEN REG32(RCU + 0x54U) /*!< AHB2 sleep mode enable register */ -#define RCU_AHB3SPEN REG32(RCU + 0x58U) /*!< AHB3 sleep mode enable register */ -#define RCU_APB1SPEN REG32(RCU + 0x60U) /*!< APB1 sleep mode enable register */ -#define RCU_APB2SPEN REG32(RCU + 0x64U) /*!< APB2 sleep mode enable register */ -#define RCU_BDCTL REG32(RCU + 0x70U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x74U) /*!< reset source / clock register */ -#define RCU_PLLSSCTL REG32(RCU + 0x80U) /*!< PLL clock spread spectrum control register */ -#define RCU_PLLI2S REG32(RCU + 0x84U) /*!< PLLI2S register */ -#define RCU_PLLSAI REG32(RCU + 0x88U) /*!< PLLSAI register */ -#define RCU_CFG1 REG32(RCU + 0x8CU) /*!< clock configuration register 1 */ -#define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ -#define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ -#define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ -#define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ -#define RCU_ADDAPB1SPEN REG32(RCU + 0xE8U) /*!< APB1 additional sleep mode enable register */ -#define RCU_VKEY REG32(RCU + 0x100U) /*!< voltage key register */ -#define RCU_DSV REG32(RCU + 0x134U) /*!< deep-sleep mode voltage register */ - -/* bits definitions */ -/* RCU_CTL */ -#define RCU_CTL_IRC16MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC16MSTB BIT(1) /*!< IRC16M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC16MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC16MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL Clock Stabilization Flag */ -#define RCU_CTL_PLLI2SEN BIT(26) /*!< PLLI2S enable */ -#define RCU_CTL_PLLI2SSTB BIT(27) /*!< PLLI2S Clock Stabilization Flag */ -#define RCU_CTL_PLLSAIEN BIT(28) /*!< PLLSAI enable */ -#define RCU_CTL_PLLSAISTB BIT(29) /*!< PLLSAI Clock Stabilization Flag */ - -/* RCU_PLL */ -#define RCU_PLL_PLLPSC BITS(0,5) /*!< The PLL VCO source clock prescaler */ -#define RCU_PLL_PLLN BITS(6,14) /*!< The PLL VCO clock multi factor */ -#define RCU_PLL_PLLP BITS(16,17) /*!< The PLLP output frequency division factor from PLL VCO clock */ -#define RCU_PLL_PLLSEL BIT(22) /*!< PLL Clock Source Selection */ -#define RCU_PLL_PLLQ BITS(24,27) /*!< The PLL Q output frequency division factor from PLL VCO clock */ - -/* RCU_CFG0 */ -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(10,12) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(13,15) /*!< APB2 prescaler selection */ -#define RCU_CFG0_RTCDIV BITS(16,20) /*!< RTC clock divider factor */ -#define RCU_CFG0_CKOUT0SEL BITS(21,22) /*!< CKOUT0 Clock Source Selection */ -#define RCU_CFG0_I2SSEL BIT(23) /*!< I2S Clock Source Selection */ -#define RCU_CFG0_CKOUT0DIV BITS(24,26) /*!< The CK_OUT0 divider which the CK_OUT0 frequency can be reduced */ -#define RCU_CFG0_CKOUT1DIV BITS(27,29) /*!< The CK_OUT1 divider which the CK_OUT1 frequency can be reduced */ -#define RCU_CFG0_CKOUT1SEL BITS(30,31) /*!< CKOUT1 Clock Source Selection */ - -/* RCU_INT */ -#define RCU_INT_IRC32KSTBIF BIT(0) /*!< IRC32K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC16MSTBIF BIT(2) /*!< IRC16M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_PLLI2SSTBIF BIT(5) /*!< PLLI2S stabilization interrupt flag */ -#define RCU_INT_PLLSAISTBIF BIT(6) /*!< PLLSAI stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC32KSTBIE BIT(8) /*!< IRC32K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC16MSTBIE BIT(10) /*!< IRC16M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_PLLI2SSTBIE BIT(13) /*!< PLLI2S Stabilization Interrupt Enable */ -#define RCU_INT_PLLSAISTBIE BIT(14) /*!< PLLSAI Stabilization Interrupt Enable */ -#define RCU_INT_IRC32KSTBIC BIT(16) /*!< IRC32K Stabilization Interrupt Clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL Stabilization Interrupt Clear */ -#define RCU_INT_IRC16MSTBIC BIT(18) /*!< IRC16M Stabilization Interrupt Clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL Stabilization Interrupt Clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization Interrupt Clear */ -#define RCU_INT_PLLI2SSTBIC BIT(21) /*!< PLLI2S stabilization Interrupt Clear */ -#define RCU_INT_PLLSAISTBIC BIT(22) /*!< PLLSAI stabilization Interrupt Clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL Clock Stuck Interrupt Clear */ - -/* RCU_AHB1RST */ -#define RCU_AHB1RST_PARST BIT(0) /*!< GPIO port A reset */ -#define RCU_AHB1RST_PBRST BIT(1) /*!< GPIO port B reset */ -#define RCU_AHB1RST_PCRST BIT(2) /*!< GPIO port C reset */ -#define RCU_AHB1RST_PDRST BIT(3) /*!< GPIO port D reset */ -#define RCU_AHB1RST_PERST BIT(4) /*!< GPIO port E reset */ -#define RCU_AHB1RST_PFRST BIT(5) /*!< GPIO port F reset */ -#define RCU_AHB1RST_PGRST BIT(6) /*!< GPIO port G reset */ -#define RCU_AHB1RST_PHRST BIT(7) /*!< GPIO port H reset */ -#define RCU_AHB1RST_PIRST BIT(8) /*!< GPIO port I reset */ -#define RCU_AHB1RST_CRCRST BIT(12) /*!< CRC reset */ -#define RCU_AHB1RST_DMA0RST BIT(21) /*!< DMA0 reset */ -#define RCU_AHB1RST_DMA1RST BIT(22) /*!< DMA1 reset */ -#define RCU_AHB1RST_IPARST BIT(23) /*!< IPA reset */ -#define RCU_AHB1RST_ENETRST BIT(25) /*!< ENET reset */ -#define RCU_AHB1RST_USBHSRST BIT(29) /*!< USBHS reset */ - -/* RCU_AHB2RST */ -#define RCU_AHB2RST_DCIRST BIT(0) /*!< DCI reset */ -#define RCU_AHB2RST_TRNGRST BIT(6) /*!< TRNG reset */ -#define RCU_AHB2RST_USBFSRST BIT(7) /*!< USBFS reset */ - -/* RCU_AHB3RST */ -#define RCU_AHB3RST_EXMCRST BIT(0) /*!< EXMC reset */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ -#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ -#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ -#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ -#define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ -#define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ -#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ -#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#define RCU_APB1RST_I2C2RST BIT(23) /*!< I2C2 reset */ -#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ -#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ -#define RCU_APB1RST_UART6RST BIT(30) /*!< UART6 reset */ -#define RCU_APB1RST_UART7RST BIT(31) /*!< UART7 reset */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_TIMER0RST BIT(0) /*!< TIMER0 reset */ -#define RCU_APB2RST_TIMER7RST BIT(1) /*!< TIMER7 reset */ -#define RCU_APB2RST_USART0RST BIT(4) /*!< USART0 reset */ -#define RCU_APB2RST_USART5RST BIT(5) /*!< USART5 reset */ -#define RCU_APB2RST_ADCRST BIT(8) /*!< ADC reset */ -#define RCU_APB2RST_SDIORST BIT(11) /*!< SDIO reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_SPI3RST BIT(13) /*!< SPI3 reset */ -#define RCU_APB2RST_SYSCFGRST BIT(14) /*!< SYSCFG reset */ -#define RCU_APB2RST_TIMER8RST BIT(16) /*!< TIMER8 reset */ -#define RCU_APB2RST_TIMER9RST BIT(17) /*!< TIMER9 reset */ -#define RCU_APB2RST_TIMER10RST BIT(18) /*!< TIMER10 reset */ -#define RCU_APB2RST_SPI4RST BIT(20) /*!< SPI4 reset */ -#define RCU_APB2RST_SPI5RST BIT(21) /*!< SPI5 reset */ -#define RCU_APB2RST_TLIRST BIT(26) /*!< TLI reset */ - -/* RCU_AHB1EN */ -#define RCU_AHB1EN_PAEN BIT(0) /*!< GPIO port A clock enable */ -#define RCU_AHB1EN_PBEN BIT(1) /*!< GPIO port B clock enable */ -#define RCU_AHB1EN_PCEN BIT(2) /*!< GPIO port C clock enable */ -#define RCU_AHB1EN_PDEN BIT(3) /*!< GPIO port D clock enable */ -#define RCU_AHB1EN_PEEN BIT(4) /*!< GPIO port E clock enable */ -#define RCU_AHB1EN_PFEN BIT(5) /*!< GPIO port F clock enable */ -#define RCU_AHB1EN_PGEN BIT(6) /*!< GPIO port G clock enable */ -#define RCU_AHB1EN_PHEN BIT(7) /*!< GPIO port H clock enable */ -#define RCU_AHB1EN_PIEN BIT(8) /*!< GPIO port I clock enable */ -#define RCU_AHB1EN_CRCEN BIT(12) /*!< CRC clock enable */ -#define RCU_AHB1EN_BKPSRAMEN BIT(18) /*!< BKPSRAM clock enable */ -#define RCU_AHB1EN_TCMSRAMEN BIT(20) /*!< TCMSRAM clock enable */ -#define RCU_AHB1EN_DMA0EN BIT(21) /*!< DMA0 clock enable */ -#define RCU_AHB1EN_DMA1EN BIT(22) /*!< DMA1 clock enable */ -#define RCU_AHB1EN_IPAEN BIT(23) /*!< IPA clock enable */ -#define RCU_AHB1EN_ENETEN BIT(25) /*!< ENET clock enable */ -#define RCU_AHB1EN_ENETTXEN BIT(26) /*!< Ethernet TX clock enable */ -#define RCU_AHB1EN_ENETRXEN BIT(27) /*!< Ethernet RX clock enable */ -#define RCU_AHB1EN_ENETPTPEN BIT(28) /*!< Ethernet PTP clock enable */ -#define RCU_AHB1EN_USBHSEN BIT(29) /*!< USBHS clock enable */ -#define RCU_AHB1EN_USBHSULPIEN BIT(30) /*!< USBHS ULPI clock enable */ - -/* RCU_AHB2EN */ -#define RCU_AHB2EN_DCIEN BIT(0) /*!< DCI clock enable */ -#define RCU_AHB2EN_TRNGEN BIT(6) /*!< TRNG clock enable */ -#define RCU_AHB2EN_USBFSEN BIT(7) /*!< USBFS clock enable */ - -/* RCU_AHB3EN */ -#define RCU_AHB3EN_EXMCEN BIT(0) /*!< EXMC clock enable */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ -#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ -#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ -#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ -#define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ -#define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ -#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ -#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#define RCU_APB1EN_I2C2EN BIT(23) /*!< I2C2 clock enable */ -#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ -#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ -#define RCU_APB1EN_UART6EN BIT(30) /*!< UART6 clock enable */ -#define RCU_APB1EN_UART7EN BIT(31) /*!< UART7 clock enable */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_TIMER0EN BIT(0) /*!< TIMER0 clock enable */ -#define RCU_APB2EN_TIMER7EN BIT(1) /*!< TIMER7 clock enable */ -#define RCU_APB2EN_USART0EN BIT(4) /*!< USART0 clock enable */ -#define RCU_APB2EN_USART5EN BIT(5) /*!< USART5 clock enable */ -#define RCU_APB2EN_ADC0EN BIT(8) /*!< ADC0 clock enable */ -#define RCU_APB2EN_ADC1EN BIT(9) /*!< ADC1 clock enable */ -#define RCU_APB2EN_ADC2EN BIT(10) /*!< ADC2 clock enable */ -#define RCU_APB2EN_SDIOEN BIT(11) /*!< SDIO clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_SPI3EN BIT(13) /*!< SPI3 clock enable */ -#define RCU_APB2EN_SYSCFGEN BIT(14) /*!< SYSCFG clock enable */ -#define RCU_APB2EN_TIMER8EN BIT(16) /*!< TIMER8 clock enable */ -#define RCU_APB2EN_TIMER9EN BIT(17) /*!< TIMER9 clock enable */ -#define RCU_APB2EN_TIMER10EN BIT(18) /*!< TIMER10 clock enable */ -#define RCU_APB2EN_SPI4EN BIT(20) /*!< SPI4 clock enable */ -#define RCU_APB2EN_SPI5EN BIT(21) /*!< SPI5 clock enable */ -#define RCU_APB2EN_TLIEN BIT(26) /*!< TLI clock enable */ - -/* RCU_AHB1SPEN */ -#define RCU_AHB1SPEN_PASPEN BIT(0) /*!< GPIO port A clock enable when sleep mode */ -#define RCU_AHB1SPEN_PBSPEN BIT(1) /*!< GPIO port B clock enable when sleep mode */ -#define RCU_AHB1SPEN_PCSPEN BIT(2) /*!< GPIO port C clock enable when sleep mode */ -#define RCU_AHB1SPEN_PDSPEN BIT(3) /*!< GPIO port D clock enable when sleep mode */ -#define RCU_AHB1SPEN_PESPEN BIT(4) /*!< GPIO port E clock enable when sleep mode */ -#define RCU_AHB1SPEN_PFSPEN BIT(5) /*!< GPIO port F clock enable when sleep mode */ -#define RCU_AHB1SPEN_PGSPEN BIT(6) /*!< GPIO port G clock enable when sleep mode */ -#define RCU_AHB1SPEN_PHSPEN BIT(7) /*!< GPIO port H clock enable when sleep mode */ -#define RCU_AHB1SPEN_PISPEN BIT(8) /*!< GPIO port I clock enable when sleep mode */ -#define RCU_AHB1SPEN_CRCSPEN BIT(12) /*!< CRC clock enable when sleep mode */ -#define RCU_AHB1SPEN_FMCSPEN BIT(15) /*!< FMC clock enable when sleep mode */ -#define RCU_AHB1SPEN_SRAM0SPEN BIT(16) /*!< SRAM0 clock enable when sleep mode */ -#define RCU_AHB1SPEN_SRAM1SPEN BIT(17) /*!< SRAM1 clock enable when sleep mode */ -#define RCU_AHB1SPEN_BKPSRAMSPEN BIT(18) /*!< BKPSRAM clock enable when sleep mode */ -#define RCU_AHB1SPEN_SRAM2SPEN BIT(19) /*!< SRAM2 clock enable when sleep mode */ -#define RCU_AHB1SPEN_DMA0SPEN BIT(21) /*!< DMA0 clock when sleep mode enable */ -#define RCU_AHB1SPEN_DMA1SPEN BIT(22) /*!< DMA1 clock when sleep mode enable */ -#define RCU_AHB1SPEN_IPASPEN BIT(23) /*!< IPA clock enable when sleep mode */ -#define RCU_AHB1SPEN_ENETSPEN BIT(25) /*!< ENET clock enable when sleep mode */ -#define RCU_AHB1SPEN_ENETTXSPEN BIT(26) /*!< Ethernet TX clock enable when sleep mode */ -#define RCU_AHB1SPEN_ENETRXSPEN BIT(27) /*!< Ethernet RX clock enable when sleep mode */ -#define RCU_AHB1SPEN_ENETPTPSPEN BIT(28) /*!< Ethernet PTP clock enable when sleep mode */ -#define RCU_AHB1SPEN_USBHSSPEN BIT(29) /*!< USBHS clock enable when sleep mode */ -#define RCU_AHB1SPEN_USBHSULPISPEN BIT(30) /*!< USBHS ULPI clock enable when sleep mode */ - -/* RCU_AHB2SPEN */ -#define RCU_AHB2SPEN_DCISPEN BIT(0) /*!< DCI clock enable when sleep mode */ -#define RCU_AHB2SPEN_TRNGSPEN BIT(6) /*!< TRNG clock enable when sleep mode */ -#define RCU_AHB2SPEN_USBFSSPEN BIT(7) /*!< USBFS clock enable when sleep mode */ - -/* RCU_AHB3SPEN */ -#define RCU_AHB3SPEN_EXMCSPEN BIT(0) /*!< EXMC clock enable when sleep mode */ - -/* RCU_APB1SPEN */ -#define RCU_APB1SPEN_TIMER1SPEN BIT(0) /*!< TIMER1 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER2SPEN BIT(1) /*!< TIMER2 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER3SPEN BIT(2) /*!< TIMER3 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER4SPEN BIT(3) /*!< TIMER4 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER5SPEN BIT(4) /*!< TIMER5 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER6SPEN BIT(5) /*!< TIMER6 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER11SPEN BIT(6) /*!< TIMER11 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER12SPEN BIT(7) /*!< TIMER12 clock enable when sleep mode */ -#define RCU_APB1SPEN_TIMER13SPEN BIT(8) /*!< TIMER13 clock enable when sleep mode */ -#define RCU_APB1SPEN_WWDGTSPEN BIT(11) /*!< WWDGT clock enable when sleep mode */ -#define RCU_APB1SPEN_SPI1SPEN BIT(14) /*!< SPI1 clock enable when sleep mode */ -#define RCU_APB1SPEN_SPI2SPEN BIT(15) /*!< SPI2 clock enable when sleep mode */ -#define RCU_APB1SPEN_USART1SPEN BIT(17) /*!< USART1 clock enable when sleep mode*/ -#define RCU_APB1SPEN_USART2SPEN BIT(18) /*!< USART2 clock enable when sleep mode*/ -#define RCU_APB1SPEN_UART3SPEN BIT(19) /*!< UART3 clock enable when sleep mode*/ -#define RCU_APB1SPEN_UART4SPEN BIT(20) /*!< UART4 clock enable when sleep mode */ -#define RCU_APB1SPEN_I2C0SPEN BIT(21) /*!< I2C0 clock enable when sleep mode */ -#define RCU_APB1SPEN_I2C1SPEN BIT(22) /*!< I2C1 clock enable when sleep mode*/ -#define RCU_APB1SPEN_I2C2SPEN BIT(23) /*!< I2C2 clock enable when sleep mode */ -#define RCU_APB1SPEN_CAN0SPEN BIT(25) /*!< CAN0 clock enable when sleep mode*/ -#define RCU_APB1SPEN_CAN1SPEN BIT(26) /*!< CAN1 clock enable when sleep mode */ -#define RCU_APB1SPEN_PMUSPEN BIT(28) /*!< PMU clock enable when sleep mode */ -#define RCU_APB1SPEN_DACSPEN BIT(29) /*!< DAC clock enable when sleep mode */ -#define RCU_APB1SPEN_UART6SPEN BIT(30) /*!< UART6 clock enable when sleep mode */ -#define RCU_APB1SPEN_UART7SPEN BIT(31) /*!< UART7 clock enable when sleep mode */ - -/* RCU_APB2SPEN */ -#define RCU_APB2SPEN_TIMER0SPEN BIT(0) /*!< TIMER0 clock enable when sleep mode */ -#define RCU_APB2SPEN_TIMER7SPEN BIT(1) /*!< TIMER7 clock enable when sleep mode */ -#define RCU_APB2SPEN_USART0SPEN BIT(4) /*!< USART0 clock enable when sleep mode */ -#define RCU_APB2SPEN_USART5SPEN BIT(5) /*!< USART5 clock enable when sleep mode */ -#define RCU_APB2SPEN_ADC0SPEN BIT(8) /*!< ADC0 clock enable when sleep mode */ -#define RCU_APB2SPEN_ADC1SPEN BIT(9) /*!< ADC1 clock enable when sleep mode */ -#define RCU_APB2SPEN_ADC2SPEN BIT(10) /*!< ADC2 clock enable when sleep mode */ -#define RCU_APB2SPEN_SDIOSPEN BIT(11) /*!< SDIO clock enable when sleep mode */ -#define RCU_APB2SPEN_SPI0SPEN BIT(12) /*!< SPI0 clock enable when sleep mode */ -#define RCU_APB2SPEN_SPI3SPEN BIT(13) /*!< SPI3 clock enable when sleep mode */ -#define RCU_APB2SPEN_SYSCFGSPEN BIT(14) /*!< SYSCFG clock enable when sleep mode */ -#define RCU_APB2SPEN_TIMER8SPEN BIT(16) /*!< TIMER8 clock enable when sleep mode */ -#define RCU_APB2SPEN_TIMER9SPEN BIT(17) /*!< TIMER9 clock enable when sleep mode */ -#define RCU_APB2SPEN_TIMER10SPEN BIT(18) /*!< TIMER10 clock enable when sleep mode */ -#define RCU_APB2SPEN_SPI4SPEN BIT(20) /*!< SPI4 clock enable when sleep mode */ -#define RCU_APB2SPEN_SPI5SPEN BIT(21) /*!< SPI5 clock enable when sleep mode */ -#define RCU_APB2SPEN_TLISPEN BIT(26) /*!< TLI clock enable when sleep mode*/ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_LXTALDRI BIT(3) /*!< LXTAL drive capability */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC32KEN BIT(0) /*!< IRC32K enable */ -#define RCU_RSTSCK_IRC32KSTB BIT(1) /*!< IRC32K stabilization flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_BORRSTF BIT(25) /*!< BOR reset flag */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -/* RCU_PLLSSCTL */ -#define RCU_PLLSSCTL_MODCNT BITS(0,12) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria - must be met: MODSTEP*MODCNT=215-1 */ -#define RCU_PLLSSCTL_MODSTEP BITS(13,27) /*!< these bits configure PLL spread spectrum modulation - profile amplitude and frequency. the following criteria - must be met: MODSTEP*MODCNT=215-1 */ -#define RCU_PLLSSCTL_SS_TYPE BIT(30) /*!< PLL spread spectrum modulation type select */ -#define RCU_PLLSSCTL_SSCGON BIT(31) /*!< PLL spread spectrum modulation enable */ - -/* RCU_PLLI2S */ -#define RCU_PLLI2S_PLLI2SN BITS(6,14) /*!< the PLLI2S VCO clock multi factor */ -#define RCU_PLLI2S_PLLI2SQ BITS(24,27) /*!< the PLLI2S Q output frequency division factor from PLLI2S VCO clock */ -#define RCU_PLLI2S_PLLI2SR BITS(28,30) /*!< the PLLI2S R output frequency division factor from PLLI2S VCO clock */ - -/* RCU_PLLSAI */ -#define RCU_PLLSAI_PLLSAIN BITS(6,14) /*!< the PLLSAI VCO clock multi factor */ -#define RCU_PLLSAI_PLLSAIP BITS(16,17) /*!< the PLLSAI P output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAI_PLLSAIQ BITS(24,27) /*!< the PLLSAI Q output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAI_PLLSAIR BITS(28,30) /*!< the PLLSAI R output frequency division factor from PLLSAI VCO clock */ - -/* RCU_CFG1 */ -#define RCU_CFG1_PLLSAIRDIV BITS(16,17) /*!< the divider factor from PLLSAIR clock */ -#define RCU_CFG1_TIMERSEL BIT(24) /*!< TIMER clock selection */ - -/* RCU_ADDCTL */ -#define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ -#define RCU_ADDCTL_PLL48MSEL BIT(1) /*!< PLL48M clock selection */ -#define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ -#define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ -#define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ - -/* RCU_ADDINT */ -#define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ -#define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ -#define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ - -/* RCU_ADDAPB1RST */ -#define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ -#define RCU_ADDAPB1RST_IREFRST BIT(31) /*!< IREF reset */ - -/* RCU_ADDAPB1EN */ -#define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ -#define RCU_ADDAPB1EN_IREFEN BIT(31) /*!< IREF interface clock enable */ - -/* RCU_ADDAPB1SPEN */ -#define RCU_ADDAPB1SPEN_CTCSPEN BIT(27) /*!< CTC clock enable during sleep mode */ -#define RCU_ADDAPB1SPEN_IREFSPEN BIT(31) /*!< IREF interface clock enable during sleep mode */ - -/* RCU_VKEY */ -#define RCU_VKEY_KEY BITS(0,31) /*!< RCU_DSV key register */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -/* define the voltage key unlock value */ -#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) - -/* register offset */ -/* peripherals enable */ -#define AHB1EN_REG_OFFSET 0x30U /*!< AHB1 enable register offset */ -#define AHB2EN_REG_OFFSET 0x34U /*!< AHB2 enable register offset */ -#define AHB3EN_REG_OFFSET 0x38U /*!< AHB3 enable register offset */ -#define APB1EN_REG_OFFSET 0x40U /*!< APB1 enable register offset */ -#define APB2EN_REG_OFFSET 0x44U /*!< APB2 enable register offset */ -#define AHB1SPEN_REG_OFFSET 0x50U /*!< AHB1 sleep mode enable register offset */ -#define AHB2SPEN_REG_OFFSET 0x54U /*!< AHB2 sleep mode enable register offset */ -#define AHB3SPEN_REG_OFFSET 0x58U /*!< AHB3 sleep mode enable register offset */ -#define APB1SPEN_REG_OFFSET 0x60U /*!< APB1 sleep mode enable register offset */ -#define APB2SPEN_REG_OFFSET 0x64U /*!< APB2 sleep mode enable register offset */ -#define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ -#define ADD_APB1SPEN_REG_OFFSET 0xE8U /*!< APB1 additional sleep mode enable register offset */ - -/* peripherals reset */ -#define AHB1RST_REG_OFFSET 0x10U /*!< AHB1 reset register offset */ -#define AHB2RST_REG_OFFSET 0x14U /*!< AHB2 reset register offset */ -#define AHB3RST_REG_OFFSET 0x18U /*!< AHB3 reset register offset */ -#define APB1RST_REG_OFFSET 0x20U /*!< APB1 reset register offset */ -#define APB2RST_REG_OFFSET 0x24U /*!< APB2 reset register offset */ -#define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ -#define RSTSCK_REG_OFFSET 0x74U /*!< reset source/clock register offset */ - -/* clock control */ -#define CTL_REG_OFFSET 0x00U /*!< control register offset */ -#define BDCTL_REG_OFFSET 0x70U /*!< backup domain control register offset */ -#define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ - -/* clock stabilization and stuck interrupt */ -#define INT_REG_OFFSET 0x0CU /*!< clock interrupt register offset */ -#define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ - -/* configuration register */ -#define PLL_REG_OFFSET 0x04U /*!< PLL register offset */ -#define CFG0_REG_OFFSET 0x08U /*!< clock configuration register 0 offset */ -#define PLLSSCTL_REG_OFFSET 0x80U /*!< PLL clock spread spectrum control register offset */ -#define PLLI2S_REG_OFFSET 0x84U /*!< PLLI2S register offset */ -#define PLLSAI_REG_OFFSET 0x88U /*!< PLLSAI register offset */ -#define CFG1_REG_OFFSET 0x8CU /*!< clock configuration register 1 offset */ - -/* peripheral clock enable */ -typedef enum -{ - /* AHB1 peripherals */ - RCU_GPIOA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 0U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 1U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 2U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 3U), /*!< GPIOD clock */ - RCU_GPIOE = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 4U), /*!< GPIOE clock */ - RCU_GPIOF = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 5U), /*!< GPIOF clock */ - RCU_GPIOG = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 6U), /*!< GPIOG clock */ - RCU_GPIOH = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 7U), /*!< GPIOH clock */ - RCU_GPIOI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 8U), /*!< GPIOI clock */ - RCU_CRC = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 12U), /*!< CRC clock */ - RCU_BKPSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ - RCU_TCMSRAM = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 20U), /*!< TCMSRAM clock */ - RCU_DMA0 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 21U), /*!< DMA0 clock */ - RCU_DMA1 = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 22U), /*!< DMA1 clock */ - RCU_IPA = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 23U), /*!< IPA clock */ - RCU_ENET = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 25U), /*!< ENET clock */ - RCU_ENETTX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 26U), /*!< ENETTX clock */ - RCU_ENETRX = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 27U), /*!< ENETRX clock */ - RCU_ENETPTP = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 28U), /*!< ENETPTP clock */ - RCU_USBHS = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 29U), /*!< USBHS clock */ - RCU_USBHSULPI = RCU_REGIDX_BIT(AHB1EN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ - /* AHB2 peripherals */ - RCU_DCI = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 0U), /*!< DCI clock */ - RCU_TRNG = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 6U), /*!< TRNG clock */ - RCU_USBFS = RCU_REGIDX_BIT(AHB2EN_REG_OFFSET, 7U), /*!< USBFS clock */ - /* AHB3 peripherals */ - RCU_EXMC = RCU_REGIDX_BIT(AHB3EN_REG_OFFSET, 0U), /*!< EXMC clock */ - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ - RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ - RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ - RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 23U), /*!< I2C2 clock */ - RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ - RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ - RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_UART6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 30U), /*!< UART6 clock */ - RCU_UART7 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 31U), /*!< UART7 clock */ - RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - /* APB2 peripherals */ - RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< TIMER0 clock */ - RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 1U), /*!< TIMER7 clock */ - RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< USART0 clock */ - RCU_USART5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< USART5 clock */ - RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< ADC0 clock */ - RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC1 clock */ - RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC2 clock */ - RCU_SDIO = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< SDIO clock */ - RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_SPI3 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< SPI3 clock */ - RCU_SYSCFG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< SYSCFG clock */ - RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 16U), /*!< TIMER8 clock */ - RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 17U), /*!< TIMER9 clock */ - RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 18U), /*!< TIMER10 clock */ - RCU_SPI4 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< SPI4 clock */ - RCU_SPI5 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< SPI5 clock */ - RCU_TLI = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 26U), /*!< TLI clock */ - /* APB1 additional peripherals */ - RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ - RCU_IREF = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 31U), /*!< IREF clock */ -}rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum -{ - /* AHB1 peripherals */ - RCU_GPIOA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 0U), /*!< GPIOA clock */ - RCU_GPIOB_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 1U), /*!< GPIOB clock */ - RCU_GPIOC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 2U), /*!< GPIOC clock */ - RCU_GPIOD_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 3U), /*!< GPIOD clock */ - RCU_GPIOE_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 4U), /*!< GPIOE clock */ - RCU_GPIOF_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 5U), /*!< GPIOF clock */ - RCU_GPIOG_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 6U), /*!< GPIOG clock */ - RCU_GPIOH_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 7U), /*!< GPIOH clock */ - RCU_GPIOI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 8U), /*!< GPIOI clock */ - RCU_CRC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 12U), /*!< CRC clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 15U), /*!< FMC clock */ - RCU_SRAM0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 16U), /*!< SRAM0 clock */ - RCU_SRAM1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 17U), /*!< SRAM1 clock */ - RCU_BKPSRAM_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 18U), /*!< BKPSRAM clock */ - RCU_SRAM2_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 19U), /*!< SRAM2 clock */ - RCU_DMA0_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 21U), /*!< DMA0 clock */ - RCU_DMA1_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 22U), /*!< DMA1 clock */ - RCU_IPA_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 23U), /*!< IPA clock */ - RCU_ENET_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 25U), /*!< ENET clock */ - RCU_ENETTX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 26U), /*!< ENETTX clock */ - RCU_ENETRX_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 27U), /*!< ENETRX clock */ - RCU_ENETPTP_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 28U), /*!< ENETPTP clock */ - RCU_USBHS_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 29U), /*!< USBHS clock */ - RCU_USBHSULPI_SLP = RCU_REGIDX_BIT(AHB1SPEN_REG_OFFSET, 30U), /*!< USBHSULPI clock */ - /* AHB2 peripherals */ - RCU_DCI_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 0U), /*!< DCI clock */ - RCU_TRNG_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 6U), /*!< TRNG clock */ - RCU_USBFS_SLP = RCU_REGIDX_BIT(AHB2SPEN_REG_OFFSET, 7U), /*!< USBFS clock */ - /* AHB3 peripherals */ - RCU_EXMC_SLP = RCU_REGIDX_BIT(AHB3SPEN_REG_OFFSET, 0U), /*!< EXMC clock */ - /* APB1 peripherals */ - RCU_TIMER1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 5U), /*!< TIMER6 clock */ - RCU_TIMER11_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 6U), /*!< TIMER11 clock */ - RCU_TIMER12_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 7U), /*!< TIMER12 clock */ - RCU_TIMER13_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 8U), /*!< TIMER13 clock */ - RCU_WWDGT_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_I2C2_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 23U), /*!< I2C2 clock */ - RCU_CAN0_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 25U), /*!< CAN0 clock */ - RCU_CAN1_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 26U), /*!< CAN1 clock */ - RCU_PMU_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_UART6_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 30U), /*!< UART6 clock */ - RCU_UART7_SLP = RCU_REGIDX_BIT(APB1SPEN_REG_OFFSET, 31U), /*!< UART7 clock */ - /* APB2 peripherals */ - RCU_TIMER0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 0U), /*!< TIMER0 clock */ - RCU_TIMER7_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 1U), /*!< TIMER7 clock */ - RCU_USART0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 4U), /*!< USART0 clock */ - RCU_USART5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 5U), /*!< USART5 clock */ - RCU_ADC0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 8U), /*!< ADC0 clock */ - RCU_ADC1_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 9U), /*!< ADC1 clock */ - RCU_ADC2_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 10U), /*!< ADC2 clock */ - RCU_SDIO_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 11U), /*!< SDIO clock */ - RCU_SPI0_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_SPI3_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 13U), /*!< SPI3 clock */ - RCU_SYSCFG_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 14U), /*!< SYSCFG clock */ - RCU_TIMER8_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 16U), /*!< TIMER8 clock */ - RCU_TIMER9_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 17U), /*!< TIMER9 clock */ - RCU_TIMER10_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 18U), /*!< TIMER10 clock */ - RCU_SPI4_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 20U), /*!< SPI4 clock */ - RCU_SPI5_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 21U), /*!< SPI5 clock */ - RCU_TLI_SLP = RCU_REGIDX_BIT(APB2SPEN_REG_OFFSET, 26U), /*!< TLI clock */ - /* APB1 additional peripherals */ - RCU_CTC_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 27U), /*!< CTC clock */ - RCU_IREF_SLP = RCU_REGIDX_BIT(ADD_APB1SPEN_REG_OFFSET, 31U), /*!< IREF clock */ -}rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum -{ - /* AHB1 peripherals */ - RCU_GPIOARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 0U), /*!< GPIOA clock reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 1U), /*!< GPIOB clock reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 2U), /*!< GPIOC clock reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 3U), /*!< GPIOD clock reset */ - RCU_GPIOERST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 4U), /*!< GPIOE clock reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 5U), /*!< GPIOF clock reset */ - RCU_GPIOGRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 6U), /*!< GPIOG clock reset */ - RCU_GPIOHRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 7U), /*!< GPIOH clock reset */ - RCU_GPIOIRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 8U), /*!< GPIOI clock reset */ - RCU_CRCRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 12U), /*!< CRC clock reset */ - RCU_DMA0RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 21U), /*!< DMA0 clock reset */ - RCU_DMA1RST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 22U), /*!< DMA1 clock reset */ - RCU_IPARST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 23U), /*!< IPA clock reset */ - RCU_ENETRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 25U), /*!< ENET clock reset */ - RCU_USBHSRST = RCU_REGIDX_BIT(AHB1RST_REG_OFFSET, 29U), /*!< USBHS clock reset */ - /* AHB2 peripherals */ - RCU_DCIRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 0U), /*!< DCI clock reset */ - RCU_TRNGRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 6U), /*!< TRNG clock reset */ - RCU_USBFSRST = RCU_REGIDX_BIT(AHB2RST_REG_OFFSET, 7U), /*!< USBFS clock reset */ - /* AHB3 peripherals */ - RCU_EXMCRST = RCU_REGIDX_BIT(AHB3RST_REG_OFFSET, 0U), /*!< EXMC clock reset */ - /* APB1 peripherals */ - RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ - RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ - RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ - RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ - RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ - RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ - RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ - RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ - RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ - RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ - RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ - RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ - RCU_I2C2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 23U), /*!< I2C2 clock reset */ - RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ - RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ - RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ - RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - RCU_UART6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 30U), /*!< UART6 clock reset */ - RCU_UART7RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 31U), /*!< UART7 clock reset */ - /* APB2 peripherals */ - RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< TIMER0 clock reset */ - RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 1U), /*!< TIMER7 clock reset */ - RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< USART0 clock reset */ - RCU_USART5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< USART5 clock reset */ - RCU_ADCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< ADCs all clock reset */ - RCU_SDIORST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< SDIO clock reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ - RCU_SPI3RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< SPI3 clock reset */ - RCU_SYSCFGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< SYSCFG clock reset */ - RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 16U), /*!< TIMER8 clock reset */ - RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 17U), /*!< TIMER9 clock reset */ - RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 18U), /*!< TIMER10 clock reset */ - RCU_SPI4RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< SPI4 clock reset */ - RCU_SPI5RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< SPI5 clock reset */ - RCU_TLIRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 26U), /*!< TLI clock reset */ - /* APB1 additional peripherals */ - RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< CTC clock reset */ - RCU_IREFRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 31U) /*!< IREF clock reset */ -}rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum -{ - /* clock stabilization flags */ - RCU_FLAG_IRC16MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC16M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ - RCU_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLLI2S stabilization flags */ - RCU_FLAG_PLLSAISTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLLSAI stabilization flags */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC32KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC32K stabilization flags */ - RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ - /* reset source flags */ - RCU_FLAG_BORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 25U), /*!< BOR reset flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< External PIN reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< Software reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< Low-power reset flags */ -}rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum -{ - RCU_INT_FLAG_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC32K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC16M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ - RCU_INT_FLAG_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLLI2S stabilization interrupt flag */ - RCU_INT_FLAG_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLLSAI stabilization interrupt flag */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ - RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ -}rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ - RCU_INT_FLAG_IRC32KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC32K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC16MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC16M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLI2SSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLLI2S stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSAISTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLLSAI stabilization interrupt flags clear */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ - RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ -}rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum -{ - RCU_INT_IRC32KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC32K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC16MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC16M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ - RCU_INT_PLLI2SSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLLI2S stabilization interrupt */ - RCU_INT_PLLSAISTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLLSAI stabilization interrupt */ - RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ -}rcu_int_enum; - -/* oscillator types */ -typedef enum -{ - RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ - RCU_IRC16M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC16M */ - RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ - RCU_IRC32K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC32K */ - RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ - RCU_PLLI2S_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLLI2S */ - RCU_PLLSAI_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLLSAI */ -}rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum -{ - CK_SYS = 0, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ -}rcu_clock_freq_enum; - -/* RCU_CFG0 register bit define */ -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC16M CFG0_SCS(0) /*!< system clock source select IRC16M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLLP CFG0_SCS(2) /*!< system clock source select PLLP */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC16M CFG0_SCSS(0) /*!< system clock source select IRC16M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLLP CFG0_SCSS(2) /*!< system clock source select PLLP */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(10,12) & ((uint32_t)(regval) << 10)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* RTC clock divider factor from HXTAL clock */ -#define CFG0_RTCDIV(regval) (BITS(16,20) & ((uint32_t)(regval) << 16)) -#define RCU_RTC_HXTAL_NONE CFG0_RTCDIV(0) /*!< no clock for RTC */ -#define RCU_RTC_HXTAL_DIV2 CFG0_RTCDIV(2) /*!< RTCDIV clock select CK_HXTAL/2 */ -#define RCU_RTC_HXTAL_DIV3 CFG0_RTCDIV(3) /*!< RTCDIV clock select CK_HXTAL/3 */ -#define RCU_RTC_HXTAL_DIV4 CFG0_RTCDIV(4) /*!< RTCDIV clock select CK_HXTAL/4 */ -#define RCU_RTC_HXTAL_DIV5 CFG0_RTCDIV(5) /*!< RTCDIV clock select CK_HXTAL/5 */ -#define RCU_RTC_HXTAL_DIV6 CFG0_RTCDIV(6) /*!< RTCDIV clock select CK_HXTAL/6 */ -#define RCU_RTC_HXTAL_DIV7 CFG0_RTCDIV(7) /*!< RTCDIV clock select CK_HXTAL/7 */ -#define RCU_RTC_HXTAL_DIV8 CFG0_RTCDIV(8) /*!< RTCDIV clock select CK_HXTAL/8 */ -#define RCU_RTC_HXTAL_DIV9 CFG0_RTCDIV(9) /*!< RTCDIV clock select CK_HXTAL/9 */ -#define RCU_RTC_HXTAL_DIV10 CFG0_RTCDIV(10) /*!< RTCDIV clock select CK_HXTAL/10 */ -#define RCU_RTC_HXTAL_DIV11 CFG0_RTCDIV(11) /*!< RTCDIV clock select CK_HXTAL/11 */ -#define RCU_RTC_HXTAL_DIV12 CFG0_RTCDIV(12) /*!< RTCDIV clock select CK_HXTAL/12 */ -#define RCU_RTC_HXTAL_DIV13 CFG0_RTCDIV(13) /*!< RTCDIV clock select CK_HXTAL/13 */ -#define RCU_RTC_HXTAL_DIV14 CFG0_RTCDIV(14) /*!< RTCDIV clock select CK_HXTAL/14 */ -#define RCU_RTC_HXTAL_DIV15 CFG0_RTCDIV(15) /*!< RTCDIV clock select CK_HXTAL/15 */ -#define RCU_RTC_HXTAL_DIV16 CFG0_RTCDIV(16) /*!< RTCDIV clock select CK_HXTAL/16 */ -#define RCU_RTC_HXTAL_DIV17 CFG0_RTCDIV(17) /*!< RTCDIV clock select CK_HXTAL/17 */ -#define RCU_RTC_HXTAL_DIV18 CFG0_RTCDIV(18) /*!< RTCDIV clock select CK_HXTAL/18 */ -#define RCU_RTC_HXTAL_DIV19 CFG0_RTCDIV(19) /*!< RTCDIV clock select CK_HXTAL/19 */ -#define RCU_RTC_HXTAL_DIV20 CFG0_RTCDIV(20) /*!< RTCDIV clock select CK_HXTAL/20 */ -#define RCU_RTC_HXTAL_DIV21 CFG0_RTCDIV(21) /*!< RTCDIV clock select CK_HXTAL/21 */ -#define RCU_RTC_HXTAL_DIV22 CFG0_RTCDIV(22) /*!< RTCDIV clock select CK_HXTAL/22 */ -#define RCU_RTC_HXTAL_DIV23 CFG0_RTCDIV(23) /*!< RTCDIV clock select CK_HXTAL/23 */ -#define RCU_RTC_HXTAL_DIV24 CFG0_RTCDIV(24) /*!< RTCDIV clock select CK_HXTAL/24 */ -#define RCU_RTC_HXTAL_DIV25 CFG0_RTCDIV(25) /*!< RTCDIV clock select CK_HXTAL/25 */ -#define RCU_RTC_HXTAL_DIV26 CFG0_RTCDIV(26) /*!< RTCDIV clock select CK_HXTAL/26 */ -#define RCU_RTC_HXTAL_DIV27 CFG0_RTCDIV(27) /*!< RTCDIV clock select CK_HXTAL/27 */ -#define RCU_RTC_HXTAL_DIV28 CFG0_RTCDIV(28) /*!< RTCDIV clock select CK_HXTAL/28 */ -#define RCU_RTC_HXTAL_DIV29 CFG0_RTCDIV(29) /*!< RTCDIV clock select CK_HXTAL/29 */ -#define RCU_RTC_HXTAL_DIV30 CFG0_RTCDIV(30) /*!< RTCDIV clock select CK_HXTAL/30 */ -#define RCU_RTC_HXTAL_DIV31 CFG0_RTCDIV(31) /*!< RTCDIV clock select CK_HXTAL/31 */ - -/* CKOUT0 Clock source selection */ -#define CFG0_CKOUT0SEL(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) -#define RCU_CKOUT0SRC_IRC16M CFG0_CKOUT0SEL(0) /*!< internal 16M RC oscillator clock selected */ -#define RCU_CKOUT0SRC_LXTAL CFG0_CKOUT0SEL(1) /*!< low speed crystal oscillator clock (LXTAL) selected */ -#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT0SRC_PLLP CFG0_CKOUT0SEL(3) /*!< CK_PLLP clock selected */ - -/* I2S Clock source selection */ -#define RCU_I2SSRC_PLLI2S ((uint32_t)0x00000000U) /*!< PLLI2S output clock selected as I2S source clock */ -#define RCU_I2SSRC_I2S_CKIN RCU_CFG0_I2SSEL /*!< external I2S_CKIN pin selected as I2S source clock */ - -/* The CK_OUT0 divider */ -#define CFG0_CKOUT0DIV(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUT0_DIV1 CFG0_CKOUT0DIV(0) /*!< CK_OUT0 is divided by 1 */ -#define RCU_CKOUT0_DIV2 CFG0_CKOUT0DIV(4) /*!< CK_OUT0 is divided by 2 */ -#define RCU_CKOUT0_DIV3 CFG0_CKOUT0DIV(5) /*!< CK_OUT0 is divided by 3 */ -#define RCU_CKOUT0_DIV4 CFG0_CKOUT0DIV(6) /*!< CK_OUT0 is divided by 4 */ -#define RCU_CKOUT0_DIV5 CFG0_CKOUT0DIV(7) /*!< CK_OUT0 is divided by 5 */ - -/* The CK_OUT1 divider */ -#define CFG0_CKOUT1DIV(regval) (BITS(27,29) & ((uint32_t)(regval) << 27)) -#define RCU_CKOUT1_DIV1 CFG0_CKOUT1DIV(0) /*!< CK_OUT1 is divided by 1 */ -#define RCU_CKOUT1_DIV2 CFG0_CKOUT1DIV(4) /*!< CK_OUT1 is divided by 2 */ -#define RCU_CKOUT1_DIV3 CFG0_CKOUT1DIV(5) /*!< CK_OUT1 is divided by 3 */ -#define RCU_CKOUT1_DIV4 CFG0_CKOUT1DIV(6) /*!< CK_OUT1 is divided by 4 */ -#define RCU_CKOUT1_DIV5 CFG0_CKOUT1DIV(7) /*!< CK_OUT1 is divided by 5 */ - -/* CKOUT1 Clock source selection */ -#define CFG0_CKOUT1SEL(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) -#define RCU_CKOUT1SRC_SYSTEMCLOCK CFG0_CKOUT1SEL(0) /*!< system clock selected */ -#define RCU_CKOUT1SRC_PLLI2SR CFG0_CKOUT1SEL(1) /*!< CK_PLLI2SR clock selected */ -#define RCU_CKOUT1SRC_HXTAL CFG0_CKOUT1SEL(2) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT1SRC_PLLP CFG0_CKOUT1SEL(3) /*!< CK_PLLP clock selected */ - -/* RCU_CFG1 register bit define */ -/* the divider factor from PLLI2SQ clock */ -#define CFG1_PLLI2SQDIV(regval) (BITS(0,4) & ((uint32_t)(regval) << 0)) -#define RCU_PLLI2SQ_DIV1 CFG1_PLLI2SQDIV(0) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/1 */ -#define RCU_PLLI2SQ_DIV2 CFG1_PLLI2SQDIV(1) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/2 */ -#define RCU_PLLI2SQ_DIV3 CFG1_PLLI2SQDIV(2) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/3 */ -#define RCU_PLLI2SQ_DIV4 CFG1_PLLI2SQDIV(3) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/4 */ -#define RCU_PLLI2SQ_DIV5 CFG1_PLLI2SQDIV(4) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/5 */ -#define RCU_PLLI2SQ_DIV6 CFG1_PLLI2SQDIV(5) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/6 */ -#define RCU_PLLI2SQ_DIV7 CFG1_PLLI2SQDIV(6) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/7 */ -#define RCU_PLLI2SQ_DIV8 CFG1_PLLI2SQDIV(7) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/8 */ -#define RCU_PLLI2SQ_DIV9 CFG1_PLLI2SQDIV(8) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/9 */ -#define RCU_PLLI2SQ_DIV10 CFG1_PLLI2SQDIV(9) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/10 */ -#define RCU_PLLI2SQ_DIV11 CFG1_PLLI2SQDIV(10) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/11 */ -#define RCU_PLLI2SQ_DIV12 CFG1_PLLI2SQDIV(11) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/12 */ -#define RCU_PLLI2SQ_DIV13 CFG1_PLLI2SQDIV(12) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/13 */ -#define RCU_PLLI2SQ_DIV14 CFG1_PLLI2SQDIV(13) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/14 */ -#define RCU_PLLI2SQ_DIV15 CFG1_PLLI2SQDIV(14) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/15 */ -#define RCU_PLLI2SQ_DIV16 CFG1_PLLI2SQDIV(15) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/16 */ -#define RCU_PLLI2SQ_DIV17 CFG1_PLLI2SQDIV(16) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/17 */ -#define RCU_PLLI2SQ_DIV18 CFG1_PLLI2SQDIV(17) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/18 */ -#define RCU_PLLI2SQ_DIV19 CFG1_PLLI2SQDIV(18) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/19 */ -#define RCU_PLLI2SQ_DIV20 CFG1_PLLI2SQDIV(19) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/20 */ -#define RCU_PLLI2SQ_DIV21 CFG1_PLLI2SQDIV(20) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/21 */ -#define RCU_PLLI2SQ_DIV22 CFG1_PLLI2SQDIV(21) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/22 */ -#define RCU_PLLI2SQ_DIV23 CFG1_PLLI2SQDIV(22) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/23 */ -#define RCU_PLLI2SQ_DIV24 CFG1_PLLI2SQDIV(23) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/24 */ -#define RCU_PLLI2SQ_DIV25 CFG1_PLLI2SQDIV(24) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/25 */ -#define RCU_PLLI2SQ_DIV26 CFG1_PLLI2SQDIV(25) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/26 */ -#define RCU_PLLI2SQ_DIV27 CFG1_PLLI2SQDIV(26) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/27 */ -#define RCU_PLLI2SQ_DIV28 CFG1_PLLI2SQDIV(27) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/28 */ -#define RCU_PLLI2SQ_DIV29 CFG1_PLLI2SQDIV(28) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/29 */ -#define RCU_PLLI2SQ_DIV30 CFG1_PLLI2SQDIV(29) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/30 */ -#define RCU_PLLI2SQ_DIV31 CFG1_PLLI2SQDIV(30) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/31 */ -#define RCU_PLLI2SQ_DIV32 CFG1_PLLI2SQDIV(31) /*!< CK_PLLI2SQDIV clock select CK_PLLI2SQ/32 */ - -/* the divider factor from PLLSAIR clock */ -#define CFG1_PLLSAIRDIV(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) -#define RCU_PLLSAIR_DIV2 CFG1_PLLSAIRDIV(0) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/2 */ -#define RCU_PLLSAIR_DIV4 CFG1_PLLSAIRDIV(1) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/4 */ -#define RCU_PLLSAIR_DIV8 CFG1_PLLSAIRDIV(2) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/8 */ -#define RCU_PLLSAIR_DIV16 CFG1_PLLSAIRDIV(3) /*!< CK_PLLSAIRDIV clock select CK_PLLSAIR/16 */ - -/* TIMER clock selection */ -#define RCU_TIMER_PSC_MUL2 ~RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) - or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; - TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) */ -#define RCU_TIMER_PSC_MUL4 RCU_CFG1_TIMERSEL /*!< if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; - TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) */ - -/* RCU_PLLSSCTL register bit define */ -/* PLL spread spectrum modulation type select */ -#define RCU_SS_TYPE_CENTER ((uint32_t)0x00000000U) /*!< center type is selected */ -#define RCU_SS_TYPE_DOWN RCU_PLLSSCTL_SS_TYPE /*!< down type is selected */ - -/* RCU_PLL register bit define */ -/* The PLL VCO source clock prescaler */ -#define RCU_PLLPSC_DIV_MIN ((uint32_t)2U) /*!< PLLPSC_DIV min value */ -#define RCU_PLLPSC_DIV_MAX ((uint32_t)63U) /*!< PLLPSC_DIV max value */ - -/* The PLL VCO clock multi factor */ -#define RCU_PLLN_MUL_MIN ((uint32_t)64U) /*!< PLLN_MUL min value */ -#define RCU_PLLN_MUL_MAX ((uint32_t)500U) /*!< PLLN_MUL max value */ -#define RCU_SS_MODULATION_CENTER_INC ((uint32_t)5U) /*!< minimum factor of PLLN in center mode */ -#define RCU_SS_MODULATION_DOWN_INC ((uint32_t)7U) /*!< minimum factor of PLLN in down mode */ - -/* The PLLP output frequency division factor from PLL VCO clock */ -#define RCU_PLLP_DIV_MIN ((uint32_t)2U) /*!< PLLP_DIV min value */ -#define RCU_PLLP_DIV_MAX ((uint32_t)8U) /*!< PLLP_DIV max value */ - -/* PLL Clock Source Selection */ -#define RCU_PLLSRC_IRC16M ((uint32_t)0x00000000U) /*!< IRC16M clock selected as source clock of PLL, PLLSAI, PLLI2S */ -#define RCU_PLLSRC_HXTAL RCU_PLL_PLLSEL /*!< HXTAL clock selected as source clock of PLL, PLLSAI, PLLI2S */ - -/* The PLL Q output frequency division factor from PLL VCO clock */ -#define RCU_PLLQ_DIV_MIN ((uint32_t)2U) /*!< PLLQ_DIV min value */ -#define RCU_PLLQ_DIV_MAX ((uint32_t)15U) /*!< PLLQ_DIV max value */ - -#define CHECK_PLL_PSC_VALID(val) (((val) >= RCU_PLLPSC_DIV_MIN)&&((val) <= RCU_PLLPSC_DIV_MAX)) -#define CHECK_PLL_N_VALID(val, inc) (((val) >= (RCU_PLLN_MUL_MIN + (inc)))&&((val) <= RCU_PLLN_MUL_MAX)) -#define CHECK_PLL_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) -#define CHECK_PLL_Q_VALID(val) (((val) >= RCU_PLLQ_DIV_MIN)&&((val) <= RCU_PLLQ_DIV_MAX)) - -/* RCU_BDCTL register bit define */ -/* LXTAL drive capability */ -#define RCU_LXTALDRI_LOWER_DRIVE ((uint32_t)0x00000000) /*!< LXTAL drive capability is selected lower */ -#define RCU_LXTALDRI_HIGHER_DRIVE RCU_BDCTL_LXTALDRI /*!< LXTAL drive capability is selected higher */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ -#define RCU_RTCSRC_IRC32K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC32K */ -#define RCU_RTCSRC_HXTAL_DIV_RTCDIV BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/RTCDIV */ - -/* RCU_PLLI2S register bit define */ -/* The PLLI2S VCO clock multi factor */ -#define RCU_PLLI2SN_MUL_MIN 50U -#define RCU_PLLI2SN_MUL_MAX 500U - -/* The PLLI2S Q output frequency division factor from PLLI2S VCO clock */ -#define RCU_PLLI2SQ_DIV_MIN 2U -#define RCU_PLLI2SQ_DIV_MAX 15U - -/* The PLLI2S R output frequency division factor from PLLI2S VCO clock */ -#define RCU_PLLI2SR_DIV_MIN 2U -#define RCU_PLLI2SR_DIV_MAX 7U - -/* RCU_PLLSAI register bit define */ -/* The PLLSAI VCO clock multi factor */ -#define RCU_PLLSAIN_MUL_MIN 50U -#define RCU_PLLSAIN_MUL_MAX 500U - -/* The PLLSAI P output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAIP_DIV_MIN 2U -#define RCU_PLLSAIP_DIV_MAX 8U - -/* The PLLSAI Q output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAIQ_DIV_MIN 2U -#define RCU_PLLSAIQ_DIV_MAX 15U - -/* The PLLSAI R output frequency division factor from PLLSAI VCO clock */ -#define RCU_PLLSAIR_DIV_MIN 2U -#define RCU_PLLSAIR_DIV_MAX 7U - -#define CHECK_PLLI2S_PSC_VALID(val) (((val) >= RCU_PLLI2SPSC_DIV_MIN)&&((val) <= RCU_PLLI2SPSC_DIV_MAX)) -#define CHECK_PLLI2S_N_VALID(val) (((val) >= RCU_PLLI2SN_MUL_MIN)&&((val) <= RCU_PLLI2SN_MUL_MAX)) -#define CHECK_PLLI2S_Q_VALID(val) (((val) >= RCU_PLLI2SQ_DIV_MIN)&&((val) <= RCU_PLLI2SQ_DIV_MAX)) -#define CHECK_PLLI2S_R_VALID(val) (((val) >= RCU_PLLI2SR_DIV_MIN)&&((val) <= RCU_PLLI2SR_DIV_MAX)) - -#define CHECK_PLLSAI_N_VALID(val) (((val) >= (RCU_PLLSAIN_MUL_MIN))&&((val) <= RCU_PLLSAIN_MUL_MAX)) -#define CHECK_PLLSAI_P_VALID(val) (((val) == 2U) || ((val) == 4U) || ((val) == 6U) || ((val) == 8U)) -#define CHECK_PLLSAI_Q_VALID(val) (((val) >= RCU_PLLSAIQ_DIV_MIN)&&((val) <= RCU_PLLSAIQ_DIV_MAX)) -#define CHECK_PLLSAI_R_VALID(val) (((val) >= RCU_PLLSAIR_DIV_MIN)&&((val) <= RCU_PLLSAIR_DIV_MAX)) - -/* RCU_ADDCTL register bit define */ -/* 48MHz clock selection */ -#define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ -#define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ - -/* PLL48M clock selection */ -#define RCU_PLL48MSRC_PLLQ ((uint32_t)0x00000000U) /*!< PLL48M source clock select PLLQ */ -#define RCU_PLL48MSRC_PLLSAIP RCU_ADDCTL_PLL48MSEL /*!< PLL48M source clock select PLLSAIP */ - -/* Deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ - - -/* function declarations */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP */ -void rcu_bkp_reset_enable(void); -/* disable the BKP reset */ -void rcu_bkp_reset_disable(void); - -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the CK_OUT0 clock source and divider */ -void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div); -/* configure the CK_OUT1 clock source and divider */ -void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div); -/* configure the PLL clock source selection and PLL multiply factor */ -ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q); -/* configure the PLLI2S clock */ -ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r); -/* configure the PLLSAI clock */ -ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -/* cconfigure the frequency division of RTC clock when HXTAL was selected as its clock source */ -void rcu_rtc_div_config(uint32_t rtc_div); -/* configure the I2S clock source selection */ -void rcu_i2s_clock_config(uint32_t i2s_clock_source); -/* configure the CK48M clock selection */ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); -/* configure the PLL48M clock selection */ -void rcu_pll48m_clock_config(uint32_t pll48m_clock_source); -/* configure the TIMER clock prescaler selection */ -void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler); -/* configure the TLI clock division selection */ -void rcu_tli_clock_div_config(uint32_t pllsai_r_div); - - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum interrupt); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum interrupt); - -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC16M adjust value */ -void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval); -/* configure the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt); -/* enable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_enable(void); -/* disable the spread spectrum modulation for the main PLL clock */ -void rcu_spread_spectrum_disable(void); -/* unlock the voltage key */ -void rcu_voltage_key_unlock(void); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32F4XX_RCU_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h deleted file mode 100644 index 75e66f236e..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_rtc.h +++ /dev/null @@ -1,640 +0,0 @@ -/*! - \file gd32f4xx_rtc.c - \brief definitions for the RTC - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F4XX_RTC_H -#define GD32F4XX_RTC_H - -#include "gd32f4xx.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_TIME REG32((RTC) + 0x00U) /*!< RTC time of day register */ -#define RTC_DATE REG32((RTC) + 0x04U) /*!< RTC date register */ -#define RTC_CTL REG32((RTC) + 0x08U) /*!< RTC control register */ -#define RTC_STAT REG32((RTC) + 0x0CU) /*!< RTC status register */ -#define RTC_PSC REG32((RTC) + 0x10U) /*!< RTC time prescaler register */ -#define RTC_WUT REG32((RTC) + 0x14U) /*!< RTC wakeup timer regiser */ -#define RTC_COSC REG32((RTC) + 0x18U) /*!< RTC coarse calibration register */ -#define RTC_ALRM0TD REG32((RTC) + 0x1CU) /*!< RTC alarm 0 time and date register */ -#define RTC_ALRM1TD REG32((RTC) + 0x20U) /*!< RTC alarm 1 time and date register */ -#define RTC_WPK REG32((RTC) + 0x24U) /*!< RTC write protection key register */ -#define RTC_SS REG32((RTC) + 0x28U) /*!< RTC sub second register */ -#define RTC_SHIFTCTL REG32((RTC) + 0x2CU) /*!< RTC shift function control register */ -#define RTC_TTS REG32((RTC) + 0x30U) /*!< RTC time of timestamp register */ -#define RTC_DTS REG32((RTC) + 0x34U) /*!< RTC date of timestamp register */ -#define RTC_SSTS REG32((RTC) + 0x38U) /*!< RTC sub second of timestamp register */ -#define RTC_HRFC REG32((RTC) + 0x3CU) /*!< RTC high resolution frequency compensation registor */ -#define RTC_TAMP REG32((RTC) + 0x40U) /*!< RTC tamper register */ -#define RTC_ALRM0SS REG32((RTC) + 0x44U) /*!< RTC alarm 0 sub second register */ -#define RTC_ALRM1SS REG32((RTC) + 0x48U) /*!< RTC alarm 1 sub second register */ -#define RTC_BKP0 REG32((RTC) + 0x50U) /*!< RTC backup register */ -#define RTC_BKP1 REG32((RTC) + 0x54U) /*!< RTC backup register */ -#define RTC_BKP2 REG32((RTC) + 0x58U) /*!< RTC backup register */ -#define RTC_BKP3 REG32((RTC) + 0x5CU) /*!< RTC backup register */ -#define RTC_BKP4 REG32((RTC) + 0x60U) /*!< RTC backup register */ -#define RTC_BKP5 REG32((RTC) + 0x64U) /*!< RTC backup register */ -#define RTC_BKP6 REG32((RTC) + 0x68U) /*!< RTC backup register */ -#define RTC_BKP7 REG32((RTC) + 0x6CU) /*!< RTC backup register */ -#define RTC_BKP8 REG32((RTC) + 0x70U) /*!< RTC backup register */ -#define RTC_BKP9 REG32((RTC) + 0x74U) /*!< RTC backup register */ -#define RTC_BKP10 REG32((RTC) + 0x78U) /*!< RTC backup register */ -#define RTC_BKP11 REG32((RTC) + 0x7CU) /*!< RTC backup register */ -#define RTC_BKP12 REG32((RTC) + 0x80U) /*!< RTC backup register */ -#define RTC_BKP13 REG32((RTC) + 0x84U) /*!< RTC backup register */ -#define RTC_BKP14 REG32((RTC) + 0x88U) /*!< RTC backup register */ -#define RTC_BKP15 REG32((RTC) + 0x8CU) /*!< RTC backup register */ -#define RTC_BKP16 REG32((RTC) + 0x90U) /*!< RTC backup register */ -#define RTC_BKP17 REG32((RTC) + 0x94U) /*!< RTC backup register */ -#define RTC_BKP18 REG32((RTC) + 0x98U) /*!< RTC backup register */ -#define RTC_BKP19 REG32((RTC) + 0x9CU) /*!< RTC backup register */ - -/* bits definitions */ -/* RTC_TIME */ -#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DATE */ -#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ -#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ -#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ - -/* RTC_CTL */ -#define RTC_CTL_WTCS BITS(0,2) /*!< auto wakeup timer clock selection */ -#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ -#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ -#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ -#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ -#define RTC_CTL_CCEN BIT(7) /*!< coarse calibration function enable */ -#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm0 function enable */ -#define RTC_CTL_ALRM1EN BIT(9) /*!< alarm1 function enable */ -#define RTC_CTL_WTEN BIT(10) /*!< auto wakeup timer function enable */ -#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ -#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm0 interrupt enable */ -#define RTC_CTL_ALRM1IE BIT(13) /*!< RTC alarm1 interrupt enable */ -#define RTC_CTL_WTIE BIT(14) /*!< auto wakeup timer interrupt enable */ -#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ -#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ -#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ -#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ -#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ -#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ -#define RTC_CTL_OS BITS(21,22) /*!< output selection */ -#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ - -/* RTC_STAT */ -#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm0 configuration can be write flag */ -#define RTC_STAT_ALRM1WF BIT(1) /*!< alarm1 configuration can be write flag */ -#define RTC_STAT_WTWF BIT(2) /*!< wakeup timer can be write flag */ -#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ -#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ -#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ -#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ -#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ -#define RTC_STAT_ALRM0F BIT(8) /*!< alarm0 occurs flag */ -#define RTC_STAT_ALRM1F BIT(9) /*!< alarm1 occurs flag */ -#define RTC_STAT_WTF BIT(10) /*!< wakeup timer occurs flag */ -#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ -#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ -#define RTC_STAT_TP0F BIT(13) /*!< RTC tamper 0 detected flag */ -#define RTC_STAT_TP1F BIT(14) /*!< RTC tamper 1 detected flag */ -#define RTC_STAT_SCPF BIT(16) /*!< smooth calibration pending flag */ - -/* RTC_PSC */ -#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ -#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ - -/* RTC_WUT */ -#define RTC_WUT_WTRV BITS(0,15) /*!< auto wakeup timer reloads value */ - -/* RTC_COSC */ -#define RTC_COSC_COSS BITS(0,4) /*!< coarse calibration step */ -#define RTC_COSC_COSD BIT(7) /*!< coarse calibration direction */ - -/* RTC_ALRMxTD */ -#define RTC_ALRMXTD_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_ALRMXTD_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_ALRMXTD_MSKS BIT(7) /*!< alarm second mask bit */ -#define RTC_ALRMXTD_MNU BITS(8,11) /*!< minutes units in BCD code */ -#define RTC_ALRMXTD_MNT BITS(12,14) /*!< minutes tens in BCD code */ -#define RTC_ALRMXTD_MSKM BIT(15) /*!< alarm minutes mask bit */ -#define RTC_ALRMXTD_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_ALRMXTD_HRT BITS(20,21) /*!< hour units in BCD code */ -#define RTC_ALRMXTD_PM BIT(22) /*!< AM/PM flag */ -#define RTC_ALRMXTD_MSKH BIT(23) /*!< alarm hour mask bit */ -#define RTC_ALRMXTD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ -#define RTC_ALRMXTD_DAYT BITS(28,29) /*!< date tens in BCD code */ -#define RTC_ALRMXTD_DOWS BIT(30) /*!< day of week selection */ -#define RTC_ALRMXTD_MSKD BIT(31) /*!< alarm date mask bit */ - -/* RTC_WPK */ -#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ - -/* RTC_SS */ -#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ - -/* RTC_SHIFTCTL */ -#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ -#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ - -/* RTC_TTS */ -#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ -#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DTS */ -#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ - -/* RTC_SSTS */ -#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ - -/* RTC_HRFC */ -#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ -#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ - -/* RTC_TAMP */ -#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ -#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ -#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ -#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ -#define RTC_TAMP_TP1EG BIT(4) /*!< Tamper 1 event trigger edge for RTC tamp 1 input */ -#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ -#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ -#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ -#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ -#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ -#define RTC_TAMP_TP0SEL BIT(16) /*!< Tamper 0 function input mapping selection */ -#define RTC_TAMP_TSSEL BIT(17) /*!< Timestamp input mapping selection */ -#define RTC_TAMP_AOT BIT(18) /*!< RTC_ALARM output Type */ - -/* RTC_ALRM0SS */ -#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm0 sub second value */ -#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ - -/* RTC_ALRM1SS */ -#define RTC_ALRM1SS_SSC BITS(0,14) /*!< alarm1 sub second value */ -#define RTC_ALRM1SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ - -/* constants definitions */ -/* structure for initialization of the RTC */ -typedef struct -{ - uint8_t year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ - uint8_t month; /*!< RTC month value */ - uint8_t date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ - uint8_t day_of_week; /*!< RTC weekday value */ - uint8_t hour; /*!< RTC hour value */ - uint8_t minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ - uint8_t second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ - uint16_t factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ - uint16_t factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ - uint32_t am_pm; /*!< RTC AM/PM value */ - uint32_t display_format; /*!< RTC time notation */ -}rtc_parameter_struct; - -/* structure for RTC alarm configuration */ -typedef struct -{ - uint32_t alarm_mask; /*!< RTC alarm mask */ - uint32_t weekday_or_date; /*!< specify RTC alarm is on date or weekday */ - uint8_t alarm_day; /*!< RTC alarm date or weekday value*/ - uint8_t alarm_hour; /*!< RTC alarm hour value */ - uint8_t alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ - uint8_t alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ - uint32_t am_pm; /*!< RTC alarm AM/PM value */ -}rtc_alarm_struct; - -/* structure for RTC time-stamp configuration */ -typedef struct -{ - uint8_t timestamp_month; /*!< RTC time-stamp month value */ - uint8_t timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ - uint8_t timestamp_day; /*!< RTC time-stamp weekday value */ - uint8_t timestamp_hour; /*!< RTC time-stamp hour value */ - uint8_t timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ - uint8_t timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ - uint32_t am_pm; /*!< RTC time-stamp AM/PM value */ -}rtc_timestamp_struct; - -/* structure for RTC tamper configuration */ -typedef struct -{ - uint32_t tamper_source; /*!< RTC tamper source */ - uint32_t tamper_trigger; /*!< RTC tamper trigger */ - uint32_t tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ - uint32_t tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ - ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ - uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ - ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ -}rtc_tamper_struct; - -/* time register value */ -#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */ -#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ - -#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TIME_MN bit field */ -#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ - -#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TIME_HR bit field */ -#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ - -#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ -#define RTC_PM RTC_TIME_PM /*!< PM format */ - -/* date register value */ -#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DATE_DAY bit field */ -#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ - -#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DATE_MON bit field */ -#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ -#define RTC_JAN ((uint8_t)0x01U) /*!< janurary */ -#define RTC_FEB ((uint8_t)0x02U) /*!< february */ -#define RTC_MAR ((uint8_t)0x03U) /*!< march */ -#define RTC_APR ((uint8_t)0x04U) /*!< april */ -#define RTC_MAY ((uint8_t)0x05U) /*!< may */ -#define RTC_JUN ((uint8_t)0x06U) /*!< june */ -#define RTC_JUL ((uint8_t)0x07U) /*!< july */ -#define RTC_AUG ((uint8_t)0x08U) /*!< august */ -#define RTC_SEP ((uint8_t)0x09U) /*!< september */ -#define RTC_OCT ((uint8_t)0x10U) /*!< october */ -#define RTC_NOV ((uint8_t)0x11U) /*!< november */ -#define RTC_DEC ((uint8_t)0x12U) /*!< december */ - -#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DATE_DOW bit field */ -#define GET_DATE_DOW(regval) GET_BITS((uint32_t)(regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ -#define RTC_MONDAY ((uint8_t)0x01) /*!< monday */ -#define RTC_TUESDAY ((uint8_t)0x02) /*!< tuesday */ -#define RTC_WEDSDAY ((uint8_t)0x03) /*!< wednesday */ -#define RTC_THURSDAY ((uint8_t)0x04) /*!< thursday */ -#define RTC_FRIDAY ((uint8_t)0x05) /*!< friday */ -#define RTC_SATURDAY ((uint8_t)0x06) /*!< saturday */ -#define RTC_SUNDAY ((uint8_t)0x07) /*!< sunday */ - -#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_DATE_YR bit field */ -#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ - -/* ctl register value */ -#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) /*!< write value to RTC_CTL_OS bit field */ -#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ -#define RTC_OS_ALARM0 CTL_OS(1) /*!< enable alarm0 flag output */ -#define RTC_OS_ALARM1 CTL_OS(2) /*!< enable alarm1 flag output */ -#define RTC_OS_WAKEUP CTL_OS(3) /*!< enable wakeup flag output */ - -#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ -#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */ -#define RTC_ALARM0_HIGH RTC_OS_ALARM0 /*!< enable alarm0 flag output with high level */ -#define RTC_ALARM0_LOW (RTC_OS_ALARM0 | RTC_CTL_OPOL) /*!< enable alarm0 flag output with low level*/ -#define RTC_ALARM1_HIGH RTC_OS_ALARM1 /*!< enable alarm1 flag output with high level */ -#define RTC_ALARM1_LOW (RTC_OS_ALARM1 | RTC_CTL_OPOL) /*!< enable alarm1 flag output with low level*/ -#define RTC_WAKEUP_HIGH RTC_OS_WAKEUP /*!< enable wakeup flag output with high level */ -#define RTC_WAKEUP_LOW (RTC_OS_WAKEUP | RTC_CTL_OPOL) /*!< enable wakeup flag output with low level*/ - -#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ -#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ - -#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ -#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ - -/* psc register value */ -#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_PSC_FACTOR_S bit field */ -#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ - -#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_PSC_FACTOR_A bit field */ -#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ - -/* alrmtd register value */ -#define ALRMTD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMTD_SC bit field */ -#define GET_ALRMTD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRMTD_SC bit field */ - -#define ALRMTD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_ALRMTD_MN bit field */ -#define GET_ALRMTD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRMTD_MN bit field */ - -#define ALRMTD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_ALRMTD_HR bit field */ -#define GET_ALRMTD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRMTD_HR bit field */ - -#define ALRMTD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMTD_DAY bit field */ -#define GET_ALRMTD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRMTD_DAY bit field */ - -#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ -#define RTC_ALARM_DATE_MASK RTC_ALRMXTD_MSKD /*!< alarm date mask */ -#define RTC_ALARM_HOUR_MASK RTC_ALRMXTD_MSKH /*!< alarm hour mask */ -#define RTC_ALARM_MINUTE_MASK RTC_ALRMXTD_MSKM /*!< alarm minute mask */ -#define RTC_ALARM_SECOND_MASK RTC_ALRMXTD_MSKS /*!< alarm second mask */ -#define RTC_ALARM_ALL_MASK (RTC_ALRMXTD_MSKD|RTC_ALRMXTD_MSKH|RTC_ALRMXTD_MSKM|RTC_ALRMXTD_MSKS) /*!< alarm all mask */ - -#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ -#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRMXTD_DOWS /*!< alarm weekday format selected */ - -/* wpk register value */ -#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_WPK_WPK bit field */ - -/* ss register value */ -#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SS_SSC bit field */ - -/* shiftctl register value */ -#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ - -#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ -#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ - -/* tts register value */ -#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TTS_SC bit field */ -#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ - -#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TTS_MN bit field */ -#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ - -#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TTS_HR bit field */ -#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ - -/* dts register value */ -#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DTS_DAY bit field */ -#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ - -#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */ -#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ - -#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */ -#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ - -/* ssts register value */ -#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SSTS_SSC bit field */ - -/* hrfc register value */ -#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_HRFC_CMSK bit field */ - -#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ - -#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ -#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ - -/* tamp register value */ -#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */ -#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ - -#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< write value to RTC_TAMP_FLT bit field */ -#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ -#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ -#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ -#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ - -#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_TAMP_PRCH bit field */ -#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ - -#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ -#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ - -#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ -#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ - -#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ - -#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ -#define RTC_ALARM_OUTPUT_PP RTC_TAMP_AOT /*!< RTC alarm output push-pull mode */ - -/* ALRMXSS register value */ -#define ALRMXSS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMXSS_SSC bit field */ - -#define ALRMXSS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMXSS_MASKSSC bit field */ -#define RTC_MASKSSC_0_14 ALRMXSS_MASKSSC(0) /*!< mask alarm subsecond configuration */ -#define RTC_MASKSSC_1_14 ALRMXSS_MASKSSC(1) /*!< mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared */ -#define RTC_MASKSSC_2_14 ALRMXSS_MASKSSC(2) /*!< mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared */ -#define RTC_MASKSSC_3_14 ALRMXSS_MASKSSC(3) /*!< mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared */ -#define RTC_MASKSSC_4_14 ALRMXSS_MASKSSC(4) /*!< mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared */ -#define RTC_MASKSSC_5_14 ALRMXSS_MASKSSC(5) /*!< mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared */ -#define RTC_MASKSSC_6_14 ALRMXSS_MASKSSC(6) /*!< mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared */ -#define RTC_MASKSSC_7_14 ALRMXSS_MASKSSC(7) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */ -#define RTC_MASKSSC_8_14 ALRMXSS_MASKSSC(8) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */ -#define RTC_MASKSSC_9_14 ALRMXSS_MASKSSC(9) /*!< mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared */ -#define RTC_MASKSSC_10_14 ALRMXSS_MASKSSC(10) /*!< mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared */ -#define RTC_MASKSSC_11_14 ALRMXSS_MASKSSC(11) /*!< mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared */ -#define RTC_MASKSSC_12_14 ALRMXSS_MASKSSC(12) /*!< mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared */ -#define RTC_MASKSSC_13_14 ALRMXSS_MASKSSC(13) /*!< mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared */ -#define RTC_MASKSSC_14 ALRMXSS_MASKSSC(14) /*!< mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared */ -#define RTC_MASKSSC_NONE ALRMXSS_MASKSSC(15) /*!< mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared */ - -/* RTC interrupt source */ -#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ -#define RTC_INT_ALARM0 RTC_CTL_ALRM0IE /*!< RTC alarm0 interrupt enable */ -#define RTC_INT_ALARM1 RTC_CTL_ALRM1IE /*!< RTC alarm1 interrupt enable */ -#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ -#define RTC_INT_WAKEUP RTC_CTL_WTIE /*!< RTC wakeup timer interrupt enable */ - -/* write protect key */ -#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ -#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ -#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ - -/* registers reset value */ -#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ -#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ -#define RTC_STAT_RESET ((uint32_t)0x00000000U) /*!< RTC_STAT register reset value */ -#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ -#define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */ - -/* RTC alarm */ -#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */ -#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */ - -/* RTC coarse calibration direction */ -#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */ -#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */ - -/* RTC wakeup timer clock */ -#define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0)) -#define WAKEUP_RTCCK_DIV16 CTL_WTCS(0) /*!< wakeup timer clock is RTC clock divided by 16 */ -#define WAKEUP_RTCCK_DIV8 CTL_WTCS(1) /*!< wakeup timer clock is RTC clock divided by 8 */ -#define WAKEUP_RTCCK_DIV4 CTL_WTCS(2) /*!< wakeup timer clock is RTC clock divided by 4 */ -#define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */ -#define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */ -#define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */ - -/* RTC_AF pin */ -#define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */ -#define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */ -#define RTC_AF0_TAMPER0 ((uint32_t)0x00000000) /*!< RTC_AF0 use for tamper0 */ -#define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */ - -/* RTC flags */ -#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */ -#define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */ -#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */ -#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */ -#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year configuration mark status flag */ -#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< register synchronization flag */ -#define RTC_FLAG_INIT RTC_STAT_INITF /*!< initialization state flag */ -#define RTC_FLAG_ALRM0 RTC_STAT_ALRM0F /*!< alarm0 occurs flag */ -#define RTC_FLAG_ALRM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */ -#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */ -#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */ -#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */ -#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */ -#define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */ -#define RTC_STAT_SCP RTC_STAT_SCPF /*!< smooth calibration pending flag */ - -/* function declarations */ -/* reset most of the RTC registers */ -ErrStatus rtc_deinit(void); -/* initialize RTC registers */ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); -/* enter RTC init mode */ -ErrStatus rtc_init_mode_enter(void); -/* exit RTC init mode */ -void rtc_init_mode_exit(void); -/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ -ErrStatus rtc_register_sync_wait(void); - -/* get current time and date */ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); -/* get current subsecond value */ -uint32_t rtc_subsecond_get(void); - -/* configure RTC alarm */ -void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time); -/* configure subsecond of RTC alarm */ -void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond); -/* get RTC alarm */ -void rtc_alarm_get(uint8_t rtc_alarm,rtc_alarm_struct* rtc_alarm_time); -/* get RTC alarm subsecond */ -uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm); -/* enable RTC alarm */ -void rtc_alarm_enable(uint8_t rtc_alarm); -/* disable RTC alarm */ -ErrStatus rtc_alarm_disable(uint8_t rtc_alarm); - -/* enable RTC time-stamp */ -void rtc_timestamp_enable(uint32_t edge); -/* disable RTC time-stamp */ -void rtc_timestamp_disable(void); -/* get RTC timestamp time and date */ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); -/* get RTC time-stamp subsecond */ -uint32_t rtc_timestamp_subsecond_get(void); -/* RTC time-stamp pin map */ -void rtc_timestamp_pin_map(uint32_t rtc_af); - -/* enable RTC tamper */ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); -/* disable RTC tamper */ -void rtc_tamper_disable(uint32_t source); -/* RTC tamper0 pin map */ -void rtc_tamper0_pin_map(uint32_t rtc_af); - -/* enable specified RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disble specified RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); -/* check specified flag */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear specified flag */ -void rtc_flag_clear(uint32_t flag); - -/* configure RTC alarm output source */ -void rtc_alarm_output_config(uint32_t source, uint32_t mode); -/* configure RTC calibration output source */ -void rtc_calibration_output_config(uint32_t source); - -/* adjust the daylight saving time by adding or substracting one hour from the current time */ -void rtc_hour_adjust(uint32_t operation); -/* adjust RTC second or subsecond value of current time */ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); - -/* enable RTC bypass shadow registers function */ -void rtc_bypass_shadow_enable(void); -/* disable RTC bypass shadow registers function */ -void rtc_bypass_shadow_disable(void); - -/* enable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_enable(void); -/* disable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_disable(void); - -/* enable RTC wakeup timer */ -void rtc_wakeup_enable(void); -/* disable RTC wakeup timer */ -ErrStatus rtc_wakeup_disable(void); -/* set auto wakeup timer clock */ -ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock); -/* set auto wakeup timer value */ -ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer); -/* get auto wakeup timer value */ -uint16_t rtc_wakeup_timer_get(void); - -/* configure RTC smooth calibration */ -ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); -/* enable RTC coarse calibration */ -ErrStatus rtc_coarse_calibration_enable(void); -/* disable RTC coarse calibration */ -ErrStatus rtc_coarse_calibration_disable(void); -/* configure RTC coarse calibration direction and step */ -ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step); - -#endif /* GD32F4XX_RTC_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h deleted file mode 100644 index a18214c023..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_sdio.h +++ /dev/null @@ -1,433 +0,0 @@ -/*! - \file gd32f4xx_sdio.h - \brief definitions for the SDIO - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_SDIO_H -#define GD32F4XX_SDIO_H - -#include "gd32f4xx.h" - -/* SDIO definitions */ -#define SDIO SDIO_BASE - -/* registers definitions */ -#define SDIO_PWRCTL REG32(SDIO + 0x00U) /*!< SDIO power control register */ -#define SDIO_CLKCTL REG32(SDIO + 0x04U) /*!< SDIO clock control register */ -#define SDIO_CMDAGMT REG32(SDIO + 0x08U) /*!< SDIO command argument register */ -#define SDIO_CMDCTL REG32(SDIO + 0x0CU) /*!< SDIO command control register */ -#define SDIO_RSPCMDIDX REG32(SDIO + 0x10U) /*!< SDIO command index response register */ -#define SDIO_RESP0 REG32(SDIO + 0x14U) /*!< SDIO response register 0 */ -#define SDIO_RESP1 REG32(SDIO + 0x18U) /*!< SDIO response register 1 */ -#define SDIO_RESP2 REG32(SDIO + 0x1CU) /*!< SDIO response register 2 */ -#define SDIO_RESP3 REG32(SDIO + 0x20U) /*!< SDIO response register 3 */ -#define SDIO_DATATO REG32(SDIO + 0x24U) /*!< SDIO data timeout register */ -#define SDIO_DATALEN REG32(SDIO + 0x28U) /*!< SDIO data length register */ -#define SDIO_DATACTL REG32(SDIO + 0x2CU) /*!< SDIO data control register */ -#define SDIO_DATACNT REG32(SDIO + 0x30U) /*!< SDIO data counter register */ -#define SDIO_STAT REG32(SDIO + 0x34U) /*!< SDIO status register */ -#define SDIO_INTC REG32(SDIO + 0x38U) /*!< SDIO interrupt clear register */ -#define SDIO_INTEN REG32(SDIO + 0x3CU) /*!< SDIO interrupt enable register */ -#define SDIO_FIFOCNT REG32(SDIO + 0x48U) /*!< SDIO FIFO counter register */ -#define SDIO_FIFO REG32(SDIO + 0x80U) /*!< SDIO FIFO data register */ - -/* bits definitions */ -/* SDIO_PWRCTL */ -#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */ - -/* SDIO_CLKCTL */ -#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */ -#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */ -#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */ -#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */ -#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */ -#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */ -#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */ - -/* SDIO_CMDAGMT */ -#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */ - -/* SDIO_CMDCTL */ -#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */ -#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */ -#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */ -#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */ -#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */ -#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */ -#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */ -#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */ -#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */ - -/* SDIO_DATATO */ -#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */ - -/* SDIO_DATALEN */ -#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */ - -/* SDIO_DATACTL */ -#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */ -#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */ -#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */ -#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */ -#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */ -#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */ -#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */ -#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */ -#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */ - -/* SDIO_STAT */ -#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */ -#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */ -#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */ -#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */ -#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */ -#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */ -#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */ -#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */ -#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */ -#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */ -#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */ -#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */ -#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */ -#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */ -#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */ -#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */ -#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */ -#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */ -#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */ -#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */ -#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */ -#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */ -#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */ -#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */ - -/* SDIO_INTC */ -#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */ -#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */ -#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */ -#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */ -#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */ -#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */ -#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */ -#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */ -#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */ -#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */ -#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */ -#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */ -#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */ - -/* SDIO_INTEN */ -#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */ -#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */ -#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */ -#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */ -#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */ -#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */ -#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */ -#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */ -#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */ -#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */ -#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */ -#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */ -#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */ -#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */ -#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */ -#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */ -#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */ -#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */ -#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */ -#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */ -#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */ -#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */ -#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */ -#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */ - -/* SDIO_FIFO */ -#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */ - -/* constants definitions */ -/* SDIO flags */ -#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */ -#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */ -#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */ -#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */ -#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */ -#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */ -#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */ -#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */ -#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */ -#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */ -#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */ -#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */ -#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */ -#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */ -#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */ -#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */ -#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */ -#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */ -#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */ -#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */ -#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */ -#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */ -#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */ -#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */ - -/* SDIO interrupt enable or disable */ -#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */ -#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */ -#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */ -#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */ -#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */ -#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */ -#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */ -#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */ -#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */ -#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */ -#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */ -#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */ -#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */ -#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */ -#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */ -#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */ -#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */ -#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */ -#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */ -#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */ -#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */ -#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */ -#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */ -#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */ - -/* SDIO interrupt flags */ -#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */ -#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */ -#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */ -#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */ -#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */ -#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */ -#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */ -#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */ -#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */ -#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */ -#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */ -#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */ -#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */ -#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */ -#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */ -#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */ -#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */ -#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */ -#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */ -#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */ -#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */ -#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */ -#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */ -#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */ - -/* SDIO power control */ -#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */ -#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */ - -/* SDIO card bus mode control */ -#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */ -#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */ -#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */ - -/* SDIO_CLK clock edge selection */ -#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */ -#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */ - -/* clock bypass enable or disable */ -#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */ -#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */ - -/* SDIO_CLK clock dynamic switch on/off for power saving */ -#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */ -#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */ - -/* SDIO command response type */ -#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */ -#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */ -#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */ - -/* command state machine wait type */ -#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */ -#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */ -#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */ - -#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */ -#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */ -#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */ -#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */ - -/* SDIO data block size */ -#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */ -#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */ -#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */ -#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */ -#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */ -#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */ -#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */ -#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */ -#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */ -#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */ -#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */ -#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */ -#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */ -#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */ -#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */ - -/* SDIO data transfer mode */ -#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */ -#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */ - -/* SDIO data transfer direction */ -#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */ -#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */ - -/* SDIO read wait type */ -#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */ -#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */ - -/* function declarations */ -/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */ -/* deinitialize the SDIO */ -void sdio_deinit(void); -/* configure the SDIO clock */ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division); -/* enable hardware clock control */ -void sdio_hardware_clock_enable(void); -/* disable hardware clock control */ -void sdio_hardware_clock_disable(void); -/* set different SDIO card bus mode */ -void sdio_bus_mode_set(uint32_t bus_mode); -/* set the SDIO power state */ -void sdio_power_state_set(uint32_t power_state); -/* get the SDIO power state */ -uint32_t sdio_power_state_get(void); -/* enable SDIO_CLK clock output */ -void sdio_clock_enable(void); -/* disable SDIO_CLK clock output */ -void sdio_clock_disable(void); - -/* configure the command index, argument, response type, wait type and CSM to send command functions */ -/* configure the command and response */ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type); -/* set the command state machine wait type */ -void sdio_wait_type_set(uint32_t wait_type); -/* enable the CSM(command state machine) */ -void sdio_csm_enable(void); -/* disable the CSM(command state machine) */ -void sdio_csm_disable(void); -/* get the last response command index */ -uint8_t sdio_command_index_get(void); -/* get the response for the last received command */ -uint32_t sdio_response_get(uint32_t sdio_responsex); - -/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */ -/* configure the data timeout, data length and data block size */ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize); -/* configure the data transfer mode and direction */ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction); -/* enable the DSM(data state machine) for data transfer */ -void sdio_dsm_enable(void); -/* disable the DSM(data state machine) */ -void sdio_dsm_disable(void); -/* write data(one word) to the transmit FIFO */ -void sdio_data_write(uint32_t data); -/* read data(one word) from the receive FIFO */ -uint32_t sdio_data_read(void); -/* get the number of remaining data bytes to be transferred to card */ -uint32_t sdio_data_counter_get(void); -/* get the number of words remaining to be written or read from FIFO */ -uint32_t sdio_fifo_counter_get(void); -/* enable the DMA request for SDIO */ -void sdio_dma_enable(void); -/* disable the DMA request for SDIO */ -void sdio_dma_disable(void); - -/* flag and interrupt functions */ -/* get the flags state of SDIO */ -FlagStatus sdio_flag_get(uint32_t flag); -/* clear the pending flags of SDIO */ -void sdio_flag_clear(uint32_t flag); -/* enable the SDIO interrupt */ -void sdio_interrupt_enable(uint32_t int_flag); -/* disable the SDIO interrupt */ -void sdio_interrupt_disable(uint32_t int_flag); -/* get the interrupt flags state of SDIO */ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag); -/* clear the interrupt pending flags of SDIO */ -void sdio_interrupt_flag_clear(uint32_t int_flag); - -/* SD I/O card functions */ -/* enable the read wait mode(SD I/O only) */ -void sdio_readwait_enable(void); -/* disable the read wait mode(SD I/O only) */ -void sdio_readwait_disable(void); -/* enable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_enable(void); -/* disable the function that stop the read wait process(SD I/O only) */ -void sdio_stop_readwait_disable(void); -/* set the read wait type(SD I/O only) */ -void sdio_readwait_type_set(uint32_t readwait_type); -/* enable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_enable(void); -/* disable the SD I/O mode specific operation(SD I/O only) */ -void sdio_operation_disable(void); -/* enable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_enable(void); -/* disable the SD I/O suspend operation(SD I/O only) */ -void sdio_suspend_disable(void); - -/* CE-ATA functions */ -/* enable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_enable(void); -/* disable the CE-ATA command(CE-ATA only) */ -void sdio_ceata_command_disable(void); -/* enable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_enable(void); -/* disable the CE-ATA interrupt(CE-ATA only) */ -void sdio_ceata_interrupt_disable(void); -/* enable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_enable(void); -/* disable the CE-ATA command completion signal(CE-ATA only) */ -void sdio_ceata_command_completion_disable(void); - -#endif /* GD32F4XX_SDIO_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h deleted file mode 100644 index 61bf8b1af2..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_spi.h +++ /dev/null @@ -1,379 +0,0 @@ -/*! - \file gd32f4xx_spi.h - \brief definitions for the SPI - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#ifndef GD32F4XX_SPI_H -#define GD32F4XX_SPI_H - -#include "gd32f4xx.h" - -/* SPIx(x=0,1,2,3,4,5) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE -#define SPI2 (SPI_BASE + 0x00000400U) -#define SPI3 (SPI_BASE + 0x0000FC00U) -#define SPI4 (SPI_BASE + 0x00011800U) -#define SPI5 (SPI_BASE + 0x00011C00U) - -/* I2Sx_ADD(x=1,2) definitions */ -#define I2S1_ADD I2S_ADD_BASE -#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U) - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */ - -/* I2S_ADD registers definitions */ -#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */ -#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/ -#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */ -#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */ -#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */ -#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */ -#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */ -#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */ -#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< lsb first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< nss pin selection in nss software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< nss software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */ -#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error bit */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2S_PSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* SPI_SPI_QCTL(only SPI5) */ -#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ -#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ -#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct -{ - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI nss control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI frame size */ -#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ -#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock polarity and phase */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ - -/* function declarations */ -/* initialization functions */ -/* deinitialize SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); -/* initialize SPI parameter */ -void spi_init(uint32_t spi_periph,spi_parameter_struct* spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl); -/* configure I2S prescale */ -void i2s_psc_config(uint32_t spi_periph,uint32_t i2s_audiosample,uint32_t i2s_frameformat,uint32_t i2s_mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* NSS functions */ -/* enable SPI nss output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI nss output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI nss pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI nss pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* SPI DMA functions */ -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph,uint8_t spi_dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph,uint8_t spi_dma); - -/* SPI/I2S transfer configure functions */ -/* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph,uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph,uint32_t transfer_direction); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc); - -/* SPI TI mode functions */ -/* enable SPI TI mode */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* disable SPI TI mode */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* configure i2s full duplex mode */ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat); - -/* quad wire SPI functions */ -/* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); -/* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); -/* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); -/* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); - -/* flag & interrupt functions */ -/* enable SPI interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* disable SPI interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int); -/* get SPI and I2S interrupt status*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -#endif /* GD32F4XX_SPI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h deleted file mode 100644 index 047910478a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_syscfg.h +++ /dev/null @@ -1,181 +0,0 @@ -/*! - \file gd32f4xx_syscfg.h - \brief definitions for the SYSCFG - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_SYSCFG_H -#define GD32F4XX_SYSCFG_H - -#include "gd32f4xx.h" - -/* SYSCFG definitions */ -#define SYSCFG SYSCFG_BASE - -/* registers definitions */ -#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */ -#define SYSCFG_CFG1 REG32(SYSCFG + 0x04U) /*!< system configuration register 1 */ -#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */ -#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */ -#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */ -#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */ -#define SYSCFG_CPSCTL REG32(SYSCFG + 0x20U) /*!< system I/O compensation control register */ - -/* SYSCFG_CFG0 bits definitions */ -#define SYSCFG_CFG0_BOOT_MODE BITS(0,2) /*!< SYSCFG memory remap config */ -#define SYSCFG_CFG0_FMC_SWP BIT(8) /*!< FMC memory swap config */ -#define SYSCFG_CFG0_EXMC_SWP BITS(10,11) /*!< EXMC memory swap config */ - -/* SYSCFG_CFG1 bits definitions */ -#define SYSCFG_CFG1_ENET_PHY_SEL BIT(23) /*!< Ethernet PHY selection config */ - -/* SYSCFG_EXTISS0 bits definitions */ -#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ - -/* SYSCFG_EXTISS1 bits definitions */ -#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ - -/* SYSCFG_EXTISS2 bits definitions */ -#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ - -/* SYSCFG_EXTISS3 bits definitions */ -#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ - -/* SYSCFG_CPSCTL bits definitions */ -#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ -#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ - -/* constants definitions */ -/* boot mode definitions */ -#define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< main flash memory remap */ -#define SYSCFG_BOOTMODE_BOOTLOADER ((uint8_t)0x01U) /*!< boot loader remap */ -#define SYSCFG_BOOTMODE_EXMC_SRAM ((uint8_t)0x02U) /*!< SRAM/NOR 0 and 1 of EXMC remap */ -#define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< SRAM0 of on-chip SRAM remap */ -#define SYSCFG_BOOTMODE_EXMC_SDRAM ((uint8_t)0x04U) /*!< SDRAM bank0 of EXMC remap */ - -/* FMC swap definitions */ -#define SYSCFG_FMC_SWP_BANK0 ((uint32_t)0x00000000U) /*!< main flash Bank 0 is mapped at address 0x08000000 */ -#define SYSCFG_FMC_SWP_BANK1 ((uint32_t)0x00000100U) /*!< main flash Bank 1 is mapped at address 0x08000000 */ - -/* EXMC swap enable/disable */ -#define SYSCFG_EXMC_SWP_ENABLE ((uint32_t)0x00000400U) /*!< SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card */ -#define SYSCFG_EXMC_SWP_DISABLE ((uint32_t)0x00000000U) /*!< no memory mapping swap */ - -/* EXTI source select definition */ -#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select GPIOx pin 0~3 */ -#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select GPIOx pin 4~7 */ -#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select GPIOx pin 8~11 */ -#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select GPIOx pin 12~15 */ - -/* EXTI source select mask bits definition */ -#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ - -/* EXTI source select jumping step definition */ -#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ - -/* EXTI source select moving step definition */ -#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ - -/* EXTI source port definitions */ -#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ -#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ -#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ -#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */ -#define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */ -#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ -#define EXTI_SOURCE_GPIOG ((uint8_t)0x06U) /*!< EXTI GPIOG configuration */ -#define EXTI_SOURCE_GPIOH ((uint8_t)0x07U) /*!< EXTI GPIOH configuration */ -#define EXTI_SOURCE_GPIOI ((uint8_t)0x08U) /*!< EXTI GPIOI configuration */ - -/* EXTI source pin definitions */ -#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ -#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ -#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ -#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ -#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ -#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ -#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ -#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ -#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ -#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ -#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ -#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ -#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ -#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ -#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ -#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ - -/* ethernet PHY selection */ -#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< MII is selected for the Ethernet MAC */ -#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) /*!< RMII is selected for the Ethernet MAC */ - -/* I/O compensation cell enable/disable */ -#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) /*!< I/O compensation cell enable */ -#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell disable */ - -/* function declarations */ -/* initialization functions */ -/* deinit syscfg module */ -void syscfg_deinit(void); - -/* function configuration */ -/* configure the boot mode */ -void syscfg_bootmode_config(uint8_t syscfg_bootmode); -/* configure FMC memory mapping swap */ -void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap); -/* configure the EXMC swap */ -void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap); -/* configure the GPIO pin as EXTI Line */ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); -/* configure the PHY interface for the ethernet MAC */ -void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface); -/* configure the I/O compensation cell */ -void syscfg_compensation_config(uint32_t syscfg_compensation); - -/* interrupt & flag functions */ -/* check the I/O compensation cell is ready or not */ -FlagStatus syscfg_flag_get(void); - -#endif /* GD32F4XX_SYSCFG_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h deleted file mode 100644 index 9da6e12bdd..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_timer.h +++ /dev/null @@ -1,781 +0,0 @@ -/*! - \file gd32f4xx_timer.h - \brief definitions for the TIMER - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_TIMER_H -#define GD32F4XX_TIMER_H - -#include "gd32f4xx.h" - -/* TIMERx(x=0..13) definitions */ -#define TIMER0 (TIMER_BASE + 0x00010000U) -#define TIMER1 (TIMER_BASE + 0x00000000U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER3 (TIMER_BASE + 0x00000800U) -#define TIMER4 (TIMER_BASE + 0x00000C00U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER6 (TIMER_BASE + 0x00001400U) -#define TIMER7 (TIMER_BASE + 0x00010400U) -#define TIMER8 (TIMER_BASE + 0x00014000U) -#define TIMER9 (TIMER_BASE + 0x00014400U) -#define TIMER10 (TIMER_BASE + 0x00014800U) -#define TIMER11 (TIMER_BASE + 0x00001800U) -#define TIMER12 (TIMER_BASE + 0x00001C00U) -#define TIMER13 (TIMER_BASE + 0x00002000U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ -#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ -#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ -#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ -#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ -#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ -#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ -#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ -#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* TIMER_IRMP */ -#define TIMER1_IRMP_ITI1_RMP BITS(10,11) /*!< TIMER1 internal trigger input 1 remap */ -#define TIMER4_IRMP_CI3_RMP BITS(6,7) /*!< TIMER4 channel 3 input remap */ -#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */ - -/* TIMER_CFG */ -#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ -#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ - -/* constants definitions */ -/* TIMER init parameter struct definitions*/ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint16_t clockdivision; /*!< clock division value */ - uint32_t period; /*!< period value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions*/ -typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint16_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint16_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ -#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ -#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ -#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ -#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ -#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ -#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF - - - -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ - -/* channel enable state*/ -#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ - -/* channel complementary output enable state*/ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ - -/* TIMER input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ - -/* timer1 internal trigger input1 remap */ -#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U)) -#define TIMER1_ITI1_RMP_TIMER7_TRGO TIMER1_IRMP(0) /*!< timer1 internal trigger input 1 remap to TIMER7_TRGO */ -#define TIMER1_ITI1_RMP_ETHERNET_PTP TIMER1_IRMP(1) /*!< timer1 internal trigger input 1 remap to ethernet PTP */ -#define TIMER1_ITI1_RMP_USB_FS_SOF TIMER1_IRMP(2) /*!< timer1 internal trigger input 1 remap to USB FS SOF */ -#define TIMER1_ITI1_RMP_USB_HS_SOF TIMER1_IRMP(3) /*!< timer1 internal trigger input 1 remap to USB HS SOF */ - -/* timer4 channel 3 input remap */ -#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) -#define TIMER4_CI3_RMP_GPIO TIMER4_IRMP(0) /*!< timer4 channel 3 input remap to GPIO pin */ -#define TIMER4_CI3_RMP_IRC32K TIMER4_IRMP(1) /*!< timer4 channel 3 input remap to IRC32K */ -#define TIMER4_CI3_RMP_LXTAL TIMER4_IRMP(2) /*!< timer4 channel 3 input remap to LXTAL */ -#define TIMER4_CI3_RMP_RTC_WAKEUP_INT TIMER4_IRMP(3) /*!< timer4 channel 3 input remap to RTC wakeup interrupt */ - -/* timer10 internal trigger input1 remap */ -#define TIMER10_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) -#define TIMER10_ITI1_RMP_GPIO TIMER10_IRMP(0) /*!< timer10 internal trigger input1 remap based on GPIO setting */ -#define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */ - -/* timerx(x=0,1,2,13,14,15,16) write cc register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ - -/* the output value selection */ -#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ - -/* function declarations */ -/* TIMER timebase*/ -/* deinit a TIMER */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct* initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a TIMER */ -void timer_enable(uint32_t timer_periph); -/* disable a TIMER */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph , uint32_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint32_t update); - -/* TIMER interrupt and flag*/ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -/* timer DMA and event*/ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); - -/* TIMER master and slave */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); -/* configure TIMER channel remap function */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); - -/* TIMER configure */ -/* configure TIMER write CHxVAL register selection */ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); -/* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); - -#endif /* GD32F4XX_TIMER_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h deleted file mode 100644 index 8b1232fa17..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_tli.h +++ /dev/null @@ -1,376 +0,0 @@ -/*! - \file gd32f4xx_tli.h - \brief definitions for the TLI - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_TLI_H -#define GD32F4XX_TLI_H - -#include "gd32f4xx.h" - -/* TLI definitions */ -#define TLI TLI_BASE /*!< TLI base address */ -/* TLI layer definitions */ -#define LAYER0 TLI_BASE /*!< TLI layer0 base address */ -#define LAYER1 (TLI_BASE+0x80) /*!< TLI layer1 base address */ - -/* registers definitions */ -#define TLI_SPSZ REG32(TLI + 0x08U) /*!< TLI synchronous pulse size register */ -#define TLI_BPSZ REG32(TLI + 0x0CU) /*!< TLI back-porch size register */ -#define TLI_ASZ REG32(TLI + 0x10U) /*!< TLI active size register */ -#define TLI_TSZ REG32(TLI + 0x14U) /*!< TLI total size register */ -#define TLI_CTL REG32(TLI + 0x18U) /*!< TLI control register */ -#define TLI_RL REG32(TLI + 0x24U) /*!< TLI reload Layer register */ -#define TLI_BGC REG32(TLI + 0x2CU) /*!< TLI background color register */ -#define TLI_INTEN REG32(TLI + 0x34U) /*!< TLI interrupt enable register */ -#define TLI_INTF REG32(TLI + 0x38U) /*!< TLI interrupt flag register */ -#define TLI_INTC REG32(TLI + 0x3CU) /*!< TLI interrupt flag clear register */ -#define TLI_LM REG32(TLI + 0x40U) /*!< TLI line mark register */ -#define TLI_CPPOS REG32(TLI + 0x44U) /*!< TLI current pixel position register */ -#define TLI_STAT REG32(TLI + 0x48U) /*!< TLI status register */ -#define TLI_LxCTL(layerx) REG32((layerx) + 0x84U) /*!< TLI layer x control register */ -#define TLI_LxHPOS(layerx) REG32((layerx) + 0x88U) /*!< TLI layer x horizontal position parameters register */ -#define TLI_LxVPOS(layerx) REG32((layerx) + 0x8CU) /*!< TLI layer x vertical position parameters register */ -#define TLI_LxCKEY(layerx) REG32((layerx) + 0x90U) /*!< TLI layer x color key register */ -#define TLI_LxPPF(layerx) REG32((layerx) + 0x94U) /*!< TLI layer x packeted pixel format register */ -#define TLI_LxSA(layerx) REG32((layerx) + 0x98U) /*!< TLI layer x specified alpha register */ -#define TLI_LxDC(layerx) REG32((layerx) + 0x9CU) /*!< TLI layer x default color register */ -#define TLI_LxBLEND(layerx) REG32((layerx) + 0xA0U) /*!< TLI layer x blending register */ -#define TLI_LxFBADDR(layerx) REG32((layerx) + 0xACU) /*!< TLI layer x frame base address register */ -#define TLI_LxFLLEN(layerx) REG32((layerx) + 0xB0U) /*!< TLI layer x frame line length register */ -#define TLI_LxFTLN(layerx) REG32((layerx) + 0xB4U) /*!< TLI layer x frame total line number register */ -#define TLI_LxLUT(layerx) REG32((layerx) + 0xC4U) /*!< TLI layer x look up table register */ - -/* bits definitions */ -/* TLI_SPSZ */ -#define TLI_SPSZ_VPSZ BITS(0,11) /*!< size of the vertical synchronous pulse */ -#define TLI_SPSZ_HPSZ BITS(16,27) /*!< size of the horizontal synchronous pulse */ - -/* TLI_BPSZ */ -#define TLI_BPSZ_VBPSZ BITS(0,11) /*!< size of the vertical back porch plus synchronous pulse */ -#define TLI_BPSZ_HBPSZ BITS(16,27) /*!< size of the horizontal back porch plus synchronous pulse */ - -/* TLI_ASZ */ -#define TLI_ASZ_VASZ BITS(0,11) /*!< size of the vertical active area width plus back porch and synchronous pulse */ -#define TLI_ASZ_HASZ BITS(16,27) /*!< size of the horizontal active area width plus back porch and synchronous pulse */ - -/* TLI_SPSZ */ -#define TLI_TSZ_VTSZ BITS(0,11) /*!< vertical total size of the display, including active area, back porch, synchronous pulse and front porch */ -#define TLI_TSZ_HTSZ BITS(16,27) /*!< horizontal total size of the display, including active area, back porch, synchronous pulse and front porch */ - -/* TLI_CTL */ -#define TLI_CTL_TLIEN BIT(0) /*!< TLI enable bit */ -#define TLI_CTL_BDB BITS(4,6) /*!< blue channel dither bits number */ -#define TLI_CTL_GDB BITS(8,10) /*!< green channel dither bits number */ -#define TLI_CTL_RDB BITS(12,14) /*!< red channel dither bits number */ -#define TLI_CTL_DFEN BIT(16) /*!< dither function enable */ -#define TLI_CTL_CLKPS BIT(28) /*!< pixel clock polarity selection */ -#define TLI_CTL_DEPS BIT(29) /*!< data enable polarity selection */ -#define TLI_CTL_VPPS BIT(30) /*!< vertical pulse polarity selection */ -#define TLI_CTL_HPPS BIT(31) /*!< horizontal pulse polarity selection */ - -/* TLI_RL */ -#define TLI_RL_RQR BIT(0) /*!< request reload */ -#define TLI_RL_FBR BIT(1) /*!< frame blank reload */ - -/* TLI_BGC */ -#define TLI_BGC_BVB BITS(0,7) /*!< background value blue */ -#define TLI_BGC_BVG BITS(8,15) /*!< background value green */ -#define TLI_BGC_BVR BITS(16,23) /*!< background value red */ - -/* TLI_INTEN */ -#define TLI_INTEN_LMIE BIT(0) /*!< line mark interrupt enable */ -#define TLI_INTEN_FEIE BIT(1) /*!< FIFO error interrupt enable */ -#define TLI_INTEN_TEIE BIT(2) /*!< transaction error interrupt enable */ -#define TLI_INTEN_LCRIE BIT(3) /*!< layer configuration reloaded interrupt enable */ - -/* TLI_INTF */ -#define TLI_INTF_LMF BIT(0) /*!< line mark flag */ -#define TLI_INTF_FEF BIT(1) /*!< FIFO error flag */ -#define TLI_INTF_TEF BIT(2) /*!< transaction error flag */ -#define TLI_INTF_LCRF BIT(3) /*!< layer configuration reloaded flag */ - -/* TLI_INTC */ -#define TLI_INTC_LMC BIT(0) /*!< line mark flag clear */ -#define TLI_INTC_FEC BIT(1) /*!< FIFO error flag clear */ -#define TLI_INTC_TEC BIT(2) /*!< transaction error flag clear */ -#define TLI_INTC_LCRC BIT(3) /*!< layer configuration reloaded flag clear */ - -/* TLI_LM */ -#define TLI_LM_LM BITS(0,10) /*!< line mark value */ - -/* TLI_CPPOS */ -#define TLI_CPPOS_VPOS BITS(0,15) /*!< vertical position */ -#define TLI_CPPOS_HPOS BITS(16,31) /*!< horizontal position */ - -/* TLI_STAT */ -#define TLI_STAT_VDE BIT(0) /*!< current VDE status */ -#define TLI_STAT_HDE BIT(1) /*!< current HDE status */ -#define TLI_STAT_VS BIT(2) /*!< current VS status of the TLI */ -#define TLI_STAT_HS BIT(3) /*!< current HS status of the TLI */ - -/* TLI_LxCTL */ -#define TLI_LxCTL_LEN BIT(0) /*!< layer enable */ -#define TLI_LxCTL_CKEYEN BIT(1) /*!< color keying enable */ -#define TLI_LxCTL_LUTEN BIT(4) /*!< LUT enable */ - -/* TLI_LxHPOS */ -#define TLI_LxHPOS_WLP BITS(0,11) /*!< window left position */ -#define TLI_LxHPOS_WRP BITS(16,27) /*!< window right position */ - -/* TLI_LxVPOS */ -#define TLI_LxVPOS_WTP BITS(0,11) /*!< window top position */ -#define TLI_LxVPOS_WBP BITS(16,27) /*!< window bottom position */ - -/* TLI_LxCKEY */ -#define TLI_LxCKEY_CKEYB BITS(0,7) /*!< color key blue */ -#define TLI_LxCKEY_CKEYG BITS(8,15) /*!< color key green */ -#define TLI_LxCKEY_CKEYR BITS(16,23) /*!< color key red */ - -/* TLI_LxPPF */ -#define TLI_LxPPF_PPF BITS(0,2) /*!< packeted pixel format */ - -/* TLI_LxSA */ -#define TLI_LxSA_SA BITS(0,7) /*!< specified alpha */ - -/* TLI_LxDC */ -#define TLI_LxDC_DCB BITS(0,7) /*!< the default color blue */ -#define TLI_LxDC_DCG BITS(8,15) /*!< the default color green */ -#define TLI_LxDC_DCR BITS(16,23) /*!< the default color red */ -#define TLI_LxDC_DCA BITS(24,31) /*!< the default color alpha */ - -/* TLI_LxBLEND */ -#define TLI_LxBLEND_ACF2 BITS(0,2) /*!< alpha calculation factor 2 of blending method */ -#define TLI_LxBLEND_ACF1 BITS(8,10) /*!< alpha calculation factor 1 of blending method */ - -/* TLI_LxFBADDR */ -#define TLI_LxFBADDR_FBADD BITS(0,31) /*!< frame buffer base address */ - -/* TLI_LxFLLEN */ -#define TLI_LxFLLEN_FLL BITS(0,13) /*!< frame line length */ -#define TLI_LxFLLEN_STDOFF BITS(16,29) /*!< frame buffer stride offset */ - -/* TLI_LxFTLN */ -#define TLI_LxFTLN_FTLN BITS(0,10) /*!< frame total line number */ - -/* TLI_LxLUT */ -#define TLI_LxLUT_TB BITS(0,7) /*!< blue channel of a LUT entry */ -#define TLI_LxLUT_TG BITS(8,15) /*!< green channel of a LUT entry */ -#define TLI_LxLUT_TR BITS(16,23) /*!< red channel of a LUT entry */ -#define TLI_LxLUT_TADD BITS(24,31) /*!< look up table write address */ - -/* constants definitions */ -/* TLI parameter struct definitions */ -typedef struct -{ - uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */ - uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */ - uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */ - uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */ - uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */ - uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */ - uint32_t totalsz_vtsz; /*!< vertical total size of the display */ - uint32_t totalsz_htsz; /*!< horizontal total size of the display */ - uint32_t backcolor_red; /*!< background value red */ - uint32_t backcolor_green; /*!< background value green */ - uint32_t backcolor_blue; /*!< background value blue */ - uint32_t signalpolarity_hs; /*!< horizontal pulse polarity selection */ - uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */ - uint32_t signalpolarity_de; /*!< data enable polarity selection */ - uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */ -}tli_parameter_struct; - -/* TLI layer parameter struct definitions */ -typedef struct -{ - uint16_t layer_window_rightpos; /*!< window right position */ - uint16_t layer_window_leftpos; /*!< window left position */ - uint16_t layer_window_bottompos; /*!< window bottom position */ - uint16_t layer_window_toppos; /*!< window top position */ - uint32_t layer_ppf; /*!< packeted pixel format */ - uint8_t layer_sa; /*!< specified alpha */ - uint8_t layer_default_alpha; /*!< the default color alpha */ - uint8_t layer_default_red; /*!< the default color red */ - uint8_t layer_default_green; /*!< the default color green */ - uint8_t layer_default_blue; /*!< the default color blue */ - uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */ - uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */ - uint32_t layer_frame_bufaddr; /*!< frame buffer base address */ - uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */ - uint16_t layer_frame_line_length; /*!< frame line length */ - uint16_t layer_frame_total_line_number; /*!< frame total line number */ -}tli_layer_parameter_struct; - -/* TLI layer LUT parameter struct definitions */ -typedef struct -{ - uint32_t layer_table_addr; /*!< look up table write address */ - uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */ - uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */ - uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */ -}tli_layer_lut_parameter_struct; - -/* packeted pixel format */ -typedef enum -{ - LAYER_PPF_ARGB8888, /*!< layerx pixel format ARGB8888 */ - LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */ - LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */ - LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */ - LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */ - LAYER_PPF_L8, /*!< layerx pixel format L8 */ - LAYER_PPF_AL44, /*!< layerx pixel format AL44 */ - LAYER_PPF_AL88 /*!< layerx pixel format AL88 */ -}tli_layer_ppf_enum; - -/* TLI flags */ -#define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */ -#define TLI_FLAG_HDE TLI_STAT_HDE /*!< current HDE status */ -#define TLI_FLAG_VS TLI_STAT_VS /*!< current VS status of the TLI */ -#define TLI_FLAG_HS TLI_STAT_HS /*!< current HS status of the TLI */ -#define TLI_FLAG_LM BIT(0) | BIT(31) /*!< line mark interrupt flag */ -#define TLI_FLAG_FE BIT(1) | BIT(31) /*!< FIFO error interrupt flag */ -#define TLI_FLAG_TE BIT(2) | BIT(31) /*!< transaction error interrupt flag */ -#define TLI_FLAG_LCR BIT(3) | BIT(31) /*!< layer configuration reloaded interrupt flag */ - -/* TLI interrupt enable or disable */ -#define TLI_INT_LM BIT(0) /*!< line mark interrupt */ -#define TLI_INT_FE BIT(1) /*!< FIFO error interrupt */ -#define TLI_INT_TE BIT(2) /*!< transaction error interrupt */ -#define TLI_INT_LCR BIT(3) /*!< layer configuration reloaded interrupt */ - -/* TLI interrupt flag */ -#define TLI_INT_FLAG_LM BIT(0) /*!< line mark interrupt flag */ -#define TLI_INT_FLAG_FE BIT(1) /*!< FIFO error interrupt flag */ -#define TLI_INT_FLAG_TE BIT(2) /*!< transaction error interrupt flag */ -#define TLI_INT_FLAG_LCR BIT(3) /*!< layer configuration reloaded interrupt flag */ - -/* layer reload configure */ -#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */ -#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */ - -/* dither function */ -#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */ -#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */ - -/* horizontal pulse polarity selection */ -#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */ -#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */ - -/* vertical pulse polarity selection */ -#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */ -#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */ - -/* pixel clock polarity selection */ -#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */ -#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */ - -/* data enable polarity selection */ -#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */ -#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */ - -/* alpha calculation factor 1 of blending method */ -#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8)) -#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */ -#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */ - -/* alpha calculation factor 2 of blending method */ -#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval))) -#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */ -#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */ - -/* function declarations */ -/* initialization functions, TLI enable or disable, TLI reload mode configuration */ -/* deinitialize TLI registers */ -void tli_deinit(void); -/* initialize the parameters of TLI parameter structure with the default values, it is suggested - that call this function after a tli_parameter_struct structure is defined */ -void tli_struct_para_init(tli_parameter_struct *tli_struct); -/* initialize TLI */ -void tli_init(tli_parameter_struct *tli_struct); -/* configure TLI dither function */ -void tli_dither_config(uint8_t dither_stat); -/* enable TLI */ -void tli_enable(void); -/* disable TLI */ -void tli_disable(void); -/* configurate TLI reload mode */ -void tli_reload_config(uint8_t reload_mod); - -/* TLI layer configuration functions */ -/* initialize the parameters of TLI layer structure with the default values, it is suggested - that call this function after a tli_layer_parameter_struct structure is defined */ -void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct); -/* initialize TLI layer */ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct); -/* reconfigure window position */ -void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y); -/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested - that call this function after a tli_layer_lut_parameter_struct structure is defined */ -void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct); -/* initialize TLI layer LUT */ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct); -/* initialize TLI layer color key */ -void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey); -/* enable TLI layer */ -void tli_layer_enable(uint32_t layerx); -/* disable TLI layer */ -void tli_layer_disable(uint32_t layerx); -/* enable TLI layer color keying */ -void tli_color_key_enable(uint32_t layerx); -/* disable TLI layer color keying */ -void tli_color_key_disable(uint32_t layerx); -/* enable TLI layer LUT */ -void tli_lut_enable(uint32_t layerx); -/* disable TLI layer LUT */ -void tli_lut_disable(uint32_t layerx); - -/* set line mark value */ -void tli_line_mark_set(uint16_t line_num); -/* get current displayed position */ -uint32_t tli_current_pos_get(void); - -/* flag and interrupt functions */ -/* enable TLI interrupt */ -void tli_interrupt_enable(uint32_t int_flag); -/* disable TLI interrupt */ -void tli_interrupt_disable(uint32_t int_flag); -/* get TLI interrupt flag */ -FlagStatus tli_interrupt_flag_get(uint32_t int_flag); -/* clear TLI interrupt flag */ -void tli_interrupt_flag_clear(uint32_t int_flag); -/* get TLI flag or state in TLI_INTF register or TLI_STAT register */ -FlagStatus tli_flag_get(uint32_t flag); - -#endif /* GD32F4XX_TLI_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h deleted file mode 100644 index f321b15d28..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_trng.h +++ /dev/null @@ -1,104 +0,0 @@ -/*! - \file gd32f4xx_trng.h - \brief definitions for the TRNG - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_TRNG_H -#define GD32F4XX_TRNG_H - -#include "gd32f4xx.h" - -/* TRNG definitions */ -#define TRNG TRNG_BASE - -/* registers definitions */ -#define TRNG_CTL REG32(TRNG + 0x00U) /*!< control register */ -#define TRNG_STAT REG32(TRNG + 0x04U) /*!< status register */ -#define TRNG_DATA REG32(TRNG + 0x08U) /*!< data register */ - -/* bits definitions */ -/* TRNG_CTL */ -#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */ -#define TRNG_CTL_IE BIT(3) /*!< interrupt enable bit */ - -/* TRNG_STAT */ -#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */ -#define TRNG_STAT_CECS BIT(1) /*!< clock error current status */ -#define TRNG_STAT_SECS BIT(2) /*!< seed error current status */ -#define TRNG_STAT_CEIF BIT(5) /*!< clock error interrupt flag */ -#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */ - -/* TRNG_DATA */ -#define TRNG_DATA_TRNDATA BITS(0,31) /*!< 32-Bit Random data */ - -/* constants definitions */ -/* trng status flag */ -typedef enum -{ - TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */ - TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */ - TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */ -}trng_flag_enum; - -/* trng inerrupt flag */ -typedef enum -{ - TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */ - TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */ -}trng_int_flag_enum; - -/* function declarations */ -/* initialization functions */ -/* deinitialize the TRNG */ -void trng_deinit(void); -/* enable the TRNG interface */ -void trng_enable(void); -/* disable the TRNG interface */ -void trng_disable(void); -/* get the true random data */ -uint32_t trng_get_true_random_data(void); - -/* flag & interrupt functions */ -/* trng interrupt enable */ -void trng_interrupt_enable(void); -/* trng interrupt disable */ -void trng_interrupt_disable(void); -/* get the trng status flags */ -FlagStatus trng_flag_get(trng_flag_enum flag); -/* get the trng interrupt flags */ -FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag); -/* clear the trng interrupt flags */ -void trng_interrupt_flag_clear(trng_int_flag_enum int_flag); - -#endif /* GD32F4XX_TRNG_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h deleted file mode 100644 index 3cd49d827f..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_usart.h +++ /dev/null @@ -1,495 +0,0 @@ -/*! - \file gd32f4xx_usart.h - \brief definitions for the USART - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_USART_H -#define GD32F4XX_USART_H - -#include "gd32f4xx.h" - -/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */ -#define USART1 USART_BASE /*!< USART1 base address */ -#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ -#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ -#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ -#define UART6 (USART_BASE+0x00003400U) /*!< UART6 base address */ -#define UART7 (USART_BASE+0x00003800U) /*!< UART7 base address */ -#define USART0 (USART_BASE+0x0000CC00U) /*!< USART0 base address */ -#define USART5 (USART_BASE+0x0000D000U) /*!< USART5 base address */ - -/* registers definitions */ -#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ -#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ -#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ -#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ -#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ -#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ -#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ -#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ -#define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */ - -/* bits definitions */ -/* USARTx_STAT0 */ -#define USART_STAT0_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT0_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT0_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT0_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT0_TC BIT(6) /*!< transmission complete */ -#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ - -/* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ - -/* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ -#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ -#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* USARTx_CTL3 */ -#define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ -#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ -#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ -#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ -#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ -#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ -#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ -#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ - -/* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ - -/* USARTx_STAT1 */ -#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT1_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT1_BSY BIT(16) /*!< busy flag */ - -/* USARTx_CHC */ -#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ -#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */ -#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */ -#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ - -/* constants definitions */ -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ -#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ -#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ -#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ -#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ - -/* USART flags */ -typedef enum -{ - /* flags in STAT0 register */ - USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ - /* flags in STAT1 register */ - USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ - /* flags in CHC register */ - USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ - /* interrupt flags in CTL3 register */ - USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ - USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ - /* interrupt in CTL3 register */ - USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */ - USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */ -}usart_interrupt_enum; - -/* USART invert configure */ -typedef enum -{ - /* data bit level inversion */ - USART_DINV_ENABLE, /*!< data bit level inversion */ - USART_DINV_DISABLE, /*!< data bit level not inversion */ - /* TX pin level inversion */ - USART_TXPIN_ENABLE, /*!< TX pin level inversion */ - USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ - /* RX pin level inversion */ - USART_RXPIN_ENABLE, /*!< RX pin level inversion */ - USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ -}usart_invert_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address mask */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART oversampling mode definitions */ -#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */ -#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ - -/* USART CK length */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART DMA request for receive configure */ -#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ - -/* USART DMA request for transmission configure */ -#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ - -/* USART RTS configure */ -#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ - -/* USART CTS configure */ -#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ - -/* USART one sample bit method configure */ -#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */ -#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* USART data is transmitted/received with the LSB/MSB first */ -#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ -#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ - -/* break frame coherence mode */ -#define CHC_BCM(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_BCM_NONE CHC_BCM(0) /*!< no parity error is detected */ -#define USART_BCM_EN CHC_BCM(1) /*!< parity error is detected */ - -/* USART parity check coherence mode */ -#define CHC_PCM(regval) (BIT(1) & ((uint32_t)(regval) << 1)) -#define USART_PCM_NONE CHC_PCM(0) /*!< not check parity */ -#define USART_PCM_EN CHC_PCM(1) /*!< check the parity */ - -/* USART hardware flow control coherence mode */ -#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) -#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ -#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure usart baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure usart parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure usart word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure usart stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); -/* enable usart */ -void usart_enable(uint32_t usart_periph); -/* disable usart */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); - -/* USART normal mode communication */ -/* data is transmitted/received with the LSB/MSB first */ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); -/* configure USART inverted */ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); -/* configure the USART oversample mode */ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); -/* configure sample bit method */ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm); -/* enable receiver timeout */ -void usart_receiver_timeout_enable(uint32_t usart_periph); -/* disable receiver timeout */ -void usart_receiver_timeout_disable(uint32_t usart_periph); -/* configure receiver timeout threshold */ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod); - -/* LIN mode communication */ -/* enable LIN mode */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* disable LIN mode */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); -/* send break frame */ -void usart_send_break(uint32_t usart_periph); - -/* half-duplex communication */ -/* enable half-duplex mode */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* disable half-duplex mode */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* enable CK pin in synchronous mode */ -void usart_synchronous_clock_enable(uint32_t usart_periph); -/* disable CK pin in synchronous mode */ -void usart_synchronous_clock_disable(uint32_t usart_periph); -/* configure usart synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); -/* enable smartcard mode */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* disable smartcard mode */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* enable NACK in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* disable NACK in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* coherence control */ -/* configure break frame coherence mode */ -void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm); -/* configure parity check coherence mode */ -void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm); -/* configure hardware flow control coherence mode */ -void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); - -/* DMA communication */ -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); - -/* flag & interrupt functions */ -/* get flag in STAT0/STAT1 register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT0/STAT1 register */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -/* clear interrupt flag in STAT0/STAT1 register */ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); - -#endif /* GD32F4XX_USART_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h deleted file mode 100644 index 525b9a6e5a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Include/gd32f4xx_wwdgt.h +++ /dev/null @@ -1,88 +0,0 @@ -/*! - \file gd32f4xx_wwdgt.h - \brief definitions for the WWDGT - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32F4XX_WWDGT_H -#define GD32F4XX_WWDGT_H - -#include "gd32f4xx.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32F4XX_WWDGT_H */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c deleted file mode 100644 index f249e6c840..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c +++ /dev/null @@ -1,1202 +0,0 @@ -/*! - \file gd32f4xx_adc.c - \brief ADC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_adc.h" - -#define REGULAR_TRIGGER_MODE ((uint32_t)28U) -#define INSERTED_TRIGGER_MODE ((uint32_t)20U) -/* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) - -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) - -/* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) - -/* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) - -/* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) - -/*! - \brief reset ADC - \param[in] none - \param[out] none - \retval none -*/ -void adc_deinit(void) -{ - rcu_periph_reset_enable(RCU_ADCRST); - rcu_periph_reset_disable(RCU_ADCRST); -} - -/*! - \brief configure the ADC clock for all the ADCs - \param[in] prescaler: configure ADCs prescaler ratio - only one parameter can be selected which is shown as below: - \arg ADC_ADCCK_PCLK2_DIV2: PCLK2 div2 - \arg ADC_ADCCK_PCLK2_DIV4: PCLK2 div4 - \arg ADC_ADCCK_PCLK2_DIV6: PCLK2 div6 - \arg ADC_ADCCK_PCLK2_DIV8: PCLK2 div8 - \arg ADC_ADCCK_HCLK_DIV5: HCLK div5 - \arg ADC_ADCCK_HCLK_DIV6: HCLK div6 - \arg ADC_ADCCK_HCLK_DIV10: HCLK div10 - \arg ADC_ADCCK_HCLK_DIV20: HCLK div20 - \param[out] none - \retval none -*/ -void adc_clock_config(uint32_t prescaler) -{ - ADC_SYNCCTL &= ~((uint32_t)ADC_SYNCCTL_ADCCK); - ADC_SYNCCTL |= (uint32_t) prescaler; -} - -/*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] function: the function to config - only one parameter can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (function & ADC_SCAN_MODE)){ - /* enable scan mode */ - ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* enable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* enable continuous mode */ - ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ - /* disable scan mode */ - ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* disable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* disable continuous mode */ - ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment){ - /* MSB alignment */ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ - /* LSB alignment */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief enable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_enable(uint32_t adc_periph) -{ - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ - /* enable ADC */ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_disable(uint32_t adc_periph) -{ - /* disable ADC */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_calibration_enable(uint32_t adc_periph) -{ - /* reset the selected ADC calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ - } -} - -/*! - \brief configure temperature sensor and internal reference voltage channel or VBAT channel function - \param[in] function: temperature sensor and internal reference voltage channel or VBAT channel - only one parameter can be selected which is shown as below: - \arg ADC_VBAT_CHANNEL_SWITCH: channel 18 (1/4 voltate of external battery) switch of ADC0 - \arg ADC_TEMP_VREF_CHANNEL_SWITCH: channel 16 (temperature sensor) and 17 (internal reference voltage) switch of ADC0 - \param[in] newvalue: ENABLE or DISABLE -\param[out] none - \retval none -*/ -void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue) -{ - if(newvalue){ - if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ - /* enable ADC0 Vbat channel */ - ADC_SYNCCTL |= ADC_VBAT_CHANNEL_SWITCH; - } - if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ - /* enable ADC0 Vref and Temperature channel */ - ADC_SYNCCTL |= ADC_TEMP_VREF_CHANNEL_SWITCH; - } - }else{ - if(RESET != (function & ADC_VBAT_CHANNEL_SWITCH)){ - /* disable ADC0 Vbat channel */ - ADC_SYNCCTL &= ~ADC_VBAT_CHANNEL_SWITCH; - } - if(RESET != (function & ADC_TEMP_VREF_CHANNEL_SWITCH)){ - /* disable ADC0 Vref and Temperature channel */ - ADC_SYNCCTL &= ~ADC_TEMP_VREF_CHANNEL_SWITCH; - } - } -} - -/*! - \brief configure ADC resolution - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DRES); - ADC_CTL0(adc_periph) |= (uint32_t)resolution; -} - -/*! - \brief configure ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio) -{ - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ - ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); - } - /* config the shift and ratio */ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief enable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN; -} - -/*! - \brief disable ADC oversample mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(uint32_t adc_periph) -{ - ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); -} - -/*! - \brief enable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - /* enable DMA request */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - /* disable DMA request */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief when DMA=1, the DMA engine issues a request at end of each regular conversion - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_request_after_last_enable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DDM); -} - -/*! - \brief the DMA engine is disabled after the end of transfer signal from DMA controller is detected - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_dma_request_after_last_disable(uint32_t adc_periph) -{ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DDM); -} - -/*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length) -{ - /* disable discontinuous mode of regular & inserted channel */ - ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* config the number of conversions in discontinuous mode */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - if((length <= 8U) && (length >= 1U)){ - ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - } - /* enable regular channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ - default: - break; - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - if((length >= 1U) && (length <= 16U)){ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - } - break; - case ADC_INSERTED_CHANNEL: - if((length >= 1U) && (length <= 4U)){ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - } - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the regular group sequencer rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ - /* the regular group sequence rank is smaller than six */ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); - ADC_RSQ2(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ - /* the regular group sequence rank is smaller than twelve */ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); - ADC_RSQ1(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ - /* the regular group sequence rank is smaller than sixteen */ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); - ADC_RSQ0(adc_periph) = rsq; - }else{ - } - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the regular group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the regular group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..18): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_3: 3 cycles - \arg ADC_SAMPLETIME_15: 15 cycles - \arg ADC_SAMPLETIME_28: 28 cycles - \arg ADC_SAMPLETIME_56: 56 cycles - \arg ADC_SAMPLETIME_84: 84 cycles - \arg ADC_SAMPLETIME_112: 112 cycles - \arg ADC_SAMPLETIME_144: 144 cycles - \arg ADC_SAMPLETIME_480: 480 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - - /* get inserted channel group length */ - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ - if(rank < 4U){ - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); - isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); - ADC_ISQ(adc_periph) = isq; - } - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the inserted group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel <= ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the inserted group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel - ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset : the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - - if(num <= ADC_OFFSET_LENGTH){ - /* calculate the offset of the register */ - num = num * ADC_OFFSET_SHIFT_LENGTH; - /* config the offset of the selected channels */ - REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief configure ADC external trigger source - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - for regular channel: - only one parameter can be selected which is shown as below: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: external trigger timer 0 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH1: external trigger timer 0 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T0_CH2: external trigger timer 0 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH1: external trigger timer 1 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH2: external trigger timer 1 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_CH3: external trigger timer 1 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T1_TRGO: external trigger timer 1 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_CH0 : external trigger timer 2 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T2_TRGO : external trigger timer 2 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T3_CH3: external trigger timer 3 CC3 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH0: external trigger timer 4 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH1: external trigger timer 4 CC1 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T4_CH2: external trigger timer 4 CC2 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_CH0: external trigger timer 7 CC0 event select for regular channel - \arg ADC_EXTTRIG_REGULAR_T7_TRGO: external trigger timer 7 TRGO event select for regular channel - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external trigger extiline 11 select for regular channel - for inserted channel: - only one parameter can be selected which is shown as below: - \arg ADC_EXTTRIG_INSERTED_T0_CH3: timer0 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: timer0 TRGO event - \arg ADC_EXTTRIG_INSERTED_T1_CH0: timer1 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T1_TRGO: timer1 TRGO event - \arg ADC_EXTTRIG_INSERTED_T2_CH1: timer2 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T2_CH3: timer2 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T3_CH0: timer3 capture compare 0 - \arg ADC_EXTTRIG_INSERTED_T3_CH1: timer3 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T3_CH2: timer3 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T3_TRGO: timer3 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T4_CH3: timer4 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_T4_TRGO: timer4 capture compare TRGO - \arg ADC_EXTTRIG_INSERTED_T7_CH1: timer7 capture compare 1 - \arg ADC_EXTTRIG_INSERTED_T7_CH2: timer7 capture compare 2 - \arg ADC_EXTTRIG_INSERTED_T7_CH3: timer7 capture compare 3 - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief enable ADC external trigger - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] trigger_mode: external trigger mode - only one parameter can be selected which is shown as below: - \arg EXTERNAL_TRIGGER_DISABLE: external trigger disable - \arg EXTERNAL_TRIGGER_RISING: rising edge of external trigger - \arg EXTERNAL_TRIGGER_FALLING: falling edge of external trigger - \arg EXTERNAL_TRIGGER_RISING_FALLING: rising and falling edge of external trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t trigger_mode) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular channel group external trigger mode */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMRC); - ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << REGULAR_TRIGGER_MODE); - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted channel group external trigger mode */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETMIC); - ADC_CTL1(adc_periph) |= (uint32_t) (trigger_mode << INSERTED_TRIGGER_MODE); - break; - default: - break; - } -} - -/*! - \brief enable ADC software trigger - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* enable ADC regular channel group software trigger */ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWRCST; - break; - case ADC_INSERTED_CHANNEL: - /* enable ADC inserted channel group software trigger */ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_SWICST; - break; - default: - break; - } -} - -/*! - \brief configure end of conversion mode - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] end_selection: end of conversion mode - only one parameter can be selected which is shown as below: - \arg ADC_EOC_SET_SEQUENCE: only at the end of a sequence of regular conversions, the EOC bit is set.Overflow detection is disabled unless DMA=1. - \arg ADC_EOC_SET_CONVERSION: at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically. - \param[out] none - \retval none -*/ -void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection) -{ - switch(end_selection){ - case ADC_EOC_SET_SEQUENCE: - /* only at the end of a sequence of regular conversions, the EOC bit is set */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_EOCM); - break; - case ADC_EOC_SET_CONVERSION: - /* at the end of each regular conversion, the EOC bit is set.Overflow is detected automatically */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_EOCM); - break; - default: - break; - } -} - -/*! - \brief read ADC regular group data register - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(uint32_t adc_periph) -{ - return (uint16_t)(ADC_RDATA(adc_periph)); -} - -/*! - \brief read ADC inserted group data register - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] inserted_channel : insert channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - /* read the data of channel 0 */ - idata = ADC_IDATA0(adc_periph); - break; - case ADC_INSERTED_CHANNEL_1: - /* read the data of channel 1 */ - idata = ADC_IDATA1(adc_periph); - break; - case ADC_INSERTED_CHANNEL_2: - /* read the data of channel 2 */ - idata = ADC_IDATA2(adc_periph); - break; - case ADC_INSERTED_CHANNEL_3: - /* read the data of channel 3 */ - idata = ADC_IDATA3(adc_periph); - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief disable ADC analog watchdog single channel - \param[in] adc_periph: ADCx,x=0,1,2 - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_disable(uint32_t adc_periph ) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDSC); -} - -/*! - \brief enable ADC analog watchdog single channel - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x: ADC Channelx(x=0..18) - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDCHSEL); - - /* analog watchdog channel select */ - ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDSC; -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint32_t adc_periph , uint8_t adc_channel_group) -{ - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC)); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - /* inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_channel_group) -{ - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* disable ADC analog watchdog regular channel group */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_RWDEN); - break; - case ADC_INSERTED_CHANNEL: - /* disable ADC analog watchdog inserted channel group */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_IWDEN); - break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* disable ADC analog watchdog regular and inserted channel group */ - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN)); - break; - default: - break; - } -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] low_threshold: analog watchdog low threshold,0..4095 - \param[in] high_threshold: analog watchdog high threshold,0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold) -{ - /* configure ADC analog watchdog low threshold */ - ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); - /* configure ADC analog watchdog high threshold */ - ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); -} - -/*! - \brief get the ADC flag bits - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) -{ - FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ - reval = SET; - } - return reval; - -} - -/*! - \brief clear the ADC flag bits - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \arg ADC_FLAG_ROVF: regular data register overflow flag - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); -} - -/*! - \brief get the bit state of ADCx software start conversion - \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the bit state of ADCx software inserted channel start conversion - \param[in] adc_periph: ADCx, x=0,1,2 only one among these parameters can be selected - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the ADC interrupt bits - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_interrupt: the adc interrupt bits - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch(adc_interrupt){ - case ADC_INT_FLAG_WDE: - /* get the ADC analog watchdog interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_ROVF: - /* get the ADC regular data register overflow interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_ROVF; - if((ADC_CTL0(adc_periph) & ADC_CTL0_ROVFIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear the ADC flag - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_interrupt: the adc status flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \arg ADC_INT_FLAG_ROVF: regular data register overflow interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief enable ADC interrupt - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_interrupt: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) -{ - switch(adc_interrupt){ - case ADC_INT_WDE: - /* enable analog watchdog interrupt */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - break; - case ADC_INT_EOC: - /* enable end of group conversion interrupt */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - break; - case ADC_INT_EOIC: - /* enable end of inserted group conversion interrupt */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; - break; - case ADC_INT_ROVF: - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_ROVFIE; - break; - default: - break; - } -} - -/*! - \brief disable ADC interrupt - \param[in] adc_periph: ADCx,x=0,1,2 - \param[in] adc_flag: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \arg ADC_INT_ROVF: regular data register overflow interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt) -{ - switch(adc_interrupt){ - /* select the interrupt source */ - case ADC_INT_WDE: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_WDEIE); - break; - case ADC_INT_EOC: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOCIE); - break; - case ADC_INT_EOIC: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_EOICIE); - break; - case ADC_INT_ROVF: - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_ROVFIE); - break; - default: - break; - } -} - -/*! - \brief configure the ADC sync mode - \param[in] sync_mode: ADC sync mode - only one parameter can be selected which is shown as below: - \arg ADC_SYNC_MODE_INDEPENDENT: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel & inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel & trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode - \arg ADC_DAUL_REGULAL_FOLLOW_UP: ADC0 and ADC1 work in follow-up mode - \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_PARALLEL: all ADCs work in combined regular parallel & inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL_INSERTED_ROTATION: all ADCs work in combined regular parallel & trigger rotation mode - \arg ADC_ALL_INSERTED_PARALLEL: all ADCs work in inserted parallel mode - \arg ADC_ALL_REGULAL_PARALLEL: all ADCs work in regular parallel mode - \arg ADC_ALL_REGULAL_FOLLOW_UP: all ADCs work in follow-up mode - \arg ADC_ALL_INSERTED_TRRIGGER_ROTATION: all ADCs work in trigger rotation mode - \param[out] none - \retval none -*/ -void adc_sync_mode_config(uint32_t sync_mode) -{ - ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCM); - ADC_SYNCCTL |= sync_mode; -} - -/*! - \brief configure the delay between 2 sampling phases in ADC sync modes - \param[in] sample_delay: the delay between 2 sampling phases in ADC sync modes - only one parameter can be selected which is shown as below: - \arg ADC_SYNC_DELAY_xCYCLE: x=5..20,the delay between 2 sampling phases in ADC sync modes is x ADC clock cycles - \param[out] none - \retval none -*/ -void adc_sync_delay_config(uint32_t sample_delay) -{ - ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDLY); - ADC_SYNCCTL |= sample_delay; -} - -/*! - \brief configure ADC sync DMA mode selection - \param[in] dma_mode: ADC sync DMA mode - only one parameter can be selected which is shown as below: - \arg ADC_SYNC_DMA_DISABLE: ADC sync DMA disabled - \arg ADC_SYNC_DMA_MODE0: ADC sync DMA mode 0 - \arg ADC_SYNC_DMA_MODE1: ADC sync DMA mode 1 - \param[out] none - \retval none -*/ -void adc_sync_dma_config(uint32_t dma_mode ) -{ - ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDMA); - ADC_SYNCCTL |= dma_mode; -} - -/*! - \brief configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected - \param[in] none - \param[out] none - \retval none -*/ -void adc_sync_dma_request_after_last_enable(void) -{ - ADC_SYNCCTL |= ADC_SYNCCTL_SYNCDDM; -} - -/*! - \brief configure ADC sync DMA engine issues requests according to the SYNCDMA bits - \param[in] none - \param[out] none - \retval none -*/ -void adc_sync_dma_request_after_last_disable(void) -{ - ADC_SYNCCTL &= ~(ADC_SYNCCTL_SYNCDDM); -} - -/*! - \brief read ADC sync regular data register - \param[in] none - \param[out] none - \retval sync regular data -*/ -uint32_t adc_sync_regular_data_read(void) -{ - return (uint32_t)ADC_SYNCDATA; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c deleted file mode 100644 index 5eb2974739..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c +++ /dev/null @@ -1,1027 +0,0 @@ -/*! - \file gd32f4xx_can.c - \brief CAN driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-11-27, V2.0.1, firmware for GD32F4xx - \version 2020-07-14, V2.0.2, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_can.h" - -#define CAN_ERROR_HANDLE(s) do{}while(1) - -/*! - \brief deinitialize CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_deinit(uint32_t can_periph) -{ - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - }else{ - rcu_periph_reset_enable(RCU_CAN1RST); - rcu_periph_reset_disable(RCU_CAN1RST); - } -} - -/*! - \brief initialize CAN parameter struct with a default value - \param[in] type: the type of CAN parameter struct - only one parameter can be selected which is shown as below: - \arg CAN_INIT_STRUCT: the CAN initial struct - \arg CAN_FILTER_STRUCT: the CAN filter struct - \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct - \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct - \param[in] p_struct: the pointer of the specific struct - \param[out] none - \retval none -*/ -void can_struct_para_init(can_struct_type_enum type, void* p_struct) -{ - uint8_t i; - - /* get type of the struct */ - switch(type){ - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct*)p_struct)->no_auto_retrans = DISABLE; - ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; - - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; - - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; - } - - ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; - - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; - } - - ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct*)p_struct)->rx_efid = 0U; - ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct*)p_struct)->rx_fi = 0U; - ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; - - break; - - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); - } -} - -/*! - \brief initialize CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] can_parameter_init: parameters for CAN initializtion - \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) - \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) - \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) - \arg time_triggered: ENABLE or DISABLE - \arg auto_bus_off_recovery: ENABLE or DISABLE - \arg auto_wake_up: ENABLE or DISABLE - \arg no_auto_retrans: ENABLE or DISABLE - \arg rec_fifo_overwrite: ENABLE or DISABLE - \arg trans_fifo_order: ENABLE or DISABLE - \arg prescaler: 0x0001 - 0x0400 - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) -{ - uint32_t timeout = CAN_TIMEOUT; - ErrStatus flag = ERROR; - - /* disable sleep mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - /* enable initialize mode */ - CAN_CTL(can_periph) |= CAN_CTL_IWMOD; - /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - /* set the bit timing register */ - CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ - BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ - BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ - BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ - BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); - /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ - CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; - } - /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ - CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_AWU; - } - /* automatic retransmission mode disable*/ - if(ENABLE == can_parameter_init->no_auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ARD; - } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } - /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ - CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } - /* disable initialize mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; - timeout = CAN_TIMEOUT; - /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check exit initialize mode */ - if(CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = SUCCESS; - } - } - return flag; -} - -/*! - \brief initialize CAN filter - \param[in] can_filter_parameter_init: struct for CAN filter initialization - \arg filter_list_high: 0x0000 - 0xFFFF - \arg filter_list_low: 0x0000 - 0xFFFF - \arg filter_mask_high: 0x0000 - 0xFFFF - \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - \arg filter_number: 0 - 27 - \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - \arg filter_enable: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) -{ - uint32_t val = 0U; - - val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* disable filter */ - CAN_FW(CAN0) &= ~(uint32_t)val; - - /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ - /* set filter 16 bits */ - CAN_FSCFG(CAN0) &= ~(uint32_t)val; - /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); - } - /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ - /* set filter 32 bits */ - CAN_FSCFG(CAN0) |= (uint32_t)val; - /* 32 bits list or first 32 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* 32 bits mask or second 32 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); - } - - /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ - /* mask mode */ - CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ - /* list mode */ - CAN_FMCFG(CAN0) |= (uint32_t)val; - } - - /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ - /* FIFO0 */ - CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - } - - if(CAN_FIFO1 == can_filter_parameter_init->filter_fifo_number){ - /* FIFO1 */ - CAN_FAFIFO(CAN0) |= (uint32_t)val; - } - - /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ - - CAN_FW(CAN0) |= (uint32_t)val; - } - - /* filter lock enable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief set CAN1 fliter start bank number - \param[in] can1_start_bank_number - \arg (1..27) - \param[out] none - \retval none -*/ -void can1_filter_start_bank(uint8_t start_bank) -{ - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* set CAN1 filter start number */ - CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; - CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief enable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_debug_freeze_enable(uint32_t can_periph) -{ - CAN_CTL(can_periph) |= CAN_CTL_DFZ; - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - }else{ - dbg_periph_enable(DBG_CAN1_HOLD); - } -} - -/*! - \brief disable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_debug_freeze_disable(uint32_t can_periph) -{ - CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; - if(CAN0 == can_periph){ - dbg_periph_disable(DBG_CAN0_HOLD); - }else{ - dbg_periph_disable(DBG_CAN0_HOLD); - } -} - -/*! - \brief enable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_time_trigger_mode_enable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* enable the tcc mode */ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - /* enable time stamp */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; - } -} - -/*! - \brief disable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_time_trigger_mode_disable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* disable the TCC mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - /* reset TSEN bits */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; - } -} - -/*! - \brief transmit CAN message - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] transmit_message: struct for CAN transmit message - \arg tx_sfid: 0x00000000 - 0x000007FF - \arg tx_efid: 0x00000000 - 0x1FFFFFFF - \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg tx_dlen: 0 - 8 - \arg tx_data[]: 0x00 - 0xFF - \param[out] none - \retval mailbox_number -*/ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) -{ - uint8_t mailbox_number = CAN_MAILBOX0; - - /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ - mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ - mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ - mailbox_number = CAN_MAILBOX2; - }else{ - mailbox_number = CAN_NOMAILBOX; - } - /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number){ - return CAN_NOMAILBOX; - } - - CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ - /* set transmit mailbox standard identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ - /* set transmit mailbox extended identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); - } - /* set the data length */ - transmit_message->tx_dlen &= (uint8_t)(CAN_TMP_DLENC); - CAN_TMP(can_periph, mailbox_number) &= ((uint32_t)~CAN_TMP_DLENC); - CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; - /* set the data */ - CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); - CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); - /* enable transmission */ - CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; - - return mailbox_number; -} - -/*! - \brief get CAN transmit state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOX(x=0,1,2) - \param[out] none - \retval can_transmit_state_enum -*/ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) -{ - can_transmit_state_enum state = CAN_TRANSMIT_FAILED; - uint32_t val = 0U; - - /* check selected mailbox state */ - switch(mailbox_number){ - /* mailbox0 */ - case CAN_MAILBOX0: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); - break; - /* mailbox1 */ - case CAN_MAILBOX1: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); - break; - /* mailbox2 */ - case CAN_MAILBOX2: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); - break; - default: - val = CAN_TRANSMIT_FAILED; - break; - } - - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): - state = CAN_TRANSMIT_PENDING; - break; - /* transmit failed */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_FAILED; - break; - case (CAN_TSTAT_MTF1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_FAILED; - break; - case (CAN_TSTAT_MTF2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_FAILED; - break; - /* transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_OK; - break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_OK; - break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_OK; - break; - /* transmit failed */ - default: - state = CAN_TRANSMIT_FAILED; - break; - } - return state; -} - -/*! - \brief stop CAN transmission - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOXx(x=0,1,2) - \param[out] none - \retval none -*/ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) -{ - if(CAN_MAILBOX0 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ - } - }else if(CAN_MAILBOX1 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ - } - }else if(CAN_MAILBOX2 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ - } - }else{ - /* illegal parameters */ - } -} - -/*! - \brief CAN receive message - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] receive_message: struct for CAN receive message - \arg rx_sfid: 0x00000000 - 0x000007FF - \arg rx_efid: 0x00000000 - 0x1FFFFFFF - \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg rx_dlen: 0 - 8 - \arg rx_data[]: 0x00 - 0xFF - \arg rx_fi: 0 - 27 - \retval none -*/ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) -{ - /* get the frame format */ - receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ - /* get standard identifier */ - receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ - /* get extended identifier */ - receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); - } - - /* get frame type */ - receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* filtering index */ - receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - /* get recevie data length */ - receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - - /* receive data */ - receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - - /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - } -} - -/*! - \brief release FIFO0 - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval none -*/ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) -{ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ - /* illegal parameters */ - CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); - } -} - -/*! - \brief CAN receive message length - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval message length -*/ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) -{ - uint8_t val = 0U; - - if(CAN_FIFO0 == fifo_number){ - /* FIFO0 */ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ - /* FIFO1 */ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ - /* illegal parameters */ - } - return val; -} - -/*! - \brief set CAN working mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] can_working_mode - only one parameter can be selected which is shown as below: - \arg CAN_MODE_INITIALIZE - \arg CAN_MODE_NORMAL - \arg CAN_MODE_SLEEP - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) -{ - ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if(CAN_MODE_INITIALIZE == working_mode){ - /* disable sleep mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); - /* set initialize mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_NORMAL == working_mode){ - /* enter normal mode */ - CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ - timeout--; - } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_SLEEP == working_mode){ - /* disable initialize mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); - /* set sleep mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; - /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else{ - flag = ERROR; - } - return flag; -} - -/*! - \brief wake up CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_wakeup(uint32_t can_periph) -{ - ErrStatus flag = ERROR; - uint32_t timeout = CAN_TIMEOUT; - - /* wakeup */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ - timeout--; - } - /* check state */ - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - return flag; -} - -/*! - \brief get CAN error type - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval can_error_enum - \arg CAN_ERROR_NONE: no error - \arg CAN_ERROR_FILL: fill error - \arg CAN_ERROR_FORMATE: format error - \arg CAN_ERROR_ACK: ACK error - \arg CAN_ERROR_BITRECESSIVE: bit recessive - \arg CAN_ERROR_BITDOMINANTER: bit dominant error - \arg CAN_ERROR_CRC: CRC error - \arg CAN_ERROR_SOFTWARECFG: software configure -*/ -can_error_enum can_error_get(uint32_t can_periph) -{ - can_error_enum error; - error = CAN_ERROR_NONE; - - /* get error type */ - error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); - return error; -} - -/*! - \brief get CAN receive error number - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval error number -*/ -uint8_t can_receive_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - /* get error count */ - val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief get CAN transmit error number - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval error number -*/ -uint8_t can_transmit_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - -/*! - \brief get CAN flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_RXL: RX level - \arg CAN_FLAG_LASTRX: last sample value of RX pin - \arg CAN_FLAG_RS: receiving state - \arg CAN_FLAG_TS: transmitting state - \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode - \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode - \arg CAN_FLAG_ERRIF: error flag - \arg CAN_FLAG_SLPWS: sleep working state - \arg CAN_FLAG_IWS: initial working state - \arg CAN_FLAG_TMLS2: transmit mailbox 2 last sending in Tx FIFO - \arg CAN_FLAG_TMLS1: transmit mailbox 1 last sending in Tx FIFO - \arg CAN_FLAG_TMLS0: transmit mailbox 0 last sending in Tx FIFO - \arg CAN_FLAG_TME2: transmit mailbox 2 empty - \arg CAN_FLAG_TME1: transmit mailbox 1 empty - \arg CAN_FLAG_TME0: transmit mailbox 0 empty - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost - \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost - \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost - \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error - \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error - \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ - /* get flag and interrupt enable state */ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_SLPIF: status change flag of entering sleep working mode - \arg CAN_FLAG_WUIF: status change flag of wakeup from sleep working mode - \arg CAN_FLAG_ERRIF: error flag - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MAL2: mailbox 2 arbitration lost - \arg CAN_FLAG_MAL1: mailbox 1 arbitration lost - \arg CAN_FLAG_MAL0: mailbox 0 arbitration lost - \arg CAN_FLAG_MTFNERR2: mailbox 2 transmit finished with no error - \arg CAN_FLAG_MTFNERR1: mailbox 1 transmit finished with no error - \arg CAN_FLAG_MTFNERR0: mailbox 0 transmit finished with no error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \param[out] none - \retval none -*/ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag) -{ - CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); -} - -/*! - \brief get CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFL0: receive FIFO0 not empty interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \arg CAN_INT_FLAG_RFL1: receive FIFO1 not empty interrupt flag - \arg CAN_INT_FLAG_ERRN: error number interrupt flag - \arg CAN_INT_FLAG_BOERR: bus-off error interrupt flag - \arg CAN_INT_FLAG_PERR: passive error interrupt flag - \arg CAN_INT_FLAG_WERR: warning error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - uint32_t ret1 = RESET; - uint32_t ret2 = RESET; - - /* get the staus of interrupt flag */ - if (flag == CAN_INT_FLAG_RFF0) { - ret1 = can_receive_message_length_get(can_periph, CAN_FIFO0); - } else if (flag == CAN_INT_FLAG_RFF1) { - ret1 = can_receive_message_length_get(can_periph, CAN_FIFO1); - } else if (flag == CAN_INT_FLAG_ERRN) { - ret1 = can_error_get(can_periph); - } else { - ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); - } - /* get the staus of interrupt enale bit */ - ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval none -*/ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c deleted file mode 100644 index bfe79cb9aa..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c +++ /dev/null @@ -1,128 +0,0 @@ -/*! - \file gd32f4xx_crc.c - \brief CRC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_crc.h" - -#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) -#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_DATA = CRC_DATA_RESET_VALUE; - CRC_FDATA = CRC_FDATA_RESET_VALUE; - CRC_CTL = (uint32_t)CRC_CTL_RST; -} - -/*! - \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the value of the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the value of the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write data to the free data register - \param[in] free_data: specified 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief calculate the CRC value of a 32-bit data - \param[in] sdata: specified 32-bit data - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return (CRC_DATA); -} - -/*! - \brief calculate the CRC value of an array of 32-bit values - \param[in] array: pointer to an array of 32-bit values - \param[in] size: size of the array - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for(index = 0U; index < size; index++){ - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c deleted file mode 100644 index ab67c4ad73..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c +++ /dev/null @@ -1,405 +0,0 @@ -/*! - \file gd32f4xx_ctc.c - \brief CTC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_ctc.h" - -#define CTC_FLAG_MASK ((uint32_t)0x00000700U) - -/* CTC register bit offset */ -#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U) -#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U) -#define CTC_REFCAP_OFFSET ((uint32_t)16U) -#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U) - -/*! - \brief reset CTC clock trim controller - \param[in] none - \param[out] none - \retval none -*/ -void ctc_deinit(void) -{ - /* reset CTC */ - rcu_periph_reset_enable(RCU_CTCRST); - rcu_periph_reset_disable(RCU_CTCRST); -} - -/*! - \brief enable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_enable(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN; -} - -/*! - \brief disable CTC trim counter - \param[in] none - \param[out] none - \retval none -*/ -void ctc_counter_disable(void) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN); -} - -/*! - \brief configure the IRC48M trim value - \param[in] ctc_trim_value: 8-bit IRC48M trim value - \arg 0x00 - 0x3F - \param[out] none - \retval none -*/ -void ctc_irc48m_trim_value_config(uint8_t trim_value) -{ - /* clear TRIMVALUE bits */ - CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE); - /* set TRIMVALUE bits */ - CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET); -} - -/*! - \brief generate software reference source sync pulse - \param[in] none - \param[out] none - \retval none -*/ -void ctc_software_refsource_pulse_generate(void) -{ - CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL; -} - -/*! - \brief configure hardware automatically trim mode - \param[in] hardmode: - only one parameter can be selected which is shown as below: - \arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable - \arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable - \param[out] none - \retval none -*/ -void ctc_hardware_trim_mode_config(uint32_t hardmode) -{ - CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM); - CTC_CTL0 |= (uint32_t)hardmode; -} - -/*! - \brief configure reference signal source polarity - \param[in] polarity: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge - \arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge - \param[out] none - \retval none -*/ -void ctc_refsource_polarity_config(uint32_t polarity) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL); - CTC_CTL1 |= (uint32_t)polarity; -} - -/*! - \brief select USBFS or USBHS SOF signal - \param[in] usbsof: - \arg CTC_USBSOFSEL_USBHS: USBHS SOF signal is selected - \arg CTC_USBSOFSEL_USBFS: USBFS SOF signal is selected - \param[out] none - \retval none -*/ -void ctc_usbsof_signal_select(uint32_t usbsof) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_USBSOFSEL); - CTC_CTL1 |= (uint32_t)usbsof; -} - -/*! - \brief select reference signal source - \param[in] refs: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_GPIO: GPIO is selected - \arg CTC_REFSOURCE_LXTAL: LXTAL is selected - \arg CTC_REFSOURCE_USBSOF: USBSOF is selected - \param[out] none - \retval none -*/ -void ctc_refsource_signal_select(uint32_t refs) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL); - CTC_CTL1 |= (uint32_t)refs; -} - -/*! - \brief configure reference signal source prescaler - \param[in] prescaler: - only one parameter can be selected which is shown as below: - \arg CTC_REFSOURCE_PSC_OFF: reference signal not divided - \arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2 - \arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4 - \arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8 - \arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16 - \arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32 - \arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64 - \arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128 - \param[out] none - \retval none -*/ -void ctc_refsource_prescaler_config(uint32_t prescaler) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC); - CTC_CTL1 |= (uint32_t)prescaler; -} - -/*! - \brief configure clock trim base limit value - \param[in] limit_value: 8-bit clock trim base limit value - \arg 0x00 - 0xFF - \param[out] none - \retval none -*/ -void ctc_clock_limit_value_config(uint8_t limit_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM); - CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET); -} - -/*! - \brief configure CTC counter reload value - \param[in] reload_value: 16-bit CTC counter reload value - \arg 0x0000 - 0xFFFF - \param[out] none - \retval none -*/ -void ctc_counter_reload_value_config(uint16_t reload_value) -{ - CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE); - CTC_CTL1 |= (uint32_t)reload_value; -} - -/*! - \brief read CTC counter capture value when reference sync pulse occurred - \param[in] none - \param[out] none - \retval the 16-bit CTC counter capture value -*/ -uint16_t ctc_counter_capture_value_read(void) -{ - uint16_t capture_value = 0U; - capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP)>> CTC_REFCAP_OFFSET); - return (capture_value); -} - -/*! - \brief read CTC trim counter direction when reference sync pulse occurred - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - \arg SET: CTC trim counter direction is down-counting - \arg RESET: CTC trim counter direction is up-counting -*/ -FlagStatus ctc_counter_direction_read(void) -{ - if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief read CTC counter reload value - \param[in] none - \param[out] none - \retval the 16-bit CTC counter reload value -*/ -uint16_t ctc_counter_reload_value_read(void) -{ - uint16_t reload_value = 0U; - reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE); - return (reload_value); -} - -/*! - \brief read the IRC48M trim value - \param[in] none - \param[out] none - \retval the 8-bit IRC48M trim value -*/ -uint8_t ctc_irc48m_trim_value_read(void) -{ - uint8_t trim_value = 0U; - trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET); - return (trim_value); -} - -/*! - \brief enable the CTC interrupt - \param[in] interrupt: CTC interrupt enable - one or more parameters can be selected which are shown as below: - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_enable(uint32_t interrupt) -{ - CTC_CTL0 |= (uint32_t)interrupt; -} - -/*! - \brief disable the CTC interrupt - \param[in] interrupt: CTC interrupt enable source - one or more parameters can be selected which are shown as below: - \arg CTC_INT_CKOK: clock trim OK interrupt enable - \arg CTC_INT_CKWARN: clock trim warning interrupt enable - \arg CTC_INT_ERR: error interrupt enable - \arg CTC_INT_EREF: expect reference interrupt enable - \param[out] none - \retval none -*/ -void ctc_interrupt_disable(uint32_t interrupt) -{ - CTC_CTL0 &= (uint32_t)(~interrupt); -} - -/*! - \brief get CTC interrupt flag - \param[in] int_flag: the CTC interrupt flag - only one parameter can be selected which is shown as below: - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) -{ - uint32_t interrupt_flag = 0U, intenable = 0U; - - /* check whether the interrupt is enabled */ - if(RESET != (int_flag & CTC_FLAG_MASK)){ - intenable = CTC_CTL0 & CTC_CTL0_ERRIE; - }else{ - intenable = CTC_CTL0 & int_flag; - } - - /* get interrupt flag status */ - interrupt_flag = CTC_STAT & int_flag; - - if(interrupt_flag && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CTC interrupt flag - \param[in] int_flag: the CTC interrupt flag - only one parameter can be selected which is shown as below: - \arg CTC_INT_FLAG_CKOK: clock trim OK interrupt - \arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt - \arg CTC_INT_FLAG_ERR: error interrupt - \arg CTC_INT_FLAG_EREF: expect reference interrupt - \arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt - \arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt - \arg CTC_INT_FLAG_TRIMERR: trim value error interrupt - \param[out] none - \retval none -*/ -void ctc_interrupt_flag_clear(uint32_t int_flag) -{ - if(RESET != (int_flag & CTC_FLAG_MASK)){ - CTC_INTC |= CTC_INTC_ERRIC; - }else{ - CTC_INTC |= int_flag; - } -} - -/*! - \brief get CTC flag - \param[in] flag: the CTC flag - only one parameter can be selected which is shown as below: - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ctc_flag_get(uint32_t flag) -{ - if(RESET != (CTC_STAT & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CTC flag - \param[in] flag: the CTC flag - only one parameter can be selected which is shown as below: - \arg CTC_FLAG_CKOK: clock trim OK flag - \arg CTC_FLAG_CKWARN: clock trim warning flag - \arg CTC_FLAG_ERR: error flag - \arg CTC_FLAG_EREF: expect reference flag - \arg CTC_FLAG_CKERR: clock trim error bit - \arg CTC_FLAG_REFMISS: reference sync pulse miss - \arg CTC_FLAG_TRIMERR: trim value error bit - \param[out] none - \retval none -*/ -void ctc_flag_clear(uint32_t flag) -{ - if(RESET != (flag & CTC_FLAG_MASK)){ - CTC_INTC |= CTC_INTC_ERRIC; - }else{ - CTC_INTC |= flag; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c deleted file mode 100644 index 3a5dd52cdd..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c +++ /dev/null @@ -1,677 +0,0 @@ -/*! - \file gd32f4xx_dac.c - \brief DAC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_dac.h" - -/* DAC register bit offset */ -#define DAC1_REG_OFFSET ((uint32_t)16U) -#define DH_12BIT_OFFSET ((uint32_t)16U) -#define DH_8BIT_OFFSET ((uint32_t)8U) - -/*! - \brief deinitialize DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_deinit(void) -{ - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); -} - -/*! - \brief enable DAC - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DEN0; - }else{ - DAC_CTL |= DAC_CTL_DEN1; - } -} - -/*! - \brief disable DAC - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DEN1; - } -} - -/*! - \brief enable DAC DMA function - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_dma_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ - DAC_CTL |= DAC_CTL_DDMAEN1; - } -} - -/*! - \brief disable DAC DMA function - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_dma_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DDMAEN1; - } -} - -/*! - \brief enable DAC output buffer - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ - DAC_CTL &= ~DAC_CTL_DBOFF1; - } -} - -/*! - \brief disable DAC output buffer - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DBOFF0; - }else{ - DAC_CTL |= DAC_CTL_DBOFF1; - } -} - -/*! - \brief get DAC output value - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if(DAC0 == dac_periph){ - /* store the DAC0 output value */ - data = (uint16_t)DAC0_DO; - }else{ - /* store the DAC1 output value */ - data = (uint16_t)DAC1_DO; - } - return data; -} - -/*! - \brief set the DAC specified data holding register value - \param[in] dac_periph: DACx(x = 0,1) - \param[in] dac_align: data alignment - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8 bit alignment - \arg DAC_ALIGN_12B_R: data right 12 bit alignment - \arg DAC_ALIGN_12B_L: data left 12 bit alignment - \param[in] data: data to be loaded - \param[out] none - \retval none -*/ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) -{ - if(DAC0 == dac_periph){ - switch(dac_align){ - /* data right 12 bit alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12 bit alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8 bit alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } - }else{ - switch(dac_align){ - /* data right 12 bit alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12 bit alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8 bit alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } - } -} - -/*! - \brief enable DAC trigger - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DTEN0; - }else{ - DAC_CTL |= DAC_CTL_DTEN1; - } -} - -/*! - \brief disable DAC trigger - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DTEN1; - } -} - -/*! - \brief set DAC trigger source - \param[in] dac_periph: DACx(x = 0,1) - \param[in] triggersource: external triggers of DAC - only one parameter can be selected which is shown as below: - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO - \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO - \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO - \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger - \param[out] none - \retval none -*/ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; - }else{ - /* configure DAC1 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC software trigger - \param[in] dac_periph: DACx(x = 0,1) - \retval none -*/ -void dac_software_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; - }else{ - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; - } -} - -/*! - \brief configure DAC wave mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] wave_mode: noise wave mode - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_DISABLE: wave disable - \arg DAC_WAVE_MODE_LFSR: LFSR noise mode - \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode - \param[out] none - \retval none -*/ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM0; - DAC_CTL |= wave_mode; - }else{ - /* configure DAC1 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC wave bit width - \param[in] dac_periph: DACx(x = 0,1) - \param[in] bit_width: noise wave bit width - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= bit_width; - }else{ - /* configure DAC1 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (bit_width << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC LFSR noise mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode - only one parameter can be selected which is shown as below: - \arg DAC_LFSR_BIT0: unmask the LFSR bit0 - \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] - \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] - \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] - \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] - \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] - \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] - \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] - \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] - \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] - \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] - \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] - \param[out] none - \retval none -*/ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= unmask_bits; - }else{ - /* configure DAC1 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC triangle noise mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] amplitude: triangle amplitude in DAC triangle noise mode - only one parameter can be selected which is shown as below: - \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 - \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 - \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 - \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 - \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 - \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 - \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 - \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 - \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 - \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 - \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 - \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 - \param[out] none - \retval none -*/ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= amplitude; - }else{ - /* configure DAC1 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (amplitude << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL |= (ctl); -} - -/*! - \brief disable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL &= (~ctl); -} - -/*! - \brief enable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_enable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); -} - -/*! - \brief disable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_disable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT &= (~swt); -} - -/*! - \brief enable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL &= (~ctl); -} - -/*! - \brief disable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL |= (ctl); -} - -/*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align: data alignment - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded - \param[out] none - \retval none -*/ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) -{ - uint32_t data = 0U; - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; - DACC_R8DH = data; - break; - default: - break; - } -} - -/*! - \brief enable DAC concurrent interrupt funcution - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_interrupt_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1; - DAC_CTL |= (ctl); -} - -/*! - \brief disable DAC concurrent interrupt funcution - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_interrupt_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DDUDRIE0 | DAC_CTL_DDUDRIE1; - DAC_CTL &= (~ctl); -} - -/*! - \brief enable DAC interrupt(DAC DMA underrun interrupt) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_interrupt_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL |= DAC_CTL_DDUDRIE1; - } -} - -/*! - \brief disable DAC interrupt(DAC DMA underrun interrupt) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_interrupt_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDUDRIE0; - }else{ - DAC_CTL &= ~DAC_CTL_DDUDRIE1; - } -} - -/*! - \brief get the specified DAC flag (DAC DMA underrun flag) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dac_flag_get(uint32_t dac_periph) -{ - FlagStatus temp_flag = RESET; - if(DAC0 == dac_periph){ - /* check the DMA underrun flag */ - if(RESET != (DAC_STAT & DAC_STAT_DDUDR0)){ - temp_flag = SET; - } - }else{ - /* check the DMA underrun flag */ - if(RESET != (DAC_STAT & DAC_STAT_DDUDR1)){ - temp_flag = SET; - } - } - return temp_flag; -} - -/*! - \brief clear the specified DAC flag (DAC DMA underrun flag) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_flag_clear(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_STAT |= DAC_STAT_DDUDR0; - }else{ - DAC_STAT |= DAC_STAT_DDUDR1; - } -} - -/*! - \brief get the specified DAC interrupt flag (DAC DMA underrun interrupt flag) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dac_interrupt_flag_get(uint32_t dac_periph) -{ - FlagStatus temp_flag = RESET; - uint32_t ddudr_flag = 0U, ddudrie_flag = 0U; - - if(DAC0 == dac_periph){ - /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ - ddudr_flag = DAC_STAT & DAC_STAT_DDUDR0; - ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE0; - if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ - temp_flag = SET; - } - }else{ - /* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */ - ddudr_flag = DAC_STAT & DAC_STAT_DDUDR1; - ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE1; - if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){ - temp_flag = SET; - } - } - return temp_flag; -} - -/*! - \brief clear the specified DAC interrupt flag (DAC DMA underrun interrupt flag) - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_interrupt_flag_clear(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_STAT |= DAC_STAT_DDUDR0; - }else{ - DAC_STAT |= DAC_STAT_DDUDR1; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c deleted file mode 100644 index a408136ea4..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c +++ /dev/null @@ -1,198 +0,0 @@ -/*! - \file gd32f4xx_dbg.c - \brief DBG driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_dbg.h" - -#define DBG_RESET_VAL 0x00000000U - -/*! - \brief deinitialize the DBG - \param[in] none - \param[out] none - \retval none -*/ -void dbg_deinit(void) -{ - DBG_CTL0 = DBG_RESET_VAL; - DBG_CTL1 = DBG_RESET_VAL; -} - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL0 |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL0 &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: dbg_periph_enum - only one parameter can be selected which is shown as below: - \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted - \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted - \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted - \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted - \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted - \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted - \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted - \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted - \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted - \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted - \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted - \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted - \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted - \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted - \arg \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: dbg_periph_enum - only one parameter can be selected which is shown as below: - \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted - \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted - \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted - \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted - \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted - \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted - \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted - \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted - \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted - \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted - \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted - \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted - \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted - \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); -} - -/*! - \brief enable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_enable(void) -{ - DBG_CTL0 |= DBG_CTL0_TRACE_IOEN; -} - -/*! - \brief disable trace pin assignment - \param[in] none - \param[out] none - \retval none -*/ -void dbg_trace_pin_disable(void) -{ - DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN; -} - -/*! - \brief trace pin mode selection - \param[in] trace_mode: - \arg TRACE_MODE_ASYNC: trace pin used for async mode - \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1 - \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2 - \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4 - \param[out] none - \retval none -*/ -void dbg_trace_pin_mode_set(uint32_t trace_mode) -{ - DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE; - DBG_CTL0 |= trace_mode; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c deleted file mode 100644 index a1ddcab384..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c +++ /dev/null @@ -1,345 +0,0 @@ -/*! - \file gd32f4xx_dci.c - \brief DCI driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_dci.h" - -/*! - \brief DCI deinit - \param[in] none - \param[out] none - \retval none -*/ -void dci_deinit(void) -{ - rcu_periph_reset_enable(RCU_DCIRST); - rcu_periph_reset_disable(RCU_DCIRST); -} - -/*! - \brief initialize DCI registers - \param[in] dci_struct: DCI parameter initialization structure - members of the structure and the member values are shown as below: - capture_mode : DCI_CAPTURE_MODE_CONTINUOUS, DCI_CAPTURE_MODE_SNAPSHOT - colck_polarity : DCI_CK_POLARITY_FALLING, DCI_CK_POLARITY_RISING - hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH - vsync_polarity : DCI_VSYNC_POLARITY_LOW, DCI_VSYNC_POLARITY_HIGH - frame_rate : DCI_FRAME_RATE_ALL, DCI_FRAME_RATE_1_2, DCI_FRAME_RATE_1_4 - interface_format: DCI_INTERFACE_FORMAT_8BITS, DCI_INTERFACE_FORMAT_10BITS, - DCI_INTERFACE_FORMAT_12BITS, DCI_INTERFACE_FORMAT_14BITS - \param[out] none - \retval none -*/ -void dci_init(dci_parameter_struct* dci_struct) -{ - uint32_t reg = 0U; - /* disable capture function and DCI */ - DCI_CTL &= ~(DCI_CTL_CAP | DCI_CTL_DCIEN); - /* configure DCI parameter */ - reg |= dci_struct->capture_mode; - reg |= dci_struct->clock_polarity; - reg |= dci_struct->hsync_polarity; - reg |= dci_struct->vsync_polarity; - reg |= dci_struct->frame_rate; - reg |= dci_struct->interface_format; - - DCI_CTL = reg; -} - -/*! - \brief enable DCI function - \param[in] none - \param[out] none - \retval none -*/ -void dci_enable(void) -{ - DCI_CTL |= DCI_CTL_DCIEN; -} - -/*! - \brief disable DCI function - \param[in] none - \param[out] none - \retval none -*/ -void dci_disable(void) -{ - DCI_CTL &= ~DCI_CTL_DCIEN; -} - -/*! - \brief enable DCI capture - \param[in] none - \param[out] none - \retval none -*/ -void dci_capture_enable(void) -{ - DCI_CTL |= DCI_CTL_CAP; -} - -/*! - \brief disable DCI capture - \param[in] none - \param[out] none - \retval none -*/ -void dci_capture_disable(void) -{ - DCI_CTL &= ~DCI_CTL_CAP; -} - -/*! - \brief enable DCI jpeg mode - \param[in] none - \param[out] none - \retval none -*/ -void dci_jpeg_enable(void) -{ - DCI_CTL |= DCI_CTL_JM; -} - -/*! - \brief disable DCI jpeg mode - \param[in] none - \param[out] none - \retval none -*/ -void dci_jpeg_disable(void) -{ - DCI_CTL &= ~DCI_CTL_JM; -} - -/*! - \brief enable cropping window function - \param[in] none - \param[out] none - \retval none -*/ -void dci_crop_window_enable(void) -{ - DCI_CTL |= DCI_CTL_WDEN; -} - -/*! - \brief disable cropping window function - \param[in] none - \param[out] none - \retval none -*/ -void dci_crop_window_disable(void) -{ - DCI_CTL &= ~DCI_CTL_WDEN; -} - -/*! - \brief configure DCI cropping window - \param[in] start_x: window horizontal start position - \param[in] start_y: window vertical start position - \param[in] size_width: window horizontal size - \param[in] size_height: window vertical size - \param[out] none - \retval none -*/ -void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height) -{ - DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y<<16)); - DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height<<16)); -} - -/*! - \brief enable embedded synchronous mode - \param[in] none - \param[out] none - \retval none -*/ -void dci_embedded_sync_enable(void) -{ - DCI_CTL |= DCI_CTL_ESM; -} - -/*! - \brief disble embedded synchronous mode - \param[in] none - \param[out] none - \retval none -*/ -void dci_embedded_sync_disable(void) -{ - DCI_CTL &= ~DCI_CTL_ESM; -} -/*! - \brief config synchronous codes in embedded synchronous mode - \param[in] frame_start: frame start code in embedded synchronous mode - \param[in] line_start: line start code in embedded synchronous mode - \param[in] line_end: line end code in embedded synchronous mode - \param[in] frame_end: frame end code in embedded synchronous mode - \param[out] none - \retval none -*/ -void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) -{ - DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); -} - -/*! - \brief config synchronous codes unmask in embedded synchronous mode - \param[in] frame_start: frame start code unmask bits in embedded synchronous mode - \param[in] line_start: line start code unmask bits in embedded synchronous mode - \param[in] line_end: line end code unmask bits in embedded synchronous mode - \param[in] frame_end: frame end code unmask bits in embedded synchronous mode - \param[out] none - \retval none -*/ -void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end) -{ - DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start<<8) | ((uint32_t)line_end<<16) | ((uint32_t)frame_end<<24)); -} - -/*! - \brief read DCI data register - \param[in] none - \param[out] none - \retval data -*/ -uint32_t dci_data_read(void) -{ - return DCI_DATA; -} - -/*! - \brief get specified flag - \param[in] flag: - \arg DCI_FLAG_HS: HS line status - \arg DCI_FLAG_VS: VS line status - \arg DCI_FLAG_FV:FIFO valid - \arg DCI_FLAG_EF: end of frame flag - \arg DCI_FLAG_OVR: FIFO overrun flag - \arg DCI_FLAG_ESE: embedded synchronous error flag - \arg DCI_FLAG_VSYNC: vsync flag - \arg DCI_FLAG_EL: end of line flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dci_flag_get(uint32_t flag) -{ - uint32_t stat = 0U; - - if(flag >> 31){ - /* get flag status from DCI_STAT1 register */ - stat = DCI_STAT1; - }else{ - /* get flag status from DCI_STAT0 register */ - stat = DCI_STAT0; - } - - if(flag & stat){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief enable specified DCI interrupt - \param[in] interrupt: - \arg DCI_INT_EF: end of frame interrupt - \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VSYNC: vsync interrupt - \arg DCI_INT_EL: end of line interrupt - \param[out] none - \retval none -*/ -void dci_interrupt_enable(uint32_t interrupt) -{ - DCI_INTEN |= interrupt; -} - -/*! - \brief disable specified DCI interrupt - \param[in] interrupt: - \arg DCI_INT_EF: end of frame interrupt - \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VSYNC: vsync interrupt - \arg DCI_INT_EL: end of line interrupt - \param[out] none - \retval none -*/ -void dci_interrupt_disable(uint32_t interrupt) -{ - DCI_INTEN &= ~interrupt; -} - -/*! - \brief clear specified interrupt flag - \param[in] int_flag: - \arg DCI_INT_EF: end of frame interrupt - \arg DCI_INT_OVR: FIFO overrun interrupt - \arg DCI_INT_ESE: embedded synchronous error interrupt - \arg DCI_INT_VSYNC: vsync interrupt - \arg DCI_INT_EL: end of line interrupt - \param[out] none - \retval none -*/ -void dci_interrupt_flag_clear(uint32_t int_flag) -{ - DCI_INTC |= int_flag; -} - -/*! - \brief get specified interrupt flag - \param[in] int_flag: - \arg DCI_INT_FLAG_EF: end of frame interrupt flag - \arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag - \arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag - \arg DCI_INT_FLAG_VSYNC: vsync interrupt flag - \arg DCI_INT_FLAG_EL: end of line interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dci_interrupt_flag_get(uint32_t int_flag) -{ - if(RESET == (DCI_INTF & int_flag)){ - return RESET; - }else{ - return SET; - } -} - - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c deleted file mode 100644 index d8bd7be2d7..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c +++ /dev/null @@ -1,905 +0,0 @@ -/*! - \file gd32f4xx_dma.c - \brief DMA driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#include "gd32f4xx_dma.h" - -/* DMA register bit offset */ -#define CHXCTL_PERIEN_OFFSET ((uint32_t)25U) - -/*! - \brief deinitialize DMA a channel registers - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is deinitialized - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) -{ - /* disable DMA a channel */ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(dma_periph,channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph,channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph,channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHM0ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_CHM1ADDR(dma_periph,channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_CHFCTL(dma_periph,channelx) = DMA_CHFCTL_RESET_VALUE; - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); - }else{ - channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE,channelx); - } -} - -/*! - \brief initialize the DMA single data mode parameters struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory0_addr = 0U; - init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; - init_struct->periph_memory_width = 0U; - init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; - init_struct->direction = DMA_PERIPH_TO_MEMORY; - init_struct->number = 0U; - init_struct->priority = DMA_PRIORITY_LOW; -} - -/*! - \brief initialize the DMA multi data mode parameters struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory0_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; - init_struct->memory_burst_width = 0U; - init_struct->periph_burst_width = 0U; - init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE; - init_struct->direction = DMA_PERIPH_TO_MEMORY; - init_struct->number = 0U; - init_struct->priority = DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA single data mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is initialized - \arg DMA_CHx(x=0..7) - \param[in] init_struct: the data needed to initialize DMA single data mode - periph_addr: peripheral base address - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX - memory0_addr: memory base address - memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE - periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE - direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct) -{ - uint32_t ctl; - - /* select single data mode */ - DMA_CHFCTL(dma_periph,channelx) &= ~DMA_CHXFCTL_MDMEN; - - /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct->number; - - /* configure peripheral and memory transfer width,channel priotity,transfer mode */ - ctl = DMA_CHCTL(dma_periph,channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM); - ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction); - DMA_CHCTL(dma_periph,channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; - } -} - -/*! - \brief initialize DMA multi data mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is initialized - \arg DMA_CHx(x=0..7) - \param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode - periph_addr: peripheral base address - periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX - memory0_addr: memory0 base address - memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE - memory_burst_width: DMA_MEMORY_BURST_SINGLE,DMA_MEMORY_BURST_4_BEAT,DMA_MEMORY_BURST_8_BEAT,DMA_MEMORY_BURST_16_BEAT - periph_burst_width: DMA_PERIPH_BURST_SINGLE,DMA_PERIPH_BURST_4_BEAT,DMA_PERIPH_BURST_8_BEAT,DMA_PERIPH_BURST_16_BEAT - critical_value: DMA_FIFO_1_WORD,DMA_FIFO_2_WORD,DMA_FIFO_3_WORD,DMA_FIFO_4_WORD - circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE - direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct) -{ - uint32_t ctl; - - /* select multi data mode and configure FIFO critical value */ - DMA_CHFCTL(dma_periph,channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value); - - /* configure peripheral base address */ - DMA_CHPADDR(dma_periph,channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHM0ADDR(dma_periph,channelx) = init_struct->memory0_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph,channelx) = init_struct->number; - - /* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */ - ctl = DMA_CHCTL(dma_periph,channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST); - ctl |= (init_struct->periph_width | (init_struct->memory_width ) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width | init_struct->periph_burst_width); - DMA_CHCTL(dma_periph,channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure DMA circular mode */ - if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; - } -} - -/*! - \brief set DMA peripheral base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set peripheral base address - \arg DMA_CHx(x=0..7) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - DMA_CHPADDR(dma_periph,channelx) = address; -} - -/*! - \brief set DMA Memory0 base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set Memory base address - \arg DMA_CHx(x=0..7) - \param[in] memory_flag: DMA_MEMORY_x(x=0,1) - \param[in] address: Memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address) -{ - if(memory_flag){ - DMA_CHM1ADDR(dma_periph,channelx) = address; - }else{ - DMA_CHM0ADDR(dma_periph,channelx) = address; - } -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - \arg DMA_CHx(x=0..7) - \param[in] number: the number of remaining data to be transferred by the DMA - \param[out] none - \retval none -*/ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) -{ - DMA_CHCNT(dma_periph,channelx) = number; -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - \arg DMA_CHx(x=0..7) - \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - return (uint32_t)DMA_CHCNT(dma_periph,channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] priority: priority Level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer burst beats of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] mbeat: transfer burst beats - \arg DMA_MEMORY_BURST_SINGLE: memory transfer single burst - \arg DMA_MEMORY_BURST_4_BEAT: memory transfer 4-beat burst - \arg DMA_MEMORY_BURST_8_BEAT: memory transfer 8-beat burst - \arg DMA_MEMORY_BURST_16_BEAT: memory transfer 16-beat burst - \param[out] none - \retval none -*/ -void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MBURST; - ctl |= mbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer burst beats of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] pbeat: transfer burst beats - only one parameter can be selected which is shown as below: - \arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst - \arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst - \arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst - \arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst - \param[out] none - \retval none -*/ -void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PBURST; - ctl |= pbeat; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer data size of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] msize: transfer data size of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= msize; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure transfer data size of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] msize: transfer data size of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= psize; - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief configure memory address generation generation_algorithm - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] generation_algorithm: the address generation algorithm - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode - \arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode - \param[out] none - \retval none -*/ -void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) -{ - if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MNAGA; - } -} - -/*! - \brief configure peripheral address generation_algorithm - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] generation_algorithm: the address generation algorithm - only one parameter can be selected which is shown as below: - \arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode - \arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode - \arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed - \param[out] none - \retval none -*/ -void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm) -{ - if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - }else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PNAGA; - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_PAIF; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval none -*/ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral - \arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_TM; - ctl |= direction; - - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief DMA switch buffer mode config - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] memory1_addr: memory1 base address - \param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1 - \param[out] none - \retval none -*/ -void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select) -{ - /* configure memory1 base address */ - DMA_CHM1ADDR(dma_periph,channelx) = memory1_addr; - - if(DMA_MEMORY_0 == memory_select){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_MBS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_MBS; - } -} - -/*! - \brief DMA using memory get - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval the using memory -*/ -uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - if((DMA_CHCTL(dma_periph,channelx)) & DMA_CHXCTL_MBS){ - return DMA_MEMORY_1; - }else{ - return DMA_MEMORY_0; - } -} - -/*! - \brief DMA channel peripheral select - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] sub_periph: specify DMA channel peripheral - \arg DMA_SUBPERIx(x=0..7) - \param[out] none - \retval none -*/ -void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph) -{ - uint32_t ctl; - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph,channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PERIEN; - ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET); - - DMA_CHCTL(dma_periph,channelx) = ctl; -} - -/*! - \brief DMA flow controller configure - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] controller: specify DMA flow controler - only one parameter can be selected which is shown as below: - \arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller - \arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller - \param[out] none - \retval none -*/ -void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller) -{ - if(DMA_FLOW_CONTROLLER_DMA == controller){ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_TFCS; - }else{ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_TFCS; - } -} - -/*! - \brief DMA switch buffer mode enable - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - /* switch buffer mode enable */ - DMA_CHCTL(dma_periph,channelx) |= DMA_CHXCTL_SBMEN; - }else{ - /* switch buffer mode disable */ - DMA_CHCTL(dma_periph,channelx) &= ~DMA_CHXCTL_SBMEN; - } -} - -/*! - \brief DMA FIFO status get - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[out] none - \retval the using memory -*/ -uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - return (DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FCNT); -} - -/*! - \brief get DMA flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - \arg DMA_CHx(x=0..7) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_FEE: FIFO error and exception flag - \arg DMA_FLAG_SDE: single data mode exception flag - \arg DMA_FLAG_TAE: transfer access error flag - \arg DMA_FLAG_HTF: half transfer finish flag - \arg DMA_FLAG_FTF: full transger finish flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - if(channelx < DMA_CH4){ - if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ - return SET; - }else{ - return RESET; - } - }else{ - channelx -= (dma_channel_enum)4; - if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag,channelx)){ - return SET; - }else{ - return RESET; - } - } -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - \arg DMA_CHx(x=0..7) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_FEE: FIFO error and exception flag - \arg DMA_FLAG_SDE: single data mode exception flag - \arg DMA_FLAG_TAE: transfer access error flag - \arg DMA_FLAG_HTF: half transfer finish flag - \arg DMA_FLAG_FTF: full transger finish flag - \param[out] none - \retval none -*/ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag,channelx); - }else{ - channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag,channelx); - } -} - -/*! - \brief get DMA interrupt flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get interrupt flag - \arg DMA_CHx(x=0..7) - \param[in] interrupt: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FEE: FIFO error and exception flag - \arg DMA_INT_FLAG_SDE: single data mode exception flag - \arg DMA_INT_FLAG_TAE: transfer access error flag - \arg DMA_INT_FLAG_HTF: half transfer finish flag - \arg DMA_INT_FLAG_FTF: full transger finish flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) -{ - uint32_t interrupt_enable = 0U,interrupt_flag = 0U; - dma_channel_enum channel_flag_offset = channelx; - if(channelx < DMA_CH4){ - switch(interrupt){ - case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; - break; - case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; - break; - case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; - break; - case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INTF_FTFIF: - interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt,channelx)); - interrupt_enable = (DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE); - break; - default: - break; - } - }else{ - channel_flag_offset -= (dma_channel_enum)4; - switch(interrupt){ - case DMA_INTF_FEEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHFCTL(dma_periph,channelx) & DMA_CHXFCTL_FEEIE; - break; - case DMA_INTF_SDEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_SDEIE; - break; - case DMA_INTF_TAEIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_TAEIE; - break; - case DMA_INTF_HTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INTF_FTFIF: - interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt,channel_flag_offset); - interrupt_enable = DMA_CHCTL(dma_periph,channelx) & DMA_CHXCTL_FTFIE; - break; - default: - break; - } - } - - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel interrupt flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear interrupt flag - \arg DMA_CHx(x=0..7) - \param[in] interrupt: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FEE: FIFO error and exception flag - \arg DMA_INT_FLAG_SDE: single data mode exception flag - \arg DMA_INT_FLAG_TAE: transfer access error flag - \arg DMA_INT_FLAG_HTF: half transfer finish flag - \arg DMA_INT_FLAG_FTF: full transger finish flag - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt) -{ - if(channelx < DMA_CH4){ - DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); - }else{ - channelx -= (dma_channel_enum)4; - DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt,channelx); - } -} - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) |= source; - }else{ - DMA_CHFCTL(dma_periph,channelx) |= source; - } -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - \arg DMA_CHx(x=0..7) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg DMA_CHXCTL_SDEIE: single data mode exception interrupt enable - \arg DMA_CHXCTL_TAEIE: tranfer access error interrupt enable - \arg DMA_CHXCTL_HTFIE: half transfer finish interrupt enable - \arg DMA_CHXCTL_FTFIE: full transfer finish interrupt enable - \arg DMA_CHXFCTL_FEEIE: FIFO exception interrupt enable - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(DMA_CHXFCTL_FEEIE != source){ - DMA_CHCTL(dma_periph,channelx) &= ~source; - }else{ - DMA_CHFCTL(dma_periph,channelx) &= ~source; - } -} - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c deleted file mode 100644 index 456e476fd8..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c +++ /dev/null @@ -1,3505 +0,0 @@ -/*! - \file gd32f4xx_enet.c - \brief ENET driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_enet.h" - -#if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#elif defined ( __ICCARM__ ) /*!< IAR compiler */ -#pragma data_alignment=4 -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -#pragma data_alignment=4 -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -#pragma data_alignment=4 -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -#pragma data_alignment=4 -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ - -#elif defined (__GNUC__) /* GNU Compiler */ -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ - -#endif /* __CC_ARM */ - -/* global transmit and receive descriptors pointers */ -enet_descriptors_struct *dma_current_txdesc; -enet_descriptors_struct *dma_current_rxdesc; - -/* structure pointer of ptp descriptor for normal mode */ -enet_descriptors_struct *dma_current_ptp_txdesc = NULL; -enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; - -/* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; -static uint32_t enet_unknow_err = 0U; -/* array of register offset for debug information get */ -static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, - -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, -0x104C, 0x1050, 0x1054}; - -/* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ -static void enet_default_init(void); -#ifdef USE_DELAY -/* user can provide more timing precise _ENET_DELAY_ function */ -#define _ENET_DELAY_ delay_ms -#else -/* insert a delay time */ -static void enet_delay(uint32_t ncount); -/* default _ENET_DELAY_ function with less precise timing */ -#define _ENET_DELAY_ enet_delay -#endif - - -/*! - \brief deinitialize the ENET, and reset structure parameters for ENET initialization - \param[in] none - \param[out] none - \retval none -*/ -void enet_deinit(void) -{ - rcu_periph_reset_enable(RCU_ENETRST); - rcu_periph_reset_disable(RCU_ENETRST); - enet_initpara_reset(); -} - -/*! - \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise - configuration will be no effect - \param[in] option: different function option, which is related to several parameters, refer to enet_option_enum - only one parameter can be selected which is shown as below - \arg FORWARD_OPTION: choose to configure the frame forward related parameters - \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters - \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters - \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters - \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters - \arg VLAN_OPTION: choose to configure vlan related parameters - \arg FLOWCTL_OPTION: choose to configure flow control related parameters - \arg HASHH_OPTION: choose to configure hash high - \arg HASHL_OPTION: choose to configure hash low - \arg FILTER_OPTION: choose to configure frame filter related parameters - \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters - \arg TIMER_OPTION: choose to configure time counter related parameters - \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option - all the related parameters should be configured which are shown as below - FORWARD_OPTION related parameters: - - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; - - ENET_TYPEFRAME_CRC_DROP_ENABLE/ ENET_TYPEFRAME_CRC_DROP_DISABLE ; - - ENET_FORWARD_ERRFRAMES_ENABLE/ ENET_FORWARD_ERRFRAMES_DISABLE ; - - ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE/ ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE . - DMABUS_OPTION related parameters: - - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; - - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; - - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; - DMA_MAXBURST_OPTION related parameters: - - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ - ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ - ENET_RXDP_4xPGBL_4BEAT/ ENET_RXDP_4xPGBL_8BEAT/ - ENET_RXDP_4xPGBL_16BEAT/ ENET_RXDP_4xPGBL_32BEAT/ - ENET_RXDP_4xPGBL_64BEAT/ ENET_RXDP_4xPGBL_128BEAT ; - - ENET_PGBL_1BEAT/ ENET_PGBL_2BEAT/ ENET_PGBL_4BEAT/ - ENET_PGBL_8BEAT/ ENET_PGBL_16BEAT/ ENET_PGBL_32BEAT/ - ENET_PGBL_4xPGBL_4BEAT/ ENET_PGBL_4xPGBL_8BEAT/ - ENET_PGBL_4xPGBL_16BEAT/ ENET_PGBL_4xPGBL_32BEAT/ - ENET_PGBL_4xPGBL_64BEAT/ ENET_PGBL_4xPGBL_128BEAT ; - - ENET_RXTX_DIFFERENT_PGBL/ ENET_RXTX_SAME_PGBL ; - DMA_ARBITRATION_OPTION related parameters: - - ENET_ARBITRATION_RXPRIORTX - - ENET_ARBITRATION_RXTX_1_1/ ENET_ARBITRATION_RXTX_2_1/ - ENET_ARBITRATION_RXTX_3_1/ ENET_ARBITRATION_RXTX_4_1/. - STORE_OPTION related parameters: - - ENET_RX_MODE_STOREFORWARD/ ENET_RX_MODE_CUTTHROUGH ; - - ENET_TX_MODE_STOREFORWARD/ ENET_TX_MODE_CUTTHROUGH ; - - ENET_RX_THRESHOLD_64BYTES/ ENET_RX_THRESHOLD_32BYTES/ - ENET_RX_THRESHOLD_96BYTES/ ENET_RX_THRESHOLD_128BYTES ; - - ENET_TX_THRESHOLD_64BYTES/ ENET_TX_THRESHOLD_128BYTES/ - ENET_TX_THRESHOLD_192BYTES/ ENET_TX_THRESHOLD_256BYTES/ - ENET_TX_THRESHOLD_40BYTES/ ENET_TX_THRESHOLD_32BYTES/ - ENET_TX_THRESHOLD_24BYTES/ ENET_TX_THRESHOLD_16BYTES . - DMA_OPTION related parameters: - - ENET_FLUSH_RXFRAME_ENABLE/ ENET_FLUSH_RXFRAME_DISABLE ; - - ENET_SECONDFRAME_OPT_ENABLE/ ENET_SECONDFRAME_OPT_DISABLE ; - - ENET_ENHANCED_DESCRIPTOR/ ENET_NORMAL_DESCRIPTOR . - VLAN_OPTION related parameters: - - ENET_VLANTAGCOMPARISON_12BIT/ ENET_VLANTAGCOMPARISON_16BIT ; - - MAC_VLT_VLTI(regval) . - FLOWCTL_OPTION related parameters: - - MAC_FCTL_PTM(regval) ; - - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ - ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; - - ENET_TX_FLOWCONTROL_ENABLE/ ENET_TX_FLOWCONTROL_DISABLE . - HASHH_OPTION related parameters: - - 0x0~0xFFFF FFFFU - HASHL_OPTION related parameters: - - 0x0~0xFFFF FFFFU - FILTER_OPTION related parameters: - - ENET_SRC_FILTER_NORMAL_ENABLE/ ENET_SRC_FILTER_INVERSE_ENABLE/ - ENET_SRC_FILTER_DISABLE ; - - ENET_DEST_FILTER_INVERSE_ENABLE/ ENET_DEST_FILTER_INVERSE_DISABLE ; - - ENET_MULTICAST_FILTER_HASH_OR_PERFECT/ ENET_MULTICAST_FILTER_HASH/ - ENET_MULTICAST_FILTER_PERFECT/ ENET_MULTICAST_FILTER_NONE ; - - ENET_UNICAST_FILTER_EITHER/ ENET_UNICAST_FILTER_HASH/ - ENET_UNICAST_FILTER_PERFECT ; - - ENET_PCFRM_PREVENT_ALL/ ENET_PCFRM_PREVENT_PAUSEFRAME/ - ENET_PCFRM_FORWARD_ALL/ ENET_PCFRM_FORWARD_FILTERED . - HALFDUPLEX_OPTION related parameters: - - ENET_CARRIERSENSE_ENABLE/ ENET_CARRIERSENSE_DISABLE ; - - ENET_RECEIVEOWN_ENABLE/ ENET_RECEIVEOWN_DISABLE ; - - ENET_RETRYTRANSMISSION_ENABLE/ ENET_RETRYTRANSMISSION_DISABLE ; - - ENET_BACKOFFLIMIT_10/ ENET_BACKOFFLIMIT_8/ - ENET_BACKOFFLIMIT_4/ ENET_BACKOFFLIMIT_1 ; - - ENET_DEFERRALCHECK_ENABLE/ ENET_DEFERRALCHECK_DISABLE . - TIMER_OPTION related parameters: - - ENET_WATCHDOG_ENABLE/ ENET_WATCHDOG_DISABLE ; - - ENET_JABBER_ENABLE/ ENET_JABBER_DISABLE ; - INTERFRAMEGAP_OPTION related parameters: - - ENET_INTERFRAMEGAP_96BIT/ ENET_INTERFRAMEGAP_88BIT/ - ENET_INTERFRAMEGAP_80BIT/ ENET_INTERFRAMEGAP_72BIT/ - ENET_INTERFRAMEGAP_64BIT/ ENET_INTERFRAMEGAP_56BIT/ - ENET_INTERFRAMEGAP_48BIT/ ENET_INTERFRAMEGAP_40BIT . - \param[out] none - \retval none -*/ -void enet_initpara_config(enet_option_enum option, uint32_t para) -{ - switch(option){ - case FORWARD_OPTION: - /* choose to configure forward_frame, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; - enet_initpara.forward_frame = para; - break; - case DMABUS_OPTION: - /* choose to configure dmabus_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; - enet_initpara.dmabus_mode = para; - break; - case DMA_MAXBURST_OPTION: - /* choose to configure dma_maxburst, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; - enet_initpara.dma_maxburst = para; - break; - case DMA_ARBITRATION_OPTION: - /* choose to configure dma_arbitration, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; - enet_initpara.dma_arbitration = para; - break; - case STORE_OPTION: - /* choose to configure store_forward_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)STORE_OPTION; - enet_initpara.store_forward_mode = para; - break; - case DMA_OPTION: - /* choose to configure dma_function, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - -#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE - para &= ~ENET_ENHANCED_DESCRIPTOR; -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - - enet_initpara.dma_function = para; - break; - case VLAN_OPTION: - /* choose to configure vlan_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; - enet_initpara.vlan_config = para; - break; - case FLOWCTL_OPTION: - /* choose to configure flow_control, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; - enet_initpara.flow_control = para; - break; - case HASHH_OPTION: - /* choose to configure hashtable_high, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; - enet_initpara.hashtable_high = para; - break; - case HASHL_OPTION: - /* choose to configure hashtable_low, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; - enet_initpara.hashtable_low = para; - break; - case FILTER_OPTION: - /* choose to configure framesfilter_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; - enet_initpara.framesfilter_mode = para; - break; - case HALFDUPLEX_OPTION: - /* choose to configure halfduplex_param, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; - enet_initpara.halfduplex_param = para; - break; - case TIMER_OPTION: - /* choose to configure timer_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; - break; - case INTERFRAMEGAP_OPTION: - /* choose to configure interframegap, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; - enet_initpara.interframegap = para; - break; - default: - break; - } -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared - parameters - \param[in] mediamode: PHY mode and mac loopback configurations, refer to enet_mediamode_enum - only one parameter can be selected which is shown as below - \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation - \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex - \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex - \arg ENET_10M_FULLDUPLEX: 10Mbit/s, full-duplex - \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex - \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII - \param[in] checksum: IP frame checksum offload function, refer to enet_mediamode_enum - only one parameter can be selected which is shown as below - \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function - \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function - \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame - with only payload error but no other errors will not be dropped - \param[in] recept: frame filter function, refer to enet_frmrecept_enum - only one parameter can be selected which is shown as below - \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled - \arg ENET_RECEIVEALL: all received frame are forwarded to application - \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames - \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) -{ - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; - uint32_t media_temp = 0U; - uint32_t timeout = 0U; - uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; - - /* PHY interface configuration, configure SMI clock and reset PHY chip */ - if(ERROR == enet_phy_config()){ - _ENET_DELAY_(PHY_RESETDELAY); - if(ERROR == enet_phy_config()){ - return enet_state; - } - } - /* initialize ENET peripheral with generally concerned parameters */ - enet_default_init(); - - /* 1st, configure mediamode */ - media_temp = (uint32_t)mediamode; - /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ - /* wait for PHY_LINKED_STATUS bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; - timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* enable auto-negotiation */ - phy_value = PHY_AUTONEGOTIATION; - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - - /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_AUTONEGO_COMPLETE; - timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - - /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); - /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ - media_temp = ENET_MODE_FULLDUPLEX; - }else{ - media_temp = ENET_MODE_HALFDUPLEX; - } - /* configure the communication speed of MAC following the auto-negotiation result */ - if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ - media_temp |= ENET_SPEEDMODE_10M; - }else{ - media_temp |= ENET_SPEEDMODE_100M; - } - }else{ - phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); - phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; - } - /* PHY configuration need some time */ - _ENET_DELAY_(PHY_CONFIGDELAY); - } - /* after configuring the PHY, use mediamode to configure registers */ - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); - reg_value |= media_temp; - ENET_MAC_CFG = reg_value; - - - /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ - ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~ENET_DMA_CTL_DTCERFD; - reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); - ENET_DMA_CTL = reg_value; - } - - /* 3rd, configure recept */ - ENET_MAC_FRMF |= (uint32_t)recept; - - /* 4th, configure different function options */ - /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ - reg_temp = enet_initpara.forward_frame; - - reg_value = ENET_MAC_CFG; - temp = reg_temp; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_TFCD |ENET_MAC_CFG_APCD)); - temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); - reg_value |= temp; - ENET_MAC_CFG = reg_value; - - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); - temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); - reg_value |= (temp >> 2); - ENET_DMA_CTL = reg_value; - } - - /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ - temp = enet_initpara.dmabus_mode; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ - temp = enet_initpara.dma_maxburst; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ - temp = enet_initpara.dma_arbitration; - - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ - temp = enet_initpara.store_forward_mode; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - } - - /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ - reg_temp = enet_initpara.dma_function; - - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); - temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - - reg_value = ENET_DMA_BCTL; - temp = reg_temp; - /* configure ENET_DMA_BCTL register */ - reg_value &= (~ENET_DMA_BCTL_DFM); - temp &= ENET_DMA_BCTL_DFM; - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } - - /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ - reg_temp = enet_initpara.vlan_config; - - reg_value = ENET_MAC_VLT; - /* configure ENET_MAC_VLT register */ - reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); - reg_value |= reg_temp; - ENET_MAC_VLT = reg_value; - } - - /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ - reg_temp = enet_initpara.flow_control; - - reg_value = ENET_MAC_FCTL; - temp = reg_temp; - /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - reg_value |= temp; - ENET_MAC_FCTL = reg_value; - - reg_value = ENET_MAC_FCTH; - temp = reg_temp; - /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); - reg_value |= (temp >> 8); - ENET_MAC_FCTH = reg_value; - } - - /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ - ENET_MAC_HLH = enet_initpara.hashtable_high; - } - - /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ - ENET_MAC_HLL = enet_initpara.hashtable_low; - } - - /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ - reg_temp = enet_initpara.framesfilter_mode; - - reg_value = ENET_MAC_FRMF; - /* configure ENET_MAC_FRMF register */ - reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); - reg_value |= reg_temp; - ENET_MAC_FRMF = reg_value; - } - - /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ - reg_temp = enet_initpara.halfduplex_param; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ - reg_temp = enet_initpara.timer_config; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ - reg_temp = enet_initpara.interframegap; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~ENET_MAC_CFG_IGBS; - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } - - enet_state = SUCCESS; - return enet_state; -} - -/*! - \brief reset all core internal registers located in CLK_TX and CLK_RX - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_software_reset(void) -{ - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - uint32_t dma_flag; - - /* reset all core internal registers located in CLK_TX and CLK_RX */ - ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; - - /* wait for reset operation complete */ - do{ - dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); - timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - - /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief check receive frame valid and return frame size - \param[in] none - \param[out] none - \retval size of received frame: 0x0 - 0x3FFF -*/ -uint32_t enet_rxframe_size_get(void) -{ - uint32_t size = 0U; - uint32_t status; - - /* get rdes0 information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - - /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ - return 0U; - } - - /* if has any error, or the frame uses two or more descriptors */ - if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; - } -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE - /* if is an ethernet-type frame, and IP frame payload error occurred */ - if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && - ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; - } -#else - /* if is an ethernet-type frame, and IP frame payload error occurred */ - if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; - } -#endif - /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ - if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ - /* get the size of the received data including CRC */ - size = GET_RDES0_FRML(status); - /* substract the CRC size */ - size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - }else{ - enet_unknow_err++; - enet_rxframe_drop(); - - return 1U; - } - - /* return packet size */ - return size; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in chain mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_chain_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode */ - desc_status = ENET_TDES0_TCHM; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; - } - } -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in ring mode - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_descriptors_ring_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc; - enet_descriptors_struct *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* set buffer1 size */ - desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - dma_current_ptp_rxdesc = NULL; - dma_current_ptp_txdesc = NULL; - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - } -} - -/*! - \brief handle current received frame data to application buffer - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] buffer: pointer to the received frame data - note -- if the input is NULL, user should copy data in application by himself - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status); - size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); - } - - }else{ - /* return ERROR */ - return ERROR; - } - } - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief handle application buffer data to transmit it - \param[in] buffer: pointer to the frame data to be transmitted, - note -- if the input is NULL, user should handle the data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) -{ - uint32_t offset = 0U; - uint32_t dma_tbu_flag, dma_tu_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); - } - } - - return SUCCESS; -} - -/*! - \brief configure the transmit IP frame checksum offload calculation and insertion - \param[in] desc: the descriptor pointer which users want to configure, refer to enet_descriptors_struct - \param[in] checksum: IP frame checksum configuration - only one parameter can be selected which is shown as below - \arg ENET_CHECKSUM_DISABLE: checksum insertion disabled - \arg ENET_CHECKSUM_IPV4HEADER: only IP header checksum calculation and insertion are enabled - \arg ENET_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP checksum insertion calculated but pseudo-header - \arg ENET_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP checksum insertion fully calculated - \param[out] none - \retval none -*/ -void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) -{ - desc->status &= ~ENET_TDES0_CM; - desc->status |= checksum; -} - -/*! - \brief ENET Tx and Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_enable(void) -{ - enet_tx_enable(); - enet_rx_enable(); -} - -/*! - \brief ENET Tx and Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_disable(void) -{ - enet_tx_disable(); - enet_rx_disable(); -} - -/*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, refer to enet_macaddress_enum - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: set MAC address 0 filter - \arg ENET_MAC_ADDRESS1: set MAC address 1 filter - \arg ENET_MAC_ADDRESS2: set MAC address 2 filter - \arg ENET_MAC_ADDRESS3: set MAC address 3 filter - \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \param[out] none - \retval none -*/ -void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); - REG32(ENET_ADDRL_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRL(paddr); -} - -/*! - \brief get MAC address - \param[in] mac_addr: select which MAC address will be get, refer to enet_macaddress_enum - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS0: get MAC address 0 filter - \arg ENET_MAC_ADDRESS1: get MAC address 1 filter - \arg ENET_MAC_ADDRESS2: get MAC address 2 filter - \arg ENET_MAC_ADDRESS3: get MAC address 3 filter - \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) - \retval none -*/ -void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]) -{ - paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); - paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); - paddr[2] = ENET_GET_MACADDR(mac_addr, 2U); - paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); - paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); - paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); -} - -/*! - \brief get the ENET MAC/MSC/PTP/DMA status flag - \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, - only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag - \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag - \arg ENET_MAC_FLAG_WUM: WUM status flag - \arg ENET_MAC_FLAG_MSC: MSC status flag - \arg ENET_MAC_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_FLAG_TMST: time stamp trigger status flag - \arg ENET_PTP_FLAG_TSSCO: timestamp second counter overflow flag - \arg ENET_PTP_FLAG_TTM: target time match flag - \arg ENET_MSC_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_FLAG_TS: transmit status flag - \arg ENET_DMA_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_FLAG_RO: receive overflow status flag - \arg ENET_DMA_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_FLAG_RS: receive status flag - \arg ENET_DMA_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_FLAG_ET: early transmit status flag - \arg ENET_DMA_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_FLAG_ER: early receive status flag - \arg ENET_DMA_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_FLAG_EB_DMA_ERROR: DMA error flag - \arg ENET_DMA_FLAG_EB_TRANSFER_ERROR: transfer error flag - \arg ENET_DMA_FLAG_EB_ACCESS_ERROR: access error flag - \arg ENET_DMA_FLAG_MSC: MSC status flag - \arg ENET_DMA_FLAG_WUM: WUM status flag - \arg ENET_DMA_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_flag_get(enet_flag_enum enet_flag) -{ - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the ENET DMA status flag - \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear - \arg ENET_DMA_FLAG_TPS_CLR: transmit process stopped status flag clear - \arg ENET_DMA_FLAG_TBU_CLR: transmit buffer unavailable status flag clear - \arg ENET_DMA_FLAG_TJT_CLR: transmit jabber timeout status flag clear - \arg ENET_DMA_FLAG_RO_CLR: receive overflow status flag clear - \arg ENET_DMA_FLAG_TU_CLR: transmit underflow status flag clear - \arg ENET_DMA_FLAG_RS_CLR: receive status flag clear - \arg ENET_DMA_FLAG_RBU_CLR: receive buffer unavailable status flag clear - \arg ENET_DMA_FLAG_RPS_CLR: receive process stopped status flag clear - \arg ENET_DMA_FLAG_RWT_CLR: receive watchdog timeout status flag clear - \arg ENET_DMA_FLAG_ET_CLR: early transmit status flag clear - \arg ENET_DMA_FLAG_FBE_CLR: fatal bus error status flag clear - \arg ENET_DMA_FLAG_ER_CLR: early receive status flag clear - \arg ENET_DMA_FLAG_AI_CLR: abnormal interrupt summary flag clear - \arg ENET_DMA_FLAG_NI_CLR: normal interrupt summary flag clear - \param[out] none - \retval none -*/ -void enet_flag_clear(enet_flag_clear_enum enet_flag) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(enet_flag) = BIT(ENET_BIT_POS(enet_flag)); -} - -/*! - \brief enable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt,, refer to enet_int_enum - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_enable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief disable ENET MAC/MSC/DMA interrupt - \param[in] enet_int: ENET interrupt, refer to enet_int_enum - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_WUMIM: WUM interrupt mask - \arg ENET_MAC_INT_TMSTIM: timestamp trigger interrupt mask - \arg ENET_MSC_INT_RFCEIM: received frame CRC error interrupt mask - \arg ENET_MSC_INT_RFAEIM: received frames alignment error interrupt mask - \arg ENET_MSC_INT_RGUFIM: received good unicast frames interrupt mask - \arg ENET_MSC_INT_TGFSCIM: transmitted good frames single collision interrupt mask - \arg ENET_MSC_INT_TGFMSCIM: transmitted good frames more single collision interrupt mask - \arg ENET_MSC_INT_TGFIM: transmitted good frames interrupt mask - \arg ENET_DMA_INT_TIE: transmit interrupt enable - \arg ENET_DMA_INT_TPSIE: transmit process stopped interrupt enable - \arg ENET_DMA_INT_TBUIE: transmit buffer unavailable interrupt enable - \arg ENET_DMA_INT_TJTIE: transmit jabber timeout interrupt enable - \arg ENET_DMA_INT_ROIE: receive overflow interrupt enable - \arg ENET_DMA_INT_TUIE: transmit underflow interrupt enable - \arg ENET_DMA_INT_RIE: receive interrupt enable - \arg ENET_DMA_INT_RBUIE: receive buffer unavailable interrupt enable - \arg ENET_DMA_INT_RPSIE: receive process stopped interrupt enable - \arg ENET_DMA_INT_RWTIE: receive watchdog timeout interrupt enable - \arg ENET_DMA_INT_ETIE: early transmit interrupt enable - \arg ENET_DMA_INT_FBEIE: fatal bus error interrupt enable - \arg ENET_DMA_INT_ERIE: early receive interrupt enable - \arg ENET_DMA_INT_AIE: abnormal interrupt summary enable - \arg ENET_DMA_INT_NIE: normal interrupt summary enable - \param[out] none - \retval none -*/ -void enet_interrupt_disable(enet_int_enum enet_int) -{ - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ - /* ENET_DMA_INTEN register interrupt */ - ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ - /* other INTMSK register interrupt */ - ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - } -} - -/*! - \brief get ENET MAC/MSC/DMA interrupt flag - \param[in] int_flag: ENET interrupt flag, refer to enet_int_flag_enum - only one parameter can be selected which is shown as below - \arg ENET_MAC_INT_FLAG_WUM: WUM status flag - \arg ENET_MAC_INT_FLAG_MSC: MSC status flag - \arg ENET_MAC_INT_FLAG_MSCR: MSC receive status flag - \arg ENET_MAC_INT_FLAG_MSCT: MSC transmit status flag - \arg ENET_MAC_INT_FLAG_TMST: time stamp trigger status flag - \arg ENET_MSC_INT_FLAG_RFCE: received frames CRC error flag - \arg ENET_MSC_INT_FLAG_RFAE: received frames alignment error flag - \arg ENET_MSC_INT_FLAG_RGUF: received good unicast frames flag - \arg ENET_MSC_INT_FLAG_TGFSC: transmitted good frames single collision flag - \arg ENET_MSC_INT_FLAG_TGFMSC: transmitted good frames more single collision flag - \arg ENET_MSC_INT_FLAG_TGF: transmitted good frames flag - \arg ENET_DMA_INT_FLAG_TS: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS: receive status flag - \arg ENET_DMA_INT_FLAG_RBU: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER: early receive status flag - \arg ENET_DMA_INT_FLAG_AI: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI: normal interrupt summary flag - \arg ENET_DMA_INT_FLAG_MSC: MSC status flag - \arg ENET_DMA_INT_FLAG_WUM: WUM status flag - \arg ENET_DMA_INT_FLAG_TST: timestamp trigger status flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) -{ - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear ENET DMA interrupt flag - \param[in] int_flag_clear: clear ENET interrupt flag, refer to enet_int_flag_clear_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag - \arg ENET_DMA_INT_FLAG_TPS_CLR: transmit process stopped status flag - \arg ENET_DMA_INT_FLAG_TBU_CLR: transmit buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_TJT_CLR: transmit jabber timeout status flag - \arg ENET_DMA_INT_FLAG_RO_CLR: receive overflow status flag - \arg ENET_DMA_INT_FLAG_TU_CLR: transmit underflow status flag - \arg ENET_DMA_INT_FLAG_RS_CLR: receive status flag - \arg ENET_DMA_INT_FLAG_RBU_CLR: receive buffer unavailable status flag - \arg ENET_DMA_INT_FLAG_RPS_CLR: receive process stopped status flag - \arg ENET_DMA_INT_FLAG_RWT_CLR: receive watchdog timeout status flag - \arg ENET_DMA_INT_FLAG_ET_CLR: early transmit status flag - \arg ENET_DMA_INT_FLAG_FBE_CLR: fatal bus error status flag - \arg ENET_DMA_INT_FLAG_ER_CLR: early receive status flag - \arg ENET_DMA_INT_FLAG_AI_CLR: abnormal interrupt summary flag - \arg ENET_DMA_INT_FLAG_NI_CLR: normal interrupt summary flag - \param[out] none - \retval none -*/ -void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear) -{ - /* write 1 to the corresponding bit in ENET_DMA_STAT, to clear it */ - ENET_REG_VAL(int_flag_clear) = BIT(ENET_BIT_POS(int_flag_clear)); -} - -/*! - \brief ENET Tx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_TEN; - enet_txfifo_flush(); - ENET_DMA_CTL |= ENET_DMA_CTL_STE; -} - -/*! - \brief ENET Tx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_tx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; - enet_txfifo_flush(); - ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; -} - -/*! - \brief ENET Rx function enable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_enable(void) -{ - ENET_MAC_CFG |= ENET_MAC_CFG_REN; - ENET_DMA_CTL |= ENET_DMA_CTL_SRE; -} - -/*! - \brief ENET Rx function disable (include MAC and DMA module) - \param[in] none - \param[out] none - \retval none -*/ -void enet_rx_disable(void) -{ - ENET_DMA_CTL &= ~ENET_DMA_CTL_SRE; - ENET_MAC_CFG &= ~ENET_MAC_CFG_REN; -} - -/*! - \brief put registers value into the application buffer - \param[in] type: register type which will be get, refer to enet_registers_type_enum, - only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH - \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT - \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL - \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR - \param[in] num: the number of registers that the user want to get - \param[out] preg: the application buffer pointer for storing the register value - \retval none -*/ -void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num) -{ - uint32_t offset = 0U, max = 0U, limit = 0U; - - offset = (uint32_t)type; - max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); - - /* prevent element in this array is out of range */ - if(max > limit){ - max = limit; - } - - for(; offset < max; offset++){ - /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); - preg++; - } -} - -/*! - \brief get the enet debug status from the debug register - \param[in] mac_debug: enet debug status - only one parameter can be selected which is shown as below - \arg ENET_MAC_RECEIVER_NOT_IDLE: MAC receiver is not in idle state - \arg ENET_RX_ASYNCHRONOUS_FIFO_STATE: Rx asynchronous FIFO status - \arg ENET_RXFIFO_WRITING: RxFIFO is doing write operation - \arg ENET_RXFIFO_READ_STATUS: RxFIFO read operation status - \arg ENET_RXFIFO_STATE: RxFIFO state - \arg ENET_MAC_TRANSMITTER_NOT_IDLE: MAC transmitter is not in idle state - \arg ENET_MAC_TRANSMITTER_STATUS: status of MAC transmitter - \arg ENET_PAUSE_CONDITION_STATUS: pause condition status - \arg ENET_TXFIFO_READ_STATUS: TxFIFO read operation status - \arg ENET_TXFIFO_WRITING: TxFIFO is doing write operation - \arg ENET_TXFIFO_NOT_EMPTY: TxFIFO is not empty - \arg ENET_TXFIFO_FULL: TxFIFO is full - \param[out] none - \retval value of the status users want to get -*/ -uint32_t enet_debug_status_get(uint32_t mac_debug) -{ - uint32_t temp_state = 0U; - - switch(mac_debug){ - case ENET_RX_ASYNCHRONOUS_FIFO_STATE: - temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); - break; - case ENET_RXFIFO_READ_STATUS: - temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); - break; - case ENET_RXFIFO_STATE: - temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); - break; - case ENET_MAC_TRANSMITTER_STATUS: - temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); - break; - case ENET_TXFIFO_READ_STATUS: - temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); - break; - default: - if(RESET != (ENET_MAC_DBG & mac_debug)){ - temp_state = 0x1U; - } - break; - } - return temp_state; -} - -/*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable, refer to enet_macaddress_enum - \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_enable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) |= ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief disable the MAC address filter - \param[in] mac_addr: select which MAC address will be disable, refer to enet_macaddress_enum - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter - \arg ENET_MAC_ADDRESS2: disable MAC address 2 filter - \arg ENET_MAC_ADDRESS3: disable MAC address 3 filter - \param[out] none - \retval none -*/ -void enet_address_filter_disable(enet_macaddress_enum mac_addr) -{ - REG32(ENET_ADDRH_BASE + mac_addr) &= ~ENET_MAC_ADDR1H_AFE; -} - -/*! - \brief configure the MAC address filter - \param[in] mac_addr: select which MAC address will be configured, refer to enet_macaddress_enum - only one parameter can be selected which is shown as below - \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter - \arg ENET_MAC_ADDRESS2: configure MAC address 2 filter - \arg ENET_MAC_ADDRESS3: configure MAC address 3 filter - \param[in] addr_mask: select which MAC address bytes will be mask - one or more parameters can be selected which are shown as below - \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits - \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits - \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits - \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits - \arg ENET_ADDRESS_MASK_BYTE5: mask ENET_MAC_ADDR1H [15:8] bits - \param[in] filter_type: select which MAC address filter type will be selected - only one parameter can be selected which is shown as below - \arg ENET_ADDRESS_FILTER_SA: The MAC address is used to compared with the SA field of the received frame - \arg ENET_ADDRESS_FILTER_DA: The MAC address is used to compared with the DA field of the received frame - \param[out] none - \retval none -*/ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) -{ - uint32_t reg; - - /* get the address filter register value which is to be configured */ - reg = REG32(ENET_ADDRH_BASE + mac_addr); - - /* clear and configure the address filter register */ - reg &= ~(ENET_MAC_ADDR1H_MB | ENET_MAC_ADDR1H_SAF); - reg |= (addr_mask | filter_type); - REG32(ENET_ADDRH_BASE + mac_addr) = reg; -} - -/*! - \brief PHY interface configuration (configure SMI clock and reset PHY chip) - \param[in] none - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_config(void) -{ - uint32_t ahbclk; - uint32_t reg; - uint16_t phy_value; - ErrStatus enet_state = ERROR; - - /* clear the previous MDC clock */ - reg = ENET_MAC_PHY_CTL; - reg &= ~ENET_MAC_PHY_CTL_CLR; - - /* get the HCLK frequency */ - ahbclk = rcu_clock_freq_get(CK_AHB); - - /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ - reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ - reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){ - reg |= ENET_MDC_HCLK_DIV42; - }else if(ENET_RANGE(ahbclk, 100000000U, 150000000U)){ - reg |= ENET_MDC_HCLK_DIV62; - }else if((ENET_RANGE(ahbclk, 150000000U, 200000000U))||(200000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV102; - }else{ - return enet_state; - } - ENET_MAC_PHY_CTL = reg; - - /* reset PHY */ - phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - /* PHY reset need some time */ - _ENET_DELAY_(ENET_DELAY_TO); - - /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; - } - - /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief write to / read from a PHY register - \param[in] direction: only one parameter can be selected which is shown as below, refer to enet_phydirection_enum - \arg ENET_PHY_WRITE: write data to phy register - \arg ENET_PHY_READ: read data from phy register - \param[in] phy_address: 0x0000 - 0x001F - \param[in] phy_reg: 0x0000 - 0x001F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction - \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) -{ - uint32_t reg, phy_flag; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* configure ENET_MAC_PHY_CTL with write/read operation */ - reg = ENET_MAC_PHY_CTL; - reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); - reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); - - /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ - ENET_MAC_PHY_DATA = *pvalue; - } - - /* do PHY write/read operation, and wait the operation complete */ - ENET_MAC_PHY_CTL = reg; - do{ - phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); - timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); - - /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ - enet_state = SUCCESS; - } - - /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ - *pvalue = (uint16_t)ENET_MAC_PHY_DATA; - } - - return enet_state; -} - -/*! - \brief enable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_enable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* enable the PHY loopback mode */ - temp_phy |= PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief disable the loopback function of PHY chip - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_phyloopback_disable(void) -{ - uint16_t temp_phy = 0U; - ErrStatus phy_state = ERROR; - - /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - /* disable the PHY loopback mode */ - temp_phy &= (uint16_t)~PHY_LOOPBACK; - - /* update the PHY control register with the new configuration */ - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); - - return phy_state; -} - -/*! - \brief enable ENET forward feature - \param[in] feature: the feature of ENET forward mode - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the function of the MAC strips the Pad/FCS field on received frames - \arg ENET_TYPEFRAME_CRC_DROP: the function that FCS field(last 4 bytes) of frame will be dropped before forwarding - \arg ENET_FORWARD_ERRFRAMES: the function that all frame received with error except runt error are forwarded to memory - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: the function that forwarding undersized good frames - \param[out] none - \retval none -*/ -void enet_forward_feature_enable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG |= mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); - ENET_DMA_CTL |= (mask >> 2); -} - -/*! - \brief disable ENET forward feature - \param[in] feature: the feature of ENET forward mode - one or more parameters can be selected which are shown as below - \arg ENET_AUTO_PADCRC_DROP: the automatic zero-quanta generation function - \arg ENET_TYPEFRAME_CRC_DROP: the flow control operation in the MAC - \arg ENET_FORWARD_ERRFRAMES: decoding function for the received pause frame and process it - \arg ENET_FORWARD_UNDERSZ_GOODFRAMES: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_forward_feature_disable(uint32_t feature) -{ - uint32_t mask; - - mask = (feature & (~(ENET_FORWARD_ERRFRAMES | ENET_FORWARD_UNDERSZ_GOODFRAMES))); - ENET_MAC_CFG &= ~mask; - - mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); - ENET_DMA_CTL &= ~(mask >> 2); -} - -/*! - \brief enable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_enable(uint32_t feature) -{ - ENET_MAC_FRMF |= feature; -} - -/*! - \brief disable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode - one or more parameters can be selected which are shown as below - \arg ENET_SRC_FILTER: filter source address function - \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function - \arg ENET_DEST_FILTER_INVERSE: inverse DA filtering result function - \arg ENET_MULTICAST_FILTER_PASS: pass all multicast frames function - \arg ENET_MULTICAST_FILTER_HASH_MODE: HASH multicast filter function - \arg ENET_UNICAST_FILTER_HASH_MODE: HASH unicast filter function - \arg ENET_FILTER_MODE_EITHER: HASH or perfect filter function - \param[out] none - \retval none -*/ -void enet_fliter_feature_disable(uint32_t feature) -{ - ENET_MAC_FRMF &= ~feature; -} - -/*! - \brief generate the pause frame, ENET will send pause frame after enable transmit flow control - this function only use in full-dulex mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_pauseframe_generate(void) -{ - ErrStatus enet_state =ERROR; - uint32_t temp = 0U; - - /* in full-duplex mode, must make sure this bit is 0 before writing register */ - temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ - ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; - enet_state = SUCCESS; - } - return enet_state; -} - -/*! - \brief configure the pause frame detect type - \param[in] detect: pause frame detect type - only one parameter can be selected which is shown as below - \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also - use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified - in IEEE802.3 can be detected - \param[out] none - \retval none -*/ -void enet_pauseframe_detect_config(uint32_t detect) -{ - ENET_MAC_FCTL &= ~ENET_MAC_FCTL_UPFDT; - ENET_MAC_FCTL |= detect; -} - -/*! - \brief configure the pause frame parameters - \param[in] pausetime: pause time in transmit pause control frame - \param[in] pause_threshold: the threshold of the pause timer for retransmitting frames automatically - this value must make sure to be less than configured pause time - only one parameter can be selected which is shown as below - \arg ENET_PAUSETIME_MINUS4: pause time minus 4 slot times - \arg ENET_PAUSETIME_MINUS28: pause time minus 28 slot times - \arg ENET_PAUSETIME_MINUS144: pause time minus 144 slot times - \arg ENET_PAUSETIME_MINUS256: pause time minus 256 slot times - \param[out] none - \retval none -*/ -void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) -{ - ENET_MAC_FCTL &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_PLTS); - ENET_MAC_FCTL |= (MAC_FCTL_PTM(pausetime) | pause_threshold); -} - -/*! - \brief configure the threshold of the flow control(deactive and active threshold) - \param[in] deactive: the threshold of the deactive flow control - this value should always be less than active flow control value - only one parameter can be selected which is shown as below - \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_DEACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_DEACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_DEACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_DEACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_DEACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[in] active: the threshold of the active flow control - only one parameter can be selected which is shown as below - \arg ENET_ACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes - \arg ENET_ACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes - \arg ENET_ACTIVE_THRESHOLD_768BYTES: threshold level is 768 bytes - \arg ENET_ACTIVE_THRESHOLD_1024BYTES: threshold level is 1024 bytes - \arg ENET_ACTIVE_THRESHOLD_1280BYTES: threshold level is 1280 bytes - \arg ENET_ACTIVE_THRESHOLD_1536BYTES: threshold level is 1536 bytes - \arg ENET_ACTIVE_THRESHOLD_1792BYTES: threshold level is 1792 bytes - \param[out] none - \retval none -*/ -void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) -{ - ENET_MAC_FCTH = ((deactive | active) >> 8); -} - -/*! - \brief enable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_enable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL |= feature; -} - -/*! - \brief disable ENET flow control feature - \param[in] feature: the feature of ENET flow control mode - one or more parameters can be selected which are shown as below - \arg ENET_ZERO_QUANTA_PAUSE: the automatic zero-quanta generation function - \arg ENET_TX_FLOWCONTROL: the flow control operation in the MAC - \arg ENET_RX_FLOWCONTROL: decoding function for the received pause frame and process it - \arg ENET_BACK_PRESSURE: back pressure operation in the MAC(only use in half-dulex mode) - \param[out] none - \retval none -*/ -void enet_flowcontrol_feature_disable(uint32_t feature) -{ - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ - ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; - } - feature &= ~ENET_ZERO_QUANTA_PAUSE; - ENET_MAC_FCTL &= ~feature; -} - -/*! - \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: dma transmit process - \arg ENET_DMA_RX: dma receive process - \param[out] none - \retval state of dma process, the value range shows below: - ENET_RX_STATE_STOPPED, ENET_RX_STATE_FETCHING, ENET_RX_STATE_WAITING, - ENET_RX_STATE_SUSPENDED, ENET_RX_STATE_CLOSING, ENET_RX_STATE_QUEUING, - ENET_TX_STATE_STOPPED, ENET_TX_STATE_FETCHING, ENET_TX_STATE_WAITING, - ENET_TX_STATE_READING, ENET_TX_STATE_SUSPENDED, ENET_TX_STATE_CLOSING -*/ -uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) -{ - uint32_t reval; - reval = (uint32_t)(ENET_DMA_STAT & (uint32_t)direction); - return reval; -} - -/*! - \brief poll the DMA transmission/reception enable by writing any value to the - ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA transmit process - \arg ENET_DMA_RX: DMA receive process - \param[out] none - \retval none -*/ -void enet_dmaprocess_resume(enet_dmadirection_enum direction) -{ - if(ENET_DMA_TX == direction){ - ENET_DMA_TPEN = 0U; - }else{ - ENET_DMA_RPEN = 0U; - } -} - -/*! - \brief check and recover the Rx process - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxprocess_check_recovery(void) -{ - uint32_t status; - - /* get DAV information of current RxDMA descriptor */ - status = dma_current_rxdesc->status; - status &= ENET_RDES0_DAV; - - /* if current descriptor is owned by DMA, but the descriptor address mismatches with - receive descriptor address pointer updated by RxDMA controller */ - if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; - } -} - -/*! - \brief flush the ENET transmit FIFO, and wait until the flush operation completes - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus enet_txfifo_flush(void) -{ - uint32_t flush_state; - uint32_t timeout = 0U; - ErrStatus enet_state = ERROR; - - /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; - /* wait until the flush operation completes */ - do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; - timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(RESET == flush_state){ - enet_state = SUCCESS; - } - - return enet_state; -} - -/*! - \brief get the transmit/receive address of current descriptor, or current buffer, or descriptor table - \param[in] addr_get: choose the address which users want to get, refer to enet_desc_reg_enum - only one parameter can be selected which is shown as below - \arg ENET_RX_DESC_TABLE: the start address of the receive descriptor table - \arg ENET_RX_CURRENT_DESC: the start descriptor address of the current receive descriptor read by - the RxDMA controller - \arg ENET_RX_CURRENT_BUFFER: the current receive buffer address being read by the RxDMA controller - \arg ENET_TX_DESC_TABLE: the start address of the transmit descriptor table - \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by - the TxDMA controller - \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none - \retval address value -*/ -uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) -{ - uint32_t reval = 0U; - - reval = REG32((ENET) +(uint32_t)addr_get); - return reval; -} - -/*! - \brief get the Tx or Rx descriptor information - \param[in] desc: the descriptor pointer which users want to get information - \param[in] info_get: the descriptor information type which is selected, refer to enet_descstate_enum - only one parameter can be selected which is shown as below - \arg RXDESC_BUFFER_1_SIZE: receive buffer 1 size - \arg RXDESC_BUFFER_2_SIZE: receive buffer 2 size - \arg RXDESC_FRAME_LENGTH: the byte length of the received frame that was transferred to the buffer - \arg TXDESC_COLLISION_COUNT: the number of collisions occurred before the frame was transmitted - \arg RXDESC_BUFFER_1_ADDR: the buffer1 address of the Rx frame - \arg TXDESC_BUFFER_1_ADDR: the buffer1 address of the Tx frame - \param[out] none - \retval descriptor information, if value is 0xFFFFFFFFU, means the false input parameter -*/ -uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get) -{ - uint32_t reval = 0xFFFFFFFFU; - - switch(info_get){ - case RXDESC_BUFFER_1_SIZE: - reval = GET_RDES1_RB1S(desc->control_buffer_size); - break; - case RXDESC_BUFFER_2_SIZE: - reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: - reval = GET_RDES0_FRML(desc->status); - if(reval > 4U){ - reval = reval - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ - reval = reval + 4U; - } - }else{ - reval = 0U; - } - - break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_COLLISION_COUNT: - reval = GET_TDES0_COCNT(desc->status); - break; - default: - break; - } - return reval; -} - -/*! - \brief get the number of missed frames during receiving - \param[in] none - \param[out] rxfifo_drop: pointer to the number of frames dropped by RxFIFO - \param[out] rxdma_drop: pointer to the number of frames missed by the RxDMA controller - \retval none -*/ -void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) -{ - uint32_t temp_counter = 0U; - - temp_counter = ENET_DMA_MFBOCNT; - *rxfifo_drop = GET_DMA_MFBOCNT_MSFA(temp_counter); - *rxdma_drop = GET_DMA_MFBOCNT_MSFC(temp_counter); -} - -/*! - \brief get the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to get flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor - only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred - \arg ENET_TDES0_UFE: underflow error - \arg ENET_TDES0_EXD: excessive deferral - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_ECO: excessive collision - \arg ENET_TDES0_LCO: late collision - \arg ENET_TDES0_NCA: no carrier - \arg ENET_TDES0_LCA: loss of carrier - \arg ENET_TDES0_IPPE: IP payload error - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_JT: jabber timeout - \arg ENET_TDES0_ES: error summary - \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error - \arg ENET_RDES0_EXSV: extended status valid - \arg ENET_RDES0_CERR: CRC error - \arg ENET_RDES0_DBERR: dribble bit error - \arg ENET_RDES0_RERR: receive error - \arg ENET_RDES0_RWDT: receive watchdog timeout - \arg ENET_RDES0_FRMT: frame type - \arg ENET_RDES0_LCO: late collision - \arg ENET_RDES0_IPHERR: IP frame header error - \arg ENET_RDES0_TSV: timestamp valid - \arg ENET_RDES0_LDES: last descriptor - \arg ENET_RDES0_FDES: first descriptor - \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error - \arg ENET_RDES0_LERR: length error - \arg ENET_RDES0_SAFF: SA filter fail - \arg ENET_RDES0_DERR: descriptor error - \arg ENET_RDES0_ERRS: error summary - \arg ENET_RDES0_DAFF: destination address filter fail - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - FlagStatus enet_flag = RESET; - - if ((uint32_t)RESET != (desc->status & desc_flag)){ - enet_flag = SET; - } - - return enet_flag; -} - -/*! - \brief set the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to set flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status |= desc_flag; -} - -/*! - \brief clear the bit flag of ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to clear flag - \param[in] desc_flag: the bit flag of ENET DMA descriptor - only one parameter can be selected which is shown as below - \arg ENET_TDES0_VFRM: VLAN frame - \arg ENET_TDES0_FRMF: frame flushed - \arg ENET_TDES0_TCHM: the second address chained mode - \arg ENET_TDES0_TERM: transmit end of ring mode - \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad - \arg ENET_TDES0_DCRC: disable CRC - \arg ENET_TDES0_FSG: first segment - \arg ENET_TDES0_LSG: last segment - \arg ENET_TDES0_INTC: interrupt on completion - \arg ENET_TDES0_DAV: DAV bit - \arg ENET_RDES0_DAV: descriptor available - \param[out] none - \retval none -*/ -void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) -{ - desc->status &= ~desc_flag; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set - \param[in] desc: the descriptor pointer which users want to configure - \param[out] none - \retval none -*/ -void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc) -{ - desc->control_buffer_size &= ~ENET_RDES1_DINTC; -} - -/*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time - \param[in] desc: the descriptor pointer which users want to configure - \param[in] delay_time: delay a time of 256*delay_time HCLK(0x00000000 - 0x000000FF) - \param[out] none - \retval none -*/ -void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time) -{ - desc->control_buffer_size |= ENET_RDES1_DINTC; - ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time); -} - -/*! - \brief drop current receive frame - \param[in] none - \param[out] none - \retval none -*/ -void enet_rxframe_drop(void) -{ - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - } - - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - } - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc++; - } - } - } -} - -/*! - \brief enable DMA feature - \param[in] feature: the feature of DMA mode - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_enable(uint32_t feature) -{ - ENET_DMA_CTL |= feature; -} - -/*! - \brief disable DMA feature - \param[in] feature: the feature of DMA mode - one or more parameters can be selected which are shown as below - \arg ENET_NO_FLUSH_RXFRAME: RxDMA does not flushes frames function - \arg ENET_SECONDFRAME_OPT: TxDMA controller operate on second frame function - \param[out] none - \retval none -*/ -void enet_dma_feature_disable(uint32_t feature) -{ - ENET_DMA_CTL &= ~feature; -} - -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE -/*! - \brief get the bit of extended status flag in ENET DMA descriptor - \param[in] desc: the descriptor pointer which users want to get the extended status flag - \param[in] desc_status: the extended status want to get - only one parameter can be selected which is shown as below - \arg ENET_RDES4_IPPLDT: IP frame payload type - \arg ENET_RDES4_IPHERR: IP frame header error - \arg ENET_RDES4_IPPLDERR: IP frame payload error - \arg ENET_RDES4_IPCKSB: IP frame checksum bypassed - \arg ENET_RDES4_IPF4: IP frame in version 4 - \arg ENET_RDES4_IPF6: IP frame in version 6 - \arg ENET_RDES4_PTPMT: PTP message type - \arg ENET_RDES4_PTPOEF: PTP on ethernet frame - \arg ENET_RDES4_PTPVF: PTP version format - \param[out] none - \retval value of extended status -*/ -uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) -{ - uint32_t reval = 0xFFFFFFFFU; - - switch (desc_status){ - case ENET_RDES4_IPPLDT: - reval = GET_RDES4_IPPLDT(desc->extended_status); - break; - case ENET_RDES4_PTPMT: - reval = GET_RDES4_PTPMT(desc->extended_status); - break; - default: - if ((uint32_t)RESET != (desc->extended_status & desc_status)){ - reval = 1U; - }else{ - reval = 0U; - } - } - - return reval; -} - -/*! - \brief configure descriptor to work in enhanced mode - \param[in] none - \param[out] none - \retval none -*/ -void enet_desc_select_enhanced_mode(void) -{ - ENET_DMA_BCTL |= ENET_DMA_BCTL_DFM; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced chain mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - - /* configuration each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; - } - } -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in enhanced ring mode with ptp function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[out] none - \retval none -*/ -void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc; - enet_descriptors_struct *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select ring mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* set buffer1 size */ - desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - } - - /* configure each descriptor */ - for(num=0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - } -} - -/*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] buffer: pointer to the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) -{ - uint32_t offset = 0U, size = 0U; - uint32_t timeout = 0U; - uint32_t rdes0_tsv_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); - } - }else{ - return ERROR; - } - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and - write to the RDES6 and RDES7 */ - do{ - rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); - timeout++; - }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_RDES0_TSV flag */ - dma_current_rxdesc->status &= ~ENET_RDES0_TSV; - /* get the timestamp value of the received frame */ - timestamp[0] = dma_current_rxdesc->timestamp_low; - timestamp[1] = dma_current_rxdesc->timestamp_high; - } - - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* Clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - } - } - - return SUCCESS; -} - -/*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode - \param[in] buffer: pointer on the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) -{ - uint32_t offset = 0; - uint32_t dma_tbu_flag, dma_tu_flag; - uint32_t tdes0_ttmss_flag; - uint32_t timeout = 0; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0; offset < length; offset++){ - (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* Clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->timestamp_low; - timestamp[1] = dma_current_txdesc->timestamp_high; - } - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - } - } - - return SUCCESS; -} - -#else - -/*! - \brief configure descriptor to work in normal mode - \param[in] none - \param[out] none - \retval none -*/ -void enet_desc_select_normal_mode(void) -{ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DFM; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal chain mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select chain mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive chained mode and set buffer1 size */ - desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* if is not the last descriptor */ - if(num < (count - 1U)){ - /* configure the next descriptor address */ - desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief initialize the DMA Tx/Rx descriptors's parameters in normal ring mode with PTP function - \param[in] direction: the descriptors which users want to init, refer to enet_dmadirection_enum - only one parameter can be selected which is shown as below - \arg ENET_DMA_TX: DMA Tx descriptors - \arg ENET_DMA_RX: DMA Rx descriptors - \param[in] desc_ptptab: pointer to the first descriptor address of PTP Rx descriptor table - \param[out] none - \retval none -*/ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) -{ - uint32_t num = 0U, count = 0U, maxsize = 0U; - uint32_t desc_status = 0U, desc_bufsize = 0U; - enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; - - /* configure descriptor skip length */ - ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; - ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - - /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ - /* save a copy of the DMA Tx descriptors */ - desc_tab = txdesc_tab; - buf = &tx_buff[0][0]; - count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - - /* select ring mode, and enable transmit timestamp function */ - desc_status = ENET_TDES0_TTSEN; - - /* configure DMA Tx descriptor table address register */ - ENET_DMA_TDTADDR = (uint32_t)desc_tab; - dma_current_txdesc = desc_tab; - dma_current_ptp_txdesc = desc_ptptab; - }else{ - /* if want to initialize DMA Rx descriptors */ - /* save a copy of the DMA Rx descriptors */ - desc_tab = rxdesc_tab; - buf = &rx_buff[0][0]; - count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - - /* enable receiving */ - desc_status = ENET_RDES0_DAV; - /* select receive ring mode and set buffer1 size */ - desc_bufsize = (uint32_t)ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ - ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; - } - - /* configure each descriptor */ - for(num = 0U; num < count; num++){ - /* get the pointer to the next descriptor of the descriptor table */ - desc = desc_tab + num; - - /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - - /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ - desc->status |= ENET_TDES0_TERM; - }else{ - /* configure receive end of ring mode */ - desc->control_buffer_size |= ENET_RDES1_RERM; - } - } - /* set desc_ptptab equal to desc_tab */ - (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; - (&desc_ptptab[num])->buffer2_next_desc_addr = desc->buffer2_next_desc_addr; - } - /* when it is the last ptp descriptor, preserve the first descriptor - address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; -} - -/*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode - \param[in] bufsize: the size of buffer which is the parameter in function - \param[out] buffer: pointer to the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[out] timestamp: pointer to the table which stores the timestamp high and low - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) -{ - uint32_t offset = 0U, size = 0U; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); - } - - }else{ - return ERROR; - } - } - /* copy timestamp value from Rx descriptor to application array */ - timestamp[0] = dma_current_rxdesc->buffer1_addr; - timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; - - dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; - dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_rxdesc ++; - } - } - - return SUCCESS; -} - -/*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode - \param[in] buffer: pointer on the application buffer - note -- if the input is NULL, user should copy data in application by himself - \param[in] length: the length of frame data to be transmitted - \param[out] timestamp: pointer to the table which stores the timestamp high and low - note -- if the input is NULL, timestamp is ignored - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) -{ - uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; - - /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); - } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; - } - - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->buffer1_addr; - timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; - } - dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; - dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_txdesc++; - } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; - } - } - return SUCCESS; -} - -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - -/*! - \brief wakeup frame filter register pointer reset - \param[in] none - \param[out] none - \retval none -*/ -void enet_wum_filter_register_pointer_reset(void) -{ - ENET_MAC_WUM |= ENET_MAC_WUM_WUFFRPR; -} - -/*! - \brief set the remote wakeup frame registers - \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) - \param[out] none - \retval none -*/ -void enet_wum_filter_config(uint32_t pdata[]) -{ - uint32_t num = 0U; - - /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ - ENET_MAC_RWFF = pdata[num]; - } -} - -/*! - \brief enable wakeup management features - \param[in] feature: the wake up type which is selected - one or more parameters can be selected which are shown as below - \arg ENET_WUM_POWER_DOWN: power down mode - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_enable(uint32_t feature) -{ - ENET_MAC_WUM |= feature; -} - -/*! - \brief disable wakeup management features - \param[in] feature: the wake up type which is selected - one or more parameters can be selected which are shown as below - \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception - \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception - \arg ENET_WUM_GLOBAL_UNICAST: any received unicast frame passed filter is considered to be a wakeup frame - \param[out] none - \retval none -*/ -void enet_wum_feature_disable(uint32_t feature) -{ - ENET_MAC_WUM &= (~feature); -} - -/*! - \brief reset the MAC statistics counters - \param[in] none - \param[out] none - \retval none -*/ -void enet_msc_counters_reset(void) -{ - /* reset all counters */ - ENET_MSC_CTL |= ENET_MSC_CTL_CTR; -} - -/*! - \brief enable the MAC statistics counter features - \param[in] feature: the feature of MAC statistics counter - one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_enable(uint32_t feature) -{ - ENET_MSC_CTL |= feature; -} - -/*! - \brief disable the MAC statistics counter features - \param[in] feature: the feature of MAC statistics counter - one or more parameters can be selected which are shown as below - \arg ENET_MSC_COUNTER_STOP_ROLLOVER: counter stop rollover - \arg ENET_MSC_RESET_ON_READ: reset on read - \arg ENET_MSC_COUNTERS_FREEZE: MSC counter freeze - \param[out] none - \retval none -*/ -void enet_msc_feature_disable(uint32_t feature) -{ - ENET_MSC_CTL &= (~feature); -} - -/*! - \brief configure MAC statistics counters preset mode - \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum - only one parameter can be selected which is shown as below - \arg ENET_MSC_PRESET_NONE: do not preset MSC counter - \arg ENET_MSC_PRESET_HALF: preset all MSC counters to almost-half(0x7FFF FFF0) value - \arg ENET_MSC_PRESET_FULL: preset all MSC counters to almost-full(0xFFFF FFF0) value - \param[out] none - \retval none -*/ -void enet_msc_counters_preset_config(enet_msc_preset_enum mode) -{ - ENET_MSC_CTL &= ENET_MSC_PRESET_MASK; - ENET_MSC_CTL |= (uint32_t)mode; -} - -/*! - \brief get MAC statistics counter - \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum - only one parameter can be selected which is shown as below - \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter - \arg ENET_MSC_TX_MSCCNT: MSC transmitted good frames after more than a single collision counter - \arg ENET_MSC_TX_TGFCNT: MSC transmitted good frames counter - \arg ENET_MSC_RX_RFCECNT: MSC received frames with CRC error counter - \arg ENET_MSC_RX_RFAECNT: MSC received frames with alignment error counter - \arg ENET_MSC_RX_RGUFCNT: MSC received good unicast frames counter - \param[out] none - \retval the MSC counter value -*/ -uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) -{ - uint32_t reval; - - reval = REG32((ENET + (uint32_t)counter)); - - return reval; -} - -/*! - \brief enable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot - \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame - \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame - \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame - \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame - \param[out] none - \retval none -*/ -void enet_ptp_feature_enable(uint32_t feature) -{ - ENET_PTP_TSCTL |= feature; -} - -/*! - \brief disable the PTP features - \param[in] feature: the feature of ENET PTP mode - one or more parameters can be selected which are shown as below - \arg ENET_RXTX_TIMESTAMP: timestamp function for transmit and receive frames - \arg ENET_PTP_TIMESTAMP_INT: timestamp interrupt trigger - \arg ENET_ALL_RX_TIMESTAMP: all received frames are taken snapshot - \arg ENET_NONTYPE_FRAME_SNAPSHOT: take snapshot when received non type frame - \arg ENET_IPV6_FRAME_SNAPSHOT: take snapshot for IPv6 frame - \arg ENET_IPV4_FRAME_SNAPSHOT: take snapshot for IPv4 frame - \arg ENET_PTP_FRAME_USE_MACADDRESS_FILTER: use MAC address1-3 to filter the PTP frame - \param[out] none - \retval none -*/ -void enet_ptp_feature_disable(uint32_t feature) -{ - ENET_PTP_TSCTL &= ~feature; -} - -/*! - \brief configure the PTP timestamp function - \param[in] func: the function of PTP timestamp - only one parameter can be selected which is shown as below - \arg ENET_CKNT_ORDINARY: type of ordinary clock node type for timestamp - \arg ENET_CKNT_BOUNDARY: type of boundary clock node type for timestamp - \arg ENET_CKNT_END_TO_END: type of end-to-end transparent clock node type for timestamp - \arg ENET_CKNT_PEER_TO_PEER: type of peer-to-peer transparent clock node type for timestamp - \arg ENET_PTP_ADDEND_UPDATE: addend register update - \arg ENET_PTP_SYSTIME_UPDATE: timestamp update - \arg ENET_PTP_SYSTIME_INIT: timestamp initialize - \arg ENET_PTP_FINEMODE: the system timestamp uses the fine method for updating - \arg ENET_PTP_COARSEMODE: the system timestamp uses the coarse method for updating - \arg ENET_SUBSECOND_DIGITAL_ROLLOVER: digital rollover mode - \arg ENET_SUBSECOND_BINARY_ROLLOVER: binary rollover mode - \arg ENET_SNOOPING_PTP_VERSION_2: version 2 - \arg ENET_SNOOPING_PTP_VERSION_1: version 1 - \arg ENET_EVENT_TYPE_MESSAGES_SNAPSHOT: only event type messages are taken snapshot - \arg ENET_ALL_TYPE_MESSAGES_SNAPSHOT: all type messages are taken snapshot except announce, - management and signaling message - \arg ENET_MASTER_NODE_MESSAGE_SNAPSHOT: snapshot is only take for master node message - \arg ENET_SLAVE_NODE_MESSAGE_SNAPSHOT: snapshot is only taken for slave node message - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) -{ - uint32_t temp_config = 0U, temp_state = 0U; - uint32_t timeout = 0U; - ErrStatus enet_state = SUCCESS; - - switch(func){ - case ENET_CKNT_ORDINARY: - case ENET_CKNT_BOUNDARY: - case ENET_CKNT_END_TO_END: - case ENET_CKNT_PEER_TO_PEER: - ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; - ENET_PTP_TSCTL |= (uint32_t)func; - break; - case ENET_PTP_ADDEND_UPDATE: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } - break; - case ENET_PTP_SYSTIME_UPDATE: - /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; - case ENET_PTP_SYSTIME_INIT: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; - default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; - } - break; - } - - return enet_state; -} - -/*! - \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time(0x00000000 - 0x000000FF) - \param[out] none - \retval none -*/ -void enet_ptp_subsecond_increment_config(uint32_t subsecond) -{ - ENET_PTP_SSINC = PTP_SSINC_STMSSI(subsecond); -} - -/*! - \brief adjusting the clock frequency only in fine update mode - \param[in] add: the value will be added to the accumulator register to achieve time synchronization - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_addend_config(uint32_t add) -{ - ENET_PTP_TSADDEND = add; -} - -/*! - \brief initialize or add/subtract to second of the system time - \param[in] sign: timestamp update positive or negative sign - only one parameter can be selected which is shown as below - \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time - \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time - \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time - with 0.46 ns accuracy if required accuracy is 20 ns - \param[out] none - \retval none -*/ -void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond) -{ - ENET_PTP_TSUH = second; - ENET_PTP_TSUL = sign | PTP_TSUL_TMSUSS(subsecond); -} - -/*! - \brief configure the expected target time - \param[in] second: the expected target second time - \param[in] nanosecond: the expected target nanosecond time (signed) - \param[out] none - \retval none -*/ -void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) -{ - ENET_PTP_ETH = second; - ENET_PTP_ETL = nanosecond; -} - -/*! - \brief get the current system time - \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains - parameters of PTP system time - members of the structure and the member values are shown as below: - second: 0x0 - 0xFFFF FFFF - subsecond: 0x0 - 0x7FFF FFFF - sign: ENET_PTP_TIME_POSITIVE, ENET_PTP_TIME_NEGATIVE - \retval none -*/ -void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) -{ - uint32_t temp_sec = 0U, temp_subs = 0U; - - /* get the value of sysytem time registers */ - temp_sec = (uint32_t)ENET_PTP_TSH; - temp_subs = (uint32_t)ENET_PTP_TSL; - - /* get sysytem time and construct the enet_ptp_systime_struct structure */ - systime_struct->second = temp_sec; - systime_struct->subsecond = GET_PTP_TSL_STMSS(temp_subs); - systime_struct->sign = GET_PTP_TSL_STS(temp_subs); -} - -/*! - \brief configure the PPS output frequency - \param[in] freq: PPS output frequency - only one parameter can be selected which is shown as below - \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency - \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency - \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency - \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency - \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency - \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency - \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency - \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency - \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency - \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency - \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency - \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency - \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency - \arg ENET_PPSOFC_8192HZ: PPS output 8192Hz frequency - \arg ENET_PPSOFC_16384HZ: PPS output 16384Hz frequency - \arg ENET_PPSOFC_32768HZ: PPS output 32768Hz frequency - \param[out] none - \retval none -*/ -void enet_ptp_pps_output_frequency_config(uint32_t freq) -{ - ENET_PTP_PPSCTL = freq; -} - -/*! - \brief reset the ENET initpara struct, call it before using enet_initpara_config() - \param[in] none - \param[out] none - \retval none -*/ -void enet_initpara_reset(void) -{ - enet_initpara.option_enable = 0U; - enet_initpara.forward_frame = 0U; - enet_initpara.dmabus_mode = 0U; - enet_initpara.dma_maxburst = 0U; - enet_initpara.dma_arbitration = 0U; - enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; - enet_initpara.vlan_config = 0U; - enet_initpara.flow_control = 0U; - enet_initpara.hashtable_high = 0U; - enet_initpara.hashtable_low = 0U; - enet_initpara.framesfilter_mode = 0U; - enet_initpara.halfduplex_param = 0U; - enet_initpara.timer_config = 0U; - enet_initpara.interframegap = 0U; -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() - \param[in] none - \param[out] none - \retval none -*/ -static void enet_default_init(void) -{ - uint32_t reg_value = 0U; - - /* MAC */ - /* configure ENET_MAC_CFG register */ - reg_value = ENET_MAC_CFG; - reg_value &= MAC_CFG_MASK; - reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_TYPEFRAME_CRC_DROP_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; - ENET_MAC_CFG = reg_value; - - /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; - - /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ - ENET_MAC_HLH = 0x0U; - - ENET_MAC_HLL = 0x0U; - - /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ - reg_value = ENET_MAC_FCTL; - reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; - ENET_MAC_FCTL = reg_value; - - ENET_MAC_FCTH = ENET_DEACTIVE_THRESHOLD_512BYTES |ENET_ACTIVE_THRESHOLD_1536BYTES; - - /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); - - /* DMA */ - /* configure ENET_DMA_CTL register */ - reg_value = ENET_DMA_CTL; - reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_FORWARD_ERRFRAMES_DISABLE |ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE \ - |ENET_SECONDFRAME_OPT_DISABLE; - ENET_DMA_CTL = reg_value; - - /* configure ENET_DMA_BCTL register */ - reg_value = ENET_DMA_BCTL; - reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ - |ENET_NORMAL_DESCRIPTOR; - ENET_DMA_BCTL = reg_value; -} - -#ifndef USE_DELAY -/*! - \brief insert a delay time - \param[in] ncount: specifies the delay time length - \param[out] none - \param[out] none -*/ -static void enet_delay(uint32_t ncount) -{ - __IO uint32_t delay_time = 0U; - - for(delay_time = ncount; delay_time != 0U; delay_time--){ - } -} -#endif /* USE_DELAY */ diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c deleted file mode 100644 index e225258eb5..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c +++ /dev/null @@ -1,1237 +0,0 @@ -/*! - \file gd32f4xx_exmc.c - \brief EXMC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_exmc.h" - -/* EXMC bank0 register reset value */ -#define BANK0_SNCTL_RESET ((uint32_t)0x000030DAU) -#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) -#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU) - -/* EXMC bank1/2 register reset mask */ -#define BANK1_2_NPCTL_RESET ((uint32_t)0x00000008U) -#define BANK1_2_NPINTEN_RESET ((uint32_t)0x00000042U) -#define BANK1_2_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) -#define BANK1_2_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) - -/* EXMC bank3 register reset mask */ -#define BANK3_NPCTL_RESET ((uint32_t)0x00000008U) -#define BANK3_NPINTEN_RESET ((uint32_t)0x00000040U) -#define BANK3_NPCTCFG_RESET ((uint32_t)0xFFFFFFFFU) -#define BANK3_NPATCFG_RESET ((uint32_t)0xFFFFFFFFU) -#define BANK3_PIOTCFG3_RESET ((uint32_t)0xFFFFFFFFU) - -/* EXMC SDRAM device register reset mask */ -#define SDRAM_DEVICE_SDCTL_RESET ((uint32_t)0x000002D0U) -#define SDRAM_DEVICE_SDTCFG_RESET ((uint32_t)0x0FFFFFFFU) -#define SDRAM_DEVICE_SDCMD_RESET ((uint32_t)0x00000000U) -#define SDRAM_DEVICE_SDARI_RESET ((uint32_t)0x00000000U) -#define SDRAM_DEVICE_SDSTAT_RESET ((uint32_t)0x00000000U) -#define SDRAM_DEVICE_SDRSCTL_RESET ((uint32_t)0x00000000U) - -/* EXMC bank0 SQPI-PSRAM register reset mask */ -#define BANK0_SQPI_SINIT_RESET ((uint32_t)0x18010000U) -#define BANK0_SQPI_SRCMD_RESET ((uint32_t)0x00000000U) -#define BANK0_SQPI_SWCMD_RESET ((uint32_t)0x00000000U) -#define BANK0_SQPI_SIDL_RESET ((uint32_t)0x00000000U) -#define BANK0_SQPI_SIDH_RESET ((uint32_t)0x00000000U) - -/* EXMC register bit offset */ -#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) -#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U) -#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U) -#define SNCTL_WREN_OFFSET ((uint32_t)12U) -#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) -#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U) -#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) - -#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) -#define SNTCFG_DSET_OFFSET ((uint32_t)8U) -#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) - -#define NPCTL_NDWTEN_OFFSET ((uint32_t)1U) -#define NPCTL_ECCEN_OFFSET ((uint32_t)6U) - -#define NPCTCFG_COMWAIT_OFFSET ((uint32_t)8U) -#define NPCTCFG_COMHLD_OFFSET ((uint32_t)16U) -#define NPCTCFG_COMHIZ_OFFSET ((uint32_t)24U) - -#define NPATCFG_ATTWAIT_OFFSET ((uint32_t)8U) -#define NPATCFG_ATTHLD_OFFSET ((uint32_t)16U) -#define NPATCFG_ATTHIZ_OFFSET ((uint32_t)24U) - -#define PIOTCFG_IOWAIT_OFFSET ((uint32_t)8U) -#define PIOTCFG_IOHLD_OFFSET ((uint32_t)16U) -#define PIOTCFG_IOHIZ_OFFSET ((uint32_t)24U) - -#define SDCTL_WPEN_OFFSET ((uint32_t)9U) -#define SDCTL_BRSTRD_OFFSET ((uint32_t)12U) - -#define SDTCFG_XSRD_OFFSET ((uint32_t)4U) -#define SDTCFG_RASD_OFFSET ((uint32_t)8U) -#define SDTCFG_ARFD_OFFSET ((uint32_t)12U) -#define SDTCFG_WRD_OFFSET ((uint32_t)16U) -#define SDTCFG_RPD_OFFSET ((uint32_t)20U) -#define SDTCFG_RCD_OFFSET ((uint32_t)24U) - -#define SDCMD_NARF_OFFSET ((uint32_t)5U) -#define SDCMD_MRC_OFFSET ((uint32_t)9U) - -#define SDARI_ARINTV_OFFSET ((uint32_t)1U) - -#define SDRSCTL_SSCR_OFFSET ((uint32_t)1U) -#define SDRSCTL_SDSC_OFFSET ((uint32_t)4U) - -#define SDSTAT_STA0_OFFSET ((uint32_t)1U) -#define SDSTAT_STA1_OFFSET ((uint32_t)3U) - -#define SRCMD_RWAITCYCLE_OFFSET ((uint32_t)16U) -#define SWCMD_WWAITCYCLE_OFFSET ((uint32_t)16U) - -#define INTEN_INTS_OFFSET ((uint32_t)3U) - -/*! - \brief deinitialize EXMC NOR/SRAM region - \param[in] exmc_norsram_region: select the region of bank0 - only one parameter can be selected which is shown as below: - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_deinit(uint32_t exmc_norsram_region) -{ - /* reset the registers */ - EXMC_SNCTL(exmc_norsram_region) = BANK0_SNCTL_RESET; - EXMC_SNTCFG(exmc_norsram_region) = BANK0_SNTCFG_RESET; - EXMC_SNWTCFG(exmc_norsram_region) = BANK0_SNWTCFG_RESET; -} - -/*! - \brief initialize exmc_norsram_parameter_struct with the default values - \param[in] none - \param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - /* configure the structure with default values */ - exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; - exmc_norsram_init_struct->address_data_mux = ENABLE; - exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; - exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_8B; - exmc_norsram_init_struct->burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - exmc_norsram_init_struct->wrap_burst_mode = DISABLE; - exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE; - exmc_norsram_init_struct->memory_write = ENABLE; - exmc_norsram_init_struct->nwait_signal = ENABLE; - exmc_norsram_init_struct->extended_mode = DISABLE; - exmc_norsram_init_struct->asyn_wait = DISABLE; - exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE; - - /* configure read/write timing */ - exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK; - exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK; - exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; - - /* write timing configure, when extended mode is used */ - exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->write_timing->bus_latency = 0xFU; - exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A; -} - -/*! - \brief initialize EXMC NOR/SRAM region - \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - norsram_region: EXMC_BANK0_NORSRAM_REGIONx, x=0..3 - write_mode: EXMC_ASYN_WRITE, EXMC_SYN_WRITE - extended_mode: ENABLE or DISABLE - asyn_wait: ENABLE or DISABLE - nwait_signal: ENABLE or DISABLE - memory_write: ENABLE or DISABLE - nwait_config: EXMC_NWAIT_CONFIG_BEFORE, EXMC_NWAIT_CONFIG_DURING - wrap_burst_mode: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW, EXMC_NWAIT_POLARITY_HIGH - burst_mode: ENABLE or DISABLE - databus_width: EXMC_NOR_DATABUS_WIDTH_8B, EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM, EXMC_MEMORY_TYPE_PSRAM, EXMC_MEMORY_TYPE_NOR - address_data_mux: ENABLE or DISABLE - read_write_timing: struct exmc_norsram_timing_parameter_struct set the time - asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D - syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 - syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 - bus_latency: 0x0U~0xFU - asyn_data_setuptime: 0x01U~0xFFU - asyn_address_holdtime: 0x1U~0xFU - asyn_address_setuptime: 0x0U~0xFU - write_timing: struct exmc_norsram_timing_parameter_struct set the time - asyn_access_mode: EXMC_ACCESS_MODE_A, EXMC_ACCESS_MODE_B, EXMC_ACCESS_MODE_C, EXMC_ACCESS_MODE_D - syn_data_latency: EXMC_DATALAT_x_CLK, x=2..17 - syn_clk_division: EXMC_SYN_CLOCK_RATIO_x_CLK, x=2..16 - bus_latency: 0x0U~0xFU - asyn_data_setuptime: 0x01U~0xFFU - asyn_address_holdtime: 0x1U~0xFU - asyn_address_setuptime: 0x0U~0xFU - \param[out] none - \retval none -*/ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - uint32_t snctl = 0x00000000U,sntcfg = 0x00000000U,snwtcfg = 0x00000000U; - - /* get the register value */ - snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); - - /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN | - EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG | EXMC_SNCTL_WREN | - EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_SYNCWR | - EXMC_SNCTL_NRMUX )); - - snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - (exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) | - exmc_norsram_init_struct->nwait_config | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) | - exmc_norsram_init_struct->write_mode; - - sntcfg = (uint32_t)exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->read_write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->read_write_timing->syn_clk_division | - exmc_norsram_init_struct->read_write_timing->syn_data_latency | - exmc_norsram_init_struct->read_write_timing->asyn_access_mode; - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ - snctl |= (uint32_t)EXMC_SNCTL_NREN; - } - - /* extended mode configure */ - if(ENABLE == exmc_norsram_init_struct->extended_mode){ - snwtcfg = (uint32_t)exmc_norsram_init_struct->write_timing->asyn_address_setuptime | - (exmc_norsram_init_struct->write_timing->asyn_address_holdtime << SNTCFG_AHLD_OFFSET )| - (exmc_norsram_init_struct->write_timing->asyn_data_setuptime << SNTCFG_DSET_OFFSET) | - (exmc_norsram_init_struct->write_timing->bus_latency << SNTCFG_BUSLAT_OFFSET) | - exmc_norsram_init_struct->write_timing->asyn_access_mode; - }else{ - snwtcfg = BANK0_SNWTCFG_RESET; - } - - /* configure the registers */ - EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; - EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; - EXMC_SNWTCFG(exmc_norsram_init_struct->norsram_region) = snwtcfg; -} - -/*! - \brief enable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_enable(uint32_t exmc_norsram_region) -{ - EXMC_SNCTL(exmc_norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief disable EXMC NOR/PSRAM bank region - \param[in] exmc_norsram_region: specifie the region of NOR/PSRAM Bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[out] none - \retval none -*/ -void exmc_norsram_disable(uint32_t exmc_norsram_region) -{ - EXMC_SNCTL(exmc_norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief deinitialize EXMC NAND bank - \param[in] exmc_nand_bank: select the bank of NAND - only one parameter can be selected which is shown as below: - \arg EXMC_BANKx_NAND(x=1..2) - \param[out] none - \retval none -*/ -void exmc_nand_deinit(uint32_t exmc_nand_bank) -{ - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND */ - EXMC_NPCTL(exmc_nand_bank) = BANK1_2_NPCTL_RESET; - EXMC_NPINTEN(exmc_nand_bank) = BANK1_2_NPINTEN_RESET; - EXMC_NPCTCFG(exmc_nand_bank) = BANK1_2_NPCTCFG_RESET; - EXMC_NPATCFG(exmc_nand_bank) = BANK1_2_NPATCFG_RESET; -} - -/*! - \brief initialize exmc_norsram_parameter_struct with the default values - \param[in] none - \param[out] the initialized struct exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - /* configure the structure with default values */ - exmc_nand_init_struct->nand_bank = EXMC_BANK1_NAND; - exmc_nand_init_struct->wait_feature = DISABLE; - exmc_nand_init_struct->databus_width = EXMC_NAND_DATABUS_WIDTH_8B; - exmc_nand_init_struct->ecc_logic = DISABLE; - exmc_nand_init_struct->ecc_size = EXMC_ECC_SIZE_256BYTES; - exmc_nand_init_struct->ctr_latency = 0x0U; - exmc_nand_init_struct->atr_latency = 0x0U; - exmc_nand_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_nand_init_struct->common_space_timing->waittime = 0xFCU; - exmc_nand_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_nand_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_nand_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief initialize EXMC NAND bank - \param[in] exmc_nand_parameter_struct: configure the EXMC NAND parameter - nand_bank: EXMC_BANK1_NAND,EXMC_BANK2_NAND - ecc_size: EXMC_ECC_SIZE_xBYTES,x=256,512,1024,2048,4096 - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - ecc_logic: ENABLE or DISABLE - databus_width: EXMC_NAND_DATABUS_WIDTH_8B,EXMC_NAND_DATABUS_WIDTH_16B - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - databus_hiztime: 0x01U~0xFFU - holdtime: 0x01U~0xFEU - waittime: 0x02U~0xFFU - setuptime: 0x01U~0xFFU - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - databus_hiztime: 0x00U~0xFEU - holdtime: 0x01U~0xFEU - waittime: 0x02U~0xFFU - setuptime: 0x01U~0xFFU - \param[out] none - \retval none -*/ -void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct) -{ - uint32_t npctl = 0x00000000U, npctcfg = 0x00000000U, npatcfg = 0x00000000U; - - npctl = (uint32_t)(exmc_nand_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET)| - EXMC_NPCTL_NDTP | - exmc_nand_init_struct->databus_width | - (exmc_nand_init_struct->ecc_logic << NPCTL_ECCEN_OFFSET)| - exmc_nand_init_struct->ecc_size | - exmc_nand_init_struct->ctr_latency | - exmc_nand_init_struct->atr_latency; - - npctcfg = (uint32_t)((exmc_nand_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_nand_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_nand_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_nand_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - npatcfg = (uint32_t)((exmc_nand_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_nand_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_nand_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - ((exmc_nand_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ ); - - /* EXMC_BANK1_NAND or EXMC_BANK2_NAND initialize */ - EXMC_NPCTL(exmc_nand_init_struct->nand_bank) = npctl; - EXMC_NPCTCFG(exmc_nand_init_struct->nand_bank) = npctcfg; - EXMC_NPATCFG(exmc_nand_init_struct->nand_bank) = npatcfg; -} - -/*! - \brief enable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_enable(uint32_t exmc_nand_bank) -{ - EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable NAND bank - \param[in] exmc_nand_bank: specifie the NAND bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval none -*/ -void exmc_nand_disable(uint32_t exmc_nand_bank) -{ - EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_NDBKEN; -} - -/*! - \brief deinitialize EXMC PC card bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_deinit(void) -{ - /* EXMC_BANK3_PCCARD */ - EXMC_NPCTL3 = BANK3_NPCTL_RESET; - EXMC_NPINTEN3 = BANK3_NPINTEN_RESET; - EXMC_NPCTCFG3 = BANK3_NPCTCFG_RESET; - EXMC_NPATCFG3 = BANK3_NPATCFG_RESET; - EXMC_PIOTCFG3 = BANK3_PIOTCFG3_RESET; -} - -/*! - \brief initialize exmc_pccard_parameter_struct with the default values - \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer - \retval none -*/ -void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the structure with default values */ - exmc_pccard_init_struct->wait_feature = DISABLE; - exmc_pccard_init_struct->ctr_latency = 0x0U; - exmc_pccard_init_struct->atr_latency = 0x0U; - exmc_pccard_init_struct->common_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->common_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->attribute_space_timing->databus_hiztime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->setuptime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->waittime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->holdtime = 0xFCU; - exmc_pccard_init_struct->io_space_timing->databus_hiztime = 0xFCU; -} - -/*! - \brief initialize EXMC PC card bank - \param[in] exmc_pccard_parameter_struct: configure the EXMC NAND parameter - atr_latency: EXMC_ALE_RE_DELAY_x_HCLK,x=1..16 - ctr_latency: EXMC_CLE_RE_DELAY_x_HCLK,x=1..16 - wait_feature: ENABLE or DISABLE - common_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - databus_hiztime: 0x01U~0xFFU - holdtime: 0x01U~0xFEU - waittime: 0x02U~0xFFU - setuptime: 0x01U~0xFFU - attribute_space_timing: struct exmc_nand_pccard_timing_parameter_struct set the time - databus_hiztime: 0x00U~0xFEU - holdtime: 0x01U~0xFEU - waittime: 0x02U~0xFFU - setuptime: 0x01U~0xFFU - io_space_timing: exmc_nand_pccard_timing_parameter_struct set the time - databus_hiztime: 0x00U~0xFFU - holdtime: 0x01U~0xFFU - waittime: 0x02U~0x100U - setuptime: 0x01U~0x100U - \param[out] none - \retval none -*/ -void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct) -{ - /* configure the EXMC bank3 PC card control register */ - EXMC_NPCTL3 = (uint32_t)(exmc_pccard_init_struct->wait_feature << NPCTL_NDWTEN_OFFSET) | - EXMC_NAND_DATABUS_WIDTH_16B | - exmc_pccard_init_struct->ctr_latency | - exmc_pccard_init_struct->atr_latency ; - - /* configure the EXMC bank3 PC card common space timing configuration register */ - EXMC_NPCTCFG3 = (uint32_t)((exmc_pccard_init_struct->common_space_timing->setuptime - 1U) & EXMC_NPCTCFG_COMSET ) | - (((exmc_pccard_init_struct->common_space_timing->waittime - 1U) << NPCTCFG_COMWAIT_OFFSET) & EXMC_NPCTCFG_COMWAIT ) | - ((exmc_pccard_init_struct->common_space_timing->holdtime << NPCTCFG_COMHLD_OFFSET) & EXMC_NPCTCFG_COMHLD ) | - (((exmc_pccard_init_struct->common_space_timing->databus_hiztime - 1U) << NPCTCFG_COMHIZ_OFFSET) & EXMC_NPCTCFG_COMHIZ ); - - /* configure the EXMC bank3 PC card attribute space timing configuration register */ - EXMC_NPATCFG3 = (uint32_t)((exmc_pccard_init_struct->attribute_space_timing->setuptime - 1U) & EXMC_NPATCFG_ATTSET ) | - (((exmc_pccard_init_struct->attribute_space_timing->waittime - 1U) << NPATCFG_ATTWAIT_OFFSET) & EXMC_NPATCFG_ATTWAIT ) | - ((exmc_pccard_init_struct->attribute_space_timing->holdtime << NPATCFG_ATTHLD_OFFSET) & EXMC_NPATCFG_ATTHLD ) | - ((exmc_pccard_init_struct->attribute_space_timing->databus_hiztime << NPATCFG_ATTHIZ_OFFSET) & EXMC_NPATCFG_ATTHIZ); - - /* configure the EXMC bank3 PC card io space timing configuration register */ - EXMC_PIOTCFG3 = (uint32_t)((exmc_pccard_init_struct->io_space_timing->setuptime - 1U) & EXMC_PIOTCFG3_IOSET ) | - (((exmc_pccard_init_struct->io_space_timing->waittime - 1U) << PIOTCFG_IOWAIT_OFFSET) & EXMC_PIOTCFG3_IOWAIT ) | - ((exmc_pccard_init_struct->io_space_timing->holdtime << PIOTCFG_IOHLD_OFFSET) & EXMC_PIOTCFG3_IOHLD ) | - ((exmc_pccard_init_struct->io_space_timing->databus_hiztime << PIOTCFG_IOHIZ_OFFSET) & EXMC_PIOTCFG3_IOHIZ ); -} - -/*! - \brief enable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_enable(void) -{ - EXMC_NPCTL3 |= EXMC_NPCTL_NDBKEN; -} - -/*! - \brief disable PC Card Bank - \param[in] none - \param[out] none - \retval none -*/ -void exmc_pccard_disable(void) -{ - EXMC_NPCTL3 &= ~EXMC_NPCTL_NDBKEN; -} - -/*! - \brief deinitialize EXMC SDRAM device - \param[in] exmc_sdram_device: select the SRAM device - only one parameter can be selected which is shown as below: - \arg EXMC_SDRAM_DEVICEx(x=0, 1) - \param[in] none - \param[out] none - \retval none -*/ -void exmc_sdram_deinit(uint32_t exmc_sdram_device) -{ - /* reset SDRAM registers */ - EXMC_SDCTL(exmc_sdram_device) = SDRAM_DEVICE_SDCTL_RESET; - EXMC_SDTCFG(exmc_sdram_device) = SDRAM_DEVICE_SDTCFG_RESET; - EXMC_SDCMD = SDRAM_DEVICE_SDCMD_RESET; - EXMC_SDARI = SDRAM_DEVICE_SDARI_RESET; - EXMC_SDRSCTL = SDRAM_DEVICE_SDRSCTL_RESET; -} - -/*! - \brief initialize exmc_sdram_parameter_struct with the default values - \param[in] none - \param[out] the initialized struct exmc_pccard_parameter_struct pointer - \retval none -*/ -void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) -{ - /* configure the structure with default values */ - exmc_sdram_init_struct->sdram_device = EXMC_SDRAM_DEVICE0; - exmc_sdram_init_struct->column_address_width = EXMC_SDRAM_COW_ADDRESS_8; - exmc_sdram_init_struct->row_address_width = EXMC_SDRAM_ROW_ADDRESS_11; - exmc_sdram_init_struct->data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; - exmc_sdram_init_struct->internal_bank_number = EXMC_SDRAM_4_INTER_BANK; - exmc_sdram_init_struct->cas_latency = EXMC_CAS_LATENCY_1_SDCLK; - exmc_sdram_init_struct->write_protection = ENABLE; - exmc_sdram_init_struct->sdclock_config = EXMC_SDCLK_DISABLE; - exmc_sdram_init_struct->brust_read_switch = DISABLE; - exmc_sdram_init_struct->pipeline_read_delay = EXMC_PIPELINE_DELAY_0_HCLK; - - exmc_sdram_init_struct->timing->load_mode_register_delay = 16U; - exmc_sdram_init_struct->timing->exit_selfrefresh_delay = 16U; - exmc_sdram_init_struct->timing->row_address_select_delay = 16U; - exmc_sdram_init_struct->timing->auto_refresh_delay = 16U; - exmc_sdram_init_struct->timing->write_recovery_delay = 16U; - exmc_sdram_init_struct->timing->row_precharge_delay = 16U; - exmc_sdram_init_struct->timing->row_to_column_delay = 16U; -} - -/*! - \brief initialize EXMC SDRAM device - \param[in] exmc_sdram_parameter_struct: configure the EXMC SDRAM parameter - sdram_device: EXMC_SDRAM_DEVICE0,EXMC_SDRAM_DEVICE1 - pipeline_read_delay: EXMC_PIPELINE_DELAY_x_HCLK,x=0..2 - brust_read_switch: ENABLE or DISABLE - sdclock_config: EXMC_SDCLK_DISABLE,EXMC_SDCLK_PERIODS_2_HCLK,EXMC_SDCLK_PERIODS_3_HCLK - write_protection: ENABLE or DISABLE - cas_latency: EXMC_CAS_LATENCY_x_SDCLK,x=1..3 - internal_bank_number: EXMC_SDRAM_2_INTER_BANK,EXMC_SDRAM_4_INTER_BANK - data_width: EXMC_SDRAM_DATABUS_WIDTH_8B,EXMC_SDRAM_DATABUS_WIDTH_16B,EXMC_SDRAM_DATABUS_WIDTH_32B - row_address_width: EXMC_SDRAM_ROW_ADDRESS_x,x=11..13 - column_address_width: EXMC_SDRAM_COW_ADDRESS_x,x=8..11 - timing: exmc_sdram_timing_parameter_struct set the time - row_to_column_delay: 1U~16U - row_precharge_delay: 1U~16U - write_recovery_delay: 1U~16U - auto_refresh_delay: 1U~16U - row_address_select_delay: 1U~16U - exit_selfrefresh_delay: 1U~16U - load_mode_register_delay: 1U~16U - \param[out] none - \retval none -*/ -void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct) -{ - uint32_t sdctl0, sdctl1, sdtcfg0, sdtcfg1; - - /* configuration EXMC_SDCTL0 or EXMC_SDCTL1 */ - if(EXMC_SDRAM_DEVICE0 == exmc_sdram_init_struct->sdram_device){ - /* configuration EXMC_SDCTL0 */ - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - (exmc_sdram_init_struct->write_protection << SDCTL_WPEN_OFFSET)| - exmc_sdram_init_struct->sdclock_config | - (exmc_sdram_init_struct->brust_read_switch << SDCTL_BRSTRD_OFFSET)| - exmc_sdram_init_struct->pipeline_read_delay; - - /* configuration EXMC_SDTCFG0 */ - EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); - }else{ - /* configuration EXMC_SDCTL0 and EXMC_SDCTL1 */ - /* some bits in the EXMC_SDCTL1 register are reserved */ - sdctl0 = EXMC_SDCTL(EXMC_SDRAM_DEVICE0) & (~( EXMC_SDCTL_PIPED | EXMC_SDCTL_BRSTRD | EXMC_SDCTL_SDCLK )); - - sdctl0 |= (uint32_t)exmc_sdram_init_struct->sdclock_config | - exmc_sdram_init_struct->brust_read_switch | - exmc_sdram_init_struct->pipeline_read_delay; - - sdctl1 = (uint32_t)exmc_sdram_init_struct->column_address_width | - exmc_sdram_init_struct->row_address_width | - exmc_sdram_init_struct->data_width | - exmc_sdram_init_struct->internal_bank_number | - exmc_sdram_init_struct->cas_latency | - exmc_sdram_init_struct->write_protection ; - - EXMC_SDCTL(EXMC_SDRAM_DEVICE0) = sdctl0; - EXMC_SDCTL(EXMC_SDRAM_DEVICE1) = sdctl1; - - /* configuration EXMC_SDTCFG0 and EXMC_SDTCFG1 */ - /* some bits in the EXMC_SDTCFG1 register are reserved */ - sdtcfg0 = EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) & (~(EXMC_SDTCFG_RPD | EXMC_SDTCFG_WRD | EXMC_SDTCFG_ARFD)); - - sdtcfg0 |= (uint32_t)(((exmc_sdram_init_struct->timing->auto_refresh_delay)-1U) << SDTCFG_ARFD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_precharge_delay)-1U) << SDTCFG_RPD_OFFSET) | - (((exmc_sdram_init_struct->timing->write_recovery_delay)-1U) << SDTCFG_WRD_OFFSET); - - sdtcfg1 = (uint32_t)((exmc_sdram_init_struct->timing->load_mode_register_delay)-1U) | - (((exmc_sdram_init_struct->timing->exit_selfrefresh_delay)-1U) << SDTCFG_XSRD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_address_select_delay)-1U) << SDTCFG_RASD_OFFSET) | - (((exmc_sdram_init_struct->timing->row_to_column_delay)-1U) << SDTCFG_RCD_OFFSET); - - EXMC_SDTCFG(EXMC_SDRAM_DEVICE0) = sdtcfg0; - EXMC_SDTCFG(EXMC_SDRAM_DEVICE1) = sdtcfg1; - } -} - -/*! - \brief deinitialize exmc SQPIPSRAM - \param[in] none - \param[out] none - \retval none -*/ -void exmc_sqpipsram_deinit(void) -{ - /* reset the registers */ - EXMC_SINIT = BANK0_SQPI_SINIT_RESET; - EXMC_SRCMD = BANK0_SQPI_SRCMD_RESET; - EXMC_SWCMD = BANK0_SQPI_SWCMD_RESET; - EXMC_SIDL = BANK0_SQPI_SIDL_RESET; - EXMC_SIDH = BANK0_SQPI_SIDH_RESET; -} - -/*! - \brief initialize exmc_sqpipsram_parameter_struct with the default values - \param[in] the struct exmc_sqpipsram_parameter_struct pointer - \param[out] none - \retval none -*/ -void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) -{ - /* configure the structure with default values */ - exmc_sqpipsram_init_struct->sample_polarity = EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE; - exmc_sqpipsram_init_struct->id_length = EXMC_SQPIPSRAM_ID_LENGTH_64B; - exmc_sqpipsram_init_struct->address_bits = EXMC_SQPIPSRAM_ADDR_LENGTH_24B; - exmc_sqpipsram_init_struct->command_bits = EXMC_SQPIPSRAM_COMMAND_LENGTH_8B; -} - -/*! - \brief initialize EXMC SQPIPSRAM - \param[in] exmc_sqpipsram_parameter_struct: configure the EXMC SQPIPSRAM parameter - sample_polarity: EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE,EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE - id_length: EXMC_SQPIPSRAM_ID_LENGTH_xB,x=8,16,32,64 - address_bits: EXMC_SQPIPSRAM_ADDR_LENGTH_xB,x=1..26 - command_bits: EXMC_SQPIPSRAM_COMMAND_LENGTH_xB,x=4,8,16 - \param[out] none - \retval none -*/ -void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct) -{ - /* initialize SQPI controller */ - EXMC_SINIT = (uint32_t)exmc_sqpipsram_init_struct->sample_polarity | - exmc_sqpipsram_init_struct->id_length | - exmc_sqpipsram_init_struct->address_bits | - exmc_sqpipsram_init_struct->command_bits; -} - -/*! - \brief configure consecutive clock - \param[in] clock_mode: specifie when the clock is generated - only one parameter can be selected which is shown as below: - \arg EXMC_CLOCK_SYN_MODE: the clock is generated only during synchronous access - \arg EXMC_CLOCK_UNCONDITIONALLY: the clock is generated unconditionally - \param[out] none - \retval none -*/ -void exmc_norsram_consecutive_clock_config(uint32_t clock_mode) -{ - if (EXMC_CLOCK_UNCONDITIONALLY == clock_mode){ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) |= EXMC_CLOCK_UNCONDITIONALLY; - }else{ - EXMC_SNCTL(EXMC_BANK0_NORSRAM_REGION0) &= ~EXMC_CLOCK_UNCONDITIONALLY; - } -} - -/*! - \brief configure CRAM page size - \param[in] exmc_norsram_region: select the region of bank0 - only one parameter can be selected which is shown as below: - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0..3) - \param[in] page_size: CRAM page size - only one parameter can be selected which is shown as below: - \arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access - \arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes - \arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes - \arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes - \arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes - \param[out] none - \retval none -*/ -void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size) -{ - /* reset the bits */ - EXMC_SNCTL(exmc_norsram_region) &= ~EXMC_SNCTL_CPS; - - /* set the CPS bits */ - EXMC_SNCTL(exmc_norsram_region) |= page_size; -} - -/*! - \brief enable or disable the EXMC NAND ECC function - \param[in] exmc_nand_bank: specifie the NAND bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANKx_NAND(x=1,2) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue) -{ - if (ENABLE == newvalue){ - /* enable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) |= EXMC_NPCTL_ECCEN; - }else{ - /* disable the selected NAND bank ECC function */ - EXMC_NPCTL(exmc_nand_bank) &= ~EXMC_NPCTL_ECCEN; - } -} - -/*! - \brief get the EXMC ECC value - \param[in] exmc_nand_bank: specifie the NAND bank - only one parameter can be selected which is shown as below: - \arg EXMC_BANKx_NAND(x=1,2) - \param[out] none - \retval the error correction code(ECC) value -*/ -uint32_t exmc_ecc_get(uint32_t exmc_nand_bank) -{ - return(EXMC_NECC(exmc_nand_bank)); -} - -/*! - \brief enable or disable read sample - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void exmc_sdram_readsample_enable(ControlStatus newvalue) -{ - if (ENABLE == newvalue){ - EXMC_SDRSCTL |= EXMC_SDRSCTL_RSEN; - }else{ - EXMC_SDRSCTL &= (uint32_t)(~EXMC_SDRSCTL_RSEN); - } -} - -/*! - \brief configure the delayed sample clock of read data - \param[in] delay_cell: SDRAM the delayed sample clock of read data - only one parameter can be selected which is shown as below: - \arg EXMC_SDRAM_x_DELAY_CELL(x=0..15) - \param[in] extra_hclk: sample cycle of read data - only one parameter can be selected which is shown as below: - \arg EXMC_SDRAM_READSAMPLE_x_EXTRAHCLK(x=0,1) - \param[out] none - \retval none -*/ -void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk) -{ - uint32_t sdrsctl = 0U; - - /* reset the bits */ - sdrsctl = EXMC_SDRSCTL & (~(EXMC_SDRSCTL_SDSC | EXMC_SDRSCTL_SSCR)); - /* set the bits */ - sdrsctl |= (uint32_t)(delay_cell & EXMC_SDRSCTL_SDSC) | - ((extra_hclk << SDRSCTL_SSCR_OFFSET) & EXMC_SDRSCTL_SSCR); - EXMC_SDRSCTL = sdrsctl; -} - -/*! - \brief configure the SDRAM memory command - \param[in] exmc_sdram_command_init_struct: initialize EXMC SDRAM command - mode_register_content: - auto_refresh_number: EXMC_SDRAM_AUTO_REFLESH_x_SDCLK, x=1..15 - bank_select: EXMC_SDRAM_DEVICE0_SELECT, EXMC_SDRAM_DEVICE1_SELECT, EXMC_SDRAM_DEVICE0_1_SELECT - command: EXMC_SDRAM_NORMAL_OPERATION, EXMC_SDRAM_CLOCK_ENABLE, EXMC_SDRAM_PRECHARGE_ALL, - EXMC_SDRAM_AUTO_REFRESH, EXMC_SDRAM_LOAD_MODE_REGISTER, EXMC_SDRAM_SELF_REFRESH, - EXMC_SDRAM_POWERDOWN_ENTRY - \param[out] none - \retval none -*/ -void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct) -{ - /* configure command register */ - EXMC_SDCMD = (uint32_t)((exmc_sdram_command_init_struct->command) | - (exmc_sdram_command_init_struct->bank_select) | - ((exmc_sdram_command_init_struct->auto_refresh_number)) | - ((exmc_sdram_command_init_struct->mode_register_content)<> SDSTAT_STA0_OFFSET); - }else{ - sdstat = ((uint32_t)(EXMC_SDSTAT & EXMC_SDSDAT_STA1) >> SDSTAT_STA1_OFFSET); - } - - return sdstat; -} - -/*! - \brief set the read command - \param[in] read_command_mode: configure SPI PSRAM read command mode - only one parameter can be selected which is shown as below: - \arg EXMC_SQPIPSRAM_READ_MODE_DISABLE: not SPI mode - \arg EXMC_SQPIPSRAM_READ_MODE_SPI: SPI mode - \arg EXMC_SQPIPSRAM_READ_MODE_SQPI: SQPI mode - \arg EXMC_SQPIPSRAM_READ_MODE_QPI: QPI mode - \param[in] read_wait_cycle: wait cycle number after address phase,0..15 - \param[in] read_command_code: read command for AHB read transfer - \param[out] none - \retval none -*/ -void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle, uint32_t read_command_code) -{ - uint32_t srcmd; - - srcmd = (uint32_t) read_command_mode | - ((read_wait_cycle << SRCMD_RWAITCYCLE_OFFSET) & EXMC_SRCMD_RWAITCYCLE) | - ((read_command_code & EXMC_SRCMD_RCMD)); - EXMC_SRCMD = srcmd; -} - -/*! - \brief set the write command - \param[in] write_command_mode: configure SPI PSRAM write command mode - only one parameter can be selected which is shown as below: - \arg EXMC_SQPIPSRAM_WRITE_MODE_DISABLE: not SPI mode - \arg EXMC_SQPIPSRAM_WRITE_MODE_SPI: SPI mode - \arg EXMC_SQPIPSRAM_WRITE_MODE_SQPI: SQPI mode - \arg EXMC_SQPIPSRAM_WRITE_MODE_QPI: QPI mode - \param[in] write_wait_cycle: wait cycle number after address phase,0..15 - \param[in] write_command_code: read command for AHB read transfer - \param[out] none - \retval none -*/ -void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle, uint32_t write_command_code) -{ - uint32_t swcmd; - - swcmd = (uint32_t) write_command_mode | - ((write_wait_cycle << SWCMD_WWAITCYCLE_OFFSET) & EXMC_SWCMD_WWAITCYCLE) | - ((write_command_code & EXMC_SWCMD_WCMD)); - EXMC_SWCMD = swcmd; -} - -/*! - \brief send SPI read ID command - \param[in] none - \param[out] none - \retval none -*/ -void exmc_sqpipsram_read_id_command_send(void) -{ - EXMC_SRCMD |= EXMC_SRCMD_RDID; -} - -/*! - \brief send SPI special command which does not have address and data phase - \param[in] none - \param[out] none - \retval none -*/ -void exmc_sqpipsram_write_cmd_send(void) -{ - EXMC_SWCMD |= EXMC_SWCMD_SC; -} - -/*! - \brief get the EXMC SPI ID low data - \param[in] none - \param[out] none - \retval the ID low data -*/ -uint32_t exmc_sqpipsram_low_id_get(void) -{ - return (EXMC_SIDL); -} - -/*! - \brief get the EXMC SPI ID high data - \param[in] none - \param[out] none - \retval the ID high data -*/ -uint32_t exmc_sqpipsram_high_id_get(void) -{ - return (EXMC_SIDH); -} - -/*! - \brief get the bit value of EXMC send write command bit or read ID command - \param[in] send_command_flag: the send command flag - only one parameter can be selected which is shown as below: - \arg EXMC_SEND_COMMAND_FLAG_RDID: EXMC_SRCMD_RDID flag bit - \arg EXMC_SEND_COMMAND_FLAG_SC: EXMC_SWCMD_SC flag bit - \param[out] none - \retval the new value of send command flag -*/ -FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag) -{ - uint32_t flag = 0x00000000U; - - if(EXMC_SEND_COMMAND_FLAG_RDID == send_command_flag){ - flag = EXMC_SRCMD; - }else if(EXMC_SEND_COMMAND_FLAG_SC == send_command_flag){ - flag = EXMC_SWCMD; - }else{ - } - - if (flag & send_command_flag){ - /* flag is set */ - return SET; - }else{ - /* flag is reset */ - return RESET; - } -} - -/*! - \brief enable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank,PC card bank or SDRAM device - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: specify get which interrupt flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag - \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag - \param[out] none - \retval none -*/ -void exmc_interrupt_enable(uint32_t exmc_bank, uint32_t interrupt) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) |= interrupt; - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDARI |= EXMC_SDARI_REIE; - } -} - -/*! - \brief disable EXMC interrupt - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: specify get which interrupt flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag - \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag - \param[out] none - \retval none -*/ -void exmc_interrupt_disable(uint32_t exmc_bank, uint32_t interrupt) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~interrupt; - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDARI &= ~EXMC_SDARI_REIE; - } -} - -/*! - \brief get EXMC flag status - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC Card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: EXMC status and flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \arg EXMC_SDRAM_FLAG_REFRESH: refresh error interrupt flag - \arg EXMC_SDRAM_FLAG_NREADY: not ready status - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) -{ - uint32_t status = 0x00000000U; - - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(exmc_bank); - }else{ - /* SDRAM device0 or device1 */ - status = EXMC_SDSTAT; - } - - if ((status & flag) != (uint32_t)flag ){ - /* flag is reset */ - return RESET; - }else{ - /* flag is set */ - return SET; - } -} - -/*! - \brief clear EXMC flag status - \param[in] exmc_bank: specifie the NAND bank , PCCARD bank or SDRAM device - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] flag: EXMC status and flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_FLAG_RISE: interrupt rising edge status - \arg EXMC_NAND_PCCARD_FLAG_LEVEL: interrupt high-level status - \arg EXMC_NAND_PCCARD_FLAG_FALL: interrupt falling edge status - \arg EXMC_NAND_PCCARD_FLAG_FIFOE: FIFO empty flag - \arg EXMC_SDRAM_FLAG_REFRESH: refresh error interrupt flag - \arg EXMC_SDRAM_FLAG_NREADY: not ready status - \param[out] none - \retval none -*/ -void exmc_flag_clear(uint32_t exmc_bank, uint32_t flag) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~flag; - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDSTAT &= ~flag; - } -} - -/*! - \brief get EXMC interrupt flag - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: EXMC interrupt flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag - \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank, uint32_t interrupt) -{ - uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; - - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - status = EXMC_NPINTEN(exmc_bank); - interrupt_state = (status & (interrupt >> INTEN_INTS_OFFSET)); - }else{ - /* SDRAM device0 or device1 */ - status = EXMC_SDARI; - interrupt_state = (EXMC_SDSTAT & EXMC_SDSDAT_REIF); - } - - interrupt_enable = (status & interrupt); - - if ((interrupt_enable) && (interrupt_state)){ - /* interrupt flag is set */ - return SET; - }else{ - /* interrupt flag is reset */ - return RESET; - } -} - -/*! - \brief clear EXMC interrupt flag - \param[in] exmc_bank: specifies the NAND bank , PC card bank or SDRAM device - only one parameter can be selected which is shown as below: - \arg EXMC_BANK1_NAND: the NAND bank1 - \arg EXMC_BANK2_NAND: the NAND bank2 - \arg EXMC_BANK3_PCCARD: the PC card bank - \arg EXMC_SDRAM_DEVICE0: the SDRAM device0 - \arg EXMC_SDRAM_DEVICE1: the SDRAM device1 - \param[in] interrupt: EXMC interrupt flag - only one parameter can be selected which is shown as below: - \arg EXMC_NAND_PCCARD_INT_FLAG_RISE: rising edge interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_LEVEL: high-level interrupt and flag - \arg EXMC_NAND_PCCARD_INT_FLAG_FALL: falling edge interrupt and flag - \arg EXMC_SDRAM_INT_FLAG_REFRESH: refresh error interrupt and flag - \param[out] none - \retval none -*/ -void exmc_interrupt_flag_clear(uint32_t exmc_bank, uint32_t interrupt) -{ - if((EXMC_BANK1_NAND == exmc_bank) || (EXMC_BANK2_NAND == exmc_bank) || (EXMC_BANK3_PCCARD == exmc_bank)){ - /* NAND bank1,bank2 or PC card bank3 */ - EXMC_NPINTEN(exmc_bank) &= ~(interrupt >> INTEN_INTS_OFFSET); - }else{ - /* SDRAM device0 or device1 */ - EXMC_SDARI |= EXMC_SDARI_REC; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c deleted file mode 100644 index a3eacb0202..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c +++ /dev/null @@ -1,257 +0,0 @@ -/*! - \file gd32f4xx_exti.c - \brief EXTI driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_exti.h" - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x00000000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; -} - -/*! - \brief initialize the EXTI - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling trigger - \arg EXTI_TRIG_BOTH: rising and falling trigger - \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, \ - exti_mode_enum mode, \ - exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch(trig_type){ - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_NONE: - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI lines flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..22): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c deleted file mode 100644 index 4e2b0db9a5..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c +++ /dev/null @@ -1,932 +0,0 @@ -/*! - \file gd32f4xx_fmc.c - \brief FMC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#include "gd32f4xx_fmc.h" - -/*! - \brief set the wait state counter value - \param[in] wscnt: wait state counter value - only one parameter can be selected which is shown as below: - \arg WS_WSCNT_0: FMC 0 wait - \arg WS_WSCNT_1: FMC 1 wait - \arg WS_WSCNT_2: FMC 2 wait - \arg WS_WSCNT_3: FMC 3 wait - \arg WS_WSCNT_4: FMC 4 wait - \arg WS_WSCNT_5: FMC 5 wait - \arg WS_WSCNT_6: FMC 6 wait - \arg WS_WSCNT_7: FMC 7 wait - \arg WS_WSCNT_8: FMC 8 wait - \arg WS_WSCNT_9: FMC 9 wait - \arg WS_WSCNT_10: FMC 10 wait - \arg WS_WSCNT_11: FMC 11 wait - \arg WS_WSCNT_12: FMC 12 wait - \arg WS_WSCNT_13: FMC 13 wait - \arg WS_WSCNT_14: FMC 14 wait - \arg WS_WSCNT_15: FMC 15 wait - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint32_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WC_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief unlock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL & FMC_CTL_LK))){ - /* write the FMC key */ - FMC_KEY = UNLOCK_KEY0; - FMC_KEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit*/ - FMC_CTL |= FMC_CTL_LK; -} - -/*! - \brief erase sector - \param[in] fmc_sector: select the sector to erase - only one parameter can be selected which is shown as below: - \arg CTL_SECTOR_NUMBER_0: sector 0 - \arg CTL_SECTOR_NUMBER_1: sector 1 - \arg CTL_SECTOR_NUMBER_2: sector 2 - \arg CTL_SECTOR_NUMBER_3: sector 3 - \arg CTL_SECTOR_NUMBER_4: sector 4 - \arg CTL_SECTOR_NUMBER_5: sector 5 - \arg CTL_SECTOR_NUMBER_6: sector 6 - \arg CTL_SECTOR_NUMBER_7: sector 7 - \arg CTL_SECTOR_NUMBER_8: sector 8 - \arg CTL_SECTOR_NUMBER_9: sector 9 - \arg CTL_SECTOR_NUMBER_10: sector 10 - \arg CTL_SECTOR_NUMBER_11: sector 11 - \arg CTL_SECTOR_NUMBER_12: sector 12 - \arg CTL_SECTOR_NUMBER_13: sector 13 - \arg CTL_SECTOR_NUMBER_14: sector 14 - \arg CTL_SECTOR_NUMBER_15: sector 15 - \arg CTL_SECTOR_NUMBER_16: sector 16 - \arg CTL_SECTOR_NUMBER_17: sector 17 - \arg CTL_SECTOR_NUMBER_18: sector 18 - \arg CTL_SECTOR_NUMBER_19: sector 19 - \arg CTL_SECTOR_NUMBER_20: sector 20 - \arg CTL_SECTOR_NUMBER_21: sector 21 - \arg CTL_SECTOR_NUMBER_22: sector 22 - \arg CTL_SECTOR_NUMBER_23: sector 23 - \arg CTL_SECTOR_NUMBER_24: sector 24 - \arg CTL_SECTOR_NUMBER_25: sector 25 - \arg CTL_SECTOR_NUMBER_26: sector 26 - \arg CTL_SECTOR_NUMBER_27: sector 27 - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_sector_erase(uint32_t fmc_sector) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - /* start sector erase */ - FMC_CTL &= ~FMC_CTL_SN; - FMC_CTL |= (FMC_CTL_SER | fmc_sector); - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - /* reset the SER bit */ - FMC_CTL &= (~FMC_CTL_SER); - FMC_CTL &= ~FMC_CTL_SN; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL |= (FMC_CTL_MER0 | FMC_CTL_MER1); - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - /* reset the MER bits */ - FMC_CTL &= ~(FMC_CTL_MER0 | FMC_CTL_MER1); - } - - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief erase all FMC sectors in bank0 - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_bank0_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - /* start FMC bank0 erase */ - FMC_CTL |= FMC_CTL_MER0; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - /* reset the MER0 bit */ - FMC_CTL &= (~FMC_CTL_MER0); - } - - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief erase all FMC sectors in bank1 - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_bank1_erase(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - /* start FMC bank1 erase */ - FMC_CTL |= FMC_CTL_MER1; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - /* reset the MER1 bit */ - FMC_CTL &= (~FMC_CTL_MER1); - } - - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program(0x00000000 - 0xFFFFFFFF) - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL &= ~FMC_CTL_PSZ; - FMC_CTL |= CTL_PSZ_WORD; - FMC_CTL |= FMC_CTL_PG; - - REG32(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a half word at the corresponding address - \param[in] address: address to program - \param[in] data: halfword to program(0x0000 - 0xFFFF) - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL &= ~FMC_CTL_PSZ; - FMC_CTL |= CTL_PSZ_HALF_WORD; - FMC_CTL |= FMC_CTL_PG; - - REG16(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a byte at the corresponding address - \param[in] address: address to program - \param[in] data: byte to program(0x00 - 0xFF) - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL &= ~FMC_CTL_PSZ; - FMC_CTL |= CTL_PSZ_BYTE; - FMC_CTL |= FMC_CTL_PG; - - REG8(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_OB_LK)){ - /* write the FMC key */ - FMC_OBKEY = OB_UNLOCK_KEY0; - FMC_OBKEY = OB_UNLOCK_KEY1; - } -} - -/*! - \brief lock the option byte operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OB_LK bit */ - FMC_OBCTL0 |= FMC_OBCTL0_OB_LK; -} - -/*! - \brief send option byte change command - \param[in] none - \param[out] none - \retval none -*/ -void ob_start(void) -{ - fmc_state_enum fmc_state = FMC_READY; - /* set the OB_START bit in OBCTL0 register */ - FMC_OBCTL0 |= FMC_OBCTL0_OB_START; - fmc_state = fmc_ready_wait(); - if(FMC_READY != fmc_state){ - while(1){ - } - } -} - -/*! - \brief erase option byte - \param[in] none - \param[out] none - \retval none -*/ -void ob_erase(void) -{ - uint32_t reg, reg1; - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - reg = FMC_OBCTL0; - reg1 = FMC_OBCTL1; - - /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ - reg |= (FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); - /* reset the BOR level */ - reg |= FMC_OBCTL0_BOR_TH; - /* reset option byte boot bank value */ - reg &= ~FMC_OBCTL0_BB; - /* reset option byte dbs value */ - reg &= ~FMC_OBCTL0_DBS; - - /* reset drp and wp value */ - reg |= FMC_OBCTL0_WP0; - reg &= (~FMC_OBCTL0_DRP); - FMC_OBCTL0 = reg; - - reg1 |= FMC_OBCTL1_WP1; - FMC_OBCTL1 = reg1; - - FMC_OBCTL0 = reg; - } -} - -/*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected - one or more parameters can be selected which are shown as below: - \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) - \arg OB_WP_23_27: sector23~27 - \arg OB_WP_ALL: all sector - \param[out] none - \retval none -*/ -void ob_write_protection_enable(uint32_t ob_wp) -{ - uint32_t reg0 = FMC_OBCTL0; - uint32_t reg1 = FMC_OBCTL1; - fmc_state_enum fmc_state = FMC_READY; - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ - while(1){ - } - } - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - reg0 &= (~((uint32_t)ob_wp << 16)); - reg1 &= (~(ob_wp & 0xFFFF0000U)); - FMC_OBCTL0 = reg0; - FMC_OBCTL1 = reg1; - } -} - -/*! - \brief disable write protection - \param[in] ob_wp: specify sector to be write protected - one or more parameters can be selected which are shown as below: - \arg OB_WP_x(x=0..22):sector x(x = 0,1,2...22) - \arg OB_WP_23_27: sector23~27 - \arg OB_WP_ALL: all sector - \param[out] none - \retval none -*/ -void ob_write_protection_disable(uint32_t ob_wp) -{ - uint32_t reg0 = FMC_OBCTL0; - uint32_t reg1 = FMC_OBCTL1; - fmc_state_enum fmc_state = FMC_READY; - if(RESET != (FMC_OBCTL0 & FMC_OBCTL0_DRP)){ - while(1){ - } - } - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - reg0 |= ((uint32_t)ob_wp << 16); - reg1 |= (ob_wp & 0xFFFF0000U); - FMC_OBCTL0 = reg0; - FMC_OBCTL1 = reg1; - } -} - -/*! - \brief enable erase/program protection and D-bus read protection - \param[in] ob_drp: enable the WPx bits used as erase/program protection and D-bus read protection of each sector - one or more parameters can be selected which are shown as below: - \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) - \arg OB_DRP_23_27: sector23~27 - \arg OB_DRP_ALL: all sector - \param[out] none - \retval none -*/ -void ob_drp_enable(uint32_t ob_drp) -{ - uint32_t reg0 = FMC_OBCTL0; - uint32_t reg1 = FMC_OBCTL1; - fmc_state_enum fmc_state = FMC_READY; - uint32_t drp_state = FMC_OBCTL0 & FMC_OBCTL0_DRP; - uint32_t wp0_state = FMC_OBCTL0 & FMC_OBCTL0_WP0; - uint32_t wp1_state = FMC_OBCTL1 & FMC_OBCTL1_WP1; - /*disable write protection before enable D-bus read protection*/ - if((RESET != drp_state) && ((FMC_OBCTL0_WP0 != wp0_state) && (FMC_OBCTL1_WP1 != wp1_state))){ - while(1){ - } - } - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - reg0 &= ~FMC_OBCTL0_WP0; - reg1 &= ~FMC_OBCTL1_WP1; - reg0 |= ((uint32_t)ob_drp << 16); - reg1 |= ((uint32_t)ob_drp & 0xFFFF0000U); - FMC_OBCTL0 = reg0; - FMC_OBCTL1 = reg1; - FMC_OBCTL0 |= FMC_OBCTL0_DRP; - } -} - -/*! - \brief disable erase/program protection and D-bus read protection - \param[in] ob_drp: disable the WPx bits used as erase/program protection and D-bus read protection of each sector - one or more parameters can be selected which are shown as below: - \arg OB_DRP_x(x=0..22): sector x(x = 0,1,2...22) - \arg OB_DRP_23_27: sector23~27 - \arg OB_DRP_ALL: all sector - \param[out] none - \retval none -*/ -void ob_drp_disable(uint32_t ob_drp) -{ - uint32_t reg0 = FMC_OBCTL0; - uint32_t reg1 = FMC_OBCTL1; - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - reg0 |= FMC_OBCTL0_WP0; - reg0 &= (~FMC_OBCTL0_DRP); - FMC_OBCTL0 = reg0; - - reg1 |= FMC_OBCTL1_WP1; - FMC_OBCTL1 = reg1; - } -} - -/*! - \brief configure security protection level - \param[in] ob_spc: specify security protection level - only one parameter can be selected which is shown as below: - \arg FMC_NSPC: no security protection - \arg FMC_LSPC: low security protection - \arg FMC_HSPC: high security protection - \param[out] none - \retval none -*/ -void ob_security_protection_config(uint8_t ob_spc) -{ - fmc_state_enum fmc_state = FMC_READY; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - uint32_t reg; - - reg = FMC_OBCTL0; - /* reset the OBCTL0_SPC, set according to ob_spc */ - reg &= ~FMC_OBCTL0_SPC; - reg |= ((uint32_t)ob_spc << 8); - FMC_OBCTL0 = reg; - } -} - -/*! - \brief program the FMC user option byte - \param[in] ob_fwdgt: option byte watchdog value - only one parameter can be selected which is shown as below: - \arg OB_FWDGT_SW: software free watchdog - \arg OB_FWDGT_HW: hardware free watchdog - \param[in] ob_deepsleep: option byte deepsleep reset value - only one parameter can be selected which is shown as below: - \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \param[in] ob_stdby:option byte standby reset value - only one parameter can be selected which is shown as below: - \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \param[out] none - \retval none -*/ -void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby) -{ - fmc_state_enum fmc_state = FMC_READY; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(); - - if(FMC_READY == fmc_state){ - uint32_t reg; - - reg = FMC_OBCTL0; - /* reset the OB_FWDGT, OB_DEEPSLEEP and OB_STDBY, set according to ob_fwdgt ,ob_deepsleep and ob_stdby */ - reg &= ~(FMC_OBCTL0_NWDG_HW | FMC_OBCTL0_NRST_DPSLP | FMC_OBCTL0_NRST_STDBY); - FMC_OBCTL0 = (reg | ob_fwdgt | ob_deepsleep | ob_stdby); - } -} - -/*! - \brief program the option byte BOR threshold value - \param[in] ob_bor_th: user option byte - only one parameter can be selected which is shown as below: - \arg OB_BOR_TH_VALUE3: BOR threshold value 3 - \arg OB_BOR_TH_VALUE2: BOR threshold value 2 - \arg OB_BOR_TH_VALUE1: BOR threshold value 1 - \arg OB_BOR_TH_OFF: no BOR function - \param[out] none - \retval none -*/ -void ob_user_bor_threshold(uint32_t ob_bor_th) -{ - uint32_t reg; - - reg = FMC_OBCTL0; - /* set the BOR level */ - reg &= ~FMC_OBCTL0_BOR_TH; - FMC_OBCTL0 = (reg | ob_bor_th); -} - -/*! - \brief configure the option byte boot bank value - \param[in] boot_mode: specifies the option byte boot bank value - only one parameter can be selected which is shown as below: - \arg OB_BB_DISABLE: boot from bank0 - \arg OB_BB_ENABLE: boot from bank1 or bank0 if bank1 is void - \param[out] none - \retval none -*/ -void ob_boot_mode_config(uint32_t boot_mode) -{ - uint32_t reg; - - reg = FMC_OBCTL0; - /* set option byte boot bank value */ - reg &= ~FMC_OBCTL0_BB; - FMC_OBCTL0 = (reg | boot_mode); -} - -/*! - \brief get the FMC user option byte - \param[in] none - \param[out] none - \retval the FMC user option byte values: ob_fwdgt(Bit0), ob_deepsleep(Bit1), ob_stdby(Bit2) -*/ -uint8_t ob_user_get(void) -{ - return (uint8_t)((uint8_t)(FMC_OBCTL0 >> 5) & (uint8_t)0x07); -} - -/*! - \brief get the FMC option byte write protection - \param[in] none - \param[out] none - \retval the FMC write protection option byte value -*/ -uint16_t ob_write_protection0_get(void) -{ - /* return the FMC write protection option byte value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF); -} - -/*! - \brief get the FMC option byte write protection - \param[in] none - \param[out] none - \retval the FMC write protection option byte value -*/ -uint16_t ob_write_protection1_get(void) -{ - /* return the the FMC write protection option byte value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF); -} - -/*! - \brief get the FMC D-bus read protection protection - \param[in] none - \param[out] none - \retval the FMC erase/program protection and D-bus read protection option bytes value -*/ -uint16_t ob_drp0_get(void) -{ - /* return the FMC erase/program protection and D-bus read protection option bytes value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL0 >> 16)) & (uint16_t)0x0FFF); -} - -/*! - \brief get the FMC D-bus read protection protection - \param[in] none - \param[out] none - \retval the FMC erase/program protection and D-bus read protection option bytes value -*/ -uint16_t ob_drp1_get(void) -{ - /* return the FMC erase/program protection and D-bus read protection option bytes value */ - return (uint16_t)(((uint16_t)(FMC_OBCTL1 >> 16)) & (uint16_t)0x0FFF); -} - -/*! - \brief get the FMC option byte security protection - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus ob_spc_get(void) -{ - FlagStatus spc_state = RESET; - - if (((uint8_t)(FMC_OBCTL0 >> 8)) != (uint8_t)FMC_NSPC){ - spc_state = SET; - }else{ - spc_state = RESET; - } - return spc_state; -} - -/*! - \brief get the FMC option byte BOR threshold value - \param[in] none - \param[out] none - \retval the FMC BOR threshold value:OB_BOR_TH_OFF,OB_BOR_TH_VALUE1,OB_BOR_TH_VALUE2,OB_BOR_TH_VALUE3 -*/ -uint8_t ob_user_bor_threshold_get(void) -{ - /* return the FMC BOR threshold value */ - return (uint8_t)((uint8_t)FMC_OBCTL0 & (uint8_t)0x0C); -} - -/*! - \brief enable FMC interrupt - \param[in] fmc_int: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: enable FMC end of program interrupt - \arg FMC_INT_ERR: enable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t fmc_int) -{ - FMC_CTL |= fmc_int; -} - -/*! - \brief disable FMC interrupt - \param[in] fmc_int: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: disable FMC end of program interrupt - \arg FMC_INT_ERR: disable FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t fmc_int) -{ - FMC_CTL &= ~(uint32_t)fmc_int; -} - -/*! - \brief get flag set or reset - \param[in] fmc_flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag bit - \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit - \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit - \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit - \arg FMC_FLAG_WPERR: FMC Erase/Program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t fmc_flag) -{ - if(FMC_STAT & fmc_flag){ - return SET; - } - /* return the state of corresponding FMC flag */ - return RESET; -} - -/*! - \brief clear the FMC pending flag - \param[in] FMC_flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_RDDERR: FMC read D-bus protection error flag bit - \arg FMC_FLAG_PGSERR: FMC program sequence error flag bit - \arg FMC_FLAG_PGMERR: FMC program size not match error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_OPERR: FMC operation error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t fmc_flag) -{ - /* clear the flags */ - FMC_STAT = fmc_flag; -} - -/*! - \brief get the FMC state - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((FMC_STAT & FMC_FLAG_BUSY) == FMC_FLAG_BUSY){ - fmc_state = FMC_BUSY; - }else{ - if((FMC_STAT & FMC_FLAG_WPERR) != (uint32_t)0x00){ - fmc_state = FMC_WPERR; - }else{ - if((FMC_STAT & FMC_FLAG_RDDERR) != (uint32_t)0x00){ - fmc_state = FMC_RDDERR; - }else{ - if((FMC_STAT & (uint32_t)0xEF) != (uint32_t)0x00){ - fmc_state = FMC_PGERR; - }else{ - if((FMC_STAT & FMC_FLAG_OPERR) != (uint32_t)0x00){ - fmc_state = FMC_OPERR; - }else{ - fmc_state = FMC_READY; - } - } - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC is ready or not - \param[in] none - \param[out] none - \retval state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_RDDERR: read D-bus protection error - \arg FMC_PGSERR: program sequence error - \arg FMC_PGMERR: program size not match error - \arg FMC_WPERR: erase/program protection error - \arg FMC_OPERR: operation error - \arg FMC_PGERR: program error -*/ -fmc_state_enum fmc_ready_wait(void) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_state_get(); - }while(FMC_BUSY == fmc_state); - - /* return the FMC state */ - return fmc_state; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c deleted file mode 100644 index 04e2c5b99d..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c +++ /dev/null @@ -1,157 +0,0 @@ -/*! - \file gd32f4xx_fwdgt.c - \brief FWDGT driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_fwdgt.h" - -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(RESET != (FWDGT_STAT & flag)){ - return SET; - } - - return RESET; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c deleted file mode 100644 index d3693abb17..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c +++ /dev/null @@ -1,433 +0,0 @@ -/*! - \file gd32f4xx_gpio.c - \brief GPIO driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_gpio.h" - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch(gpio_periph){ - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOD: - /* reset GPIOD */ - rcu_periph_reset_enable(RCU_GPIODRST); - rcu_periph_reset_disable(RCU_GPIODRST); - break; - case GPIOE: - /* reset GPIOE */ - rcu_periph_reset_enable(RCU_GPIOERST); - rcu_periph_reset_disable(RCU_GPIOERST); - break; - case GPIOF: - /* reset GPIOF */ - rcu_periph_reset_enable(RCU_GPIOFRST); - rcu_periph_reset_disable(RCU_GPIOFRST); - break; - case GPIOG: - /* reset GPIOG */ - rcu_periph_reset_enable(RCU_GPIOGRST); - rcu_periph_reset_disable(RCU_GPIOGRST); - break; - case GPIOH: - /* reset GPIOH */ - rcu_periph_reset_enable(RCU_GPIOHRST); - rcu_periph_reset_disable(RCU_GPIOHRST); - break; - case GPIOI: - /* reset GPIOI */ - rcu_periph_reset_enable(RCU_GPIOIRST); - rcu_periph_reset_disable(RCU_GPIOIRST); - break; - default: - break; - } -} - -/*! - \brief set GPIO mode - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] mode: GPIO pin mode - \arg GPIO_MODE_INPUT: input mode - \arg GPIO_MODE_OUTPUT: output mode - \arg GPIO_MODE_AF: alternate function mode - \arg GPIO_MODE_ANALOG: analog mode - \param[in] pull_up_down: GPIO pin with pull-up or pull-down resistor - \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors - \arg GPIO_PUPD_PULLUP: with pull-up resistor - \arg GPIO_PUPD_PULLDOWN:with pull-down resistor - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) -{ - uint16_t i; - uint32_t ctl, pupd; - - ctl = GPIO_CTL(gpio_periph); - pupd = GPIO_PUD(gpio_periph); - - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin mode bits */ - ctl &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - ctl |= GPIO_MODE_SET(i, mode); - - /* clear the specified pin pupd bits */ - pupd &= ~GPIO_PUPD_MASK(i); - /* set the specified pin pupd bits */ - pupd |= GPIO_PUPD_SET(i, pull_up_down); - } - } - - GPIO_CTL(gpio_periph) = ctl; - GPIO_PUD(gpio_periph) = pupd; -} - -/*! - \brief set GPIO output type and speed - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] otype: GPIO pin output mode - \arg GPIO_OTYPE_PP: push pull mode - \arg GPIO_OTYPE_OD: open drain mode - \param[in] speed: GPIO pin output max speed - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_25MHZ: output max speed 25MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \arg GPIO_OSPEED_200MHZ: output max speed 200MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t ospeedr; - - if(GPIO_OTYPE_OD == otype){ - GPIO_OMODE(gpio_periph) |= (uint32_t)pin; - }else{ - GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); - } - - /* get the specified pin output speed bits value */ - ospeedr = GPIO_OSPD(gpio_periph); - - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin output speed bits */ - ospeedr &= ~GPIO_OSPEED_MASK(i); - /* set the specified pin output speed bits */ - ospeedr |= GPIO_OSPEED_SET(i,speed); - } - } - GPIO_OSPD(gpio_periph) = ospeedr; -} - -/*! - \brief set GPIO pin bit - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin bit - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if(RESET != bit_value){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] data: specify the value to be written to the port output control register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph, uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval input status of GPIO pin: SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO all pins input status - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[out] none - \retval input status of GPIO all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return ((uint16_t)GPIO_ISTAT(gpio_periph)); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval output status of GPIO pin: SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO all pins output status - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[out] none - \retval output status of GPIO all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return ((uint16_t)GPIO_OCTL(gpio_periph)); -} - -/*! - \brief set GPIO alternate function - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] alt_func_num: GPIO pin af function - \arg GPIO_AF_0: SYSTEM - \arg GPIO_AF_1: TIMER0, TIMER1 - \arg GPIO_AF_2: TIMER2, TIMER3, TIMER4 - \arg GPIO_AF_3: TIMER7, TIMER8, TIMER9, TIMER10 - \arg GPIO_AF_4: I2C0, I2C1, I2C2 - \arg GPIO_AF_5: SPI0, SPI1, SPI2, SPI3, SPI4, SPI5 - \arg GPIO_AF_6: SPI1, SPI2, SAI0 - \arg GPIO_AF_7: USART0, USART1, USART2 - \arg GPIO_AF_8: UART3, UART4, USART5, UART6, UART7 - \arg GPIO_AF_9: CAN0, CAN1, TLI, TIMER11, TIMER12, TIMER13 - \arg GPIO_AF_10: USB_FS, USB_HS - \arg GPIO_AF_11: ENET - \arg GPIO_AF_12: EXMC, SDIO, USB_HS - \arg GPIO_AF_13: DCI - \arg GPIO_AF_14: TLI - \arg GPIO_AF_15: EVENTOUT - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) -{ - uint16_t i; - uint32_t afrl, afrh; - - afrl = GPIO_AFSEL0(gpio_periph); - afrh = GPIO_AFSEL1(gpio_periph); - - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ - /* clear the specified pin alternate function bits */ - afrl &= ~GPIO_AFR_MASK(i); - afrl |= GPIO_AFR_SET(i,alt_func_num); - } - } - - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin alternate function bits */ - afrh &= ~GPIO_AFR_MASK(i - 8U); - afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); - } - } - - GPIO_AFSEL0(gpio_periph) = afrl; - GPIO_AFSEL1(gpio_periph) = afrh; -} - -/*! - \brief lock GPIO pin bit - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -/*! - \brief toggle GPIO pin status - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_TG(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief toggle GPIO port status - \param[in] gpio_periph: GPIO port - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,D,E,F,G,H,I) - - \param[out] none - \retval none -*/ -void gpio_port_toggle(uint32_t gpio_periph) -{ - GPIO_TG(gpio_periph) = 0x0000FFFFU; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c deleted file mode 100644 index c3ac50c178..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c +++ /dev/null @@ -1,819 +0,0 @@ -/*! - \file gd32f4xx_i2c.c - \brief I2C driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2019-04-16, V2.0.2, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x00000032U) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ -#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch(i2c_periph){ - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - case I2C2: - /* reset I2C2 */ - rcu_periph_reset_enable(RCU_I2C2RST); - rcu_periph_reset_disable(RCU_I2C2RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - \param[in] dutycyc: duty cycle in fast mode - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) = I2CCLK_MAX; - }else{ - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - }else if(400000U >= clkspeed){ - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if(0U == (clkc & I2C_CKCFG_CLKC)){ - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - }else{ - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief configure I2C POAP position - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ - addr = addr & I2C_TRANSMITTER; - }else{ - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief enable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] addr: the second address in dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) -{ - /* configure address */ - addr = addr & I2C_ADDRESS2_MASK; - I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); -} - -/*! - \brief disable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_dualaddr_disable(uint32_t i2c_periph) -{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none -*/ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SS); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C PEC calculation on or off - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] pecstate: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none -*/ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable or disable I2C ARP protocol in SMBus switch - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] arpstate: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief analog noise filter disable - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_analog_noise_filter_disable(uint32_t i2c_periph) -{ - I2C_FCTL(i2c_periph) |= I2C_FCTL_AFD; -} - -/*! - \brief analog noise filter enable - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_analog_noise_filter_enable(uint32_t i2c_periph) -{ - I2C_FCTL(i2c_periph) &= ~(I2C_FCTL_AFD); -} - -/*! - \brief digital noise filter configuration - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] dfilterpara: refer to enum i2c_digital_filter_enum - \param[out] none - \retval none -*/ -void i2c_digital_noise_filter_config(uint32_t i2c_periph,i2c_digital_filter_enum dfilterpara) -{ - I2C_FCTL(i2c_periph) |= dfilterpara; -} - -/*! - \brief enable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_sam_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; -} - -/*! - \brief disable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_sam_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); -} - -/*! - \brief enable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; -} - -/*! - \brief disable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TRS: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(I2C_FLAG_ADDSEND == flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ - intenable = 1U; - }else{ - intenable = 0U; - } - } - if((0U != flagstatus) && (0U != intenable)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1,2) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - if(I2C_INT_FLAG_ADDSEND == int_flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c deleted file mode 100644 index 5afcc48e0d..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c +++ /dev/null @@ -1,637 +0,0 @@ -/*! - \file gd32f4xx_ipa.c - \brief IPA driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_ipa.h" - -#define IPA_DEFAULT_VALUE 0x00000000U - -/*! - \brief deinitialize IPA registers - \param[in] none - \param[out] none - \retval none -*/ -void ipa_deinit(void) -{ - rcu_periph_reset_enable(RCU_IPARST); - rcu_periph_reset_disable(RCU_IPARST); -} - -/*! - \brief enable IPA transfer - \param[in] none - \param[out] none - \retval none -*/ -void ipa_transfer_enable(void) -{ - IPA_CTL |= IPA_CTL_TEN; -} - -/*! - \brief enable IPA transfer hang up - \param[in] none - \param[out] none - \retval none -*/ -void ipa_transfer_hangup_enable(void) -{ - IPA_CTL |= IPA_CTL_THU; -} - -/*! - \brief disable IPA transfer hang up - \param[in] none - \param[out] none - \retval none -*/ -void ipa_transfer_hangup_disable(void) -{ - IPA_CTL &= ~(IPA_CTL_THU); -} - -/*! - \brief enable IPA transfer stop - \param[in] none - \param[out] none - \retval none -*/ -void ipa_transfer_stop_enable(void) -{ - IPA_CTL |= IPA_CTL_TST; -} - -/*! - \brief disable IPA transfer stop - \param[in] none - \param[out] none - \retval none -*/ -void ipa_transfer_stop_disable(void) -{ - IPA_CTL &= ~(IPA_CTL_TST); -} -/*! - \brief enable IPA foreground LUT loading - \param[in] none - \param[out] none - \retval none -*/ -void ipa_foreground_lut_loading_enable(void) -{ - IPA_FPCTL |= IPA_FPCTL_FLLEN; -} - -/*! - \brief enable IPA background LUT loading - \param[in] none - \param[out] none - \retval none -*/ -void ipa_background_lut_loading_enable(void) -{ - IPA_BPCTL |= IPA_BPCTL_BLLEN; -} - -/*! - \brief set pixel format convert mode, the function is invalid when the IPA transfer is enabled - \param[in] pfcm: pixel format convert mode - only one parameter can be selected which is shown as below: - \arg IPA_FGTODE: foreground memory to destination memory without pixel format convert - \arg IPA_FGTODE_PF_CONVERT: foreground memory to destination memory with pixel format convert - \arg IPA_FGBGTODE: blending foreground and background memory to destination memory - \arg IPA_FILL_UP_DE: fill up destination memory with specific color - \param[out] none - \retval none -*/ -void ipa_pixel_format_convert_mode_set(uint32_t pfcm) -{ - IPA_CTL |= pfcm; -} - -/*! - \brief initialize the structure of IPA foreground parameter struct with the default values, it is - suggested that call this function after an ipa_foreground_parameter_struct structure is defined - \param[in] none - \param[out] foreground_struct: the data needed to initialize foreground - foreground_memaddr: foreground memory base address - foreground_lineoff: foreground line offset - foreground_prealpha: foreground pre-defined alpha value - foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 - foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, - FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, - FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) - foreground_prered: foreground pre-defined red value - foreground_pregreen: foreground pre-defined green value - foreground_preblue: foreground pre-defined blue value - \retval none -*/ -void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct* foreground_struct) -{ - /* initialize the struct parameters with default values */ - foreground_struct->foreground_memaddr = IPA_DEFAULT_VALUE; - foreground_struct->foreground_lineoff = IPA_DEFAULT_VALUE; - foreground_struct->foreground_prealpha = IPA_DEFAULT_VALUE; - foreground_struct->foreground_alpha_algorithm = IPA_FG_ALPHA_MODE_0; - foreground_struct->foreground_pf = FOREGROUND_PPF_ARGB8888; - foreground_struct->foreground_prered = IPA_DEFAULT_VALUE; - foreground_struct->foreground_pregreen = IPA_DEFAULT_VALUE; - foreground_struct->foreground_preblue = IPA_DEFAULT_VALUE; -} - -/*! - \brief initialize foreground parameters - \param[in] foreground_struct: the data needed to initialize foreground - foreground_memaddr: foreground memory base address - foreground_lineoff: foreground line offset - foreground_prealpha: foreground pre-defined alpha value - foreground_alpha_algorithm: IPA_FG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 - foreground_pf: foreground pixel format(FOREGROUND_PPF_ARGB8888,FOREGROUND_PPF_RGB888,FOREGROUND_PPF_RGB565, - FOREGROUND_PPF_ARG1555,FOREGROUND_PPF_ARGB4444,FOREGROUND_PPF_L8,FOREGROUND_PPF_AL44, - FOREGROUND_PPF_AL88,FOREGROUND_PPF_L4,FOREGROUND_PPF_A8,FOREGROUND_PPF_A4) - foreground_prered: foreground pre-defined red value - foreground_pregreen: foreground pre-defined green value - foreground_preblue: foreground pre-defined blue value - \param[out] none - \retval none -*/ -void ipa_foreground_init(ipa_foreground_parameter_struct* foreground_struct) -{ - FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ - tempflag = SET; - /* reset the TEN in order to configure the following bits */ - IPA_CTL &= ~IPA_CTL_TEN; - } - - /* foreground memory base address configuration */ - IPA_FMADDR &= ~(IPA_FMADDR_FMADDR); - IPA_FMADDR = foreground_struct->foreground_memaddr; - /* foreground line offset configuration */ - IPA_FLOFF &= ~(IPA_FLOFF_FLOFF); - IPA_FLOFF = foreground_struct->foreground_lineoff; - /* foreground pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_FPCTL &= ~(IPA_FPCTL_FPDAV|IPA_FPCTL_FAVCA|IPA_FPCTL_FPF); - IPA_FPCTL |= (foreground_struct->foreground_prealpha<<24U); - IPA_FPCTL |= foreground_struct->foreground_alpha_algorithm; - IPA_FPCTL |= foreground_struct->foreground_pf; - /* foreground pre-defined red green blue configuration */ - IPA_FPV &= ~(IPA_FPV_FPDRV|IPA_FPV_FPDGV|IPA_FPV_FPDBV); - IPA_FPV |= ((foreground_struct->foreground_prered<<16U)|(foreground_struct->foreground_pregreen<<8U) - |(foreground_struct->foreground_preblue)); - - if(SET == tempflag){ - /* restore the state of TEN */ - IPA_CTL |= IPA_CTL_TEN; - } -} - -/*! - \brief initialize the structure of IPA background parameter struct with the default values, it is - suggested that call this function after an ipa_background_parameter_struct structure is defined - \param[in] none - \param[out] background_struct: the data needed to initialize background - background_memaddr: background memory base address - background_lineoff: background line offset - background_prealpha: background pre-defined alpha value - background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_BG_ALPHA_MODE_1,IPA_BG_ALPHA_MODE_2 - background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, - BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, - BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) - background_prered: background pre-defined red value - background_pregreen: background pre-defined green value - background_preblue: background pre-defined blue value - \retval none -*/ -void ipa_background_struct_para_init(ipa_background_parameter_struct* background_struct) -{ - /* initialize the struct parameters with default values */ - background_struct->background_memaddr = IPA_DEFAULT_VALUE; - background_struct->background_lineoff = IPA_DEFAULT_VALUE; - background_struct->background_prealpha = IPA_DEFAULT_VALUE; - background_struct->background_alpha_algorithm = IPA_BG_ALPHA_MODE_0; - background_struct->background_pf = BACKGROUND_PPF_ARGB8888; - background_struct->background_prered = IPA_DEFAULT_VALUE; - background_struct->background_pregreen = IPA_DEFAULT_VALUE; - background_struct->background_preblue = IPA_DEFAULT_VALUE; -} - -/*! - \brief initialize background parameters - \param[in] background_struct: the data needed to initialize background - background_memaddr: background memory base address - background_lineoff: background line offset - background_prealpha: background pre-defined alpha value - background_alpha_algorithm: IPA_BG_ALPHA_MODE_0,IPA_FG_ALPHA_MODE_1,IPA_FG_ALPHA_MODE_2 - background_pf: background pixel format(BACKGROUND_PPF_ARGB8888,BACKGROUND_PPF_RGB888,BACKGROUND_PPF_RGB565, - BACKGROUND_PPF_ARG1555,BACKGROUND_PPF_ARGB4444,BACKGROUND_PPF_L8,BACKGROUND_PPF_AL44, - BACKGROUND_PPF_AL88,BACKGROUND_PPF_L4,BACKGROUND_PPF_A8,BACKGROUND_PPF_A4) - background_prered: background pre-defined red value - background_pregreen: background pre-defined green value - background_preblue: background pre-defined blue value - \param[out] none - \retval none -*/ -void ipa_background_init(ipa_background_parameter_struct* background_struct) -{ - FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ - tempflag = SET; - /* reset the TEN in order to configure the following bits */ - IPA_CTL &= ~IPA_CTL_TEN; - } - - /* background memory base address configuration */ - IPA_BMADDR &= ~(IPA_BMADDR_BMADDR); - IPA_BMADDR = background_struct->background_memaddr; - /* background line offset configuration */ - IPA_BLOFF &= ~(IPA_BLOFF_BLOFF); - IPA_BLOFF = background_struct->background_lineoff; - /* background pixel format pre-defined alpha, alpha calculation algorithm configuration */ - IPA_BPCTL &= ~(IPA_BPCTL_BPDAV|IPA_BPCTL_BAVCA|IPA_BPCTL_BPF); - IPA_BPCTL |= (background_struct->background_prealpha<<24U); - IPA_BPCTL |= background_struct->background_alpha_algorithm; - IPA_BPCTL |= background_struct->background_pf; - /* background pre-defined red green blue configuration */ - IPA_BPV &= ~(IPA_BPV_BPDRV|IPA_BPV_BPDGV|IPA_BPV_BPDBV); - IPA_BPV |= ((background_struct->background_prered<<16U)|(background_struct->background_pregreen<<8U) - |(background_struct->background_preblue)); - - if(SET == tempflag){ - /* restore the state of TEN */ - IPA_CTL |= IPA_CTL_TEN; - } -} - -/*! - \brief initialize the structure of IPA destination parameter struct with the default values, it is - suggested that call this function after an ipa_destination_parameter_struct structure is defined - \param[in] none - \param[out] destination_struct: the data needed to initialize destination parameter - destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, - IPA_DPF_ARGB4444,refer to ipa_dpf_enum - destination_lineoff: destination line offset - destination_prealpha: destination pre-defined alpha value - destination_prered: destination pre-defined red value - destination_pregreen: destination pre-defined green value - destination_preblue: destination pre-defined blue value - destination_memaddr: destination memory base address - image_width: width of the image to be processed - image_height: height of the image to be processed - \retval none -*/ -void ipa_destination_struct_para_init(ipa_destination_parameter_struct* destination_struct) -{ - /* initialize the struct parameters with default values */ - destination_struct->destination_pf = IPA_DPF_ARGB8888; - destination_struct->destination_lineoff = IPA_DEFAULT_VALUE; - destination_struct->destination_prealpha = IPA_DEFAULT_VALUE; - destination_struct->destination_prered = IPA_DEFAULT_VALUE; - destination_struct->destination_pregreen = IPA_DEFAULT_VALUE; - destination_struct->destination_preblue = IPA_DEFAULT_VALUE; - destination_struct->destination_memaddr = IPA_DEFAULT_VALUE; - destination_struct->image_width = IPA_DEFAULT_VALUE; - destination_struct->image_height = IPA_DEFAULT_VALUE; -} - -/*! - \brief initialize destination parameters - \param[in] destination_struct: the data needed to initialize destination parameters - destination_pf: IPA_DPF_ARGB8888,IPA_DPF_RGB888,IPA_DPF_RGB565,IPA_DPF_ARGB1555, - IPA_DPF_ARGB4444,refer to ipa_dpf_enum - destination_lineoff: destination line offset - destination_prealpha: destination pre-defined alpha value - destination_prered: destination pre-defined red value - destination_pregreen: destination pre-defined green value - destination_preblue: destination pre-defined blue value - destination_memaddr: destination memory base address - image_width: width of the image to be processed - image_height: height of the image to be processed - \param[out] none - \retval none -*/ -void ipa_destination_init(ipa_destination_parameter_struct* destination_struct) -{ - uint32_t destination_pixelformat; - FlagStatus tempflag = RESET; - if(RESET != (IPA_CTL & IPA_CTL_TEN)){ - tempflag = SET; - /* reset the TEN in order to configure the following bits */ - IPA_CTL &= ~IPA_CTL_TEN; - } - - /* destination pixel format configuration */ - IPA_DPCTL &= ~(IPA_DPCTL_DPF); - IPA_DPCTL = destination_struct->destination_pf; - destination_pixelformat = destination_struct->destination_pf; - /* destination pixel format ARGB8888 */ - switch(destination_pixelformat){ - case IPA_DPF_ARGB8888: - IPA_DPV &= ~(IPA_DPV_DPDBV_0|(IPA_DPV_DPDGV_0)|(IPA_DPV_DPDRV_0)|(IPA_DPV_DPDAV_0)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<8U) - |(destination_struct->destination_prered<<16U) - |(destination_struct->destination_prealpha<<24U)); - break; - /* destination pixel format RGB888 */ - case IPA_DPF_RGB888: - IPA_DPV &= ~(IPA_DPV_DPDBV_1|(IPA_DPV_DPDGV_1)|(IPA_DPV_DPDRV_1)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<8U) - |(destination_struct->destination_prered<<16U)); - break; - /* destination pixel format RGB565 */ - case IPA_DPF_RGB565: - IPA_DPV &= ~(IPA_DPV_DPDBV_2|(IPA_DPV_DPDGV_2)|(IPA_DPV_DPDRV_2)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<11U)); - break; - /* destination pixel format ARGB1555 */ - case IPA_DPF_ARGB1555: - IPA_DPV &= ~(IPA_DPV_DPDBV_3|(IPA_DPV_DPDGV_3)|(IPA_DPV_DPDRV_3)|(IPA_DPV_DPDAV_3)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<5U) - |(destination_struct->destination_prered<<10U) - |(destination_struct->destination_prealpha<<15U)); - break; - /* destination pixel format ARGB4444 */ - case IPA_DPF_ARGB4444: - IPA_DPV &= ~(IPA_DPV_DPDBV_4|(IPA_DPV_DPDGV_4)|(IPA_DPV_DPDRV_4)|(IPA_DPV_DPDAV_4)); - IPA_DPV = (destination_struct->destination_preblue|(destination_struct->destination_pregreen<<4U) - |(destination_struct->destination_prered<<8U) - |(destination_struct->destination_prealpha<<12U)); - break; - default: - break; - } - /* destination memory base address configuration */ - IPA_DMADDR &= ~(IPA_DMADDR_DMADDR); - IPA_DMADDR = destination_struct->destination_memaddr; - /* destination line offset configuration */ - IPA_DLOFF &= ~(IPA_DLOFF_DLOFF); - IPA_DLOFF =destination_struct->destination_lineoff; - /* image size configuration */ - IPA_IMS &= ~(IPA_IMS_HEIGHT|IPA_IMS_WIDTH); - IPA_IMS |= ((destination_struct->image_width<<16U)|(destination_struct->image_height)); - - if(SET == tempflag){ - /* restore the state of TEN */ - IPA_CTL |= IPA_CTL_TEN; - } -} - -/*! - \brief initialize IPA foreground LUT parameters - \param[in] fg_lut_num: foreground LUT number of pixel - \param[in] fg_lut_pf: foreground LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) - \param[in] fg_lut_addr: foreground LUT memory base address - \param[out] none - \retval none -*/ -void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr) -{ - FlagStatus tempflag = RESET; - if(RESET != (IPA_FPCTL & IPA_FPCTL_FLLEN)){ - tempflag = SET; - /* reset the FLLEN in order to configure the following bits */ - IPA_FPCTL &= ~IPA_FPCTL_FLLEN; - } - - /* foreground LUT number of pixel configuration */ - IPA_FPCTL |= ((uint32_t)fg_lut_num<<8U); - /* foreground LUT pixel format configuration */ - if(IPA_LUT_PF_RGB888 == fg_lut_pf){ - IPA_FPCTL |= IPA_FPCTL_FLPF; - }else{ - IPA_FPCTL &= ~(IPA_FPCTL_FLPF); - } - /* foreground LUT memory base address configuration */ - IPA_FLMADDR &= ~(IPA_FLMADDR_FLMADDR); - IPA_FLMADDR = fg_lut_addr; - - if(SET == tempflag){ - /* restore the state of FLLEN */ - IPA_FPCTL |= IPA_FPCTL_FLLEN; - } -} - -/*! - \brief initialize IPA background LUT parameters - \param[in] bg_lut_num: background LUT number of pixel - \param[in] bg_lut_pf: background LUT pixel format(IPA_LUT_PF_ARGB8888, IPA_LUT_PF_RGB888) - \param[in] bg_lut_addr: background LUT memory base address - \param[out] none - \retval none -*/ -void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr) -{ - FlagStatus tempflag = RESET; - if(RESET != (IPA_BPCTL & IPA_BPCTL_BLLEN)){ - tempflag = SET; - /* reset the BLLEN in order to configure the following bits */ - IPA_BPCTL &= ~IPA_BPCTL_BLLEN; - } - - /* background LUT number of pixel configuration */ - IPA_BPCTL |= ((uint32_t)bg_lut_num<<8U); - /* background LUT pixel format configuration */ - if(IPA_LUT_PF_RGB888 == bg_lut_pf){ - IPA_BPCTL |= IPA_BPCTL_BLPF; - }else{ - IPA_BPCTL &= ~(IPA_BPCTL_BLPF); - } - /* background LUT memory base address configuration */ - IPA_BLMADDR &= ~(IPA_BLMADDR_BLMADDR); - IPA_BLMADDR = bg_lut_addr; - - if(SET == tempflag){ - /* restore the state of BLLEN */ - IPA_BPCTL |= IPA_BPCTL_BLLEN; - } -} - -/*! - \brief configure IPA line mark - \param[in] line_num: line number - \param[out] none - \retval none -*/ -void ipa_line_mark_config(uint16_t line_num) -{ - IPA_LM &= ~(IPA_LM_LM); - IPA_LM = line_num; -} - -/*! - \brief inter-timer enable or disable - \param[in] timer_cfg: IPA_INTER_TIMER_ENABLE,IPA_INTER_TIMER_DISABLE - \param[out] none - \retval none -*/ -void ipa_inter_timer_config(uint8_t timer_cfg) -{ - if(IPA_INTER_TIMER_ENABLE == timer_cfg){ - IPA_ITCTL |= IPA_ITCTL_ITEN; - }else{ - IPA_ITCTL &= ~(IPA_ITCTL_ITEN); - } -} - -/*! - \brief configure the number of clock cycles interval - \param[in] clk_num: the number of clock cycles - \param[out] none - \retval none -*/ -void ipa_interval_clock_num_config(uint8_t clk_num) -{ - /* NCCI[7:0] bits have no meaning if ITEN is '0' */ - IPA_ITCTL &= ~(IPA_ITCTL_NCCI); - IPA_ITCTL |= ((uint32_t)clk_num<<8U); -} - -/*! - \brief get IPA flag status in IPA_INTF register - \param[in] flag: IPA flags - one or more parameters can be selected which are shown as below: - \arg IPA_FLAG_TAE: transfer access error interrupt flag - \arg IPA_FLAG_FTF: full transfer finish interrupt flag - \arg IPA_FLAG_TLM: transfer line mark interrupt flag - \arg IPA_FLAG_LAC: LUT access conflict interrupt flag - \arg IPA_FLAG_LLF: LUT loading finish interrupt flag - \arg IPA_FLAG_WCF: wrong configuration interrupt flag - \param[out] none - \retval none -*/ -FlagStatus ipa_flag_get(uint32_t flag) -{ - if(RESET != (IPA_INTF & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear IPA flag in IPA_INTF register - \param[in] flag: IPA flags - one or more parameters can be selected which are shown as below: - \arg IPA_FLAG_TAE: transfer access error interrupt flag - \arg IPA_FLAG_FTF: full transfer finish interrupt flag - \arg IPA_FLAG_TLM: transfer line mark interrupt flag - \arg IPA_FLAG_LAC: LUT access conflict interrupt flag - \arg IPA_FLAG_LLF: LUT loading finish interrupt flag - \arg IPA_FLAG_WCF: wrong configuration interrupt flag - \param[out] none - \retval none -*/ -void ipa_flag_clear(uint32_t flag) -{ - IPA_INTC |= (flag); -} - -/*! - \brief enable IPA interrupt - \param[in] int_flag: IPA interrupt flags - one or more parameters can be selected which are shown as below: - \arg IPA_INT_TAE: transfer access error interrupt - \arg IPA_INT_FTF: full transfer finish interrupt - \arg IPA_INT_TLM: transfer line mark interrupt - \arg IPA_INT_LAC: LUT access conflict interrupt - \arg IPA_INT_LLF: LUT loading finish interrupt - \arg IPA_INT_WCF: wrong configuration interrupt - \param[out] none - \retval none -*/ -void ipa_interrupt_enable(uint32_t int_flag) -{ - IPA_CTL |= (int_flag); -} - -/*! - \brief disable IPA interrupt - \param[in] int_flag: IPA interrupt flags - one or more parameters can be selected which are shown as below: - \arg IPA_INT_TAE: transfer access error interrupt - \arg IPA_INT_FTF: full transfer finish interrupt - \arg IPA_INT_TLM: transfer line mark interrupt - \arg IPA_INT_LAC: LUT access conflict interrupt - \arg IPA_INT_LLF: LUT loading finish interrupt - \arg IPA_INT_WCF: wrong configuration interrupt - \param[out] none - \retval none -*/ -void ipa_interrupt_disable(uint32_t int_flag) -{ - IPA_CTL &= ~(int_flag); -} - -/*! - \brief get IPA interrupt flag - \param[in] int_flag: IPA interrupt flag flags - one or more parameters can be selected which are shown as below: - \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag - \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag - \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag - \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag - \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag - \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag - \param[out] none - \retval none -*/ -FlagStatus ipa_interrupt_flag_get(uint32_t int_flag) -{ - if(0U != (IPA_INTF & int_flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear IPA interrupt flag - \param[in] int_flag: IPA interrupt flag flags - one or more parameters can be selected which are shown as below: - \arg IPA_INT_FLAG_TAE: transfer access error interrupt flag - \arg IPA_INT_FLAG_FTF: full transfer finish interrupt flag - \arg IPA_INT_FLAG_TLM: transfer line mark interrupt flag - \arg IPA_INT_FLAG_LAC: LUT access conflict interrupt flag - \arg IPA_INT_FLAG_LLF: LUT loading finish interrupt flag - \arg IPA_INT_FLAG_WCF: wrong configuration interrupt flag - \param[out] none - \retval none -*/ -void ipa_interrupt_flag_clear(uint32_t int_flag) -{ - IPA_INTC |= (int_flag); -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c deleted file mode 100644 index 218a070ef4..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c +++ /dev/null @@ -1,126 +0,0 @@ -/*! - \file gd32f4xx_iref.c - \brief IREF driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_iref.h" - -/*! - \brief deinit IREF - \param[in] none - \param[out] none - \retval none -*/ -void iref_deinit(void) -{ - rcu_periph_reset_enable(RCU_IREFRST); - rcu_periph_reset_disable(RCU_IREFRST); -} - -/*! - \brief enable IREF - \param[in] none - \param[out] none - \retval none -*/ -void iref_enable(void) -{ - IREF_CTL |= IREF_CTL_CREN; -} - -/*! - \brief disable IREF - \param[in] none - \param[out] none - \retval none -*/ -void iref_disable(void) -{ - IREF_CTL &= ~IREF_CTL_CREN; -} - -/*! - \brief set IREF mode - \param[in] step - \arg IREF_MODE_LOW_POWER: 1uA step - \arg IREF_MODE_HIGH_CURRENT: 8uA step - \param[out] none - \retval none -*/ -void iref_mode_set(uint32_t step) -{ - IREF_CTL &= ~IREF_CTL_SSEL; - IREF_CTL |= step; -} - -/*! - \brief set IREF precision_trim_value - \param[in] precisiontrim - \arg IREF_CUR_PRECISION_TRIM_X(x=0..31): (-15+ x)% - \param[out] none - \retval none -*/ -void iref_precision_trim_value_set(uint32_t precisiontrim) -{ - IREF_CTL &= ~IREF_CTL_CPT; - IREF_CTL |= precisiontrim; -} - -/*! - \brief set IREF sink mode - \param[in] sinkmode - \arg IREF_SOURCE_CURRENT : source current. - \arg IREF_SINK_CURRENT: sink current - \param[out] none - \retval none -*/ -void iref_sink_set(uint32_t sinkmode) -{ - IREF_CTL &= ~IREF_CTL_SCMOD; - IREF_CTL |= sinkmode; -} - -/*! - \brief set IREF step data - \param[in] stepdata - \arg IREF_CUR_STEP_DATA_X:(x=0..63): step*x - \param[out] none - \retval none -*/ - -void iref_step_data_config(uint32_t stepdata) -{ - IREF_CTL &= ~IREF_CTL_CSDT; - IREF_CTL |= stepdata; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c deleted file mode 100644 index c826722f13..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c +++ /dev/null @@ -1,174 +0,0 @@ -/*! - \file gd32f4xx_misc.c - \brief MISC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_misc.h" - -/*! - \brief set the priority group - \param[in] nvic_prigroup: the NVIC priority group - \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority - \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority - \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority - \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority - \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority - \param[out] none - \retval none -*/ -void nvic_priority_group_set(uint32_t nvic_prigroup) -{ - /* set the priority group value */ - SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup; -} - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set - \param[in] nvic_irq_sub_priority: the subpriority needed to set - \param[out] none - \retval none -*/ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, - uint8_t nvic_irq_sub_priority) -{ - uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; - /* use the priority group value to get the temp_pre and the temp_sub */ - if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ - temp_pre=0U; - temp_sub=0x4U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ - temp_pre=1U; - temp_sub=0x3U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ - temp_pre=2U; - temp_sub=0x2U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ - temp_pre=3U; - temp_sub=0x1U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ - temp_pre=4U; - temp_sub=0x0U; - }else{ - nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre=2U; - temp_sub=0x2U; - } - /* get the temp_priority to fill the NVIC->IP register */ - temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); - temp_priority = temp_priority << 0x04U; - NVIC->IP[nvic_irq] = (uint8_t)temp_priority; - /* enable the selected IRQ */ - NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(uint8_t nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - \arg NVIC_VECTTAB_RAM: RAM base address - \are NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c deleted file mode 100644 index 05f4cd7c3a..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c +++ /dev/null @@ -1,391 +0,0 @@ -/*! - \file gd32f4xx_pmu.c - \brief PMU driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_pmu.h" -#include "core_cm4.h" -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - \arg PMU_LVDT_0: voltage threshold is 2.1V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.6V - \arg PMU_LVDT_4: voltage threshold is 2.7V - \arg PMU_LVDT_5: voltage threshold is 2.9V - \arg PMU_LVDT_6: voltage threshold is 3.0V - \arg PMU_LVDT_7: voltage threshold is 3.1V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to pmu_lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief select LDO output voltage - this bit set by software when the main PLL closed, before closing PLL, change the system clock to IRC16M or HXTAL - \param[in] ldo_output: - \arg PMU_LDOVS_LOW: low-driver mode enable in deep-sleep mode - \arg PMU_LDOVS_MID: mid-driver mode disable in deep-sleep mode - \arg PMU_LDOVS_HIGH: high-driver mode disable in deep-sleep mode - \param[out] none - \retval none -*/ -void pmu_ldo_output_select(uint32_t ldo_output) -{ - PMU_CTL &= ~PMU_CTL_LDOVS; - PMU_CTL |= ldo_output; -} - -/*! - \brief enable low-driver mode in deep-sleep mode - \param[in] lowdr_mode: - \arg PMU_LOWDRIVER_ENABLE: enable low-driver mode in deep-sleep mode - \arg PMU_LOWDRIVER_DISABLE: disable low-driver mode in deep-sleep mode - \param[out] none - \retval none -*/ -void pmu_low_driver_mode_enable(uint32_t lowdr_mode) -{ - PMU_CTL &= ~PMU_CTL_LDEN; - PMU_CTL |= lowdr_mode; -} - -/*! - \brief switch high-driver mode - this bit set by software only when IRC16M or HXTAL used as system clock - \param[in] highdr_switch: - \arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch - \arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch - \param[out] none - \retval none -*/ -void pmu_highdriver_switch_select(uint32_t highdr_switch) -{ - /* wait for HDRF flag set */ - while(SET != pmu_flag_get(PMU_FLAG_HDRF)){ - } - PMU_CTL &= ~PMU_CTL_HDS; - PMU_CTL |= highdr_switch; -} - -/*! - \brief enable high-driver mode - this bit set by software only when IRC16M or HXTAL used as system clock - \param[in] none - \param[out] none - \retval none -*/ -void pmu_highdriver_mode_enable(void) -{ - PMU_CTL |= PMU_CTL_HDEN; -} - -/*! - \brief disable high-driver mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_highdriver_mode_disable(void) -{ - PMU_CTL &= ~PMU_CTL_HDEN; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief low-driver mode when use low power LDO - \param[in] mode: - \arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO - \arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO - \param[out] none - \retval none -*/ -void pmu_lowdriver_lowpower_config(uint32_t mode) -{ - PMU_CTL &= ~PMU_CTL_LDLP; - PMU_CTL |= mode; -} - -/*! - \brief low-driver mode when use normal power LDO - \param[in] mode: - \arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO - \arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO - \param[out] none - \retval none -*/ -void pmu_lowdriver_normalpower_config(uint32_t mode) -{ - PMU_CTL &= ~PMU_CTL_LDNP; - PMU_CTL |= mode; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo - \arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) -{ - static uint32_t reg_snap[ 4 ]; - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - reg_snap[ 0 ] = REG32( 0xE000E010U ); - reg_snap[ 1 ] = REG32( 0xE000E100U ); - reg_snap[ 2 ] = REG32( 0xE000E104U ); - reg_snap[ 3 ] = REG32( 0xE000E108U ); - - REG32( 0xE000E010U ) &= 0x00010004U; - REG32( 0xE000E180U ) = 0XFF7FF831U; - REG32( 0xE000E184U ) = 0XBFFFF8FFU; - REG32( 0xE000E188U ) = 0xFFFFEFFFU; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ - __WFI(); - }else{ - __SEV(); - __WFE(); - __WFE(); - } - - REG32( 0xE000E010U ) = reg_snap[ 0 ] ; - REG32( 0xE000E100U ) = reg_snap[ 1 ] ; - REG32( 0xE000E104U ) = reg_snap[ 2 ] ; - REG32( 0xE000E108U ) = reg_snap[ 3 ] ; - - /* reset sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set sleepdeep bit of Cortex-M4 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief backup SRAM LDO on - \param[in] bkp_ldo: - \arg PMU_BLDOON_OFF: backup SRAM LDO closed - \arg PMU_BLDOON_ON: open the backup SRAM LDO - \param[out] none - \retval none -*/ -void pmu_backup_ldo_config(uint32_t bkp_ldo) -{ - PMU_CS &= ~PMU_CS_BLDOON; - PMU_CS |= bkp_ldo; -} - -/*! - \brief reset flag bit - \param[in] flag_reset: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_reset(uint32_t flag_reset) -{ - switch(flag_reset){ - case PMU_FLAG_RESET_WAKEUP: - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - break; - case PMU_FLAG_RESET_STANDBY: - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - break; - default : - break; - } -} - -/*! - \brief get flag state - \param[in] pmu_flag: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \arg PMU_FLAG_BLDORF: backup SRAM LDO ready flag - \arg PMU_FLAG_LDOVSRF: LDO voltage select ready flag - \arg PMU_FLAG_HDRF: high-driver ready flag - \arg PMU_FLAG_HDSRF: high-driver switch ready flag - \arg PMU_FLAG_LDRF: low-driver mode ready flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t pmu_flag) -{ - if(PMU_CS & pmu_flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief enable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief enable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(void) -{ - PMU_CS |= PMU_CS_WUPEN; -} - -/*! - \brief disable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(void) -{ - PMU_CS &= ~PMU_CS_WUPEN; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c deleted file mode 100644 index aecc895a09..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c +++ /dev/null @@ -1,1329 +0,0 @@ -/*! - \file gd32f4xx_rcu.c - \brief RCU driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_rcu.h" - -/* define clock source */ -#define SEL_IRC16M ((uint16_t)0U) /* IRC16M is selected as CK_SYS */ -#define SEL_HXTAL ((uint16_t)1U) /* HXTAL is selected as CK_SYS */ -#define SEL_PLLP ((uint16_t)2U) /* PLLP is selected as CK_SYS */ -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000fffffU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x0fffffffU) - -/* RCU IRC16M adjust value mask and offset*/ -#define RCU_IRC16M_ADJUST_MASK ((uint8_t)0x1FU) -#define RCU_IRC16M_ADJUST_OFFSET ((uint32_t)3U) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC16M */ - RCU_CTL |= RCU_CTL_IRC16MEN; - rcu_osci_stab_wait(RCU_IRC16M); - /* reset CFG0 register */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_RTCDIV | RCU_CFG0_CKOUT0SEL | RCU_CFG0_I2SSEL | RCU_CFG0_CKOUT0DIV | - RCU_CFG0_CKOUT1DIV | RCU_CFG0_CKOUT1SEL); - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN | RCU_CTL_PLLI2SEN - | RCU_CTL_PLLSAIEN); - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - /* reset PLL register */ - RCU_PLL = 0x24003010U; - /* reset PLLI2S register */ - RCU_PLLI2S = 0x24003000U; - /* reset PLLSAI register */ - RCU_PLLSAI = 0x24003010U; - /* reset INT register */ - RCU_INT = 0x00000000U; - /* reset CFG1 register */ - RCU_CFG1 &= ~(RCU_CFG1_PLLSAIRDIV | RCU_CFG1_TIMERSEL); -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock - \arg RCU_CRC: CRC clock - \arg RCU_BKPSRAM: BKPSRAM clock - \arg RCU_TCMSRAM: TCMSRAM clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_IPA: IPA clock - \arg RCU_ENET: ENET clock - \arg RCU_ENETTX: ENETTX clock - \arg RCU_ENETRX: ENETRX clock - \arg RCU_ENETPTP: ENETPTP clock - \arg RCU_USBHS: USBHS clock - \arg RCU_USBHSULPI: USBHSULPI clock - \arg RCU_DCI: DCI clock - \arg RCU_TRNG: TRNG clock - \arg RCU_USBFS: USBFS clock - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock - \arg RCU_SDIO: SDIO clock - \arg RCU_SYSCFG: SYSCFG clock - \arg RCU_TLI: TLI clock - \arg RCU_CTC: CTC clock - \arg RCU_IREF: IREF clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E,F,G,H,I): GPIO ports clock - \arg RCU_CRC: CRC clock - \arg RCU_BKPSRAM: BKPSRAM clock - \arg RCU_TCMSRAM: TCMSRAM clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_IPA: IPA clock - \arg RCU_ENET: ENET clock - \arg RCU_ENETTX: ENETTX clock - \arg RCU_ENETRX: ENETRX clock - \arg RCU_ENETPTP: ENETPTP clock - \arg RCU_USBHS: USBHS clock - \arg RCU_USBHSULPI: USBHSULPI clock - \arg RCU_DCI: DCI clock - \arg RCU_TRNG: TRNG clock - \arg RCU_USBFS: USBFS clock - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx (x=0,1,2,5): USART clock - \arg RCU_UARTx (x=3,4,6,7): UART clock - \arg RCU_I2Cx (x=0,1,2): I2C clock - \arg RCU_CANx (x=0,1): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1,2): ADC clock - \arg RCU_SDIO: SDIO clock - \arg RCU_SYSCFG: SYSCFG clock - \arg RCU_TLI: TLI clock - \arg RCU_CTC: CTC clock - \arg RCU_IREF: IREF clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock - \arg RCU_CRC_SLP: CRC clock - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM0_SLP: SRAM0 clock - \arg RCU_SRAM1_SLP: SRAM1 clock - \arg RCU_BKPSRAM: BKPSRAM clock - \arg RCU_SRAM2_SLP: SRAM2 clock - \arg RCU_DMAx_SLP (x=0,1): DMA clock - \arg RCU_IPA_SLP: IPA clock - \arg RCU_ENET_SLP: ENET clock - \arg RCU_ENETTX_SLP: ENETTX clock - \arg RCU_ENETRX_SLP: ENETRX clock - \arg RCU_ENETPTP_SLP: ENETPTP clock - \arg RCU_USBHS_SLP: USBHS clock - \arg RCU_USBHSULPI_SLP: USBHSULPI clock - \arg RCU_DCI_SLP: DCI clock - \arg RCU_TRNG_SLP: TRNG clock - \arg RCU_USBFS_SLP: USBFS clock - \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock - \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock - \arg RCU_PMU_SLP: PMU clock - \arg RCU_DAC_SLP: DAC clock - \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock - \arg RCU_SDIO_SLP: SDIO clock - \arg RCU_SYSCFG_SLP: SYSCFG clock - \arg RCU_TLI_SLP: TLI clock - \arg RCU_CTC_SLP: CTC clock - \arg RCU_IREF_SLP: IREF clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx_SLP (x=A,B,C,D,E,F,G,H,I): GPIO ports clock - \arg RCU_CRC_SLP: CRC clock - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM0_SLP: SRAM0 clock - \arg RCU_SRAM1_SLP: SRAM1 clock - \arg RCU_BKPSRAM: BKPSRAM clock - \arg RCU_SRAM2_SLP: SRAM2 clock - \arg RCU_DMAx_SLP (x=0,1): DMA clock - \arg RCU_IPA_SLP: IPA clock - \arg RCU_ENET_SLP: ENET clock - \arg RCU_ENETTX_SLP: ENETTX clock - \arg RCU_ENETRX_SLP: ENETRX clock - \arg RCU_ENETPTP_SLP: ENETPTP clock - \arg RCU_USBHS_SLP: USBHS clock - \arg RCU_USBHSULPI_SLP: USBHSULPI clock - \arg RCU_DCI_SLP: DCI clock - \arg RCU_TRNG_SLP: TRNG clock - \arg RCU_USBFS_SLP: USBFS clock - \arg RCU_EXMC_SLP: EXMC clock - \arg RCU_TIMERx_SLP (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): TIMER clock - \arg RCU_WWDGT_SLP: WWDGT clock - \arg RCU_SPIx_SLP (x=0,1,2,3,4,5): SPI clock - \arg RCU_USARTx_SLP (x=0,1,2,5): USART clock - \arg RCU_UARTx_SLP (x=3,4,6,7): UART clock - \arg RCU_I2Cx_SLP (x=0,1,2): I2C clock - \arg RCU_CANx_SLP (x=0,1): CAN clock - \arg RCU_PMU_SLP: PMU clock - \arg RCU_DAC_SLP: DAC clock - \arg RCU_RTC_SLP: RTC clock - \arg RCU_ADCx_SLP (x=0,1,2): ADC clock - \arg RCU_SDIO_SLP: SDIO clock - \arg RCU_SYSCFG_SLP: SYSCFG clock - \arg RCU_TLI_SLP: TLI clock - \arg RCU_CTC_SLP: CTC clock - \arg RCU_IREF_SLP: IREF clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports - \arg RCU_CRCRST: reset CRC - \arg RCU_DMAxRST (x=0,1): reset DMA - \arg RCU_IPARST: reset IPA - \arg RCU_ENETRST: reset ENET - \arg RCU_USBHSRST: reset USBHS - \arg RCU_DCIRST: reset DCI - \arg RCU_TRNGRST: reset TRNG - \arg RCU_USBFSRST: reset USBFS - \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC - \arg RCU_SDIORST: reset SDIO - \arg RCU_SYSCFGRST: reset SYSCFG - \arg RCU_TLIRST: reset TLI - \arg RCU_CTCRST: reset CTC - \arg RCU_IREFRST: reset IREF - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E,F,G,H,I): reset GPIO ports - \arg RCU_CRCRST: reset CRC - \arg RCU_DMAxRST (x=0,1): reset DMA - \arg RCU_IPARST: reset IPA - \arg RCU_ENETRST: reset ENET - \arg RCU_USBHSRST: reset USBHS - \arg RCU_DCIRST: reset DCI - \arg RCU_TRNGRST: reset TRNG - \arg RCU_USBFSRST: reset USBFS - \arg RCU_EXMCRST: reset EXMC - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2,3,4,5): reset SPI - \arg RCU_USARTxRST (x=0,1,2,5): reset USART - \arg RCU_UARTxRST (x=3,4,6,7): reset UART - \arg RCU_I2CxRST (x=0,1,2): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCRST (x=0,1,2): reset ADC - \arg RCU_SDIORST: reset SDIO - \arg RCU_SYSCFGRST: reset SYSCFG - \arg RCU_TLIRST: reset TLI - \arg RCU_CTCRST: reset CTC - \arg RCU_IREFRST: reset IREF - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC16M: select CK_IRC16M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLLP: select CK_PLLP as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - reg &= ~RCU_CFG0_SCS; - RCU_CFG0 = (reg | ck_sys); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC16M: CK_IRC16M is selected as the CK_SYS source - \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source - \arg RCU_SCSS_PLLP: CK_PLLP is selected as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the AHBPSC bits and set according to ck_ahb */ - reg &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (reg | ck_ahb); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the APB1PSC and set according to ck_apb1 */ - reg &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (reg | ck_apb1); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the APB2PSC and set according to ck_apb2 */ - reg &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (reg | ck_apb2); -} - -/*! - \brief configure the CK_OUT0 clock source and divider - \param[in] ckout0_src: CK_OUT0 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT0SRC_IRC16M: IRC16M selected - \arg RCU_CKOUT0SRC_LXTAL: LXTAL selected - \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT0SRC_PLLP: PLLP selected - \param[in] ckout0_div: CK_OUT0 divider - \arg RCU_CKOUT0_DIVx(x=1,2,3,4,5): CK_OUT0 is divided by x - \param[out] none - \retval none -*/ -void rcu_ckout0_config(uint32_t ckout0_src, uint32_t ckout0_div) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the CKOUT0SRC, CKOUT0DIV and set according to ckout0_src and ckout0_div */ - reg &= ~(RCU_CFG0_CKOUT0SEL | RCU_CFG0_CKOUT0DIV ); - RCU_CFG0 = (reg | ckout0_src | ckout0_div); -} - -/*! - \brief configure the CK_OUT1 clock source and divider - \param[in] ckout1_src: CK_OUT1 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT1SRC_SYSTEMCLOCK: system clock selected - \arg RCU_CKOUT1SRC_PLLI2SR: PLLI2SR selected - \arg RCU_CKOUT1SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT1SRC_PLLP: PLLP selected - \param[in] ckout1_div: CK_OUT1 divider - \arg RCU_CKOUT1_DIVx(x=1,2,3,4,5): CK_OUT1 is divided by x - \param[out] none - \retval none -*/ -void rcu_ckout1_config(uint32_t ckout1_src, uint32_t ckout1_div) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the CKOUT1SRC, CKOUT1DIV and set according to ckout1_src and ckout1_div */ - reg &= ~(RCU_CFG0_CKOUT1SEL | RCU_CFG0_CKOUT1DIV); - RCU_CFG0 = (reg | ckout1_src | ckout1_div); -} - -/*! - \brief configure the main PLL clock - \param[in] pll_src: PLL clock source selection - \arg RCU_PLLSRC_IRC16M: select IRC16M as PLL source clock - \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock - \param[in] pll_psc: the PLL VCO source clock prescaler - \arg this parameter should be selected between 2 and 63 - \param[in] pll_n: the PLL VCO clock multi factor - \arg this parameter should be selected between 64 and 500 - \param[in] pll_p: the PLLP output frequency division factor from PLL VCO clock - \arg this parameter should be selected 2,4,6,8 - \param[in] pll_q: the PLL Q output frequency division factor from PLL VCO clock - \arg this parameter should be selected between 2 and 15 - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_pll_config(uint32_t pll_src, uint32_t pll_psc, uint32_t pll_n, uint32_t pll_p, uint32_t pll_q) -{ - uint32_t ss_modulation_inc; - uint32_t ss_modulation_reg; - - ss_modulation_inc = 0U; - ss_modulation_reg = RCU_PLLSSCTL; - - /* calculate the minimum factor of PLLN */ - if((ss_modulation_reg & RCU_PLLSSCTL_SSCGON) == RCU_PLLSSCTL_SSCGON){ - if((ss_modulation_reg & RCU_SS_TYPE_DOWN) == RCU_SS_TYPE_DOWN){ - ss_modulation_inc += RCU_SS_MODULATION_DOWN_INC; - }else{ - ss_modulation_inc += RCU_SS_MODULATION_CENTER_INC; - } - } - - /* check the function parameter */ - if(CHECK_PLL_PSC_VALID(pll_psc) && CHECK_PLL_N_VALID(pll_n,ss_modulation_inc) && - CHECK_PLL_P_VALID(pll_p) && CHECK_PLL_Q_VALID(pll_q)){ - RCU_PLL = pll_psc | (pll_n << 6) | (((pll_p >> 1) - 1U) << 16) | - (pll_src) | (pll_q << 24); - }else{ - /* return status */ - return ERROR; - } - - /* return status */ - return SUCCESS; -} - -/*! - \brief configure the PLLI2S clock - \param[in] plli2s_n: the PLLI2S VCO clock multi factor - \arg this parameter should be selected between 50 and 500 - \param[in] plli2s_r: the PLLI2S R output frequency division factor from PLLI2S VCO clock - \arg this parameter should be selected between 2 and 7 - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_plli2s_config(uint32_t plli2s_n, uint32_t plli2s_r) -{ - /* check the function parameter */ - if(CHECK_PLLI2S_N_VALID(plli2s_n) && CHECK_PLLI2S_R_VALID(plli2s_r)){ - RCU_PLLI2S = (plli2s_n << 6) | (plli2s_r << 28); - }else{ - /* return status */ - return ERROR; - } - - /* return status */ - return SUCCESS; -} - -/*! - \brief configure the PLLSAI clock - \param[in] pllsai_n: the PLLSAI VCO clock multi factor - \arg this parameter should be selected between 50 and 500 - \param[in] pllsai_p: the PLLSAI P output frequency division factor from PLL VCO clock - \arg this parameter should be selected 2,4,6,8 - \param[in] pllsai_r: the PLLSAI R output frequency division factor from PLL VCO clock - \arg this parameter should be selected between 2 and 7 - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_pllsai_config(uint32_t pllsai_n, uint32_t pllsai_p, uint32_t pllsai_r) -{ - /* check the function parameter */ - if(CHECK_PLLSAI_N_VALID(pllsai_n) && CHECK_PLLSAI_P_VALID(pllsai_p) && CHECK_PLLSAI_R_VALID(pllsai_r)){ - RCU_PLLSAI = (pllsai_n << 6U) | (((pllsai_p >> 1U) - 1U) << 16U) | (pllsai_r << 28U); - }else{ - /* return status */ - return ERROR; - } - - /* return status */ - return SUCCESS; -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC32K: CK_IRC32K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_RTCDIV: CK_HXTAL/RTCDIV selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - uint32_t reg; - - reg = RCU_BDCTL; - /* reset the RTCSRC bits and set according to rtc_clock_source */ - reg &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL = (reg | rtc_clock_source); -} - -/*! - \brief configure the frequency division of RTC clock when HXTAL was selected as its clock source - \param[in] rtc_div: RTC clock frequency division - only one parameter can be selected which is shown as below: - \arg RCU_RTC_HXTAL_NONE: no clock for RTC - \arg RCU_RTC_HXTAL_DIVx: RTCDIV clock select CK_HXTAL/x, x = 2....31 - \param[out] none - \retval none -*/ -void rcu_rtc_div_config(uint32_t rtc_div) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the RTCDIV bits and set according to rtc_div value */ - reg &= ~RCU_CFG0_RTCDIV; - RCU_CFG0 = (reg | rtc_div); -} - - -/*! - \brief configure the I2S clock source selection - \param[in] i2s_clock_source: I2S clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2SSRC_PLLI2S: CK_PLLI2S selected as I2S source clock - \arg RCU_I2SSRC_I2S_CKIN: external i2s_ckin pin selected as I2S source clock - \param[out] none - \retval none -*/ -void rcu_i2s_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the I2SSEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG0_I2SSEL; - RCU_CFG0 = (reg | i2s_clock_source); -} - -/*! - \brief configure the CK48M clock source selection - \param[in] ck48m_clock_source: CK48M clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CK48MSRC_PLL48M: CK_PLL48M selected as CK48M source clock - \arg RCU_CK48MSRC_IRC48M: CK_IRC48M selected as CK48M source clock - \param[out] none - \retval none -*/ -void rcu_ck48m_clock_config(uint32_t ck48m_clock_source) -{ - uint32_t reg; - - reg = RCU_ADDCTL; - /* reset the CK48MSEL bit and set according to i2s_clock_source */ - reg &= ~RCU_ADDCTL_CK48MSEL; - RCU_ADDCTL = (reg | ck48m_clock_source); -} - -/*! - \brief configure the PLL48M clock source selection - \param[in] pll48m_clock_source: PLL48M clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLL48MSRC_PLLQ: CK_PLLQ selected as PLL48M source clock - \arg RCU_PLL48MSRC_PLLSAIP: CK_PLLSAIP selected as PLL48M source clock - \param[out] none - \retval none -*/ -void rcu_pll48m_clock_config(uint32_t pll48m_clock_source) -{ - uint32_t reg; - - reg = RCU_ADDCTL; - /* reset the PLL48MSEL bit and set according to pll48m_clock_source */ - reg &= ~RCU_ADDCTL_PLL48MSEL; - RCU_ADDCTL = (reg | pll48m_clock_source); -} - -/*! - \brief configure the TIMER clock prescaler selection - \param[in] timer_clock_prescaler: TIMER clock selection - only one parameter can be selected which is shown as below: - \arg RCU_TIMER_PSC_MUL2: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB) - or 0b100(CK_APBx = CK_AHB/2), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is twice the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 2 x CK_APB1; - TIMER in APB2 domain: CK_TIMERx = 2 x CK_APB2) - \arg RCU_TIMER_PSC_MUL4: if APB1PSC/APB2PSC in RCU_CFG0 register is 0b0xx(CK_APBx = CK_AHB), - 0b100(CK_APBx = CK_AHB/2), or 0b101(CK_APBx = CK_AHB/4), the TIMER clock is equal to CK_AHB(CK_TIMERx = CK_AHB). - or else, the TIMER clock is four timers the corresponding APB clock (TIMER in APB1 domain: CK_TIMERx = 4 x CK_APB1; - TIMER in APB2 domain: CK_TIMERx = 4 x CK_APB2) - \param[out] none - \retval none -*/ -void rcu_timer_clock_prescaler_config(uint32_t timer_clock_prescaler) -{ - /* configure the TIMERSEL bit and select the TIMER clock prescaler */ - if(timer_clock_prescaler == RCU_TIMER_PSC_MUL2){ - RCU_CFG1 &= timer_clock_prescaler; - }else{ - RCU_CFG1 |= timer_clock_prescaler; - } -} - -/*! - \brief configure the PLLSAIR divider used as input of TLI - \param[in] pllsai_r_div: PLLSAIR divider used as input of TLI - only one parameter can be selected which is shown as below: - \arg RCU_PLLSAIR_DIVx(x=2,4,8,16): PLLSAIR divided x used as input of TLI - \param[out] none - \retval none -*/ -void rcu_tli_clock_div_config(uint32_t pllsai_r_div) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the PLLSAIRDIV bit and set according to pllsai_r_div */ - reg &= ~RCU_CFG1_PLLSAIRDIV; - RCU_CFG1 = (reg | pllsai_r_div); -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC16MSTB: IRC16M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLLI2SSTB: PLLI2S stabilization flag - \arg RCU_FLAG_PLLSAISTB: PLLSAI stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC32KSTB: IRC32K stabilization flag - \arg RCU_FLAG_IRC48MSTB: IRC48M stabilization flag - \arg RCU_FLAG_BORRST: BOR reset flags - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: Power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval none -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB: IRC32K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC16MSTB: IRC16M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLI2SSTB: PLLI2S stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSAISTB: PLLSAI stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \arg RCU_INT_FLAG_IRC48MSTB: IRC48M stabilization interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC32KSTB_CLR: IRC32K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC16MSTB_CLR: IRC16M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLI2SSTB_CLR: PLLI2S stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSAISTB_CLR: PLLSAI stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \arg RCU_INT_FLAG_IRC48MSTB_CLR: IRC48M stabilization interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag) -{ - RCU_REG_VAL(int_flag) |= BIT(RCU_BIT_POS(int_flag)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt enable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt enable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) |= BIT(RCU_BIT_POS(interrupt)); -} - - -/*! - \brief disable the stabilization interrupt - \param[in] interrupt: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC32KSTB: IRC32K stabilization interrupt disable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable - \arg RCU_INT_IRC16MSTB: IRC16M stabilization interrupt disable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable - \arg RCU_INT_PLLI2SSTB: PLLI2S stabilization interrupt disable - \arg RCU_INT_PLLSAISTB: PLLSAI stabilization interrupt disable - \arg RCU_INT_IRC48MSTB: IRC48M stabilization interrupt disable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum interrupt) -{ - RCU_REG_VAL(interrupt) &= ~BIT(RCU_BIT_POS(interrupt)); -} - -/*! - \brief configure the LXTAL drive capability - \param[in] lxtal_dricap: drive capability of LXTAL - only one parameter can be selected which is shown as below: - \arg RCU_LXTALDRI_LOWER_DRIVE: lower driving capability - \arg RCU_LXTALDRI_HIGHER_DRIVE: higher driving capability - \param[out] none - \retval none -*/ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) -{ - uint32_t reg; - - reg = RCU_BDCTL; - - /* reset the LXTALDRI bits and set according to lxtal_dricap */ - reg &= ~RCU_BDCTL_LXTALDRI; - RCU_BDCTL = (reg | lxtal_dricap); -} - -/*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC16M: IRC16M - \arg RCU_IRC48M: IRC48M - \arg RCU_IRC32K: IRC32K - \arg RCU_PLL_CK: PLL - \arg RCU_PLLI2S_CK: PLLI2S - \arg RCU_PLLSAI_CK: PLLSAI - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - - switch(osci){ - /* wait HXTAL stable */ - case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - - /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ - reval = SUCCESS; - } - break; - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ - reval = SUCCESS; - } - break; - /* wait IRC16M stable */ - case RCU_IRC16M: - while((RESET == osci_stat) && (IRC16M_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC16MSTB); - stb_cnt++; - } - - /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC16MSTB)){ - reval = SUCCESS; - } - break; - /* wait IRC48M stable */ - case RCU_IRC48M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC48MSTB); - stb_cnt++; - } - - /* check whether flag is set */ - if (RESET != rcu_flag_get(RCU_FLAG_IRC48MSTB)){ - reval = SUCCESS; - } - break; - /* wait IRC32K stable */ - case RCU_IRC32K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC32KSTB); - stb_cnt++; - } - - /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC32KSTB)){ - reval = SUCCESS; - } - break; - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ - reval = SUCCESS; - } - break; - /* wait PLLI2S stable */ - case RCU_PLLI2S_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLI2SSTB); - stb_cnt++; - } - - /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLI2SSTB)){ - reval = SUCCESS; - } - break; - /* wait PLLSAI stable */ - case RCU_PLLSAI_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSAISTB); - stb_cnt++; - } - - /* check whether flag is set */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSAISTB)){ - reval = SUCCESS; - } - break; - - default: - break; - } - - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC16M: IRC16M - \arg RCU_IRC48M: IRC48M - \arg RCU_IRC32K: IRC32K - \arg RCU_PLL_CK: PLL - \arg RCU_PLLI2S_CK: PLLI2S - \arg RCU_PLLSAI_CK: PLLSAI - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC16M: IRC16M - \arg RCU_IRC48M: IRC48M - \arg RCU_IRC32K: IRC32K - \arg RCU_PLL_CK: PLL - \arg RCU_PLLI2S_CK: PLLI2S - \arg RCU_PLLSAI_CK: PLLSAI - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* enable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg | RCU_CTL_HXTALBPS); - break; - /* enable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC16M: - case RCU_IRC48M: - case RCU_IRC32K: - case RCU_PLL_CK: - case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* disable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); - break; - /* disable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC16M: - case RCU_IRC48M: - case RCU_IRC32K: - case RCU_PLL_CK: - case RCU_PLLI2S_CK: - case RCU_PLLSAI_CK: - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC16M adjust value - \param[in] irc16m_adjval: IRC16M adjust value, must be between 0 and 0x1F - \arg 0x00 - 0x1F - \param[out] none - \retval none -*/ -void rcu_irc16m_adjust_value_set(uint32_t irc16m_adjval) -{ - uint32_t reg; - - reg = RCU_CTL; - /* reset the IRC16MADJ bits and set according to irc16m_adjval */ - reg &= ~RCU_CTL_IRC16MADJ; - RCU_CTL = (reg | ((irc16m_adjval & RCU_IRC16M_ADJUST_MASK) << RCU_IRC16M_ADJUST_OFFSET)); -} - -/*! - \brief unlock the voltage key - \param[in] none - \param[out] none - \retval none -*/ -void rcu_voltage_key_unlock(void) -{ - RCU_VKEY = RCU_VKEY_UNLOCK; -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief configure the spread spectrum modulation for the main PLL clock - \param[in] spread_spectrum_type: PLL spread spectrum modulation type select - \arg RCU_SS_TYPE_CENTER: center spread type is selected - \arg RCU_SS_TYPE_DOWN: down spread type is selected - \param[in] modstep: configure PLL spread spectrum modulation profile amplitude and frequency - \arg This parameter should be selected between 0 and 7FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 - \param[in] modcnt: configure PLL spread spectrum modulation profile amplitude and frequency - \arg This parameter should be selected between 0 and 1FFF.The following criteria must be met: MODSTEP*MODCNT <=2^15-1 - \param[out] none - \retval none -*/ -void rcu_spread_spectrum_config(uint32_t spread_spectrum_type, uint32_t modstep, uint32_t modcnt) -{ - uint32_t reg; - - reg = RCU_PLLSSCTL; - /* reset the RCU_PLLSSCTL register bits */ - reg &= ~(RCU_PLLSSCTL_MODCNT | RCU_PLLSSCTL_MODSTEP | RCU_PLLSSCTL_SS_TYPE); - RCU_PLLSSCTL = (reg | spread_spectrum_type | modstep << 13 | modcnt); -} - -/*! - \brief enable the PLL spread spectrum modulation - \param[in] none - \param[out] none - \retval none -*/ -void rcu_spread_spectrum_enable(void) -{ - RCU_PLLSSCTL |= RCU_PLLSSCTL_SSCGON; -} - -/*! - \brief disable the PLL spread spectrum modulation - \param[in] none - \param[out] none - \retval none -*/ -void rcu_spread_spectrum_disable(void) -{ - RCU_PLLSSCTL &= ~RCU_PLLSSCTL_SSCGON; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws, ck_freq = 0U; - uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllpsc, plln, pllsel, pllp, ck_src, idx, clk_exp; - - /* exponent of AHB, APB1 and APB2 clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC16M is selected as CK_SYS */ - case SEL_IRC16M: - cksys_freq = IRC16M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLLP is selected as CK_SYS */ - case SEL_PLLP: - /* get the value of PLLPSC[5:0] */ - pllpsc = GET_BITS(RCU_PLL, 0U, 5U); - plln = GET_BITS(RCU_PLL, 6U, 14U); - pllp = (GET_BITS(RCU_PLL, 16U, 17U) + 1U) * 2U; - /* PLL clock source selection, HXTAL or IRC16M/2 */ - pllsel = (RCU_PLL & RCU_PLL_PLLSEL); - if (RCU_PLLSRC_HXTAL == pllsel) { - ck_src = HXTAL_VALUE; - } else { - ck_src = IRC16M_VALUE; - } - cksys_freq = ((ck_src / pllpsc) * plln)/pllp; - break; - /* IRC16M is selected as CK_SYS */ - default: - cksys_freq = IRC16M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 10, 12); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 13, 15); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock){ - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c deleted file mode 100644 index 323da9f788..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c +++ /dev/null @@ -1,1295 +0,0 @@ -/*! - \file gd32f4xx_rtc.c - \brief RTC driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#include "gd32f4xx_rtc.h" - -/* RTC timeout value */ -#define RTC_WTWF_TIMEOUT ((uint32_t)0x00004000U) /*!< wakeup timer can be write flag timeout */ -#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ -#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ -#define RTC_HRFC_TIMEOUT ((uint32_t)0x20000000U) /*!< recalibration pending flag timeout */ -#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ -#define RTC_ALRMXWF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ - - -/*! - \brief reset most of the RTC registers - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_deinit(void) -{ - ErrStatus error_status = ERROR; - volatile uint32_t time_index = RTC_WTWF_TIMEOUT; - uint32_t flag_status = RESET; - /* RTC_TAMP register is not under write protection */ - RTC_TAMP = RTC_REGISTER_RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - /* reset RTC_CTL register, but RTC_CTL[2:0] */ - RTC_CTL &= (RTC_REGISTER_RESET | RTC_CTL_WTCS); - /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. - in order to read calendar from shadow register, not the real registers being reset */ - RTC_TIME = RTC_REGISTER_RESET; - RTC_DATE = RTC_DATE_RESET; - - RTC_PSC = RTC_PSC_RESET; - /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2:0] */ - /* wait until the WTWF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - - if ((uint32_t)RESET == flag_status){ - error_status = ERROR; - }else{ - RTC_CTL &= RTC_REGISTER_RESET; - RTC_WUT = RTC_WUT_RESET; - RTC_COSC = RTC_REGISTER_RESET; - /* to write RTC_ALRMxSS register, ALRMxEN bit in RTC_CTL register should be reset as the condition */ - RTC_ALRM0TD = RTC_REGISTER_RESET; - RTC_ALRM1TD = RTC_REGISTER_RESET; - RTC_ALRM0SS = RTC_REGISTER_RESET; - RTC_ALRM1SS = RTC_REGISTER_RESET; - /* reset RTC_STAT register, also exit init mode. - at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ - RTC_STAT = RTC_STAT_RESET; - /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ - RTC_SHIFTCTL = RTC_REGISTER_RESET; - RTC_HRFC = RTC_REGISTER_RESET; - error_status = rtc_register_sync_wait(); - } - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief initialize RTC registers - \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - year: 0x0 - 0x99(BCD format) - month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - date: 0x1 - 0x31(BCD format) - day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - minute: 0x0 - 0x59(BCD format) - second: 0x0 - 0x59(BCD format) - factor_asyn: 0x0 - 0x7F - factor_syn: 0x0 - 0x7FFF - am_pm: RTC_AM, RTC_PM - display_format: RTC_24HOUR, RTC_12HOUR - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) -{ - ErrStatus error_status = ERROR; - uint32_t reg_time = 0U, reg_date = 0U; - - reg_date = (DATE_YR(rtc_initpara_struct->year) | \ - DATE_DOW(rtc_initpara_struct->day_of_week) | \ - DATE_MON(rtc_initpara_struct->month) | \ - DATE_DAY(rtc_initpara_struct->date)); - - reg_time = (rtc_initpara_struct->am_pm| \ - TIME_HR(rtc_initpara_struct->hour) | \ - TIME_MN(rtc_initpara_struct->minute) | \ - TIME_SC(rtc_initpara_struct->second)); - - /* 1st: disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* 2nd: enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->factor_asyn)| \ - PSC_FACTOR_S(rtc_initpara_struct->factor_syn)); - - RTC_TIME = (uint32_t)reg_time; - RTC_DATE = (uint32_t)reg_date; - - RTC_CTL &= (uint32_t)(~RTC_CTL_CS); - RTC_CTL |= rtc_initpara_struct->display_format; - - /* 3rd: exit init mode */ - rtc_init_mode_exit(); - - /* 4th: wait the RSYNF flag to set */ - error_status = rtc_register_sync_wait(); - } - - /* 5th: enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enter RTC init mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init_mode_enter(void) -{ - volatile uint32_t time_index = RTC_INITM_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - /* check whether it has been in init mode */ - if ((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ - RTC_STAT |= RTC_STAT_INITM; - - /* wait until the INITF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_INITF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - - if ((uint32_t)RESET != flag_status){ - error_status = SUCCESS; - } - }else{ - error_status = SUCCESS; - } - return error_status; -} - -/*! - \brief exit RTC init mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_init_mode_exit(void) -{ - RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); -} - -/*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow - registers are updated - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_register_sync_wait(void) -{ - volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - if ((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* firstly clear RSYNF flag */ - RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); - - /* wait until RSYNF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_RSYNF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - - if ((uint32_t)RESET != flag_status){ - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - }else{ - error_status = SUCCESS; - } - - return error_status; -} - -/*! - \brief get current time and date - \param[in] none - \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - year: 0x0 - 0x99(BCD format) - month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - date: 0x1 - 0x31(BCD format) - day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - minute: 0x0 - 0x59(BCD format) - second: 0x0 - 0x59(BCD format) - factor_asyn: 0x0 - 0x7F - factor_syn: 0x0 - 0x7FFF - am_pm: RTC_AM, RTC_PM - display_format: RTC_24HOUR, RTC_12HOUR - \retval none -*/ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) -{ - uint32_t temp_tr = 0U, temp_dr = 0U, temp_pscr = 0U, temp_ctlr = 0U; - - temp_tr = (uint32_t)RTC_TIME; - temp_dr = (uint32_t)RTC_DATE; - temp_pscr = (uint32_t)RTC_PSC; - temp_ctlr = (uint32_t)RTC_CTL; - - /* get current time and construct rtc_parameter_struct structure */ - rtc_initpara_struct->year = (uint8_t)GET_DATE_YR(temp_dr); - rtc_initpara_struct->month = (uint8_t)GET_DATE_MON(temp_dr); - rtc_initpara_struct->date = (uint8_t)GET_DATE_DAY(temp_dr); - rtc_initpara_struct->day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); - rtc_initpara_struct->hour = (uint8_t)GET_TIME_HR(temp_tr); - rtc_initpara_struct->minute = (uint8_t)GET_TIME_MN(temp_tr); - rtc_initpara_struct->second = (uint8_t)GET_TIME_SC(temp_tr); - rtc_initpara_struct->factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); - rtc_initpara_struct->factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); - rtc_initpara_struct->display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); -} - -/*! - \brief get current subsecond value - \param[in] none - \param[out] none - \retval current subsecond value -*/ -uint32_t rtc_subsecond_get(void) -{ - uint32_t reg = 0U; - /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ - reg = (uint32_t)RTC_SS; - /* read RTC_DATE to unlock the 3 shadow registers */ - (void) (RTC_DATE); - - return reg; -} - -/*! - \brief configure RTC alarm - \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - alarm_minute: 0x0 - 0x59(BCD format) - alarm_second: 0x0 - 0x59(BCD format) - am_pm: RTC_AM, RTC_PM - \param[out] none - \retval none -*/ -void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) -{ - uint32_t reg_alrmtd = 0U; - - reg_alrmtd =(rtc_alarm_time->alarm_mask | \ - rtc_alarm_time->weekday_or_date | \ - rtc_alarm_time->am_pm | \ - ALRMTD_DAY(rtc_alarm_time->alarm_day) | \ - ALRMTD_HR(rtc_alarm_time->alarm_hour) | \ - ALRMTD_MN(rtc_alarm_time->alarm_minute) | \ - ALRMTD_SC(rtc_alarm_time->alarm_second)); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - if(RTC_ALARM0 == rtc_alarm){ - RTC_ALRM0TD = (uint32_t)reg_alrmtd; - - }else{ - RTC_ALRM1TD = (uint32_t)reg_alrmtd; - } - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief configure subsecond of RTC alarm - \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[in] mask_subsecond: alarm subsecond mask - \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration - \arg RTC_MASKSSC_1_14: mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared - \arg RTC_MASKSSC_2_14: mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared - \arg RTC_MASKSSC_3_14: mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared - \arg RTC_MASKSSC_4_14: mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared - \arg RTC_MASKSSC_5_14: mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared - \arg RTC_MASKSSC_6_14: mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared - \arg RTC_MASKSSC_7_14: mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared - \arg RTC_MASKSSC_8_14: mask RTC_ALRMXSS_SSC[14:8], and RTC_ALRMXSS_SSC[7:0] is to be compared - \arg RTC_MASKSSC_9_14: mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared - \arg RTC_MASKSSC_10_14: mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared - \arg RTC_MASKSSC_11_14: mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared - \arg RTC_MASKSSC_12_14: mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared - \arg RTC_MASKSSC_13_14: mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared - \arg RTC_MASKSSC_14: mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared - \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared - \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) - \param[out] none - \retval none -*/ -void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - if(RTC_ALARM0 == rtc_alarm){ - RTC_ALRM0SS = mask_subsecond | subsecond; - }else{ - RTC_ALRM1SS = mask_subsecond | subsecond; - } - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief get RTC alarm - \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - alarm_minute: 0x0 - 0x59(BCD format) - alarm_second: 0x0 - 0x59(BCD format) - am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_alarm_get(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time) -{ - uint32_t reg_alrmtd = 0U; - - /* get the value of RTC_ALRM0TD register */ - if(RTC_ALARM0 == rtc_alarm){ - reg_alrmtd = RTC_ALRM0TD; - }else{ - reg_alrmtd = RTC_ALRM1TD; - } - /* get alarm parameters and construct the rtc_alarm_struct structure */ - rtc_alarm_time->alarm_mask = reg_alrmtd & RTC_ALARM_ALL_MASK; - rtc_alarm_time->am_pm = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_PM); - rtc_alarm_time->weekday_or_date = (uint32_t)(reg_alrmtd & RTC_ALRMXTD_DOWS); - rtc_alarm_time->alarm_day = (uint8_t)GET_ALRMTD_DAY(reg_alrmtd); - rtc_alarm_time->alarm_hour = (uint8_t)GET_ALRMTD_HR(reg_alrmtd); - rtc_alarm_time->alarm_minute = (uint8_t)GET_ALRMTD_MN(reg_alrmtd); - rtc_alarm_time->alarm_second = (uint8_t)GET_ALRMTD_SC(reg_alrmtd); -} - -/*! - \brief get RTC alarm subsecond - \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[out] none - \retval RTC alarm subsecond value -*/ -uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm) -{ - if(RTC_ALARM0 == rtc_alarm){ - return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); - }else{ - return ((uint32_t)(RTC_ALRM1SS & RTC_ALRM1SS_SSC)); - } -} - -/*! - \brief enable RTC alarm - \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[out] none - \retval none -*/ -void rtc_alarm_enable(uint8_t rtc_alarm) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - if(RTC_ALARM0 == rtc_alarm){ - RTC_CTL |= RTC_CTL_ALRM0EN; - }else{ - RTC_CTL |= RTC_CTL_ALRM1EN; - } - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC alarm - \param[in] rtc_alarm: RTC_ALARM0 or RTC_ALARM1 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_alarm_disable(uint8_t rtc_alarm) -{ - volatile uint32_t time_index = RTC_ALRMXWF_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the state of alarm */ - if(RTC_ALARM0 == rtc_alarm){ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); - /* wait until ALRM0WF flag to be set after the alarm is disabled */ - do{ - flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - }else{ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM1EN); - /* wait until ALRM1WF flag to be set after the alarm is disabled */ - do{ - flag_status = RTC_STAT & RTC_STAT_ALRM1WF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - } - - if ((uint32_t)RESET != flag_status){ - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC time-stamp - \param[in] edge: specify which edge to detect of time-stamp - \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event - \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event - \param[out] none - \retval none -*/ -void rtc_timestamp_enable(uint32_t edge) -{ - uint32_t reg_ctl = 0U; - - /* clear the bits to be configured in RTC_CTL */ - reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); - - /* new configuration */ - reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL = (uint32_t)reg_ctl; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC time-stamp - \param[in] none - \param[out] none - \retval none -*/ -void rtc_timestamp_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the TSEN bit */ - RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief get RTC timestamp time and date - \param[in] none - \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains - parameters for RTC time-stamp configuration - members of the structure and the member values are shown as below: - timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - timestamp_date: 0x1 - 0x31(BCD format) - timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - timestamp_minute: 0x0 - 0x59(BCD format) - timestamp_second: 0x0 - 0x59(BCD format) - am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) -{ - uint32_t temp_tts = 0U, temp_dts = 0U; - - /* get the value of time_stamp registers */ - temp_tts = (uint32_t)RTC_TTS; - temp_dts = (uint32_t)RTC_DTS; - - /* get timestamp time and construct the rtc_timestamp_struct structure */ - rtc_timestamp->am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); - rtc_timestamp->timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); - rtc_timestamp->timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); - rtc_timestamp->timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); - rtc_timestamp->timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); - rtc_timestamp->timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); - rtc_timestamp->timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); -} - -/*! - \brief get RTC time-stamp subsecond - \param[in] none - \param[out] none - \retval RTC time-stamp subsecond value -*/ -uint32_t rtc_timestamp_subsecond_get(void) -{ - return ((uint32_t)RTC_SSTS); -} - -/*! - \brief RTC time-stamp mapping - \param[in] rtc_af: - \arg RTC_AF0_TIMESTAMP: RTC_AF0 use for timestamp - \arg RTC_AF1_TIMESTAMP: RTC_AF1 use for timestamp - \param[out] none - \retval none -*/ -void rtc_timestamp_pin_map(uint32_t rtc_af) -{ - RTC_TAMP &= ~RTC_TAMP_TSSEL; - RTC_TAMP |= rtc_af; -} - -/*! - \brief enable RTC tamper - \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains - parameters for RTC tamper configuration - members of the structure and the member values are shown as below: - detecting tamper event can using edge mode or level mode - (1) using edge mode configuration: - tamper_source: RTC_TAMPER0, RTC_TAMPER1 - tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING - tamper_filter: RTC_FLT_EDGE - tamper_with_timestamp: DISABLE, ENABLE - (2) using level mode configuration: - tamper_source: RTC_TAMPER0, RTC_TAMPER1 - tamper_trigger:RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH - tamper_filter: RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S - tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, - RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, - RTC_FREQ_DIV512, RTC_FREQ_DIV256 - tamper_precharge_enable: DISABLE, ENABLE - tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C - tamper_with_timestamp: DISABLE, ENABLE - \param[out] none - \retval none -*/ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~(rtc_tamper->tamper_source); - - /* tamper filter must be used when the tamper source is voltage level detection */ - RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; - - /* the tamper source is voltage level detection */ - if((uint32_t)(rtc_tamper->tamper_filter) != RTC_FLT_EDGE ){ - RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); - - /* check if the tamper pin need precharge, if need, then configure the precharge time */ - if(DISABLE == rtc_tamper->tamper_precharge_enable){ - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; - }else{ - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_precharge_time); - } - - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_sample_frequency); - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_filter); - - /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_LEVEL_LOW != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); - } - }else{ - - /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->tamper_source)<< RTC_TAMPER_TRIGGER_POS); - } - } - - RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - if(DISABLE != rtc_tamper->tamper_with_timestamp){ - /* the tamper event also cause a time-stamp event */ - RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; - } - /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->tamper_source); -} - -/*! - \brief disable RTC tamper - \param[in] source: specify which tamper source to be disabled - \arg RTC_TAMPER0 - \arg RTC_TAMPER1 - \param[out] none - \retval none -*/ -void rtc_tamper_disable(uint32_t source) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~source; - -} - -/*! - \brief RTC tamper0 mapping - \param[in] rtc_af: - \arg RTC_AF0_TAMPER0: RTC_AF0 use for tamper0 - \arg RTC_AF1_TAMPER0: RTC_AF1 use for tamper0 - \param[out] none - \retval none -*/ -void rtc_tamper0_pin_map(uint32_t rtc_af) -{ - RTC_TAMP &= ~(RTC_TAMP_TP0EN | RTC_TAMP_TP0SEL); - RTC_TAMP |= rtc_af; -} - -/*! - \brief enable specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be enabled - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM0: alarm0 interrupt - \arg RTC_INT_ALARM1: alarm1 interrupt - \arg RTC_INT_TAMP: tamper detection interrupt - \arg RTC_INT_WAKEUP: wakeup timer interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enable the interrupts in RTC_CTL register */ - RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* enable the interrupts in RTC_TAMP register */ - RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disble specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be disabled - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM0: alarm interrupt - \arg RTC_INT_ALARM1: alarm interrupt - \arg RTC_INT_TAMP: tamper detection interrupt - \arg RTC_INT_WAKEUP: wakeup timer interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* disable the interrupts in RTC_CTL register */ - RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* disable the interrupts in RTC_TAMP register */ - RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief check specified flag - \param[in] flag: specify which flag to check - \arg RTC_STAT_SCP: smooth calibration pending flag - \arg RTC_FLAG_TP1: RTC tamper 1 detected flag - \arg RTC_FLAG_TP0: RTC tamper 0 detected flag - \arg RTC_FLAG_TSOVR: time-stamp overflow flag - \arg RTC_FLAG_TS: time-stamp flag - \arg RTC_FLAG_ALARM0: alarm0 occurs flag - \arg RTC_FLAG_ALARM1: alarm1 occurs flag - \arg RTC_FLAG_WT: wakeup timer occurs flag - \arg RTC_FLAG_INIT: initialization state flag - \arg RTC_FLAG_RSYN: register synchronization flag - \arg RTC_FLAG_YCM: year configuration mark status flag - \arg RTC_FLAG_SOP: shift function operation pending flag - \arg RTC_FLAG_ALRM0W: alarm0 configuration can be write flag - \arg RTC_FLAG_ALRM1W: alarm1 configuration can be write flag - \arg RTC_FLAG_WTW: wakeup timer can be write flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - FlagStatus flag_state = RESET; - - if ((uint32_t)RESET != (RTC_STAT & flag)){ - flag_state = SET; - } - return flag_state; -} - -/*! - \brief clear specified flag - \arg RTC_FLAG_TP1: RTC tamper 1 detected flag - \arg RTC_FLAG_TP0: RTC tamper 0 detected flag - \arg RTC_FLAG_TSOVR: time-stamp overflow flag - \arg RTC_FLAG_TS: time-stamp flag - \arg RTC_FLAG_WT: wakeup timer occurs flag - \arg RTC_FLAG_ALARM0: alarm0 occurs flag - \arg RTC_FLAG_ALARM1: alarm1 occurs flag - \arg RTC_FLAG_RSYN: register synchronization flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - RTC_STAT &= (uint32_t)(~flag); -} - -/*! - \brief configure rtc alarm output source - \param[in] source: specify signal to output - \arg RTC_ALARM0_HIGH: when the alarm0 flag is set, the output pin is high - \arg RTC_ALARM0_LOW: when the alarm0 flag is set, the output pin is low - \arg RTC_ALARM1_HIGH: when the alarm1 flag is set, the output pin is high - \arg RTC_ALARM1_LOW: when the alarm1 flag is set, the output pin is low - \arg RTC_WAKEUP_HIGH: when the wakeup flag is set, the output pin is high - \arg RTC_WAKEUP_LOW: when the wakeup flag is set, the output pin is low - \param[in] mode: specify the output pin mode when output alarm signal - \arg RTC_ALARM_OUTPUT_OD: open drain mode - \arg RTC_ALARM_OUTPUT_PP: push pull mode - \param[out] none - \retval none -*/ -void rtc_alarm_output_config(uint32_t source, uint32_t mode) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= ~(RTC_CTL_OS | RTC_CTL_OPOL); - RTC_TAMP &= ~RTC_TAMP_AOT; - - RTC_CTL |= (uint32_t)(source); - /* alarm output */ - RTC_TAMP |= (uint32_t)(mode); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief configure rtc calibration output source - \param[in] source: specify signal to output - \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal - \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 1Hz signal - \param[out] none - \retval none -*/ -void rtc_calibration_output_config(uint32_t source) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_COS); - - RTC_CTL |= (uint32_t)(source); - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - - -/*! - \brief adjust the daylight saving time by adding or substracting one hour from the current time - \param[in] operation: hour adjustment operation - \arg RTC_CTL_A1H: add one hour - \arg RTC_CTL_S1H: substract one hour - \param[out] none - \retval none -*/ -void rtc_hour_adjust(uint32_t operation) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= (uint32_t)(operation); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief adjust RTC second or subsecond value of current time - \param[in] add: add 1s to current time or not - \arg RTC_SHIFT_ADD1S_RESET: no effect - \arg RTC_SHIFT_ADD1S_SET: add 1s to current time - \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) -{ - volatile uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - uint32_t temp=0U; - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a shift operation is ongoing */ - do{ - flag_status = RTC_STAT & RTC_STAT_SOPF; - }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - - /* check if the function of reference clock detection is disabled */ - temp = RTC_CTL & RTC_CTL_REFEN; - if((RESET == flag_status) && (RESET == temp)){ - RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); - error_status = rtc_register_sync_wait(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= ~RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief enable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_enable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL |= (uint32_t)RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief disable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_disable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC auto wakeup function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_wakeup_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= RTC_CTL_WTEN; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC auto wakeup function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_wakeup_disable(void) -{ - ErrStatus error_status = ERROR; - volatile uint32_t time_index = RTC_WTWF_TIMEOUT; - uint32_t flag_status = RESET; - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - RTC_CTL &= ~RTC_CTL_WTEN; - /* wait until the WTWF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - - if ((uint32_t)RESET == flag_status){ - error_status = ERROR; - }else{ - error_status = SUCCESS; - } - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - return error_status; -} - -/*! - \brief set RTC auto wakeup timer clock - \param[in] wakeup_clock: - \arg WAKEUP_RTCCK_DIV16: RTC auto wakeup timer clock is RTC clock divided by 16 - \arg WAKEUP_RTCCK_DIV8: RTC auto wakeup timer clock is RTC clock divided by 8 - \arg WAKEUP_RTCCK_DIV4: RTC auto wakeup timer clock is RTC clock divided by 4 - \arg WAKEUP_RTCCK_DIV2: RTC auto wakeup timer clock is RTC clock divided by 2 - \arg WAKEUP_CKSPRE: RTC auto wakeup timer clock is ckspre - \arg WAKEUP_CKSPRE_2EXP16: RTC auto wakeup timer clock is ckspre and wakeup timer add 2exp16 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock) -{ - ErrStatus error_status = ERROR; - volatile uint32_t time_index = RTC_WTWF_TIMEOUT; - uint32_t flag_status = RESET; - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - /* only when RTC_CTL_WTEN=0 and RTC_STAT_WTWF=1 can write RTC_CTL[2:0] */ - /* wait until the WTWF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - - if ((uint32_t)RESET == flag_status){ - error_status = ERROR; - }else{ - RTC_CTL &= (uint32_t)~ RTC_CTL_WTCS; - RTC_CTL |= (uint32_t)wakeup_clock; - error_status = SUCCESS; - } - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief set wakeup timer value - \param[in] wakeup_timer: 0x0000-0xffff - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer) -{ - ErrStatus error_status = ERROR; - volatile uint32_t time_index = RTC_WTWF_TIMEOUT; - uint32_t flag_status = RESET; - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - /* wait until the WTWF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_WTWF; - }while((--time_index > 0U) && ((uint32_t)RESET == flag_status)); - - if ((uint32_t)RESET == flag_status){ - error_status = ERROR; - }else{ - RTC_WUT = (uint32_t)wakeup_timer; - error_status = SUCCESS; - } - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - return error_status; -} - -/*! - \brief get wakeup timer value - \param[in] none - \param[out] none - \retval wakeup timer value -*/ - uint16_t rtc_wakeup_timer_get(void) -{ - return (uint16_t)RTC_WUT; -} - -/*! - \brief configure RTC smooth calibration - \param[in] window: select calibration window - \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz - \param[in] plus: add RTC clock or not - \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock - \arg RTC_CALIBRATION_PLUS_RESET: no effect - \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) -{ - volatile uint32_t time_index = RTC_HRFC_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a smooth calibration operation is ongoing */ - do{ - flag_status = RTC_STAT & RTC_STAT_SCPF; - }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET == flag_status){ - RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC coarse calibration - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_coarse_calibration_enable(void) -{ - ErrStatus error_status = ERROR; - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL |= (uint32_t)RTC_CTL_CCEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - return error_status; -} - -/*! - \brief disable RTC coarse calibration - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_coarse_calibration_disable(void) -{ - ErrStatus error_status = ERROR; - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL &= (uint32_t)~RTC_CTL_CCEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - return error_status; -} - -/*! - \brief config coarse calibration direction and step - \param[in] direction: CALIB_INCREASE or CALIB_DECREASE - \param[in] step: 0x00-0x1F - COSD=0: - 0x00:+0 PPM - 0x01:+4 PPM - 0x02:+8 PPM - .... - 0x1F:+126 PPM - COSD=1: - 0x00:-0 PPM - 0x01:-2 PPM - 0x02:-4 PPM - .... - 0x1F:-63 PPM - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step) -{ - ErrStatus error_status = ERROR; - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - if(CALIB_DECREASE == direction){ - RTC_COSC |= (uint32_t)RTC_COSC_COSD; - }else{ - RTC_COSC &= (uint32_t)~RTC_COSC_COSD; - } - RTC_COSC &= ~RTC_COSC_COSS; - RTC_COSC |= (uint32_t)((uint32_t)step & 0x1FU); - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c deleted file mode 100644 index d1d0a0be32..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c +++ /dev/null @@ -1,803 +0,0 @@ -/*! - \file gd32f4xx_sdio.c - \brief SDIO driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.1, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_sdio.h" - -/*! - \brief deinitialize the SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_deinit(void) -{ - rcu_periph_reset_enable(RCU_SDIORST); - rcu_periph_reset_disable(RCU_SDIORST); -} - -/*! - \brief configure the SDIO clock - \param[in] clock_edge: SDIO_CLK clock edge - only one parameter can be selected which is shown as below: - \arg SDIO_SDIOCLKEDGE_RISING: select the rising edge of the SDIOCLK to generate SDIO_CLK - \arg SDIO_SDIOCLKEDGE_FALLING: select the falling edge of the SDIOCLK to generate SDIO_CLK - \param[in] clock_bypass: clock bypass - only one parameter can be selected which is shown as below: - \arg SDIO_CLOCKBYPASS_ENABLE: clock bypass - \arg SDIO_CLOCKBYPASS_DISABLE: no bypass - \param[in] clock_powersave: SDIO_CLK clock dynamic switch on/off for power saving - only one parameter can be selected which is shown as below: - \arg SDIO_CLOCKPWRSAVE_ENABLE: SDIO_CLK closed when bus is idle - \arg SDIO_CLOCKPWRSAVE_DISABLE: SDIO_CLK clock is always on - \param[in] clock_division: clock division, less than 512 - \param[out] none - \retval none -*/ -void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division) -{ - uint32_t clock_config = 0U; - clock_config = SDIO_CLKCTL; - /* reset the CLKEDGE, CLKBYP, CLKPWRSAV, DIV */ - clock_config &= ~(SDIO_CLKCTL_CLKEDGE | SDIO_CLKCTL_CLKBYP | SDIO_CLKCTL_CLKPWRSAV | SDIO_CLKCTL_DIV8 | SDIO_CLKCTL_DIV); - /* if the clock division is greater or equal to 256, set the DIV[8] */ - if(clock_division >= 256U){ - clock_config |= SDIO_CLKCTL_DIV8; - clock_division -= 256U; - } - /* configure the SDIO_CLKCTL according to the parameters */ - clock_config |= (clock_edge | clock_bypass | clock_powersave | clock_division); - SDIO_CLKCTL = clock_config; -} - -/*! - \brief enable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief disable hardware clock control - \param[in] none - \param[out] none - \retval none -*/ -void sdio_hardware_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_HWCLKEN; -} - -/*! - \brief set different SDIO card bus mode - \param[in] bus_mode: SDIO card bus mode - only one parameter can be selected which is shown as below: - \arg SDIO_BUSMODE_1BIT: 1-bit SDIO card bus mode - \arg SDIO_BUSMODE_4BIT: 4-bit SDIO card bus mode - \arg SDIO_BUSMODE_8BIT: 8-bit SDIO card bus mode - \param[out] none - \retval none -*/ -void sdio_bus_mode_set(uint32_t bus_mode) -{ - /* reset the SDIO card bus mode bits and set according to bus_mode */ - SDIO_CLKCTL &= ~SDIO_CLKCTL_BUSMODE; - SDIO_CLKCTL |= bus_mode; -} - -/*! - \brief set the SDIO power state - \param[in] power_state: SDIO power state - only one parameter can be selected which is shown as below: - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off - \param[out] none - \retval none -*/ -void sdio_power_state_set(uint32_t power_state) -{ - SDIO_PWRCTL = power_state; -} - -/*! - \brief get the SDIO power state - \param[in] none - \param[out] none - \retval SDIO power state - \arg SDIO_POWER_ON: SDIO power on - \arg SDIO_POWER_OFF: SDIO power off -*/ -uint32_t sdio_power_state_get(void) -{ - return SDIO_PWRCTL; -} - -/*! - \brief enable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_enable(void) -{ - SDIO_CLKCTL |= SDIO_CLKCTL_CLKEN; -} - -/*! - \brief disable SDIO_CLK clock output - \param[in] none - \param[out] none - \retval none -*/ -void sdio_clock_disable(void) -{ - SDIO_CLKCTL &= ~SDIO_CLKCTL_CLKEN; -} - -/*! - \brief configure the command and response - \param[in] cmd_index: command index, refer to the related specifications - \param[in] cmd_argument: command argument, refer to the related specifications - \param[in] response_type: response type - only one parameter can be selected which is shown as below: - \arg SDIO_RESPONSETYPE_NO: no response - \arg SDIO_RESPONSETYPE_SHORT: short response - \arg SDIO_RESPONSETYPE_LONG: long response - \param[out] none - \retval none -*/ -void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) -{ - uint32_t cmd_config = 0U; - /* disable the CSM */ - SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; - /* reset the command index, command argument and response type */ - SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; - SDIO_CMDAGMT = cmd_argument; - cmd_config = SDIO_CMDCTL; - cmd_config &= ~(SDIO_CMDCTL_CMDIDX | SDIO_CMDCTL_CMDRESP); - /* configure SDIO_CMDCTL and SDIO_CMDAGMT according to the parameters */ - cmd_config |= (cmd_index | response_type); - SDIO_CMDCTL = cmd_config; -} - -/*! - \brief set the command state machine wait type - \param[in] wait_type: wait type - only one parameter can be selected which is shown as below: - \arg SDIO_WAITTYPE_NO: not wait interrupt - \arg SDIO_WAITTYPE_INTERRUPT: wait interrupt - \arg SDIO_WAITTYPE_DATAEND: wait the end of data transfer - \param[out] none - \retval none -*/ -void sdio_wait_type_set(uint32_t wait_type) -{ - /* reset INTWAIT and WAITDEND */ - SDIO_CMDCTL &= ~(SDIO_CMDCTL_INTWAIT | SDIO_CMDCTL_WAITDEND); - /* set the wait type according to wait_type */ - SDIO_CMDCTL |= wait_type; -} - -/*! - \brief enable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_CSMEN; -} - -/*! - \brief disable the CSM(command state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_csm_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; -} - -/*! - \brief get the last response command index - \param[in] none - \param[out] none - \retval last response command index -*/ -uint8_t sdio_command_index_get(void) -{ - return (uint8_t)SDIO_RSPCMDIDX; -} - -/*! - \brief get the response for the last received command - \param[in] sdio_responsex: SDIO response - only one parameter can be selected which is shown as below: - \arg SDIO_RESPONSE0: card response[31:0]/card response[127:96] - \arg SDIO_RESPONSE1: card response[95:64] - \arg SDIO_RESPONSE2: card response[63:32] - \arg SDIO_RESPONSE3: card response[31:1], plus bit 0 - \param[out] none - \retval response for the last received command -*/ -uint32_t sdio_response_get(uint32_t sdio_responsex) -{ - uint32_t resp_content = 0U; - switch(sdio_responsex){ - case SDIO_RESPONSE0: - resp_content = SDIO_RESP0; - break; - case SDIO_RESPONSE1: - resp_content = SDIO_RESP1; - break; - case SDIO_RESPONSE2: - resp_content = SDIO_RESP2; - break; - case SDIO_RESPONSE3: - resp_content = SDIO_RESP3; - break; - default: - break; - } - return resp_content; -} - -/*! - \brief configure the data timeout, data length and data block size - \param[in] data_timeout: data timeout period in card bus clock periods - \param[in] data_length: number of data bytes to be transferred - \param[in] data_blocksize: size of data block for block transfer - only one parameter can be selected which is shown as below: - \arg SDIO_DATABLOCKSIZE_1BYTE: block size = 1 byte - \arg SDIO_DATABLOCKSIZE_2BYTES: block size = 2 bytes - \arg SDIO_DATABLOCKSIZE_4BYTES: block size = 4 bytes - \arg SDIO_DATABLOCKSIZE_8BYTES: block size = 8 bytes - \arg SDIO_DATABLOCKSIZE_16BYTES: block size = 16 bytes - \arg SDIO_DATABLOCKSIZE_32BYTES: block size = 32 bytes - \arg SDIO_DATABLOCKSIZE_64BYTES: block size = 64 bytes - \arg SDIO_DATABLOCKSIZE_128BYTES: block size = 128 bytes - \arg SDIO_DATABLOCKSIZE_256BYTES: block size = 256 bytes - \arg SDIO_DATABLOCKSIZE_512BYTES: block size = 512 bytes - \arg SDIO_DATABLOCKSIZE_1024BYTES: block size = 1024 bytes - \arg SDIO_DATABLOCKSIZE_2048BYTES: block size = 2048 bytes - \arg SDIO_DATABLOCKSIZE_4096BYTES: block size = 4096 bytes - \arg SDIO_DATABLOCKSIZE_8192BYTES: block size = 8192 bytes - \arg SDIO_DATABLOCKSIZE_16384BYTES: block size = 16384 bytes - \param[out] none - \retval none -*/ -void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize) -{ - /* reset data timeout, data length and data block size */ - SDIO_DATATO &= ~SDIO_DATATO_DATATO; - SDIO_DATALEN &= ~SDIO_DATALEN_DATALEN; - SDIO_DATACTL &= ~SDIO_DATACTL_BLKSZ; - /* configure the related parameters of data */ - SDIO_DATATO = data_timeout; - SDIO_DATALEN = data_length; - SDIO_DATACTL |= data_blocksize; -} - -/*! - \brief configure the data transfer mode and direction - \param[in] transfer_mode: mode of data transfer - only one parameter can be selected which is shown as below: - \arg SDIO_TRANSMODE_BLOCK: block transfer - \arg SDIO_TRANSMODE_STREAM: stream transfer or SDIO multibyte transfer - \param[in] transfer_direction: data transfer direction, read or write - only one parameter can be selected which is shown as below: - \arg SDIO_TRANSDIRECTION_TOCARD: write data to card - \arg SDIO_TRANSDIRECTION_TOSDIO: read data from card - \param[out] none - \retval none -*/ -void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction) -{ - uint32_t data_trans = 0U; - /* reset the data transfer mode, transfer direction and set according to the parameters */ - data_trans = SDIO_DATACTL; - data_trans &= ~(SDIO_DATACTL_TRANSMOD | SDIO_DATACTL_DATADIR); - data_trans |= (transfer_mode | transfer_direction); - SDIO_DATACTL = data_trans; -} - -/*! - \brief enable the DSM(data state machine) for data transfer - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DATAEN; -} - -/*! - \brief disable the DSM(data state machine) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dsm_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DATAEN; -} - -/*! - \brief write data(one word) to the transmit FIFO - \param[in] data: 32-bit data write to card - \param[out] none - \retval none -*/ -void sdio_data_write(uint32_t data) -{ - SDIO_FIFO = data; -} - -/*! - \brief read data(one word) from the receive FIFO - \param[in] none - \param[out] none - \retval received data -*/ -uint32_t sdio_data_read(void) -{ - return SDIO_FIFO; -} - -/*! - \brief get the number of remaining data bytes to be transferred to card - \param[in] none - \param[out] none - \retval number of remaining data bytes to be transferred -*/ -uint32_t sdio_data_counter_get(void) -{ - return SDIO_DATACNT; -} - -/*! - \brief get the number of words remaining to be written or read from FIFO - \param[in] none - \param[out] none - \retval remaining number of words -*/ -uint32_t sdio_fifo_counter_get(void) -{ - return SDIO_FIFOCNT; -} - -/*! - \brief enable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_DMAEN; -} - -/*! - \brief disable the DMA request for SDIO - \param[in] none - \param[out] none - \retval none -*/ -void sdio_dma_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_DMAEN; -} - -/*! - \brief get the flags state of SDIO - \param[in] flag: flags state of SDIO - one or more parameters can be selected which are shown as below: - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_CMDRUN: command transmission in progress flag - \arg SDIO_FLAG_TXRUN: data transmission in progress flag - \arg SDIO_FLAG_RXRUN: data reception in progress flag - \arg SDIO_FLAG_TFH: transmit FIFO is half empty flag: at least 8 words can be written into the FIFO - \arg SDIO_FLAG_RFH: receive FIFO is half full flag: at least 8 words can be read in the FIFO - \arg SDIO_FLAG_TFF: transmit FIFO is full flag - \arg SDIO_FLAG_RFF: receive FIFO is full flag - \arg SDIO_FLAG_TFE: transmit FIFO is empty flag - \arg SDIO_FLAG_RFE: receive FIFO is empty flag - \arg SDIO_FLAG_TXDTVAL: data is valid in transmit FIFO flag - \arg SDIO_FLAG_RXDTVAL: data is valid in receive FIFO flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_flag_get(uint32_t flag) -{ - FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & flag)){ - temp_flag = SET; - } - return temp_flag; -} - -/*! - \brief clear the pending flags of SDIO - \param[in] flag: flags state of SDIO - one or more parameters can be selected which are shown as below: - \arg SDIO_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_FLAG_DTTMOUT: data timeout flag - \arg SDIO_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_flag_clear(uint32_t flag) -{ - SDIO_INTC = flag; -} - -/*! - \brief enable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - one or more parameters can be selected which are shown as below: - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_enable(uint32_t int_flag) -{ - SDIO_INTEN |= int_flag; -} - -/*! - \brief disable the SDIO interrupt - \param[in] int_flag: interrupt flags state of SDIO - one or more parameters can be selected which are shown as below: - \arg SDIO_INT_CCRCERR: SDIO CCRCERR interrupt - \arg SDIO_INT_DTCRCERR: SDIO DTCRCERR interrupt - \arg SDIO_INT_CMDTMOUT: SDIO CMDTMOUT interrupt - \arg SDIO_INT_DTTMOUT: SDIO DTTMOUT interrupt - \arg SDIO_INT_TXURE: SDIO TXURE interrupt - \arg SDIO_INT_RXORE: SDIO RXORE interrupt - \arg SDIO_INT_CMDRECV: SDIO CMDRECV interrupt - \arg SDIO_INT_CMDSEND: SDIO CMDSEND interrupt - \arg SDIO_INT_DTEND: SDIO DTEND interrupt - \arg SDIO_INT_STBITE: SDIO STBITE interrupt - \arg SDIO_INT_DTBLKEND: SDIO DTBLKEND interrupt - \arg SDIO_INT_CMDRUN: SDIO CMDRUN interrupt - \arg SDIO_INT_TXRUN: SDIO TXRUN interrupt - \arg SDIO_INT_RXRUN: SDIO RXRUN interrupt - \arg SDIO_INT_TFH: SDIO TFH interrupt - \arg SDIO_INT_RFH: SDIO RFH interrupt - \arg SDIO_INT_TFF: SDIO TFF interrupt - \arg SDIO_INT_RFF: SDIO RFF interrupt - \arg SDIO_INT_TFE: SDIO TFE interrupt - \arg SDIO_INT_RFE: SDIO RFE interrupt - \arg SDIO_INT_TXDTVAL: SDIO TXDTVAL interrupt - \arg SDIO_INT_RXDTVAL: SDIO RXDTVAL interrupt - \arg SDIO_INT_SDIOINT: SDIO SDIOINT interrupt - \arg SDIO_INT_ATAEND: SDIO ATAEND interrupt - \param[out] none - \retval none -*/ -void sdio_interrupt_disable(uint32_t int_flag) -{ - SDIO_INTEN &= ~int_flag; -} - -/*! - \brief get the interrupt flags state of SDIO - \param[in] int_flag: interrupt flags state of SDIO - one or more parameters can be selected which are shown as below: - \arg SDIO_INT_FLAG_CCRCERR: SDIO CCRCERR interrupt flag - \arg SDIO_INT_FLAG_DTCRCERR: SDIO DTCRCERR interrupt flag - \arg SDIO_INT_FLAG_CMDTMOUT: SDIO CMDTMOUT interrupt flag - \arg SDIO_INT_FLAG_DTTMOUT: SDIO DTTMOUT interrupt flag - \arg SDIO_INT_FLAG_TXURE: SDIO TXURE interrupt flag - \arg SDIO_INT_FLAG_RXORE: SDIO RXORE interrupt flag - \arg SDIO_INT_FLAG_CMDRECV: SDIO CMDRECV interrupt flag - \arg SDIO_INT_FLAG_CMDSEND: SDIO CMDSEND interrupt flag - \arg SDIO_INT_FLAG_DTEND: SDIO DTEND interrupt flag - \arg SDIO_INT_FLAG_STBITE: SDIO STBITE interrupt flag - \arg SDIO_INT_FLAG_DTBLKEND: SDIO DTBLKEND interrupt flag - \arg SDIO_INT_FLAG_CMDRUN: SDIO CMDRUN interrupt flag - \arg SDIO_INT_FLAG_TXRUN: SDIO TXRUN interrupt flag - \arg SDIO_INT_FLAG_RXRUN: SDIO RXRUN interrupt flag - \arg SDIO_INT_FLAG_TFH: SDIO TFH interrupt flag - \arg SDIO_INT_FLAG_RFH: SDIO RFH interrupt flag - \arg SDIO_INT_FLAG_TFF: SDIO TFF interrupt flag - \arg SDIO_INT_FLAG_RFF: SDIO RFF interrupt flag - \arg SDIO_INT_FLAG_TFE: SDIO TFE interrupt flag - \arg SDIO_INT_FLAG_RFE: SDIO RFE interrupt flag - \arg SDIO_INT_FLAG_TXDTVAL: SDIO TXDTVAL interrupt flag - \arg SDIO_INT_FLAG_RXDTVAL: SDIO RXDTVAL interrupt flag - \arg SDIO_INT_FLAG_SDIOINT: SDIO SDIOINT interrupt flag - \arg SDIO_INT_FLAG_ATAEND: SDIO ATAEND interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) -{ - FlagStatus temp_flag = RESET; - if(RESET != (SDIO_STAT & int_flag)){ - temp_flag = SET; - } - return temp_flag; -} - -/*! - \brief clear the interrupt pending flags of SDIO - \param[in] int_flag: interrupt flags state of SDIO - one or more parameters can be selected which are shown as below: - \arg SDIO_INT_FLAG_CCRCERR: command response received (CRC check failed) flag - \arg SDIO_INT_FLAG_DTCRCERR: data block sent/received (CRC check failed) flag - \arg SDIO_INT_FLAG_CMDTMOUT: command response timeout flag - \arg SDIO_INT_FLAG_DTTMOUT: data timeout flag - \arg SDIO_INT_FLAG_TXURE: transmit FIFO underrun error occurs flag - \arg SDIO_INT_FLAG_RXORE: received FIFO overrun error occurs flag - \arg SDIO_INT_FLAG_CMDRECV: command response received (CRC check passed) flag - \arg SDIO_INT_FLAG_CMDSEND: command sent (no response required) flag - \arg SDIO_INT_FLAG_DTEND: data end (data counter, SDIO_DATACNT, is zero) flag - \arg SDIO_INT_FLAG_STBITE: start bit error in the bus flag - \arg SDIO_INT_FLAG_DTBLKEND: data block sent/received (CRC check passed) flag - \arg SDIO_INT_FLAG_SDIOINT: SD I/O interrupt received flag - \arg SDIO_INT_FLAG_ATAEND: CE-ATA command completion signal received (only for CMD61) flag - \param[out] none - \retval none -*/ -void sdio_interrupt_flag_clear(uint32_t int_flag) -{ - SDIO_INTC = int_flag; -} - -/*! - \brief enable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWEN; -} - -/*! - \brief disable the read wait mode(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWEN; -} - -/*! - \brief enable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_RWSTOP; -} - -/*! - \brief disable the function that stop the read wait process(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_stop_readwait_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWSTOP; -} - -/*! - \brief set the read wait type(SD I/O only) - \param[in] readwait_type: SD I/O read wait type - only one parameter can be selected which is shown as below: - \arg SDIO_READWAITTYPE_CLK: read wait control by stopping SDIO_CLK - \arg SDIO_READWAITTYPE_DAT2: read wait control using SDIO_DAT[2] - \param[out] none - \retval none -*/ -void sdio_readwait_type_set(uint32_t readwait_type) -{ - if(SDIO_READWAITTYPE_CLK == readwait_type){ - SDIO_DATACTL |= SDIO_DATACTL_RWTYPE; - }else{ - SDIO_DATACTL &= ~SDIO_DATACTL_RWTYPE; - } -} - -/*! - \brief enable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_enable(void) -{ - SDIO_DATACTL |= SDIO_DATACTL_IOEN; -} - -/*! - \brief disable the SD I/O mode specific operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_operation_disable(void) -{ - SDIO_DATACTL &= ~SDIO_DATACTL_IOEN; -} - -/*! - \brief enable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief disable the SD I/O suspend operation(SD I/O only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_suspend_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_SUSPEND; -} - -/*! - \brief enable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ATAEN; -} - -/*! - \brief disable the CE-ATA command(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ATAEN; -} - -/*! - \brief enable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_enable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_NINTEN; -} - -/*! - \brief disable the CE-ATA interrupt(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_interrupt_disable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_NINTEN; -} - -/*! - \brief enable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_enable(void) -{ - SDIO_CMDCTL |= SDIO_CMDCTL_ENCMDC; -} - -/*! - \brief disable the CE-ATA command completion signal(CE-ATA only) - \param[in] none - \param[out] none - \retval none -*/ -void sdio_ceata_command_completion_disable(void) -{ - SDIO_CMDCTL &= ~SDIO_CMDCTL_ENCMDC; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c deleted file mode 100644 index 3f842251fc..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c +++ /dev/null @@ -1,882 +0,0 @@ -/*! - \file gd32f4xx_spi.c - \brief SPI driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#include "gd32f4xx_spi.h" -#include "gd32f4xx_rcu.h" - -/* SPI/I2S parameter initialization mask */ -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ -#define I2S_FULL_DUPLEX_MASK ((uint32_t)0x00000480U) /*!< I2S full duples mode configure parameter initialization mask */ - -/* default value */ -#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /*!< default value of SPI_I2SPSC register */ - -/*! - \brief deinitialize SPI and I2S - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5),include I2S1_ADD and I2S2_ADD - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph){ - case SPI0: - /* reset SPI0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1,I2S1 and I2S1_ADD */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - case SPI2: - /* reset SPI2,I2S2 and I2S2_ADD */ - rcu_periph_reset_enable(RCU_SPI2RST); - rcu_periph_reset_disable(RCU_SPI2RST); - break; - case SPI3: - /* reset SPI3 */ - rcu_periph_reset_enable(RCU_SPI3RST); - rcu_periph_reset_disable(RCU_SPI3RST); - break; - case SPI4: - /* reset SPI4 */ - rcu_periph_reset_enable(RCU_SPI4RST); - rcu_periph_reset_disable(RCU_SPI4RST); - break; - case SPI5: - /* reset SPI5 */ - rcu_periph_reset_enable(RCU_SPI5RST); - rcu_periph_reset_disable(RCU_SPI5RST); - break; - default : - break; - } -} - -/*! - \brief initialize the parameters of SPI struct with default values - \param[in] none - \param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct *spi_struct) -{ - /* configure the structure with default value */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; - spi_struct->endian = SPI_ENDIAN_MSB; -} -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE. - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval none -*/ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ - uint32_t reg = 0U; - reg = SPI_CTL0(spi_periph); - reg &= SPI_INIT_MASK; - - /* select SPI as master or slave */ - reg |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg |= spi_struct->trans_mode; - /* select SPI frame size */ - reg |= spi_struct->frame_size; - /* select SPI nss use hardware or software */ - reg |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg |= spi_struct->endian; - /* select SPI polarity and phase */ - reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg |= spi_struct->prescale; - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg; - - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPIx(x=1,2) - \param[in] i2s_mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX : I2S slave transmit mode - \arg I2S_MODE_SLAVERX : I2S slave receive mode - \arg I2S_MODE_MASTERTX : I2S master transmit mode - \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS : I2S phillips standard - \arg I2S_STD_MSB : I2S MSB standard - \arg I2S_STD_LSB : I2S LSB standard - \arg I2S_STD_PCMSHORT : I2S PCM short standard - \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW : I2S clock polarity low level - \arg I2S_CKPL_HIGH : I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl) -{ - uint32_t reg= 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)i2s_mode; - /* select I2S standard */ - reg |= (uint32_t)i2s_standard; - /* select I2S polarity */ - reg |= (uint32_t)i2s_ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescale - \param[in] spi_periph: SPIx(x=1,2) - \param[in] i2s_audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] i2s_frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] i2s_mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - -#ifndef I2S_EXTERNAL_CLOCK_IN - uint32_t plli2sm = 0U, plli2sn = 0U, plli2sr = 0U; -#endif /* I2S_EXTERNAL_CLOCK_IN */ - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; - -#ifdef I2S_EXTERNAL_CLOCK_IN - rcu_i2s_clock_config(RCU_I2SSRC_I2S_CKIN); - - /* set the I2S clock to the external clock input value */ - i2sclock = I2S_EXTERNAL_CLOCK_IN; -#else - - /* turn on the oscillator HXTAL */ - rcu_osci_on(RCU_HXTAL); - /* wait for oscillator stabilization flags is SET */ - rcu_osci_stab_wait(RCU_HXTAL); - /* turn on the PLLI2S */ - rcu_osci_on(RCU_PLLI2S_CK); - /* wait for PLLI2S flags is SET */ - rcu_osci_stab_wait(RCU_PLLI2S_CK); - /* configure the I2S clock source selection */ - rcu_i2s_clock_config(RCU_I2SSRC_PLLI2S); - - /* get the RCU_PLL_PLLPSC value */ - plli2sm = (uint32_t)(RCU_PLL & RCU_PLL_PLLPSC); - /* get the RCU_PLLI2S_PLLI2SN value */ - plli2sn = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SN) >> 6); - /* get the RCU_PLLI2S_PLLI2SR value */ - plli2sr = (uint32_t)((RCU_PLLI2S & RCU_PLLI2S_PLLI2SR) >> 28); - - if((RCU_PLL & RCU_PLL_PLLSEL) == RCU_PLLSRC_HXTAL) - { - /* get the I2S source clock value */ - i2sclock = (uint32_t)(((HXTAL_VALUE / plli2sm) * plli2sn) / plli2sr); - } - else - { /* get the I2S source clock value */ - i2sclock = (uint32_t)(((IRC16M_VALUE / plli2sm) * plli2sn) / plli2sr); - } -#endif /* I2S_EXTERNAL_CLOCK_IN */ - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == i2s_mckout){ - clks = (uint32_t)(((i2sclock / 256U) * 10U) / i2s_audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == i2s_frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / i2s_audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / i2s_audiosample); - } - } - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv< 2U) || (i2sdiv > 255U)){ - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | i2s_mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN|SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)i2s_frameformat; -} - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI nss output - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI nss output - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI nss pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI nss pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA - \arg SPI_DMA_RECEIVE: SPI receive data use DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma) -{ - if(SPI_DMA_TRANSMIT == spi_dma){ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief diable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data use DMA - \arg SPI_DMA_RECEIVE: SPI receive data use DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma) -{ - if(SPI_DMA_TRANSMIT == spi_dma){ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \param[out] none - \retval none -*/ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* configure SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= (uint32_t)frame_format; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - SPI_DATA(spi_periph) = (uint32_t)data; -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - return ((uint16_t)SPI_DATA(spi_periph)); -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc) -{ - if(SPI_CRC_TX == spi_crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - -/*! - \brief configure i2s full duplex mode - \param[in] i2s_add_periph: I2Sx_ADD(x=1,2) - \param[in] i2s_mode: - \arg I2S_MODE_SLAVETX : I2S slave transmit mode - \arg I2S_MODE_SLAVERX : I2S slave receive mode - \arg I2S_MODE_MASTERTX : I2S master transmit mode - \arg I2S_MODE_MASTERRX : I2S master receive mode - \param[in] i2s_standard: - \arg I2S_STD_PHILLIPS : I2S phillips standard - \arg I2S_STD_MSB : I2S MSB standard - \arg I2S_STD_LSB : I2S LSB standard - \arg I2S_STD_PCMSHORT : I2S PCM short standard - \arg I2S_STD_PCMLONG : I2S PCM long standard - \param[in] i2s_ckpl: - \arg I2S_CKPL_LOW : I2S clock polarity low level - \arg I2S_CKPL_HIGH : I2S clock polarity high level - \param[in] i2s_frameformat: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[out] none - \retval none -*/ -void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, - uint32_t i2s_ckpl, uint32_t i2s_frameformat) -{ - uint32_t reg = 0U, tmp = 0U; - - reg = I2S_ADD_I2SCTL(i2s_add_periph); - reg &= I2S_FULL_DUPLEX_MASK; - - /* get the mode of the extra I2S module I2Sx_ADD */ - if((I2S_MODE_MASTERTX == i2s_mode) || (I2S_MODE_SLAVETX == i2s_mode)){ - tmp = I2S_MODE_SLAVERX; - }else{ - tmp = I2S_MODE_SLAVETX; - } - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)tmp; - /* select I2S standard */ - reg |= (uint32_t)i2s_standard; - /* select I2S polarity */ - reg |= (uint32_t)i2s_ckpl; - /* configure data frame format */ - reg |= (uint32_t)i2s_frameformat; - - /* write to SPI_I2SCTL register */ - I2S_ADD_I2SCTL(i2s_add_periph) = (uint32_t)reg; -} - -/*! - \brief enable quad wire SPI - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none -*/ -void qspi_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; -} - -/*! - \brief disable quad wire SPI - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none -*/ -void qspi_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); -} - -/*! - \brief enable quad wire SPI write - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none -*/ -void qspi_write_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); -} - -/*! - \brief enable quad wire SPI read - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none -*/ -void qspi_read_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; -} - -/*! - \brief enable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none -*/ -void qspi_io23_output_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; -} - - /*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(only x=5) - \param[out] none - \retval none -*/ - void qspi_io23_output_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - switch(spi_i2s_int){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - switch(spi_i2s_int){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR : - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_int: SPI/I2S interrupt flag status - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t spi_i2s_int) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(spi_i2s_int){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE : - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE : - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR : - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR : - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR : - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR : - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI/I2S format error interrupt */ - case SPI_I2S_INT_FLAG_FERR : - reg1 = reg1 & SPI_STAT_FERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - /*get SPI/I2S interrupt flag status */ - if(reg1 && reg2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[in] spi_i2s_flag: SPI/I2S flag status - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t spi_i2s_flag) -{ - if(SPI_STAT(spi_periph) & spi_i2s_flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2,3,4,5) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c deleted file mode 100644 index 6fa0a776d0..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c +++ /dev/null @@ -1,204 +0,0 @@ -/*! - \file gd32f4xx_syscfg.c - \brief SYSCFG driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_syscfg.h" - -/*! - \brief reset the SYSCFG registers - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_deinit(void) -{ - rcu_periph_reset_enable(RCU_SYSCFGRST); - rcu_periph_reset_disable(RCU_SYSCFGRST); -} - -/*! - \brief configure the boot mode - \param[in] syscfg_bootmode: selects the memory remapping - only one parameter can be selected which is shown as below: - \arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000 - \arg SYSCFG_BOOTMODE_BOOTLOADER: boot loader (0x1FFF0000 - 0x1FFF77FF) is mapped at address 0x00000000 - \arg SYSCFG_BOOTMODE_EXMC_SRAM: SRAM/NOR 0 and 1 of EXMC (0x60000000~0x67FFFFFF) is mapped at address 0x00000000 - \arg SYSCFG_BOOTMODE_SRAM: SRAM0 of on-chip SRAM (0x20000000~0x2001BFFF) is mapped at address 0x00000000 - \arg SYSCFG_BOOTMODE_EXMC_SDRAM: SDRAM bank0 of EXMC (0xC0000000~0xC7FFFFFF) is mapped at address 0x00000000 - \param[out] none - \retval none -*/ -void syscfg_bootmode_config(uint8_t syscfg_bootmode) -{ - /* reset the SYSCFG_CFG0_BOOT_MODE bit and set according to syscfg_bootmode */ - SYSCFG_CFG0 &= ~SYSCFG_CFG0_BOOT_MODE; - SYSCFG_CFG0 |= (uint32_t)syscfg_bootmode; -} - -/*! - \brief FMC memory mapping swap - \param[in] syscfg_fmc_swap: selects the interal flash bank swapping - only one parameter can be selected which is shown as below: - \arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000 - \arg SYSCFG_FMC_SWP_BANK1: bank 1 is mapped at address 0x08000000 and bank 0 is mapped at address 0x08100000 - \param[out] none - \retval none -*/ -void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap) -{ - uint32_t reg; - reg = SYSCFG_CFG0; - /* reset the FMC_SWP bit and set according to syscfg_fmc_swap */ - reg &= ~SYSCFG_CFG0_FMC_SWP; - SYSCFG_CFG0 = (reg | syscfg_fmc_swap); -} - -/*! - \brief EXMC memory mapping swap - \param[in] syscfg_exmc_swap: selects the memories in EXMC swapping - only one parameter can be selected which is shown as below: - \arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card - \arg SYSCFG_EXMC_SWP_DISABLE: no memory mapping swap - \param[out] none - \retval none -*/ -void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap) -{ - uint32_t reg; - - reg = SYSCFG_CFG0; - /* reset the SYSCFG_CFG0_EXMC_SWP bits and set according to syscfg_exmc_swap */ - reg &= ~SYSCFG_CFG0_EXMC_SWP; - SYSCFG_CFG0 = (reg | syscfg_exmc_swap); -} - -/*! - \brief configure the GPIO pin as EXTI Line - \param[in] exti_port: specify the GPIO port used in EXTI - only one parameter can be selected which is shown as below: - \arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port - \param[in] exti_pin: specify the EXTI line - only one parameter can be selected which is shown as below: - \arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin - \param[out] none - \retval none -*/ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) -{ - uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); - uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); - - switch(exti_pin/EXTI_SS_JSTEP){ - case EXTISS0: - /* clear EXTI source line(0..3) */ - SYSCFG_EXTISS0 &= clear_exti_mask; - /* configure EXTI soure line(0..3) */ - SYSCFG_EXTISS0 |= config_exti_mask; - break; - case EXTISS1: - /* clear EXTI soure line(4..7) */ - SYSCFG_EXTISS1 &= clear_exti_mask; - /* configure EXTI soure line(4..7) */ - SYSCFG_EXTISS1 |= config_exti_mask; - break; - case EXTISS2: - /* clear EXTI soure line(8..11) */ - SYSCFG_EXTISS2 &= clear_exti_mask; - /* configure EXTI soure line(8..11) */ - SYSCFG_EXTISS2 |= config_exti_mask; - break; - case EXTISS3: - /* clear EXTI soure line(12..15) */ - SYSCFG_EXTISS3 &= clear_exti_mask; - /* configure EXTI soure line(12..15) */ - SYSCFG_EXTISS3 |= config_exti_mask; - break; - default: - break; - } -} - -/*! - \brief configure the PHY interface for the ethernet MAC - \param[in] syscfg_enet_phy_interface: specifies the media interface mode. - only one parameter can be selected which is shown as below: - \arg SYSCFG_ENET_PHY_MII: MII mode is selected - \arg SYSCFG_ENET_PHY_RMII: RMII mode is selected - \param[out] none - \retval none -*/ -void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface) -{ - uint32_t reg; - - reg = SYSCFG_CFG1; - /* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */ - reg &= ~SYSCFG_CFG1_ENET_PHY_SEL; - SYSCFG_CFG1 = (reg | syscfg_enet_phy_interface); -} - -/*! - \brief configure the I/O compensation cell - \param[in] syscfg_compensation: specifies the I/O compensation cell mode - only one parameter can be selected which is shown as below: - \arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled - \arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled - \param[out] none - \retval none -*/ -void syscfg_compensation_config(uint32_t syscfg_compensation) -{ - uint32_t reg; - - reg = SYSCFG_CPSCTL; - /* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */ - reg &= ~SYSCFG_CPSCTL_CPS_EN; - SYSCFG_CPSCTL = (reg | syscfg_compensation); -} - -/*! - \brief checks whether the I/O compensation cell ready flag is set or not - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus syscfg_flag_get(void) -{ - if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)){ - return SET; - }else{ - return RESET; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c deleted file mode 100644 index e312680222..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c +++ /dev/null @@ -1,2063 +0,0 @@ -/*! - \file gd32f4xx_timer.c - \brief TIMER driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#include "gd32f4xx_timer.h" - -/*! - \brief deinit a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph){ - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER1: - /* reset TIMER1 */ - rcu_periph_reset_enable(RCU_TIMER1RST); - rcu_periph_reset_disable(RCU_TIMER1RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER3: - /* reset TIMER3 */ - rcu_periph_reset_enable(RCU_TIMER3RST); - rcu_periph_reset_disable(RCU_TIMER3RST); - break; - case TIMER4: - /* reset TIMER4 */ - rcu_periph_reset_enable(RCU_TIMER4RST); - rcu_periph_reset_disable(RCU_TIMER4RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER6: - /* reset TIMER6 */ - rcu_periph_reset_enable(RCU_TIMER6RST); - rcu_periph_reset_disable(RCU_TIMER6RST); - break; - case TIMER7: - /* reset TIMER7 */ - rcu_periph_reset_enable(RCU_TIMER7RST); - rcu_periph_reset_disable(RCU_TIMER7RST); - break; - case TIMER8: - /* reset TIMER8 */ - rcu_periph_reset_enable(RCU_TIMER8RST); - rcu_periph_reset_disable(RCU_TIMER8RST); - break; - case TIMER9: - /* reset TIMER9 */ - rcu_periph_reset_enable(RCU_TIMER9RST); - rcu_periph_reset_disable(RCU_TIMER9RST); - break; - case TIMER10: - /* reset TIMER10 */ - rcu_periph_reset_enable(RCU_TIMER10RST); - rcu_periph_reset_disable(RCU_TIMER10RST); - break; - case TIMER11: - /* reset TIMER11 */ - rcu_periph_reset_enable(RCU_TIMER11RST); - rcu_periph_reset_disable(RCU_TIMER11RST); - break; - case TIMER12: - /* reset TIMER12 */ - rcu_periph_reset_enable(RCU_TIMER12RST); - rcu_periph_reset_disable(RCU_TIMER12RST); - break; - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct* initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock,0~65535 - alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN - period: counter auto reload value,(TIMER1,TIMER4,32 bit) - clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) - || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; - } - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a TIMER - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] prescaler: prescaler value,0~65535 - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] repetition: the counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] autoreload: the counter auto-reload value - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] counter: the counter value,0~65535 - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph , uint32_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0..8,11) - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0..13) - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint32_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source enable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13) - \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13) - \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7) - \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7) - \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11) - \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11) - \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7) - \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)flag); -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to enable - one or more parameters can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to disable - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7) - \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7) - \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7) - \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: please refer to the following parameters - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7) - \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: please refer to the following parameters - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11) - \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| - ((uint32_t)(breakpara->ideloffstate))| - ((uint32_t)(breakpara->deadtime))| - ((uint32_t)(breakpara->breakpolarity))| - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode))| - ((uint32_t)(breakpara->breakstate))) ; -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,7) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief configure TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl){ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); - } - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); - } - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - - if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)){ - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); - } - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] pulse: channel output pulse value,0~65535 - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \arg TIMER_CH_2: TIMER channel2 - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel){ - /* read TIMER channel 0 capture compare register value */ - case TIMER_CH_0: - count_value = TIMER_CH0CV(timer_periph); - break; - /* read TIMER channel 1 capture compare register value */ - case TIMER_CH_1: - count_value = TIMER_CH1CV(timer_periph); - break; - /* read TIMER channel 2 capture compare register value */ - case TIMER_CH_2: - count_value = TIMER_CH2CV(timer_periph); - break; - /* read TIMER channel 3 capture compare register value */ - case TIMER_CH_3: - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ - icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ - icpolarity = TIMER_IC_POLARITY_RISING; - } - - /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ - icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel){ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: please refer to the following parameters - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..4,7,8,11)) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0..7) - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7,9,10,12,13)) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7,9,10,12,13)) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7,9,10,12,13)) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0..4,7,9,10,12,13)) - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7,9,10,12,13)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) - \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) - \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) - \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.(TIMERx(x=0..4,7,8,11)) - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, - uint16_t ic0polarity, uint16_t ic1polarity) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph, intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active high or rising edge active - \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, - uint16_t extpolarity, uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0..4,7,8,11) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief configure TIMER channel remap function - \param[in] timer_periph: TIMERx(x=1,4,10) - \param[in] remap: - only one parameter can be selected which is shown as below: - \arg TIMER1_ITI1_RMP_TIMER7_TRGO: timer1 internal trigger input1 remap to TIMER7_TRGO - \arg TIMER1_ITI1_RMP_ETHERNET_PTP: timer1 internal trigger input1 remap to ethernet PTP - \arg TIMER1_ITI1_RMP_USB_FS_SOF: timer1 internal trigger input1 remap to USB FS SOF - \arg TIMER1_ITI1_RMP_USB_HS_SOF: timer1 internal trigger input1 remap to USB HS SOF - \arg TIMER4_CI3_RMP_GPIO: timer4 channel 3 input remap to GPIO pin - \arg TIMER4_CI3_RMP_IRC32K: timer4 channel 3 input remap to IRC32K - \arg TIMER4_CI3_RMP_LXTAL: timer4 channel 3 input remap to LXTAL - \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt - \arg TIMER10_ITI1_RMP_GPIO: timer10 internal trigger input1 remap based on GPIO setting - \arg TIMER10_ITI1_RMP_RTC_HXTAL_DIV: timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) - \param[out] none - \retval none -*/ -void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) -{ - TIMER_IRMP(timer_periph) = (uint32_t)remap; -} - -/*! - \brief configure TIMER write CHxVAL register selection - \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16) - \param[in] ccsel: - only one parameter can be selected which is shown as below: - \arg TIMER_CHVSEL_DISABLE: no effect - \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored - \param[out] none - \retval none -*/ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) -{ - if(TIMER_CHVSEL_ENABLE == ccsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CHVSEL_DISABLE == ccsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER output value selection - \param[in] timer_periph: TIMERx(x=0,7) - \param[in] outsel: - only one parameter can be selected which is shown as below: - \arg TIMER_OUTSEL_DISABLE: no effect - \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled - \param[out] none - \retval none -*/ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) -{ - if(TIMER_OUTSEL_ENABLE == outsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == outsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - }else{ - /* illegal parameters */ - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c deleted file mode 100644 index 9d719bb29b..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c +++ /dev/null @@ -1,598 +0,0 @@ -/*! - \file gd32f4xx_tli.c - \brief TLI driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_tli.h" - -#define TLI_DEFAULT_VALUE 0x00000000U -#define TLI_OPAQUE_VALUE 0x000000FFU - -/*! - \brief deinitialize TLI registers - \param[in] none - \param[out] none - \retval none -*/ -void tli_deinit(void) -{ - rcu_periph_reset_enable(RCU_TLIRST); - rcu_periph_reset_disable(RCU_TLIRST); -} - -/*! - \brief initialize the parameters of TLI parameter structure with the default values, it is suggested - that call this function after a tli_parameter_struct structure is defined - \param[in] none - \param[out] tli_struct: the data needed to initialize TLI - synpsz_vpsz: size of the vertical synchronous pulse - synpsz_hpsz: size of the horizontal synchronous pulse - backpsz_vbpsz: size of the vertical back porch plus synchronous pulse - backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse - activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse - activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse - totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous - totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous - backcolor_red: background value red - backcolor_green: background value green - backcolor_blue: background value blue - signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT - signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT - signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT - signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI - \retval none -*/ -void tli_struct_para_init(tli_parameter_struct *tli_struct) -{ - /* initialize the struct parameters with default values */ - tli_struct->synpsz_vpsz = TLI_DEFAULT_VALUE; - tli_struct->synpsz_hpsz = TLI_DEFAULT_VALUE; - tli_struct->backpsz_vbpsz = TLI_DEFAULT_VALUE; - tli_struct->backpsz_hbpsz = TLI_DEFAULT_VALUE; - tli_struct->activesz_vasz = TLI_DEFAULT_VALUE; - tli_struct->activesz_hasz = TLI_DEFAULT_VALUE; - tli_struct->totalsz_vtsz = TLI_DEFAULT_VALUE; - tli_struct->totalsz_htsz = TLI_DEFAULT_VALUE; - tli_struct->backcolor_red = TLI_DEFAULT_VALUE; - tli_struct->backcolor_green = TLI_DEFAULT_VALUE; - tli_struct->backcolor_blue = TLI_DEFAULT_VALUE; - tli_struct->signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; - tli_struct->signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; - tli_struct->signalpolarity_de = TLI_DE_ACTLIVE_LOW; - tli_struct->signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; -} - -/*! - \brief initialize TLI display timing parameters - \param[in] tli_struct: the data needed to initialize TLI - synpsz_vpsz: size of the vertical synchronous pulse - synpsz_hpsz: size of the horizontal synchronous pulse - backpsz_vbpsz: size of the vertical back porch plus synchronous pulse - backpsz_hbpsz: size of the horizontal back porch plus synchronous pulse - activesz_vasz: size of the vertical active area width plus back porch and synchronous pulse - activesz_hasz: size of the horizontal active area width plus back porch and synchronous pulse - totalsz_vtsz: vertical total size of the display, including active area, back porch, synchronous - totalsz_htsz: vorizontal total size of the display, including active area, back porch, synchronous - backcolor_red: background value red - backcolor_green: background value green - backcolor_blue: background value blue - signalpolarity_hs: TLI_HSYN_ACTLIVE_LOW,TLI_HSYN_ACTLIVE_HIGHT - signalpolarity_vs: TLI_VSYN_ACTLIVE_LOW,TLI_VSYN_ACTLIVE_HIGHT - signalpolarity_de: TLI_DE_ACTLIVE_LOW,TLI_DE_ACTLIVE_HIGHT - signalpolarity_pixelck: TLI_PIXEL_CLOCK_TLI,TLI_PIXEL_CLOCK_INVERTEDTLI - \param[out] none - \retval none -*/ -void tli_init(tli_parameter_struct *tli_struct) -{ - /* synchronous pulse size configuration */ - TLI_SPSZ &= ~(TLI_SPSZ_VPSZ|TLI_SPSZ_HPSZ); - TLI_SPSZ = (uint32_t)((uint32_t)tli_struct->synpsz_vpsz|((uint32_t)tli_struct->synpsz_hpsz<<16U)); - /* back-porch size configuration */ - TLI_BPSZ &= ~(TLI_BPSZ_VBPSZ|TLI_BPSZ_HBPSZ); - TLI_BPSZ = (uint32_t)((uint32_t)tli_struct->backpsz_vbpsz|((uint32_t)tli_struct->backpsz_hbpsz<<16U)); - /* active size configuration */ - TLI_ASZ &= ~(TLI_ASZ_VASZ|TLI_ASZ_HASZ); - TLI_ASZ = (tli_struct->activesz_vasz|(tli_struct->activesz_hasz<<16U)); - /* total size configuration */ - TLI_TSZ &= ~(TLI_TSZ_VTSZ|TLI_TSZ_HTSZ); - TLI_TSZ = (tli_struct->totalsz_vtsz|(tli_struct->totalsz_htsz<<16U)); - /* background color configuration */ - TLI_BGC &= ~(TLI_BGC_BVB|(TLI_BGC_BVG)|(TLI_BGC_BVR)); - TLI_BGC = (tli_struct->backcolor_blue|(tli_struct->backcolor_green<<8U)|(tli_struct->backcolor_red<<16U)); - TLI_CTL &= ~(TLI_CTL_HPPS|TLI_CTL_VPPS|TLI_CTL_DEPS|TLI_CTL_CLKPS); - TLI_CTL |= (tli_struct->signalpolarity_hs|tli_struct->signalpolarity_vs|\ - tli_struct->signalpolarity_de|tli_struct->signalpolarity_pixelck); - -} - -/*! - \brief configure TLI dither function - \param[in] dither_stat - only one parameter can be selected which is shown as below: - \arg TLI_DITHER_ENABLE - \arg TLI_DITHER_DISABLE - \param[out] none - \retval none -*/ -void tli_dither_config(uint8_t dither_stat) -{ - if(TLI_DITHER_ENABLE == dither_stat){ - TLI_CTL |= TLI_CTL_DFEN; - }else{ - TLI_CTL &= ~(TLI_CTL_DFEN); - } -} - -/*! - \brief enable TLI - \param[in] none - \param[out] none - \retval none -*/ -void tli_enable(void) -{ - TLI_CTL |= TLI_CTL_TLIEN; -} - -/*! - \brief disable TLI - \param[in] none - \param[out] none - \retval none -*/ -void tli_disable(void) -{ - TLI_CTL &= ~(TLI_CTL_TLIEN); -} - -/*! - \brief configure TLI reload mode - \param[in] reload_mod - only one parameter can be selected which is shown as below: - \arg TLI_FRAME_BLANK_RELOAD_EN - \arg TLI_REQUEST_RELOAD_EN - \param[out] none - \retval none -*/ -void tli_reload_config(uint8_t reload_mod) -{ - if(TLI_FRAME_BLANK_RELOAD_EN == reload_mod){ - /* the layer configuration will be reloaded at frame blank */ - TLI_RL |= TLI_RL_FBR; - }else{ - /* the layer configuration will be reloaded after this bit sets */ - TLI_RL |= TLI_RL_RQR; - } -} - -/*! - \brief initialize the parameters of TLI layer structure with the default values, it is suggested - that call this function after a tli_layer_parameter_struct structure is defined - \param[in] none - \param[out] layer_struct: TLI Layer parameter struct - layer_window_rightpos: window right position - layer_window_leftpos: window left position - layer_window_bottompos: window bottom position - layer_window_toppos: window top position - layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, - LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, - LAYER_PPF_AL44,LAYER_PPF_AL88 - layer_sa: specified alpha - layer_default_alpha: the default color alpha - layer_default_red: the default color red - layer_default_green: the default color green - layer_default_blue: the default color blue - layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA - layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA - layer_frame_bufaddr: frame buffer base address - layer_frame_buf_stride_offset: frame buffer stride offset - layer_frame_line_length: frame line length - layer_frame_total_line_number: frame total line number - \retval none -*/ -void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct) -{ - /* initialize the struct parameters with default values */ - layer_struct->layer_window_rightpos = TLI_DEFAULT_VALUE; - layer_struct->layer_window_leftpos = TLI_DEFAULT_VALUE; - layer_struct->layer_window_bottompos = TLI_DEFAULT_VALUE; - layer_struct->layer_window_toppos = TLI_DEFAULT_VALUE; - layer_struct->layer_ppf = LAYER_PPF_ARGB8888; - layer_struct->layer_sa = TLI_OPAQUE_VALUE; - layer_struct->layer_default_alpha = TLI_DEFAULT_VALUE; - layer_struct->layer_default_red = TLI_DEFAULT_VALUE; - layer_struct->layer_default_green = TLI_DEFAULT_VALUE; - layer_struct->layer_default_blue = TLI_DEFAULT_VALUE; - layer_struct->layer_acf1 = LAYER_ACF1_PASA; - layer_struct->layer_acf2 = LAYER_ACF2_PASA; - layer_struct->layer_frame_bufaddr = TLI_DEFAULT_VALUE; - layer_struct->layer_frame_buf_stride_offset = TLI_DEFAULT_VALUE; - layer_struct->layer_frame_line_length = TLI_DEFAULT_VALUE; - layer_struct->layer_frame_total_line_number = TLI_DEFAULT_VALUE; -} - -/*! - \brief initialize TLI layer - \param[in] layerx: LAYERx(x=0,1) - \param[in] layer_struct: TLI Layer parameter struct - layer_window_rightpos: window right position - layer_window_leftpos: window left position - layer_window_bottompos: window bottom position - layer_window_toppos: window top position - layer_ppf: LAYER_PPF_ARGB8888,LAYER_PPF_RGB888,LAYER_PPF_RGB565, - LAYER_PPF_ARG1555,LAYER_PPF_ARGB4444,LAYER_PPF_L8, - LAYER_PPF_AL44,LAYER_PPF_AL88 - layer_sa: specified alpha - layer_default_alpha: the default color alpha - layer_default_red: the default color red - layer_default_green: the default color green - layer_default_blue: the default color blue - layer_acf1: LAYER_ACF1_SA,LAYER_ACF1_PASA - layer_acf2: LAYER_ACF2_SA,LAYER_ACF2_PASA - layer_frame_bufaddr: frame buffer base address - layer_frame_buf_stride_offset: frame buffer stride offset - layer_frame_line_length: frame line length - layer_frame_total_line_number: frame total line number - \param[out] none - \retval none -*/ -void tli_layer_init(uint32_t layerx,tli_layer_parameter_struct *layer_struct) -{ - /* configure layer window horizontal position */ - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxHPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_leftpos|((uint32_t)layer_struct->layer_window_rightpos<<16U)); - /* configure layer window vertical position */ - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - TLI_LxVPOS(layerx) = (uint32_t)((uint32_t)layer_struct->layer_window_toppos|((uint32_t)layer_struct->layer_window_bottompos<<16U)); - /* configure layer packeted pixel format */ - TLI_LxPPF(layerx) &= ~(TLI_LxPPF_PPF); - TLI_LxPPF(layerx) = layer_struct->layer_ppf; - /* configure layer specified alpha */ - TLI_LxSA(layerx) &= ~(TLI_LxSA_SA); - TLI_LxSA(layerx) = layer_struct->layer_sa; - /* configure layer default color */ - TLI_LxDC(layerx) &= ~(TLI_LxDC_DCB|(TLI_LxDC_DCG)|(TLI_LxDC_DCR)|(TLI_LxDC_DCA)); - TLI_LxDC(layerx) = (uint32_t)((uint32_t)layer_struct->layer_default_blue|((uint32_t)layer_struct->layer_default_green<<8U) - |((uint32_t)layer_struct->layer_default_red<<16U) - |((uint32_t)layer_struct->layer_default_alpha<<24U)); - - /* configure layer alpha calculation factors */ - TLI_LxBLEND(layerx) &= ~(TLI_LxBLEND_ACF2|(TLI_LxBLEND_ACF1)); - TLI_LxBLEND(layerx) = ((layer_struct->layer_acf2)|(layer_struct->layer_acf1)); - /* configure layer frame buffer base address */ - TLI_LxFBADDR(layerx) &= ~(TLI_LxFBADDR_FBADD); - TLI_LxFBADDR(layerx) = (layer_struct->layer_frame_bufaddr); - /* configure layer frame line length */ - TLI_LxFLLEN(layerx) &= ~(TLI_LxFLLEN_FLL|(TLI_LxFLLEN_STDOFF)); - TLI_LxFLLEN(layerx) = (uint32_t)((uint32_t)layer_struct->layer_frame_line_length|((uint32_t)layer_struct->layer_frame_buf_stride_offset<<16U)); - /* configure layer frame total line number */ - TLI_LxFTLN(layerx) &= ~(TLI_LxFTLN_FTLN); - TLI_LxFTLN(layerx) = (uint32_t)(layer_struct->layer_frame_total_line_number); - -} - -/*! - \brief reconfigure window position - \param[in] layerx: LAYERx(x=0,1) - \param[in] offset_x: new horizontal offset - \param[in] offset_y: new vertical offset - \param[out] none - \retval none -*/ -void tli_layer_window_offset_modify(uint32_t layerx,uint16_t offset_x,uint16_t offset_y) -{ - /* configure window start position */ - uint32_t layer_ppf, line_num, hstart, vstart; - uint32_t line_length = 0U; - TLI_LxHPOS(layerx) &= ~(TLI_LxHPOS_WLP|(TLI_LxHPOS_WRP)); - TLI_LxVPOS(layerx) &= ~(TLI_LxVPOS_WTP|(TLI_LxVPOS_WBP)); - hstart = (uint32_t)offset_x+(((TLI_BPSZ & TLI_BPSZ_HBPSZ)>>16U)+1U); - vstart = (uint32_t)offset_y+((TLI_BPSZ & TLI_BPSZ_VBPSZ)+1U); - line_num = (TLI_LxFTLN(layerx) & TLI_LxFTLN_FTLN); - layer_ppf = (TLI_LxPPF(layerx) & TLI_LxPPF_PPF); - /* the bytes of a line equal TLI_LxFLLEN_FLL bits value minus 3 */ - switch(layer_ppf){ - case LAYER_PPF_ARGB8888: - /* each pixel includes 4bytes, when pixel format is ARGB8888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/4U); - break; - case LAYER_PPF_RGB888: - /* each pixel includes 3bytes, when pixel format is RGB888 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/3U); - break; - case LAYER_PPF_RGB565: - case LAYER_PPF_ARGB1555: - case LAYER_PPF_ARGB4444: - case LAYER_PPF_AL88: - /* each pixel includes 2bytes, when pixel format is RGB565,ARG1555,ARGB4444 or AL88 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)/2U); - break; - case LAYER_PPF_L8: - case LAYER_PPF_AL44: - /* each pixel includes 1byte, when pixel format is L8 or AL44 */ - line_length = (((TLI_LxFLLEN(layerx) & TLI_LxFLLEN_FLL)-3U)); - break; - default: - break; - } - /* reconfigure window position */ - TLI_LxHPOS(layerx) = (hstart|((hstart+line_length-1U)<<16U)); - TLI_LxVPOS(layerx) = (vstart|((vstart+line_num-1U)<<16U)); -} - -/*! - \brief initialize the parameters of TLI layer LUT structure with the default values, it is suggested - that call this function after a tli_layer_lut_parameter_struct structure is defined - \param[in] none - \param[out] lut_struct: TLI layer LUT parameter struct - layer_table_addr: look up table write address - layer_lut_channel_red: red channel of a LUT entry - layer_lut_channel_green: green channel of a LUT entry - layer_lut_channel_blue: blue channel of a LUT entry - \retval none -*/ -void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct) -{ - /* initialize the struct parameters with default values */ - lut_struct->layer_table_addr = TLI_DEFAULT_VALUE; - lut_struct->layer_lut_channel_red = TLI_DEFAULT_VALUE; - lut_struct->layer_lut_channel_green = TLI_DEFAULT_VALUE; - lut_struct->layer_lut_channel_blue = TLI_DEFAULT_VALUE; -} - -/*! - \brief initialize TLI layer LUT - \param[in] layerx: LAYERx(x=0,1) - \param[in] lut_struct: TLI layer LUT parameter struct - layer_table_addr: look up table write address - layer_lut_channel_red: red channel of a LUT entry - layer_lut_channel_green: green channel of a LUT entry - layer_lut_channel_blue: blue channel of a LUT entry - \param[out] none - \retval none -*/ -void tli_lut_init(uint32_t layerx,tli_layer_lut_parameter_struct *lut_struct) -{ - TLI_LxLUT(layerx) &= ~(TLI_LxLUT_TB|TLI_LxLUT_TG|TLI_LxLUT_TR|TLI_LxLUT_TADD); - TLI_LxLUT(layerx) = (uint32_t)(((uint32_t)lut_struct->layer_lut_channel_blue)|((uint32_t)lut_struct->layer_lut_channel_green<<8U) - |((uint32_t)lut_struct->layer_lut_channel_red<<16U - |((uint32_t)lut_struct->layer_table_addr<<24U))); -} - -/*! - \brief initialize TLI layer color key - \param[in] layerx: LAYERx(x=0,1) - \param[in] redkey: color key red - \param[in] greenkey: color key green - \param[in] bluekey: color key blue - \param[out] none - \retval none -*/ -void tli_color_key_init(uint32_t layerx,uint8_t redkey,uint8_t greenkey,uint8_t bluekey) -{ - TLI_LxCKEY(layerx) = (((uint32_t)bluekey)|((uint32_t)greenkey<<8U)|((uint32_t)redkey<<16U)); -} - -/*! - \brief enable TLI layer - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_layer_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_LEN; -} - -/*! - \brief disable TLI layer - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_layer_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LEN); -} - -/*! - \brief enable TLI layer color keying - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_color_key_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_CKEYEN; -} - -/*! - \brief disable TLI layer color keying - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_color_key_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_CKEYEN); -} - -/*! - \brief enable TLI layer LUT - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_lut_enable(uint32_t layerx) -{ - TLI_LxCTL(layerx) |= TLI_LxCTL_LUTEN; -} - -/*! - \brief disable TLI layer LUT - \param[in] layerx: LAYERx(x=0,1) - \param[out] none - \retval none -*/ -void tli_lut_disable(uint32_t layerx) -{ - TLI_LxCTL(layerx) &= ~(TLI_LxCTL_LUTEN); -} - -/*! - \brief set line mark value - \param[in] line_num: line number - \param[out] none - \retval none -*/ -void tli_line_mark_set(uint16_t line_num) -{ - TLI_LM &= ~(TLI_LM_LM); - TLI_LM = (uint32_t)line_num; -} - -/*! - \brief get current displayed position - \param[in] none - \param[out] none - \retval position of current pixel -*/ -uint32_t tli_current_pos_get(void) -{ - return TLI_CPPOS; -} - -/*! - \brief enable TLI interrupt - \param[in] int_flag: TLI interrupt flags - one or more parameters can be selected which are shown as below: - \arg TLI_INT_LM: line mark interrupt - \arg TLI_INT_FE: FIFO error interrupt - \arg TLI_INT_TE: transaction error interrupt - \arg TLI_INT_LCR: layer configuration reloaded interrupt - \param[out] none - \retval none -*/ -void tli_interrupt_enable(uint32_t int_flag) -{ - TLI_INTEN |= (int_flag); -} - -/*! - \brief disable TLI interrupt - \param[in] int_flag: TLI interrupt flags - one or more parameters can be selected which are shown as below: - \arg TLI_INT_LM: line mark interrupt - \arg TLI_INT_FE: FIFO error interrupt - \arg TLI_INT_TE: transaction error interrupt - \arg TLI_INT_LCR: layer configuration reloaded interrupt - \param[out] none - \retval none -*/ -void tli_interrupt_disable(uint32_t int_flag) -{ - TLI_INTEN &= ~(int_flag); -} - -/*! - \brief get TLI interrupt flag - \param[in] int_flag: TLI interrupt flags - one or more parameters can be selected which are shown as below: - \arg TLI_INT_FLAG_LM: line mark interrupt flag - \arg TLI_INT_FLAG_FE: FIFO error interrupt flag - \arg TLI_INT_FLAG_TE: transaction error interrupt flag - \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus tli_interrupt_flag_get(uint32_t int_flag) -{ - uint32_t state; - state = TLI_INTF; - if(state & int_flag){ - state = TLI_INTEN; - if(state & int_flag){ - return SET; - } - } - return RESET; -} - -/*! - \brief clear TLI interrupt flag - \param[in] int_flag: TLI interrupt flags - one or more parameters can be selected which are shown as below: - \arg TLI_INT_FLAG_LM: line mark interrupt flag - \arg TLI_INT_FLAG_FE: FIFO error interrupt flag - \arg TLI_INT_FLAG_TE: transaction error interrupt flag - \arg TLI_INT_FLAG_LCR: layer configuration reloaded interrupt flag - \param[out] none - \retval none -*/ -void tli_interrupt_flag_clear(uint32_t int_flag) -{ - TLI_INTC |= (int_flag); -} - -/*! - \brief get TLI flag or state in TLI_INTF register or TLI_STAT register - \param[in] flag: TLI flags or states - only one parameter can be selected which is shown as below: - \arg TLI_FLAG_VDE: current VDE state - \arg TLI_FLAG_HDE: current HDE state - \arg TLI_FLAG_VS: current VS status of the TLI - \arg TLI_FLAG_HS: current HS status of the TLI - \arg TLI_FLAG_LM: line mark interrupt flag - \arg TLI_FLAG_FE: FIFO error interrupt flag - \arg TLI_FLAG_TE: transaction error interrupt flag - \arg TLI_FLAG_LCR: layer configuration reloaded interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus tli_flag_get(uint32_t flag) -{ - uint32_t stat; - /* choose which register to get flag or state */ - if(flag >> 31U){ - stat = TLI_INTF; - }else{ - stat = TLI_STAT; - } - if(flag & stat){ - return SET; - }else{ - return RESET; - } -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c deleted file mode 100644 index 8c86bb832e..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c +++ /dev/null @@ -1,155 +0,0 @@ -/*! - \file gd32f4xx_trng.c - \brief TRNG driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32f4xx_trng.h" - -/*! - \brief deinitialize the TRNG - \param[in] none - \param[out] none - \retval none -*/ -void trng_deinit(void) -{ - rcu_periph_reset_enable(RCU_TRNGRST); - rcu_periph_reset_disable(RCU_TRNGRST); -} - -/*! - \brief enable the TRNG interface - \param[in] none - \param[out] none - \retval none -*/ -void trng_enable(void) -{ - TRNG_CTL |= TRNG_CTL_TRNGEN; -} - -/*! - \brief disable the TRNG interface - \param[in] none - \param[out] none - \retval none -*/ -void trng_disable(void) -{ - TRNG_CTL &= ~TRNG_CTL_TRNGEN; -} - -/*! - \brief get the true random data - \param[in] none - \param[out] none - \retval the generated random data -*/ -uint32_t trng_get_true_random_data(void) -{ - return (TRNG_DATA); -} - -/*! - \brief enable the TRNG interrupt - \param[in] none - \param[out] none - \retval none -*/ -void trng_interrupt_enable(void) -{ - TRNG_CTL |= TRNG_CTL_IE; -} - -/*! - \brief disable the TRNG interrupt - \param[in] none - \param[out] none - \retval none -*/ -void trng_interrupt_disable(void) -{ - TRNG_CTL &= ~TRNG_CTL_IE; -} - -/*! - \brief get the trng status flags - \param[in] flag: trng status flag, refer to trng_flag_enum - only one parameter can be selected which is shown as below: - \arg TRNG_FLAG_DRDY: Random Data ready status - \arg TRNG_FLAG_CECS: Clock error current status - \arg TRNG_FLAG_SECS: Seed error current status - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus trng_flag_get(trng_flag_enum flag) -{ - if(RESET != (TRNG_STAT & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum - only one parameter can be selected which is shown as below: - \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag) -{ - if(RESET != (TRNG_STAT & int_flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the trng interrupt flags - \param[in] int_flag: trng interrupt flag, refer to trng_int_flag_enum - only one parameter can be selected which is shown as below: - \arg TRNG_INT_FLAG_CEIF: clock error interrupt flag - \arg TRNG_INT_FLAG_SEIF: Seed error interrupt flag - \param[out] none - \retval none -*/ -void trng_interrupt_flag_clear(trng_int_flag_enum int_flag) -{ - TRNG_STAT &= ~(uint32_t)int_flag; -} diff --git a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c b/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c deleted file mode 100644 index 1b864e3b96..0000000000 --- a/bsp/gd32450z-eval/Libraries/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c +++ /dev/null @@ -1,1009 +0,0 @@ -/*! - \file gd32f4xx_usart.c - \brief USART driver - - \version 2016-08-15, V1.0.0, firmware for GD32F4xx - \version 2018-12-12, V2.0.0, firmware for GD32F4xx - \version 2020-09-30, V2.1.0, firmware for GD32F4xx -*/ - -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - - -#include "gd32f4xx_usart.h" - -/* USART register bit offset */ -#define GP_GUAT_OFFSET ((uint32_t)8U) /* bit offset of GUAT in USART_GP */ -#define CTL3_SCRTNUM_OFFSET ((uint32_t)1U) /* bit offset of SCRTNUM in USART_CTL3 */ -#define RT_BL_OFFSET ((uint32_t)24U) /* bit offset of BL in USART_RT */ - -/*! - \brief reset USART/UART - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph){ - case USART0: - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - case USART2: - rcu_periph_reset_enable(RCU_USART2RST); - rcu_periph_reset_disable(RCU_USART2RST); - break; - case USART5: - rcu_periph_reset_enable(RCU_USART5RST); - rcu_periph_reset_disable(RCU_USART5RST); - break; - case UART3: - rcu_periph_reset_enable(RCU_UART3RST); - rcu_periph_reset_disable(RCU_UART3RST); - break; - case UART4: - rcu_periph_reset_enable(RCU_UART4RST); - rcu_periph_reset_disable(RCU_UART4RST); - break; - case UART6: - rcu_periph_reset_enable(RCU_UART6RST); - rcu_periph_reset_disable(RCU_UART6RST); - break; - case UART7: - rcu_periph_reset_enable(RCU_UART7RST); - rcu_periph_reset_disable(RCU_UART7RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ - case USART0: - uclk=rcu_clock_freq_get(CK_APB2); - break; - case USART5: - uclk=rcu_clock_freq_get(CK_APB2); - break; - case USART1: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case USART2: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART3: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART4: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART6: - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART7: - uclk=rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ - /* when oversampling by 8, configure the value of USART_BAUD */ - udiv = ((2U*uclk) + baudval/2U)/baudval; - intdiv = udiv & 0xfff0U; - fradiv = (udiv>>1U) & 0x7U; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - }else{ - /* when oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; - intdiv = udiv & 0xfff0U; - fradiv = udiv & 0xfU; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } -} - -/*! - \brief configure USART parity function - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] paritycfg: configure USART parity - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_EVEN: even parity - \arg USART_PM_ODD: odd parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* clear USART_CTL0 PM,PCEN Bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg ; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit(not available for UARTx(x=3,4,6,7)) - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits(not available for UARTx(x=3,4,6,7)) - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - /* configure USART stop bits */ - USART_CTL1(usart_periph) |= stblen; -} -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_TEN; - ctl |= txconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_REN; - ctl |= rxconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief data is transmitted/received with the LSB/MSB first - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] msbf: LSB/MSB - only one parameter can be selected which is shown as below: - \arg USART_MSBF_LSB: LSB first - \arg USART_MSBF_MSB: MSB first - \param[out] none - \retval none -*/ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL3(usart_periph); - ctl &= ~(USART_CTL3_MSBF); - ctl |= msbf; - /* configure data transmitted/received mode */ - USART_CTL3(usart_periph) = ctl; -} - -/*! - \brief configure USART inversion - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] invertpara: refer to enum USART_INVERT_CONFIG - only one parameter can be selected which is shown as below: - \arg USART_DINV_ENABLE: data bit level inversion - \arg USART_DINV_DISABLE: data bit level not inversion - \arg USART_TXPIN_ENABLE: TX pin level inversion - \arg USART_TXPIN_DISABLE: TX pin level not inversion - \arg USART_RXPIN_ENABLE: RX pin level inversion - \arg USART_RXPIN_DISABLE: RX pin level not inversion - \param[out] none - \retval none -*/ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) -{ - /* inverted or not the specified siginal */ - switch(invertpara){ - case USART_DINV_ENABLE: - USART_CTL3(usart_periph) |= USART_CTL3_DINV; - break; - case USART_TXPIN_ENABLE: - USART_CTL3(usart_periph) |= USART_CTL3_TINV; - break; - case USART_RXPIN_ENABLE: - USART_CTL3(usart_periph) |= USART_CTL3_RINV; - break; - case USART_DINV_DISABLE: - USART_CTL3(usart_periph) &= ~(USART_CTL3_DINV); - break; - case USART_TXPIN_DISABLE: - USART_CTL3(usart_periph) &= ~(USART_CTL3_TINV); - break; - case USART_RXPIN_DISABLE: - USART_CTL3(usart_periph) &= ~(USART_CTL3_RINV); - break; - default: - break; - } -} - -/*! - \brief configure the USART oversample mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] oversamp: oversample value - only one parameter can be selected which is shown as below: - \arg USART_OVSMOD_8: 8 bits - \arg USART_OVSMOD_16: 16 bits - \param[out] none - \retval none -*/ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) -{ - /* clear OVSMOD bit */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); - USART_CTL0(usart_periph) |= oversamp; -} - -/*! - \brief configure sample bit method - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] obsm: sample bit - only one parameter can be selected which is shown as below: - \arg USART_OSB_1bit: 1 bit - \arg USART_OSB_3bit: 3 bits - \param[out] none - \retval none -*/ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); - USART_CTL2(usart_periph) |= obsm; -} - -/*! - \brief enable receiver timeout of USART - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_enable(uint32_t usart_periph) -{ - USART_CTL3(usart_periph) |= USART_CTL3_RTEN; -} - -/*! - \brief disable receiver timeout of USART - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_disable(uint32_t usart_periph) -{ - USART_CTL3(usart_periph) &= ~(USART_CTL3_RTEN); -} - -/*! - \brief set the receiver timeout threshold of USART - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] rtimeout: 0-0x00FFFFFF - \param[out] none - \retval none -*/ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) -{ - USART_RT(usart_periph) &= ~(USART_RT_RT); - USART_RT(usart_periph) |= rtimeout; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_DATA(usart_periph) = ((uint16_t)USART_DATA_DATA & data); -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); -} - -/*! - \brief configure the address of the USART in wake up by address match mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] addr: address of USART/UART - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); -} - -/*! - \brief enable mute mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_RWU; -} - -/*! - \brief disable mute mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] wmehtod: two method be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mask - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmehtod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief configure lin break frame length - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[in] lblen: lin break frame length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits - \arg USART_LBLEN_11B: 11 bits - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); -} - -/*! - \brief send break frame - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_send_break(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; -} - -/*! - \brief enable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] clen: CK length - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame - \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2,5) - \param[in] guat: guard time value, 0-0xFF - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph,uint32_t guat) -{ - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat)< - -``` -## 驱动支æŒæƒ…况åŠè®¡åˆ’ - -| 驱动 | 支æŒæƒ…况 | 备注 | -| --------- | -------- | :------------------------: | -| UART | æ”¯æŒ | UART0~7 | -| GPIO | æœªæ”¯æŒ | | -| IIC | æœªæ”¯æŒ | | -| SPI | æ”¯æŒ | SPI0~5 | -| ETH | æ”¯æŒ | | -| LCD | æ”¯æŒ | 支æŒFrameBuffer模å¼LCD显示 | -| SDRAM | æ”¯æŒ | | -| SPI FLASH | æ”¯æŒ | | - -### IO在æ¿çº§æ”¯æŒåŒ…中的映射情况 - -| IOå· | æ¿çº§åŒ…中的定义 | -| ---- | -------------- | -| PD4 | LED1 | -| PD5 | LED2 | -| PG3 | LED3 | -| PA9 | KEY1 | -| PC13 | KEY2 | -| PB14 | KEY3 | - -## è”ç³»äººä¿¡æ¯ - -维护人：[tanek](https://github.com/liangyongxiang) diff --git a/bsp/gd32450z-eval/SConscript b/bsp/gd32450z-eval/SConscript deleted file mode 100644 index fe0ae941ae..0000000000 --- a/bsp/gd32450z-eval/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32450z-eval/SConstruct b/bsp/gd32450z-eval/SConstruct deleted file mode 100644 index 8190948a33..0000000000 --- a/bsp/gd32450z-eval/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread-gd32f4xx.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32450z-eval/applications/SConscript b/bsp/gd32450z-eval/applications/SConscript deleted file mode 100644 index 9bb9abae89..0000000000 --- a/bsp/gd32450z-eval/applications/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -from building import * -import os - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -list = os.listdir(cwd) -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - group = group + SConscript(os.path.join(item, 'SConscript')) - -Return('group') diff --git a/bsp/gd32450z-eval/applications/main.c b/bsp/gd32450z-eval/applications/main.c deleted file mode 100644 index 5c74d95c06..0000000000 --- a/bsp/gd32450z-eval/applications/main.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018-05-18 tanek first implementation - */ - -#include -#include - -int main(void) -{ - return 0; -} diff --git a/bsp/gd32450z-eval/applications/rtgui_demo.h b/bsp/gd32450z-eval/applications/rtgui_demo.h deleted file mode 100644 index d2d073b75d..0000000000 --- a/bsp/gd32450z-eval/applications/rtgui_demo.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-02 tanek first version - */ -#ifndef __APP_GUI_DEMO_H__ -#define __APP_GUI_DEMO_H__ - -extern int rt_gui_demo_init(void); - -#endif - diff --git a/bsp/gd32450z-eval/drivers/SConscript b/bsp/gd32450z-eval/drivers/SConscript deleted file mode 100644 index 71f774cc35..0000000000 --- a/bsp/gd32450z-eval/drivers/SConscript +++ /dev/null @@ -1,38 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drivers. -src = Split(""" -board.c -""") - -CPPPATH = [cwd] - -# add uart drivers. -if GetDepend('RT_USING_SERIAL'): - src += ['drv_usart.c'] - -# add sdram drivers. -if GetDepend('BSP_USING_SDRAM'): - src += ['drv_exmc_sdram.c'] - -# add Ethernet drivers. -if GetDepend('RT_USING_LWIP'): - src += ['drv_enet.c', 'synopsys_emac.c'] - -# add lcd drivers. -if GetDepend('PKG_USING_GUIENGINE'): - src += ['drv_lcd.c', 'gd32f450z_lcd_eval.c'] - -# add spi flash drivers. -if GetDepend('RT_USING_SFUD'): - src += ['drv_spi_flash.c', 'drv_spi.c'] -elif GetDepend('RT_USING_SPI'): - src += ['drv_spi.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32450z-eval/drivers/board.c b/bsp/gd32450z-eval/drivers/board.c deleted file mode 100644 index b69adfc41f..0000000000 --- a/bsp/gd32450z-eval/drivers/board.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - */ -#include -#include -#include - -#include -#include -#include - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while (1) - { - } - /* USER CODE END Error_Handler */ -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This function will initial GD32 board. - */ -void rt_hw_board_init() -{ - /* NVIC Configuration */ -#define NVIC_VTOR_MASK 0x3FFFFF80 -#ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); -#else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); -#endif - - SystemClock_Config(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef BSP_USING_SDRAM - rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END); -#else - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/gd32450z-eval/drivers/board.h b/bsp/gd32450z-eval/drivers/board.h deleted file mode 100644 index ea7dd83acd..0000000000 --- a/bsp/gd32450z-eval/drivers/board.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include - -#define EXT_SDRAM_BEGIN (0xC0000000U) /* the begining address of external SDRAM */ -#define EXT_SDRAM_END (EXT_SDRAM_BEGIN + (32U * 1024 * 1024)) /* the end address of external SDRAM */ - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#ifdef __ICCARM__ -// Use *.icf ram symbal, to avoid hardcode. -extern char __ICFEDIT_region_RAM_end__; -#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ -#else -#define GD32_SRAM_SIZE 128 -#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) -#endif - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif - -#define HEAP_END GD32_SRAM_END - -#endif - -//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32450z-eval/drivers/drv_enet.c b/bsp/gd32450z-eval/drivers/drv_enet.c deleted file mode 100644 index b37146e3c3..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_enet.c +++ /dev/null @@ -1,655 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-11-30 aozima the first version. - * 2011-12-10 aozima support dual ethernet. - * 2011-12-21 aozima cleanup code. - * 2012-07-13 aozima mask all GMAC MMC Interrupt. - * 2012-07-20 aozima fixed mask all GMAC MMC Interrupt,and read clear. - * 2012-07-20 aozima use memcpy replace byte copy. - */ - -#include -#include - -#include "lwipopts.h" -#include -#include -#include - -#include "gd32f4xx.h" -#include "synopsys_emac.h" - -#define ETHERNET_MAC0 ((struct rt_synopsys_eth *)(0x40020000U + 0x00008000U)) - -//#define EMAC_DEBUG -//#define EMAC_RX_DUMP -//#define EMAC_TX_DUMP - -#ifdef EMAC_DEBUG -#define EMAC_TRACE rt_kprintf -#else -#define EMAC_TRACE(...) -#endif - -#define EMAC_RXBUFNB 4 -#define EMAC_TXBUFNB 2 - -#define EMAC_PHY_AUTO 0 -#define EMAC_PHY_10MBIT 1 -#define EMAC_PHY_100MBIT 2 - -#define MAX_ADDR_LEN 6 -struct gd32_emac -{ - /* inherit from Ethernet device */ - struct eth_device parent; - - rt_uint8_t phy_mode; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - - struct rt_synopsys_eth * ETHERNET_MAC; - IRQn_Type ETHER_MAC_IRQ; - - EMAC_DMADESCTypeDef *DMATxDescToSet; - EMAC_DMADESCTypeDef *DMARxDescToGet; - -#pragma pack(4) - EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB]; -#pragma pack(4) - EMAC_DMADESCTypeDef DMATxDscrTab[EMAC_TXBUFNB]; -#pragma pack(4) - rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE]; -#pragma pack(4) - rt_uint8_t Tx_Buff[EMAC_TXBUFNB][EMAC_MAX_PACKET_SIZE]; - - struct rt_semaphore tx_buf_free; -}; - -static struct gd32_emac gd32_emac_device0; - -/** - * Initializes the DMA Tx descriptors in chain mode. - */ -static void EMAC_DMA_tx_desc_init(EMAC_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0; - EMAC_DMADESCTypeDef *DMATxDesc; - - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - DMATxDesc = DMATxDescTab + i; - /* Set Second Address Chained bit */ - DMATxDesc->Status = EMAC_DMATxDesc_TCH; - - /* Set Buffer1 address pointer */ - DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*EMAC_MAX_PACKET_SIZE]); - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } -} - -/** - * Initializes the DMA Rx descriptors in chain mode. - */ -static void EMAC_DMA_rx_desc_init(EMAC_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0; - EMAC_DMADESCTypeDef *DMARxDesc; - - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = EMAC_DMARxDesc_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = EMAC_DMARxDesc_RCH | (uint32_t)EMAC_MAX_PACKET_SIZE; - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*EMAC_MAX_PACKET_SIZE]); - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } -} - -static rt_err_t gd32_emac_init(rt_device_t dev) -{ - struct gd32_emac * gd32_emac_device; - struct rt_synopsys_eth * ETHERNET_MAC; - - gd32_emac_device = (struct gd32_emac *)dev; - ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC; - - /* Software reset */ - ETHERNET_MAC->BMR |= (1<<0); /* [bit0]SWR (Software Reset) */ - - /* Wait for software reset */ - while(ETHERNET_MAC->BMR & (1<<0)); - - /* Configure ETHERNET */ - EMAC_init(ETHERNET_MAC, SystemCoreClock); - - /* mask all GMAC MMC Interrupt.*/ - ETHERNET_MAC->mmc_cntl = (1<<3) | (1<<0); /* MMC Counter Freeze and reset. */ - ETHERNET_MAC->mmc_intr_mask_rx = 0xFFFFFFFF; - ETHERNET_MAC->mmc_intr_mask_tx = 0xFFFFFFFF; - ETHERNET_MAC->mmc_ipc_intr_mask_rx = 0xFFFFFFFF; - - /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ - EMAC_INT_config(ETHERNET_MAC, EMAC_DMA_INT_NIS | EMAC_DMA_INT_R | EMAC_DMA_INT_T , ENABLE); - - /* Initialize Tx Descriptors list: Chain Mode */ - EMAC_DMA_tx_desc_init(gd32_emac_device->DMATxDscrTab, &gd32_emac_device->Tx_Buff[0][0], EMAC_TXBUFNB); - gd32_emac_device->DMATxDescToSet = gd32_emac_device->DMATxDscrTab; - /* Set Transmit Descriptor List Address Register */ - ETHERNET_MAC->TDLAR = (uint32_t) gd32_emac_device->DMATxDescToSet; - - /* Initialize Rx Descriptors list: Chain Mode */ - EMAC_DMA_rx_desc_init(gd32_emac_device->DMARxDscrTab, &gd32_emac_device->Rx_Buff[0][0], EMAC_RXBUFNB); - gd32_emac_device->DMARxDescToGet = gd32_emac_device->DMARxDscrTab; - /* Set Receive Descriptor List Address Register */ - ETHERNET_MAC->RDLAR = (uint32_t) gd32_emac_device->DMARxDescToGet; - - /* MAC address configuration */ - EMAC_MAC_Addr_config(ETHERNET_MAC, EMAC_MAC_Address0, (uint8_t*)&gd32_emac_device->dev_addr[0]); - - NVIC_EnableIRQ( gd32_emac_device->ETHER_MAC_IRQ ); - - /* Enable MAC and DMA transmission and reception */ - EMAC_start(ETHERNET_MAC); - - return RT_EOK; -} - -static rt_err_t gd32_emac_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t gd32_emac_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_ssize_t gd32_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - return -RT_ENOSYS; -} - -static rt_ssize_t gd32_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - return -RT_ENOSYS; -} - -static rt_err_t gd32_emac_control(rt_device_t dev, int cmd, void *args) -{ - struct gd32_emac * gd32_emac_device = (struct gd32_emac *)dev; - - switch (cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if (args) memcpy(args, &gd32_emac_device->dev_addr[0], MAX_ADDR_LEN); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -static void EMAC_IRQHandler(struct gd32_emac * gd32_emac_device) -{ - rt_uint32_t status, ier; - struct rt_synopsys_eth * ETHERNET_MAC; - - ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC; - - /* get DMA IT status */ - status = ETHERNET_MAC->SR; - ier = ETHERNET_MAC->IER; - - /* GMAC MMC Interrupt. */ - if(status & EMAC_DMA_INT_GMI) - { - volatile rt_uint32_t dummy; - volatile rt_uint32_t * reg; - - EMAC_TRACE("EMAC_DMA_INT_GMI\r\n"); - - /* read clear all MMC interrupt. */ - reg = ÐERNET_MAC->mmc_cntl; - while((uint32_t)reg < (uint32_t)ÐERNET_MAC->rxicmp_err_octets) - { - dummy = *reg++; - } - } - - /* Normal interrupt summary. */ - if(status & EMAC_DMA_INT_NIS) - { - rt_uint32_t nis_clear = EMAC_DMA_INT_NIS; - - /* [0]:Transmit Interrupt. */ - if((status & ier) & EMAC_DMA_INT_T) /* packet transmission */ - { - rt_sem_release(&gd32_emac_device->tx_buf_free); - - nis_clear |= EMAC_DMA_INT_T; - } - - /* [2]:Transmit Buffer Unavailable. */ - - /* [6]:Receive Interrupt. */ - if((status & ier) & EMAC_DMA_INT_R) /* packet reception */ - { - /* a frame has been received */ - eth_device_ready(&(gd32_emac_device->parent)); - - nis_clear |= EMAC_DMA_INT_R; - } - - /* [14]:Early Receive Interrupt. */ - - EMAC_clear_pending(ETHERNET_MAC, nis_clear); - } - - /* Abnormal interrupt summary. */ - if( status & EMAC_DMA_INT_AIS) - { - rt_uint32_t ais_clear = EMAC_DMA_INT_AIS; - - /* [1]:Transmit Process Stopped. */ - /* [3]:Transmit Jabber Timeout. */ - /* [4]: Receive FIFO Overflow. */ - /* [5]: Transmit Underflow. */ - /* [7]: Receive Buffer Unavailable. */ - /* [8]: Receive Process Stopped. */ - /* [9]: Receive Watchdog Timeout. */ - /* [10]: Early Transmit Interrupt. */ - /* [13]: Fatal Bus Error. */ - - EMAC_clear_pending(ETHERNET_MAC, ais_clear); - } -} - -void ENET_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - EMAC_IRQHandler(&gd32_emac_device0); - - /* leave interrupt */ - rt_interrupt_leave(); -} - - -/* EtherNet Device Interface */ -rt_err_t gd32_emac_tx( rt_device_t dev, struct pbuf* p) -{ - struct pbuf* q; - char * to; - struct gd32_emac * gd32_emac_device; - struct rt_synopsys_eth * ETHERNET_MAC; - - gd32_emac_device = (struct gd32_emac *)dev; - ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC; - - /* get free tx buffer */ - { - rt_err_t result; - result = rt_sem_take(&gd32_emac_device->tx_buf_free, RT_TICK_PER_SECOND/10); - if (result != RT_EOK) return -RT_ERROR; - } - - to = (char *)gd32_emac_device->DMATxDescToSet->Buffer1Addr; - - for (q = p; q != NULL; q = q->next) - { - /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ - memcpy(to, q->payload, q->len); - to += q->len; - } - -#ifdef EMAC_TX_DUMP - { - rt_uint32_t i; - rt_uint8_t *ptr = (rt_uint8_t*)(gd32_emac_device->DMATxDescToSet->Buffer1Addr); - - EMAC_TRACE("\r\n%c%c tx_dump:", gd32_emac_device->parent.netif->name[0], gd32_emac_device->parent.netif->name[1]); - for(i=0; itot_len; i++) - { - if( (i%8) == 0 ) - { - EMAC_TRACE(" "); - } - if( (i%16) == 0 ) - { - EMAC_TRACE("\r\n"); - } - EMAC_TRACE("%02x ",*ptr); - ptr++; - } - EMAC_TRACE("\r\ndump done!\r\n"); - } -#endif - - /* Setting the Frame Length: bits[12:0] */ - gd32_emac_device->DMATxDescToSet->ControlBufferSize = (p->tot_len & EMAC_DMATxDesc_TBS1); - /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ - gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_LS | EMAC_DMATxDesc_FS; - /* Enable TX Completion Interrupt */ - gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_IC; -#ifdef CHECKSUM_BY_HARDWARE - gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_ChecksumTCPUDPICMPFull; - /* clean ICMP checksum */ - { - struct eth_hdr *ethhdr = (struct eth_hdr *)(gd32_emac_device->DMATxDescToSet->Buffer1Addr); - /* is IP ? */ - if( ethhdr->type == htons(ETHTYPE_IP) ) - { - struct ip_hdr *iphdr = (struct ip_hdr *)(gd32_emac_device->DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR); - /* is ICMP ? */ - if( IPH_PROTO(iphdr) == IP_PROTO_ICMP ) - { - struct icmp_echo_hdr *iecho = (struct icmp_echo_hdr *)(gd32_emac_device->DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR + sizeof(struct ip_hdr) ); - iecho->chksum = 0; - } - } - } -#endif - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - gd32_emac_device->DMATxDescToSet->Status |= EMAC_DMATxDesc_OWN; - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if ((ETHERNET_MAC->SR & EMAC_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - ETHERNET_MAC->SR = EMAC_DMASR_TBUS; - /* Transmit Poll Demand to resume DMA transmission*/ - ETHERNET_MAC->TPDR = 0; - } - - /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ - /* Chained Mode */ - /* Selects the next DMA Tx descriptor list for next buffer to send */ - gd32_emac_device->DMATxDescToSet = (EMAC_DMADESCTypeDef*) (gd32_emac_device->DMATxDescToSet->Buffer2NextDescAddr); - - /* Return SUCCESS */ - return RT_EOK; -} - -/* reception a Ethernet packet. */ -struct pbuf * gd32_emac_rx(rt_device_t dev) -{ - struct pbuf* p; - rt_uint32_t framelength = 0; - struct gd32_emac * gd32_emac_device; - struct rt_synopsys_eth * ETHERNET_MAC; - - gd32_emac_device = (struct gd32_emac *)dev; - ETHERNET_MAC = gd32_emac_device->ETHERNET_MAC; - - /* init p pointer */ - p = RT_NULL; - - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if(((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_OWN) != (uint32_t)RESET)) - { - return p; - } - - if (((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_ES) == (uint32_t)RESET) && - ((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_LS) != (uint32_t)RESET) && - ((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_FS) != (uint32_t)RESET)) - { - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((gd32_emac_device->DMARxDescToGet->Status & EMAC_DMARxDesc_FL) - >> EMAC_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - - /* allocate buffer */ - p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM); - if (p != RT_NULL) - { - const char * from; - struct pbuf* q; - - from = (const char *)gd32_emac_device->DMARxDescToGet->Buffer1Addr; - - for (q = p; q != RT_NULL; q= q->next) - { - /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ - memcpy(q->payload, from, q->len); - from += q->len; - } -#ifdef EMAC_RX_DUMP - { - rt_uint32_t i; - rt_uint8_t *ptr = (rt_uint8_t*)(gd32_emac_device->DMARxDescToGet->Buffer1Addr); - - EMAC_TRACE("\r\n%c%c rx_dump:", gd32_emac_device->parent.netif->name[0], gd32_emac_device->parent.netif->name[1]); - for(i=0; itot_len; i++) - { - if( (i%8) == 0 ) - { - EMAC_TRACE(" "); - } - if( (i%16) == 0 ) - { - EMAC_TRACE("\r\n"); - } - EMAC_TRACE("%02x ",*ptr); - ptr++; - } - EMAC_TRACE("\r\ndump done!\r\n"); - } -#endif - } - } - - /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - gd32_emac_device->DMARxDescToGet->Status = EMAC_DMARxDesc_OWN; - - /* When Rx Buffer unavailable flag is set: clear it and resume reception */ - if ((ETHERNET_MAC->SR & EMAC_DMASR_RBUS) != (uint32_t)RESET) - { - /* Clear RBUS ETHERNET DMA flag */ - ETHERNET_MAC->SR = EMAC_DMASR_RBUS; - /* Resume DMA reception */ - ETHERNET_MAC->RPDR = 0; - } - - /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ - /* Chained Mode */ - if((gd32_emac_device->DMARxDescToGet->ControlBufferSize & EMAC_DMARxDesc_RCH) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - gd32_emac_device->DMARxDescToGet = (EMAC_DMADESCTypeDef*) (gd32_emac_device->DMARxDescToGet->Buffer2NextDescAddr); - } - else /* Ring Mode */ - { - if((gd32_emac_device->DMARxDescToGet->ControlBufferSize & EMAC_DMARxDesc_RER) != (uint32_t)RESET) - { - /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ - gd32_emac_device->DMARxDescToGet = (EMAC_DMADESCTypeDef*) (ETHERNET_MAC->RDLAR); - } - else - { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - gd32_emac_device->DMARxDescToGet = (EMAC_DMADESCTypeDef*) ((uint32_t)gd32_emac_device->DMARxDescToGet + 0x10 + ((ETHERNET_MAC->BMR & EMAC_DMABMR_DSL) >> 2)); - } - } - - return p; -} - -/*! - \brief configures the nested vectored interrupt controller - \param[in] none - \param[out] none - \retval none -*/ -static void nvic_configuration(void) -{ - nvic_vector_table_set(NVIC_VECTTAB_FLASH, 0x0); - nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - nvic_irq_enable(ENET_IRQn, 0, 0); -} - -/*! - \brief configures the different GPIO ports - \param[in] none - \param[out] none - \retval none -*/ -static void enet_gpio_config(void) -{ - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_GPIOB); - rcu_periph_clock_enable(RCU_GPIOC); - rcu_periph_clock_enable(RCU_GPIOD); - rcu_periph_clock_enable(RCU_GPIOG); - rcu_periph_clock_enable(RCU_GPIOH); - rcu_periph_clock_enable(RCU_GPIOI); - - gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_8); - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_8); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_8); - - /* enable SYSCFG clock */ - rcu_periph_clock_enable(RCU_SYSCFG); - - /* choose DIV2 to get 50MHz from 200MHz on CKOUT0 pin (PA8) to clock the PHY */ - rcu_ckout0_config(RCU_CKOUT0SRC_PLLP, RCU_CKOUT0_DIV4); - syscfg_enet_phy_interface_config(SYSCFG_ENET_PHY_RMII); - - /* PA1: ETH_RMII_REF_CLK */ - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); - - /* PA2: ETH_MDIO */ - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_2); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_2); - - /* PA7: ETH_RMII_CRS_DV */ - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_7); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_7); - - gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_1); - gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_2); - gpio_af_set(GPIOA, GPIO_AF_11, GPIO_PIN_7); - - /* PB11: ETH_RMII_TX_EN */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_11); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_11); - - /* PB12: ETH_RMII_TXD0 */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_12); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_12); - - /* PB13: ETH_RMII_TXD1 */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_13); - - gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_11); - gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_12); - gpio_af_set(GPIOB, GPIO_AF_11, GPIO_PIN_13); - - /* PC1: ETH_MDC */ - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_1); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_1); - - /* PC4: ETH_RMII_RXD0 */ - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_4); - - /* PC5: ETH_RMII_RXD1 */ - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ,GPIO_PIN_5); - - gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_1); - gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_4); - gpio_af_set(GPIOC, GPIO_AF_11, GPIO_PIN_5); -} - - -int rt_hw_gd32_eth_init(void) -{ - rt_kprintf("rt_gd32_eth_init...\n"); - - /* enable ethernet clock */ - rcu_periph_clock_enable(RCU_ENET); - rcu_periph_clock_enable(RCU_ENETTX); - rcu_periph_clock_enable(RCU_ENETRX); - - nvic_configuration(); - - /* configure the GPIO ports for ethernet pins */ - enet_gpio_config(); - - /* set autonegotiation mode */ - gd32_emac_device0.phy_mode = EMAC_PHY_AUTO; - gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0; - gd32_emac_device0.ETHER_MAC_IRQ = ENET_IRQn; - - // OUI 00-00-0E FUJITSU LIMITED - gd32_emac_device0.dev_addr[0] = 0x00; - gd32_emac_device0.dev_addr[1] = 0x00; - gd32_emac_device0.dev_addr[2] = 0x0E; - /* set mac address: (only for test) */ - gd32_emac_device0.dev_addr[3] = 0x12; - gd32_emac_device0.dev_addr[4] = 0x34; - gd32_emac_device0.dev_addr[5] = 0x56; - - gd32_emac_device0.parent.parent.init = gd32_emac_init; - gd32_emac_device0.parent.parent.open = gd32_emac_open; - gd32_emac_device0.parent.parent.close = gd32_emac_close; - gd32_emac_device0.parent.parent.read = gd32_emac_read; - gd32_emac_device0.parent.parent.write = gd32_emac_write; - gd32_emac_device0.parent.parent.control = gd32_emac_control; - gd32_emac_device0.parent.parent.user_data = RT_NULL; - - gd32_emac_device0.parent.eth_rx = gd32_emac_rx; - gd32_emac_device0.parent.eth_tx = gd32_emac_tx; - - /* init tx buffer free semaphore */ - rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO); - eth_device_init(&(gd32_emac_device0.parent), "e0"); - - /* change device link status */ - eth_device_linkchange(&(gd32_emac_device0.parent), RT_TRUE); - - return 0; -} -INIT_DEVICE_EXPORT(rt_hw_gd32_eth_init); diff --git a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c b/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c deleted file mode 100644 index 3fe8866dfb..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.c +++ /dev/null @@ -1,315 +0,0 @@ -/*! - \file main.c - \brief exmc sdram(MICRON 48LC16M16A2) driver -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-10-19, V1.0.0, demo for GD32F4xx -*/ - -#include "gd32f4xx.h" -#include "drv_exmc_sdram.h" -#include - -/* define mode register content */ -/* burst length */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0003) - -/* burst type */ -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) - -/* CAS latency */ -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) - -/* write mode */ -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) - -#define SDRAM_TIMEOUT ((uint32_t)0x0000FFFF) - -static void delay_1ms(volatile uint32_t count) -{ - count *= 1000; - while (count--) - { - count = count; - } -} - -/*! - \brief sdram peripheral initialize - \param[in] sdram_device: specifie the SDRAM device - \param[out] none - \retval none -*/ -void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device) -{ - exmc_sdram_parameter_struct sdram_init_struct; - exmc_sdram_timing_parameter_struct sdram_timing_init_struct; - exmc_sdram_command_parameter_struct sdram_command_init_struct; - - uint32_t command_content = 0, bank_select; - uint32_t timeout = SDRAM_TIMEOUT; - - /* enable EXMC clock*/ - rcu_periph_clock_enable(RCU_EXMC); - rcu_periph_clock_enable(RCU_GPIOB); - rcu_periph_clock_enable(RCU_GPIOC); - rcu_periph_clock_enable(RCU_GPIOD); - rcu_periph_clock_enable(RCU_GPIOE); - rcu_periph_clock_enable(RCU_GPIOF); - rcu_periph_clock_enable(RCU_GPIOG); - rcu_periph_clock_enable(RCU_GPIOH); - - /* common GPIO configuration */ - /* SDNWE(PC0),SDNE0(PC2),SDCKE0(PC3) pin configuration */ - gpio_af_set(GPIOC, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3); - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_2 | GPIO_PIN_3); - - /* D2(PD0),D3(PD1),D13(PD8),D14(PD9),D15(PD10),D0(PD14),D1(PD15) pin configuration */ - gpio_af_set(GPIOD, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | - GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); - gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | - GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); - gpio_output_options_set(GPIOD, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | - GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15); - - /* NBL0(PE0),NBL1(PE1),D4(PE7),D5(PE8),D6(PE9),D7(PE10),D8(PE11),D9(PE12),D10(PE13),D11(PE14),D12(PE15) pin configuration */ - gpio_af_set(GPIOE, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | - GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | - GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - gpio_mode_set(GPIOE, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | - GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | - GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - gpio_output_options_set(GPIOE, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | GPIO_PIN_8 | - GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | - GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - - /* A0(PF0),A1(PF1),A2(PF2),A3(PF3),A4(PF4),A5(PF5),NRAS(PF11),A6(PF12),A7(PF13),A8(PF14),A9(PF15) pin configuration */ - gpio_af_set(GPIOF, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | - GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | - GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - gpio_mode_set(GPIOF, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | - GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | - GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - gpio_output_options_set(GPIOF, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | - GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | - GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15); - - /* A10(PG0),A11(PG1),A12(PG2),A14(PG4),A15(PG5),SDCLK(PG8),NCAS(PG15) pin configuration */ - gpio_af_set(GPIOG, GPIO_AF_12, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | - GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15); - gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_PULLUP, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | - GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15); - gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_4 | - GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15); - - /* specify which SDRAM to read and write */ - if(EXMC_SDRAM_DEVICE0 == sdram_device){ - bank_select = EXMC_SDRAM_DEVICE0_SELECT; - }else{ - bank_select = EXMC_SDRAM_DEVICE1_SELECT; - } - - /* EXMC SDRAM device initialization sequence --------------------------------*/ - /* Step 1 : configure SDRAM timing registers --------------------------------*/ - /* LMRD: 2 clock cycles */ - sdram_timing_init_struct.load_mode_register_delay = 2; - /* XSRD: min = 67ns */ - sdram_timing_init_struct.exit_selfrefresh_delay = 7; - /* RASD: min=42ns , max=120k (ns) */ - sdram_timing_init_struct.row_address_select_delay = 5; - /* ARFD: min=60ns */ - sdram_timing_init_struct.auto_refresh_delay = 6; - /* WRD: min=1 Clock cycles +6ns */ - sdram_timing_init_struct.write_recovery_delay = 2; - /* RPD: min=18ns */ - sdram_timing_init_struct.row_precharge_delay = 2; - /* RCD: min=18ns */ - sdram_timing_init_struct.row_to_column_delay = 2; - - /* step 2 : configure SDRAM control registers ---------------------------------*/ - sdram_init_struct.sdram_device = sdram_device; - sdram_init_struct.column_address_width = EXMC_SDRAM_COW_ADDRESS_9; - sdram_init_struct.row_address_width = EXMC_SDRAM_ROW_ADDRESS_13; - sdram_init_struct.data_width = EXMC_SDRAM_DATABUS_WIDTH_16B; - sdram_init_struct.internal_bank_number = EXMC_SDRAM_4_INTER_BANK; - sdram_init_struct.cas_latency = EXMC_CAS_LATENCY_3_SDCLK; - sdram_init_struct.write_protection = DISABLE; - sdram_init_struct.sdclock_config = EXMC_SDCLK_PERIODS_2_HCLK; - sdram_init_struct.brust_read_switch = ENABLE; - sdram_init_struct.pipeline_read_delay = EXMC_PIPELINE_DELAY_1_HCLK; - sdram_init_struct.timing = &sdram_timing_init_struct; - /* EXMC SDRAM bank initialization */ - exmc_sdram_init(&sdram_init_struct); - - /* step 3 : configure CKE high command---------------------------------------*/ - sdram_command_init_struct.command = EXMC_SDRAM_CLOCK_ENABLE; - sdram_command_init_struct.bank_select = bank_select; - sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; - sdram_command_init_struct.mode_register_content = 0; - /* wait until the SDRAM controller is ready */ - while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ - timeout--; - } - /* send the command */ - exmc_sdram_command_config(&sdram_command_init_struct); - - /* step 4 : insert 10ms delay----------------------------------------------*/ - delay_1ms(10); - - /* step 5 : configure precharge all command----------------------------------*/ - sdram_command_init_struct.command = EXMC_SDRAM_PRECHARGE_ALL; - sdram_command_init_struct.bank_select = bank_select; - sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; - sdram_command_init_struct.mode_register_content = 0; - /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ - timeout--; - } - /* send the command */ - exmc_sdram_command_config(&sdram_command_init_struct); - - /* step 6 : configure Auto-Refresh command-----------------------------------*/ - sdram_command_init_struct.command = EXMC_SDRAM_AUTO_REFRESH; - sdram_command_init_struct.bank_select = bank_select; - sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_8_SDCLK; - sdram_command_init_struct.mode_register_content = 0; - /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ - timeout--; - } - /* send the command */ - exmc_sdram_command_config(&sdram_command_init_struct); - - /* step 7 : configure load mode register command-----------------------------*/ - /* program mode register */ - command_content = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - sdram_command_init_struct.command = EXMC_SDRAM_LOAD_MODE_REGISTER; - sdram_command_init_struct.bank_select = bank_select; - sdram_command_init_struct.auto_refresh_number = EXMC_SDRAM_AUTO_REFLESH_1_SDCLK; - sdram_command_init_struct.mode_register_content = command_content; - - /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ - timeout--; - } - /* send the command */ - exmc_sdram_command_config(&sdram_command_init_struct); - - /* step 8 : set the auto-refresh rate counter--------------------------------*/ - /* 64ms, 8192-cycle refresh, 64ms/8192=7.81us */ - /* SDCLK_Freq = SYS_Freq/2 */ - /* (7.81 us * SDCLK_Freq) - 20 */ - exmc_sdram_refresh_count_set(761); - - /* wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((exmc_flag_get(sdram_device, EXMC_SDRAM_FLAG_NREADY) != RESET) && (timeout > 0)){ - timeout--; - } -} - -/*! - \brief fill the buffer with specified value - \param[in] pbuffer: pointer on the buffer to fill - \param[in] buffersize: size of the buffer to fill - \param[in] value: value to fill on the buffer - \param[out] none - \retval none -*/ -void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t offset) -{ - uint16_t index = 0; - - /* put in global buffer same values */ - for (index = 0; index < buffer_lengh; index++ ){ - pbuffer[index] = index + offset; - } -} - -/*! - \brief write a byte buffer(data is 8 bits) to the EXMC SDRAM memory - \param[in] sdram_device: specify which a SDRAM memory block is written - \param[in] pbuffer: pointer to buffer - \param[in] writeaddr: SDRAM memory internal address from which the data will be written - \param[in] numbytetowrite: number of bytes to write - \param[out] none - \retval none -*/ -void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writeaddr, uint32_t numbytetowrite) -{ - uint32_t temp_addr; - - /* Select the base address according to EXMC_Bank */ - if(sdram_device == EXMC_SDRAM_DEVICE0){ - temp_addr = SDRAM_DEVICE0_ADDR; - }else{ - temp_addr = SDRAM_DEVICE1_ADDR; - } - - /* While there is data to write */ - for(; numbytetowrite != 0; numbytetowrite--) { - /* Transfer data to the memory */ - *(uint8_t *) (temp_addr + writeaddr) = *pbuffer++; - - /* Increment the address*/ - writeaddr += 1; - } -} - -/*! - \brief read a block of 8-bit data from the EXMC SDRAM memory - \param[in] sdram_device: specify which a SDRAM memory block is written - \param[in] pbuffer: pointer to buffer - \param[in] readaddr: SDRAM memory internal address to read from - \param[in] numbytetoread: number of bytes to read - \param[out] none - \retval none -*/ -void sdram_readbuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t readaddr, uint32_t numbytetoread) -{ - uint32_t temp_addr; - - /* select the base address according to EXMC_Bank */ - if(sdram_device == EXMC_SDRAM_DEVICE0){ - temp_addr = SDRAM_DEVICE0_ADDR; - }else{ - temp_addr = SDRAM_DEVICE1_ADDR; - } - - /* while there is data to read */ - for(; numbytetoread != 0; numbytetoread--){ - /* read a byte from the memory */ - *pbuffer++ = *(uint8_t*) (temp_addr + readaddr); - - /* increment the address */ - readaddr += 1; - } -} - -int rt_hw_sdram_init(void) -{ - exmc_synchronous_dynamic_ram_init(EXMC_SDRAM_DEVICE0); - return 0; -} -INIT_BOARD_EXPORT(rt_hw_sdram_init); - diff --git a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.h b/bsp/gd32450z-eval/drivers/drv_exmc_sdram.h deleted file mode 100644 index b859d36226..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_exmc_sdram.h +++ /dev/null @@ -1,32 +0,0 @@ -/*! - \file exmc_nandflash.h - \brief the header file of sdram(MICRON 48LC16M16A2) driver -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-10-19, V1.0.0, demo for GD32F4xx -*/ - -#ifndef EXMC_SDRAM_H -#define EXMC_SDRAM_H - -#include "gd32f4xx.h" - -/* sdram peripheral initialize */ -void exmc_synchronous_dynamic_ram_init(uint32_t sdram_device); - -/* fill the buffer with specified value */ -void fill_buffer(uint8_t *pbuffer, uint16_t buffer_lengh, uint16_t offset); - -/* write a byte buffer(data is 8 bits) to the EXMC SDRAM memory */ -void sdram_writebuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t writeaddr, uint32_t numbytetowrite); - -/* read a block of 8-bit data from the EXMC SDRAM memory */ -void sdram_readbuffer_8(uint32_t sdram_device,uint8_t* pbuffer, uint32_t readaddr, uint32_t numbytetoread); - -#define SDRAM_DEVICE0_ADDR ((uint32_t)0xC0000000) -#define SDRAM_DEVICE1_ADDR ((uint32_t)0xD0000000) - -#endif /* EXMC_SDRAM_H */ diff --git a/bsp/gd32450z-eval/drivers/drv_lcd.c b/bsp/gd32450z-eval/drivers/drv_lcd.c deleted file mode 100644 index 3cbae2ac84..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_lcd.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-08-23 Tanek the first version - */ - -#include "gd32f450z_lcd_eval.h" -#include -#include -#include -#include - -#ifdef PKG_USING_GUIENGINE - - -#define RT_HW_LCD_WIDTH ((uint16_t)320) /* LCD PIXEL WIDTH */ -#define RT_HW_LCD_HEIGHT ((uint16_t)480) /* LCD PIXEL HEIGHT */ - -#define LCD_480_320_HSYNC ((uint32_t)10) /* Horizontal synchronization */ -#define LCD_480_320_HBP ((uint32_t)20) /* Horizontal back porch */ -#define LCD_480_320_HFP ((uint32_t)40) /* Horizontal front porch */ -#define LCD_480_320_VSYNC ((uint32_t)2) /* Vertical synchronization */ -#define LCD_480_320_VBP ((uint32_t)1) /* Vertical back porch */ -#define LCD_480_320_VFP ((uint32_t)4) /* Vertical front porch */ - -#define LCD_BITS_PER_PIXEL 16 - - -static rt_uint16_t *lcd_framebuffer = RT_NULL; -static rt_uint16_t *_rt_framebuffer = RT_NULL; - -static struct rt_device_graphic_info _lcd_info; -static struct rt_device lcd; - -/*! - \brief configure TLI GPIO - \param[in] none - \param[out] none - \retval none -*/ -static void tli_gpio_config(void) -{ - /* enable the periphral clock */ - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_GPIOB); - rcu_periph_clock_enable(RCU_GPIOC); - rcu_periph_clock_enable(RCU_GPIOD); - rcu_periph_clock_enable(RCU_GPIOF); - rcu_periph_clock_enable(RCU_GPIOG); - - /* configure HSYNC(PC6), VSYNC(PA4), PCLK(PG7), DE(PF10) */ - /* configure LCD_R7(PG6), LCD_R6(PA8), LCD_R5(PA12), LCD_R4(PA11), LCD_R3(PB0), - LCD_G7(PD3), LCD_G6(PC7), LCD_G5(PB11), LCD_G4(PB10), LCD_G3(PG10), LCD_G2(PA6), - LCD_B7(PB9), LCD_B6(PB8), LCD_B5(PA3), LCD_B4(PG12), LCD_B3(PG11) */ - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_3); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_4); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_6); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_12); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOA,GPIO_AF_14,GPIO_PIN_8); - - gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0); - gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10); - //gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8); - gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9); - - gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_6); - gpio_af_set(GPIOC,GPIO_AF_14,GPIO_PIN_7); - - gpio_af_set(GPIOD,GPIO_AF_14,GPIO_PIN_3); - - gpio_af_set(GPIOF,GPIO_AF_14,GPIO_PIN_10); - - gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_6); - gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_7); - gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_10); - gpio_af_set(GPIOG,GPIO_AF_14,GPIO_PIN_11); - gpio_af_set(GPIOG,GPIO_AF_9,GPIO_PIN_12); - - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_6 - |GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_4|GPIO_PIN_3 - |GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12); - - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - /*|GPIO_PIN_11*/); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 - /*|GPIO_PIN_11*/); - - gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_6|GPIO_PIN_7); - gpio_output_options_set(GPIOC, GPIO_OTYPE_PP,GPIO_OSPEED_50MHZ, GPIO_PIN_6|GPIO_PIN_7); - - gpio_mode_set(GPIOD, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_3); - gpio_output_options_set(GPIOD, GPIO_OTYPE_PP,GPIO_OSPEED_50MHZ, GPIO_PIN_3); - - gpio_mode_set(GPIOF, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10); - gpio_output_options_set(GPIOF, GPIO_OTYPE_PP,GPIO_OSPEED_50MHZ, GPIO_PIN_10); - - gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12); - gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11 - |GPIO_PIN_12); -} - -/*! - \brief LCD Configuration - \param[in] none - \param[out] none - \retval none -*/ -static void lcd_config(void) -{ - /* configure the LCD control line */ - lcd_ctrl_line_config(); - lcd_disable(); - lcd_enable(); - - /* configure the GPIO of TLI */ - tli_gpio_config(); - /* configure the LCD_SPI */ - lcd_spi_config(); - - /* power on the LCD */ - //lcd_power_on(); - lcd_power_on3(); //New Version 3.5" TFT RGB Hardware needs use this initilize funtion ---By xufei 2016.10.21 -} - -/*! - \brief configure TLI peripheral - \param[in] none - \param[out] none - \retval none -*/ -static void tli_config(void) -{ - tli_parameter_struct tli_init_struct; - tli_layer_parameter_struct tli_layer_init_struct; - - rcu_periph_clock_enable(RCU_TLI); - - /* configure the PLLSAI clock to generate lcd clock */ - if(ERROR == rcu_pllsai_config(192, 2, 3, 3)){ - while(1); - } - rcu_tli_clock_div_config(RCU_PLLSAIR_DIV8); - rcu_osci_on(RCU_PLLSAI_CK); - if(ERROR == rcu_osci_stab_wait(RCU_PLLSAI_CK)){ - while(1); - } - - /* TLI initialization */ - tli_init_struct.signalpolarity_hs = TLI_HSYN_ACTLIVE_LOW; - tli_init_struct.signalpolarity_vs = TLI_VSYN_ACTLIVE_LOW; - tli_init_struct.signalpolarity_de = TLI_DE_ACTLIVE_LOW; - tli_init_struct.signalpolarity_pixelck = TLI_PIXEL_CLOCK_TLI; - - /* LCD display timing configuration */ - tli_init_struct.synpsz_hpsz = LCD_480_320_HSYNC; - tli_init_struct.synpsz_vpsz = LCD_480_320_VSYNC; - tli_init_struct.backpsz_hbpsz = LCD_480_320_HSYNC + LCD_480_320_HBP; - tli_init_struct.backpsz_vbpsz = LCD_480_320_VSYNC + LCD_480_320_VBP; - tli_init_struct.activesz_hasz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP; - tli_init_struct.activesz_vasz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP; - tli_init_struct.totalsz_htsz = RT_HW_LCD_WIDTH + LCD_480_320_HSYNC + LCD_480_320_HBP + LCD_480_320_HFP; - tli_init_struct.totalsz_vtsz = RT_HW_LCD_HEIGHT + LCD_480_320_VSYNC + LCD_480_320_VBP + LCD_480_320_VFP; - - /* LCD background color configure*/ - tli_init_struct.backcolor_red = 0x00; - tli_init_struct.backcolor_green = 0x00; - tli_init_struct.backcolor_blue = 0x00; - tli_init(&tli_init_struct); - - lcd_framebuffer = rt_malloc(sizeof(rt_uint16_t) * RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH); - RT_ASSERT(lcd_framebuffer != NULL); - rt_memset(lcd_framebuffer, 0, sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT); - - /* TLI layer0 configuration */ - tli_layer_init_struct.layer_window_leftpos = tli_init_struct.backpsz_hbpsz + 1; - tli_layer_init_struct.layer_window_rightpos = tli_init_struct.backpsz_hbpsz + RT_HW_LCD_WIDTH; - tli_layer_init_struct.layer_window_toppos = tli_init_struct.backpsz_vbpsz + 1; - tli_layer_init_struct.layer_window_bottompos = tli_init_struct.backpsz_vbpsz + RT_HW_LCD_HEIGHT; - - tli_layer_init_struct.layer_ppf = LAYER_PPF_RGB565; - tli_layer_init_struct.layer_sa = 0xFF; - tli_layer_init_struct.layer_default_blue = 0x00; - tli_layer_init_struct.layer_default_green = 0x00; - tli_layer_init_struct.layer_default_red = 0x00; - tli_layer_init_struct.layer_default_alpha = 0x00; - tli_layer_init_struct.layer_acf1 = LAYER_ACF1_PASA; - tli_layer_init_struct.layer_acf2 = LAYER_ACF2_PASA; - tli_layer_init_struct.layer_frame_bufaddr = (uint32_t)lcd_framebuffer; - tli_layer_init_struct.layer_frame_line_length = ((RT_HW_LCD_WIDTH * 2) + 3); - tli_layer_init_struct.layer_frame_buf_stride_offset = (RT_HW_LCD_WIDTH * 2); - tli_layer_init_struct.layer_frame_total_line_number = RT_HW_LCD_HEIGHT; - - tli_layer_init(LAYER0, &tli_layer_init_struct); -} - -static rt_err_t rt_lcd_control(rt_device_t dev, int cmd, void *args) -{ - switch (cmd) - { - case RTGRAPHIC_CTRL_RECT_UPDATE: - { - memcpy((void *)lcd_framebuffer, _rt_framebuffer, sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT * RT_HW_LCD_WIDTH); - } - break; - - case RTGRAPHIC_CTRL_POWERON: - break; - - case RTGRAPHIC_CTRL_POWEROFF: - break; - - case RTGRAPHIC_CTRL_GET_INFO: - memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - - case RTGRAPHIC_CTRL_SET_MODE: - break; - } - - return RT_EOK; -} - -int gd32_hw_lcd_init(void) -{ - _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t) * RT_HW_LCD_WIDTH * RT_HW_LCD_HEIGHT, 32); - if (_rt_framebuffer == RT_NULL) - return -1; /* no memory yet */ - - lcd_config(); - tli_config(); - tli_layer_enable(LAYER0); - tli_reload_config(TLI_FRAME_BLANK_RELOAD_EN); - tli_enable(); - - _lcd_info.bits_per_pixel = LCD_BITS_PER_PIXEL; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - _lcd_info.framebuffer = (void *)_rt_framebuffer; - _lcd_info.width = RT_HW_LCD_WIDTH; - _lcd_info.height = RT_HW_LCD_HEIGHT; - - lcd.type = RT_Device_Class_Graphic; - lcd.init = NULL; - lcd.open = NULL; - lcd.close = NULL; - lcd.read = NULL; - lcd.write = NULL; - lcd.control = rt_lcd_control; - lcd.user_data = (void *)&_lcd_info; - - /* register lcd device to RT-Thread */ - rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR); - - return 0; -} -INIT_DEVICE_EXPORT(gd32_hw_lcd_init); -#endif diff --git a/bsp/gd32450z-eval/drivers/drv_spi.c b/bsp/gd32450z-eval/drivers/drv_spi.c deleted file mode 100644 index 1781266f0d..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_spi.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-05 tanek first implementation. - */ - -#include "drv_spi.h" - -#include -#include - -#ifdef RT_USING_SPI - -#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) && \ - !defined(RT_USING_SPI2) && !defined(RT_USING_SPI3) && \ - !defined(RT_USING_SPI4) && !defined(RT_USING_SPI5) -#error "Please define at least one SPIx" -#endif - -//#define DEBUG - -#define ARR_LEN(__N) (sizeof(__N) / sizeof(__N[0])) - -#ifdef DEBUG -#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) -#else -#define DEBUG_PRINTF(...) -#endif - -/* private rt-thread spi ops function */ -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); - -static struct rt_spi_ops gd32_spi_ops = -{ - configure, - xfer -}; - -static rt_err_t configure(struct rt_spi_device* device, - struct rt_spi_configuration* configuration) -{ - struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus; - struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)spi_bus->parent.user_data; - - spi_parameter_struct spi_init_struct; - - uint32_t spi_periph = f4_spi->spi_periph; - - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); - - /* data_width */ - if(configuration->data_width <= 8) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; - } - else if(configuration->data_width <= 16) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; - } - else - { - return -RT_EIO; - } - - /* baudrate */ - { - rcu_clock_freq_enum spi_src; - uint32_t spi_apb_clock; - uint32_t max_hz; - - max_hz = configuration->max_hz; - - DEBUG_PRINTF("sys freq: %d\n", HAL_RCC_GetSysClockFreq()); - DEBUG_PRINTF("pclk2 freq: %d\n", HAL_RCC_GetPCLK2Freq()); - DEBUG_PRINTF("max freq: %d\n", max_hz); - - if (spi_periph == SPI1 || spi_periph == SPI2) - { - spi_src = CK_APB1; - } - else - { - spi_src = CK_APB2; - } - spi_apb_clock = rcu_clock_freq_get(spi_src); - - if(max_hz >= spi_apb_clock/2) - { - spi_init_struct.prescale = SPI_PSC_2; - } - else if (max_hz >= spi_apb_clock/4) - { - spi_init_struct.prescale = SPI_PSC_4; - } - else if (max_hz >= spi_apb_clock/8) - { - spi_init_struct.prescale = SPI_PSC_8; - } - else if (max_hz >= spi_apb_clock/16) - { - spi_init_struct.prescale = SPI_PSC_16; - } - else if (max_hz >= spi_apb_clock/32) - { - spi_init_struct.prescale = SPI_PSC_32; - } - else if (max_hz >= spi_apb_clock/64) - { - spi_init_struct.prescale = SPI_PSC_64; - } - else if (max_hz >= spi_apb_clock/128) - { - spi_init_struct.prescale = SPI_PSC_128; - } - else - { - /* min prescaler 256 */ - spi_init_struct.prescale = SPI_PSC_256; - } - } /* baudrate */ - - switch(configuration->mode & RT_SPI_MODE_3) - { - case RT_SPI_MODE_0: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - break; - case RT_SPI_MODE_1: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; - case RT_SPI_MODE_2: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; - case RT_SPI_MODE_3: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; - break; - } - - /* MSB or LSB */ - if(configuration->mode & RT_SPI_MSB) - { - spi_init_struct.endian = SPI_ENDIAN_MSB; - } - else - { - spi_init_struct.endian = SPI_ENDIAN_LSB; - } - - spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_init_struct.device_mode = SPI_MASTER; - spi_init_struct.nss = SPI_NSS_SOFT; - - spi_crc_off(spi_periph); - - /* init SPI */ - spi_init(spi_periph, &spi_init_struct); - /* Enable SPI_MASTER */ - spi_enable(spi_periph); - - return RT_EOK; -}; - -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) -{ - struct rt_spi_bus * gd32_spi_bus = (struct rt_spi_bus *)device->bus; - struct gd32f4_spi *f4_spi = (struct gd32f4_spi *)gd32_spi_bus->parent.user_data; - struct rt_spi_configuration * config = &device->config; - struct gd32_spi_cs * gd32_spi_cs = device->parent.user_data; - uint32_t spi_periph = f4_spi->spi_periph; - - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - - /* take CS */ - if(message->cs_take) - { - gpio_bit_reset(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin); - DEBUG_PRINTF("spi take cs\n"); - } - - { - if(config->data_width <= 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - DEBUG_PRINTF("spi poll transfer start: %d\n", size); - - while(size--) - { - rt_uint8_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - // Todo: replace register read/write by gd32f4 lib - //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - // Send the byte - spi_i2s_data_transmit(spi_periph, data); - - //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - // Get the received data - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - DEBUG_PRINTF("spi poll transfer finsh\n"); - } - else if(config->data_width <= 16) - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - while(size--) - { - rt_uint16_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - // Send the byte - spi_i2s_data_transmit(spi_periph, data); - - //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - // Get the received data - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - } - } - - /* release CS */ - if(message->cs_release) - { - gpio_bit_set(gd32_spi_cs->GPIOx, gd32_spi_cs->GPIO_Pin); - DEBUG_PRINTF("spi release cs\n"); - } - - return message->length; -}; - - -static struct rt_spi_bus spi_bus[]; - -static const struct gd32f4_spi spis[] = { -#ifdef RT_USING_SPI0 - {SPI0, RCU_SPI0, &spi_bus[0]}, -#endif - -#ifdef RT_USING_SPI1 - {SPI1, RCU_SPI1, &spi_bus[1]}, -#endif - -#ifdef RT_USING_SPI2 - {SPI2, RCU_SPI2, &spi_bus[2]}, -#endif - -#ifdef RT_USING_SPI3 - {SPI3, RCU_SPI3, &spi_bus[3]}, -#endif - -#ifdef RT_USING_SPI4 - {SPI4, RCU_SPI4, &spi_bus[4]}, -#endif - -#ifdef RT_USING_SPI5 - {SPI5, RCU_SPI5, &spi_bus[5]}, -#endif -}; - -static struct rt_spi_bus spi_bus[ARR_LEN(spis)]; - -/** \brief init and register gd32 spi bus. - * - * \param SPI: gd32 SPI, e.g: SPI1,SPI2,SPI3. - * \param spi_bus_name: spi bus name, e.g: "spi1" - * \return - * - */ -rt_err_t gd32_spi_bus_register(uint32_t spi_periph, - //struct gd32_spi_bus * gd32_spi, - const char * spi_bus_name) -{ - int i; - - RT_ASSERT(spi_bus_name != RT_NULL); - - for (i = 0; i < ARR_LEN(spis); i++) - { - if (spi_periph == spis[i].spi_periph) - { - rcu_periph_clock_enable(spis[i].spi_clk); - spis[i].spi_bus->parent.user_data = (void *)&spis[i]; - rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &gd32_spi_ops); - return RT_EOK; - } - } - - return -RT_ERROR; -} -#endif diff --git a/bsp/gd32450z-eval/drivers/drv_spi.h b/bsp/gd32450z-eval/drivers/drv_spi.h deleted file mode 100644 index 51bae441ca..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_spi.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 20012-01-01 aozima first implementation. - */ - -#ifndef gd32F20X_40X_SPI_H_INCLUDED -#define gd32F20X_40X_SPI_H_INCLUDED - -#include -#include - -#include "gd32f4xx.h" - -struct gd32f4_spi -{ - uint32_t spi_periph; - rcu_periph_enum spi_clk; - struct rt_spi_bus *spi_bus; -}; - - -struct gd32_spi_cs -{ - uint32_t GPIOx; - uint32_t GPIO_Pin; -}; - -/* public function */ -rt_err_t gd32_spi_bus_register(uint32_t spi_periph, - //struct gd32_spi_bus * gd32_spi, - const char * spi_bus_name); - -#endif // gd32F20X_40X_SPI_H_INCLUDED diff --git a/bsp/gd32450z-eval/drivers/drv_spi_flash.c b/bsp/gd32450z-eval/drivers/drv_spi_flash.c deleted file mode 100644 index 1c88a4f43c..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_spi_flash.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-01 aozima first implementation. - * 2012-07-27 aozima fixed variable uninitialized. - */ -#include -#include "drv_spi.h" -#include "spi_flash.h" - -#ifdef RT_USING_SFUD -#include "spi_flash_sfud.h" -#endif - -#include -#include - -#define SPI_PERIPH SPI5 -#define SPI_BUS_NAME "spi5" -#define SPI_FLASH_DEVICE_NAME "spi50" -#define SPI_FLASH_CHIP "gd25q16" - -static int rt_hw_spi5_init(void) -{ - /* register spi bus */ - { - rt_err_t result; - - rcu_periph_clock_enable(RCU_GPIOG); - rcu_periph_clock_enable(RCU_SPI5); - - /* SPI5_CLK(PG13), SPI5_MISO(PG12), SPI5_MOSI(PG14),SPI5_IO2(PG10) and SPI5_IO3(PG11) GPIO pin configuration */ - gpio_af_set(GPIOG, GPIO_AF_5, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); - gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); - gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_200MHZ, GPIO_PIN_10|GPIO_PIN_11| GPIO_PIN_12|GPIO_PIN_13| GPIO_PIN_14); - - result = gd32_spi_bus_register(SPI5, SPI_BUS_NAME); - if (result != RT_EOK) - { - return result; - } - } - - /* attach cs */ - { - static struct rt_spi_device spi_device; - static struct gd32_spi_cs spi_cs; - rt_err_t result; - - spi_cs.GPIOx = GPIOG; - spi_cs.GPIO_Pin = GPIO_PIN_9; - - /* SPI5_CS(PG9) GPIO pin configuration */ - gpio_mode_set(GPIOG, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO_PIN_9); - gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_9); - - gpio_bit_set(GPIOG,GPIO_PIN_9); - - result = rt_spi_bus_attach_device(&spi_device, SPI_FLASH_DEVICE_NAME, SPI_BUS_NAME, (void*)&spi_cs); - if (result != RT_EOK) - { - return result; - } - } - - return RT_EOK; -} -INIT_DEVICE_EXPORT(rt_hw_spi5_init); - -#ifdef RT_USING_SFUD -static int rt_hw_spi_flash_with_sfud_init(void) -{ - if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME)) - { - return -RT_ERROR; - }; - - return RT_EOK; -} -INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init) -#endif diff --git a/bsp/gd32450z-eval/drivers/drv_usart.c b/bsp/gd32450z-eval/drivers/drv_usart.c deleted file mode 100644 index 6b5b0ced96..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_usart.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - * 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode - * 2012-02-08 aozima update for F4. - * 2012-07-28 aozima update for ART board. - * 2016-05-28 armink add DMA Rx mode - */ - -#include -#include -#include - -#ifdef RT_USING_SERIAL - -#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && \ - !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ - !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && \ - !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) -#error "Please define at least one UARTx" - -#endif - -#include - -/* GD32 uart driver */ -// Todo: compress uart info -struct gd32_uart -{ - uint32_t uart_periph; //Todo: 3bits - IRQn_Type irqn; //Todo: 7bits - rcu_periph_enum per_clk; //Todo: 5bits - rcu_periph_enum tx_gpio_clk; //Todo: 5bits - rcu_periph_enum rx_gpio_clk; //Todo: 5bits - uint32_t tx_port; //Todo: 4bits - uint16_t tx_af; //Todo: 4bits - uint16_t tx_pin; //Todo: 4bits - uint32_t rx_port; //Todo: 4bits - uint16_t rx_af; //Todo: 4bits - uint16_t rx_pin; //Todo: 4bits - - struct rt_serial_device * serial; - char *device_name; -}; - -static void uart_isr(struct rt_serial_device *serial); - -#if defined(BSP_USING_UART0) -struct rt_serial_device serial0; - -void USART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial0); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART0 */ - -#if defined(BSP_USING_UART1) -struct rt_serial_device serial1; - -void USART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial1); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART1 */ - -#if defined(BSP_USING_UART2) -struct rt_serial_device serial2; - -void USART2_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial2); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART2 */ - -#if defined(BSP_USING_UART3) -struct rt_serial_device serial3; - -void UART3_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial3); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART3 */ - -#if defined(BSP_USING_UART4) -struct rt_serial_device serial4; - -void UART4_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial4); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* BSP_USING_UART4 */ - -#if defined(BSP_USING_UART5) -struct rt_serial_device serial5; - -void USART5_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial5); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART5 */ - -#if defined(BSP_USING_UART6) -struct rt_serial_device serial6; - -void UART6_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial6); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART6 */ - -#if defined(BSP_USING_UART7) -struct rt_serial_device serial7; - -void UART7_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial7); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* BSP_USING_UART7 */ - -static const struct gd32_uart uarts[] = { - #ifdef BSP_USING_UART0 - { - USART0, // uart peripheral index - USART0_IRQn, // uart iqrn - RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_AF_7, GPIO_PIN_9, // tx port, tx alternate, tx pin - GPIOA, GPIO_AF_7, GPIO_PIN_10, // rx port, rx alternate, rx pin - &serial0, - "uart0", - }, - #endif - - #ifdef BSP_USING_UART1 - { - USART1, // uart peripheral index - USART1_IRQn, // uart iqrn - RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_AF_7, GPIO_PIN_2, // tx port, tx alternate, tx pin - GPIOA, GPIO_AF_7, GPIO_PIN_3, // rx port, rx alternate, rx pin - &serial1, - "uart1", - }, - #endif - - #ifdef BSP_USING_UART2 - { - USART2, // uart peripheral index - USART2_IRQn, // uart iqrn - RCU_USART2, RCU_GPIOB, RCU_GPIOB, // periph clock, tx gpio clock, rt gpio clock - GPIOB, GPIO_AF_7, GPIO_PIN_10, // tx port, tx alternate, tx pin - GPIOB, GPIO_AF_7, GPIO_PIN_11, // rx port, rx alternate, rx pin - &serial2, - "uart2", - }, - #endif - - #ifdef BSP_USING_UART3 - { - UART3, // uart peripheral index - UART3_IRQn, // uart iqrn - RCU_UART3, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_AF_8, GPIO_PIN_10, // tx port, tx alternate, tx pin - GPIOC, GPIO_AF_8, GPIO_PIN_11, // rx port, rx alternate, rx pin - &serial3, - "uart3", - }, - #endif - - #ifdef BSP_USING_UART4 - { - UART4, // uart peripheral index - UART4_IRQn, // uart iqrn - RCU_UART4, RCU_GPIOC, RCU_GPIOD, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_AF_8, GPIO_PIN_12, // tx port, tx alternate, tx pin - GPIOD, GPIO_AF_8, GPIO_PIN_2, // rx port, rx alternate, rx pin - &serial4, - "uart4", - }, - #endif - - #ifdef BSP_USING_UART5 - { - USART5, // uart peripheral index - USART5_IRQn, // uart iqrn - RCU_USART5, RCU_GPIOC, RCU_GPIOC, // periph clock, tx gpio clock, rt gpio clock - GPIOC, GPIO_AF_8, GPIO_PIN_6, // tx port, tx alternate, tx pin - GPIOC, GPIO_AF_8, GPIO_PIN_7, // rx port, rx alternate, rx pin - &serial5, - "uart5", - }, - #endif - - #ifdef BSP_USING_UART6 - { - UART6, // uart peripheral index - UART6_IRQn, // uart iqrn - RCU_UART6, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock - GPIOE, GPIO_AF_8, GPIO_PIN_8, // tx port, tx alternate, tx pin - GPIOE, GPIO_AF_8, GPIO_PIN_7, // rx port, rx alternate, rx pin - &serial6, - "uart6", - }, - #endif - - #ifdef BSP_USING_UART7 - { - UART7, // uart peripheral index - UART7_IRQn, // uart iqrn - RCU_UART7, RCU_GPIOE, RCU_GPIOE, // periph clock, tx gpio clock, rt gpio clock - GPIOE, GPIO_AF_8, GPIO_PIN_1, // tx port, tx alternate, tx pin - GPIOE, GPIO_AF_8, GPIO_PIN_0, // rx port, rx alternate, rx pin - &serial7, - "uart7", - }, - #endif -}; - - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example: -* - Peripheral's clock enable -* - Peripheral's GPIO Configuration -* - NVIC configuration for UART interrupt request enable -* @param huart: UART handle pointer -* @retval None -*/ -void gd32_uart_gpio_init(struct gd32_uart *uart) -{ - /* enable USART clock */ - rcu_periph_clock_enable(uart->tx_gpio_clk); - rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); - - /* connect port to USARTx_Tx */ - gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin); - - /* connect port to USARTx_Rx */ - gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin); - - /* configure USART Tx as alternate function push-pull */ - gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->tx_pin); - gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->tx_pin); - - /* configure USART Rx as alternate function push-pull */ - gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_PULLUP, uart->rx_pin); - gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, uart->rx_pin); - - NVIC_SetPriority(uart->irqn, 0); - NVIC_EnableIRQ(uart->irqn); -} - -static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = (struct gd32_uart *)serial->parent.user_data; - - gd32_uart_gpio_init(uart); - - usart_baudrate_set(uart->uart_periph, cfg->baud_rate); - - switch (cfg->data_bits) - { - case DATA_BITS_9: - usart_word_length_set(uart->uart_periph, USART_WL_9BIT); - break; - - default: - usart_word_length_set(uart->uart_periph, USART_WL_8BIT); - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT); - break; - default: - usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT); - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - usart_parity_config(uart->uart_periph, USART_PM_ODD); - break; - case PARITY_EVEN: - usart_parity_config(uart->uart_periph, USART_PM_EVEN); - break; - default: - usart_parity_config(uart->uart_periph, USART_PM_NONE); - break; - } - - usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE); - usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE); - usart_enable(uart->uart_periph); - - return RT_EOK; -} - -static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irqn); - /* disable interrupt */ - usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); - - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irqn); - /* enable interrupt */ - usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); - break; - } - - return RT_EOK; -} - -static int gd32_putc(struct rt_serial_device *serial, char ch) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - usart_data_transmit(uart->uart_periph, ch); - while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - - return 1; -} - -static int gd32_getc(struct rt_serial_device *serial) -{ - int ch; - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - ch = -1; - if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET) - ch = usart_data_receive(uart->uart_periph); - return ch; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) -{ - struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; - - RT_ASSERT(uart != RT_NULL); - - /* UART in mode Receiver -------------------------------------------------*/ - if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && - (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - /* Clear RXNE interrupt flag */ - usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE); - } -} - -static const struct rt_uart_ops gd32_uart_ops = -{ - gd32_configure, - gd32_control, - gd32_putc, - gd32_getc, -}; - -int gd32_hw_usart_init(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - int i; - - - for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) - { - uarts[i].serial->ops = &gd32_uart_ops; - uarts[i].serial->config = config; - - /* register UART1 device */ - rt_hw_serial_register(uarts[i].serial, - uarts[i].device_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&uarts[i]); - } - - return 0; -} -INIT_BOARD_EXPORT(gd32_hw_usart_init); -#endif diff --git a/bsp/gd32450z-eval/drivers/drv_usart.h b/bsp/gd32450z-eval/drivers/drv_usart.h deleted file mode 100644 index 547384efec..0000000000 --- a/bsp/gd32450z-eval/drivers/drv_usart.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - */ - -#ifndef __USART_H__ -#define __USART_H__ - -#include -#include - -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -int gd32_hw_usart_init(void); - -#endif diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_eval.h b/bsp/gd32450z-eval/drivers/gd32f450z_eval.h deleted file mode 100644 index 6eb91aee01..0000000000 --- a/bsp/gd32450z-eval/drivers/gd32f450z_eval.h +++ /dev/null @@ -1,118 +0,0 @@ -/*! - \file gd32f450z_eval.h - \brief definitions for GD32F450_EVAL's leds, keys and COM ports hardware resources -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-10-19, V1.0.0, firmware for GD32F450Z -*/ - -#ifndef GD32F450Z_EVAL_H -#define GD32F450Z_EVAL_H - -#ifdef cplusplus - extern "C" { -#endif - -#include "gd32f4xx.h" - -/* exported types */ -typedef enum -{ - LED1 = 0, - LED2 = 1, - LED3 = 2 -} led_typedef_enum; - -typedef enum -{ - KEY_WAKEUP = 0, - KEY_TAMPER = 1, - KEY_USER = 2 -} key_typedef_enum; - -typedef enum -{ - KEY_MODE_GPIO = 0, - KEY_MODE_EXTI = 1 -} keymode_typedef_enum; - -/* eval board low layer led */ -#define LEDn 3U - -#define LED1_PIN GPIO_PIN_4 -#define LED1_GPIO_PORT GPIOD -#define LED1_GPIO_CLK RCU_GPIOD - -#define LED2_PIN GPIO_PIN_5 -#define LED2_GPIO_PORT GPIOD -#define LED2_GPIO_CLK RCU_GPIOD - -#define LED3_PIN GPIO_PIN_3 -#define LED3_GPIO_PORT GPIOG -#define LED3_GPIO_CLK RCU_GPIOG - -#define COMn 1U -#define EVAL_COM1 USART0 -#define EVAL_COM1_CLK RCU_USART0 - -#define EVAL_COM1_TX_PIN GPIO_PIN_9 -#define EVAL_COM1_RX_PIN GPIO_PIN_10 - -#define EVAL_COM_GPIO_PORT GPIOA -#define EVAL_COM_GPIO_CLK RCU_GPIOA -#define EVAL_COM_AF GPIO_AF_7 - -#define KEYn 3U - -/* tamper push-button */ -#define TAMPER_KEY_PIN GPIO_PIN_13 -#define TAMPER_KEY_GPIO_PORT GPIOC -#define TAMPER_KEY_GPIO_CLK RCU_GPIOC -#define TAMPER_KEY_EXTI_LINE EXTI_13 -#define TAMPER_KEY_EXTI_PORT_SOURCE EXTI_SOURCE_GPIOC -#define TAMPER_KEY_EXTI_PIN_SOURCE EXTI_SOURCE_PIN13 -#define TAMPER_KEY_EXTI_IRQn EXTI10_15_IRQn - -/* wakeup push-button */ -#define WAKEUP_KEY_PIN GPIO_PIN_0 -#define WAKEUP_KEY_GPIO_PORT GPIOA -#define WAKEUP_KEY_GPIO_CLK RCU_GPIOA -#define WAKEUP_KEY_EXTI_LINE EXTI_0 -#define WAKEUP_KEY_EXTI_PORT_SOURCE EXTI_SOURCE_GPIOA -#define WAKEUP_KEY_EXTI_PIN_SOURCE EXTI_SOURCE_PIN0 -#define WAKEUP_KEY_EXTI_IRQn EXTI0_IRQn - -/* user push-button */ -#define USER_KEY_PIN GPIO_PIN_14 -#define USER_KEY_GPIO_PORT GPIOB -#define USER_KEY_GPIO_CLK RCU_GPIOB -#define USER_KEY_EXTI_LINE EXTI_14 -#define USER_KEY_EXTI_PORT_SOURCE EXTI_SOURCE_GPIOB -#define USER_KEY_EXTI_PIN_SOURCE EXTI_SOURCE_PIN14 -#define USER_KEY_EXTI_IRQn EXTI10_15_IRQn - -/* function declarations */ -/* configures led GPIO */ -void gd_eval_led_init(led_typedef_enum lednum); -/* turn on selected led */ -void gd_eval_led_on(led_typedef_enum lednum); -/* turn off selected led */ -void gd_eval_led_off(led_typedef_enum lednum); -/* toggle the selected led */ -void gd_eval_led_toggle(led_typedef_enum lednum); -/* configure key */ -void gd_eval_key_init(key_typedef_enum key_num, keymode_typedef_enum key_mode); -/* return the selected button state */ -uint8_t gd_eval_key_state_get(key_typedef_enum button); -/* configure COM port */ -void gd_eval_com_init(uint32_t com); - - -#ifdef cplusplus -} -#endif - -#endif /* GD32F450Z_EVAL_H */ diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c deleted file mode 100644 index b71005b6dd..0000000000 --- a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.c +++ /dev/null @@ -1,316 +0,0 @@ -/*! - \file gd32f450z_lcd_eval.c - \brief firmware functions to manage LCD -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-10-19, V1.0.0, firmware for GD32F450Z -*/ - -#include "gd32f450z_lcd_eval.h" - -static void delay(uint32_t time); - -/*! - \brief enable the LCD - \param[in] none - \param[out] none - \retval none -*/ -void lcd_enable(void) -{ - gpio_bit_set(LCD_CS_GPIO_PORT, LCD_CS_PIN); -} - -/*! - \brief disable the LCD - \param[in] none - \param[out] none - \retval none -*/ -void lcd_disable(void) -{ - gpio_bit_reset(LCD_CS_GPIO_PORT, LCD_CS_PIN); -} - -/*! - \brief configure the LCD control line - \param[in] none - \param[out] none - \retval none -*/ -void lcd_ctrl_line_config(void) -{ - /* enable GPIOs clock*/ - rcu_periph_clock_enable(LCD_CS_GPIO_CLK); - rcu_periph_clock_enable(LCD_RS_GPIO_CLK); - - /* configure LCD_CS_GPIO_PORT(PD11) and LCD_RS_GPIO_PORT(PE3) */ - gpio_mode_set(LCD_CS_GPIO_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LCD_CS_PIN); - gpio_output_options_set(LCD_CS_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,LCD_CS_PIN); - - gpio_mode_set(LCD_RS_GPIO_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LCD_RS_PIN); - gpio_output_options_set(LCD_RS_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ,LCD_RS_PIN); - - /* set the chip select pin */ - lcd_ctrl_line_set(LCD_CS_GPIO_PORT, LCD_CS_PIN); -} - -/*! - \brief set the LCD control line - \param[in] gpiox: control line GPIO - \arg LCD_CS_GPIO_PORT: LCD chip select GPIO - \arg LCD_RS_GPIO_PORT: LCD register/RAM selection GPIO - \param[in] gpiopin: control line pin - \arg LCD_CS_PIN: LCD chip select pin - \arg LCD_RS_PIN: LCD register/RAM selection pin - \param[out] none - \retval none -*/ -void lcd_ctrl_line_set(uint32_t gpiox, uint16_t gpiopin) -{ - gpio_bit_set(gpiox, gpiopin); -} - -/*! - \brief reset the LCD control line - \param[in] gpiox: control line GPIO - \arg LCD_CS_GPIO_PORT: LCD chip select GPIO - \arg LCD_RS_GPIO_PORT: LCD register/RAM selection GPIO - \param[in] gpiopin: control line pin - \arg LCD_CS_PIN: LCD chip select pin - \arg LCD_RS_PIN: LCD register/RAM selection pin - \param[out] none - \retval none -*/ -void lcd_ctrl_line_reset(uint32_t gpiox, uint16_t gpiopin) -{ - gpio_bit_reset(gpiox, gpiopin); -} - -/*! - \brief configure the LCD SPI and it's GPIOs - \param[in] none - \param[out] none - \retval none -*/ -void lcd_spi_config(void) -{ - spi_parameter_struct spi_init_struct; - rcu_periph_clock_enable(RCU_GPIOG); - rcu_periph_clock_enable(RCU_SPI5); - - /* configure SPI5_SCK(PG13) and SPI5_MOSI(PG14) */ - gpio_af_set(GPIOG,GPIO_AF_5,GPIO_PIN_13); - gpio_af_set(GPIOG,GPIO_AF_5,GPIO_PIN_14); - gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13|GPIO_PIN_14); - gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13|GPIO_PIN_14); - spi_i2s_deinit(SPI5); - - if(0 == (SPI_CTL0(LCD_SPI) & SPI_CTL0_SPIEN)){ - spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_init_struct.device_mode = SPI_MASTER; - spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_init_struct.nss = SPI_NSS_SOFT; - spi_init_struct.prescale = SPI_PSC_16; - spi_init_struct.endian = SPI_ENDIAN_MSB; - spi_init(LCD_SPI, &spi_init_struct); - spi_enable(LCD_SPI); - } -} - -/*! - \brief write command to select LCD register - \param[in] lcd_register: the address of the selected register - \param[out] none - \retval none -*/ -void lcd_command_write(uint8_t lcd_register) -{ - /* reset LCD_RS to send command */ - lcd_ctrl_line_reset(LCD_RS_GPIO_PORT, LCD_RS_PIN); - - /* reset LCD control line and send command */ - lcd_disable(); - while(RESET == spi_i2s_flag_get(LCD_SPI, SPI_FLAG_TBE)) ; - spi_i2s_data_transmit(LCD_SPI, lcd_register); - - /* wait until a data is sent */ - while(RESET != spi_i2s_flag_get(LCD_SPI, SPI_FLAG_TRANS)); - - lcd_enable(); -} - -/*! - \brief write data to select LCD register - \param[in] value: the value that will be written to the selected register - \param[out] none - \retval none -*/ -void lcd_data_write(uint8_t value) -{ - /* set LCD_RS to send data */ - lcd_ctrl_line_set(LCD_RS_GPIO_PORT, LCD_RS_PIN); - - /* reset LCD control line and send data */ - lcd_disable(); - while(RESET == spi_i2s_flag_get(LCD_SPI, SPI_FLAG_TBE)) ; - - spi_i2s_data_transmit(LCD_SPI, value); - - /* wait until a data is sent */ - while(RESET != spi_i2s_flag_get(LCD_SPI, SPI_FLAG_TRANS)) ; - - lcd_enable(); -} - -/*! - \brief configure the LCD based on the power on sequence - \param[in] none - \param[out] none - \retval none -*/ -void lcd_power_on(void) -{ - lcd_command_write(0x11); - delay(120); - lcd_command_write(0x36); - lcd_data_write(0x48); - lcd_command_write(0x3A); - lcd_data_write(0x55); - lcd_command_write(0xB4); - lcd_data_write(0x11); - lcd_command_write(0xB3); - lcd_data_write(0x00); - lcd_data_write(0x00); - lcd_data_write(0x00); - lcd_data_write(0x20); - lcd_command_write(0xC0); - lcd_data_write(0x10); - lcd_data_write(0x3B); - lcd_data_write(0x00); - lcd_data_write(0x12); - lcd_data_write(0x01); - lcd_command_write(0xC5); - lcd_data_write(0x07); - lcd_command_write(0xC8); - lcd_data_write(0x01 ); - lcd_data_write(0x36); - lcd_data_write(0x00); - lcd_data_write(0x02); - lcd_data_write(0x00); - lcd_data_write(0x1C); - lcd_data_write(0x77); - lcd_data_write(0x14); - lcd_data_write(0x67); - lcd_data_write(0x20); - lcd_data_write(0x0E); - lcd_data_write(0x00); - lcd_command_write(0xD0); - lcd_data_write(0x44); - lcd_data_write(0x41 ); - lcd_data_write(0x08); - lcd_data_write(0xC2); - lcd_command_write(0xD1); - lcd_data_write(0x50); - lcd_data_write(0x11); - lcd_command_write(0xD2); - lcd_data_write(0x05); - lcd_data_write(0x12); - - lcd_command_write(0xC6); - lcd_data_write(0x83); - lcd_command_write(0x29); - delay(5); -} -/** - * @brief New Version 3.5" TFT RGB Hardware needs add this initilize funtion ---By xufei 2016.10.21 - Modified by GAO HAIYANG, test pass, 17, Nov, 2016 - * @param None - * @retval None - */ -void lcd_power_on3(void) -{ - lcd_command_write(0xC0);//power control1 command/w/ - lcd_data_write(0x0A); // P-Gamma level//4.1875v - lcd_data_write(0x0A); // N-Gamma level - lcd_command_write(0xC1); // BT & VC Setting//power contrl2 command/w/ - lcd_data_write(0x41); - lcd_data_write(0x07); // VCI1 = 2.5V - lcd_command_write(0xC2); // DC1.DC0 Setting//power control3 for normal mode - lcd_data_write(0x33); - lcd_command_write(0xC5);//VCOM control - lcd_data_write(0x00); //NV memory is not programmed - lcd_data_write(0x42); // VCM Setting - lcd_data_write(0x80); // VCM Register Enable - lcd_command_write(0xB0); //interface mode control //Polarity Setting - lcd_data_write(0x02); - lcd_command_write(0xB1);//frame rate control for normal mode - lcd_data_write(0xB0); // Frame Rate Setting//70 frame per second//no division for internal clocks - lcd_data_write(0x11);//17 clocks per line period for idle mode at cpu interface - lcd_command_write(0xB4);//dispaly inversion control - lcd_data_write(0x00); // disable Z-inversion , column inversion - lcd_command_write(0xB6); //display function control// RM.DM Setting - lcd_data_write(0x70);////0xF0 - lcd_data_write(0x02);//direction of gate scan: G1->G480 one by one, source scan: S1->S960, scan cycle if interval scan in non-display area - lcd_data_write(0x3B); // number of lines to drive LCD: 8*(0x3C) = 480 - lcd_command_write(0xB7); // Entry Mode - lcd_data_write(0x07); // disable low voltage detection, normal display, - lcd_command_write(0xF0); // Enter ENG , must be set before gamma setting - lcd_data_write(0x36); - lcd_data_write(0xA5); - lcd_data_write(0xD3); - lcd_command_write(0xE5); // Open gamma function , must be set before gamma setting - lcd_data_write(0x80); - lcd_command_write(0xE5); // Page 1 - lcd_data_write(0x01); - lcd_command_write(0XB3); // WEMODE=0(Page 1) , pixels over window setting will be ignored.//frame rate control in partial mode/full colors - lcd_data_write(0x00); - lcd_command_write(0xE5); // Page 0 - lcd_data_write(0x00); - lcd_command_write(0xF0); // Exit ENG , must be set before gamma setting - lcd_data_write(0x36); - lcd_data_write(0xA5); - lcd_data_write(0x53); - lcd_command_write(0xE0); // Gamma setting - //y fine adjustment register for positive polarity - lcd_data_write(0x00); - lcd_data_write(0x35); - lcd_data_write(0x33); - //y gradient adjustment register for positive polarity - lcd_data_write(0x00); - //y amplitude adjustment register for positive polarity - lcd_data_write(0x00); - lcd_data_write(0x00); - //y fine adjustment register for negative polarity - lcd_data_write(0x00); - lcd_data_write(0x35); - lcd_data_write(0x33); - //y gradient adjustment register for negative polarity - lcd_data_write(0x00); - //y amplitude adjustment register for negative polarity - lcd_data_write(0x00); - lcd_data_write(0x00); - lcd_command_write(0x36); // memory data access control // - lcd_data_write(0x48);// - lcd_command_write(0x3A); // interface pixel format setting - lcd_data_write(0x55);//16-bits - lcd_command_write(0x11); // Exit sleep mode - lcd_command_write(0x29); // Display on - - delay(10); -} -/*! - \brief insert a delay time - \param[in] time: delay time length - \param[out] none - \retval none -*/ -static void delay(uint32_t time) -{ - uint32_t timecount = time; - while(0 != timecount--); -} diff --git a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h b/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h deleted file mode 100644 index 00b7f51cb2..0000000000 --- a/bsp/gd32450z-eval/drivers/gd32f450z_lcd_eval.h +++ /dev/null @@ -1,55 +0,0 @@ -/*! - \file gd32f450z_lcd_eval.h - \brief definitions for GD32F450Z_EVAL's LCD -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-10-19, V1.0.0, firmware for GD32F450Z -*/ - -#ifndef GD32F450Z_LCD_EVAL_H -#define GD32F450Z_LCD_EVAL_H - -#include "gd32f450z_eval.h" - -#define LCD_CS_PIN GPIO_PIN_11 -#define LCD_CS_GPIO_PORT GPIOD -#define LCD_CS_GPIO_CLK RCU_GPIOD - -#define LCD_RS_PIN GPIO_PIN_3 -#define LCD_RS_GPIO_PORT GPIOE -#define LCD_RS_GPIO_CLK RCU_GPIOE - -#define LCD_SPI_SCK_PIN GPIO_PIN_13 -#define LCD_SPI_SCK_GPIO_PORT GPIOG -#define LCD_SPI_SCK_GPIO_CLK RCU_GPIOG - -#define LCD_SPI_MOSI_PIN GPIO_PIN_14 -#define LCD_SPI_MOSI_GPIO_PORT GPIOG -#define LCD_SPI_MOSI_GPIO_CLK RCU_GPIOG - -#define LCD_SPI SPI5 -#define LCD_SPI_CLK RCU_SPI5 - -/* enable the LCD */ -void lcd_enable(void); -/* disable the LCD */ -void lcd_disable(void); -/* configure the LCD control line */ -void lcd_ctrl_line_config(void); -/* set the LCD control line */ -void lcd_ctrl_line_set(uint32_t gpiox, uint16_t gpiopin); -/* reset the LCD control line */ -void lcd_ctrl_line_reset(uint32_t gpiox, uint16_t gpiopin); -/* configure the LCD SPI and it's GPIOs */ -void lcd_spi_config(void); -/* write command to select LCD register */ -void lcd_command_write(uint8_t lcd_register); -/* write data to select LCD register */ -void lcd_data_write(uint8_t value); -/* configure the LCD based on the power on sequence */ -void lcd_power_on(void); -void lcd_power_on3(void); -#endif /* GD32F450Z_LCD_EVAL_H */ diff --git a/bsp/gd32450z-eval/drivers/gd32f4xx_libopt.h b/bsp/gd32450z-eval/drivers/gd32f4xx_libopt.h deleted file mode 100644 index d26e3d15ec..0000000000 --- a/bsp/gd32450z-eval/drivers/gd32f4xx_libopt.h +++ /dev/null @@ -1,45 +0,0 @@ -/*! - \file gd32f4xx_libopt.h - \brief library optional for gd32f4xx -*/ - -/* - Copyright (C) 2016 GigaDevice - - 2016-10-19, V1.0.0, firmware for GD32F4xx -*/ - -#ifndef GD32F4XX_LIBOPT_H -#define GD32F4XX_LIBOPT_H -#include "gd32f4xx_rcu.h" -#include "gd32f4xx_adc.h" -#include "gd32f4xx_can.h" -#include "gd32f4xx_crc.h" -#include "gd32f4xx_ctc.h" -#include "gd32f4xx_dac.h" -#include "gd32f4xx_dbg.h" -#include "gd32f4xx_dci.h" -#include "gd32f4xx_dma.h" -//#include "gd32f4xx_enet.h" -#include "gd32f4xx_exmc.h" -#include "gd32f4xx_exti.h" -#include "gd32f4xx_fmc.h" -#include "gd32f4xx_fwdgt.h" -#include "gd32f4xx_gpio.h" -#include "gd32f4xx_syscfg.h" -#include "gd32f4xx_i2c.h" -#include "gd32f4xx_ipa.h" -#include "gd32f4xx_iref.h" -#include "gd32f4xx_pmu.h" -#include "gd32f4xx_rcu.h" -#include "gd32f4xx_rtc.h" -#include "gd32f4xx_sdio.h" -#include "gd32f4xx_spi.h" -#include "gd32f4xx_timer.h" -#include "gd32f4xx_tli.h" -#include "gd32f4xx_trng.h" -#include "gd32f4xx_usart.h" -#include "gd32f4xx_wwdgt.h" -#include "gd32f4xx_misc.h" - -#endif /* GD32F4XX_LIBOPT_H */ diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.c b/bsp/gd32450z-eval/drivers/synopsys_emac.c deleted file mode 100644 index 1894792d82..0000000000 --- a/bsp/gd32450z-eval/drivers/synopsys_emac.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "synopsys_emac.h" -#include "gd32f4xx_enet.h" - -/* The state of enet initialization */ -volatile uint32_t enet_init_state = 0; - -/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ -extern EMAC_DMADESCTypeDef *DMATxDescToSet; -extern EMAC_DMADESCTypeDef *DMARxDescToGet; - -/** - * Initializes the ETHERNET peripheral according to the specified - */ -rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock) -{ - /*-------------------------------- Reset ethernet -------------------------------*/ - enet_deinit(); - enet_software_reset(); - - /* configure the parameters which are usually less cared for enet initialization */ - enet_initpara_config(HALFDUPLEX_OPTION, ENET_CARRIERSENSE_DISABLE|ENET_RECEIVEOWN_ENABLE|ENET_RETRYTRANSMISSION_DISABLE|ENET_BACKOFFLIMIT_10|ENET_DEFERRALCHECK_DISABLE); - - /*-------------------------------- Initialize ENET ------------------------------*/ - enet_init_state = enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS); - - /* Return Ethernet configuration success */ - return EMAC_SUCCESS; -} - -/** - * Enables or disables the specified ETHERNET DMA interrupts. - */ -void EMAC_INT_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT, rt_bool_t NewState) -{ - if (NewState) - { - /* Enable the selected ETHERNET DMA interrupts */ - ETHERNET_MAC->IER |= EMAC_DMA_IT; - } - else - { - /* Disable the selected ETHERNET DMA interrupts */ - ETHERNET_MAC->IER &=(~(rt_uint32_t)EMAC_DMA_IT); - } -} - -/** - * Configures the selected MAC address. - */ -void EMAC_MAC_Addr_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t MacAddr, rt_uint8_t *Addr) -{ - rt_uint32_t value; - - /* Calculate the selectecd MAC address high register */ - value = ((rt_uint32_t)Addr[5] << 8) | (rt_uint32_t)Addr[4]; - /* Load the selectecd MAC address high register */ - //(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_HBASE + MacAddr)) = value; - ETHERNET_MAC->MARs[MacAddr].MARH = value; - /* Calculate the selectecd MAC address low register */ - value = ((rt_uint32_t)Addr[3] << 24) | ((rt_uint32_t)Addr[2] << 16) | ((rt_uint32_t)Addr[1] << 8) | Addr[0]; - - /* Load the selectecd MAC address low register */ - //(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_LBASE + MacAddr)) = value; - ETHERNET_MAC->MARs[MacAddr].MARL = value; -} - -/** - * Enables or disables the MAC transmission. - */ -void EMAC_MACTransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState) -{ - if (NewState) - { - /* Enable the MAC transmission */ - ETHERNET_MAC->MCR |= EMAC_MACCR_TE; - } - else - { - /* Disable the MAC transmission */ - ETHERNET_MAC->MCR &= ~EMAC_MACCR_TE; - } -} - -/** - * Clears the ETHERNET transmit FIFO. - */ -void EMAC_FlushTransmitFIFO(struct rt_synopsys_eth * ETHERNET_MAC) -{ - /* Set the Flush Transmit FIFO bit */ - ETHERNET_MAC->OMR |= EMAC_DMAOMR_FTF; -} - -/** - * Enables or disables the MAC reception. - */ -void EMAC_MACReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState) -{ - if (NewState) - { - /* Enable the MAC reception */ - ETHERNET_MAC->MCR |= EMAC_MACCR_RE; - } - else - { - /* Disable the MAC reception */ - ETHERNET_MAC->MCR &= ~EMAC_MACCR_RE; - } -} - -/** - * Enables or disables the DMA transmission. - */ -void EMAC_DMATransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState) -{ - if (NewState) - { - /* Enable the DMA transmission */ - ETHERNET_MAC->OMR |= EMAC_DMAOMR_ST; - } - else - { - /* Disable the DMA transmission */ - ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_ST; - } -} - -/** - * Enables or disables the DMA reception. - */ -void EMAC_DMAReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState) -{ - if (NewState) - { - /* Enable the DMA reception */ - ETHERNET_MAC->OMR |= EMAC_DMAOMR_SR; - } - else - { - /* Disable the DMA reception */ - ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_SR; - } -} - -/** - * Enables ENET MAC and DMA reception/transmission - */ -void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC) -{ - /* Enable transmit state machine of the MAC for transmission on the MII */ - EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE); - /* Flush Transmit FIFO */ - enet_txfifo_flush(); - /* Enable receive state machine of the MAC for reception from the MII */ - EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE); - - /* Start DMA transmission */ - EMAC_DMATransmissionCmd(ETHERNET_MAC, RT_TRUE); - /* Start DMA reception */ - EMAC_DMAReceptionCmd(ETHERNET_MAC, RT_TRUE); -} - -/** - * Clears the ETHERNET's DMA interrupt pending bit. - */ -void EMAC_clear_pending(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t pending) -{ - /* Clear the selected ETHERNET DMA IT */ - ETHERNET_MAC->SR = (rt_uint32_t) pending; -} - -/** - * Resumes the DMA Transmission by writing to the DmaRxPollDemand register - * (the data written could be anything). This forces the DMA to resume reception. - */ -void EMAC_resume_reception(struct rt_synopsys_eth * ETHERNET_MAC) -{ - ETHERNET_MAC->RPDR = 0; -} - -/** - * Resumes the DMA Transmission by writing to the DmaTxPollDemand register - * (the data written could be anything). This forces the DMA to resume transmission. - */ -void EMAC_resume_transmission(struct rt_synopsys_eth * ETHERNET_MAC) -{ - ETHERNET_MAC->TPDR = 0; -} - -/** - * Read a PHY register - */ -rt_uint16_t EMAC_PHY_read(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg) -{ - rt_uint32_t value = 0; - volatile rt_uint32_t timeout = 0; - - /* Get the ETHERNET MACMIIAR value */ - value = ETHERNET_MAC->GAR; - /* Keep only the CSR Clock Range CR[2:0] bits value */ - value &= ~MACMIIAR_CR_MASK; - /* Prepare the MII address register value */ - value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */ - value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */ - value &= ~EMAC_MACMIIAR_MW; /* Set the read mode */ - value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */ - /* Write the result value into the MII Address register */ - ETHERNET_MAC->GAR = value; - /* Check for the Busy flag */ - do - { - timeout++; - value = ETHERNET_MAC->GAR; - } - while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_READ_TO)); - /* Return ERROR in case of timeout */ - if(timeout == PHY_READ_TO) - { - return (rt_uint16_t)EMAC_ERROR; - } - - /* Return data register value */ - return (rt_uint16_t)(ETHERNET_MAC->GDR); -} - -/** - * Write to a PHY register - */ -rt_uint32_t EMAC_PHY_write(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg, rt_uint16_t PHYValue) -{ - rt_uint32_t value = 0; - volatile rt_uint32_t timeout = 0; - - /* Get the ETHERNET MACMIIAR value */ - value = ETHERNET_MAC->GAR; - /* Keep only the CSR Clock Range CR[2:0] bits value */ - value &= ~MACMIIAR_CR_MASK; - /* Prepare the MII register address value */ - value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */ - value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */ - value |= EMAC_MACMIIAR_MW; /* Set the write mode */ - value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */ - /* Give the value to the MII data register */ - ETHERNET_MAC->GDR = PHYValue; - /* Write the result value into the MII Address register */ - ETHERNET_MAC->GAR = value; - /* Check for the Busy flag */ - do - { - timeout++; - value = ETHERNET_MAC->GAR; - } - while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_WRITE_TO)); - /* Return ERROR in case of timeout */ - if(timeout == PHY_WRITE_TO) - { - return EMAC_ERROR; - } - - /* Return SUCCESS */ - return EMAC_SUCCESS; -} diff --git a/bsp/gd32450z-eval/drivers/synopsys_emac.h b/bsp/gd32450z-eval/drivers/synopsys_emac.h deleted file mode 100644 index f6c303ce7f..0000000000 --- a/bsp/gd32450z-eval/drivers/synopsys_emac.h +++ /dev/null @@ -1,1277 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __SYNOPSYS_EMAC_H__ -#define __SYNOPSYS_EMAC_H__ - -#include - - -/******************************************************************************/ -/* Ethernet MAC Registers bits definitions */ -/******************************************************************************/ -/* Bit definition for Ethernet MAC Control Register register */ -#define EMAC_MACCR_WD ((rt_uint32_t)0x00800000) /* Watchdog disable */ -#define EMAC_MACCR_JD ((rt_uint32_t)0x00400000) /* Jabber disable */ -#define EMAC_MACCR_IFG ((rt_uint32_t)0x000E0000) /* Inter-frame gap */ -#define EMAC_MACCR_IFG_96Bit ((rt_uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ -#define EMAC_MACCR_IFG_88Bit ((rt_uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ -#define EMAC_MACCR_IFG_80Bit ((rt_uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ -#define EMAC_MACCR_IFG_72Bit ((rt_uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ -#define EMAC_MACCR_IFG_64Bit ((rt_uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ -#define EMAC_MACCR_IFG_56Bit ((rt_uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ -#define EMAC_MACCR_IFG_48Bit ((rt_uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ -#define EMAC_MACCR_IFG_40Bit ((rt_uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ -#define EMAC_MACCR_CSD ((rt_uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ -#define EMAC_MACCR_FES ((rt_uint32_t)0x00004000) /* Fast ethernet speed */ -#define EMAC_MACCR_ROD ((rt_uint32_t)0x00002000) /* Receive own disable */ -#define EMAC_MACCR_LM ((rt_uint32_t)0x00001000) /* loopback mode */ -#define EMAC_MACCR_DM ((rt_uint32_t)0x00000800) /* Duplex mode */ -#define EMAC_MACCR_IPCO ((rt_uint32_t)0x00000400) /* IP Checksum offload */ -#define EMAC_MACCR_RD ((rt_uint32_t)0x00000200) /* Retry disable */ -#define EMAC_MACCR_APCS ((rt_uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ -#define EMAC_MACCR_BL ((rt_uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling - a transmission attempt during retries after a collision: 0 =< r <2^k */ -#define EMAC_MACCR_BL_10 ((rt_uint32_t)0x00000000) /* k = min (n, 10) */ -#define EMAC_MACCR_BL_8 ((rt_uint32_t)0x00000020) /* k = min (n, 8) */ -#define EMAC_MACCR_BL_4 ((rt_uint32_t)0x00000040) /* k = min (n, 4) */ -#define EMAC_MACCR_BL_1 ((rt_uint32_t)0x00000060) /* k = min (n, 1) */ -#define EMAC_MACCR_DC ((rt_uint32_t)0x00000010) /* Defferal check */ -#define EMAC_MACCR_TE ((rt_uint32_t)0x00000008) /* Transmitter enable */ -#define EMAC_MACCR_RE ((rt_uint32_t)0x00000004) /* Receiver enable */ - -/* Bit definition for Ethernet MAC Frame Filter Register */ -#define EMAC_MACFFR_RA ((rt_uint32_t)0x80000000) /* Receive all */ -#define EMAC_MACFFR_HPF ((rt_uint32_t)0x00000400) /* Hash or perfect filter */ -#define EMAC_MACFFR_SAF ((rt_uint32_t)0x00000200) /* Source address filter enable */ -#define EMAC_MACFFR_SAIF ((rt_uint32_t)0x00000100) /* SA inverse filtering */ -#define EMAC_MACFFR_PCF ((rt_uint32_t)0x000000C0) /* Pass control frames: 3 cases */ -#define EMAC_MACFFR_PCF_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ -#define EMAC_MACFFR_PCF_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ -#define EMAC_MACFFR_PCF_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ -#define EMAC_MACFFR_BFD ((rt_uint32_t)0x00000020) /* Broadcast frame disable */ -#define EMAC_MACFFR_PAM ((rt_uint32_t)0x00000010) /* Pass all mutlicast */ -#define EMAC_MACFFR_DAIF ((rt_uint32_t)0x00000008) /* DA Inverse filtering */ -#define EMAC_MACFFR_HM ((rt_uint32_t)0x00000004) /* Hash multicast */ -#define EMAC_MACFFR_HU ((rt_uint32_t)0x00000002) /* Hash unicast */ -#define EMAC_MACFFR_PM ((rt_uint32_t)0x00000001) /* Promiscuous mode */ - -/* Bit definition for Ethernet MAC Hash Table High Register */ -#define EMAC_MACHTHR_HTH ((rt_uint32_t)0xFFFFFFFF) /* Hash table high */ - -/* Bit definition for Ethernet MAC Hash Table Low Register */ -#define EMAC_MACHTLR_HTL ((rt_uint32_t)0xFFFFFFFF) /* Hash table low */ - -/* Bit definition for Ethernet MAC MII Address Register */ -#define EMAC_MACMIIAR_PA ((rt_uint32_t)0x0000F800) /* Physical layer address */ -#define EMAC_MACMIIAR_MR ((rt_uint32_t)0x000007C0) /* MII register in the selected PHY */ -#define EMAC_MACMIIAR_CR ((rt_uint32_t)0x0000001C) /* CR clock range: 6 cases */ -#define EMAC_MACMIIAR_CR_Div42 ((rt_uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ -#define EMAC_MACMIIAR_CR_Div62 ((rt_uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ -#define EMAC_MACMIIAR_CR_Div16 ((rt_uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ -#define EMAC_MACMIIAR_CR_Div26 ((rt_uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ -#define EMAC_MACMIIAR_CR_Div102 ((rt_uint32_t)0x00000010) /* HCLK:150-250 MHz; MDC clock= HCLK/102 */ -#define EMAC_MACMIIAR_CR_Div122 ((rt_uint32_t)0x00000014) /* HCLK:250-300 MHz; MDC clock= HCLK/122*/ -#define EMAC_MACMIIAR_MW ((rt_uint32_t)0x00000002) /* MII write */ -#define EMAC_MACMIIAR_MB ((rt_uint32_t)0x00000001) /* MII busy */ - -/* Bit definition for Ethernet MAC MII Data Register */ -#define EMAC_MACMIIDR_MD ((rt_uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ - -/* Bit definition for Ethernet MAC Flow Control Register */ -#define EMAC_MACFCR_PT ((rt_uint32_t)0xFFFF0000) /* Pause time */ -#define EMAC_MACFCR_ZQPD ((rt_uint32_t)0x00000080) /* Zero-quanta pause disable */ -#define EMAC_MACFCR_PLT ((rt_uint32_t)0x00000030) /* Pause low threshold: 4 cases */ -#define EMAC_MACFCR_PLT_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */ -#define EMAC_MACFCR_PLT_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */ -#define EMAC_MACFCR_PLT_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */ -#define EMAC_MACFCR_PLT_Minus256 ((rt_uint32_t)0x00000030) /* Pause time minus 256 slot times */ -#define EMAC_MACFCR_UPFD ((rt_uint32_t)0x00000008) /* Unicast pause frame detect */ -#define EMAC_MACFCR_RFCE ((rt_uint32_t)0x00000004) /* Receive flow control enable */ -#define EMAC_MACFCR_TFCE ((rt_uint32_t)0x00000002) /* Transmit flow control enable */ -#define EMAC_MACFCR_FCBBPA ((rt_uint32_t)0x00000001) /* Flow control busy/backpressure activate */ - -/* Bit definition for Ethernet MAC VLAN Tag Register */ -#define EMAC_MACVLANTR_VLANTC ((rt_uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ -#define EMAC_MACVLANTR_VLANTI ((rt_uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ - -/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ -#define EMAC_MACRWUFFR_D ((rt_uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ -/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. - Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ -/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask - Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask - Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask - Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask - Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - - RSVD - Filter1 Command - RSVD - Filter0 Command - Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset - Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 - Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ - -/* Bit definition for Ethernet MAC PMT Control and Status Register */ -#define EMAC_MACPMTCSR_WFFRPR ((rt_uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define EMAC_MACPMTCSR_GU ((rt_uint32_t)0x00000200) /* Global Unicast */ -#define EMAC_MACPMTCSR_WFR ((rt_uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define EMAC_MACPMTCSR_MPR ((rt_uint32_t)0x00000020) /* Magic Packet Received */ -#define EMAC_MACPMTCSR_WFE ((rt_uint32_t)0x00000004) /* Wake-Up Frame Enable */ -#define EMAC_MACPMTCSR_MPE ((rt_uint32_t)0x00000002) /* Magic Packet Enable */ -#define EMAC_MACPMTCSR_PD ((rt_uint32_t)0x00000001) /* Power Down */ - -/* Bit definition for Ethernet MAC Status Register */ -#define EMAC_MACSR_TSTS ((rt_uint32_t)0x00000200) /* Time stamp trigger status */ -#define EMAC_MACSR_MMCTS ((rt_uint32_t)0x00000040) /* MMC transmit status */ -#define EMAC_MACSR_MMMCRS ((rt_uint32_t)0x00000020) /* MMC receive status */ -#define EMAC_MACSR_MMCS ((rt_uint32_t)0x00000010) /* MMC status */ -#define EMAC_MACSR_PMTS ((rt_uint32_t)0x00000008) /* PMT status */ - -/* Bit definition for Ethernet MAC Interrupt Mask Register */ -#define EMAC_MACIMR_TSTIM ((rt_uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ -#define EMAC_MACIMR_PMTIM ((rt_uint32_t)0x00000008) /* PMT interrupt mask */ - -/* Bit definition for Ethernet MAC Address0 High Register */ -#define EMAC_MACA0HR_MACA0H ((rt_uint32_t)0x0000FFFF) /* MAC address0 high */ - -/* Bit definition for Ethernet MAC Address0 Low Register */ -#define EMAC_MACA0LR_MACA0L ((rt_uint32_t)0xFFFFFFFF) /* MAC address0 low */ - -/* Bit definition for Ethernet MAC Address1 High Register */ -#define EMAC_MACA1HR_AE ((rt_uint32_t)0x80000000) /* Address enable */ -#define EMAC_MACA1HR_SA ((rt_uint32_t)0x40000000) /* Source address */ -#define EMAC_MACA1HR_MBC ((rt_uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define EMAC_MACA1HR_MBC_HBits15_8 ((rt_uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define EMAC_MACA1HR_MBC_HBits7_0 ((rt_uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define EMAC_MACA1HR_MBC_LBits31_24 ((rt_uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define EMAC_MACA1HR_MBC_LBits23_16 ((rt_uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define EMAC_MACA1HR_MBC_LBits15_8 ((rt_uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define EMAC_MACA1HR_MBC_LBits7_0 ((rt_uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ -#define EMAC_MACA1HR_MACA1H ((rt_uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address1 Low Register */ -#define EMAC_MACA1LR_MACA1L ((rt_uint32_t)0xFFFFFFFF) /* MAC address1 low */ - -/* Bit definition for Ethernet MAC Address2 High Register */ -#define EMAC_MACA2HR_AE ((rt_uint32_t)0x80000000) /* Address enable */ -#define EMAC_MACA2HR_SA ((rt_uint32_t)0x40000000) /* Source address */ -#define EMAC_MACA2HR_MBC ((rt_uint32_t)0x3F000000) /* Mask byte control */ -#define EMAC_MACA2HR_MBC_HBits15_8 ((rt_uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define EMAC_MACA2HR_MBC_HBits7_0 ((rt_uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define EMAC_MACA2HR_MBC_LBits31_24 ((rt_uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define EMAC_MACA2HR_MBC_LBits23_16 ((rt_uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define EMAC_MACA2HR_MBC_LBits15_8 ((rt_uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define EMAC_MACA2HR_MBC_LBits7_0 ((rt_uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define EMAC_MACA2HR_MACA2H ((rt_uint32_t)0x0000FFFF) /* MAC address1 high */ - -/* Bit definition for Ethernet MAC Address2 Low Register */ -#define EMAC_MACA2LR_MACA2L ((rt_uint32_t)0xFFFFFFFF) /* MAC address2 low */ - -/* Bit definition for Ethernet MAC Address3 High Register */ -#define EMAC_MACA3HR_AE ((rt_uint32_t)0x80000000) /* Address enable */ -#define EMAC_MACA3HR_SA ((rt_uint32_t)0x40000000) /* Source address */ -#define EMAC_MACA3HR_MBC ((rt_uint32_t)0x3F000000) /* Mask byte control */ -#define EMAC_MACA3HR_MBC_HBits15_8 ((rt_uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define EMAC_MACA3HR_MBC_HBits7_0 ((rt_uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define EMAC_MACA3HR_MBC_LBits31_24 ((rt_uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define EMAC_MACA3HR_MBC_LBits23_16 ((rt_uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define EMAC_MACA3HR_MBC_LBits15_8 ((rt_uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define EMAC_MACA3HR_MBC_LBits7_0 ((rt_uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ -#define EMAC_MACA3HR_MACA3H ((rt_uint32_t)0x0000FFFF) /* MAC address3 high */ - -/* Bit definition for Ethernet MAC Address3 Low Register */ -#define EMAC_MACA3LR_MACA3L ((rt_uint32_t)0xFFFFFFFF) /* MAC address3 low */ - -/******************************************************************************/ -/* Ethernet MMC Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet MMC Contol Register */ -#define EMAC_MMCCR_MCF ((rt_uint32_t)0x00000008) /* MMC Counter Freeze */ -#define EMAC_MMCCR_ROR ((rt_uint32_t)0x00000004) /* Reset on Read */ -#define EMAC_MMCCR_CSR ((rt_uint32_t)0x00000002) /* Counter Stop Rollover */ -#define EMAC_MMCCR_CR ((rt_uint32_t)0x00000001) /* Counters Reset */ - -/* Bit definition for Ethernet MMC Receive Interrupt Register */ -#define EMAC_MMCRIR_RGUFS ((rt_uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ -#define EMAC_MMCRIR_RFAES ((rt_uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ -#define EMAC_MMCRIR_RFCES ((rt_uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Register */ -#define EMAC_MMCTIR_TGFS ((rt_uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ -#define EMAC_MMCTIR_TGFMSCS ((rt_uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ -#define EMAC_MMCTIR_TGFSCS ((rt_uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ -#define EMAC_MMCRIMR_RGUFM ((rt_uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ -#define EMAC_MMCRIMR_RFAEM ((rt_uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ -#define EMAC_MMCRIMR_RFCEM ((rt_uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ -#define EMAC_MMCTIMR_TGFM ((rt_uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ -#define EMAC_MMCTIMR_TGFMSCM ((rt_uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ -#define EMAC_MMCTIMR_TGFSCM ((rt_uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ -#define EMAC_MMCTGFSCCR_TGFSCC ((rt_uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ -#define EMAC_MMCTGFMSCCR_TGFMSCC ((rt_uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ - -/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ -#define EMAC_MMCTGFCR_TGFC ((rt_uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ - -/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ -#define EMAC_MMCRFCECR_RFCEC ((rt_uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ - -/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */ -#define EMAC_MMCRFAECR_RFAEC ((rt_uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ - -/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ -#define EMAC_MMCRGUFCR_RGUFC ((rt_uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ - -/******************************************************************************/ -/* Ethernet PTP Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet PTP Time Stamp Control Register */ -#define EMAC_PTPTSCR_TSARU ((rt_uint32_t)0x00000020) /* Addend register update */ -#define EMAC_PTPTSCR_TSITE ((rt_uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ -#define EMAC_PTPTSCR_TSSTU ((rt_uint32_t)0x00000008) /* Time stamp update */ -#define EMAC_PTPTSCR_TSSTI ((rt_uint32_t)0x00000004) /* Time stamp initialize */ -#define EMAC_PTPTSCR_TSFCU ((rt_uint32_t)0x00000002) /* Time stamp fine or coarse update */ -#define EMAC_PTPTSCR_TSE ((rt_uint32_t)0x00000001) /* Time stamp enable */ - -/* Bit definition for Ethernet PTP Sub-Second Increment Register */ -#define EMAC_PTPSSIR_STSSI ((rt_uint32_t)0x000000FF) /* System time Sub-second increment value */ - -/* Bit definition for Ethernet PTP Time Stamp High Register */ -#define EMAC_PTPTSHR_STS ((rt_uint32_t)0xFFFFFFFF) /* System Time second */ - -/* Bit definition for Ethernet PTP Time Stamp Low Register */ -#define EMAC_PTPTSLR_STPNS ((rt_uint32_t)0x80000000) /* System Time Positive or negative time */ -#define EMAC_PTPTSLR_STSS ((rt_uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp High Update Register */ -#define EMAC_PTPTSHUR_TSUS ((rt_uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ -#define EMAC_PTPTSLUR_TSUPNS ((rt_uint32_t)0x80000000) /* Time stamp update Positive or negative time */ -#define EMAC_PTPTSLUR_TSUSS ((rt_uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ - -/* Bit definition for Ethernet PTP Time Stamp Addend Register */ -#define EMAC_PTPTSAR_TSA ((rt_uint32_t)0xFFFFFFFF) /* Time stamp addend */ - -/* Bit definition for Ethernet PTP Target Time High Register */ -#define EMAC_PTPTTHR_TTSH ((rt_uint32_t)0xFFFFFFFF) /* Target time stamp high */ - -/* Bit definition for Ethernet PTP Target Time Low Register */ -#define EMAC_PTPTTLR_TTSL ((rt_uint32_t)0xFFFFFFFF) /* Target time stamp low */ - -/******************************************************************************/ -/* Ethernet DMA Registers bits definition */ -/******************************************************************************/ - -/* Bit definition for Ethernet DMA Bus Mode Register */ -#define EMAC_DMABMR_AAB ((rt_uint32_t)0x02000000) /* Address-Aligned beats */ -#define EMAC_DMABMR_FPM ((rt_uint32_t)0x01000000) /* 4xPBL mode */ -#define EMAC_DMABMR_USP ((rt_uint32_t)0x00800000) /* Use separate PBL */ -#define EMAC_DMABMR_RDP ((rt_uint32_t)0x007E0000) /* RxDMA PBL */ -#define EMAC_DMABMR_RDP_1Beat ((rt_uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define EMAC_DMABMR_RDP_2Beat ((rt_uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define EMAC_DMABMR_RDP_4Beat ((rt_uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define EMAC_DMABMR_RDP_8Beat ((rt_uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define EMAC_DMABMR_RDP_16Beat ((rt_uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define EMAC_DMABMR_RDP_32Beat ((rt_uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define EMAC_DMABMR_RDP_4xPBL_4Beat ((rt_uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define EMAC_DMABMR_RDP_4xPBL_8Beat ((rt_uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define EMAC_DMABMR_RDP_4xPBL_16Beat ((rt_uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define EMAC_DMABMR_RDP_4xPBL_32Beat ((rt_uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define EMAC_DMABMR_RDP_4xPBL_64Beat ((rt_uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define EMAC_DMABMR_RDP_4xPBL_128Beat ((rt_uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ -#define EMAC_DMABMR_FB ((rt_uint32_t)0x00010000) /* Fixed Burst */ -#define EMAC_DMABMR_RTPR ((rt_uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define EMAC_DMABMR_RTPR_1_1 ((rt_uint32_t)0x00000000) /* Rx Tx priority ratio */ -#define EMAC_DMABMR_RTPR_2_1 ((rt_uint32_t)0x00004000) /* Rx Tx priority ratio */ -#define EMAC_DMABMR_RTPR_3_1 ((rt_uint32_t)0x00008000) /* Rx Tx priority ratio */ -#define EMAC_DMABMR_RTPR_4_1 ((rt_uint32_t)0x0000C000) /* Rx Tx priority ratio */ -#define EMAC_DMABMR_PBL ((rt_uint32_t)0x00003F00) /* Programmable burst length */ -#define EMAC_DMABMR_PBL_1Beat ((rt_uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define EMAC_DMABMR_PBL_2Beat ((rt_uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define EMAC_DMABMR_PBL_4Beat ((rt_uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define EMAC_DMABMR_PBL_8Beat ((rt_uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define EMAC_DMABMR_PBL_16Beat ((rt_uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define EMAC_DMABMR_PBL_32Beat ((rt_uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define EMAC_DMABMR_PBL_4xPBL_4Beat ((rt_uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define EMAC_DMABMR_PBL_4xPBL_8Beat ((rt_uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define EMAC_DMABMR_PBL_4xPBL_16Beat ((rt_uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define EMAC_DMABMR_PBL_4xPBL_32Beat ((rt_uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define EMAC_DMABMR_PBL_4xPBL_64Beat ((rt_uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define EMAC_DMABMR_PBL_4xPBL_128Beat ((rt_uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -#define EMAC_DMABMR_EDE ((rt_uint32_t)0x00000080) /* Enhanced Descriptor Enable */ -#define EMAC_DMABMR_DSL ((rt_uint32_t)0x0000007C) /* Descriptor Skip Length */ -#define EMAC_DMABMR_DA ((rt_uint32_t)0x00000002) /* DMA arbitration scheme */ -#define EMAC_DMABMR_SR ((rt_uint32_t)0x00000001) /* Software reset */ - -/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ -#define EMAC_DMATPDR_TPD ((rt_uint32_t)0xFFFFFFFF) /* Transmit poll demand */ - -/* Bit definition for Ethernet DMA Receive Poll Demand Register */ -#define EMAC_DMARPDR_RPD ((rt_uint32_t)0xFFFFFFFF) /* Receive poll demand */ - -/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ -#define EMAC_DMARDLAR_SRL ((rt_uint32_t)0xFFFFFFFF) /* Start of receive list */ - -/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ -#define EMAC_DMATDLAR_STL ((rt_uint32_t)0xFFFFFFFF) /* Start of transmit list */ - -/* Bit definition for Ethernet DMA Status Register */ -#define EMAC_DMASR_TSTS ((rt_uint32_t)0x20000000) /* Time-stamp trigger status */ -#define EMAC_DMASR_PMTS ((rt_uint32_t)0x10000000) /* PMT status */ -#define EMAC_DMASR_MMCS ((rt_uint32_t)0x08000000) /* MMC status */ -#define EMAC_DMASR_EBS ((rt_uint32_t)0x03800000) /* Error bits status */ -/* combination with EBS[2:0] for GetFlagStatus function */ -#define EMAC_DMASR_EBS_DescAccess ((rt_uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ -#define EMAC_DMASR_EBS_ReadTransf ((rt_uint32_t)0x01000000) /* Error bits 0-write transfer, 1-read transfer */ -#define EMAC_DMASR_EBS_DataTransfTx ((rt_uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define EMAC_DMASR_TPS ((rt_uint32_t)0x00700000) /* Transmit process state */ -#define EMAC_DMASR_TPS_Stopped ((rt_uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ -#define EMAC_DMASR_TPS_Fetching ((rt_uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ -#define EMAC_DMASR_TPS_Waiting ((rt_uint32_t)0x00200000) /* Running - waiting for status */ -#define EMAC_DMASR_TPS_Reading ((rt_uint32_t)0x00300000) /* Running - reading the data from host memory */ -#define EMAC_DMASR_TPS_Suspended ((rt_uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailable */ -#define EMAC_DMASR_TPS_Closing ((rt_uint32_t)0x00700000) /* Running - closing Rx descriptor */ -#define EMAC_DMASR_RPS ((rt_uint32_t)0x000E0000) /* Receive process state */ -#define EMAC_DMASR_RPS_Stopped ((rt_uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ -#define EMAC_DMASR_RPS_Fetching ((rt_uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ -#define EMAC_DMASR_RPS_Waiting ((rt_uint32_t)0x00060000) /* Running - waiting for packet */ -#define EMAC_DMASR_RPS_Suspended ((rt_uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ -#define EMAC_DMASR_RPS_Closing ((rt_uint32_t)0x000A0000) /* Running - closing descriptor */ -#define EMAC_DMASR_RPS_Queuing ((rt_uint32_t)0x000E0000) /* Running - queuing the receive frame into host memory */ -#define EMAC_DMASR_NIS ((rt_uint32_t)0x00010000) /* Normal interrupt summary */ -#define EMAC_DMASR_AIS ((rt_uint32_t)0x00008000) /* Abnormal interrupt summary */ -#define EMAC_DMASR_ERS ((rt_uint32_t)0x00004000) /* Early receive status */ -#define EMAC_DMASR_FBES ((rt_uint32_t)0x00002000) /* Fatal bus error status */ -#define EMAC_DMASR_ETS ((rt_uint32_t)0x00000400) /* Early transmit status */ -#define EMAC_DMASR_RWTS ((rt_uint32_t)0x00000200) /* Receive watchdog timeout status */ -#define EMAC_DMASR_RPSS ((rt_uint32_t)0x00000100) /* Receive process stopped status */ -#define EMAC_DMASR_RBUS ((rt_uint32_t)0x00000080) /* Receive buffer unavailable status */ -#define EMAC_DMASR_RS ((rt_uint32_t)0x00000040) /* Receive status */ -#define EMAC_DMASR_TUS ((rt_uint32_t)0x00000020) /* Transmit underflow status */ -#define EMAC_DMASR_ROS ((rt_uint32_t)0x00000010) /* Receive overflow status */ -#define EMAC_DMASR_TJTS ((rt_uint32_t)0x00000008) /* Transmit jabber timeout status */ -#define EMAC_DMASR_TBUS ((rt_uint32_t)0x00000004) /* Transmit buffer unavailable status */ -#define EMAC_DMASR_TPSS ((rt_uint32_t)0x00000002) /* Transmit process stopped status */ -#define EMAC_DMASR_TS ((rt_uint32_t)0x00000001) /* Transmit status */ - -/* Bit definition for Ethernet DMA Operation Mode Register */ -#define EMAC_DMAOMR_DTCEFD ((rt_uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ -#define EMAC_DMAOMR_RSF ((rt_uint32_t)0x02000000) /* Receive store and forward */ -#define EMAC_DMAOMR_DFRF ((rt_uint32_t)0x01000000) /* Disable flushing of received frames */ -#define EMAC_DMAOMR_TSF ((rt_uint32_t)0x00200000) /* Transmit store and forward */ -#define EMAC_DMAOMR_FTF ((rt_uint32_t)0x00100000) /* Flush transmit FIFO */ -#define EMAC_DMAOMR_TTC ((rt_uint32_t)0x0001C000) /* Transmit threshold control */ -#define EMAC_DMAOMR_TTC_64Bytes ((rt_uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define EMAC_DMAOMR_TTC_128Bytes ((rt_uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define EMAC_DMAOMR_TTC_192Bytes ((rt_uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define EMAC_DMAOMR_TTC_256Bytes ((rt_uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define EMAC_DMAOMR_TTC_40Bytes ((rt_uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define EMAC_DMAOMR_TTC_32Bytes ((rt_uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define EMAC_DMAOMR_TTC_24Bytes ((rt_uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define EMAC_DMAOMR_TTC_16Bytes ((rt_uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ -#define EMAC_DMAOMR_ST ((rt_uint32_t)0x00002000) /* Start/stop transmission command */ -#define EMAC_DMAOMR_FEF ((rt_uint32_t)0x00000080) /* Forward error frames */ -#define EMAC_DMAOMR_FUGF ((rt_uint32_t)0x00000040) /* Forward undersized good frames */ -#define EMAC_DMAOMR_RTC ((rt_uint32_t)0x00000018) /* receive threshold control */ -#define EMAC_DMAOMR_RTC_64Bytes ((rt_uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ -#define EMAC_DMAOMR_RTC_32Bytes ((rt_uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ -#define EMAC_DMAOMR_RTC_96Bytes ((rt_uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ -#define EMAC_DMAOMR_RTC_128Bytes ((rt_uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ -#define EMAC_DMAOMR_OSF ((rt_uint32_t)0x00000004) /* operate on second frame */ -#define EMAC_DMAOMR_SR ((rt_uint32_t)0x00000002) /* Start/stop receive */ - -/* Bit definition for Ethernet DMA Interrupt Enable Register */ -#define EMAC_DMAIER_NISE ((rt_uint32_t)0x00010000) /* Normal interrupt summary enable */ -#define EMAC_DMAIER_AISE ((rt_uint32_t)0x00008000) /* Abnormal interrupt summary enable */ -#define EMAC_DMAIER_ERIE ((rt_uint32_t)0x00004000) /* Early receive interrupt enable */ -#define EMAC_DMAIER_FBEIE ((rt_uint32_t)0x00002000) /* Fatal bus error interrupt enable */ -#define EMAC_DMAIER_ETIE ((rt_uint32_t)0x00000400) /* Early transmit interrupt enable */ -#define EMAC_DMAIER_RWTIE ((rt_uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ -#define EMAC_DMAIER_RPSIE ((rt_uint32_t)0x00000100) /* Receive process stopped interrupt enable */ -#define EMAC_DMAIER_RBUIE ((rt_uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ -#define EMAC_DMAIER_RIE ((rt_uint32_t)0x00000040) /* Receive interrupt enable */ -#define EMAC_DMAIER_TUIE ((rt_uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ -#define EMAC_DMAIER_ROIE ((rt_uint32_t)0x00000010) /* Receive Overflow interrupt enable */ -#define EMAC_DMAIER_TJTIE ((rt_uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ -#define EMAC_DMAIER_TBUIE ((rt_uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ -#define EMAC_DMAIER_TPSIE ((rt_uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ -#define EMAC_DMAIER_TIE ((rt_uint32_t)0x00000001) /* Transmit interrupt enable */ - -/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ -#define EMAC_DMAMFBOCR_OFOC ((rt_uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define EMAC_DMAMFBOCR_MFA ((rt_uint32_t)0x0FFE0000) /* Number of frames missed by the application */ -#define EMAC_DMAMFBOCR_OMFC ((rt_uint32_t)0x00010000) /* Overflow bit for missed frame counter */ -#define EMAC_DMAMFBOCR_MFC ((rt_uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ - -/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ -#define EMAC_DMACHTDR_HTDAP ((rt_uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ -#define EMAC_DMACHRDR_HRDAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ - -/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ -#define EMAC_DMACHTBAR_HTBAP ((rt_uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ - -/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ -#define EMAC_DMACHRBAR_HRBAP ((rt_uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ - -//typedef enum { -// RESET = 0, SET = !RESET -//} FlagStatus, ITStatus; -//typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; - -/** - * ETH MAC Init structure definition - */ -typedef struct -{ - /** - * MAC - */ - rt_uint32_t EMAC_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref EMAC_AutoNegotiation */ - - rt_uint32_t EMAC_Watchdog; /* Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref EMAC_watchdog */ - - rt_uint32_t EMAC_Jabber; /* Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref EMAC_Jabber */ - - rt_uint32_t EMAC_InterFrameGap; /* Selects the minimum IFG between frames during transmission - This parameter can be a value of @ref EMAC_Inter_Frame_Gap */ - - rt_uint32_t EMAC_CarrierSense; /* Selects or not the Carrier Sense - This parameter can be a value of @ref EMAC_Carrier_Sense */ - - rt_uint32_t EMAC_Speed; /* Sets the Ethernet speed: 10/100 Mbps - This parameter can be a value of @ref EMAC_Speed */ - - rt_uint32_t EMAC_ReceiveOwn; /* Selects or not the ReceiveOwn - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode - This parameter can be a value of @ref EMAC_Receive_Own */ - - rt_uint32_t EMAC_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode - This parameter can be a value of @ref EMAC_Loop_Back_Mode */ - - rt_uint32_t EMAC_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref EMAC_Duplex_Mode */ - - rt_uint32_t EMAC_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref EMAC_Checksum_Offload */ - - rt_uint32_t EMAC_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a colision occurs (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Retry_Transmission */ - - rt_uint32_t EMAC_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping - This parameter can be a value of @ref EMAC_Automatic_Pad_CRC_Strip */ - - rt_uint32_t EMAC_BackOffLimit; /* Selects the BackOff limit value - This parameter can be a value of @ref EMAC_Back_Off_Limit */ - - rt_uint32_t EMAC_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Deferral_Check */ - - rt_uint32_t EMAC_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) - This parameter can be a value of @ref EMAC_Receive_All */ - - rt_uint32_t EMAC_SourceAddrFilter; /* Selects the Source Address Filter mode - This parameter can be a value of @ref EMAC_Source_Addr_Filter */ - - rt_uint32_t EMAC_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref EMAC_Pass_Control_Frames */ - - rt_uint32_t EMAC_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames - This parameter can be a value of @ref EMAC_Broadcast_Frames_Reception */ - - rt_uint32_t EMAC_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames - This parameter can be a value of @ref EMAC_Destination_Addr_Filter */ - - rt_uint32_t EMAC_PromiscuousMode; /* Selects or not the Promiscuous Mode - This parameter can be a value of @ref EMAC_Promiscuous_Mode */ - - rt_uint32_t EMAC_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref EMAC_Multicast_Frames_Filter */ - - rt_uint32_t EMAC_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter - This parameter can be a value of @ref EMAC_Unicast_Frames_Filter */ - - rt_uint32_t EMAC_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ - - rt_uint32_t EMAC_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ - - rt_uint32_t EMAC_PauseTime; /* This field holds the value to be used in the Pause Time field in the - transmit control frame */ - - rt_uint32_t EMAC_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames - This parameter can be a value of @ref EMAC_Zero_Quanta_Pause */ - - rt_uint32_t EMAC_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame - This parameter can be a value of @ref EMAC_Pause_Low_Threshold */ - - rt_uint32_t EMAC_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address) - This parameter can be a value of @ref EMAC_Unicast_Pause_Frame_Detect */ - - rt_uint32_t EMAC_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref EMAC_Receive_Flow_Control */ - - rt_uint32_t EMAC_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref EMAC_Transmit_Flow_Control */ - - rt_uint32_t EMAC_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering - This parameter can be a value of @ref EMAC_VLAN_Tag_Comparison */ - - rt_uint32_t EMAC_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ - - /** - * DMA - */ - - rt_uint32_t EMAC_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames - This parameter can be a value of @ref EMAC_Drop_TCP_IP_Checksum_Error_Frame */ - - rt_uint32_t EMAC_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode - This parameter can be a value of @ref EMAC_Receive_Store_Forward */ - - rt_uint32_t EMAC_FlushReceivedFrame; /* Enables or disables the flushing of received frames - This parameter can be a value of @ref EMAC_Flush_Received_Frame */ - - rt_uint32_t EMAC_TransmitStoreForward; /* Enables or disables Transmit store and forward mode - This parameter can be a value of @ref EMAC_Transmit_Store_Forward */ - - rt_uint32_t EMAC_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control - This parameter can be a value of @ref EMAC_Transmit_Threshold_Control */ - - rt_uint32_t EMAC_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames - This parameter can be a value of @ref EMAC_Forward_Error_Frames */ - - rt_uint32_t EMAC_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref EMAC_Forward_Undersized_Good_Frames */ - - rt_uint32_t EMAC_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO - This parameter can be a value of @ref EMAC_Receive_Threshold_Control */ - - rt_uint32_t EMAC_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref EMAC_Second_Frame_Operate */ - - rt_uint32_t EMAC_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats - This parameter can be a value of @ref EMAC_Address_Aligned_Beats */ - - rt_uint32_t EMAC_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers - This parameter can be a value of @ref EMAC_Fixed_Burst */ - - rt_uint32_t EMAC_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction - This parameter can be a value of @ref EMAC_Rx_DMA_Burst_Length */ - - rt_uint32_t EMAC_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction - This parameter can be a value of @ref EMAC_Tx_DMA_Burst_Length */ - - rt_uint32_t EMAC_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained int (Ring mode) */ - - rt_uint32_t EMAC_DMAArbitration; /* Selects the DMA Tx/Rx arbitration - This parameter can be a value of @ref EMAC_DMA_Arbitration */ -} EMAC_InitTypeDef; - -/**--------------------------------------------------------------------------**/ -/** - * DMA int types - */ -/**--------------------------------------------------------------------------**/ - -/** - * ETH DMA Descriptors data structure definition - */ -typedef struct -{ - rt_uint32_t Status; /* Status */ - rt_uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ - rt_uint32_t Buffer1Addr; /* Buffer1 address pointer */ - rt_uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ -} EMAC_DMADESCTypeDef; - -/**--------------------------------------------------------------------------**/ -/** - * ETH Frames defines - */ -/**--------------------------------------------------------------------------**/ - -#define EMAC_MAX_PACKET_SIZE 1520 /* EMAC_HEADER + EMAC_EXTRA + MAX_EMAC_PAYLOAD + EMAC_CRC */ -#define EMAC_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define EMAC_CRC 4 /* Ethernet CRC */ -#define EMAC_EXTRA 2 /* Extra bytes in some cases */ -#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ -#define MIN_EMAC_PAYLOAD 46 /* Minimum Ethernet payload size */ -#define MAX_EMAC_PAYLOAD 1500 /* Maximum Ethernet payload size */ -#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ - -/**--------------------------------------------------------------------------**/ -/** - * Ethernet DMA int registers bits definition - */ -/**--------------------------------------------------------------------------**/ - -#define EMAC_DMATxDesc_OWN ((rt_uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ -#define EMAC_DMATxDesc_IC ((rt_uint32_t)0x40000000) /* Interrupt on Completion */ -#define EMAC_DMATxDesc_LS ((rt_uint32_t)0x20000000) /* Last Segment */ -#define EMAC_DMATxDesc_FS ((rt_uint32_t)0x10000000) /* First Segment */ -#define EMAC_DMATxDesc_DC ((rt_uint32_t)0x08000000) /* Disable CRC */ -#define EMAC_DMATxDesc_DP ((rt_uint32_t)0x04000000) /* Disable Padding */ -#define EMAC_DMATxDesc_TTSE ((rt_uint32_t)0x02000000) /* Transmit Time Stamp Enable */ -#define EMAC_DMATxDesc_CIC ((rt_uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ -#define EMAC_DMATxDesc_CIC_ByPass ((rt_uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ -#define EMAC_DMATxDesc_CIC_IPV4Header ((rt_uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ -#define EMAC_DMATxDesc_CIC_TCPUDPICMP_Segment ((rt_uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define EMAC_DMATxDesc_CIC_TCPUDPICMP_Full ((rt_uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define EMAC_DMATxDesc_TER ((rt_uint32_t)0x00200000) /* Transmit End of Ring */ -#define EMAC_DMATxDesc_TCH ((rt_uint32_t)0x00100000) /* Second Address Chained */ -#define EMAC_DMATxDesc_TTSS ((rt_uint32_t)0x00020000) /* Tx Time Stamp Status */ -#define EMAC_DMATxDesc_IHE ((rt_uint32_t)0x00010000) /* IP Header Error */ -#define EMAC_DMATxDesc_ES ((rt_uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define EMAC_DMATxDesc_JT ((rt_uint32_t)0x00004000) /* Jabber Timeout */ -#define EMAC_DMATxDesc_FF ((rt_uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define EMAC_DMATxDesc_PCE ((rt_uint32_t)0x00001000) /* Payload Checksum Error */ -#define EMAC_DMATxDesc_LCA ((rt_uint32_t)0x00000800) /* Loss of Carrier: carrier lost during transmission */ -#define EMAC_DMATxDesc_NC ((rt_uint32_t)0x00000400) /* No Carrier: no carrier signal from the transceiver */ -#define EMAC_DMATxDesc_LCO ((rt_uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ -#define EMAC_DMATxDesc_EC ((rt_uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ -#define EMAC_DMATxDesc_VF ((rt_uint32_t)0x00000080) /* VLAN Frame */ -#define EMAC_DMATxDesc_CC ((rt_uint32_t)0x00000078) /* Collision Count */ -#define EMAC_DMATxDesc_ED ((rt_uint32_t)0x00000004) /* Excessive Deferral */ -#define EMAC_DMATxDesc_UF ((rt_uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ -#define EMAC_DMATxDesc_DB ((rt_uint32_t)0x00000001) /* Deferred Bit */ - -#define EMAC_DMATxDesc_TBS2 ((rt_uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ -#define EMAC_DMATxDesc_TBS1 ((rt_uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ - -#define EMAC_DMATxDesc_B1AP ((rt_uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ - -#define EMAC_DMATxDesc_B2AP ((rt_uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ - -#define EMAC_DMARxDesc_OWN ((rt_uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ -#define EMAC_DMARxDesc_AFM ((rt_uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ -#define EMAC_DMARxDesc_FL ((rt_uint32_t)0x3FFF0000) /* Receive descriptor frame length */ -#define EMAC_DMARxDesc_ES ((rt_uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define EMAC_DMARxDesc_DE ((rt_uint32_t)0x00004000) /* Descriptor error: no more int for receive frame */ -#define EMAC_DMARxDesc_SAF ((rt_uint32_t)0x00002000) /* SA Filter Fail for the received frame */ -#define EMAC_DMARxDesc_LE ((rt_uint32_t)0x00001000) /* Frame size not matching with length field */ -#define EMAC_DMARxDesc_OE ((rt_uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ -#define EMAC_DMARxDesc_VLAN ((rt_uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ -#define EMAC_DMARxDesc_FS ((rt_uint32_t)0x00000200) /* First descriptor of the frame */ -#define EMAC_DMARxDesc_LS ((rt_uint32_t)0x00000100) /* Last descriptor of the frame */ -#define EMAC_DMARxDesc_IPV4HCE ((rt_uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ -#define EMAC_DMARxDesc_LC ((rt_uint32_t)0x00000040) /* Late collision occurred during reception */ -#define EMAC_DMARxDesc_FT ((rt_uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ -#define EMAC_DMARxDesc_RWT ((rt_uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ -#define EMAC_DMARxDesc_RE ((rt_uint32_t)0x00000008) /* Receive error: error reported by MII interface */ -#define EMAC_DMARxDesc_DBE ((rt_uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ -#define EMAC_DMARxDesc_CE ((rt_uint32_t)0x00000002) /* CRC error */ -#define EMAC_DMARxDesc_MAMPCE ((rt_uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -#define EMAC_DMARxDesc_DIC ((rt_uint32_t)0x80000000) /* Disable Interrupt on Completion */ -#define EMAC_DMARxDesc_RBS2 ((rt_uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ -#define EMAC_DMARxDesc_RER ((rt_uint32_t)0x00008000) /* Receive End of Ring */ -#define EMAC_DMARxDesc_RCH ((rt_uint32_t)0x00004000) /* Second Address Chained */ -#define EMAC_DMARxDesc_RBS1 ((rt_uint32_t)0x00001FFF) /* Receive Buffer1 Size */ - -#define EMAC_DMARxDesc_B1AP ((rt_uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ - -#define EMAC_DMARxDesc_B2AP ((rt_uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ - -#define PHY_READ_TO ((rt_uint32_t)0x0004FFFF) -#define PHY_WRITE_TO ((rt_uint32_t)0x0004FFFF) - -#define PHY_ResetDelay ((rt_uint32_t)0x000FFFFF) - -#define PHY_ConfigDelay ((rt_uint32_t)0x00FFFFFF) - -#define PHY_BCR 0 /* Tranceiver Basic Control Register */ -#define PHY_BSR 1 /* Tranceiver Basic Status Register */ - -#define PHY_Reset ((rt_uint16_t)0x8000) /* PHY Reset */ -//#define PHY_Loopback ((rt_uint16_t)0x4000) /* Select loop-back mode */ -//#define PHY_FULLDUPLEX_100M ((rt_uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ -//#define PHY_HALFDUPLEX_100M ((rt_uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ -//#define PHY_FULLDUPLEX_10M ((rt_uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ -//#define PHY_HALFDUPLEX_10M ((rt_uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ -//#define PHY_AutoNegotiation ((rt_uint16_t)0x1000) /* Enable auto-negotiation function */ -//#define PHY_Restart_AutoNegotiation ((rt_uint16_t)0x0200) /* Restart auto-negotiation function */ -//#define PHY_Powerdown ((rt_uint16_t)0x0800) /* Select the power down mode */ -//#define PHY_Isolate ((rt_uint16_t)0x0400) /* Isolate PHY from MII */ -// -//#define PHY_AutoNego_Complete ((rt_uint16_t)0x0020) /* Auto-Negotiation process completed */ -//#define PHY_Linked_Status ((rt_uint16_t)0x0004) /* Valid link established */ -//#define PHY_Jabber_detection ((rt_uint16_t)0x0002) /* Jabber condition detected */ -// -//#define PHY_SR 16 /* Transceiver Status Register */ -// -//#define PHY_Speed_Status ((rt_uint16_t)0x0002) /* Configured information of Speed: 10Mbps */ -//#define PHY_Duplex_Status ((rt_uint16_t)0x0004) /* Configured information of Duplex: Full-duplex */ - -#define EMAC_AutoNegotiation_Enable ((rt_uint32_t)0x00000001) -#define EMAC_AutoNegotiation_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_Watchdog_Enable ((rt_uint32_t)0x00000000) -#define EMAC_Watchdog_Disable ((rt_uint32_t)0x00800000) - -#define EMAC_Jabber_Enable ((rt_uint32_t)0x00000000) -#define EMAC_Jabber_Disable ((rt_uint32_t)0x00400000) - -#define EMAC_InterFrameGap_96Bit ((rt_uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ -#define EMAC_InterFrameGap_88Bit ((rt_uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ -#define EMAC_InterFrameGap_80Bit ((rt_uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ -#define EMAC_InterFrameGap_72Bit ((rt_uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ -#define EMAC_InterFrameGap_64Bit ((rt_uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ -#define EMAC_InterFrameGap_56Bit ((rt_uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ -#define EMAC_InterFrameGap_48Bit ((rt_uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ -#define EMAC_InterFrameGap_40Bit ((rt_uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ - -#define EMAC_CarrierSense_Enable ((rt_uint32_t)0x00000000) -#define EMAC_CarrierSense_Disable ((rt_uint32_t)0x00010000) - -#define EMAC_Speed_10M ((rt_uint32_t)0x00000000) -#define EMAC_Speed_100M ((rt_uint32_t)0x00004000) - -#define EMAC_ReceiveOwn_Enable ((rt_uint32_t)0x00000000) -#define EMAC_ReceiveOwn_Disable ((rt_uint32_t)0x00002000) - -#define EMAC_LoopbackMode_Enable ((rt_uint32_t)0x00001000) -#define EMAC_LoopbackMode_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_Mode_FullDuplex ((rt_uint32_t)0x00000800) -#define EMAC_Mode_HalfDuplex ((rt_uint32_t)0x00000000) - -#define EMAC_ChecksumOffload_Enable ((rt_uint32_t)0x00000400) -#define EMAC_ChecksumOffload_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_RetryTransmission_Enable ((rt_uint32_t)0x00000000) -#define EMAC_RetryTransmission_Disable ((rt_uint32_t)0x00000200) - -#define EMAC_AutomaticPadCRCStrip_Enable ((rt_uint32_t)0x00000080) -#define EMAC_AutomaticPadCRCStrip_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_BackOffLimit_10 ((rt_uint32_t)0x00000000) -#define EMAC_BackOffLimit_8 ((rt_uint32_t)0x00000020) -#define EMAC_BackOffLimit_4 ((rt_uint32_t)0x00000040) -#define EMAC_BackOffLimit_1 ((rt_uint32_t)0x00000060) - -#define EMAC_DeferralCheck_Enable ((rt_uint32_t)0x00000010) -#define EMAC_DeferralCheck_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_ReceiveAll_Enable ((rt_uint32_t)0x80000000) -#define EMAC_ReceiveAll_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_SourceAddrFilter_Normal_Enable ((rt_uint32_t)0x00000200) -#define EMAC_SourceAddrFilter_Inverse_Enable ((rt_uint32_t)0x00000300) -#define EMAC_SourceAddrFilter_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_PassControlFrames_BlockAll ((rt_uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ -#define EMAC_PassControlFrames_ForwardAll ((rt_uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ -#define EMAC_PassControlFrames_ForwardPassedAddrFilter ((rt_uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ - -#define EMAC_BroadcastFramesReception_Enable ((rt_uint32_t)0x00000000) -#define EMAC_BroadcastFramesReception_Disable ((rt_uint32_t)0x00000020) - -#define EMAC_DestinationAddrFilter_Normal ((rt_uint32_t)0x00000000) -#define EMAC_DestinationAddrFilter_Inverse ((rt_uint32_t)0x00000008) - -#define EMAC_PromiscuousMode_Enable ((rt_uint32_t)0x00000001) -#define EMAC_PromiscuousMode_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_MulticastFramesFilter_PerfectHashTable ((rt_uint32_t)0x00000404) -#define EMAC_MulticastFramesFilter_HashTable ((rt_uint32_t)0x00000004) -#define EMAC_MulticastFramesFilter_Perfect ((rt_uint32_t)0x00000000) -#define EMAC_MulticastFramesFilter_None ((rt_uint32_t)0x00000010) - -#define EMAC_UnicastFramesFilter_PerfectHashTable ((rt_uint32_t)0x00000402) -#define EMAC_UnicastFramesFilter_HashTable ((rt_uint32_t)0x00000002) -#define EMAC_UnicastFramesFilter_Perfect ((rt_uint32_t)0x00000000) - -#define EMAC_ZeroQuantaPause_Enable ((rt_uint32_t)0x00000000) -#define EMAC_ZeroQuantaPause_Disable ((rt_uint32_t)0x00000080) - -#define EMAC_PauseLowThreshold_Minus4 ((rt_uint32_t)0x00000000) /* Pause time minus 4 slot times */ -#define EMAC_PauseLowThreshold_Minus28 ((rt_uint32_t)0x00000010) /* Pause time minus 28 slot times */ -#define EMAC_PauseLowThreshold_Minus144 ((rt_uint32_t)0x00000020) /* Pause time minus 144 slot times */ -#define EMAC_PauseLowThreshold_Minus256 ((rt_uint32_t)0x00000030) /* Pause time minus 256 slot times */ - -#define EMAC_UnicastPauseFrameDetect_Enable ((rt_uint32_t)0x00000008) -#define EMAC_UnicastPauseFrameDetect_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_ReceiveFlowControl_Enable ((rt_uint32_t)0x00000004) -#define EMAC_ReceiveFlowControl_Disable ((rt_uint32_t)0x00000000) -#define EMAC_TransmitFlowControl_Enable ((rt_uint32_t)0x00000002) -#define EMAC_TransmitFlowControl_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_VLANTagComparison_12Bit ((rt_uint32_t)0x00010000) -#define EMAC_VLANTagComparison_16Bit ((rt_uint32_t)0x00000000) - -#define EMAC_MAC_FLAG_TST ((rt_uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ -#define EMAC_MAC_FLAG_MMCT ((rt_uint32_t)0x00000040) /* MMC transmit flag */ -#define EMAC_MAC_FLAG_MMCR ((rt_uint32_t)0x00000020) /* MMC receive flag */ -#define EMAC_MAC_FLAG_MMC ((rt_uint32_t)0x00000010) /* MMC flag (on MAC) */ -#define EMAC_MAC_FLAG_PMT ((rt_uint32_t)0x00000008) /* PMT flag (on MAC) */ - -#define EMAC_MAC_IT_TST ((rt_uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ -#define EMAC_MAC_IT_MMCT ((rt_uint32_t)0x00000040) /* MMC transmit interrupt */ -#define EMAC_MAC_IT_MMCR ((rt_uint32_t)0x00000020) /* MMC receive interrupt */ -#define EMAC_MAC_IT_MMC ((rt_uint32_t)0x00000010) /* MMC interrupt (on MAC) */ -#define EMAC_MAC_IT_PMT ((rt_uint32_t)0x00000008) /* PMT interrupt (on MAC) */ - -#define EMAC_MAC_Address0 ((rt_uint32_t)0x00000000) -#define EMAC_MAC_Address1 ((rt_uint32_t)0x00000008) -#define EMAC_MAC_Address2 ((rt_uint32_t)0x00000010) -#define EMAC_MAC_Address3 ((rt_uint32_t)0x00000018) - -#define EMAC_MAC_AddressFilter_SA ((rt_uint32_t)0x00000000) -#define EMAC_MAC_AddressFilter_DA ((rt_uint32_t)0x00000008) - -#define EMAC_MAC_AddressMask_Byte6 ((rt_uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define EMAC_MAC_AddressMask_Byte5 ((rt_uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define EMAC_MAC_AddressMask_Byte4 ((rt_uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define EMAC_MAC_AddressMask_Byte3 ((rt_uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define EMAC_MAC_AddressMask_Byte2 ((rt_uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define EMAC_MAC_AddressMask_Byte1 ((rt_uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ - -#define EMAC_DMATxDesc_LastSegment ((rt_uint32_t)0x40000000) /* Last Segment */ -#define EMAC_DMATxDesc_FirstSegment ((rt_uint32_t)0x20000000) /* First Segment */ - -#define EMAC_DMATxDesc_ChecksumByPass ((rt_uint32_t)0x00000000) /* Checksum engine bypass */ -#define EMAC_DMATxDesc_ChecksumIPV4Header ((rt_uint32_t)0x00400000) /* IPv4 header checksum insertion */ -#define EMAC_DMATxDesc_ChecksumTCPUDPICMPSegment ((rt_uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define EMAC_DMATxDesc_ChecksumTCPUDPICMPFull ((rt_uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ - -#define EMAC_DMARxDesc_Buffer1 ((rt_uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ -#define EMAC_DMARxDesc_Buffer2 ((rt_uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ - -#define EMAC_DropTCPIPChecksumErrorFrame_Enable ((rt_uint32_t)0x00000000) -#define EMAC_DropTCPIPChecksumErrorFrame_Disable ((rt_uint32_t)0x04000000) - -#define EMAC_ReceiveStoreForward_Enable ((rt_uint32_t)0x02000000) -#define EMAC_ReceiveStoreForward_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_FlushReceivedFrame_Enable ((rt_uint32_t)0x00000000) -#define EMAC_FlushReceivedFrame_Disable ((rt_uint32_t)0x01000000) - -#define EMAC_TransmitStoreForward_Enable ((rt_uint32_t)0x00200000) -#define EMAC_TransmitStoreForward_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_TransmitThresholdControl_64Bytes ((rt_uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define EMAC_TransmitThresholdControl_128Bytes ((rt_uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define EMAC_TransmitThresholdControl_192Bytes ((rt_uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define EMAC_TransmitThresholdControl_256Bytes ((rt_uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define EMAC_TransmitThresholdControl_40Bytes ((rt_uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define EMAC_TransmitThresholdControl_32Bytes ((rt_uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define EMAC_TransmitThresholdControl_24Bytes ((rt_uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define EMAC_TransmitThresholdControl_16Bytes ((rt_uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ - -#define EMAC_ForwardErrorFrames_Enable ((rt_uint32_t)0x00000080) -#define EMAC_ForwardErrorFrames_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_ForwardUndersizedGoodFrames_Enable ((rt_uint32_t)0x00000040) -#define EMAC_ForwardUndersizedGoodFrames_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_ReceiveThresholdControl_64Bytes ((rt_uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ -#define EMAC_ReceiveThresholdControl_32Bytes ((rt_uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ -#define EMAC_ReceiveThresholdControl_96Bytes ((rt_uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ -#define EMAC_ReceiveThresholdControl_128Bytes ((rt_uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ - -#define EMAC_SecondFrameOperate_Enable ((rt_uint32_t)0x00000004) -#define EMAC_SecondFrameOperate_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_AddressAlignedBeats_Enable ((rt_uint32_t)0x02000000) -#define EMAC_AddressAlignedBeats_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_FixedBurst_Enable ((rt_uint32_t)0x00010000) -#define EMAC_FixedBurst_Disable ((rt_uint32_t)0x00000000) - -#define EMAC_RxDMABurstLength_1Beat ((rt_uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define EMAC_RxDMABurstLength_2Beat ((rt_uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define EMAC_RxDMABurstLength_4Beat ((rt_uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define EMAC_RxDMABurstLength_8Beat ((rt_uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define EMAC_RxDMABurstLength_16Beat ((rt_uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define EMAC_RxDMABurstLength_32Beat ((rt_uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define EMAC_RxDMABurstLength_4xPBL_4Beat ((rt_uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define EMAC_RxDMABurstLength_4xPBL_8Beat ((rt_uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define EMAC_RxDMABurstLength_4xPBL_16Beat ((rt_uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define EMAC_RxDMABurstLength_4xPBL_32Beat ((rt_uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define EMAC_RxDMABurstLength_4xPBL_64Beat ((rt_uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define EMAC_RxDMABurstLength_4xPBL_128Beat ((rt_uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ - -#define EMAC_TxDMABurstLength_1Beat ((rt_uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define EMAC_TxDMABurstLength_2Beat ((rt_uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define EMAC_TxDMABurstLength_4Beat ((rt_uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define EMAC_TxDMABurstLength_8Beat ((rt_uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define EMAC_TxDMABurstLength_16Beat ((rt_uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define EMAC_TxDMABurstLength_32Beat ((rt_uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define EMAC_TxDMABurstLength_4xPBL_4Beat ((rt_uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define EMAC_TxDMABurstLength_4xPBL_8Beat ((rt_uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define EMAC_TxDMABurstLength_4xPBL_16Beat ((rt_uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define EMAC_TxDMABurstLength_4xPBL_32Beat ((rt_uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define EMAC_TxDMABurstLength_4xPBL_64Beat ((rt_uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define EMAC_TxDMABurstLength_4xPBL_128Beat ((rt_uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ - -#define EMAC_DMAArbitration_RoundRobin_RxTx_1_1 ((rt_uint32_t)0x00000000) -#define EMAC_DMAArbitration_RoundRobin_RxTx_2_1 ((rt_uint32_t)0x00004000) -#define EMAC_DMAArbitration_RoundRobin_RxTx_3_1 ((rt_uint32_t)0x00008000) -#define EMAC_DMAArbitration_RoundRobin_RxTx_4_1 ((rt_uint32_t)0x0000C000) -#define EMAC_DMAArbitration_RxPriorTx ((rt_uint32_t)0x00000002) - -#define EMAC_DMA_FLAG_TST ((rt_uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ -#define EMAC_DMA_FLAG_PMT ((rt_uint32_t)0x10000000) /* PMT interrupt (on DMA) */ -#define EMAC_DMA_FLAG_MMC ((rt_uint32_t)0x08000000) /* MMC interrupt (on DMA) */ -#define EMAC_DMA_FLAG_DataTransferError ((rt_uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ -#define EMAC_DMA_FLAG_ReadWriteError ((rt_uint32_t)0x01000000) /* Error bits 0-write transfer, 1-read transfer */ -#define EMAC_DMA_FLAG_AccessError ((rt_uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ -#define EMAC_DMA_FLAG_NIS ((rt_uint32_t)0x00010000) /* Normal interrupt summary flag */ -#define EMAC_DMA_FLAG_AIS ((rt_uint32_t)0x00008000) /* Abnormal interrupt summary flag */ -#define EMAC_DMA_FLAG_ER ((rt_uint32_t)0x00004000) /* Early receive flag */ -#define EMAC_DMA_FLAG_FBE ((rt_uint32_t)0x00002000) /* Fatal bus error flag */ -#define EMAC_DMA_FLAG_ET ((rt_uint32_t)0x00000400) /* Early transmit flag */ -#define EMAC_DMA_FLAG_RWT ((rt_uint32_t)0x00000200) /* Receive watchdog timeout flag */ -#define EMAC_DMA_FLAG_RPS ((rt_uint32_t)0x00000100) /* Receive process stopped flag */ -#define EMAC_DMA_FLAG_RBU ((rt_uint32_t)0x00000080) /* Receive buffer unavailable flag */ -#define EMAC_DMA_FLAG_R ((rt_uint32_t)0x00000040) /* Receive flag */ -#define EMAC_DMA_FLAG_TU ((rt_uint32_t)0x00000020) /* Underflow flag */ -#define EMAC_DMA_FLAG_RO ((rt_uint32_t)0x00000010) /* Overflow flag */ -#define EMAC_DMA_FLAG_TJT ((rt_uint32_t)0x00000008) /* Transmit jabber timeout flag */ -#define EMAC_DMA_FLAG_TBU ((rt_uint32_t)0x00000004) /* Transmit buffer unavailable flag */ -#define EMAC_DMA_FLAG_TPS ((rt_uint32_t)0x00000002) /* Transmit process stopped flag */ -#define EMAC_DMA_FLAG_T ((rt_uint32_t)0x00000001) /* Transmit flag */ - -#define EMAC_DMA_INT_GLPII ((rt_uint32_t)(1UL<<30)) /* GMAC LPI Interrupt. */ -#define EMAC_DMA_INT_TTI ((rt_uint32_t)(1UL<<29)) /* Time-Stamp Trigger Interrupt. */ -#define EMAC_DMA_INT_GPI ((rt_uint32_t)(1UL<<28)) /* GMAC PMT Interrupt. */ -#define EMAC_DMA_INT_GMI ((rt_uint32_t)(1UL<<27)) /* GMAC MMC Interrupt. */ -#define EMAC_DMA_INT_GLI ((rt_uint32_t)(1UL<<26)) /* GMAC Line interface Interrupt. */ -#define EMAC_DMA_INT_NIS ((rt_uint32_t)(1UL<<16)) /* Normal interrupt summary. */ -#define EMAC_DMA_INT_AIS ((rt_uint32_t)(1UL<<15)) /* Abnormal interrupt summary. */ -#define EMAC_DMA_INT_ER ((rt_uint32_t)0x00004000) /* Early receive interrupt */ -#define EMAC_DMA_INT_FBE ((rt_uint32_t)0x00002000) /* Fatal bus error interrupt */ -#define EMAC_DMA_INT_ET ((rt_uint32_t)0x00000400) /* Early transmit interrupt */ -#define EMAC_DMA_INT_RWT ((rt_uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ -#define EMAC_DMA_INT_RPS ((rt_uint32_t)0x00000100) /* Receive process stopped interrupt */ -#define EMAC_DMA_INT_RBU ((rt_uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ -#define EMAC_DMA_INT_R ((rt_uint32_t)0x00000040) /* Receive interrupt */ -#define EMAC_DMA_INT_TU ((rt_uint32_t)0x00000020) /* Underflow interrupt */ -#define EMAC_DMA_INT_RO ((rt_uint32_t)0x00000010) /* Overflow interrupt */ -#define EMAC_DMA_INT_TJT ((rt_uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ -#define EMAC_DMA_INT_TBU ((rt_uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ -#define EMAC_DMA_INT_TPS ((rt_uint32_t)0x00000002) /* Transmit process stopped interrupt */ -#define EMAC_DMA_INT_T ((rt_uint32_t)0x00000001) /* Transmit interrupt */ - -#define EMAC_DMA_TransmitProcess_Stopped ((rt_uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ -#define EMAC_DMA_TransmitProcess_Fetching ((rt_uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ -#define EMAC_DMA_TransmitProcess_Waiting ((rt_uint32_t)0x00200000) /* Running - waiting for status */ -#define EMAC_DMA_TransmitProcess_Reading ((rt_uint32_t)0x00300000) /* Running - reading the data from host memory */ -#define EMAC_DMA_TransmitProcess_Suspended ((rt_uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailable */ -#define EMAC_DMA_TransmitProcess_Closing ((rt_uint32_t)0x00700000) /* Running - closing Rx descriptor */ - -#define EMAC_DMA_ReceiveProcess_Stopped ((rt_uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ -#define EMAC_DMA_ReceiveProcess_Fetching ((rt_uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ -#define EMAC_DMA_ReceiveProcess_Waiting ((rt_uint32_t)0x00060000) /* Running - waiting for packet */ -#define EMAC_DMA_ReceiveProcess_Suspended ((rt_uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ -#define EMAC_DMA_ReceiveProcess_Closing ((rt_uint32_t)0x000A0000) /* Running - closing descriptor */ -#define EMAC_DMA_ReceiveProcess_Queuing ((rt_uint32_t)0x000E0000) /* Running - queuing the receive frame into host memory */ - -#define EMAC_DMA_Overflow_RxFIFOCounter ((rt_uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ -#define EMAC_DMA_Overflow_MissedFrameCounter ((rt_uint32_t)0x00010000) /* Overflow bit for missed frame counter */ - -#define EMAC_PMT_FLAG_WUFFRPR ((rt_uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ -#define EMAC_PMT_FLAG_WUFR ((rt_uint32_t)0x00000040) /* Wake-Up Frame Received */ -#define EMAC_PMT_FLAG_MPR ((rt_uint32_t)0x00000020) /* Magic Packet Received */ - -#define EMAC_MMC_IT_TGF ((rt_uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ -#define EMAC_MMC_IT_TGFMSC ((rt_uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ -#define EMAC_MMC_IT_TGFSC ((rt_uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ -#define EMAC_MMC_IT_RGUF ((rt_uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ -#define EMAC_MMC_IT_RFAE ((rt_uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ -#define EMAC_MMC_IT_RFCE ((rt_uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ - -#define EMAC_MMCCR ((rt_uint32_t)0x00000100) /* MMC CR register */ -#define EMAC_MMCRIR ((rt_uint32_t)0x00000104) /* MMC RIR register */ -#define EMAC_MMCTIR ((rt_uint32_t)0x00000108) /* MMC TIR register */ -#define EMAC_MMCRIMR ((rt_uint32_t)0x0000010C) /* MMC RIMR register */ -#define EMAC_MMCTIMR ((rt_uint32_t)0x00000110) /* MMC TIMR register */ -#define EMAC_MMCTGFSCCR ((rt_uint32_t)0x0000014C) /* MMC TGFSCCR register */ -#define EMAC_MMCTGFMSCCR ((rt_uint32_t)0x00000150) /* MMC TGFMSCCR register */ -#define EMAC_MMCTGFCR ((rt_uint32_t)0x00000168) /* MMC TGFCR register */ -#define EMAC_MMCRFCECR ((rt_uint32_t)0x00000194) /* MMC RFCECR register */ -#define EMAC_MMCRFAECR ((rt_uint32_t)0x00000198) /* MMC RFAECR register */ -#define EMAC_MMCRGUFCR ((rt_uint32_t)0x000001C4) /* MMC RGUFCR register */ - -#define EMAC_PTP_FineUpdate ((rt_uint32_t)0x00000001) /* Fine Update method */ -#define EMAC_PTP_CoarseUpdate ((rt_uint32_t)0x00000000) /* Coarse Update method */ - -#define EMAC_PTP_FLAG_TSARU ((rt_uint32_t)0x00000020) /* Addend Register Update */ -#define EMAC_PTP_FLAG_TSITE ((rt_uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ -#define EMAC_PTP_FLAG_TSSTU ((rt_uint32_t)0x00000008) /* Time Stamp Update */ -#define EMAC_PTP_FLAG_TSSTI ((rt_uint32_t)0x00000004) /* Time Stamp Initialize */ - -#define EMAC_PTP_PositiveTime ((rt_uint32_t)0x00000000) /* Positive time value */ -#define EMAC_PTP_NegativeTime ((rt_uint32_t)0x80000000) /* Negative time value */ - -#define EMAC_PTPTSCR ((rt_uint32_t)0x00000700) /* PTP TSCR register */ -#define EMAC_PTPSSIR ((rt_uint32_t)0x00000704) /* PTP SSIR register */ -#define EMAC_PTPTSHR ((rt_uint32_t)0x00000708) /* PTP TSHR register */ -#define EMAC_PTPTSLR ((rt_uint32_t)0x0000070C) /* PTP TSLR register */ -#define EMAC_PTPTSHUR ((rt_uint32_t)0x00000710) /* PTP TSHUR register */ -#define EMAC_PTPTSLUR ((rt_uint32_t)0x00000714) /* PTP TSLUR register */ -#define EMAC_PTPTSAR ((rt_uint32_t)0x00000718) /* PTP TSAR register */ -#define EMAC_PTPTTHR ((rt_uint32_t)0x0000071C) /* PTP TTHR register */ -#define EMAC_PTPTTLR ((rt_uint32_t)0x00000720) /* PTP TTLR register */ - -/* ETHERNET MAC address offsets */ -#define EMAC_MAC_ADDR_HBASE (ETHERNET_MAC0_BASE + 0x40) /* ETHERNET MAC address high offset */ -#define EMAC_MAC_ADDR_LBASE (ETHERNET_MAC0_BASE + 0x44) /* ETHERNET MAC address low offset */ - -/* ETHERNET MACMIIAR register Mask */ -#define MACMIIAR_CR_MASK ((rt_uint32_t)0xFFFFFFE3) - -/* ETHERNET MACCR register Mask */ -#define MACCR_CLEAR_MASK ((rt_uint32_t)0xFF20810F) - -/* ETHERNET MACFCR register Mask */ -#define MACFCR_CLEAR_MASK ((rt_uint32_t)0x0000FF41) - -/* ETHERNET DMAOMR register Mask */ -#define DMAOMR_CLEAR_MASK ((rt_uint32_t)0xF8DE3F23) - -/* ETHERNET errors */ -#define EMAC_ERROR ((rt_uint32_t)0) -#define EMAC_SUCCESS ((rt_uint32_t)1) - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define EMAC_DMARXDESC_FRAME_LENGTHSHIFT 16 - - - - -/* ETHERNET-MAC registers */ -/* ETHERNET-MAC registers */ -struct rt_synopsys_eth -{ - volatile rt_uint32_t MCR; - volatile rt_uint32_t MFFR; - volatile rt_uint32_t MHTRH; - volatile rt_uint32_t MHTRL; - volatile rt_uint32_t GAR; - volatile rt_uint32_t GDR; - volatile rt_uint32_t FCR; - volatile rt_uint32_t VTR; - rt_uint8_t RESERVED0[8]; - - volatile rt_uint32_t RWFFR; - volatile rt_uint32_t PMTR; - volatile rt_uint32_t LPICSR; - volatile rt_uint32_t LPITCR; - volatile rt_uint32_t ISR; - volatile rt_uint32_t IMR; - - struct MARS - { - volatile rt_uint32_t MARH; - volatile rt_uint32_t MARL; - } MARs[16]; - - rt_uint8_t RESERVED1[24]; - volatile rt_uint32_t RGSR; - rt_uint8_t RESERVED2[36]; - volatile rt_uint32_t mmc_cntl; - volatile rt_uint32_t mmc_intr_rx; - volatile rt_uint32_t mmc_intr_tx; - volatile rt_uint32_t mmc_intr_mask_rx; - volatile rt_uint32_t mmc_intr_mask_tx; - volatile rt_uint32_t txoctetcount_gb; - volatile rt_uint32_t txframecount_gb; - volatile rt_uint32_t txbroadcastframes_g; - volatile rt_uint32_t txmulticastframes_g; - volatile rt_uint32_t tx64octets_gb; - volatile rt_uint32_t tx65to127octets_gb; - volatile rt_uint32_t tx128to255octets_gb; - volatile rt_uint32_t tx256to511octets_gb; - volatile rt_uint32_t tx512to1023octets_gb; - volatile rt_uint32_t tx1024tomaxoctets_gb; - volatile rt_uint32_t txunicastframes_gb; - volatile rt_uint32_t txmulticastframes_gb; - volatile rt_uint32_t txbroadcastframes_gb; - volatile rt_uint32_t txunderflowerror; - volatile rt_uint32_t txsinglecol_g; - volatile rt_uint32_t txmulticol_g; - volatile rt_uint32_t txdeferred; - volatile rt_uint32_t txlatecol; - volatile rt_uint32_t txexesscol; - volatile rt_uint32_t txcarriererror; - volatile rt_uint32_t txoctetcount_g; - volatile rt_uint32_t txframecount_g; - volatile rt_uint32_t txexecessdef_g; - volatile rt_uint32_t txpauseframes; - volatile rt_uint32_t txvlanframes_g; - rt_uint8_t RESERVED3[8]; - volatile rt_uint32_t rxframecount_gb; - volatile rt_uint32_t rxoctetcount_gb; - volatile rt_uint32_t rxoctetcount_g; - volatile rt_uint32_t rxbroadcastframes_g; - volatile rt_uint32_t rxmulticastframes_g; - volatile rt_uint32_t rxcrcerror; - volatile rt_uint32_t rxallignmenterror; - volatile rt_uint32_t rxrunterror; - volatile rt_uint32_t rxjabbererror; - volatile rt_uint32_t rxundersize_g; - volatile rt_uint32_t rxoversize_g; - volatile rt_uint32_t rx64octets_gb; - volatile rt_uint32_t rx65to127octets_gb; - volatile rt_uint32_t rx128to255octets_gb; - volatile rt_uint32_t rx256to511octets_gb; - volatile rt_uint32_t rx512to1023octets_gb; - volatile rt_uint32_t rx1024tomaxoctets_gb; - volatile rt_uint32_t rxunicastframes_g; - volatile rt_uint32_t rxlengtherror; - volatile rt_uint32_t rxoutofrangetype; - volatile rt_uint32_t rxpauseframes; - volatile rt_uint32_t rxfifooverflow; - volatile rt_uint32_t rxvlanframes_gb; - volatile rt_uint32_t rxwatchdogerror; - rt_uint8_t RESERVED4[32]; - volatile rt_uint32_t mmc_ipc_intr_mask_rx; - rt_uint8_t RESERVED5[4]; - volatile rt_uint32_t mmc_ipc_intr_rx; - rt_uint8_t RESERVED6[4]; - volatile rt_uint32_t rxipv4_gd_frms; - volatile rt_uint32_t rxipv4_hdrerr_frms; - volatile rt_uint32_t rxipv4_nopay_frms; - volatile rt_uint32_t rxipv4_frag_frms; - volatile rt_uint32_t rxipv4_udsbl_frms; - volatile rt_uint32_t rxipv6_gd_frms; - volatile rt_uint32_t rxipv6_hdrerr_frms; - volatile rt_uint32_t rxipv6_nopay_frms; - volatile rt_uint32_t rxudp_gd_frms; - volatile rt_uint32_t rxudp_err_frms; - volatile rt_uint32_t rxtcp_gd_frms; - volatile rt_uint32_t rxtcp_err_frms; - volatile rt_uint32_t rxicmp_gd_frms; - volatile rt_uint32_t rxicmp_err_frms; - rt_uint8_t RESERVED7[8]; - volatile rt_uint32_t rxipv4_gd_octets; - volatile rt_uint32_t rxipv4_hdrerr_octets; - volatile rt_uint32_t rxipv4_nopay_octets; - volatile rt_uint32_t rxipv4_frag_octets; - volatile rt_uint32_t rxipv4_udsbl_octets; - volatile rt_uint32_t rxipv6_gd_octets; - volatile rt_uint32_t rxipv6_hdrerr_octets; - volatile rt_uint32_t rxipv6_nopay_octets; - volatile rt_uint32_t rxudp_gd_octets; - volatile rt_uint32_t rxudp_err_octets; - volatile rt_uint32_t rxtcp_gd_octets; - volatile rt_uint32_t rxtcp_err_octets; - volatile rt_uint32_t rxicmp_gd_octets; - volatile rt_uint32_t rxicmp_err_octets; - rt_uint8_t RESERVED8[1144]; - volatile rt_uint32_t TSCR; - volatile rt_uint32_t SSIR; - volatile rt_uint32_t STSR; - volatile rt_uint32_t STNR; - volatile rt_uint32_t STSUR; - volatile rt_uint32_t STNUR; - volatile rt_uint32_t TSAR; - volatile rt_uint32_t TTSR; - volatile rt_uint32_t TTNR; - volatile rt_uint32_t STHWSR; - volatile rt_uint32_t TSR; - volatile rt_uint32_t PPSCR; - volatile rt_uint32_t ATNR; - volatile rt_uint32_t ATSR; - rt_uint8_t RESERVED9[200]; - volatile rt_uint32_t MAR16H; - volatile rt_uint32_t MAR16L; - volatile rt_uint32_t MAR17H; - volatile rt_uint32_t MAR17L; - volatile rt_uint32_t MAR18H; - volatile rt_uint32_t MAR18L; - volatile rt_uint32_t MAR19H; - volatile rt_uint32_t MAR19L; - volatile rt_uint32_t MAR20H; - volatile rt_uint32_t MAR20L; - volatile rt_uint32_t MAR21H; - volatile rt_uint32_t MAR21L; - volatile rt_uint32_t MAR22H; - volatile rt_uint32_t MAR22L; - volatile rt_uint32_t MAR23H; - volatile rt_uint32_t MAR23L; - volatile rt_uint32_t MAR24H; - volatile rt_uint32_t MAR24L; - volatile rt_uint32_t MAR25H; - volatile rt_uint32_t MAR25L; - volatile rt_uint32_t MAR26H; - volatile rt_uint32_t MAR26L; - volatile rt_uint32_t MAR27H; - volatile rt_uint32_t MAR27L; - volatile rt_uint32_t MAR28H; - volatile rt_uint32_t MAR28L; - volatile rt_uint32_t MAR29H; - volatile rt_uint32_t MAR29L; - volatile rt_uint32_t MAR30H; - volatile rt_uint32_t MAR30L; - volatile rt_uint32_t MAR31H; - volatile rt_uint32_t MAR31L; - rt_uint8_t RESERVED10[1920]; - volatile rt_uint32_t BMR; - volatile rt_uint32_t TPDR; - volatile rt_uint32_t RPDR; - volatile rt_uint32_t RDLAR; - volatile rt_uint32_t TDLAR; - volatile rt_uint32_t SR; - volatile rt_uint32_t OMR; - volatile rt_uint32_t IER; - volatile rt_uint32_t MFBOCR; - volatile rt_uint32_t RIWTR; - rt_uint8_t RESERVED11[4]; - volatile rt_uint32_t AHBSR; - rt_uint8_t RESERVED12[24]; - volatile rt_uint32_t CHTDR; - volatile rt_uint32_t CHRDR; - volatile rt_uint32_t CHTBAR; - volatile rt_uint32_t CHRBAR; -}; -typedef struct rt_synopsys_eth rt_synopsys_eth; - - -rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock); - -void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC); - -rt_uint16_t EMAC_PHY_read(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg); -rt_uint32_t EMAC_PHY_write(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg, rt_uint16_t PHYValue); - -void EMAC_MAC_Addr_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t MacAddr, rt_uint8_t *Addr); -void EMAC_clear_pending(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT); - -void EMAC_INT_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT, rt_bool_t NewState); -void EMAC_resume_transmission(struct rt_synopsys_eth * ETHERNET_MAC); -void EMAC_resume_reception(struct rt_synopsys_eth * ETHERNET_MAC); - -#endif diff --git a/bsp/gd32450z-eval/gd32_rom.icf b/bsp/gd32450z-eval/gd32_rom.icf deleted file mode 100644 index 80461d6dfa..0000000000 --- a/bsp/gd32450z-eval/gd32_rom.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x082FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -export symbol __ICFEDIT_region_RAM_end__; - -define symbol __region_RAM1_start__ = 0x10000000; -define symbol __region_RAM1_end__ = 0x1000FFFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; diff --git a/bsp/gd32450z-eval/gd32_rom.ld b/bsp/gd32450z-eval/gd32_rom.ld deleted file mode 100644 index ec1c65c34e..0000000000 --- a/bsp/gd32450z-eval/gd32_rom.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linker script for GD32F4xx with GNU ld - * bernard.xiong 2009-10-14 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 3072k /* 3072KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/gd32450z-eval/gd32_rom.sct b/bsp/gd32450z-eval/gd32_rom.sct deleted file mode 100644 index f8a5eaf1e2..0000000000 --- a/bsp/gd32450z-eval/gd32_rom.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x00300000 { ; load region size_region - ER_IROM1 0x08000000 0x00300000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00030000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/gd32450z-eval/project.ewp b/bsp/gd32450z-eval/project.ewp deleted file mode 100644 index 3b9074aaba..0000000000 --- a/bsp/gd32450z-eval/project.ewp +++ /dev/null @@ -1,2412 +0,0 @@ - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - Applications - - $PROJ_DIR$\applications\main.c - - - - Compiler - - $PROJ_DIR$\..\..\components\libc\compilers\common\cctype.c - - - $PROJ_DIR$\..\..\components\libc\compilers\common\cstdlib.c - - - $PROJ_DIR$\..\..\components\libc\compilers\common\cstring.c - - - $PROJ_DIR$\..\..\components\libc\compilers\common\ctime.c - - - $PROJ_DIR$\..\..\components\libc\compilers\common\cunistd.c - - - $PROJ_DIR$\..\..\components\libc\compilers\common\cwchar.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c - - - $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscalls.c - - - - CPU - - $PROJ_DIR$\..\..\libcpu\arm\common\div0.c - - - $PROJ_DIR$\..\..\libcpu\arm\common\showmem.c - - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m4\context_iar.S - - - $PROJ_DIR$\..\..\libcpu\arm\cortex-m4\cpuport.c - - - - DeviceDrivers - - $PROJ_DIR$\..\..\components\drivers\core\device.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\completion.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\dataqueue.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\pipe.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\ringblk_buf.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\ringbuffer.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\waitqueue.c - - - $PROJ_DIR$\..\..\components\drivers\ipc\workqueue.c - - - $PROJ_DIR$\..\..\components\drivers\misc\pin.c - - - $PROJ_DIR$\..\..\components\drivers\serial\serial.c - - - - Drivers - - $PROJ_DIR$\drivers\drv_enet.c - - - $PROJ_DIR$\drivers\drv_usart.c - - - $PROJ_DIR$\drivers\synopsys_emac.c - - - $PROJ_DIR$\drivers\board.c - - - $PROJ_DIR$\drivers\drv_exmc_sdram.c - - - - Filesystem - - $PROJ_DIR$\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c - - - $PROJ_DIR$\..\..\components\dfs\dfs_v1\filesystems\elmfat\dfs_elm.c - - - $PROJ_DIR$\..\..\components\dfs\dfs_v1\filesystems\elmfat\ff.c - - - $PROJ_DIR$\..\..\components\dfs\dfs_v1\filesystems\elmfat\ffunicode.c - - - $PROJ_DIR$\..\..\components\dfs\dfs_v1\src\dfs.c - - - $PROJ_DIR$\..\..\components\dfs\dfs_v1\src\dfs_file.c - - - $PROJ_DIR$\..\..\components\dfs\dfs_v1\src\dfs_fs.c - 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- - $PROJ_DIR$\..\..\components\net\sal\dfs_net\dfs_net.c - - - $PROJ_DIR$\..\..\components\net\sal\impl\af_inet_lwip.c - - - $PROJ_DIR$\..\..\components\net\sal\socket\net_netdb.c - - - $PROJ_DIR$\..\..\components\net\sal\socket\net_sockets.c - - - $PROJ_DIR$\..\..\components\net\sal\src\sal_socket.c - - - diff --git a/bsp/gd32450z-eval/project.eww b/bsp/gd32450z-eval/project.eww deleted file mode 100644 index c2cb02eb1e..0000000000 --- a/bsp/gd32450z-eval/project.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\project.ewp - - - - - diff --git a/bsp/gd32450z-eval/project.uvoptx b/bsp/gd32450z-eval/project.uvoptx deleted file mode 100644 index fe3cccb4dc..0000000000 --- a/bsp/gd32450z-eval/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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- - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler_up.c - 1 - ..\..\src\scheduler_up.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - Libraries - - - startup_gd32f4xx.s - 2 - Libraries\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s - - - - - gd32f4xx_iref.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c - - - - - gd32f4xx_ctc.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c - - - - - gd32f4xx_enet.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c - - - - - gd32f4xx_misc.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c - - - - - gd32f4xx_trng.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c - - - - - gd32f4xx_rcu.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c - - - - - gd32f4xx_dci.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c - - - - - gd32f4xx_pmu.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c - - - - - gd32f4xx_gpio.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c - - - - - gd32f4xx_syscfg.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c - - - - - system_gd32f4xx.c - 1 - Libraries\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c - - - - - gd32f4xx_ipa.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c - - - - - gd32f4xx_crc.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c - - - - - gd32f4xx_exmc.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c - - - - - gd32f4xx_usart.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c - - - - - gd32f4xx_fmc.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c - - - - - gd32f4xx_sdio.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c - - - - - gd32f4xx_spi.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c - - - - - gd32f4xx_timer.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c - - - - - gd32f4xx_can.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c - - - - - gd32f4xx_adc.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c - - - - - gd32f4xx_tli.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c - - - - - gd32f4xx_dbg.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c - - - - - gd32f4xx_rtc.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c - - - - - gd32f4xx_dma.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c - - - - - gd32f4xx_i2c.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c - - - - - gd32f4xx_fwdgt.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c - - - - - gd32f4xx_wwdgt.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c - - - - - gd32f4xx_dac.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c - - - - - gd32f4xx_exti.c - 1 - Libraries\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c - - - - - lwIP - - - api_lib.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\api_lib.c - - - - - api_msg.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\api_msg.c - - - - - err.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\err.c - - - - - netbuf.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\netbuf.c - - - - - netdb.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\netdb.c - - - - - netifapi.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\netifapi.c - - - - - sockets.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\sockets.c - - - - - tcpip.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\api\tcpip.c - - - - - ping.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\apps\ping\ping.c - - - - - def.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\def.c - - - - - dns.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\dns.c - - - - - inet_chksum.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\inet_chksum.c - - - - - init.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\init.c - - - - - ip.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ip.c - - - - - autoip.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\autoip.c - - - - - dhcp.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\dhcp.c - - - - - etharp.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\etharp.c - - - - - icmp.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\icmp.c - - - - - igmp.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\igmp.c - - - - - ip4.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4.c - - - - - ip4_addr.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_addr.c - - - - - ip4_frag.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\ipv4\ip4_frag.c - - - - - memp.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\memp.c - - - - - netif.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\netif.c - - - - - pbuf.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\pbuf.c - - - - - raw.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\raw.c - - - - - stats.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\stats.c - - - - - sys.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\sys.c - - - - - tcp.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\tcp.c - - - - - tcp_in.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\tcp_in.c - - - - - tcp_out.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\tcp_out.c - - - - - timeouts.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\timeouts.c - - - - - udp.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\core\udp.c - - - - - ethernet.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\netif\ethernet.c - - - - - lowpan6.c - 1 - ..\..\components\net\lwip\lwip-2.0.3\src\netif\lowpan6.c - - - - - ethernetif.c - 1 - ..\..\components\net\lwip\port\ethernetif.c - - - - - sys_arch.c - 1 - ..\..\components\net\lwip\port\sys_arch.c - - - - - POSIX - - - poll.c - 1 - ..\..\components\libc\posix\io\poll\poll.c - - - - - select.c - 1 - ..\..\components\libc\posix\io\poll\select.c - - - - - SAL - - - netdev.c - 1 - ..\..\components\net\netdev\src\netdev.c - - - - - netdev_ipaddr.c - 1 - ..\..\components\net\netdev\src\netdev_ipaddr.c - - - - - dfs_net.c - 1 - ..\..\components\net\sal\dfs_net\dfs_net.c - - - - - af_inet_lwip.c - 1 - ..\..\components\net\sal\impl\af_inet_lwip.c - - - - - net_netdb.c - 1 - ..\..\components\net\sal\socket\net_netdb.c - - - - - net_sockets.c - 1 - ..\..\components\net\sal\socket\net_sockets.c - - - - - sal_socket.c - 1 - ..\..\components\net\sal\src\sal_socket.c - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32450z-eval/rtconfig.h b/bsp/gd32450z-eval/rtconfig.h deleted file mode 100644 index bb272cfba4..0000000000 --- a/bsp/gd32450z-eval/rtconfig.h +++ /dev/null @@ -1,318 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 - -/* kservice optimization */ - -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FD_MAX 16 -#define RT_USING_DFS_V1 -#define DFS_FILESYSTEMS_MAX 4 -#define DFS_FILESYSTEM_TYPES_MAX 4 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_0 -#define RT_DFS_ELM_USE_LFN 0 -#define RT_DFS_ELM_LFN_UNICODE_0 -#define RT_DFS_ELM_LFN_UNICODE 0 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 2 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -#define RT_DFS_ELM_REENTRANT -#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SYSTEM_WORKQUEUE -#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 -#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - -#define RT_USING_POSIX_FS -#define RT_USING_POSIX_POLL -#define RT_USING_POSIX_SELECT - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - -#define RT_USING_SAL -#define SAL_INTERNET_CHECK - -/* Docking with protocol stacks */ - -#define SAL_USING_LWIP -#define SAL_USING_POSIX -#define RT_USING_NETDEV -#define NETDEV_USING_IFCONFIG -#define NETDEV_USING_PING -#define NETDEV_USING_NETSTAT -#define NETDEV_USING_AUTO_DEFAULT -#define NETDEV_IPV4 1 -#define NETDEV_IPV6 0 -#define RT_USING_LWIP -#define RT_USING_LWIP203 -#define RT_USING_LWIP_VER_NUM 0x20003 -#define RT_LWIP_MEM_ALIGNMENT 4 -#define RT_LWIP_IGMP -#define RT_LWIP_ICMP -#define RT_LWIP_DNS -#define RT_LWIP_DHCP -#define IP_SOF_BROADCAST 1 -#define IP_SOF_BROADCAST_RECV 1 - -/* Static IPv4 Address */ - -#define RT_LWIP_IPADDR "192.168.1.30" -#define RT_LWIP_GWADDR "192.168.1.1" -#define RT_LWIP_MSKADDR "255.255.255.0" -#define RT_LWIP_UDP -#define RT_LWIP_TCP -#define RT_LWIP_RAW -#define RT_MEMP_NUM_NETCONN 8 -#define RT_LWIP_PBUF_NUM 16 -#define RT_LWIP_RAW_PCB_NUM 4 -#define RT_LWIP_UDP_PCB_NUM 4 -#define RT_LWIP_TCP_PCB_NUM 4 -#define RT_LWIP_TCP_SEG_NUM 40 -#define RT_LWIP_TCP_SND_BUF 8196 -#define RT_LWIP_TCP_WND 8196 -#define RT_LWIP_TCPTHREAD_PRIORITY 10 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_PRIORITY 12 -#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 -#define LWIP_NETIF_STATUS_CALLBACK 1 -#define LWIP_NETIF_LINK_CALLBACK 1 -#define SO_REUSE 1 -#define LWIP_SO_RCVTIMEO 1 -#define LWIP_SO_SNDTIMEO 1 -#define LWIP_SO_RCVBUF 1 -#define LWIP_SO_LINGER 0 -#define LWIP_NETIF_LOOPBACK 0 -#define RT_LWIP_USING_PING - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* sensors drivers */ - - -/* touch drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -#define SOC_GD32450Z -#define BSP_USING_SDRAM -#define BSP_USING_UART0 - -#endif diff --git a/bsp/gd32450z-eval/rtconfig.py b/bsp/gd32450z-eval/rtconfig.py deleted file mode 100644 index 56fce9b8c0..0000000000 --- a/bsp/gd32450z-eval/rtconfig.py +++ /dev/null @@ -1,126 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -DGD32F450' - CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu=cortex-m4.fp' - CFLAGS = DEVICE + ' --apcs=interwork --cpu Cortex-M4.fp' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - CFLAGS += ' --c99' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F450xK' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M4' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M4' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config gd32_rom.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH += '/arm/bin/' - POST_ACTION = '' diff --git a/bsp/gd32450z-eval/startcmd.bat b/bsp/gd32450z-eval/startcmd.bat deleted file mode 100644 index a03f9d44c3..0000000000 --- a/bsp/gd32450z-eval/startcmd.bat +++ /dev/null @@ -1 +0,0 @@ -start cmd.exe \ No newline at end of file diff --git a/bsp/gd32450z-eval/template.ewp b/bsp/gd32450z-eval/template.ewp deleted file mode 100644 index 0aaf7642be..0000000000 --- a/bsp/gd32450z-eval/template.ewp +++ /dev/null @@ -1,1892 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 22 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 22 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/gd32450z-eval/template.uvoptx b/bsp/gd32450z-eval/template.uvoptx deleted file mode 100644 index fe3cccb4dc..0000000000 --- a/bsp/gd32450z-eval/template.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32f4xx - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U59401765 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB.FLM -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM) - - - 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM)) - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/gd32450z-eval/template.uvproj b/bsp/gd32450z-eval/template.uvproj deleted file mode 100644 index d6ae5fe439..0000000000 --- a/bsp/gd32450z-eval/template.uvproj +++ /dev/null @@ -1,628 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread_gd32f4xx - 0x4 - ARM-ADS - 0 - - - GD32F450ZK - GigaDevice - IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x08000000-0x082FFFFF) CLOCK(16000000) CPUTYPE("Cortex-M4") FPU2 - - "Startup\GD\GD32F4xx\startup_gd32f4xx.s" ("GD32F4xx Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000) - 0 - gd32f4xx0.h - - - - - - - - - - SFD\GD\GD32F4xx\GD32F4xx.SFR - 0 - 0 - - - - GD\GD32F4xx\ - GD\GD32F4xx\ - - 0 - 0 - 0 - 0 - 1 - - .\output\ - rtthread-gd32f4xx - 1 - 0 - 1 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP - DCM.DLL - -pCM3 - SARMCM3.DLL - - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 1 - - 0 - 3 - - - - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 1 - 0 - 8 - 1 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x30000 - - - 1 - 0x8000000 - 0x300000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x300000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x30000 - - - 0 - 0x10000000 - 0x10000 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Include;..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Include;..\..\..\Library\Utilities;..\ - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Application - - - main.c - 1 - ..\main.c - - - gd32f4xx_it.c - 1 - ..\gd32f4xx_it.c - - - - - CMSIS - - - system_gd32f4xx.c - 1 - ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\system_gd32f4xx.c - - - - - GD32F4xx_Peripherals - - - gd32f4xx_adc.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_adc.c - - - gd32f4xx_can.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_can.c - - - gd32f4xx_crc.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_crc.c - - - gd32f4xx_ctc.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ctc.c - - - gd32f4xx_dac.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dac.c - - - gd32f4xx_dbg.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dbg.c - - - gd32f4xx_dci.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dci.c - - - gd32f4xx_dma.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_dma.c - - - gd32f4xx_enet.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_enet.c - - - gd32f4xx_exmc.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exmc.c - - - gd32f4xx_exti.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_exti.c - - - gd32f4xx_fmc.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fmc.c - - - gd32f4xx_fwdgt.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_fwdgt.c - - - gd32f4xx_gpio.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_gpio.c - - - gd32f4xx_i2c.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_i2c.c - - - gd32f4xx_ipa.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_ipa.c - - - gd32f4xx_iref.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_iref.c - - - gd32f4xx_misc.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_misc.c - - - gd32f4xx_pmu.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_pmu.c - - - gd32f4xx_rcu.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rcu.c - - - gd32f4xx_rtc.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_rtc.c - - - gd32f4xx_sdio.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_sdio.c - - - gd32f4xx_spi.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_spi.c - - - gd32f4xx_syscfg.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_syscfg.c - - - gd32f4xx_timer.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_timer.c - - - gd32f4xx_tli.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_tli.c - - - gd32f4xx_trng.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_trng.c - - - gd32f4xx_usart.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_usart.c - - - gd32f4xx_wwdgt.c - 1 - ..\..\..\Library\Firmware\GD32F4xx_standard_peripheral\Source\gd32f4xx_wwdgt.c - - - - - GD32F4xx_EVAL - - - gd32f450z_eval.c - 1 - ..\..\..\Library\Utilities\gd32f450z_eval.c - - - - - Startup - - - startup_gd32f4xx.s - 2 - ..\..\..\Library\Firmware\CMSIS\GD\GD32F4xx\Source\ARM\startup_gd32f4xx.s - - - - - Doc - - - readme.txt - 5 - ..\readme.txt - - - - - - - - diff --git a/bsp/gd32450z-eval/template.uvprojx b/bsp/gd32450z-eval/template.uvprojx deleted file mode 100644 index 49c076be27..0000000000 --- a/bsp/gd32450z-eval/template.uvprojx +++ /dev/null @@ -1,400 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread_gd32f4xx - 0x4 - ARM-ADS - 0 - - - GD32F450ZK - GigaDevice - GigaDevice.GD32F4xx_DFP.1.0.1 - http://gd32mcu.21ic.com/data/documents/yingyongruanjian/GD32F4 - IRAM(0x20000000,0x030000) IRAM2(0x10000000,0x010000) IROM(0x08000000,0x0300000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32F4xx_3MB -FS08000000 -FL0300000 -FP0($$Device:GD32F450ZK$Flash\GD32F4xx_3MB.FLM)) - 0 - $$Device:GD32F450ZK$Device\Include\gd32f4xx.h - - - - - - - - - - $$Device:GD32F450ZK$SVD\GD32F4xx.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-gd32f4xx - 1 - 0 - 0 - 1 - 0 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2CM3.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M4" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 2 - 1 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x30000 - - - 1 - 0x8000000 - 0x300000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x300000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x30000 - - - 0 - 0x10000000 - 0x10000 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - .\gd32_rom.ld - - - - - - - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32e230k-start/.config b/bsp/gd32e230k-start/.config deleted file mode 100644 index 020876b700..0000000000 --- a/bsp/gd32e230k-start/.config +++ /dev/null @@ -1,1009 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_INIT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50002 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -# CONFIG_RT_USING_DFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -# CONFIG_RT_USING_I2C_BITOPS is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -CONFIG_RT_USING_SFUD=y -# CONFIG_RT_SFUD_USING_SFDP is not set -CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y -# CONFIG_RT_SFUD_USING_QSPI is not set -CONFIG_RT_SFUD_SPI_MAX_HZ=50000000 -# CONFIG_RT_DEBUG_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_KTIME is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# -CONFIG_SOC_GD32E230K=y -CONFIG_RT_USING_USART0=y -CONFIG_RT_USING_USART1=y -# CONFIG_RT_USING_USART2 is not set -# CONFIG_RT_USING_UART3 is not set -# CONFIG_RT_USING_UART4 is not set -CONFIG_RT_USING_SPI0=y -CONFIG_RT_USING_SPI1=y -CONFIG_RT_USING_I2C0=y -# CONFIG_RT_USING_I2C1 is not set diff --git a/bsp/gd32e230k-start/Kconfig b/bsp/gd32e230k-start/Kconfig deleted file mode 100644 index 6391f8ce3d..0000000000 --- a/bsp/gd32e230k-start/Kconfig +++ /dev/null @@ -1,73 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" - -config SOC_GD32E230K - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -config RT_USING_USART0 - bool "Using USART0" - select RT_USING_SERIAL - default y - -config RT_USING_USART1 - bool "Using USART1" - select RT_USING_SERIAL - default n - -config RT_USING_USART2 - bool "Using USART2" - select RT_USING_SERIAL - default n - -config RT_USING_UART3 - bool "Using UART3" - select RT_USING_SERIAL - default n - -config RT_USING_UART4 - bool "Using UART4" - select RT_USING_SERIAL - default n - -config RT_USING_SPI0 - bool "Using SPI0" - select RT_USING_SPI - default y - -config RT_USING_SPI1 - bool "Using SPI1" - select RT_USING_SPI - default n - -config RT_USING_I2C0 - bool "Using I2C0" - select RT_USING_I2C - default n - -config RT_USING_I2C1 - bool "Using I2C1" - select RT_USING_I2C - default n - - - diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h deleted file mode 100644 index 60838636f7..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h +++ /dev/null @@ -1,212 +0,0 @@ -/*! - \file gd32e230.h - \brief general definitions for GD32E230 - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_H -#define GD32E230_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* define GD32E230 */ -#if !defined (GD32E230) - #define GD32E230 -#endif /* define GD32E230 */ -#if !defined (GD32E230) - #error "Please select the target GD32E230 device used in your application (in gd32e230.h file)" -#endif /* undefine GD32E230 tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined (HXTAL_VALUE) -#define HXTAL_VALUE ((uint32_t)8000000) -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal RC oscillator for ADC in Hz */ -#if !defined (IRC28M_VALUE) -#define IRC28M_VALUE ((uint32_t)28000000) -#endif /* IRC28M_VALUE */ - -#if !defined (IRC48M_VALUE) -#define IRC48M_VALUE ((uint32_t)48000000) -#endif /* IRC48M_VALUE */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* GD32E1x0 firmware library version number V1.0 */ -#define __GD32E230_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __GD32E230_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32E230_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32E230_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32E230_STDPERIPH_VERSION ((__GD32E230_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32E230_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32E230_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32E230_STDPERIPH_VERSION_RC)) - -/* configuration of the Cortex-M23 processor and core peripherals */ -#define __CM23_REV 0x0100U /*!< Core revision r1p0 */ -#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */ -#define __MPU_PRESENT 0U /*!< MPU is present */ -#define __VTOR_PRESENT 1U /*!< VTOR is present */ -#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/* define interrupt number */ -typedef enum IRQn -{ - /* Cortex-M23 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */ - HardFault_IRQn = -13, /*!< hardfault interrupt */ - - SVCall_IRQn = -5, /*!< sv call interrupt */ - - PendSV_IRQn = -2, /*!< pend sv interrupt */ - SysTick_IRQn = -1, /*!< system tick interrupt */ - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */ - FMC_IRQn = 3, /*!< FMC interrupt */ - RCU_IRQn = 4, /*!< RCU interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */ - DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */ - DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */ - DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */ - ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */ - TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */ - TIMER2_IRQn = 16, /*!< TIMER2 interrupt */ - TIMER5_IRQn = 17, /*!< TIMER5 interrupt */ - TIMER13_IRQn = 19, /*!< TIMER13 interrupt */ - TIMER14_IRQn = 20, /*!< TIMER14 interrupt */ - TIMER15_IRQn = 21, /*!< TIMER15 interrupt */ - TIMER16_IRQn = 22, /*!< TIMER16 interrupt */ - I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */ - I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */ - SPI0_IRQn = 25, /*!< SPI0 interrupt */ - SPI1_IRQn = 26, /*!< SPI1 interrupt */ - USART0_IRQn = 27, /*!< USART0 interrupt */ - USART1_IRQn = 28, /*!< USART1 interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ -} IRQn_Type; - -/* includes */ -#include "core_cm23.h" -#include "system_gd32e230.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ -/* SRAM and peripheral base bit-band region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */ -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ -#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -/* advanced peripheral bus 2 memory map */ -#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ -#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ -/* advanced high performance bus 1 memory map */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ -#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ -/* advanced high performance bus 2 memory map */ -#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ -/* option byte and debug memory map */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */ - -#include "gd32e230_libopt.h" - -#ifdef __cplusplus -} -#endif - -#endif /* GD32E230_H */ diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h deleted file mode 100644 index 45441bd546..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h +++ /dev/null @@ -1,58 +0,0 @@ -/*! - \file system_gd32e230.h - \brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for - GD32E230 Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32E230_H -#define SYSTEM_GD32E230_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit (void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32E230_H */ diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s deleted file mode 100644 index 8b001a390f..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s +++ /dev/null @@ -1,256 +0,0 @@ -;/*! -; \file startup_gd32e230.s -; \brief start up file -; -; \version 2018-6-19, V1.0.0, firmware for GD32E230 -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD RTC_IRQHandler ; 18:RTC through EXTI Line - DCD FMC_IRQHandler ; 19:FMC - DCD RCU_IRQHandler ; 20:RCU - DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 - DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 - DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 - DCD 0 ; Reserved - DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 - DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 - DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 - DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator - DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare - DCD 0 ; Reserved - DCD TIMER2_IRQHandler ; 32:TIMER2 - DCD TIMER5_IRQHandler ; 33:TIMER5 - DCD 0 ; Reserved - DCD TIMER13_IRQHandler ; 35:TIMER13 - DCD TIMER14_IRQHandler ; 36:TIMER14 - DCD TIMER15_IRQHandler ; 37:TIMER15 - DCD TIMER16_IRQHandler ; 38:TIMER16 - DCD I2C0_EV_IRQHandler ; 39:I2C0 Event - DCD I2C1_EV_IRQHandler ; 40:I2C1 Event - DCD SPI0_IRQHandler ; 41:SPI0 - DCD SPI1_IRQHandler ; 42:SPI1 - DCD USART0_IRQHandler ; 43:USART0 - DCD USART1_IRQHandler ; 44:USART1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD 0 ; Reserved - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA_Channel0_IRQHandler [WEAK] - EXPORT DMA_Channel1_2_IRQHandler [WEAK] - EXPORT DMA_Channel3_4_IRQHandler [WEAK] - EXPORT ADC_CMP_IRQHandler [WEAK] - EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER13_IRQHandler [WEAK] - EXPORT TIMER14_IRQHandler [WEAK] - EXPORT TIMER15_IRQHandler [WEAK] - EXPORT TIMER16_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA_Channel0_IRQHandler -DMA_Channel1_2_IRQHandler -DMA_Channel3_4_IRQHandler -ADC_CMP_IRQHandler -TIMER0_BRK_UP_TRG_COM_IRQHandler -TIMER0_Channel_IRQHandler -TIMER2_IRQHandler -TIMER5_IRQHandler -TIMER13_IRQHandler -TIMER14_IRQHandler -TIMER15_IRQHandler -TIMER16_IRQHandler -I2C0_EV_IRQHandler -I2C1_EV_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -I2C0_ER_IRQHandler -I2C1_ER_IRQHandler - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s deleted file mode 100644 index a491356ce0..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s +++ /dev/null @@ -1,303 +0,0 @@ -;/*! -; \file startup_gd32e230.s -; \brief start up file -; -; \version 2018-06-19, V1.0.0, firmware for GD32E230 -;*/ -; -;/* -; Copyright (c) 2018, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -;are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, this -; list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -;OF SUCH DAMAGE. -;*/ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler - DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler - DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD RTC_IRQHandler ; 18:RTC through EXTI Line - DCD FMC_IRQHandler ; 19:FMC - DCD RCU_IRQHandler ; 20:RCU - DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 - DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 - DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 - DCD 0 ; Reserved - DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 - DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 - DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 - DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator - DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare - DCD 0 ; Reserved - DCD TIMER2_IRQHandler ; 32:TIMER2 - DCD TIMER5_IRQHandler ; 33:TIMER5 - DCD 0 ; Reserved - DCD TIMER13_IRQHandler ; 35:TIMER13 - DCD TIMER14_IRQHandler ; 36:TIMER14 - DCD TIMER15_IRQHandler ; 37:TIMER15 - DCD TIMER16_IRQHandler ; 38:TIMER16 - DCD I2C0_EV_IRQHandler ; 39:I2C0 Event - DCD I2C1_EV_IRQHandler ; 40:I2C1 Event - DCD SPI0_IRQHandler ; 41:SPI0 - DCD SPI1_IRQHandler ; 42:SPI1 - DCD USART0_IRQHandler ; 43:USART0 - DCD USART1_IRQHandler ; 44:USART1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD 0 ; Reserved - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK DMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel0_IRQHandler - B DMA_Channel0_IRQHandler - - PUBWEAK DMA_Channel1_2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel1_2_IRQHandler - B DMA_Channel1_2_IRQHandler - - PUBWEAK DMA_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel3_4_IRQHandler - B DMA_Channel3_4_IRQHandler - - PUBWEAK ADC_CMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC_CMP_IRQHandler - B ADC_CMP_IRQHandler - - PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_UP_TRG_COM_IRQHandler - B TIMER0_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER13_IRQHandler - B TIMER13_IRQHandler - - PUBWEAK TIMER14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER14_IRQHandler - B TIMER14_IRQHandler - - PUBWEAK TIMER15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER15_IRQHandler - B TIMER15_IRQHandler - - PUBWEAK TIMER16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER16_IRQHandler - B TIMER16_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - END \ No newline at end of file diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c b/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c deleted file mode 100644 index a4768d181f..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c +++ /dev/null @@ -1,371 +0,0 @@ -/*! - \file system_gd32e230.c - \brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for - GD32E1x0 Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32e230.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ - -/* select a system clock by uncommenting the following line */ -//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) -//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) -#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) - -#define SEL_IRC8M 0x00 -#define SEL_HXTAL 0x01 -#define SEL_PLL 0x02 - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_8M_HXTAL -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; -static void system_clock_8m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; -static void system_clock_72m_irc8m(void); - -#else -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; -static void system_clock_8m_irc8m(void); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none -*/ -void SystemInit (void) -{ - /* enable IRC8M */ - RCU_CTL0 |= RCU_CTL0_IRC8MEN; - while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ - } - /* reset RCU */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ - RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); - RCU_CFG1 &= ~(RCU_CFG1_PREDV); - RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; - RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; - RCU_INT = 0x00000000U; - - /* configure system clock */ - system_clock_config(); - -#ifdef VECT_TAB_SRAM - nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET); -#else - nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET); -#endif -} - -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_config(void) -{ -#ifdef __SYSTEM_CLOCK_8M_HXTAL - system_clock_8m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2) - system_clock_72m_irc48m(); -#else - system_clock_8m_irc8m(); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ -} - -#ifdef __SYSTEM_CLOCK_8M_HXTAL -/*! - \brief configure the system clock to 8M by HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL0 |= RCU_CTL0_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB); - } - while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){ - while(1){ - } - } - - FMC_WS &= ~FMC_WS_WSCNT; - FMC_WS |= WS_WSCNT_2; - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* PLL = HXTAL * 9 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL0 |= RCU_CTL0_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ - while(1){ - } - } - - FMC_WS &= ~FMC_WS_WSCNT; - FMC_WS |= WS_WSCNT_2; - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - /* PLL = (IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18); - - /* enable PLL */ - RCU_CTL0 |= RCU_CTL0_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#else -/*! - \brief configure the system clock to 8M by IRC8M - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_8m_irc8m(void) -{ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV1; - - /* select IRC8M as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_IRC8M; - - /* wait until IRC8M is selected as system clock */ - while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){ - } -} -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none -*/ -void SystemCoreClockUpdate (void) -{ - uint32_t sws = 0U; - uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; - /* exponent of AHB clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* get the value of PLLMF[3:0] */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - pllmf4 = GET_BITS(RCU_CFG0, 27, 27); - /* high 16 bits */ - if(1U == pllmf4){ - pllmf += 17U; - }else if(15U == pllmf){ - pllmf = 16U; - }else{ - pllmf += 2U; - } - - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = GET_BITS(RCU_CFG0, 16, 16); - if(0U != pllsel){ - prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); - SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf; - }else{ - SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - SystemCoreClock >>= clk_exp; -} diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_compiler.h b/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_compiler.h deleted file mode 100644 index fdb1a971c6..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_compiler.h +++ /dev/null @@ -1,271 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_gcc.h b/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_gcc.h deleted file mode 100644 index d86b0a2d5a..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_gcc.h +++ /dev/null @@ -1,2101 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.1.0 - * @date 20. December 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_version.h b/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_version.h deleted file mode 100644 index 660f612aa3..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/bsp/gd32e230k-start/Libraries/CMSIS/core_cm23.h b/bsp/gd32e230k-start/Libraries/CMSIS/core_cm23.h deleted file mode 100644 index 26fe163a0e..0000000000 --- a/bsp/gd32e230k-start/Libraries/CMSIS/core_cm23.h +++ /dev/null @@ -1,1993 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_adc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_adc.h deleted file mode 100644 index 2ffbec390e..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_adc.h +++ /dev/null @@ -1,351 +0,0 @@ -/*! - \file gd32e230_adc.h - \brief definitions for the ADC - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_ADC_H -#define GD32E230_ADC_H - -#include "gd32e230.h" - -/* ADC definitions */ -#define ADC ADC_BASE - -/* registers definitions */ -#define ADC_STAT REG32(ADC + 0x00U) /*!< ADC status register */ -#define ADC_CTL0 REG32(ADC + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1 REG32(ADC + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0 REG32(ADC + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1 REG32(ADC + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0 REG32(ADC + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1 REG32(ADC + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2 REG32(ADC + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3 REG32(ADC + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT REG32(ADC + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT REG32(ADC + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0 REG32(ADC + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1 REG32(ADC + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2 REG32(ADC + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ REG32(ADC + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0 REG32(ADC + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1 REG32(ADC + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2 REG32(ADC + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3 REG32(ADC + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA REG32(ADC + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL REG32(ADC + 0x80U) /*!< ADC oversampling control register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */ - -/* ADC_SAMPTx x=0,1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..9,16 and 17) sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx x=0..2 */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */ - -/* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ - -/* constants definitions */ -/* ADC flag definitions */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */ - -/* ADC special function */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */ - -/* external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */ -#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - -/* external trigger select for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) -#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ -#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */ -#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* ADC data offset for inserted channel x*/ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC analog watchdog high threshold */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC analog watchdog low threshold */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC regular channel group length */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) - -/* ADC inserted channel group length */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) - -/* ADC resolution definitions */ -#define CTL0_DRES(regval) (BITS(24,25) & ((regval) << 24)) /*!< ADC resolution */ -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ - -/* ADC oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - -/* ADC oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -/* ADC triggered oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ - -/* ADC interrupt definitions */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* function declarations */ -/* reset ADC */ -void adc_deinit(void); -/* enable ADC interface */ -void adc_enable(void); -/* disable ADC interface */ -void adc_disable(void); - -/* ADC calibration and reset calibration */ -void adc_calibration_enable(void); -/* enable DMA request */ -void adc_dma_mode_enable(void); -/* disable DMA request */ -void adc_dma_mode_disable(void); - -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); - -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length); -/* configure ADC special function */ -void adc_special_function_config(uint32_t function, ControlStatus newvalue); - -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t data_alignment); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint8_t channel_group, uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); -/* enable ADC external trigger */ -void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue); -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint8_t channel_group); - -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(void); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint8_t inserted_channel); - -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t flag); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t flag); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t flag); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t interrupt); - -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint8_t channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint8_t channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(void); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); - -/* configure ADC resolution */ -void adc_resolution_config(uint32_t resolution); -/* configure ADC oversample mode */ -void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio); -/* enable ADC oversample mode */ -void adc_oversample_mode_enable(void); -/* disable ADC oversample mode */ -void adc_oversample_mode_disable(void); - -#endif /* GD32E230_ADC_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h deleted file mode 100644 index aa9d8a9b2c..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h +++ /dev/null @@ -1,162 +0,0 @@ -/*! - \file gd32e230_cmp.h - \brief definitions for the CMP - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_CMP_H -#define GD32E230_CMP_H - -#include "gd32e230.h" - -/* CMP definitions */ -#define CMP CMP_BASE /*!< CMP base address */ - -/* registers definitions */ -#define CMP_CS REG32((CMP) + 0x00U) /*!< CMP control and status register */ - -/* CMP_CS bits definitions */ -#define CMP_CS_CMPEN BIT(0) /*!< CMP enable */ -#define CMP_CS_CMPSW BIT(1) /*!< CMP switch */ -#define CMP_CS_CMPM BITS(2,3) /*!< CMP mode */ -#define CMP_CS_CMPMSEL BITS(4,6) /*!< COMP_M input selection */ -#define CMP_CS_CMPOSEL BITS(8,10) /*!< CMP output selection */ -#define CMP_CS_CMPPL BIT(11) /*!< polarity of CMP output */ -#define CMP_CS_CMPHST BITS(12,13) /*!< CMP hysteresis */ -#define CMP_CS_CMPO BIT(14) /*!< CMP output */ -#define CMP_CS_CMPLK BIT(15) /*!< CMP lock */ - -/* consts definitions */ -/* operating mode */ -typedef enum{ - CMP_HIGHSPEED = 0, /*!< high speed mode */ - CMP_MIDDLESPEED, /*!< medium speed mode */ - CMP_LOWSPEED, /*!< low speed mode */ - CMP_VERYLOWSPEED /*!< very-low speed mode */ -}operating_mode_enum; - -/* inverting input */ -typedef enum{ - CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */ - CMP_1_2VREFINT, /*!< VREFINT /2 input */ - CMP_3_4VREFINT, /*!< VREFINT *3/4 input */ - CMP_VREFINT, /*!< VREFINT input */ - CMP_PA4, /*!< PA4 input */ - CMP_PA5, /*!< PA5 input */ - CMP_PA0, /*!< PA0 input */ - CMP_PA2 /*!< PA2 input */ -}inverting_input_enum; - -/* hysteresis */ -typedef enum{ - CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */ - CMP_HYSTERESIS_LOW, /*!< output low hysteresis */ - CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */ - CMP_HYSTERESIS_HIGH /*!< output high hysteresis */ -}cmp_hysteresis_enum; - -/* output */ -typedef enum{ - CMP_OUTPUT_NONE = 0x0U, /*!< output no selection */ - CMP_OUTPUT_TIMER0BKIN = 0x1U, /*!< TIMER 0 break input */ - CMP_OUTPUT_TIMER0IC0 = 0x2U, /*!< TIMER 0 channel0 input capture */ - CMP_OUTPUT_TIMER0OCPRECLR = 0x3U, /*!< TIMER 0 OCPRE_CLR input */ - CMP_OUTPUT_TIMER2IC0 = 0x06U, /*!< TIMER 2 channel0 input capture */ - CMP_OUTPUT_TIMER2OCPRECLR = 0x7U /*!< TIMER 2 OCPRE_CLR input */ -}cmp_output_enum; - -/* CMP mode */ -#define CS_CMPM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define CS_CMPM_HIGHSPEED CS_CMPM(0) /*!< CMP mode high speed */ -#define CS_CMPM_MIDDLESPEED CS_CMPM(1) /*!< CMP mode middle speed */ -#define CS_CMPM_LOWSPEED CS_CMPM(2) /*!< CMP mode low speed */ -#define CS_CMPM_VERYLOWSPEED CS_CMPM(3) /*!< CMP mode very low speed */ - -/* comparator inverting input */ -#define CS_CMPMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CS_CMPMSEL_1_4VREFINT CS_CMPMSEL(0) /*!< CMP inverting input 1/4 Vrefint */ -#define CS_CMPMSEL_1_2VREFINT CS_CMPMSEL(1) /*!< CMP inverting input 1/2 Vrefint */ -#define CS_CMPMSEL_3_4VREFINT CS_CMPMSEL(2) /*!< CMP inverting input 3/4 Vrefint */ -#define CS_CMPMSEL_VREFINT CS_CMPMSEL(3) /*!< CMP inverting input Vrefint */ -#define CS_CMPMSEL_PA4 CS_CMPMSEL(4) /*!< CMP inverting input PA4*/ -#define CS_CMPMSEL_PA5 CS_CMPMSEL(5) /*!< CMP inverting input PA5*/ -#define CS_CMPMSEL_PA0 CS_CMPMSEL(6) /*!< CMP inverting input PA0*/ -#define CS_CMPMSEL_PA2 CS_CMPMSEL(7) /*!< CMP inverting input PA2*/ - -/* CMP output */ -#define CS_CMPOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define CS_CMPOSEL_OUTPUT_NONE CS_CMPOSEL(0) /*!< CMP output none */ -#define CS_CMPOSEL_OUTPUT_TIMER0BKIN CS_CMPOSEL(1) /*!< CMP output TIMER 0 break input */ -#define CS_CMPOSEL_OUTPUT_TIMER0IC0 CS_CMPOSEL(2) /*!< CMP output TIMER 0 channel 0 input capture */ -#define CS_CMPOSEL_OUTPUT_TIMER0OCPRECLR CS_CMPOSEL(3) /*!< CMP output TIMER 0 ocpreclear input */ -#define CS_CMPOSEL_OUTPUT_TIMER2IC0 CS_CMPOSEL(6) /*!< CMP output TIMER 2 channle 0 input capture */ -#define CS_CMPOSEL_OUTPUT_TIMER2OCPRECLR CS_CMPOSEL(7) /*!< CMP output TIMER 2 ocpreclear input */ - -/* CMP hysteresis */ -#define CS_CMPHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define CS_CMPHST_HYSTERESIS_NO CS_CMPHST(0) /*!< CMP output no hysteresis */ -#define CS_CMPHST_HYSTERESIS_LOW CS_CMPHST(1) /*!< CMP output low hysteresis */ -#define CS_CMPHST_HYSTERESIS_MIDDLE CS_CMPHST(2) /*!< CMP output middle hysteresis */ -#define CS_CMPHST_HYSTERESIS_HIGH CS_CMPHST(3) /*!< CMP output high hysteresis */ - -/* CMP output level */ -#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */ -#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */ - -/* output polarity of comparator */ -#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */ -#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */ - -/* function declarations */ - -/* initialization functions */ -/* CMP deinit */ -void cmp_deinit(void); -/* CMP mode init */ -void cmp_mode_init(operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis); -/* CMP output init */ -void cmp_output_init(cmp_output_enum output_slection, uint32_t output_polarity); -/* enable CMP */ -void cmp_enable(void); -/* disable CMP */ -void cmp_disable(void); -/* enable CMP switch */ -void cmp_switch_enable(void); -/* disable CMP switch */ -void cmp_switch_disable(void); -/* get output level */ -uint32_t cmp_output_level_get(void); -/* lock the CMP */ -void cmp_lock_enable(void); - -#endif /* GD32E230_CMP_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h deleted file mode 100644 index 619ce47970..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h +++ /dev/null @@ -1,120 +0,0 @@ -/*! - \file gd32e230_crc.h - \brief definitions for the CRC - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_CRC_H -#define GD32E230_CRC_H - -#include "gd32e230.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32((CRC) + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32((CRC) + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32((CRC) + 0x08U) /*!< CRC control register */ -#define CRC_IDATA REG32((CRC) + 0x10U) /*!< CRC initialization data register */ -#define CRC_POLY REG32((CRC) + 0x14U) /*!< CRC polynomial register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ -#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */ -#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */ -#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */ - -/* CRC_INIT */ -#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */ - -/* CRC_POLY */ -#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */ - -/* constants definitions */ -/* size of polynomial function */ -#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3)) -#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */ - -/* input data reverse function */ -#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5)) -#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */ -#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */ -#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */ -#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */ - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* enable the reverse operation of output data */ -void crc_reverse_output_data_enable(void); -/* disable the reverse operation of output data */ -void crc_reverse_output_data_disable(void); - -/* reset data register to the value of initializaiton data register */ -void crc_data_register_reset(void); -/* read the data register */ -uint32_t crc_data_register_read(void); - -/* read the free data register */ -uint8_t crc_free_data_register_read(void); -/* write the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* write the initial value register */ -void crc_init_data_register_write(uint32_t init_data); -/* configure the CRC input data function */ -void crc_input_data_reverse_config(uint32_t data_reverse); - -/* configure the CRC size of polynomial function */ -void crc_polynomial_size_set(uint32_t poly_size); -/* configure the CRC polynomial value function */ -void crc_polynomial_set(uint32_t poly); - -/* CRC calculate a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* CRC calculate a 32-bit data array */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32E230_CRC_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h deleted file mode 100644 index 4a07da903e..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h +++ /dev/null @@ -1,123 +0,0 @@ -/*! - \file gd32e230_dbg.h - \brief definitions for the DBG - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_DBG_H -#define GD32E230_DBG_H - -#include "gd32e230.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ -#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL0 */ -#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */ -#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */ -#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ - -/* DBG_CTL1 */ -#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ -#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */ -#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */ -#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */ - -/* constants definitions */ -#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* define the peripheral debug hold bit position and its register index offset */ -#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) -#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) -#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register index */ -enum dbg_reg_idx -{ - DBG_IDX_CTL0 = 0x04U, - DBG_IDX_CTL1 = 0x08U, -}; - -/* peripherals hold bit */ -typedef enum -{ - DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */ - DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */ - DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */ - DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */ - DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */ - DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */ - DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */ - DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */ - DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */ - DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */ - DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */ - DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */ -}dbg_periph_enum; - -/* function declarations */ -/* deinitialize the DBG */ -void dbg_deinit(void); -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -#endif /* GD32E230_DBG_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h deleted file mode 100644 index 2205e1bdce..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h +++ /dev/null @@ -1,264 +0,0 @@ -/*! - \file gd32e230_dma.h - \brief definitions for the DMA - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_DMA_H -#define GD32E230_DMA_H - -#include "gd32e230.h" - -/* DMA definitions */ -#define DMA DMA_BASE /*!< DMA base address */ - -/* registers definitions */ -#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */ -#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */ -#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */ -#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */ -#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */ -#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL,x=0..4 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT,x=0..4 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR,x=0..4 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR,x=0..4 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA Channel0 */ - DMA_CH1, /*!< DMA Channel1 */ - DMA_CH2, /*!< DMA Channel2 */ - DMA_CH3, /*!< DMA Channel3 */ - DMA_CH4, /*!< DMA Channel4 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ -} dma_parameter_struct; - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) - -#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_CHCTL base address */ -#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */ -#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */ -#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */ -#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */ - -/* DMA channel shift bit */ -#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT - -/* function declarations */ -/* deinitialize DMA a channel registers */ -void dma_deinit(dma_channel_enum channelx); -/* initialize the parameters of DMA struct with the default values */ -void dma_struct_para_init(dma_parameter_struct* init_struct); -/* initialize DMA channel */ -void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct); -/* enable DMA circulation mode */ -void dma_circulation_enable(dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(dma_channel_enum channelx); - -/* set DMA peripheral base address */ -void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); -/* set DMA memory base address */ -void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction); - -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); - -#endif /* GD32E230_DMA_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_exti.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_exti.h deleted file mode 100644 index 4d8b875c4a..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_exti.h +++ /dev/null @@ -1,278 +0,0 @@ -/*! - \file gd32e230_exti.h - \brief definitions for the EXTI - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_EXTI_H -#define GD32E230_EXTI_H - -#include "gd32e230.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ -#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ -#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ -#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ -#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ -#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */ -#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */ -#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */ -#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */ -#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ -#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ -#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ -#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ -#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ -#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */ -#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */ -#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */ -#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */ -#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ -#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ -#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ -#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */ -#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum -{ - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ - EXTI_20 = BIT(20), /*!< EXTI line 20 */ - EXTI_21 = BIT(21), /*!< EXTI line 21 */ - EXTI_22 = BIT(22), /*!< EXTI line 22 */ - EXTI_23 = BIT(23), /*!< EXTI line 23 */ - EXTI_24 = BIT(24), /*!< EXTI line 24 */ - EXTI_25 = BIT(25), /*!< EXTI line 25 */ - EXTI_26 = BIT(26), /*!< EXTI line 26 */ - EXTI_27 = BIT(27), /*!< EXTI line 27 */ -}exti_line_enum; - -/* external interrupt and event */ -typedef enum -{ - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -}exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum -{ - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */ -}exti_trig_type_enum; - -/* function declarations */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - -/* get EXTI lines pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); -/* EXTI software interrupt event enable */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* EXTI software interrupt event disable */ -void exti_software_interrupt_disable(exti_line_enum linex); - -#endif /* GD32E230_EXTI_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h deleted file mode 100644 index 50f6d4b8bd..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h +++ /dev/null @@ -1,272 +0,0 @@ -/*! - \file gd32e230_fmc.h - \brief definitions for the FMC - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_FMC_H -#define GD32E230_FMC_H - -#include "gd32e230.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option byte base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ -#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC_USER REG32((OB) + 0x00U) /*!< option byte security protection value and user value */ -#define OB_DATA REG32((OB) + 0x04U) /*!< option byte data value*/ -#define OB_WP REG32((OB) + 0x08U) /*!< option byte write protection */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ -#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ -#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */ - -/* FMC_KEY */ -#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT */ -#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT_PGAERR BIT(3) /*!< program alignment error flag bit */ -#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */ -#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL */ -#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ -#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */ -#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */ -#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL_LK BIT(7) /*!< flash lock bit */ -#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ -#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */ - -/* FMC_ADDR */ -#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */ -#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */ -#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */ -#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */ -#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */ - -/* FMC_WP */ -#define FMC_WP_WP BITS(0,15) /*!< store WP[15:0] of option byte block after system reset */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_PGAERR, /*!< program alignment error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ - FMC_OB_HSPC /*!< option byte security protection code high */ -}fmc_state_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* wait state counter value */ -#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */ -#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */ -#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */ - -/* read protect configure */ -#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */ -#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */ -#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */ - -#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< low 16 bits mask */ -#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< high 16 bits mask */ - -/* option byte address */ -#define OB_SPC_USER_ADDRESS ((uint32_t)0x1FFFF800U) /*!< address of option byte security protection and user */ -#define OB_DATA_ADDRESS ((uint32_t)0x1FFFF804U) /*!< address of option byte data */ -#define OB_WP_ADDRESS ((uint32_t)0x1FFFF808U) /*!< address of option byte write protection */ - -/* option byte write protection */ -#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ -#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ - -/* option byte software/hardware free watchdog timer */ -#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */ -#define OB_FWDGT_SW ((uint8_t)BIT(0)) /*!< software free watchdog timer */ - -/* option byte reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */ -#define OB_DEEPSLEEP_NRST ((uint8_t)BIT(1)) /*!< no reset when entering deepsleep mode */ - -/* option byte reset or not entering standby mode */ -#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */ -#define OB_STDBY_NRST ((uint8_t)BIT(2)) /*!< no reset when entering deepsleep mode */ - -/* option byte OB_BOOT1_n set */ -#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */ -#define OB_BOOT1_SET_0 ((uint8_t)BIT(4)) /*!< BOOT1 bit is 0 */ - -/* option byte VDDA monitor enable/disable */ -#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */ -#define OB_VDDA_ENABLE ((uint8_t)BIT(5)) /*!< enable VDDA monitor */ - -/* option byte SRAM parity enable/disable */ -#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */ -#define OB_SRAM_PARITY_DISABLE ((uint8_t)BIT(6)) /*!< disable SRAM parity check */ - -/* option byte security protection level in FMC_OBSTAT register */ -#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */ -#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x01U) /*!< low security protection */ -#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x03U) /*!< high security protection */ - -/* option byte user mask */ -#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */ - -/* option byte data address */ -#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */ -#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */ - -/* FMC flags */ -#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ -#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ -#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */ -#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ -#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ - -/* FMC interrupt flags */ -#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ -#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */ -#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ -#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ - -/* FMC interrupt enable */ -#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */ -#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */ - -/* FMC time out */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* set the wait state counter value */ -void fmc_wscnt_set(uint8_t wscnt); - -/* pre-fetch enable */ -void fmc_prefetch_enable(void); -/* pre-fetch disable */ -void fmc_prefetch_disable(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC program a double word at the corresponding address */ -fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* reload the option byte and generate a system reset */ -void ob_reset(void); -/* get option byte value */ -uint32_t option_byte_value_get(uint32_t addr); -/* erase option byte */ -fmc_state_enum ob_erase(void); -/* enable option byte write protection (OB_WP) */ -fmc_state_enum ob_write_protection_enable(uint16_t ob_wp); -/* configure read out protect */ -fmc_state_enum ob_security_protection_config(uint16_t ob_spc); -/* write the FMC option byte user */ -fmc_state_enum ob_user_write(uint8_t ob_user); -/* write the FMC option byte data */ -fmc_state_enum ob_data_program(uint16_t data); -/* get the FMC option byte OB_USER */ -uint8_t ob_user_get(void); -/* get the FMC option byte OB_DATA */ -uint16_t ob_data_get(void); -/* get the FMC option byte write protection */ -uint16_t ob_write_protection_get(void); -/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */ -uint32_t ob_obstat_plevel_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* get flag set or reset */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC pending flag */ -void fmc_flag_clear(uint32_t flag); -/* get intrrupt flag set or reset */ -FlagStatus fmc_interrupt_flag_get(uint32_t int_flag); -/* clear the FMC interrupt pending flag by writing 1 */ -void fmc_interrupt_flag_clear(uint32_t int_flag); -/* return the FMC state */ -fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(uint32_t timeout); - -#endif /* GD32E230_FMC_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h deleted file mode 100644 index 101f87a34a..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h +++ /dev/null @@ -1,119 +0,0 @@ -/*! - \file gd32e230_fwdgt.h - \brief definitions for the FWDGT - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_FWDGT_H -#define GD32E230_FWDGT_H - -#include "gd32e230.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ -#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ -#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ - -/* FWDGT_WND */ -#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ - -/* constants definitions */ -/* FWDGT_PSC register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x00005555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x00000000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0x0000AAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0x0000CCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ -#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* configure the free watchdog timer counter prescaler value */ -ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); -/* configure the free watchdog timer counter reload value */ -ErrStatus fwdgt_reload_value_config(uint16_t reload_value); -/* configure the free watchdog timer counter window value */ -ErrStatus fwdgt_window_value_config(uint16_t window_value); -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32E230_FWDGT_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_gpio.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_gpio.h deleted file mode 100644 index 252383983d..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_gpio.h +++ /dev/null @@ -1,388 +0,0 @@ -/*! - \file gd32e230_gpio.h - \brief definitions for the GPIO - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_GPIO_H -#define GD32E230_GPIO_H - -#include "gd32e230.h" - -/* GPIOx(x=A,B,C,F) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOF (GPIO_BASE + 0x00001400U) - -/* registers definitions */ -#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */ -#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */ -#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */ -#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ -#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ -#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */ -#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */ - -/* bits definitions */ -/* GPIO_CTL */ -#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ -#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ -#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ -#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ -#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ -#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ -#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ -#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ -#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ -#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ -#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ -#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ -#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ -#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ -#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ -#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_OMODE */ -#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ -#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ -#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ -#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ -#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ -#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ -#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ -#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ -#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ -#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ -#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ -#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ -#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ -#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ -#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ -#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ - -/* GPIO_OSPD */ -#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ -#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ -#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ -#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ -#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ -#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ -#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ -#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ -#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ -#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ -#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ -#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ -#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ -#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ -#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ -#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ - -/* GPIO_PUD */ -#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ -#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ -#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ -#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ -#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ -#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ -#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ -#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ -#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ -#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ -#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ -#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ -#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ -#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ -#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ -#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* GPIO_AFSEL0 */ -#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ -#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ -#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ -#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ -#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ -#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ -#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ -#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ - -/* GPIO_AFSEL1 */ -#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ -#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ -#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ -#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ -#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ -#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ -#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ -#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_TG */ -#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ -#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ -#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ -#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ -#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ -#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ -#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ -#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ -#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ -#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ -#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ -#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ -#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ -#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ -#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ -#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* output mode definitions */ -#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ -#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ -#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ -#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ - -/* pull-up/pull-down definitions */ -#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ -#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ -#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* GPIO mode configuration values */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) -#define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) - -/* GPIO pull-up/pull-down values */ -#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) -#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) - -/* GPIO output speed values */ -#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) -#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) - -/* GPIO output type */ -#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ -#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ - -/* GPIO output max speed value */ -#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */ - -/* GPIO alternate function values */ -#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) -#define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) - -/* GPIO alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ -#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ -#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ -#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ -#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */ -#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */ -#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */ -#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* set GPIO mode */ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); -/* set GPIO output type and speed */ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* set GPIO alternate function */ -void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin); -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -/* toggle GPIO pin status */ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); -/* toggle GPIO port status */ -void gpio_port_toggle(uint32_t gpio_periph); - -#endif /* GD32E230_GPIO_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_i2c.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_i2c.h deleted file mode 100644 index ab07d46987..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_i2c.h +++ /dev/null @@ -1,389 +0,0 @@ -/*! - \file gd32e230_i2c.h - \brief definitions for the I2C - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_I2C_H -#define GD32E230_I2C_H - -#include "gd32e230.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE+0x400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ -#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x80U) /*!< I2C SAM control and status register */ -#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ - -/* I2Cx_SAMCS */ -#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ -#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ -#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ -#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ -#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ -#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ -#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ -#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ -#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ -#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ -#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ -#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ - -/* I2Cx_FMPCFG */ -#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET 0x80U /*!< SAMCS register offset */ - -/* I2C flags */ -typedef enum -{ - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ - /* flags in SAMCS register */ - I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ - I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ - I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ - I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ -}i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ - /* interrupt flags in SAMCS register */ - I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ - I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ - I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ - I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ -}i2c_interrupt_flag_enum; - -/* I2C interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ - /* interrupt in SAMCS register */ - I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ - I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ - I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ - I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt enable */ -}i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE I2C_CTL0_SS /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE ((uint32_t)0x00000000U) /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - -/* fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ -#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode or fast mode plus */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* enable dual-address mode */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); -/* disable dual-address mode */ -void i2c_dualaddr_disable(uint32_t i2c_periph); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); - -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* enable SAM_V interface */ -void i2c_sam_enable(uint32_t i2c_periph); -/* disable SAM_V interface */ -void i2c_sam_disable(uint32_t i2c_periph); -/* enable SAM_V interface timeout detect */ -void i2c_sam_timeout_enable(uint32_t i2c_periph); -/* disable SAM_V interface timeout detect */ -void i2c_sam_timeout_disable(uint32_t i2c_periph); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); - -#endif /* GD32E230_I2C_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h deleted file mode 100644 index 4bc91a9600..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h +++ /dev/null @@ -1,86 +0,0 @@ -/*! - \file gd32e230_misc.h - \brief definitions for the MISC - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_MISC_H -#define GD32E230_MISC_H - -#include "gd32e230.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */ - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */ -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */ -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */ - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ - -/* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_priority); -/* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); -/* initiates a system reset request to reset the MCU */ -void nvic_system_reset(void); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32E230_MISC_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h deleted file mode 100644 index 1db5b1fb47..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h +++ /dev/null @@ -1,146 +0,0 @@ -/*! - \file gd32e230_pmu.h - \brief definitions for the PMU - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_PMU_H -#define GD32E230_PMU_H - -#include "gd32e230.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */ -#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - -/* PMU LDO output voltage select definitions */ -#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */ -#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */ - -/* PMU WKUP pin definitions */ -#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ -#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ -#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ -#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU registers */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* select LDO output voltage */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* set PMU mode */ -/* PMU work in sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work in deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work in standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(uint32_t wakeup_pin); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(uint32_t wakeup_pin); - -/* backup related functions */ -/* enable backup domain write */ -void pmu_backup_write_enable(void); -/* disable backup domain write */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag_clear); -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); - -#endif /* GD32E230_PMU_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rcu.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rcu.h deleted file mode 100644 index 53f2e34e34..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rcu.h +++ /dev/null @@ -1,672 +0,0 @@ -/*! - \file gd32e230_rcu.h - \brief definitions for the RCU - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_RCU_H -#define GD32E230_RCU_H - -#include "gd32e230.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#define RCU_CTL0 REG32(RCU + 0x00U) /*!< control register 0 */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source /clock register */ -#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< configuration register 1 */ -#define RCU_CFG2 REG32(RCU + 0x30U) /*!< configuration register 2 */ -#define RCU_CTL1 REG32(RCU + 0x34U) /*!< control register 1 */ -#define RCU_VKEY REG32(RCU + 0x100U) /*!< voltage key register */ -#define RCU_DSV REG32(RCU + 0x134U) /*!< deep-sleep mode voltage register */ - -/* bits definitions */ -/* RCU_CTL0 */ -#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ - -/* RCU_CFG0 */ -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */ -#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */ -#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ -#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ -#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ - -/* RCU_INT */ -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */ -#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */ -#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */ -#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ -#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ -#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ -#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */ -#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */ -#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */ -#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */ -#define RCU_APB2EN_DBGMCUEN BIT(22) /*!< DBGMCU clock enable */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */ -#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -/* RCU_AHBRST */ -#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ -#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ -#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ -#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ - -/* RCU_CFG1 */ -#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ - -/* RCU_CFG2 */ -#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ -#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ -#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */ -#define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */ - -/* RCU_CTL1 */ -#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */ -#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */ -#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */ -#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */ - -/* RCU_VKEY */ -#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -/* define the voltage key unlock value */ -#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D) - -/* register index */ -typedef enum -{ - /* peripherals enable */ - IDX_AHBEN = 0x14U, - IDX_APB2EN = 0x18U, - IDX_APB1EN = 0x1CU, - /* peripherals reset */ - IDX_AHBRST = 0x28U, - IDX_APB2RST = 0x0CU, - IDX_APB1RST = 0x10U, - /* clock stabilization */ - IDX_CTL0 = 0x00U, - IDX_BDCTL = 0x20U, - IDX_CTL1 = 0x34U, - /* peripheral reset */ - IDX_RSTSCK = 0x24U, - /* clock stabilization and stuck interrupt */ - IDX_INT = 0x08U, - /* configuration register */ - IDX_CFG0 = 0x04U, - IDX_CFG2 = 0x30U -}reg_idx; - -/* peripheral clock enable */ -typedef enum -{ - /* AHB peripherals */ - RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */ - RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */ - RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */ - RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */ - - /* APB2 peripherals */ - RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */ - RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */ - RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */ - RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */ - RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */ - RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */ - RCU_DBGMCU = RCU_REGIDX_BIT(IDX_APB2EN, 22U), /*!< DBGMCU clock */ - - /* APB1 peripherals */ - RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */ - RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */ - RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */ - RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */ - - /* Backup domain control(BDCTL) */ - RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U) /*!< RTC clock */ -}rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum -{ - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */ -}rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum -{ - /* AHB peripherals reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */ - - /* APB2 peripherals reset */ - RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */ - RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */ - RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */ - RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */ - RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */ - RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */ - - /* APB1 peripherals reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */ - RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */ - RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */ - RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */ -}rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum -{ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */ - RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */ - - RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */ - RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */ -}rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */ - RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */ -}rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */ -}rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum -{ - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */ - RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */ -}rcu_int_enum; - -/* ADC clock source */ -typedef enum -{ - RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */ - RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */ - RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */ - RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */ - RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */ - RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */ - RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */ - RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */ - RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */ - RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */ -}rcu_adc_clock_enum; - -/* oscillator types */ -typedef enum -{ - RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */ - RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */ - RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */ -}rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum -{ - CK_SYS = 0U, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ - CK_ADC, /*!< ADC clock */ - CK_USART /*!< USART clock */ -}rcu_clock_freq_enum; - -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC clock prescaler selection */ -#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) -#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ -#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ -#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ -#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000U /*!< PLL clock source select IRC8M/2 */ -#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL */ - -/* HXTAL divider for PLL source clock selection */ -#define RCU_PLLPREDV (uint32_t)0x00000000U /*!< HXTAL clock selected */ -#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< HXTAL/2 clock selected */ - -/* PLL multiply factor */ -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ - -/* CK_OUT clock source selection */ -#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ -#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */ -#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */ -#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ -#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ -#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */ -#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ -#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ -#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ - -/* CK_OUT divider */ -#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) -#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ -#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ -#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ -#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ -#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ -#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ -#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ -#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ - -/* CK_PLL divide by 1 or 2 for CK_OUT */ -#define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U /*!< CK_PLL divide by 2 for CK_OUT */ -#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ - -/* LXTAL drive capability */ -#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ -#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ -#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ -#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */ -#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ - -/* CK_HXTAL divider previous PLL */ -#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ -#define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ -#define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ -#define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ -#define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ -#define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ -#define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ -#define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ -#define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ -#define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ -#define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ -#define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ -#define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ -#define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ -#define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ -#define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ - -/* USART0 clock source selection */ -#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ -#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ -#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ -#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */ - -/* ADC clock source selection */ -#define RCU_ADCSRC_IRC28M (uint32_t)0x00000000U /*!< ADC clock source select */ -#define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ - -/* IRC28M clock divider for ADC */ -#define RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U /*!< IRC28M/2 select to ADC clock */ -#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */ - -/* Deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(3) /*!< core voltage is 1.2V in deep-sleep mode */ - -/* function declarations */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP */ -void rcu_bkp_reset_enable(void); -/* disable the BKP reset */ -void rcu_bkp_reset_disable(void); - -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the ADC clock source and prescaler selection */ -void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc); -/* configure the CK_OUT clock source and divider */ -void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); - -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -/* configure the USART clock source selection */ -void rcu_usart_clock_config(uint32_t ck_usart); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -/* configure the HXTAL divider used as input of PLL */ -void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* wait until oscillator stabilization flags is SET */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); -/* set the IRC28M adjust value */ -void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval); -/* unlock the voltage key */ -void rcu_voltage_key_unlock(void); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32E230_RCU_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rtc.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rtc.h deleted file mode 100644 index 27756b1609..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_rtc.h +++ /dev/null @@ -1,561 +0,0 @@ -/*! - \file gd32e230_rtc.h - \brief definitions for the RTC - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_RTC_H -#define GD32E230_RTC_H - -#include "gd32e230.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_TIME REG32((RTC) + 0x00000000U) /*!< RTC time of day register */ -#define RTC_DATE REG32((RTC) + 0x00000004U) /*!< RTC date register */ -#define RTC_CTL REG32((RTC) + 0x00000008U) /*!< RTC control register */ -#define RTC_STAT REG32((RTC) + 0x0000000CU) /*!< RTC status register */ -#define RTC_PSC REG32((RTC) + 0x00000010U) /*!< RTC time prescaler register */ -#define RTC_ALRM0TD REG32((RTC) + 0x0000001CU) /*!< RTC alarm 0 time and date register */ -#define RTC_WPK REG32((RTC) + 0x00000024U) /*!< RTC write protection key register */ -#define RTC_SS REG32((RTC) + 0x00000028U) /*!< RTC sub second register */ -#define RTC_SHIFTCTL REG32((RTC) + 0x0000002CU) /*!< RTC shift function control register */ -#define RTC_TTS REG32((RTC) + 0x00000030U) /*!< RTC time of timestamp register */ -#define RTC_DTS REG32((RTC) + 0x00000034U) /*!< RTC date of timestamp register */ -#define RTC_SSTS REG32((RTC) + 0x00000038U) /*!< RTC sub second of timestamp register */ -#define RTC_HRFC REG32((RTC) + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */ -#define RTC_TAMP REG32((RTC) + 0x00000040U) /*!< RTC tamper register */ -#define RTC_ALRM0SS REG32((RTC) + 0x00000044U) /*!< RTC alarm 0 sub second register */ -#define RTC_BKP0 REG32((RTC) + 0x00000050U) /*!< RTC backup 0 register */ -#define RTC_BKP1 REG32((RTC) + 0x00000054U) /*!< RTC backup 1 register */ -#define RTC_BKP2 REG32((RTC) + 0x00000058U) /*!< RTC backup 2 register */ -#define RTC_BKP3 REG32((RTC) + 0x0000005CU) /*!< RTC backup 3 register */ -#define RTC_BKP4 REG32((RTC) + 0x00000060U) /*!< RTC backup 4 register */ - -/* bits definitions */ -/* RTC_TIME */ -#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DATE */ -#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ -#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ -#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ - -/* RTC_CTL */ -#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ -#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ -#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ -#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ -#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */ -#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ -#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */ -#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ -#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ -#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ -#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ -#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ -#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ -#define RTC_CTL_OS BITS(21,22) /*!< output selection */ -#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ - -/* RTC_STAT */ -#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ -#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ -#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ -#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ -#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ -#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ -#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */ -#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ -#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ -#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ -#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ -#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */ - -/* RTC_PSC */ -#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ -#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ - -/* RTC_ALRM0TD */ -#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */ -#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */ -#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */ -#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */ -#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */ -#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */ -#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */ -#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ -#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */ -#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */ -#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */ - -/* RTC_WPK */ -#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ - -/* RTC_SS */ -#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ - -/* RTC_SHIFTCTL */ -#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ -#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ - -/* RTC_TTS */ -#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ -#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DTS */ -#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ - -/* RTC_SSTS */ -#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ - -/* RTC_HRFC */ -#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ -#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ - -/* RTC_TAMP */ -#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ -#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ -#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ -#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ -#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ -#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ -#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ -#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ -#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ -#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ -#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */ -#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */ -#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */ -#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */ -#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */ -#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */ - -/* RTC_ALRM0SS */ -#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */ -#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ - -/* RTC_BKP0 */ -#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP1 */ -#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP2 */ -#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP3 */ -#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP4 */ -#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ - -/* constants definitions */ -/* structure for initialization of the RTC */ -typedef struct -{ - uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ - uint8_t rtc_month; /*!< RTC month value */ - uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ - uint8_t rtc_day_of_week; /*!< RTC weekday value */ - uint8_t rtc_hour; /*!< RTC hour value */ - uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ - uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ - uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ - uint32_t rtc_am_pm; /*!< RTC AM/PM value */ - uint32_t rtc_display_format; /*!< RTC time notation */ -}rtc_parameter_struct; - -/* structure for RTC alarm configuration */ -typedef struct -{ - uint32_t rtc_alarm_mask; /*!< RTC alarm mask */ - uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */ - uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/ - uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */ - uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ - uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */ -}rtc_alarm_struct; - -/* structure for RTC time-stamp configuration */ -typedef struct -{ - uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */ - uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ - uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */ - uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */ - uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ - uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */ -}rtc_timestamp_struct; - -/* structure for RTC tamper configuration */ -typedef struct -{ - uint32_t rtc_tamper_source; /*!< RTC tamper source */ - uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */ - uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ - uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ - ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ - uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ - ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ -}rtc_tamper_struct; - -/* time register value */ -#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */ -#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ - -#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */ -#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ - -#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */ -#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ - -#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ -#define RTC_PM RTC_TIME_PM /*!< PM format */ - -/* date register value */ -#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */ -#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ - -#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */ -#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ -#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ -#define RTC_FEB ((uint8_t)0x02U) /*!< February */ -#define RTC_MAR ((uint8_t)0x03U) /*!< March */ -#define RTC_APR ((uint8_t)0x04U) /*!< April */ -#define RTC_MAY ((uint8_t)0x05U) /*!< May */ -#define RTC_JUN ((uint8_t)0x06U) /*!< June */ -#define RTC_JUL ((uint8_t)0x07U) /*!< July */ -#define RTC_AUG ((uint8_t)0x08U) /*!< August */ -#define RTC_SEP ((uint8_t)0x09U) /*!< September */ -#define RTC_OCT ((uint8_t)0x10U) /*!< October */ -#define RTC_NOV ((uint8_t)0x11U) /*!< November */ -#define RTC_DEC ((uint8_t)0x12U) /*!< December */ - -#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */ -#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ -#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */ -#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ -#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */ -#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */ -#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */ -#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ -#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ - -#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */ -#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ - -/* ctl register value */ -#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */ -#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ -#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */ - -#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ -#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */ -#define RTC_ALARM_HIGH RTC_CTL_OS /*!< enable alarm flag output with high level */ -#define RTC_ALARM_LOW (RTC_CTL_OS | RTC_CTL_OPOL) /*!< enable alarm flag output with low level*/ - -#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ -#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ - -#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ -#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ - -/* psc register value */ -#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */ -#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ - -#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */ -#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ - -/* alrm0td register value */ -#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */ -#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */ - -#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */ -#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */ - -#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */ -#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */ - -#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */ -#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */ - -#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ -#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */ -#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */ -#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */ -#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */ -#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */ - -#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ -#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */ - -/* wpk register value */ -#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */ - -/* ss register value */ -#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */ - -/* shiftctl register value */ -#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ - -#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ -#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ - -/* tts register value */ -#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */ -#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ - -#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */ -#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ - -#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */ -#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ - -/* dts register value */ -#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */ -#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ - -#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */ -#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ - -#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */ -#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ - -/* ssts register value */ -#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */ - -/* hrfc register value */ -#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */ - -#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ - -#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ -#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ - -/* tamp register value */ -#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */ -#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ - -#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */ -#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ -#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ -#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ -#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ - -#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */ -#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ - -#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ -#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ - -#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ -#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */ - -#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ - -#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ -#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */ - -/* alrm0ss register value */ -#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */ - -#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */ -#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */ -#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */ -#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */ -#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */ -#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */ -#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */ -#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */ -#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */ -#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */ -#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */ -#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */ -#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */ -#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */ -#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */ -#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */ -#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */ - -/* RTC interrupt source */ -#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ -#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */ -#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ - -/* write protect key */ -#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ -#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ -#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ - -/* registers reset value */ -#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ -#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ -#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ -#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ - -/* RTC timeout value */ -#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ -#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ -#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */ -#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ -#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ - -/* RTC flag */ -#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */ -#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */ -#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */ -#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */ -#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */ -#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ -#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ -#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ -#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */ -#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */ - -/* function declarations */ -/* reset most of the RTC registers */ -ErrStatus rtc_deinit(void); -/* initialize RTC registers */ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); -/* enter RTC init mode */ -ErrStatus rtc_init_mode_enter(void); -/* exit RTC init mode */ -void rtc_init_mode_exit(void); -/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ -ErrStatus rtc_register_sync_wait(void); - -/* get current time and date */ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); -/* get current subsecond value */ -uint32_t rtc_subsecond_get(void); - -/* configure RTC alarm */ -void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time); -/* configure subsecond of RTC alarm */ -void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond); -/* get RTC alarm */ -void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time); -/* get RTC alarm subsecond */ -uint32_t rtc_alarm_subsecond_get(void); -/* enable RTC alarm */ -void rtc_alarm_enable(void); -/* disable RTC alarm */ -ErrStatus rtc_alarm_disable(void); - -/* enable RTC time-stamp */ -void rtc_timestamp_enable(uint32_t edge); -/* disable RTC time-stamp */ -void rtc_timestamp_disable(void); -/* get RTC timestamp time and date */ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); -/* get RTC time-stamp subsecond */ -uint32_t rtc_timestamp_subsecond_get(void); - -/* enable RTC tamper */ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); -/* disable RTC tamper */ -void rtc_tamper_disable(uint32_t source); - -/* enable specified RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disble specified RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); -/* check specified flag */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear specified flag */ -void rtc_flag_clear(uint32_t flag); - -/* configure RTC alternate output source */ -void rtc_alter_output_config(uint32_t source, uint32_t mode); -/* configure RTC calibration register */ -ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); -/* ajust the daylight saving time by adding or substracting one hour from the current time */ -void rtc_hour_adjust(uint32_t operation); -/* ajust RTC second or subsecond value of current time */ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); -/* enable RTC bypass shadow registers function */ -void rtc_bypass_shadow_enable(void); -/* disable RTC bypass shadow registers function */ -void rtc_bypass_shadow_disable(void); -/* enable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_enable(void); -/* disable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_disable(void); - -#endif /* GD32E230_RTC_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_spi.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_spi.h deleted file mode 100644 index 5be789ff11..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_spi.h +++ /dev/null @@ -1,424 +0,0 @@ -/*! - \file gd32e230_spi.h - \brief definitions for the SPI - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_SPI_H -#define GD32E230_SPI_H - -#include "gd32e230.h" - -/* SPIx(x=0,1) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register(only SPI1) */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection */ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -/* only available in SPI0*/ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -/* only available in SPI1*/ -#define SPI_CTL0_CRCL BIT(11) /*!< CRC length */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ -#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ -/* only available in SPI1 */ -#define SPI_CTL1_DZ BITS(8,11) /*!< data size */ -#define SPI_CTL1_BYTEN BIT(12) /*!< byte access to FIFO enable */ -#define SPI_CTL1_RXDMA_ODD BIT(13) /*!< odd bytes in RX DMA channel */ -#define SPI_CTL1_TXDMA_ODD BIT(14) /*!< odd bytes in TX DMA channel */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error bit */ -/* only available in SPI1 */ -#define SPI_STAT_RXLVL BITS(9,10) /*!< RXFIFO level */ -#define SPI_STAT_TXLVL BITS(11,12) /*!< TXFIFO level */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* SPIx_QCTL(x=1) */ -#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ -#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ -#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ - -/* constants definitions */ -/* SPIx and I2Sx parameter struct definitions */ -typedef struct -{ - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -/* SPIx frame size */ -#define CTL1_FRAMESIZE(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define SPI_FRAMESIZE_4BIT CTL1_FRAMESIZE(3) /*!< SPI frame size is 4 bits */ -#define SPI_FRAMESIZE_5BIT CTL1_FRAMESIZE(4) /*!< SPI frame size is 5 bits */ -#define SPI_FRAMESIZE_6BIT CTL1_FRAMESIZE(5) /*!< SPI frame size is 6 bits */ -#define SPI_FRAMESIZE_7BIT CTL1_FRAMESIZE(6) /*!< SPI frame size is 7 bits */ -#define SPI_FRAMESIZE_8BIT CTL1_FRAMESIZE(7) /*!< SPI frame size is 8 bits */ -#define SPI_FRAMESIZE_9BIT CTL1_FRAMESIZE(8) /*!< SPI frame size is 9 bits */ -#define SPI_FRAMESIZE_10BIT CTL1_FRAMESIZE(9) /*!< SPI frame size is 10 bits */ -#define SPI_FRAMESIZE_11BIT CTL1_FRAMESIZE(10) /*!< SPI frame size is 11 bits */ -#define SPI_FRAMESIZE_12BIT CTL1_FRAMESIZE(11) /*!< SPI frame size is 12 bits */ -#define SPI_FRAMESIZE_13BIT CTL1_FRAMESIZE(12) /*!< SPI frame size is 13 bits */ -#define SPI_FRAMESIZE_14BIT CTL1_FRAMESIZE(13) /*!< SPI frame size is 14 bits */ -#define SPI_FRAMESIZE_15BIT CTL1_FRAMESIZE(14) /*!< SPI frame size is 15 bits */ -#define SPI_FRAMESIZE_16BIT CTL1_FRAMESIZE(15) /*!< SPI frame size is 16 bits */ - -/* SPIx CRC length(x=1) */ -#define SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< SPI CRC length is 8 bits */ -#define SPI_CRC_16BIT SPI_CTL0_CRCL /*!< SPI CRC length is 16 bits */ - -/* SPIx byte access enable(x=1) */ -#define SPI_HALFWORD_ACCESS ((uint32_t)0x00000000U) /*!< SPI half-word access to FIFO */ -#define SPI_BYTE_ACCESS SPI_CTL1_BYTEN /*!< SPI byte access to FIFO */ - -/* SPIx odd bytes in TX DMA channel(x=1) */ -#define SPI_TXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in TX DMA channel is even */ -#define SPI_TXDMA_ODD SPI_CTL1_TXDMA_ODD /*!< SPI number of byte in TX DMA channel is odd */ - -/* SPIx odd bytes in RX DMA channel(x=1) */ -#define SPI_RXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in RX DMA channel is even */ -#define SPI_RXDMA_ODD SPI_CTL1_RXDMA_ODD /*!< SPI number of byte in RX DMA channel is odd */ - -/* SPIx TXFIFO level(x=1) */ -#define CTL1_TXLVL(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -#define SPI_TXLVL_EMPTY CTL1_RXLVL(0) /*!< SPI TXFIFO is empty */ -#define SPI_TXLVL_QUARTER_FULL CTL1_RXLVL(1) /*!< SPI TXFIFO is a quarter of full */ -#define SPI_TXLVL_HAlF_FULL CTL1_RXLVL(2) /*!< SPI TXFIFO is a half of full */ -#define SPI_TXLVL_FULL CTL1_RXLVL(3) /*!< SPI TXFIFO is full */ - -/* SPIx RXFIFO level(x=1) */ -#define CTL1_RXLVL(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define SPI_RXLVL_EMPTY CTL1_RXLVL(0) /*!< SPI RXFIFO is empty */ -#define SPI_RXLVL_QUARTER_FULL CTL1_RXLVL(1) /*!< SPI RXFIFO is a quarter of full */ -#define SPI_RXLVL_HAlF_FULL CTL1_RXLVL(2) /*!< SPI RXFIFO is a half of full */ -#define SPI_RXLVL_FULL CTL1_RXLVL(3) /*!< SPI RXFIFO is full */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ - -/* function declarations */ -/* SPI/I2S deinitialization and initialization functions */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); -/* initialize SPI parameter */ -ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* NSS functions */ -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); - -/* configure SPI/I2S data frame format */ -ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); - -/* SPI TI mode functions */ -/* enable SPI TI mode */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* disable SPI TI mode */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* SPI NSS pulse mode functions */ -/* enable SPI NSS pulse mode */ -void spi_nssp_mode_enable(uint32_t spi_periph); -/* disable SPI NSS pulse mode */ -void spi_nssp_mode_disable(uint32_t spi_periph); - -/* quad wire SPI functions */ -/* enable quad wire SPI */ -void qspi_enable(uint32_t spi_periph); -/* disable quad wire SPI */ -void qspi_disable(uint32_t spi_periph); -/* enable quad wire SPI write */ -void qspi_write_enable(uint32_t spi_periph); -/* enable quad wire SPI read */ -void qspi_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void qspi_io23_output_disable(uint32_t spi_periph); - -/* flag and interrupt functions */ -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -/* only for SPI1 FIFO added */ -/* configure SPI access size to FIFO(8-bit or 16-bit) */ -void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size); -/* configure SPI total number of data transmitting by DMA is odd or not */ -void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd); -/* configure SPI total number of data receiving by DMA is odd or not */ -void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd); -/* set CRC length */ -void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length); - -#endif /* GD32E230_SPI_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_syscfg.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_syscfg.h deleted file mode 100644 index 9109a89602..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_syscfg.h +++ /dev/null @@ -1,187 +0,0 @@ -/*! - \file GD32e230_syscfg.h - \brief definitions for the SYSCFG - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_SYSCFG_H -#define GD32E230_SYSCFG_H - -#include "gd32e230.h" - -/* SYSCFG definitions */ -#define SYSCFG SYSCFG_BASE - -/* registers definitions */ -#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */ -#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */ -#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */ -#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */ -#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */ -#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U) /*!< system configuration register 2 */ -#define SYSCFG_CPU_IRQ_LAT REG32(SYSCFG + 0x100U) /*!< IRQ Latency register */ - -/* SYSCFG_CFG0 bits definitions */ -#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */ -#define SYSCFG_CFG0_PA11_PA12_RMP BIT(4) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */ -#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */ -#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */ -#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */ -#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */ -#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */ -#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */ - -/* SYSCFG_EXTISS0 bits definitions */ -#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ - -/* SYSCFG_EXTISS1 bits definitions */ -#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ - -/* SYSCFG_EXTISS2 bits definitions */ -#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ - -/* SYSCFG_EXTISS3 bits definitions */ -#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ - -/* SYSCFG_CFG2 bits definitions */ -#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M23 with break input of TIMER0/14/15/16 */ -#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */ -#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */ -#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */ - -/* SYSCFG_CPU_IRQ_LAT bits definitions */ -#define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY BITS(0,7) /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */ - -/* constants definitions */ -/* DMA remap definitions */ -#define SYSCFG_PA11_REMAP_PA12 SYSCFG_CFG0_PA11_PA12_RMP /*!< PA11 PA12 remap */ -#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */ -#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */ -#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */ -#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */ -#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */ - -/* high current definitions */ -#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */ -#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */ - -/* EXTI source select definition */ -#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ -#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ -#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ -#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ - -/* EXTI source select mask bits definition */ -#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ - -/* EXTI source select jumping step definition */ -#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ - -/* EXTI source select moving step definition */ -#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ - -/* EXTI source port definitions */ -#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ -#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ -#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ -#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ - -/* EXTI source pin definitions */ -#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ -#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ -#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ -#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ -#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ -#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ -#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ -#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ -#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ -#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ -#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ -#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ -#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ -#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ -#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ -#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ - -/* lock definitions */ -#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ -#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */ -#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ - -/* SRAM parity check error flag definitions */ -#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */ - -/* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */ -#define IRQ_LATENCY(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to IRQ_LATENCY bits field */ - -/* function declarations */ -/* deinit syscfg module */ -void syscfg_deinit(void); - -/* enable the DMA channels remapping */ -void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap); -/* disable the DMA channels remapping */ -void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap); - -/* enable PB9 high current capability */ -void syscfg_high_current_enable(void); -/* disable PB9 high current capability */ -void syscfg_high_current_disable(void); - -/* configure the GPIO pin as EXTI Line */ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); -/* connect TIMER0/14/15/16 break input to the selected parameter */ -void syscfg_lock_config(uint32_t syscfg_lock); - -/* set the IRQ_LATENCY value */ -void irq_latency_set(uint8_t irq_latency); - -/* check if the specified flag in SYSCFG_CFG2 is set or not */ -FlagStatus syscfg_flag_get(uint32_t syscfg_flag); -/* clear the flag in SYSCFG_CFG2 by writing 1 */ -void syscfg_flag_clear(uint32_t syscfg_flag); - -#endif /* GD32E230_SYSCFG_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_timer.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_timer.h deleted file mode 100644 index c69aa8f895..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_timer.h +++ /dev/null @@ -1,760 +0,0 @@ -/*! - \file gd32e230_timer.h - \brief definitions for the TIMER - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_TIMER_H -#define GD32E230_TIMER_H - -#include "gd32e230.h" - -/* TIMERx(x=0,1,2,5,13..16) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER13 (TIMER_BASE + 0x00002000U) -#define TIMER14 (TIMER_BASE + 0x00014000U) -#define TIMER15 (TIMER_BASE + 0x00014400U) -#define TIMER16 (TIMER_BASE + 0x00014800U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ -#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ -#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ -#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* TIMER_IRMP */ -#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */ - -/* TIMER_CFG */ -#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ -#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ - -/* constants definitions */ -/* TIMER init parameter struct definitions*/ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint16_t clockdivision; /*!< clock division value */ - uint32_t period; /*!< period value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions*/ -typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint16_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint16_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ -#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ -#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ -#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ -#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ -#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ -#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF - -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel y is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel y is sent when channel y event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0,2,13..16)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0,2,14)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0,2)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0,2)) */ -#define TIMER_CH_0_1 ((uint16_t)0x0004U) /*!< TIMER channel 0 and 1 for function parameter */ - -/* channel enable state*/ -#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ - -/* channel complementary output enable state*/ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers are updated when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ - -/* TIMER input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* OCPRE clear source selection */ -#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */ -#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */ -#define TIMER_OCPRE_CLEAR_SOURCE_DISABLE ((uint8_t)0x02U) /*!< OCRC=0, and disable ETI */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ - -/* TIMERx(x=0,2,13,14,15,16) write cc register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CC register selection enable */ - -/* the output value selection */ -#define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection enable */ - -/* timer13 channel 0 input remap */ -#define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) -#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0) /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */ -#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1) /*!< timer13 channel 0 input is connected to the RTCCLK */ -#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2) /*!< timer13 channel 0 input is connected to HXTAL/32 clock */ -#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3) /*!< timer13 channel 0 input is connected to CKOUTSEL */ - -/* function declarations */ -/* TIMER timebase*/ -/* deinit a TIMER */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct* initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a TIMER */ -void timer_enable(uint32_t timer_periph); -/* disable a TIMER */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph , uint16_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint32_t update); -/* OCPRE clear source selection */ -void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear); - -/* TIMER interrupt and flag*/ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -/* timer DMA and event*/ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); - -/* TIMER master and slave */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); -/* configure TIMER channel remap function */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); - -/* TIMER configure */ -/* configure TIMER write CHxVAL register selection */ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); -/* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); - -#endif /* GD32E230_TIMER_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_usart.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_usart.h deleted file mode 100644 index 6cb6f61056..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_usart.h +++ /dev/null @@ -1,614 +0,0 @@ -/*! - \file gd32e230_usart.h - \brief definitions for the USART - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_USART_H -#define GD32E230_USART_H - -#include "gd32e230.h" - -/* USARTx(x=0,1) definitions */ -#define USART0 (USART_BASE + 0x0000F400U) -#define USART1 USART_BASE - -/* registers definitions */ -#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ -#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ -#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ -#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ -#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ -#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ -#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ -#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ -#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ -#define USART_CHC(usartx) REG32((usartx) + 0x000000C0U) /*!< USART coherence control register */ -#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ - -/* bits definitions */ -/* USARTx_CTL0 */ -#define USART_CTL0_UEN BIT(0) /*!< USART enable */ -#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */ -#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */ -#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ -#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */ -#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */ -#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */ -#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ -#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ -#define USART_CTL1_CPH BIT(9) /*!< clock phase */ -#define USART_CTL1_CPL BIT(10) /*!< clock polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ -#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ -#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ -#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ -#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ -#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ -#define USART_CTL1_ABDEN BIT(20) /*!< auto baud rate enable */ -#define USART_CTL1_ABDM BITS(21,22) /*!< auto baud rate mode */ -#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ -#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ -#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ -#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */ -#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ -#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */ -#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */ -#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ -#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ -#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ - -/* USARTx_CMD */ -#define USART_CMD_ABDCMD BIT(0) /*!< auto baudrate detection command */ -#define USART_CMD_SBKCMD BIT(1) /*!< send break command */ -#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ -#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ -#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ - -/* USARTx_STAT */ -#define USART_STAT_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ -#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT_TC BIT(6) /*!< transmission completed */ -#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ -#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ -#define USART_STAT_CTS BIT(10) /*!< CTS level */ -#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT_ABDE BIT(14) /*!< auto baudrate detection error */ -#define USART_STAT_ABDF BIT(15) /*!< auto baudrate detection flag */ -#define USART_STAT_BSY BIT(16) /*!< busy flag */ -#define USART_STAT_AMF BIT(17) /*!< address match flag */ -#define USART_STAT_SBF BIT(18) /*!< send break flag */ -#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ -#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ -#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ -#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ - -/* USARTx_INTC */ -#define USART_INTC_PEC BIT(0) /*!< parity error clear */ -#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */ -#define USART_INTC_NEC BIT(2) /*!< noise detected clear */ -#define USART_INTC_OREC BIT(3) /*!< overrun error clear */ -#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */ -#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */ -#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */ -#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */ -#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */ -#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */ -#define USART_INTC_AMC BIT(17) /*!< address match clear */ -#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ - -/* USARTx_RDATA */ -#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ - -/* USARTx_TDATA */ -#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ - -/* USARTx_CHC */ -#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ -#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ - -/* USARTx_RFCS */ -#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ -#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */ -#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */ -#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ -#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ -#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ -#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ - -/* constants definitions */ - -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) - -/* register offset */ -#define USART_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */ -#define USART_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */ -#define USART_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */ -#define USART_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */ - -/* USART flags */ -typedef enum{ - /* flags in STAT register */ - USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ - USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ - USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */ - USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ - USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ - USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ - USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_ABD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 15U), /*!< auto baudrate detection flag */ - USART_FLAG_ABDE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 14U), /*!< auto baudrate detection error */ - USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ - USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ - USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ - /* flags in CHC register */ - USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ - /* flags in RFCS register */ - USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ - USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ - USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */ - USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */ - USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ - /* interrupt flags in RFCS register */ - USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ - USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ - USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ - /* interrupt in RFCS register */ - USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ -}usart_interrupt_enum; - -/* USART invert configure */ -typedef enum { - /* data bit level inversion */ - USART_DINV_ENABLE, /*!< data bit level inversion */ - USART_DINV_DISABLE, /*!< data bit level not inversion */ - /* TX pin level inversion */ - USART_TXPIN_ENABLE, /*!< TX pin level inversion */ - USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ - /* RX pin level inversion */ - USART_RXPIN_ENABLE, /*!< RX pin level inversion */ - USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ - /* swap TX/RX pins */ - USART_SWAP_ENABLE, /*!< swap TX/RX pins */ - USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ -}usart_invert_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART oversample mode */ -#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ -#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ - -/* USART address detection mode */ -#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) -#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ -#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ - -/* USART last bit clock pulse */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART data is transmitted/received with the LSB/MSB first */ -#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) -#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ -#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ - -/* USART auto baud rate detection mode bits definitions */ -#define CTL1_ABDM(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) -#define USART_ABDM_FTOR CTL1_ABDM(0) /*!< falling edge to rising edge measurement */ -#define USART_ABDM_FTOF CTL1_ABDM(1) /*!< falling edge to falling edge measurement */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* DMA enable for reception */ -#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */ -#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */ - -/* DMA enable for transmission */ -#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */ -#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */ - -/* USART RTS hardware flow control configure */ -#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */ -#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */ - -/* USART CTS hardware flow control configure */ -#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */ -#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */ - -/* USART one sample bit method configure */ -#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ -#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ - -/* USART driver enable polarity mode */ -#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ -#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ - -/* USART wakeup mode from deep-sleep mode */ -#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ -#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ -#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ - -/* USART hardware flow control coherence mode */ -#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) -#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ -#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); - -/* USART normal mode communication */ -/* data is transmitted/received with the LSB/MSB first */ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); -/* configure USART inverted */ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); -/* enable the USART overrun function */ -void usart_overrun_enable(uint32_t usart_periph); -/* disable the USART overrun function */ -void usart_overrun_disable(uint32_t usart_periph); -/* configure the USART oversample mode */ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); -/* configure sample bit method */ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); -/* enable receiver timeout */ -void usart_receiver_timeout_enable(uint32_t usart_periph); -/* disable receiver timeout */ -void usart_receiver_timeout_disable(uint32_t usart_periph); -/* configure receiver timeout threshold */ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* auto baud rate detection */ -/* enable auto baud rate detection */ -void usart_autobaud_detection_enable(uint32_t usart_periph); -/* disable auto baud rate detection */ -void usart_autobaud_detection_disable(uint32_t usart_periph); -/* configure auto baud rate detection mode */ -void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* configure address detection mode */ -void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* enable LIN mode */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* disable LIN mode */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); - -/* half-duplex communication */ -/* enable half-duplex mode */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* disable half-duplex mode */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* enable clock */ -void usart_clock_enable(uint32_t usart_periph); -/* disable clock */ -void usart_clock_disable(uint32_t usart_periph); -/* configure USART synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); -/* enable smartcard mode */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* disable smartcard mode */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* enable NACK in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* disable NACK in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* enable early NACK in smartcard mode */ -void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); -/* disable early NACK in smartcard mode */ -void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); -/* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* coherence control */ -/* configure hardware flow control coherence mode */ -void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); - -/* enable RS485 driver */ -void usart_rs485_driver_enable(uint32_t usart_periph); -/* disable RS485 driver */ -void usart_rs485_driver_disable(uint32_t usart_periph); -/* configure driver enable assertion time */ -void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); -/* configure driver enable de-assertion time */ -void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); -/* configure driver enable polarity mode */ -void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); - -/* USART DMA */ -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); -/* disable DMA on reception error */ -void usart_reception_error_dma_disable(uint32_t usart_periph); -/* enable DMA on reception error */ -void usart_reception_error_dma_enable(uint32_t usart_periph); - -/* enable USART to wakeup the mcu from deep-sleep mode */ -void usart_wakeup_enable(uint32_t usart_periph); -/* disable USART to wakeup the mcu from deep-sleep mode */ -void usart_wakeup_disable(uint32_t usart_periph); -/* configure the USART wakeup mode from deep-sleep mode */ -void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); - -/* USART receive FIFO */ -/* enable receive FIFO */ -void usart_receive_fifo_enable(uint32_t usart_periph); -/* disable receive FIFO */ -void usart_receive_fifo_disable(uint32_t usart_periph); -/* read receive FIFO counter number */ -uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); - -/* flag & interrupt functions */ -/* get flag in STAT/RFCS register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear USART status */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum inttype); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum inttype); -/* enable USART command */ -void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -/* clear USART interrupt flag */ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag); - -#endif /* GD32E230_USART_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_wwdgt.h b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_wwdgt.h deleted file mode 100644 index 38445b36de..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_wwdgt.h +++ /dev/null @@ -1,88 +0,0 @@ -/*! - \file gd32e230_wwdgt.h - \brief definitions for the WWDGT - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_WWDGT_H -#define GD32E230_WWDGT_H - -#include "gd32e230.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32E230_WWDGT_H */ diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_adc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_adc.c deleted file mode 100644 index d0f7065336..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_adc.c +++ /dev/null @@ -1,844 +0,0 @@ -/*! - \file gd32e230_adc.c - \brief ADC driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_adc.h" - -/*! - \brief reset ADC - \param[in] none - \param[out] none - \retval none -*/ -void adc_deinit(void) -{ - rcu_periph_reset_enable(RCU_ADCRST); - rcu_periph_reset_disable(RCU_ADCRST); -} - -/*! - \brief enable ADC interface - \param[in] none - \param[out] none - \retval none -*/ -void adc_enable(void) -{ - if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)){ - ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] none - \param[out] none - \retval none -*/ -void adc_disable(void) -{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] none - \param[out] none - \retval none -*/ -void adc_calibration_enable(void) -{ - /* reset the selected ADC calibration register */ - ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while((ADC_CTL1 & ADC_CTL1_RSTCLB)){ - } - - /* enable ADC calibration process */ - ADC_CTL1 |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while((ADC_CTL1 & ADC_CTL1_CLB)){ - } -} - -/*! - \brief enable DMA request - \param[in] none - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(void) -{ - ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] none - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(void) -{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1 |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1 &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief configure ADC discontinuous mode - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel - \param[in] length: number of conversions in discontinuous mode, the number can be 1..8 - for regular channel, the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length) -{ - ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure the number of conversions in discontinuous mode */ - ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U)); - ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - default: - break; - } -} - -/*! - \brief configure ADC special function - \param[in] function: the function to configure - one or more parameters can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t function, ControlStatus newvalue) -{ - if(newvalue){ - /* enable ADC scan mode */ - if(RESET != (function & ADC_SCAN_MODE)){ - ADC_CTL0 |= ADC_SCAN_MODE; - } - /* enable ADC inserted channel group convert automatically */ - if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ - ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO; - } - /* enable ADC continuous mode */ - if(RESET != (function & ADC_CONTINUOUS_MODE)){ - ADC_CTL1 |= ADC_CONTINUOUS_MODE; - } - }else{ - /* disable ADC scan mode */ - if(RESET != (function & ADC_SCAN_MODE)){ - ADC_CTL0 &= ~ADC_SCAN_MODE; - } - /* disable ADC inserted channel group convert automatically */ - if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)){ - ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO; - } - /* disable ADC continuous mode */ - if(RESET != (function & ADC_CONTINUOUS_MODE)){ - ADC_CTL1 &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: right alignment - \arg ADC_DATAALIGN_LEFT: left alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment){ - ADC_CTL1 |= ADC_CTL1_DAL; - }else{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint8_t channel_group, uint32_t length) -{ - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure the length of regular channel group */ - ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0 |= RSQ0_RL((uint32_t)(length-1U)); - break; - case ADC_INSERTED_CHANNEL: - /* configure the length of inserted channel group */ - ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ |= ISQ_IL((uint32_t)(length-1U)); - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] rank: the regular group sequence rank, this parameter must be between 0 to 15 - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* configure ADC regular sequence */ - if(rank < 6U){ - rsq = ADC_RSQ2; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); - rsq |= ((uint32_t)channel << (5U*rank)); - ADC_RSQ2 = rsq; - }else if(rank < 12U){ - rsq = ADC_RSQ1; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-6U)))); - rsq |= ((uint32_t)channel << (5U*(rank-6U))); - ADC_RSQ1 = rsq; - }else if(rank < 16U){ - rsq = ADC_RSQ0; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*(rank-12U)))); - rsq |= ((uint32_t)channel << (5U*(rank-12U))); - ADC_RSQ0 = rsq; - }else{ - } - - /* configure ADC sampling time */ - if(channel < 10U){ - sampt = ADC_SAMPT1; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel))); - sampt |= (uint32_t)(sample_time << (3U*channel)); - ADC_SAMPT1 = sampt; - }else if(channel < 19U){ - sampt = ADC_SAMPT0; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel-10U)))); - sampt |= (uint32_t)(sample_time << (3U*(channel-10U))); - ADC_SAMPT0 = sampt; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ , 20U , 21U); - - isq = ADC_ISQ; - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank)*5U))); - isq |= ((uint32_t)channel << (15U - (inserted_length - rank)*5U)); - ADC_ISQ = isq; - - /* configure ADC sampling time */ - if(channel < 10U){ - sampt = ADC_SAMPT1; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*channel))); - sampt |= (uint32_t) sample_time << (3U*channel); - ADC_SAMPT1 = sampt; - }else if(channel < 19U){ - sampt = ADC_SAMPT0; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U*(channel - 10U)))); - sampt |= ((uint32_t)sample_time << (3U*(channel - 10U))); - ADC_SAMPT0 = sampt; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] inserted_channel: insert channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 - \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 - \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 - \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 - \param[in] offset: the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); - num = 3U - (inserted_length - inserted_channel); - - if(num <= 3U){ - /* calculate the offset of the register */ - num = num * 4U; - /* configure the offset of the selected channels */ - REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief enable or disable ADC external trigger - \param[in] channel_group: select the channel group - one or more parameters can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue) -{ - if(newvalue){ - /* external trigger enable for regular channel */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_ETERC; - } - /* external trigger enable for inserted channel */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_ETEIC; - } - }else{ - /* external trigger disable for regular channel */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1 &= ~ADC_CTL1_ETERC; - } - /* external trigger disable for inserted channel */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1 &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief configure ADC external trigger source - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected which is shown as below: - for regular channel: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select - \arg ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select - \arg ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select - \arg ADC_EXTTRIG_REGULAR_T14_CH0: TIMER14 CH0 event select - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 - \arg ADC_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select - \arg ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source) -{ - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - /* external trigger select for regular channel */ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1 |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* external trigger select for inserted channel */ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1 |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief enable ADC software trigger - \param[in] channel_group: select the channel group - one or more parameters can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint8_t channel_group) -{ - /* enable regular group channel software trigger */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_SWRCST; - } - /* enable inserted channel group software trigger */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)){ - ADC_CTL1 |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(void) -{ - return ((uint16_t)ADC_RDATA); -} - -/*! - \brief read ADC inserted group data register - \param[in] inserted_channel: inserted channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 - \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 - \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 - \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - idata = ADC_IDATA0; - break; - case ADC_INSERTED_CHANNEL_1: - idata = ADC_IDATA1; - break; - case ADC_INSERTED_CHANNEL_2: - idata = ADC_IDATA2; - break; - case ADC_INSERTED_CHANNEL_3: - idata = ADC_IDATA3; - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief get the ADC flag bits - \param[in] flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t flag) -{ - FlagStatus reval = RESET; - - if(ADC_STAT & flag){ - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag - \param[in] flag: the adc flag - one or more parameters can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t flag) -{ - ADC_STAT &= ~((uint32_t)flag); -} - -/*! - \brief get the ADC interrupt flag - \param[in] flag: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t flag) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - - /* check the interrupt bits */ - switch(flag){ - case ADC_INT_FLAG_WDE: - state = ADC_STAT & ADC_STAT_WDE; - if((ADC_CTL0 & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - state = ADC_STAT & ADC_STAT_EOC; - if((ADC_CTL0 & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - state = ADC_STAT & ADC_STAT_EOIC; - if((ADC_CTL0 & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear ADC interrupt flag - \param[in] flag: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t flag) -{ - ADC_STAT &= ~((uint32_t)flag); -} - -/*! - \brief enable ADC interrupt - \param[in] interrupt: the adc interrupt - one or more parameters can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t interrupt) -{ - /* enable analog watchdog interrupt */ - if(RESET != (interrupt & ADC_INT_WDE)){ - ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE; - } - - /* enable end of group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOC)){ - ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE; - } - - /* enable end of inserted group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOIC)){ - ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] interrupt: the adc interrupt flag - one or more parameters can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t interrupt) -{ - /* disable analog watchdog interrupt */ - if(RESET != (interrupt & ADC_INT_WDE)){ - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE; - } - - /* disable end of group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOC)){ - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE; - } - - /* disable end of inserted group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOIC)){ - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE; - } -} - -/*! - \brief configure ADC analog watchdog single channel - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint8_t channel) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - - ADC_CTL0 |= (uint32_t)channel; - ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint8_t channel_group) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - - /* select the group */ - switch(channel_group){ - case ADC_REGULAR_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] none - \param[out] none - \retval none -*/ -void adc_watchdog_disable(void) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] low_threshold: analog watchdog low threshold,0..4095 - \param[in] high_threshold: analog watchdog high threshold,0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold) -{ - ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold); -} - - -/*! - \brief configure ADC resolution - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t resolution) -{ - ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES); - ADC_CTL0 |= (uint32_t)resolution; -} - -/*! - \brief configure ADC oversample mode - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio) -{ - /* configure ADC oversampling mode */ - if(ADC_OVERSAMPLING_ONE_CONVERT == mode){ - ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS; - }else{ - ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); - } - - /* configure the shift and ratio */ - ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief enable ADC oversample mode - \param[in] none - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(void) -{ - ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN; -} - -/*! - \brief disable ADC oversample mode - \param[in] none - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(void) -{ - ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_cmp.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_cmp.c deleted file mode 100644 index 46ef66cbcf..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_cmp.c +++ /dev/null @@ -1,180 +0,0 @@ -/*! - \file gd32e230_cmp.c - \brief CMP driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_cmp.h" - -/*! - \brief deinitialize comparator - \param[in] none - \param[out] none - \retval none -*/ -void cmp_deinit(void) -{ - CMP_CS = ((uint32_t)0x00000000U); -} - -/*! - \brief initialize comparator mode - \param[in] operating_mode - \arg CMP_HIGHSPEED: high speed mode - \arg CMP_MIDDLESPEED: medium speed mode - \arg CMP_LOWSPEED: low speed mode - \arg CMP_VERYLOWSPEED: very-low speed mode - \param[in] inverting_input - \arg CMP_1_4VREFINT: VREFINT *1/4 input - \arg CMP_1_2VREFINT: VREFINT *1/2 input - \arg CMP_3_4VREFINT: VREFINT *3/4 input - \arg CMP_VREFINT: VREFINT input - \arg CMP_PA4: PA4 input - \arg CMP_PA5: PA5 input - \arg CMP_PA0: PA0 input - \arg CMP_PA2: PA2 input - \param[in] hysteresis - \arg CMP_HYSTERESIS_NO: output no hysteresis - \arg CMP_HYSTERESIS_LOW: output low hysteresis - \arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis - \arg CMP_HYSTERESIS_HIGH: output high hysteresis - \param[out] none - \retval none -*/ -void cmp_mode_init(operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis) -{ - /* initialize comparator mode */ - CMP_CS |= CS_CMPM(operating_mode) | CS_CMPMSEL(inverting_input) | CS_CMPHST(output_hysteresis); - -} - -/*! - \brief initialize comparator output - \param[in] output_slection - \arg CMP_OUTPUT_NONE: output no selection - \arg CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input - \arg CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture - \arg CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input - \arg CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture - \arg CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input - \param[in] output_polarity - \arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted - \arg CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted - \param[out] none - \retval none -*/ -void cmp_output_init(cmp_output_enum output_slection, uint32_t output_polarity) -{ - /* initialize comparator output */ - - CMP_CS |= CS_CMPOSEL(output_slection); - /* output polarity */ - if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){ - CMP_CS |= CMP_CS_CMPPL; - }else{ - CMP_CS &= ~CMP_CS_CMPPL; - } - -} - -/*! - \brief enable comparator - \param[in] none - \param[out] none - \retval none -*/ -void cmp_enable(void) -{ - CMP_CS |= CMP_CS_CMPEN; -} - -/*! - \brief disable comparator - \param[in] none - \param[out] none - \retval none -*/ -void cmp_disable(void) -{ - CMP_CS &= ~CMP_CS_CMPEN; -} - -/*! - \brief enable comparator switch - \param[in] none - \param[out] none - \retval none -*/ -void cmp_switch_enable(void) -{ - CMP_CS |= CMP_CS_CMPSW; -} - -/*! - \brief disable comparator switch - \param[in] none - \param[out] none - \retval none -*/ -void cmp_switch_disable(void) -{ - CMP_CS &= ~CMP_CS_CMPSW; -} - -/*! - \brief get output level - \param[in] none - \param[out] none - \retval the output level -*/ -uint32_t cmp_output_level_get(void) -{ - if(CMP_CS & CMP_CS_CMPO){ - return CMP_OUTPUTLEVEL_HIGH; - }else{ - return CMP_OUTPUTLEVEL_LOW; - } - -} - -/*! - \brief lock the comparator - \param[in] none - \param[out] none - \retval none -*/ -void cmp_lock_enable(void) -{ - CMP_CS |= CMP_CS_CMPLK; -} - diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_crc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_crc.c deleted file mode 100644 index 59391d7d38..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_crc.c +++ /dev/null @@ -1,206 +0,0 @@ -/*! - \file gd32e230_crc.c - \brief CRC driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_crc.h" - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_IDATA = (uint32_t)0xFFFFFFFFU; - CRC_DATA = (uint32_t)0xFFFFFFFFU; - CRC_FDATA = (uint32_t)0x00000000U; - CRC_POLY = (uint32_t)0x04C11DB7U; - CRC_CTL = CRC_CTL_RST; -} - -/*! - \brief enable the reverse operation of output data - \param[in] none - \param[out] none - \retval none -*/ -void crc_reverse_output_data_enable(void) -{ - CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); - CRC_CTL |= (uint32_t)CRC_CTL_REV_O; -} - -/*! - \brief disable the reverse operation of output data - \param[in] none - \param[out] none - \retval none -*/ -void crc_reverse_output_data_disable(void) -{ - CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); -} - -/*! - \brief reset data register to the value of initializaiton data register - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write the free data register - \param[in] free_data: specify 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief write the initializaiton data register - \param[in] init_data:specify 32-bit data - \param[out] none - \retval none -*/ -void crc_init_data_register_write(uint32_t init_data) -{ - CRC_IDATA = (uint32_t)init_data; -} - -/*! - \brief configure the CRC input data function - \param[in] data_reverse: specify input data reverse function - \arg CRC_INPUT_DATA_NOT: input data is not reversed - \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits - \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits - \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits - \param[out] none - \retval none -*/ -void crc_input_data_reverse_config(uint32_t data_reverse) -{ - CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I); - CRC_CTL |= (uint32_t)data_reverse; -} - -/*! - \brief configure the CRC size of polynomial function - \param[in] poly_size: size of polynomial - \arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation - \arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation - \arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation - \arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation - \param[out] none - \retval none -*/ -void crc_polynomial_size_set(uint32_t poly_size) -{ - CRC_CTL &= (uint32_t)(~(CRC_CTL_PS)); - CRC_CTL |= (uint32_t)poly_size; -} - -/*! - \brief configure the CRC polynomial value function - \param[in] poly: configurable polynomial value - \param[out] none - \retval none -*/ -void crc_polynomial_set(uint32_t poly) -{ - CRC_POLY &= (uint32_t)(~CRC_POLY_POLY); - CRC_POLY = poly; -} - -/*! - \brief CRC calculate a 32-bit data - \param[in] sdata: specify 32-bit data - \param[out] none - \retval 32-bit CRC calculate value -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return(CRC_DATA); -} - -/*! - \brief CRC calculate a 32-bit data array - \param[in] array: pointer to an array of 32 bit data words - \param[in] size: size of the array - \param[out] none - \retval 32-bit CRC calculate value -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for(index = 0U; index < size; index++){ - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dbg.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dbg.c deleted file mode 100644 index 614bd6016e..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dbg.c +++ /dev/null @@ -1,140 +0,0 @@ -/*! - \file gd32e230_dbg.c - \brief DBG driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_dbg.h" - -#define DBG_RESET_VAL 0x00000000U - -/*! - \brief deinitialize the DBG - \param[in] none - \param[out] none - \retval none -*/ -void dbg_deinit(void) -{ - DBG_CTL0 = DBG_RESET_VAL; - DBG_CTL1 = DBG_RESET_VAL; -} - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL0 |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL0 &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: DBG peripheral - only one parameter can be selected which is shown as below: - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted - \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted - \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted - \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: DBG peripheral - only one parameter can be selected which is shown as below: - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted - \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted - \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted - \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dma.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dma.c deleted file mode 100644 index 5cdf462001..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_dma.c +++ /dev/null @@ -1,562 +0,0 @@ -/*! - \file gd32e230_dma.c - \brief DMA driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_dma.h" - -/*! - \brief deinitialize DMA a channel registers - \param[in] channelx: specify which DMA channel is deinitialized - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_deinit(dma_channel_enum channelx) -{ - /* disable DMA a channel */ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_struct_para_init(dma_parameter_struct* init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; - init_struct->number = 0U; - init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; - init_struct->priority = (uint32_t)DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA channel - \param[in] channelx: specify which DMA channel is initialized - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct) -{ - uint32_t ctl; - - dma_channel_disable(channelx); - - /* configure peripheral base address */ - DMA_CHPADDR(channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(channelx) = init_struct->memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width,channel priotity */ - ctl = DMA_CHCTL(channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); - DMA_CHCTL(channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; - }else{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] channelx: specify which DMA channel to set peripheral base address - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(dma_channel_enum channelx, uint32_t address) -{ - DMA_CHPADDR(channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] channelx: specify which DMA channel to set memory base address - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(dma_channel_enum channelx, uint32_t address) -{ - DMA_CHMADDR(channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] number: the number of remaining data to be transferred by the DMA - \param[out] none - \retval none -*/ -void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number) -{ - DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(dma_channel_enum channelx) -{ - return (uint32_t)DMA_CHCNT(channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] priority: priority level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief configure transfer data width of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] mwidth: transfer data width of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief configure transfer data width of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] pwidth: transfer data width of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction) -{ - if(DMA_PERIPHERAL_TO_MEMORY == direction){ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))){ - reval = SET; - }else{ - reval = RESET; - } - - return reval; -} - -/*! - \brief clear DMA a channel flag - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: transfer finish flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel - \arg DMA_INT_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch(flag){ - case DMA_INT_FLAG_FTF: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE; - break; - default: - break; - } - - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel interrupt flag - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: transfer finish flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel - \arg DMA_INT_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC |= DMA_FLAG_ADD(flag,channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to enable - only one parameter can be selected which is shown as below: - \arg DMA_INT_ERR: channel error interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_FTF: channel full transfer finish interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source) -{ - DMA_CHCTL(channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to disable - only one parameter can be selected which is shown as below: - \arg DMA_INT_ERR: channel error interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_FTF: channel full transfer finish interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source) -{ - DMA_CHCTL(channelx) &= ~source; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_exti.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_exti.c deleted file mode 100644 index 894a38c62f..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_exti.c +++ /dev/null @@ -1,254 +0,0 @@ -/*! - \file gd32e230_exti.c - \brief EXTI driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_exti.h" - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = (uint32_t)0x0F940000U; - EXTI_EVEN = (uint32_t)0x00000000U; - EXTI_RTEN = (uint32_t)0x00000000U; - EXTI_FTEN = (uint32_t)0x00000000U; - EXTI_SWIEV = (uint32_t)0x00000000U; -} - -/*! - \brief initialize the EXTI - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling trigger - \arg EXTI_TRIG_BOTH: rising and falling trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, \ - exti_mode_enum mode, \ - exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode){ - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch(trig_type){ - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI lines flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t)linex; - flag_right = EXTI_INTEN & (uint32_t)linex; - - if((RESET != flag_left) && (RESET != flag_right)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fmc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fmc.c deleted file mode 100644 index 1489157807..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fmc.c +++ /dev/null @@ -1,814 +0,0 @@ -/*! - \file gd32e230_fmc.c - \brief FMC driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_fmc.h" - -/* FMC register bit offset */ -#define OB_HIGH_WP_OFFSET ((uint32_t)8U) -#define FMC_OBSTAT_USER_OFFSET ((uint32_t)8U) -#define FMC_OBSTAT_DATA_OFFSET ((uint32_t)16U) - -/*! - \brief unlock the main FMC operation - it is better to used in pairs with fmc_lock - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL & FMC_CTL_LK))){ - /* write the FMC key */ - FMC_KEY = UNLOCK_KEY0; - FMC_KEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - it is better to used in pairs with fmc_unlock after an operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit*/ - FMC_CTL |= FMC_CTL_LK; -} - -/*! - \brief set the wait state counter value - \param[in] wscnt: wait state counter value - \arg WS_WSCNT_0: 0 wait state added - \arg WS_WSCNT_1: 1 wait state added - \arg WS_WSCNT_2: 2 wait state added - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint8_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief pre-fetch enable - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_enable(void) -{ - FMC_WS |= FMC_WS_PFEN; -} - -/*! - \brief pre-fetch disable - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_disable(void) -{ - FMC_WS &= ~FMC_WS_PFEN; -} - -/*! - \brief erase page - \param[in] page_address: target page start address - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start page erase */ - FMC_CTL |= FMC_CTL_PER; - FMC_ADDR = page_address; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PER bit */ - FMC_CTL &= ~FMC_CTL_PER; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start chip erase */ - FMC_CTL |= FMC_CTL_MER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the MER bit */ - FMC_CTL &= ~FMC_CTL_MER; - } - - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief program a double word at the corresponding address in main flash, this - function also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming - \param[in] address: address to program - \param[in] data: double word to program - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data) -{ - uint32_t data0, data1; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - data0 = (uint32_t)(data & 0xFFFFFFFFU); - data1 = (uint32_t)((data>>32U) & 0xFFFFFFFFU); - - /* configure program width */ - FMC_WS |= FMC_WS_PGW; - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - REG32(address) = data0; - REG32(address+4U) = data1; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - FMC_WS &= ~(FMC_WS_PGW); - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address in main flash, this function - also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - it is better to used in pairs with ob_lock - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL & FMC_CTL_OBWEN)){ - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } - /* wait until OBWEN bit is set by hardware */ - while(RESET == (FMC_CTL & FMC_CTL_OBWEN)){ - } -} - -/*! - \brief lock the option byte operation - it is better to used in pairs with ob_unlock after an operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWE bit */ - FMC_CTL &= ~FMC_CTL_OBWEN; -} - -/*! - \brief reload the option byte and generate a system reset - \param[in] none - \param[out] none - \retval none -*/ -void ob_reset(void) -{ - /* set the OBRLD bit */ - FMC_CTL |= FMC_CTL_OBRLD; -} - -/*! - \brief get option byte value - \param[in] addr: address of option byte - \arg OB_SPC_USER_ADDRESS: address of option byte security protection and user - \arg OB_DATA_ADDRESS: address of option byte data - \arg OB_WP_ADDRESS: address of option byte write protection - \param[out] option byte value -*/ -uint32_t option_byte_value_get(uint32_t addr) -{ - return *(volatile uint32_t *)(addr); -} - -/*! - \brief erase the option byte - programmer must ensure FMC & option byte are both unlocked before calling this function - \param[in] none - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_erase(void) -{ - uint16_t fmc_spc; - uint32_t val; - uint32_t fmc_plevel = ob_obstat_plevel_get(); - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* get the original option byte security protection code */ - if(OB_OBSTAT_PLEVEL_NO == fmc_plevel){ - fmc_spc = FMC_NSPC; - }else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel){ - fmc_spc = FMC_LSPC; - }else{ - fmc_spc = FMC_HSPC; - fmc_state = FMC_OB_HSPC; - } - val = HIGH_16BITS_MASK | (uint32_t)fmc_spc; - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - - /* restore the last get option byte security protection code */ - OB_SPC_USER = val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable option byte write protection (OB_WP) - \param[in] ob_wp: write protection configuration data. Notice that set the - bit to 1 if you want to protect the corresponding pages. - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_write_protection_enable(uint16_t ob_wp) -{ - uint32_t ob_wrp_val = 0U; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - ob_wp = (uint16_t)(~ob_wp); - ob_wrp_val |= (uint32_t)ob_wp&0x00FFU; - ob_wrp_val |= (((uint32_t)ob_wp&0xFF00U)>>8U) << 16U; - - if(FMC_READY == fmc_state){ - /* set the OBPG bit*/ - FMC_CTL |= FMC_CTL_OBPG; - - if(0xFFFFFFFFU != ob_wrp_val){ - OB_WP = ob_wrp_val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection code - \arg FMC_NSPC: no security protection - \arg FMC_LSPC: low security protection - \arg FMC_HSPC: high security protection - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_security_protection_config(uint16_t ob_spc) -{ - uint32_t val; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - val = option_byte_value_get(OB_SPC_USER_ADDRESS); - /* the OB_SPC byte cannot be reprogrammed if protection level is high */ - if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()){ - fmc_state = FMC_OB_HSPC; - } - - val &= ~LOW_16BITS_MASK; - val |= (uint32_t)ob_spc; - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* enable the option bytes programming */ - FMC_CTL |= FMC_CTL_OBPG; - - OB_SPC_USER = val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option byte - this function can only clear the corresponding bits to be 0 rather than 1. - the function ob_erase is used to set all the bits to be 1. - \param[in] ob_user: user option byte - one or more parameters (bitwise AND) can be selected which are shown as below: - \arg OB_FWDGT_HW: hardware free watchdog timer - \arg OB_DEEPSLEEP_RST: no reset when entering deepsleep mode - \arg OB_STDBY_RST: no reset when entering standby mode - \arg OB_BOOT1_SET_1: BOOT1 bit is 1 - \arg OB_VDDA_DISABLE: disable VDDA monitor - \arg OB_SRAM_PARITY_ENABLE: enable sram parity check - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_user_write(uint8_t ob_user) -{ - uint32_t val_spc_user; - /* check whether FMC is ready or not */ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - val_spc_user = option_byte_value_get(OB_SPC_USER_ADDRESS); - - val_spc_user &= ~HIGH_16BITS_MASK; - - val_spc_user |= ((uint32_t)ob_user<<16U); - - if(FMC_READY == fmc_state){ - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* enable the option bytes programming */ - FMC_CTL |= FMC_CTL_OBPG; - - OB_SPC_USER = val_spc_user; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC data option byte - \param[in] data: the data to be programmed, OB_DATA[0:15] - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_data_program(uint16_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - uint32_t val = 0U; - - val |= (uint32_t)data&0x00FFU; - val |= (((uint32_t)data&0xFF00U)>>8U) << 16U; - - if(FMC_READY == fmc_state){ - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - OB_DATA = val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get OB_USER in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_user -*/ -uint8_t ob_user_get(void) -{ - return (uint8_t)(FMC_OBSTAT >> FMC_OBSTAT_USER_OFFSET); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> FMC_OBSTAT_DATA_OFFSET); -} - -/*! - \brief get the FMC option byte write protection (OB_WP) in register FMC_WP - \param[in] none - \param[out] none - \retval OB_WP -*/ -uint16_t ob_write_protection_get(void) -{ - return (uint16_t)(FMC_WP); -} - -/*! - \brief get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register - \param[in] none - \param[out] none - \retval the value of PLEVEL -*/ -uint32_t ob_obstat_plevel_get(void) -{ - return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1)); -} - -/* FMC interrupts and flags management functions */ -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - \arg FMC_INTEN_END: FMC end of operation interrupt - \arg FMC_INTEN_ERR: FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_CTL |= interrupt; -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - \arg FMC_INTEN_END: FMC end of operation interrupt - \arg FMC_INTEN_ERR: FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_CTL &= ~(uint32_t)interrupt; -} - -/*! - \brief get flag set or reset - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: FMC end of programming flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - FlagStatus status = RESET; - - if(FMC_STAT & flag){ - status = SET; - } - /* return the state of corresponding FMC flag */ - return status; -} - -/*! - \brief clear the FMC pending flag by writing 1 - \param[in] flag: clear FMC flag - one or more parameters can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: FMC end of programming flag - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - /* clear the flags */ - FMC_STAT = flag; -} - -/*! - \brief get intrrupt flag set or reset - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC programming error flag - \arg FMC_INT_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_INT_FLAG_WPERR: FMC write protection error flag - \arg FMC_INT_FLAG_END: FMC end of programming flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(uint32_t int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - - if(FMC_INT_FLAG_END == int_flag){ - /* get the interrupt enable bit status */ - intenable = FMC_CTL & FMC_INTEN_END; - /* get the corresponding flag bit status */ - flagstatus = FMC_STAT & int_flag; - if(intenable && flagstatus){ - return SET; - }else{ - return RESET; - } - }else{ - /* get the interrupt enable bit status */ - intenable = FMC_CTL & FMC_INTEN_ERR; - /* get the corresponding flag bit status */ - flagstatus = FMC_STAT & int_flag; - if(intenable && flagstatus){ - return SET; - }else{ - return RESET; - } - } -} - -/*! - \brief clear the FMC interrupt pending flag by writing 1 - \param[in] flag: clear FMC flag - one or more parameters can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC programming error flag - \arg FMC_INT_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_INT_FLAG_WPERR: FMC write protection error flag - \arg FMC_INT_FLAG_END: FMC end of programming flag - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(uint32_t int_flag) -{ - /* clear the flags */ - FMC_STAT = int_flag; -} - -/*! - \brief get the FMC state - \param[in] none - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)){ - fmc_state = FMC_PGERR; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC is ready or not - \param[in] timeout: timeout count - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fwdgt.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fwdgt.c deleted file mode 100644 index d3daa1fc32..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_fwdgt.c +++ /dev/null @@ -1,252 +0,0 @@ -/*! - \file gd32e230_fwdgt.c - \brief FWDGT driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_fwdgt.h" - -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_CTL_CMD bit field */ -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */ -/* write value to FWDGT_WND_WND bit field */ -#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */ - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief configure the free watchdog timer counter prescaler value - \param[in] prescaler_value: specify prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_value; - - return SUCCESS; -} - -/*! - \brief configure the free watchdog timer counter reload value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_reload_value_config(uint16_t reload_value) -{ - uint32_t timeout = FWDGT_RLD_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - return SUCCESS; -} - -/*! - \brief configure the free watchdog timer counter window value - \param[in] window_value: specify window value(0x0000 - 0x0FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_window_value_config(uint16_t window_value) -{ - uint32_t time_index = FWDGT_WND_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_WND */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the WUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_WUD; - }while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - FWDGT_WND = WND_WND(window_value); - - return SUCCESS; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if ((uint32_t)RESET != flag_status){ - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(RESET != (FWDGT_STAT & flag)){ - return SET; - } - return RESET; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_gpio.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_gpio.c deleted file mode 100644 index 7223c98b85..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_gpio.c +++ /dev/null @@ -1,399 +0,0 @@ -/*! - \file gd32e230_gpio.c - \brief GPIO driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_gpio.h" - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch(gpio_periph){ - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOF: - /* reset GPIOF */ - rcu_periph_reset_enable(RCU_GPIOFRST); - rcu_periph_reset_disable(RCU_GPIOFRST); - break; - default: - break; - } -} - -/*! - \brief set GPIO mode - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] mode: gpio pin mode - \arg GPIO_MODE_INPUT: input mode - \arg GPIO_MODE_OUTPUT: output mode - \arg GPIO_MODE_AF: alternate function mode - \arg GPIO_MODE_ANALOG: analog mode - \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor - \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors - \arg GPIO_PUPD_PULLUP: with pull-up resistor - \arg GPIO_PUPD_PULLDOWN:with pull-down resistor - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) -{ - uint16_t i; - uint32_t ctl, pupd; - - ctl = GPIO_CTL(gpio_periph); - pupd = GPIO_PUD(gpio_periph); - - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin mode bits */ - ctl &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - ctl |= GPIO_MODE_SET(i, mode); - - /* clear the specified pin pupd bits */ - pupd &= ~GPIO_PUPD_MASK(i); - /* set the specified pin pupd bits */ - pupd |= GPIO_PUPD_SET(i, pull_up_down); - } - } - - GPIO_CTL(gpio_periph) = ctl; - GPIO_PUD(gpio_periph) = pupd; -} - -/*! - \brief set GPIO output type and speed - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] otype: gpio pin output mode - \arg GPIO_OTYPE_PP: push pull mode - \arg GPIO_OTYPE_OD: open drain mode - \param[in] speed: gpio pin output max speed - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t ospeed; - - if(GPIO_OTYPE_OD == otype){ - GPIO_OMODE(gpio_periph) |= (uint32_t)pin; - }else{ - GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); - } - - /* get the specified pin output speed bits value */ - ospeed = GPIO_OSPD(gpio_periph); - - for(i = 0U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin output speed bits */ - ospeed &= ~GPIO_OSPEED_MASK(i); - /* set the specified pin output speed bits */ - ospeed |= GPIO_OSPEED_SET(i,speed); - } - } - GPIO_OSPD(gpio_periph) = ospeed; -} - -/*! - \brief set GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if(RESET != bit_value){ - GPIO_BOP(gpio_periph) = (uint32_t)pin; - }else{ - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] data: specify the value to be written to the port output control register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph, uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO all pins input status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval state of GPIO all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t)GPIO_ISTAT(gpio_periph); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get GPIO all pins output status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval state of GPIO all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return (uint16_t)GPIO_OCTL(gpio_periph); -} - -/*! - \brief set GPIO alternate function - \param[in] gpio_periph: GPIOx(x = A,B,C) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C) - \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet - \arg GPIO_AF_0: TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, - I2C0, I2C1, SWDIO, SWCLK - \arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1 - \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0 - \arg GPIO_AF_3: I2C0, TIMER14 - \arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13 - \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, I2S0 - \arg GPIO_AF_6(port A,B only): SPI1 - \arg GPIO_AF_7(port A,B only): CMP - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) -{ - uint16_t i; - uint32_t afrl, afrh; - - afrl = GPIO_AFSEL0(gpio_periph); - afrh = GPIO_AFSEL1(gpio_periph); - - for(i = 0U;i < 8U;i++){ - if((1U << i) & pin){ - /* clear the specified pin alternate function bits */ - afrl &= ~GPIO_AFR_MASK(i); - afrl |= GPIO_AFR_SET(i,alt_func_num); - } - } - - for(i = 8U;i < 16U;i++){ - if((1U << i) & pin){ - /* clear the specified pin alternate function bits */ - afrh &= ~GPIO_AFR_MASK(i - 8U); - afrh |= GPIO_AFR_SET(i - 8U,alt_func_num); - } - } - - GPIO_AFSEL0(gpio_periph) = afrl; - GPIO_AFSEL1(gpio_periph) = afrh; -} - -/*! - \brief lock GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -/*! - \brief toggle GPIO pin status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_TG(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief toggle GPIO port status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval none -*/ -void gpio_port_toggle(uint32_t gpio_periph) -{ - GPIO_TG(gpio_periph) = 0x0000FFFFU; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_i2c.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_i2c.c deleted file mode 100644 index 89fb7f52e9..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_i2c.c +++ /dev/null @@ -1,797 +0,0 @@ -/*! - \file gd32e230_i2c.c - \brief I2C driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x0000007FU) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ -#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch(i2c_periph){ - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - and fast mode plus (up to 1MHz) - \param[in] dutycyc: duty cycle in fast mode or fast mode plus - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1/1000000U); - if(freq >= I2CCLK_MAX){ - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed){ - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1/1000000U)+1U); - if(risetime >= I2CCLK_MAX){ - I2C_RT(i2c_periph) = I2CCLK_MAX; - }else if(risetime <= I2CCLK_MIN){ - I2C_RT(i2c_periph) = I2CCLK_MIN; - }else{ - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1/(clkspeed*2U)); - if(clkc < 0x04U){ - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - }else if(400000U >= clkspeed){ - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)300U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if(0U == (clkc & I2C_CKCFG_CLKC)){ - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - }else{ - /* fast mode plus, the maximum SCL rise time is 120ns */ - I2C_RT(i2c_periph) = (uint32_t)(((freq*(uint32_t)120U)/(uint32_t)1000U)+(uint32_t)1U); - if(I2C_DTCY_2 == dutycyc){ - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1/(clkspeed*3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - }else{ - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1/(clkspeed*25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - /* enable fast mode */ - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - /* enable I2C fast mode plus */ - I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if(I2C_SMBUS_HOST == type){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if(I2C_ACK_ENABLE == ack){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief configure I2C POAP position - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if(I2C_ACKPOS_NEXT == pos){ - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - }else{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection){ - addr = addr & I2C_TRANSMITTER; - }else{ - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief enable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: the second address in dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) -{ - /* configure address */ - addr = addr & I2C_ADDRESS2_MASK; - I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); -} - -/*! - \brief disable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_dualaddr_disable(uint32_t i2c_periph) -{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none -*/ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SS); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C PEC calculation on or off - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none -*/ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>>STAT1_PECV_OFFSET); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable or disable I2C ARP protocol in SMBus switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; -} - -/*! - \brief disable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); -} - -/*! - \brief enable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; -} - -/*! - \brief disable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(I2C_FLAG_ADDSEND == flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \arg I2C_INT_TFF: txframe fall interrupt enable - \arg I2C_INT_TFR: txframe rise interrupt enable - \arg I2C_INT_RFF: rxframe fall interrupt enable - \arg I2C_INT_RFR: rxframe rise interrupt enable - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)){ - if(intenable && bufie){ - intenable = 1U; - }else{ - intenable = 0U; - } - } - if((0U != flagstatus) && (0U != intenable)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - if(I2C_INT_FLAG_ADDSEND == int_flag){ - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - }else{ - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_misc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_misc.c deleted file mode 100644 index eac0dc0958..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_misc.c +++ /dev/null @@ -1,142 +0,0 @@ -/*! - \file gd32e230_misc.c - \brief MISC driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_misc.h" - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_priority: the priority needed to set (0-3) - \param[out] none - \retval none -*/ -void nvic_irq_enable(uint8_t nvic_irq, - uint8_t nvic_irq_priority) -{ - /* set the priority and enable the selected IRQ */ - NVIC_SetPriority((IRQn_Type)nvic_irq, (uint32_t)nvic_irq_priority); - NVIC_EnableIRQ((IRQn_Type)nvic_irq); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(uint8_t nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC_DisableIRQ((IRQn_Type)nvic_irq); -} - -/* */ -/*! - \brief initiates a system reset request to reset the MCU - \param[in] none - \param[out] none - \retval none -*/ -void nvic_system_reset(void) -{ - NVIC_SystemReset(); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - \arg NVIC_VECTTAB_RAM: RAM base address - \arg NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){ - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - }else{ - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_pmu.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_pmu.c deleted file mode 100644 index 53e8a2e521..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_pmu.c +++ /dev/null @@ -1,301 +0,0 @@ -/*! - \file gd32e230_pmu.c - \brief PMU driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_pmu.h" - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - only one parameter can be selected which is shown as below: - \arg PMU_LVDT_0: voltage threshold is 2.1V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.6V - \arg PMU_LVDT_4: voltage threshold is 2.7V - \arg PMU_LVDT_5: voltage threshold is 2.9V - \arg PMU_LVDT_6: voltage threshold is 3.0V - \arg PMU_LVDT_7: voltage threshold is 3.1V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief select LDO output voltage - these bits set by software when the main PLL closed - \param[in] ldo_output: - only one parameter can be selected which is shown as below: - \arg PMU_LDOVS_LOW: LDO output voltage low mode - \arg PMU_LDOVS_HIGH: LDO output voltage high mode - \param[out] none - \retval none -*/ -void pmu_ldo_output_select(uint32_t ldo_output) -{ - PMU_CTL &= ~PMU_CTL_LDOVS; - PMU_CTL |= ldo_output; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo: - only one parameter can be selected which is shown as below: - \arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) -{ - static uint32_t reg_snap[ 3 ]; - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - reg_snap[ 0 ] = REG32( 0xE000E010U ); - reg_snap[ 1 ] = REG32( 0xE000E100U ); - reg_snap[ 2 ] = REG32( 0xE000E104U ); - - REG32( 0xE000E010U ) &= 0x00010004U; - REG32( 0xE000E180U ) = 0XF7FFEF19U; - REG32( 0xE000E184U ) = 0XFFFFFFFFU; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ - __WFI(); - }else{ - __SEV(); - __WFE(); - __WFE(); - } - - REG32( 0xE000E010U ) = reg_snap[ 0 ] ; - REG32( 0xE000E100U ) = reg_snap[ 1 ] ; - REG32( 0xE000E104U ) = reg_snap[ 2 ] ; - - /* reset sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - __WFE(); - } -} - -/*! - \brief enable wakeup pin - \param[in] wakeup_pin: - one or more parameters can be selected which are shown as below: - \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) - \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) - \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) - \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(uint32_t wakeup_pin) -{ - PMU_CS |= wakeup_pin; -} - -/*! - \brief disable wakeup pin - \param[in] wakeup_pin: - one or more parameters can be selected which are shown as below: - \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) - \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) - \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) - \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(uint32_t wakeup_pin) -{ - PMU_CS &= ~(wakeup_pin); -} - -/*! - \brief enable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief clear flag bit - \param[in] flag_clear: - one or more parameters can be selected which are shown as below: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag_clear) -{ - if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){ - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - } - if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){ - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - } -} - -/*! - \brief get flag state - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \param[out] none - \retval FlagStatus SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - FlagStatus ret_status = RESET; - - if(PMU_CS & flag){ - ret_status = SET; - } - - return ret_status; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rcu.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rcu.c deleted file mode 100644 index 9483fa68f9..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rcu.c +++ /dev/null @@ -1,1034 +0,0 @@ -/*! - \file gd32e230_rcu.c - \brief RCU driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_rcu.h" - -/* define clock source */ -#define SEL_IRC8M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLL 0x02U - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL0 |= RCU_CTL0_IRC8MEN; - while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){ - } - /* reset RCU */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\ - RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); - RCU_CFG1 &= ~(RCU_CFG1_PREDV); - RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; - RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; - RCU_INT = 0x00000000U; -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,F): GPIO ports clock - \arg RCU_DMA: DMA clock - \arg RCU_CRC: CRC clock - \arg RCU_CFGCMP: CFGCMP clock - \arg RCU_ADC: ADC clock - \arg RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock - \arg RCU_SPIx (x=0,1): SPI clock - \arg RCU_USARTx (x=0,1): USART clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_PMU: PMU clock - \arg RCU_RTC: RTC clock - \arg RCU_DBGMCU: DBGMCU clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,F): GPIO ports clock - \arg RCU_DMA: DMA clock - \arg RCU_CRC: CRC clock - \arg RCU_CFGCMP: CFGCMP clock - \arg RCU_ADC: ADC clock - \arg RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock - \arg RCU_SPIx (x=0,1): SPI clock - \arg RCU_USARTx (x=0,1): USART clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_PMU: PMU clock - \arg RCU_RTC: RTC clock - \arg RCU_DBGMCU: DBGMCU clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports - \arg RCU_CFGCMPRST: reset CFGCMP - \arg RCU_ADCRST: reset ADC - \arg RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER - \arg RCU_SPIxRST (x=0,1): reset SPI - \arg RCU_USARTxRST (x=0,1): reset USART - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_PMURST: reset PMU - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports - \arg RCU_CFGCMPRST: reset CFGCMP - \arg RCU_ADCRST: reset ADC - \arg RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER - \arg RCU_SPIxRST (x=0,1): reset SPI - \arg RCU_USARTxRST (x=0,1): reset USART - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_PMURST: reset PMU - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t cksys_source = 0U; - cksys_source = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - cksys_source &= ~RCU_CFG0_SCS; - RCU_CFG0 = (ck_sys | cksys_source); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t ahbpsc = 0U; - ahbpsc = RCU_CFG0; - /* reset the AHBPSC bits and set according to ck_ahb */ - ahbpsc &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (ck_ahb | ahbpsc); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t apb1psc = 0U; - apb1psc = RCU_CFG0; - /* reset the APB1PSC and set according to ck_apb1 */ - apb1psc &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (ck_apb1 | apb1psc); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t apb2psc = 0U; - apb2psc = RCU_CFG0; - /* reset the APB2PSC and set according to ck_apb2 */ - apb2psc &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (ck_apb2 | apb2psc); -} - -/*! - \brief configure the ADC clock prescaler selection - \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum - only one parameter can be selected which is shown as below: - \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC - \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC - \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC - \arg RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC - \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC - \arg RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC - \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC - \arg RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC - \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC - \arg RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc) -{ - /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */ - RCU_CFG0 &= ~RCU_CFG0_ADCPSC; - RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2); - - /* set the ADC clock according to ck_adc */ - switch(ck_adc){ - case RCU_ADCCK_IRC28M_DIV2: - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_IRC28M: - RCU_CFG2 |= RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV2: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV3: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV4: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV5: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV6: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV7: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV8: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV9: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - default: - break; - } -} - -/*! - \brief configure the CK_OUT clock source and divider - \param[in] ckout_src: CK_OUT clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUTSRC_NONE: no clock selected - \arg RCU_CKOUTSRC_IRC28M: IRC28M selected - \arg RCU_CKOUTSRC_IRC40K: IRC40K selected - \arg RCU_CKOUTSRC_LXTAL: LXTAL selected - \arg RCU_CKOUTSRC_CKSYS: CKSYS selected - \arg RCU_CKOUTSRC_IRC8M: IRC8M selected - \arg RCU_CKOUTSRC_HXTAL: HXTAL selected - \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected - \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected - \param[in] ckout_div: CK_OUT divider - \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x - \param[out] none - \retval none -*/ -void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div) -{ - uint32_t ckout = 0U; - ckout = RCU_CFG0; - /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */ - ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 = (ckout | ckout_src | ckout_div); -} - -/*! - \brief configure the PLL clock source selection and PLL multiply factor - \param[in] pll_src: PLL clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock - \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock - \param[in] pll_mul: PLL multiply factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL_MULx(x=2..32): PLL source clock * x - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (pll_src | pll_mul); -} - -/*! - \brief configure the USART clock source selection - \param[in] ck_usart: USART clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2 - \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS - \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL - \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M - \param[out] none - \retval none -*/ -void rcu_usart_clock_config(uint32_t ck_usart) -{ - /* reset the USART0SEL bits and set according to ck_usart */ - RCU_CFG2 &= ~RCU_CFG2_USART0SEL; - RCU_CFG2 |= ck_usart; -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - /* reset the RTCSRC bits and set according to rtc_clock_source */ - RCU_BDCTL &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL |= rtc_clock_source; -} - -/*! - \brief configure the HXTAL divider used as input of PLL - \param[in] hxtal_prediv: HXTAL divider used as input of PLL - only one parameter can be selected which is shown as below: - \arg RCU_PLL_PREDVx(x=1..16): HXTAL divided x used as input of PLL - \param[out] none - \retval none -*/ -void rcu_hxtal_prediv_config(uint32_t hxtal_prediv) -{ - uint32_t prediv = 0U; - prediv = RCU_CFG1; - /* reset the PREDV bits and set according to hxtal_prediv */ - prediv &= ~RCU_CFG1_PREDV; - RCU_CFG1 = (prediv | hxtal_prediv); -} - -/*! - \brief configure the LXTAL drive capability - \param[in] lxtal_dricap: drive capability of LXTAL - only one parameter can be selected which is shown as below: - \arg RCU_LXTAL_LOWDRI: lower driving capability - \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability - \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability - \arg RCU_LXTAL_HIGHDRI: higher driving capability - \param[out] none - \retval none -*/ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) -{ - /* reset the LXTALDRI bits and set according to lxtal_dricap */ - RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI; - RCU_BDCTL |= lxtal_dricap; -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag - \arg RCU_FLAG_V12RST: V12 domain power reset flag - \arg RCU_FLAG_OBLRST: option byte loader reset flag - \arg RCU_FLAG_EPRST: external pin reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable - \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief wait until oscillator stabilization flags is SET - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - switch(osci){ - case RCU_HXTAL: - /* wait until HXTAL is stabilization and osci_stat is not more than timeout */ - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC28M stable */ - case RCU_IRC28M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ - reval = SUCCESS; - } - break; - - default: - break; - } - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - switch(osci){ - case RCU_HXTAL: - /* HXTALEN must be reset before enable the oscillator bypass mode */ - reg = RCU_CTL0; - RCU_CTL0 &= ~RCU_CTL0_HXTALEN; - RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS); - break; - case RCU_LXTAL: - /* LXTALEN must be reset before enable the oscillator bypass mode */ - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC28M: - case RCU_IRC40K: - case RCU_PLL_CK: - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - switch(osci){ - case RCU_HXTAL: - /* HXTALEN must be reset before disable the oscillator bypass mode */ - reg = RCU_CTL0; - RCU_CTL0 &= ~RCU_CTL0_HXTALEN; - RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS)); - break; - case RCU_LXTAL: - /* LXTALEN must be reset before disable the oscillator bypass mode */ - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS)); - break; - case RCU_IRC8M: - case RCU_IRC28M: - case RCU_IRC40K: - case RCU_PLL_CK: - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL0 |= RCU_CTL0_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL0 &= ~RCU_CTL0_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) -{ - uint32_t adjust = 0U; - adjust = RCU_CTL0; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - adjust &= ~RCU_CTL0_IRC8MADJ; - RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval)<<3)); -} - -/*! - \brief set the IRC28M adjust value - \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval) -{ - uint32_t adjust = 0U; - adjust = RCU_CTL1; - /* reset the IRC28MADJ bits and set according to irc28m_adjval */ - adjust &= ~RCU_CTL1_IRC28MADJ; - RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval)<<3)); -} - -/*! - \brief unlock the voltage key - \param[in] none - \param[out] none - \retval none -*/ -void rcu_voltage_key_unlock(void) -{ - /* reset the KEY bits and set 0x1A2B3C4D */ - RCU_VKEY &= ~RCU_VKEY_KEY; - RCU_VKEY |= RCU_VKEY_UNLOCK; -} - -/*! - \brief set voltage in deep sleep mode - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - /* reset the DSLPVS bits and set according to dsvol */ - RCU_DSV &= ~RCU_DSV_DSLPVS; - RCU_DSV |= dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \arg CK_ADC: ADC clock frequency - \arg CK_USART: USART0 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2, ADC or USRAT0 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U; - uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U; - uint32_t adc_freq = 0U, usart_freq = 0U; - uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; - /* exponent of AHB, APB1 and APB2 clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* get the value of PLLMF[3:0] */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - pllmf4 = GET_BITS(RCU_CFG0, 27, 27); - /* high 16 bits */ - if(1U == pllmf4){ - pllmf += 17U; - }else if(15U == pllmf){ - pllmf = 16U; - }else{ - pllmf += 2U; - } - - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = GET_BITS(RCU_CFG0, 16, 16); - if(0U != pllsel){ - prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); - cksys_freq = (HXTAL_VALUE / prediv) * pllmf; - }else{ - cksys_freq = (IRC8M_VALUE >> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock){ - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - case CK_ADC: - /* calculate ADC clock frequency */ - if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)){ - if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)){ - adc_freq = IRC28M_VALUE >> 1; - }else{ - adc_freq = IRC28M_VALUE; - } - }else{ - /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */ - adcps = GET_BITS(RCU_CFG0, 14, 15); - adcps2 = GET_BITS(RCU_CFG2, 31, 31); - if(0U != adcps2){ - /* ADC clock select CK_AHB divided by 3/5/7/9 */ - adc_freq = ahb_freq / (adcps + 1U); - }else{ - /* ADC clock select CK_APB2 divided by 2/4/6/8 */ - adc_freq = apb2_freq / adcps; - } - } - ck_freq = adc_freq; - break; - case CK_USART: - /* calculate USART0 clock frequency */ - if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = apb2_freq; - }else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = cksys_freq; - }else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = LXTAL_VALUE; - }else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)){ - usart_freq = IRC8M_VALUE; - }else{ - } - ck_freq = usart_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rtc.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rtc.c deleted file mode 100644 index 546afa781e..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_rtc.c +++ /dev/null @@ -1,965 +0,0 @@ -/*! - \file gd32e230_rtc.c - \brief RTC driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_rtc.h" - -/*! - \brief reset most of the RTC registers - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_deinit(void) -{ - ErrStatus error_status = ERROR; - - /* RTC_TAMP register is not under write protection */ - RTC_TAMP = RTC_REGISTER_RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* reset RTC_CTL register, this can be done without the init mode */ - RTC_CTL &= RTC_REGISTER_RESET; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. - in order to read calendar from shadow register, not the real registers being reset */ - RTC_TIME = RTC_REGISTER_RESET; - RTC_DATE = RTC_DATE_RESET; - - RTC_PSC = RTC_PSC_RESET; - - /* reset RTC_STAT register, also exit init mode. - at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ - RTC_STAT = RTC_STAT_RESET; - - /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */ - RTC_ALRM0TD = RTC_REGISTER_RESET; - RTC_ALRM0SS = RTC_REGISTER_RESET; - - /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ - RTC_SHIFTCTL = RTC_REGISTER_RESET; - RTC_HRFC = RTC_REGISTER_RESET; - - error_status = rtc_register_sync_wait(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief initialize RTC registers - \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - rtc_year: 0x0 - 0x99(BCD format) - rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_date: 0x1 - 0x31(BCD format) - rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - rtc_minute: 0x0 - 0x59(BCD format) - rtc_second: 0x0 - 0x59(BCD format) - rtc_factor_asyn: 0x0 - 0x7F - rtc_factor_syn: 0x0 - 0x7FFF - rtc_am_pm: RTC_AM, RTC_PM - rtc_display_format: RTC_24HOUR, RTC_12HOUR - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct) -{ - ErrStatus error_status = ERROR; - uint32_t reg_time = 0x00U, reg_date = 0x00U; - - reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \ - DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \ - DATE_MON(rtc_initpara_struct->rtc_month) | \ - DATE_DAY(rtc_initpara_struct->rtc_date)); - - reg_time = (rtc_initpara_struct->rtc_am_pm| \ - TIME_HR(rtc_initpara_struct->rtc_hour) | \ - TIME_MN(rtc_initpara_struct->rtc_minute) | \ - TIME_SC(rtc_initpara_struct->rtc_second)); - - /* 1st: disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* 2nd: enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn)| \ - PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn)); - - RTC_TIME = (uint32_t)reg_time; - RTC_DATE = (uint32_t)reg_date; - - RTC_CTL &= (uint32_t)(~RTC_CTL_CS); - RTC_CTL |= rtc_initpara_struct->rtc_display_format; - - /* 3rd: exit init mode */ - rtc_init_mode_exit(); - - /* 4th: wait the RSYNF flag to set */ - error_status = rtc_register_sync_wait(); - } - - /* 5th: enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enter RTC init mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init_mode_enter(void) -{ - uint32_t time_index = RTC_INITM_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - /* check whether it has been in init mode */ - if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)){ - RTC_STAT |= RTC_STAT_INITM; - - /* wait until the INITF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_INITF; - }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); - - if((uint32_t)RESET != flag_status){ - error_status = SUCCESS; - } - }else{ - error_status = SUCCESS; - } - return error_status; -} - -/*! - \brief exit RTC init mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_init_mode_exit(void) -{ - RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); -} - -/*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow - registers are updated - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_register_sync_wait(void) -{ - volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)){ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* firstly clear RSYNF flag */ - RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); - - /* wait until RSYNF flag to be set */ - do{ - flag_status = RTC_STAT & RTC_STAT_RSYNF; - }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); - - if((uint32_t)RESET != flag_status){ - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - }else{ - error_status = SUCCESS; - } - - return error_status; -} - -/*! - \brief get current time and date - \param[in] none - \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - rtc_year: 0x0 - 0x99(BCD format) - rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_date: 0x1 - 0x31(BCD format) - rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - rtc_minute: 0x0 - 0x59(BCD format) - rtc_second: 0x0 - 0x59(BCD format) - rtc_factor_asyn: 0x0 - 0x7F - rtc_factor_syn: 0x0 - 0x7FFF - rtc_am_pm: RTC_AM, RTC_PM - rtc_display_format: RTC_24HOUR, RTC_12HOUR - \retval none -*/ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct) -{ - uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U; - - temp_tr = (uint32_t)RTC_TIME; - temp_dr = (uint32_t)RTC_DATE; - temp_pscr = (uint32_t)RTC_PSC; - temp_ctlr = (uint32_t)RTC_CTL; - - /* get current time and construct rtc_parameter_struct structure */ - rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr); - rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr); - rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr); - rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); - rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr); - rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr); - rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr); - rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); - rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_pscr & RTC_TIME_PM); - rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); -} - -/*! - \brief get current subsecond value - \param[in] none - \param[out] none - \retval current subsecond value -*/ -uint32_t rtc_subsecond_get(void) -{ - uint32_t reg = 0x00U; - /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ - reg = (uint32_t)RTC_SS; - /* read RTC_DATE to unlock the 3 shadow registers */ - (void) (RTC_DATE); - - return reg; -} - -/*! - \brief configure RTC alarm - \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_alarm_minute: 0x0 - 0x59(BCD format) - rtc_alarm_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \param[out] none - \retval none -*/ -void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time) -{ - uint32_t reg_alrm0td = 0x00U; - - reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \ - rtc_alarm_time->rtc_weekday_or_date | \ - rtc_alarm_time->rtc_am_pm | \ - ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \ - ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \ - ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \ - ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second)); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_ALRM0TD = (uint32_t)reg_alrm0td; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief configure subsecond of RTC alarm - \param[in] mask_subsecond: alarm subsecond mask - only one parameter can be selected which is shown as below: - \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration - \arg RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared - \arg RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared - \arg RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared - \arg RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared - \arg RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared - \arg RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared - \arg RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared - \arg RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared - \arg RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared - \arg RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared - \arg RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared - \arg RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared - \arg RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared - \arg RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared - \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared - \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) - \param[out] none - \retval none -*/ -void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_ALRM0SS = mask_subsecond | subsecond; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief enable RTC alarm - \param[in] none - \param[out] none - \retval none -*/ -void rtc_alarm_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= RTC_CTL_ALRM0EN; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC alarm - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_alarm_disable(void) -{ - volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the state of alarm */ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); - - /* wait until ALRM0WF flag to be set after the alarm is disabled */ - do{ - flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - }while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); - - if((uint32_t)RESET != flag_status){ - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief get RTC alarm - \param[in] none - \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_alarm_minute: 0x0 - 0x59(BCD format) - rtc_alarm_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time) -{ - uint32_t reg_alrm0td = 0x00U; - - /* get the value of RTC_ALRM0TD register */ - reg_alrm0td = RTC_ALRM0TD; - - /* get alarm parameters and construct the rtc_alarm_struct structure */ - rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; - rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM); - rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS); - rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td); - rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td); - rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td); - rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td); -} - -/*! - \brief get RTC alarm subsecond - \param[in] none - \param[out] none - \retval RTC alarm subsecond value -*/ -uint32_t rtc_alarm_subsecond_get(void) -{ - return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); -} - -/*! - \brief enable RTC time-stamp - \param[in] edge: specify which edge to detect of time-stamp - only one parameter can be selected which is shown as below: - \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event - \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event - \param[out] none - \retval none -*/ -void rtc_timestamp_enable(uint32_t edge) -{ - uint32_t reg_ctl = 0x00U; - - /* clear the bits to be configured in RTC_CTL */ - reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); - - /* new configuration */ - reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL = (uint32_t)reg_ctl; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC time-stamp - \param[in] none - \param[out] none - \retval none -*/ -void rtc_timestamp_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the TSEN bit */ - RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief get RTC timestamp time and date - \param[in] none - \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains - parameters for RTC time-stamp configuration - members of the structure and the member values are shown as below: - rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_timestamp_date: 0x1 - 0x31(BCD format) - rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_timestamp_minute: 0x0 - 0x59(BCD format) - rtc_timestamp_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp) -{ - uint32_t temp_tts = 0x00U, temp_dts = 0x00U; - - /* get the value of time_stamp registers */ - temp_tts = (uint32_t)RTC_TTS; - temp_dts = (uint32_t)RTC_DTS; - - /* get timestamp time and construct the rtc_timestamp_struct structure */ - rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); - rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); - rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); - rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); - rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); - rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); - rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); -} - -/*! - \brief get RTC time-stamp subsecond - \param[in] none - \param[out] none - \retval RTC time-stamp subsecond value -*/ -uint32_t rtc_timestamp_subsecond_get(void) -{ - return ((uint32_t)RTC_SSTS); -} - -/*! - \brief enable RTC tamper - \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains - parameters for RTC tamper configuration - members of the structure and the member values are shown as below: - rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 - rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING - RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH - rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S - rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, - RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, - RTC_FREQ_DIV512, RTC_FREQ_DIV256 - rtc_tamper_precharge_enable: DISABLE, ENABLE - rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C - rtc_tamper_with_timestamp: DISABLE, ENABLE - \param[out] none - \retval none -*/ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source); - - /* tamper filter must be used when the tamper source is voltage level detection */ - RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; - - /* the tamper source is voltage level detection */ - if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE ){ - RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); - - /* check if the tamper pin need precharge, if need, then configure the precharge time */ - if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable){ - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; - }else{ - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time); - } - - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency); - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter); - } - - RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - - if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp){ - /* the tamper event also cause a time-stamp event */ - RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; - } - - /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger){ - RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source)<< RTC_TAMPER_TRIGGER_POS); - } - /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source); -} - -/*! - \brief disable RTC tamper - \param[in] source: specify which tamper source to be disabled - only one parameter can be selected which is shown as below: - \arg RTC_TAMPER0 - \arg RTC_TAMPER1 - \param[out] none - \retval none -*/ -void rtc_tamper_disable(uint32_t source) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~source; - -} - -/*! - \brief enable specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be enabled - only one parameter can be selected which is shown as below: - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enable the interrupts in RTC_CTL register */ - RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* enable the interrupts in RTC_TAMP register */ - RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disble specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be disabled - only one parameter can be selected which is shown as below: - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* disable the interrupts in RTC_CTL register */ - RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* disable the interrupts in RTC_TAMP register */ - RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief check specified flag - \param[in] flag: specify which flag to check - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_RECALIBRATION: recalibration pending flag - \arg RTC_FLAG_TAMP1: tamper 1 event flag - \arg RTC_FLAG_TAMP0: tamper 0 event flag - \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag - \arg RTC_FLAG_TIMESTAMP: time-stamp event flag - \arg RTC_FLAG_ALARM0: alarm event flag - \arg RTC_FLAG_INIT: init mode event flag - \arg RTC_FLAG_RSYN: time and date registers synchronized event flag - \arg RTC_FLAG_YCM: year parameter configured event flag - \arg RTC_FLAG_SHIFT: shift operation pending flag - \arg RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - FlagStatus flag_state = RESET; - - if((uint32_t)RESET != (RTC_STAT & flag)){ - flag_state = SET; - } - return flag_state; -} - -/*! - \brief clear specified flag - \param[in] flag: specify which flag to clear - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_TAMP1: tamper 1 event flag - \arg RTC_FLAG_TAMP0: tamper 0 event flag - \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag - \arg RTC_FLAG_TIMESTAMP: time-stamp event flag - \arg RTC_FLAG_ALARM0: alarm event flag - \arg RTC_FLAG_RSYN: time and date registers synchronized event flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - RTC_STAT &= (uint32_t)(~flag); -} - -/*! - \brief configure rtc alternate output source - \param[in] source: specify signal to output - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_512HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal - \arg RTC_CALIBRATION_1HZ: when the LSE freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal - \arg RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high - \arg RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low - \param[in] mode: specify the output pin (PC13) mode when output alarm signal - only one parameter can be selected which is shown as below: - \arg RTC_ALARM_OUTPUT_OD: open drain mode - \arg RTC_ALARM_OUTPUT_PP: push pull mode - \param[out] none - \retval none -*/ -void rtc_alter_output_config(uint32_t source, uint32_t mode) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS); - - RTC_CTL |= (uint32_t)(source); - - /* alarm output */ - if((uint32_t)RESET != (source & RTC_OS_ENABLE)){ - RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL); - RTC_TAMP |= (uint32_t)(mode); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief configure RTC calibration register - \param[in] window: select calibration window - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz - \param[in] plus: add RTC clock or not - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock - \arg RTC_CALIBRATION_PLUS_RESET: no effect - \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) -{ - uint32_t time_index = RTC_HRFC_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a calibration operation is ongoing */ - do{ - flag_status = RTC_STAT & RTC_STAT_SCPF; - }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET == flag_status){ - RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief adjust the daylight saving time by adding or substracting one hour from the current time - \param[in] operation: hour ajustment operation - only one parameter can be selected which is shown as below: - \arg RTC_CTL_A1H: add one hour - \arg RTC_CTL_S1H: substract one hour - \param[out] none - \retval none -*/ -void rtc_hour_adjust(uint32_t operation) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= (uint32_t)(operation); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief adjust RTC second or subsecond value of current time - \param[in] add: add 1s to current time or not - only one parameter can be selected which is shown as below: - \arg RTC_SHIFT_ADD1S_RESET: no effect - \arg RTC_SHIFT_ADD1S_SET: add 1s to current time - \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) -{ - uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - uint32_t temp=0U; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a shift operation is ongoing */ - do{ - flag_status = RTC_STAT & RTC_STAT_SOPF; - }while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status)); - - temp = RTC_CTL & RTC_CTL_REFEN; - /* check if the function of reference clock detection is disabled */ - if(((uint32_t)RESET == flag_status) && (RESET == temp)){ - RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); - error_status = rtc_register_sync_wait(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief enable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_enable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL |= (uint32_t)RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief disable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_disable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status){ - RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_spi.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_spi.c deleted file mode 100644 index a48f5c426a..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_spi.c +++ /dev/null @@ -1,1003 +0,0 @@ -/*! - \file gd32e230_spi.c - \brief SPI driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_spi.h" - -/* SPI/I2S parameter initialization mask */ -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI0 parameter initialization mask */ -#define SPI_FIFO_INIT_MASK1 ((uint32_t)0x00003840U) /*!< SPI1 parameter initialization mask1 */ -#define SPI_FIFO_INIT_MASK2 ((uint32_t)0x0000F0FFU) /*!< SPI1 parameter initialization mask2*/ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -#define SPI_FRAMESIZE_MASK ((uint32_t)0x00000800U) /*!< SPI0 frame size mask */ -#define SPI_BYTEN_MASK ((uint32_t)0x00001000U) /*!< SPI1 access to FIFO mask */ -#define SPI_TXLVL_EMPTY_MASK ((uint32_t)0x00001800U) /*!< SPI1 TXFIFO empty mask */ -#define SPI_RXLVL_EMPTY_MASK ((uint32_t)0x00000600U) /*!< SPI1 RXFIFO empty mask */ - -/* I2S clock source selection, multiplication and division mask */ -#define SPI_I2SPSC_RESET ((uint32_t)0x00000002U) /*!< I2S clock prescaler register reset value */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph){ - case SPI0: - /* reset SPI0 and I2S0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - default : - break; - } -} - -/*! - \brief initialize the parameters of SPI struct with the default values - \param[in] spi_struct: SPI parameter stuct - \param[out] none - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct* spi_struct) -{ - /* set the SPI struct with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; -} - -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_4BIT, SPI_FRAMESIZE_5BIT - SPI_FRAMESIZE_6BIT, SPI_FRAMESIZE_7BIT - SPI_FRAMESIZE_8BIT, SPI_FRAMESIZE_9BIT - SPI_FRAMESIZE_10BIT, SPI_FRAMESIZE_11BIT - SPI_FRAMESIZE_12BIT, SPI_FRAMESIZE_13BIT - SPI_FRAMESIZE_14BIT, SPI_FRAMESIZE_15BIT - SPI_FRAMESIZE_16BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ - uint32_t reg1, reg2, reg3 = 0U; - - reg1 = SPI_CTL0(spi_periph); - reg1 &= SPI_INIT_MASK; - - reg2 = SPI_CTL0(spi_periph); - reg2 &= SPI_FIFO_INIT_MASK1; - - reg3 = SPI_CTL1(spi_periph); - reg3 &= SPI_FIFO_INIT_MASK2; - - if( SPI0 == spi_periph){ - /* select SPI as master or slave */ - reg1 |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg1 |= spi_struct->trans_mode; - /* select SPI NSS use hardware or software */ - reg1 |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg1 |= spi_struct->endian; - /* select SPI polarity and phase */ - reg1 |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg1 |= spi_struct->prescale; - /* select SPI frame size */ - /* check SPI0 frame size is 8bits/16bits or not*/ - if((SPI_FRAMESIZE_8BIT != spi_struct->frame_size) && (SPI_FRAMESIZE_16BIT != spi_struct->frame_size)) - { - return ERROR; - }else{ - reg1 |= (spi_struct->frame_size & SPI_FRAMESIZE_MASK); - } - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg1; - - }else{ - /* select SPI as master or slave */ - reg2 |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg2 |= spi_struct->trans_mode; - /* select SPI NSS use hardware or software */ - reg2 |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg2 |= spi_struct->endian; - /* select SPI polarity and phase */ - reg2 |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg2 |= spi_struct->prescale; - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg2; - - /* select SPI data size */ - reg3 |= spi_struct->frame_size; - /* write to SPI_CTL0 register */ - SPI_CTL1(spi_periph) = (uint32_t)reg3; - } - - /* select SPI mode */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); - - return SUCCESS; -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPIx(x=0) - \param[in] mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg = 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPIx(x=0) - \param[in] audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_RESET; - - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout){ - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)){ - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=0) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=0) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_4BIT: SPI frame size is 4 bits - \arg SPI_FRAMESIZE_5BIT: SPI frame size is 5 bits - \arg SPI_FRAMESIZE_6BIT: SPI frame size is 6 bits - \arg SPI_FRAMESIZE_7BIT: SPI frame size is 7 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \arg SPI_FRAMESIZE_9BIT: SPI frame size is 9 bits - \arg SPI_FRAMESIZE_10BIT: SPI frame size is 10 bits - \arg SPI_FRAMESIZE_11BIT: SPI frame size is 11 bits - \arg SPI_FRAMESIZE_12BIT: SPI frame size is 12 bits - \arg SPI_FRAMESIZE_13BIT: SPI frame size is 13 bits - \arg SPI_FRAMESIZE_14BIT: SPI frame size is 14 bits - \arg SPI_FRAMESIZE_15BIT: SPI frame size is 15 bits - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - if(SPI0 == spi_periph) - { - /* check SPI0 frame size is 8bits/16bits or not*/ - if((SPI_FRAMESIZE_8BIT != frame_format) && (SPI_FRAMESIZE_16BIT != frame_format)) - { - return ERROR; - }else{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* configure SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= ((uint32_t)frame_format & SPI_FRAMESIZE_MASK); - } - } - else{ - /* clear SPI_CTL1_DZ bits */ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DZ); - /* confige SPI_CTL1_DZ bits */ - SPI_CTL1(spi_periph) |= (uint32_t)frame_format; - } - return SUCCESS; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - uint32_t reg, byten; - if(SPI0 == spi_periph) - { - SPI_DATA(spi_periph) = (uint32_t)data; - } - else - { - /* get the access size to FIFO */ - byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK; - if(RESET != byten) - { - reg = spi_periph + 0x0CU; - *( uint8_t *)(reg) = (uint8_t)data; - }else - { - SPI_DATA(spi_periph) = (uint16_t)data; - } - } -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - uint32_t reg, byten; - if(SPI0 == spi_periph) - { - return ((uint16_t)SPI_DATA(spi_periph)); - } - else - { - /* get the access size to FIFO */ - byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK; - if(RESET != byten) - { - reg = spi_periph + 0x0CU; - return (uint16_t)(*(uint8_t *)(reg)); - }else - { - return ((uint16_t)SPI_DATA(spi_periph)); - } - } -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit-only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive-only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1) - \param[in] crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) -{ - if(SPI_CRC_TX == crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - -/*! - \brief enable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nssp_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; -} - -/*! - \brief disable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nssp_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); -} - -/*! - \brief enable quad wire SPI - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void qspi_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; -} - -/*! - \brief disable quad wire SPI - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void qspi_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); -} - -/*! - \brief enable quad wire SPI write - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void qspi_write_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); -} - -/*! - \brief enable quad wire SPI read - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void qspi_read_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; -} - -/*! - \brief enable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void qspi_io23_output_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; -} - - /*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ - void qspi_io23_output_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default : - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt flag status - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI/I2S format error interrupt */ - case SPI_I2S_INT_FLAG_FERR: - reg1 = reg1 & SPI_STAT_FERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - /*get SPI/I2S interrupt flag status */ - if((0U != reg1) && (0U != reg2)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[in] flag: SPI/I2S flag status - one or more parameters can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - only for SPI1: - \arg SPI_TXLVL_EMPTY: SPI TXFIFO is empty - \arg SPI_TXLVL_QUARTER_FULL: SPI TXFIFO is a quarter of full - \arg SPI_TXLVL_HAlF_FULL: SPI TXFIFO is a half of full - \arg SPI_TXLVL_FULL: SPI TXFIFO is full - \arg SPI_RXLVL_EMPTY: SPI RXFIFO is empty - \arg SPI_RXLVL_QUARTER_FULL: SPI RXFIFO is a quarter of full - \arg SPI_RXLVL_HAlF_FULL: SPI RXFIFO is a half of full - \arg SPI_RXLVL_FULL: SPI RXFIFO is full - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(RESET != (SPI_STAT(spi_periph) & flag)){ - return SET; - }else{ - if(SPI1 == spi_periph){ - /* check TXFIFO is empty or not */ - if(SPI_TXLVL_EMPTY == flag){ - if(RESET != (SPI_STAT(spi_periph) & SPI_TXLVL_EMPTY_MASK)){ - return RESET; - }else{ - return SET; - } - } - /* check RXFIFO is empty or not */ - if(SPI_RXLVL_EMPTY == flag){ - if(RESET != (SPI_STAT(spi_periph) & SPI_RXLVL_EMPTY_MASK)){ - return RESET; - }else{ - return SET; - } - } - } - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} - -/*! - \brief configure SPI1 access size to FIFO(8bit or 16bit) - \param[in] spi_periph: SPIx(x=1) - \param[in] fifo_access_size: byte access enable - only one parameter can be selected which is shown as below: - \arg SPI_HALFWORD_ACCESS: half-word access to FIFO - \arg SPI_BYTE_ACCESS: byte access to FIFO - \param[out] none - \retval none -*/ -void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size) -{ - /* clear SPI_CTL1_BYTEN bit */ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_BYTEN); - /* confige SPI_CTL1_BYTEN bit */ - SPI_CTL1(spi_periph) |= (uint32_t)fifo_access_size; -} - -/*! - \brief configure SPI1 total number of data to transmit by DMA is odd or not - \param[in] spi_periph: SPIx(x=1) - \param[in] odd: odd bytes in TX DMA channel - only one parameter can be selected which is shown as below: - \arg SPI_TXDMA_EVEN: number of byte in TX DMA channel is even - \arg SPI_TXDMA_ODD: number of byte in TX DMA channel is odd - \param[out] none - \retval none -*/ -void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd) -{ - /* clear SPI_CTL1_TXDMA_ODD bit */ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TXDMA_ODD); - /* confige SPI_CTL1_TXDMA_ODD bit */ - SPI_CTL1(spi_periph) |= (uint32_t)odd; -} - -/*! - \brief configure SPI1 total number of data to receive by DMA is odd or not - \param[in] spi_periph: SPIx(x=1) - \param[in] odd: odd bytes in RX DMA channel - only one parameter can be selected which is shown as below: - \arg SPI_RXDMA_EVEN: number of bytes in RX DMA channel is even - \arg SPI_RXDMA_ODD: number of bytes in RX DMA channel is odd - \param[out] none - \retval none -*/ -void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd) -{ - /* clear SPI_CTL1_RXDMA_ODD bit */ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RXDMA_ODD); - /* confige SPI_CTL1_RXDMA_ODD bit */ - SPI_CTL1(spi_periph) |= (uint32_t)odd; -} - -/*! - \brief set CRC length - \param[in] spi_periph: SPIx(x=1) - \param[in] crc_length: CRC length - only one parameter can be selected which is shown as below: - \arg SPI_CRC_8BIT: CRC length is 8 bits - \arg SPI_CRC_16BIT: CRC length is 16 bits - \param[out] none - \retval none -*/ -void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length) -{ - /* clear SPI_CTL0_CRCL bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCL); - /* confige SPI_CTL0_CRCL bit */ - SPI_CTL0(spi_periph) |= (uint32_t)crc_length; -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_syscfg.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_syscfg.c deleted file mode 100644 index a0e79e4176..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_syscfg.c +++ /dev/null @@ -1,207 +0,0 @@ - /*! - \file gd32e230_syscfg.h - \brief SYSCFG driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_syscfg.h" - -/*! - \brief reset the SYSCFG registers - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_deinit(void) -{ - rcu_periph_reset_enable(RCU_CFGCMPRST); - rcu_periph_reset_disable(RCU_CFGCMPRST); -} - -/*! - \brief enable the DMA channels remapping - \param[in] syscfg_dma_remap: specify the DMA channels to remap - \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) - \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) - \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) - \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) - \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 - \arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12 - \param[out] none - \retval none -*/ -void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap) -{ - SYSCFG_CFG0 |= syscfg_dma_remap; -} - -/*! - \brief disable the DMA channels remapping - \param[in] syscfg_dma_remap: specify the DMA channels to remap - \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) - \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) - \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) - \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) - \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 - \arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12 - \param[out] none - \retval none -*/ -void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap) -{ - SYSCFG_CFG0 &= ~syscfg_dma_remap; -} - -/*! - \brief enable PB9 high current capability - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_high_current_enable(void) -{ - SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE; -} - -/*! - \brief disable PB9 high current capability - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_high_current_disable(void) -{ - SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE; -} - -/*! - \brief configure the GPIO pin as EXTI Line - \param[in] exti_port: specify the GPIO port used in EXTI - \arg EXTI_SOURCE_GPIOx(x = A,B,C,F): EXTI GPIO port - \param[in] exti_pin: specify the EXTI line - \arg EXTI_SOURCE_PINx(GPIOA x = 0..15,GPIOB x = 0..15,GPIOC x = 13..15,GPIOF x = 0.1.6.7): EXTI GPIO pin - \param[out] none - \retval none -*/ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) -{ - uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); - uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); - - switch(exti_pin / EXTI_SS_JSTEP){ - case EXTISS0: - /* clear EXTI source line(0..3) */ - SYSCFG_EXTISS0 &= clear_exti_mask; - /* configure EXTI soure line(0..3) */ - SYSCFG_EXTISS0 |= config_exti_mask; - break; - case EXTISS1: - /* clear EXTI soure line(4..7) */ - SYSCFG_EXTISS1 &= clear_exti_mask; - /* configure EXTI soure line(4..7) */ - SYSCFG_EXTISS1 |= config_exti_mask; - break; - case EXTISS2: - /* clear EXTI soure line(8..11) */ - SYSCFG_EXTISS2 &= clear_exti_mask; - /* configure EXTI soure line(8..11) */ - SYSCFG_EXTISS2 |= config_exti_mask; - break; - case EXTISS3: - /* clear EXTI soure line(12..15) */ - SYSCFG_EXTISS3 &= clear_exti_mask; - /* configure EXTI soure line(12..15) */ - SYSCFG_EXTISS3 |= config_exti_mask; - break; - default: - break; - } -} - -/*! - \brief connect TIMER0/14/15/16 break input to the selected parameter - \param[in] syscfg_lock: Specify the parameter to be connected - \arg SYSCFG_LOCK_LOCKUP: Cortex-M23 lockup output connected to the break input - \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input - \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input - \param[out] none - \retval none -*/ -void syscfg_lock_config(uint32_t syscfg_lock) -{ - SYSCFG_CFG2 |= syscfg_lock; -} - -/*! - \brief set the wait state counter value - \param[in] irq_latency: IRQ_LATENCY value (0x00 - 0xFF) - \param[out] none - \retval none -*/ -void irq_latency_set(uint8_t irq_latency) -{ - uint32_t reg; - - reg = SYSCFG_CPU_IRQ_LAT &(~(uint32_t)SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY); - reg |= (uint32_t)(IRQ_LATENCY(irq_latency)); - - SYSCFG_CPU_IRQ_LAT = (uint32_t)reg; -} -/*! - \brief check if the specified flag in SYSCFG_CFG2 is set or not. - \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check. - \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. - \param[out] none - \retval the syscfg_flag state returned (SET or RESET). - */ -FlagStatus syscfg_flag_get(uint32_t syscfg_flag) -{ - if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the flag in SYSCFG_CFG2 by writing 1. - \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear. - \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. - \param[out] none - \retval none -*/ -void syscfg_flag_clear(uint32_t syscfg_flag) -{ - SYSCFG_CFG2 |= (uint32_t) syscfg_flag; -} - diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_timer.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_timer.c deleted file mode 100644 index 3fce2c47f8..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_timer.c +++ /dev/null @@ -1,2059 +0,0 @@ -/*! - \file gd32e230_timer.c - \brief TIMER driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_timer.h" - -/* TIMER init parameter mask */ -#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ -#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ -#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ - -/*! - \brief deinit a TIMER - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph){ - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; - case TIMER14: - /* reset TIMER14 */ - rcu_periph_reset_enable(RCU_TIMER14RST); - rcu_periph_reset_disable(RCU_TIMER14RST); - break; - case TIMER15: - /* reset TIMER15 */ - rcu_periph_reset_enable(RCU_TIMER15RST); - rcu_periph_reset_disable(RCU_TIMER15RST); - break; - case TIMER16: - /* reset TIMER16 */ - rcu_periph_reset_enable(RCU_TIMER16RST); - rcu_periph_reset_disable(RCU_TIMER16RST); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct* initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock, 0~65535 - alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN - period: counter auto reload value, 0~65535 - clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value, 0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER2 == timer_periph)){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR|TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER0 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph) - || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; - } - - if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a TIMER - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a TIMER - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] prescaler: prescaler value,0~65535 - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,15,16) - \param[in] repetition: the counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] autoreload: the counter auto-reload value,0~65535 - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] counter: the counter value,0~65535 - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0,2,5,14..16) - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint32_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER OCPRE clear source selection - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] ocpreclear: - only one parameter can be selected which is shown as below: - \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input - \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF - \param[out] none - \retval none -*/ -void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear) -{ - if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC; - }else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,13..16) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,14) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,14) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source disable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,13..16) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,14) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,14) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0,2,13..16) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0,2,13..16) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) &= (~(uint32_t)flag); -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to enable - one or more parameters can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16) - \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16) - \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14) - \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14) - \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to disable - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16) - \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16) - \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14) - \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14) - \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0,2,14..16) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: TIMERx(x=0,2,14..16) - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0,2,14) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0,2) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0,2,14) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0,2) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0,2) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0,2,14..16) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: please refer to the following parameters - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0,2,5,13..16) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0,2,13..16) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0,2,14) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0,2) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0,2) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0,2,14) - \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate))| - ((uint32_t)(breakpara->ideloffstate))| - ((uint32_t)(breakpara->deadtime))| - ((uint32_t)(breakpara->breakpolarity))| - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode))| - ((uint32_t)(breakpara->breakstate))) ; -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief configure TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl){ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,2)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)){ - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - - if(TIMER0 == timer_periph){ - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); - } - - if(TIMER14 == timer_periph){ - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - } - - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - - if(TIMER0 == timer_periph){ - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); - } - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - - if(TIMER0 == timer_periph){ - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); - } - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] pulse: channel output pulse value,0~65535 - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel2(TIMERx(x=0,2)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0)) - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph,uint16_t channel, timer_ic_parameter_struct* icpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P|TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P and CH3NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P|TIMER_CHCTL2_CH3NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel){ - /* read TIMER channel 0 capture compare register value */ - case TIMER_CH_0: - count_value = TIMER_CH0CV(timer_periph); - break; - /* read TIMER channel 1 capture compare register value */ - case TIMER_CH_1: - count_value = TIMER_CH1CV(timer_periph); - break; - /* read TIMER channel 2 capture compare register value */ - case TIMER_CH_2: - count_value = TIMER_CH2CV(timer_periph); - break; - /* read TIMER channel 3 capture compare register value */ - case TIMER_CH_3: - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ - icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ - icpolarity = TIMER_IC_POLARITY_RISING; - } - - /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ - icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel){ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_0,(uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph,TIMER_CH_1,(uint16_t)(icpwm->icprescaler)); - }else{ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2)) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0,2)) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0,2,5,14) - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0,2,5,14)) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0,2,5,14)) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0,2,5,14)) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0,2,14)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0,2,14)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0,2,14)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0,2,14)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0,2,14)) - \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0,2)) - \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0,2)) - \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0,2)) - \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0,2,14)) - \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0,2,14)) - \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0,2,14)) - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0,2,14)) - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, - uint16_t ic0polarity, uint16_t ic1polarity) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS))&((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI|((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity|((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2)) - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph, intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active high or rising edge active - \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active - \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, - uint16_t extpolarity, uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P|TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 8U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P|TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)extfilter; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph,extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief configure TIMER channel remap function - \param[in] timer_periph: TIMERx(x=13) - \param[in] remap: - only one parameter can be selected which is shown as below: - \arg TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0) - \arg TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK - \arg TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock - \arg TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL - \param[out] none - \retval none -*/ -void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) -{ - TIMER_IRMP(timer_periph) = (uint32_t)remap; -} - -/*! - \brief configure TIMER write CHxVAL register selection - \param[in] timer_periph: TIMERx(x=0,2,13..16) - \param[in] ccsel: - only one parameter can be selected which is shown as below: - \arg TIMER_CHVSEL_DISABLE: no effect - \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored - \param[out] none - \retval none -*/ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) -{ - if(TIMER_CHVSEL_ENABLE == ccsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - }else if(TIMER_CHVSEL_DISABLE == ccsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER output value selection - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] outsel: - only one parameter can be selected which is shown as below: - \arg TIMER_OUTSEL_DISABLE: no effect - \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled - \param[out] none - \retval none -*/ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) -{ - if(TIMER_OUTSEL_ENABLE == outsel){ - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - }else if(TIMER_OUTSEL_DISABLE == outsel){ - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - }else{ - /* illegal parameters */ - } -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_usart.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_usart.c deleted file mode 100644 index f73723e4be..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_usart.c +++ /dev/null @@ -1,1318 +0,0 @@ -/*! - \file gd32e230_usart.c - \brief USART driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_usart.h" - -/*! - \brief reset USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph){ - case USART0: - /* reset USART0 */ - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - /* reset USART1 */ - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; - switch(usart_periph){ - /* get clock frequency */ - case USART0: - /* get USART0 clock */ - uclk = rcu_clock_freq_get(CK_USART); - break; - case USART1: - /* get USART1 clock */ - uclk = rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD){ - /* oversampling by 8, configure the value of USART_BAUD */ - udiv = ((2U*uclk)+baudval/2U)/baudval; - intdiv = udiv & 0x0000fff0U; - fradiv = (udiv>>1U) & 0x00000007U; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - }else{ - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; - intdiv = udiv & 0x0000fff0U; - fradiv = udiv & 0x0000000fU; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1) - \param[in] paritycfg: USART parity configure - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5bit - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5bit - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - USART_CTL1(usart_periph) |= stblen; -} - -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - USART_CTL0(usart_periph) &= ~USART_CTL0_TEN; - /* configure transfer mode */ - USART_CTL0(usart_periph) |= txconfig; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - USART_CTL0(usart_periph) &= ~USART_CTL0_REN; - /* configure receiver mode */ - USART_CTL0(usart_periph) |= rxconfig; -} - -/*! - \brief data is transmitted/received with the LSB/MSB first - \param[in] usart_periph: USARTx(x=0,1) - \param[in] msbf: LSB/MSB - only one parameter can be selected which is shown as below: - \arg USART_MSBF_LSB: LSB first - \arg USART_MSBF_MSB: MSB first - \param[out] none - \retval none -*/ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* configure LSB or MSB first */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); - USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); -} - -/*! - \brief USART inverted configure - \param[in] usart_periph: USARTx(x=0,1) - \param[in] invertpara: refer to usart_invert_enum - only one parameter can be selected which is shown as below: - \arg USART_DINV_ENABLE: data bit level inversion - \arg USART_DINV_DISABLE: data bit level not inversion - \arg USART_TXPIN_ENABLE: TX pin level inversion - \arg USART_TXPIN_DISABLE: TX pin level not inversion - \arg USART_RXPIN_ENABLE: RX pin level inversion - \arg USART_RXPIN_DISABLE: RX pin level not inversion - \arg USART_SWAP_ENABLE: swap TX/RX pins - \arg USART_SWAP_DISABLE: not swap TX/RX pins - \param[out] none - \retval none -*/ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* inverted or not the specified signal */ - switch(invertpara){ - case USART_DINV_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_DINV; - break; - case USART_DINV_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); - break; - case USART_TXPIN_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_TINV; - break; - case USART_TXPIN_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); - break; - case USART_RXPIN_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_RINV; - break; - case USART_RXPIN_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); - break; - case USART_SWAP_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_STRP; - break; - case USART_SWAP_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP); - break; - default: - break; - } -} - -/*! - \brief enable the USART overrun function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_overrun_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* enable overrun function */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD); -} - -/*! - \brief disable the USART overrun function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_overrun_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* disable overrun function */ - USART_CTL2(usart_periph) |= USART_CTL2_OVRD; -} - -/*! - \brief configure the USART oversample mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] oversamp: oversample value - only one parameter can be selected which is shown as below: - \arg USART_OVSMOD_8: oversampling by 8 - \arg USART_OVSMOD_16: oversampling by 16 - \param[out] none - \retval none -*/ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear OVSMOD bit */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); - USART_CTL0(usart_periph) |= oversamp; -} - -/*! - \brief configure the sample bit method - \param[in] usart_periph: USARTx(x=0,1) - \param[in] osb: sample bit - only one parameter can be selected which is shown as below: - \arg USART_OSB_1BIT: 1 bit - \arg USART_OSB_3BIT: 3 bits - \param[out] none - \retval none -*/ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); - USART_CTL2(usart_periph) |= osb; -} - -/*! - \brief enable receiver timeout - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_RTEN; -} - -/*! - \brief disable receiver timeout - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN); -} - -/*! - \brief configure receiver timeout threshold - \param[in] usart_periph: USARTx(x=0) - \param[in] rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks - \param[out] none - \retval none -*/ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) -{ - USART_RT(usart_periph) &= ~(USART_RT_RT); - USART_RT(usart_periph) |= rtimeout; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data); -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); -} - -/*! - \brief enable auto baud rate detection - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_autobaud_detection_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_ABDEN; -} - -/*! - \brief disable auto baud rate detection - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_autobaud_detection_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDEN); -} - -/*! - \brief configure auto baud rate detection mode - \param[in] usart_periph: USARTx(x=0) - \param[in] abdmod: auto baud rate detection mode - only one parameter can be selected which is shown as below: - \arg USART_ABDM_FTOR: falling edge to rising edge measurement - \arg USART_ABDM_FTOF: falling edge to falling edge measurement - \param[out] none - \retval none -*/ -void usart_autobaud_detection_mode_config(uint32_t usart_periph, uint32_t abdmod) -{ - /* reset ABDM bits */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ABDM); - USART_CTL1(usart_periph) |= abdmod; -} - -/*! - \brief address of the USART terminal - \param[in] usart_periph: USARTx(x=0,1) - \param[in] addr: 0x00-0xFF, address of USART terminal - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24)); -} - -/*! - \brief configure address detection mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] addmod: address detection mode - only one parameter can be selected which is shown as below: - \arg USART_ADDM_4BIT: 4 bits - \arg USART_ADDM_FULLBIT: full bits - \param[out] none - \retval none -*/ -void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM); - USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod); -} - -/*! - \brief enable mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_MEN; -} - -/*! - \brief disable mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] wmethod: two methods be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mark - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief LIN break detection length - \param[in] usart_periph: USARTx(x=0) - \param[in] lblen: LIN break detection length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits break detection - \arg USART_LBLEN_11B: 11 bits break detection - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen); -} - -/*! - \brief enable half-duplex mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half-duplex mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable clock - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_clock_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable clock - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_clock_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1) - \param[in] clen: last bit clock pulse - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin - \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset USART_CTL1 CLEN,CPH,CPL bits */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - - USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen); - USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph); - USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl); -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[in] guat: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief enable early NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) |= USART_RFCS_ELNACK; -} - -/*! - \brief disable early NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK; -} - -/*! - \brief configure smartcard auto-retry number - \param[in] usart_periph: USARTx(x=0) - \param[in] scrtnum: 0x00000000-0x00000007, smartcard auto-retry number - \param[out] none - \retval none -*/ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM); - USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17)); -} - -/*! - \brief configure block length - \param[in] usart_periph: USARTx(x=0) - \param[in] bl: 0x00000000-0x000000FF - \param[out] none - \retval none -*/ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl) -{ - USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24)); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode - \param[in] usart_periph: USARTx(x=0) - \param[in] psc: 0x00000000-0x000000FF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0) - \param[in] irlp: IrDA low-power or normal - only one parameter can be selected which is shown as below: - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1) - \param[in] rtsconfig: enable or disable RTS - only one parameter can be selected which is shown as below: - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); - USART_CTL2(usart_periph) |= rtsconfig; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1) - \param[in] ctsconfig: enable or disable CTS - only one parameter can be selected which is shown as below: - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN; - USART_CTL2(usart_periph) |= ctsconfig; -} - - /*! - \brief configure hardware flow control coherence mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] hcm: - only one parameter can be selected which is shown as below: - \arg USART_HCM_NONE: nRTS signal equals to the rxne status register - \arg USART_HCM_EN: nRTS signal is set when the last data bit has been sampled - \param[out] none - \retval none -*/ -void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) -{ - USART_CHC(usart_periph) &= ~(USART_CHC_HCM); - USART_CHC(usart_periph) |= (USART_CHC_HCM & hcm); -} - -/*! - \brief enable RS485 driver - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_rs485_driver_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_DEM; -} - -/*! - \brief disable RS485 driver - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_rs485_driver_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM); -} - -/*! - \brief configure driver enable assertion time - \param[in] usart_periph: USARTx(x=0,1) - \param[in] deatime: 0x00000000-0x0000001F - \param[out] none - \retval none -*/ -void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA); - USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21)); -} - -/*! - \brief configure driver enable de-assertion time - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dedtime: 0x00000000-0x0000001F - \param[out] none - \retval none -*/ -void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_DED); - USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16)); -} - -/*! - \brief configure driver enable polarity mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dep: DE signal - only one parameter can be selected which is shown as below: - \arg USART_DEP_HIGH: DE signal is active high - \arg USART_DEP_LOW: DE signal is active low - \param[out] none - \retval none -*/ -void usart_depolarity_config(uint32_t usart_periph, uint32_t dep) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset DEP bit */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP); - USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep); -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dmacmd: enable or disable DMA for reception - only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - USART_CTL2(usart_periph) &= ~USART_CTL2_DENR; - /* configure DMA reception */ - USART_CTL2(usart_periph) |= dmacmd; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dmacmd: enable or disable DMA for transmission - only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - USART_CTL2(usart_periph) &= ~USART_CTL2_DENT; - /* configure DMA transmission */ - USART_CTL2(usart_periph) |= dmacmd; -} - -/*! - \brief disable DMA on reception error - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_reception_error_dma_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_DDRE; -} - -/*! - \brief enable DMA on reception error - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_reception_error_dma_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE); -} - -/*! - \brief enable USART to wakeup the mcu from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_wakeup_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UESM; -} - -/*! - \brief disable USART to wakeup the mcu from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_wakeup_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM); -} - -/*! - \brief configure the USART wakeup mode from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[in] wum: wakeup mode - only one parameter can be selected which is shown as below: - \arg USART_WUM_ADDR: WUF active on address match - \arg USART_WUM_STARTB: WUF active on start bit - \arg USART_WUM_RBNE: WUF active on RBNE - \param[out] none - \retval none -*/ -void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset WUM bit */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM); - USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum); -} - -/*! - \brief enable receive FIFO - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_receive_fifo_enable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) |= USART_RFCS_RFEN; -} - -/*! - \brief disable receive FIFO - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_receive_fifo_disable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN); -} - -/*! - \brief read receive FIFO counter number - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval receive FIFO counter number -*/ -uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph) -{ - return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U)); -} - -/*! - \brief get flag in STAT/CHC/RFCS register - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: flag type - only one parameter can be selected which is shown as below: - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_IDLE: idle line detected flag - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_TC: transmission completed - \arg USART_FLAG_TBE: transmit data register empty - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_CTS: CTS level - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_ABDE: auto baudrate detection error - \arg USART_FLAG_ABD: auto baudrate detection flag - \arg USART_FLAG_BSY: busy flag - \arg USART_FLAG_AM: address match flag - \arg USART_FLAG_SB: send break flag - \arg USART_FLAG_RWU: receiver wakeup from mute mode. - \arg USART_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_FLAG_TEA: transmit enable acknowledge flag - \arg USART_FLAG_REA: receive enable acknowledge flag - \arg USART_FLAG_EPERR: early parity error flag - \arg USART_FLAG_RFE: receive FIFO empty flag - \arg USART_FLAG_RFF: receive FIFO full flag - \arg USART_FLAG_RFFINT: receive FIFO full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART status - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: flag type - only one parameter can be selected which is shown as below: - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_NERR: noise detected flag - \arg USART_FLAG_ORERR: overrun error flag - \arg USART_FLAG_IDLE: idle line detected flag - \arg USART_FLAG_TC: transmission complete flag - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_AM: address match flag - \arg USART_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_FLAG_EPERR: early parity error flag - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1) - \param[in] inttype: interrupt type - only one parameter can be selected which is shown as below: - \arg USART_INT_IDLE: idle interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and - overrun error interrupt enable interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_TBE: transmit data register empty interrupt - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_AM: address match interrupt - \arg USART_INT_RT: receiver timeout interrupt - \arg USART_INT_EB: end of block interrupt - \arg USART_INT_LBD: LIN break detection interrupt - \arg USART_INT_ERR: error interrupt enable in multibuffer communication - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_WU: wakeup from deep-sleep mode interrupt - \arg USART_INT_RFF: receive FIFO full interrupt enable - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum inttype) -{ - USART_REG_VAL(usart_periph, inttype) |= BIT(USART_BIT_POS(inttype)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1) - \param[in] inttype: interrupt type - only one parameter can be selected which is shown as below: - \arg USART_INT_IDLE: idle interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and - overrun error interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_TBE: transmit data register empty interrupt - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_AM: address match interrupt - \arg USART_INT_RT: receiver timeout interrupt - \arg USART_INT_EB: end of block interrupt - \arg USART_INT_LBD: LIN break detection interrupt - \arg USART_INT_ERR: error interrupt enable in multibuffer communication - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_WU: wakeup from deep-sleep mode interrupt - \arg USART_INT_RFF: receive FIFO full interrupt enable - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum inttype) -{ - USART_REG_VAL(usart_periph, inttype) &= ~BIT(USART_BIT_POS(inttype)); -} - -/*! - \brief enable USART command - \param[in] usart_periph: USARTx(x=0,1) - \param[in] cmdtype: command type - only one parameter can be selected which is shown as below: - \arg USART_CMD_ABDCMD: auto baudrate detection command - \arg USART_CMD_SBKCMD: send break command - \arg USART_CMD_MMCMD: mute mode command - \arg USART_CMD_RXFCMD: receive data flush command - \arg USART_CMD_TXFCMD: transmit data flush request - \param[out] none - \retval none -*/ -void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype) -{ - USART_CMD(usart_periph) |= (cmdtype); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1) - \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_EB: end of block interrupt and flag - \arg USART_INT_FLAG_RT: receiver timeout interrupt and flag - \arg USART_INT_FLAG_AM: address match interrupt and flag - \arg USART_INT_FLAG_PERR: parity error interrupt and flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag - \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if(flagstatus && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART interrupt flag - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: USART interrupt flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_PERR: parity error flag - \arg USART_INT_FLAG_ERR_FERR: frame error flag - \arg USART_INT_FLAG_ERR_NERR: noise detected flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_IDLE: idle line detected flag - \arg USART_INT_FLAG_TC: transmission complete flag - \arg USART_INT_FLAG_LBD: LIN break detected flag - \arg USART_INT_FLAG_CTS: CTS change flag - \arg USART_INT_FLAG_RT: receiver timeout flag - \arg USART_INT_FLAG_EB: end of block flag - \arg USART_INT_FLAG_AM: address match flag - \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag) -{ - if(USART_INT_FLAG_RFF == flag){ - USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT); - }else{ - USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag)); - } -} diff --git a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_wwdgt.c b/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_wwdgt.c deleted file mode 100644 index 4d1ad0200c..0000000000 --- a/bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Source/gd32e230_wwdgt.c +++ /dev/null @@ -1,148 +0,0 @@ -/*! - \file gd32e230_wwdgt.c - \brief WWDGT driver - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e230_wwdgt.h" -#include "gd32e230_rcu.h" - -/* WWDGT_CTL register value */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */ -/* WWDGT_CFG register value */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */ - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00000000 - 0x0000007F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - uint32_t reg = 0x00000000U; - - reg = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT); - reg |= (uint32_t)(CTL_CNT(counter_value)); - - WWDGT_CTL = (uint32_t)reg; -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00000000 - 0x0000007F - \param[in] window: 0x00000000 - 0x0000007F - \param[in] prescaler: wwdgt prescaler value - only one parameter can be selected which is shown as below: - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - uint32_t reg_cfg = 0x00000000U, reg_ctl = 0x00000000U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = WWDGT_CFG &(~((uint32_t)WWDGT_CFG_WIN|(uint32_t)WWDGT_CFG_PSC)); - reg_ctl = WWDGT_CTL &(~(uint32_t)WWDGT_CTL_CNT); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= (uint32_t)(CFG_WIN(window)); - reg_cfg |= (uint32_t)(prescaler); - reg_ctl |= (uint32_t)(CTL_CNT(counter)); - - WWDGT_CFG = (uint32_t)reg_cfg; - WWDGT_CTL = (uint32_t)reg_ctl; -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)){ - return SET; - } - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (uint32_t)(~(uint32_t)WWDGT_STAT_EWIF); -} diff --git a/bsp/gd32e230k-start/Libraries/SConscript b/bsp/gd32e230k-start/Libraries/SConscript deleted file mode 100644 index c531f34b31..0000000000 --- a/bsp/gd32e230k-start/Libraries/SConscript +++ /dev/null @@ -1,27 +0,0 @@ -import rtconfig -from building import * - -# get current directory -cwd = GetCurrentDir() - -# The set of source files associated with this SConscript file. - -src = Glob('GD32E230_standard_peripheral/Source/*.c') -src += [cwd + '/CMSIS/GD/GD32E230/Source/system_gd32e230.c'] - -#add for startup script -if rtconfig.PLATFORM in ['armcc', 'armclang']: - src += [cwd + '/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s'] -elif rtconfig.PLATFORM in ['iccarm']: - src += [cwd + '/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s'] - -path = [ - cwd + '/CMSIS/GD/GD32E230/Include', - cwd + '/CMSIS', - cwd + '/GD32E230_standard_peripheral/Include',] - -CPPDEFINES = ['GD32E230'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/gd32e230k-start/README.md b/bsp/gd32e230k-start/README.md deleted file mode 100644 index 1b676bc0b4..0000000000 --- a/bsp/gd32e230k-start/README.md +++ /dev/null @@ -1,51 +0,0 @@ -# GD32E230K-START # - -## 1. 简介 - -[GD32E230K-START](http://gd32mcu.21ic.com/site)是兆易科技æ供的开å‘æ¿ï¼Œä½¿ç”¨ Cortex-M23 内核的 GD32E230K8T6 作为主控制器。æ供包括扩展引脚åŠæ¿è½½ GD-Link 仿真器等外设资æºã€‚除 GD32E230K-START（32引脚）外，GD32E230 系列 START å¼€å‘æ¿è¿˜æœ‰ GD32E230C-START（48引脚）ã€GD32E230G-START（28引脚）ã€GD32E230F-START（20引脚），四ç§å¼€å‘æ¿ç¨‹åºå¯ä»¥é€šç”¨ï¼Œå¯èƒ½éœ€è¦æ”¹å˜éƒ¨åˆ†å¼•è„šå®šä¹‰ã€‚ - -æ¿è½½ä¸»è¦èµ„æºå¦‚下： - -| 硬件 | æè¿° | -| -- | -- | -|CPU| Cortex-M23| -|主频| 72MHz | -|SRAM| 8KB | -|Flash| 64KB | - -## 2. 编译说明 - -GD32E230K-STARTæ¿çº§åŒ…æ”¯æŒ MDK5，以下是具体版本信æ¯ï¼š -注：Cortex-M23 内核åªæ”¯æŒ ARM Compiler 6 (Armclang)，并ä¸æ”¯æŒ ARM Compiler 5 (armcc)。 - -| IDE/编译器 | 已测试版本 | -| -- | -- | -| MDK5(ARM Compiler 6) | MDK5.27 | - -## 3. 烧写åŠæ‰§è¡Œ - -下载程åºï¼šä½¿ç”¨æ¿è½½ GD-Link 工具。 - -### 3.1 é…置和仿真 - -工程已ç»é»˜è®¤ä½¿èƒ½äº†RT-Thread UART驱动ã€GPIO驱动ã€SPI驱动ã€I2C驱动。若想进一步é…置工程请 -使用ENV工具。 - -## 4. 驱动支æŒæƒ…况åŠè®¡åˆ’ - -| 驱动 | 支æŒæƒ…况 | 备注 | -| ------ | ---- | :------: | -| UART | æ”¯æŒ | USART0/1 | -| GPIO | æ”¯æŒ | | -| SPI | æ”¯æŒ | SPI0/1 | -| I2C | æ”¯æŒ | I2C0/1 | - -## 5. è”ç³»äººä¿¡æ¯ - -维护人： - -- [xuzhuoyi](https://github.com/xuzhuoyi) - -## 6. å‚考 - -* [GD32E230K-START](http://gd32mcu.21ic.com/site) diff --git a/bsp/gd32e230k-start/SConscript b/bsp/gd32e230k-start/SConscript deleted file mode 100644 index 20f7689c53..0000000000 --- a/bsp/gd32e230k-start/SConscript +++ /dev/null @@ -1,15 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') -from building import * - -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32e230k-start/SConstruct b/bsp/gd32e230k-start/SConstruct deleted file mode 100644 index 7b40e97402..0000000000 --- a/bsp/gd32e230k-start/SConstruct +++ /dev/null @@ -1,40 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread-gd32f230.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32e230k-start/applications/SConscript b/bsp/gd32e230k-start/applications/SConscript deleted file mode 100644 index 41dbee935c..0000000000 --- a/bsp/gd32e230k-start/applications/SConscript +++ /dev/null @@ -1,9 +0,0 @@ -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32e230k-start/applications/main.c b/bsp/gd32e230k-start/applications/main.c deleted file mode 100644 index 999becd329..0000000000 --- a/bsp/gd32e230k-start/applications/main.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2015-07-29 Arda.Fu first implementation - */ -#include -#include - -int main(void) -{ - /* user app entry */ - - return 0; -} diff --git a/bsp/gd32e230k-start/drivers/SConscript b/bsp/gd32e230k-start/drivers/SConscript deleted file mode 100644 index c19cc7a9c1..0000000000 --- a/bsp/gd32e230k-start/drivers/SConscript +++ /dev/null @@ -1,27 +0,0 @@ -from building import * - -cwd = GetCurrentDir() - -# add the general drivers. -src = Split(""" -board.c -drv_usart.c -""") - -CPPPATH = [cwd] - -# add spi drivers. -if GetDepend('RT_USING_SPI'): - src += ['drv_spi.c'] - -# add i2c drivers. -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -# add pin drivers. -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32e230k-start/drivers/board.c b/bsp/gd32e230k-start/drivers/board.c deleted file mode 100644 index 239d842054..0000000000 --- a/bsp/gd32e230k-start/drivers/board.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard first implementation - */ -#include -#include -#include -#include - -/** - * @brief This function is executed in case of error occurrence. - * @param None - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler */ - /* User can add his own implementation to report the HAL error return state */ - while (1) - { - } - /* USER CODE END Error_Handler */ -} - -/** System Clock Configuration -*/ -void SystemClock_Config(void) -{ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - NVIC_SetPriority(SysTick_IRQn, 0); -} - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** - * This function will initial GD32 board. - */ -void rt_hw_board_init() -{ - /* NVIC Configuration */ -#define NVIC_VTOR_MASK 0x3FFFFF80 -#ifdef VECT_TAB_RAM - /* Set the Vector Table base location at 0x10000000 */ - SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); -#else /* VECT_TAB_FLASH */ - /* Set the Vector Table base location at 0x08000000 */ - SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK); -#endif - - SystemClock_Config(); - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/gd32e230k-start/drivers/board.h b/bsp/gd32e230k-start/drivers/board.h deleted file mode 100644 index c76f570768..0000000000 --- a/bsp/gd32e230k-start/drivers/board.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - */ - -// <<< Use Configuration Wizard in Context Menu >>> -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include - -// Internal SRAM memory size[Kbytes] <8-64> -// Default: 64 -#ifdef __ICCARM__ -// Use *.icf ram symbal, to avoid hardcode. -extern char __ICFEDIT_region_RAM_end__; -#define GD32_SRAM_END &__ICFEDIT_region_RAM_end__ -#else -#define GD32_SRAM_SIZE 8 -#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024) -#endif - -#if defined(__ARMCC_VERSION) -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) -#endif - -#define HEAP_END GD32_SRAM_END - -#endif - -//*** <<< end of configuration section >>> *** diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.c b/bsp/gd32e230k-start/drivers/drv_gpio.c deleted file mode 100644 index d75a09f140..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_gpio.c +++ /dev/null @@ -1,472 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-10-20 ZYH the first version - * 2018-04-23 misonyo port to gd32f30x - * 2019-03-31 xuzhuoyi Porting for gd32e230 - */ - -#include "drv_gpio.h" -#include -#include -#include "gd32e230.h" -#include "gd32e230_exti.h" - -#ifdef RT_USING_PIN - -#define __GD32_PIN(index, port, pin) {index, RCU_GPIO##port, GPIO##port, \ - GPIO_PIN_##pin, EXTI_SOURCE_GPIO##port, EXTI_SOURCE_PIN##pin} -#define __GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0} - -/* GD32 GPIO driver */ -struct pin_index -{ - rt_int16_t index; - rcu_periph_enum clk; - rt_uint32_t gpio_periph; - rt_uint32_t pin; - rt_uint32_t port_src; - rt_uint32_t pin_src; -}; - -static const struct pin_index pins[] = -{ - __GD32_PIN_DEFAULT, - __GD32_PIN(2, F, 0), - __GD32_PIN(3, F, 1), - __GD32_PIN_DEFAULT, - __GD32_PIN_DEFAULT, - __GD32_PIN(6, A, 0), - __GD32_PIN(7, A, 1), - __GD32_PIN(8, A, 2), - __GD32_PIN(9, A, 3), - __GD32_PIN(10, A, 4), - __GD32_PIN(11, A, 5), - __GD32_PIN(12, A, 6), - __GD32_PIN(13, A, 7), - __GD32_PIN(14, B, 0), - __GD32_PIN(15, B, 1), - __GD32_PIN(16, B, 2), - __GD32_PIN_DEFAULT, - __GD32_PIN(18, A, 8), - __GD32_PIN(19, A, 9), - __GD32_PIN(20, A, 10), - __GD32_PIN(21, A, 11), - __GD32_PIN(22, A, 12), - __GD32_PIN(23, A, 13), - __GD32_PIN(24, A, 14), - __GD32_PIN(25, A, 15), - __GD32_PIN(26, B, 3), - __GD32_PIN(27, B, 4), - __GD32_PIN(28, B, 5), - __GD32_PIN(29, B, 6), - __GD32_PIN(30, B, 7), - __GD32_PIN_DEFAULT, - __GD32_PIN(32, B, 8), -}; - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_1_IRQn}, - {GPIO_PIN_1, EXTI0_1_IRQn}, - {GPIO_PIN_2, EXTI2_3_IRQn}, - {GPIO_PIN_3, EXTI2_3_IRQn}, - {GPIO_PIN_4, EXTI4_15_IRQn}, - {GPIO_PIN_5, EXTI4_15_IRQn}, - {GPIO_PIN_6, EXTI4_15_IRQn}, - {GPIO_PIN_7, EXTI4_15_IRQn}, - {GPIO_PIN_8, EXTI4_15_IRQn}, - {GPIO_PIN_9, EXTI4_15_IRQn}, - {GPIO_PIN_10, EXTI4_15_IRQn}, - {GPIO_PIN_11, EXTI4_15_IRQn}, - {GPIO_PIN_12, EXTI4_15_IRQn}, - {GPIO_PIN_13, EXTI4_15_IRQn}, - {GPIO_PIN_14, EXTI4_15_IRQn}, - {GPIO_PIN_15, EXTI4_15_IRQn}, -}; -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(rt_uint8_t pin) -{ - const struct pin_index *index; - - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - - return index; -}; - -void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) -{ - const struct pin_index *index; - rt_uint32_t pin_mode; - rt_uint32_t otype; - rt_uint32_t pull_up_down; - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* GPIO Periph clock enable */ - rcu_periph_clock_enable(index->clk); - pin_mode = GPIO_MODE_OUTPUT; - otype = GPIO_OTYPE_PP; - pull_up_down = GPIO_PUPD_NONE; - - switch(mode) - { - case PIN_MODE_OUTPUT: - /* output setting */ - break; - case PIN_MODE_OUTPUT_OD: - /* output setting: od. */ - otype = GPIO_OTYPE_OD; - break; - case PIN_MODE_INPUT: - /* input setting: not pull. */ - pin_mode = GPIO_MODE_INPUT; - break; - case PIN_MODE_INPUT_PULLUP: - /* input setting: pull up. */ - pin_mode = GPIO_MODE_INPUT; - pull_up_down = GPIO_PUPD_PULLUP; - break; - case PIN_MODE_INPUT_PULLDOWN: - /* input setting: pull down. */ - pin_mode = GPIO_MODE_INPUT; - pull_up_down = GPIO_PUPD_PULLDOWN; - break; - default: - break; - } - - gpio_mode_set(index->gpio_periph, pin_mode, pull_up_down, index->pin); - gpio_output_options_set(index->gpio_periph, otype, GPIO_OSPEED_50MHZ, index->pin); - -} - -void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) -{ - const struct pin_index *index; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); -} - -rt_int8_t gd32_pin_read(rt_device_t dev, rt_base_t pin) -{ - rt_int8_t value; - const struct pin_index *index; - - value = PIN_LOW; - - index = get_pin(pin); - if (index == RT_NULL) - { - return value; - } - - value = gpio_input_bit_get(index->gpio_periph, index->pin); - - return value; -} - - -rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) -{ - rt_uint8_t i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { - return i; - } - } - return -1; -} -rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) -{ - rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; -rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == pin && - pin_irq_hdr_tab[hdr_index].hdr == hdr && - pin_irq_hdr_tab[hdr_index].mode == mode && - pin_irq_hdr_tab[hdr_index].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[hdr_index].pin != -1) - { - rt_hw_interrupt_enable(level); - return -RT_EFULL; - } - pin_irq_hdr_tab[hdr_index].pin = pin; - pin_irq_hdr_tab[hdr_index].hdr = hdr; - pin_irq_hdr_tab[hdr_index].mode = mode; - pin_irq_hdr_tab[hdr_index].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -rt_err_t gd32_pin_detach_irq(struct rt_device *device, rt_base_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t hdr_index = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[hdr_index].pin = -1; - pin_irq_hdr_tab[hdr_index].hdr = RT_NULL; - pin_irq_hdr_tab[hdr_index].mode = 0; - pin_irq_hdr_tab[hdr_index].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} -rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t hdr_index = -1; - exti_trig_type_enum trigger_mode; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_EINVAL; - } - if (enabled == PIN_IRQ_ENABLE) - { - hdr_index = bit2bitno(index->pin); - if (hdr_index < 0 || hdr_index >= ITEM_NUM(pin_irq_map)) - { - return -RT_EINVAL; - } - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[hdr_index].pin == -1) - { - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - irqmap = &pin_irq_map[hdr_index]; - - switch (pin_irq_hdr_tab[hdr_index].mode) - { - case PIN_IRQ_MODE_RISING: - trigger_mode = EXTI_TRIG_RISING; - break; - case PIN_IRQ_MODE_FALLING: - trigger_mode = EXTI_TRIG_FALLING; - break; - case PIN_IRQ_MODE_RISING_FALLING: - trigger_mode = EXTI_TRIG_BOTH; - break; - default: - rt_hw_interrupt_enable(level); - return -RT_EINVAL; - } - - //rcu_periph_clock_enable(RCU_AF); - - /* enable and set interrupt priority */ - nvic_irq_enable(irqmap->irqno, 5U); - - /* connect EXTI line to GPIO pin */ - syscfg_exti_line_config(index->port_src, index->pin_src); - - /* configure EXTI line */ - exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode); - exti_interrupt_flag_clear((exti_line_enum)(index->pin)); - - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return -RT_EINVAL; - } - nvic_irq_disable(irqmap->irqno); - } - else - { - return -RT_EINVAL; - } - - return RT_EOK; -} -const static struct rt_pin_ops _gd32_pin_ops = -{ - gd32_pin_mode, - gd32_pin_write, - gd32_pin_read, - gd32_pin_attach_irq, - gd32_pin_detach_irq, - gd32_pin_irq_enable, - RT_NULL, -}; - -int rt_hw_pin_init(void) -{ - int result; - - result = rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL); - - return result; -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -rt_inline void pin_irq_hdr(int irqno) -{ - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line) -{ - if(RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line))) - { - pin_irq_hdr(exti_line); - exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line)); - } -} -void EXTI0_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(0); - rt_interrupt_leave(); -} -void EXTI1_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(1); - rt_interrupt_leave(); -} -void EXTI2_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(2); - rt_interrupt_leave(); -} -void EXTI3_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(3); - rt_interrupt_leave(); -} -void EXTI4_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(4); - rt_interrupt_leave(); -} -void EXTI5_9_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(5); - GD32_GPIO_EXTI_IRQHandler(6); - GD32_GPIO_EXTI_IRQHandler(7); - GD32_GPIO_EXTI_IRQHandler(8); - GD32_GPIO_EXTI_IRQHandler(9); - rt_interrupt_leave(); -} -void EXTI10_15_IRQHandler(void) -{ - rt_interrupt_enter(); - GD32_GPIO_EXTI_IRQHandler(10); - GD32_GPIO_EXTI_IRQHandler(11); - GD32_GPIO_EXTI_IRQHandler(12); - GD32_GPIO_EXTI_IRQHandler(13); - GD32_GPIO_EXTI_IRQHandler(14); - GD32_GPIO_EXTI_IRQHandler(15); - rt_interrupt_leave(); -} - -#endif diff --git a/bsp/gd32e230k-start/drivers/drv_gpio.h b/bsp/gd32e230k-start/drivers/drv_gpio.h deleted file mode 100644 index ae9bda7dce..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2015-01-05 Bernard the first version - */ -#ifndef GPIO_H__ -#define GPIO_H__ - - -#endif diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.c b/bsp/gd32e230k-start/drivers/drv_i2c.c deleted file mode 100644 index 7242ad5649..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_i2c.c +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-05 tanek first implementation. - * 2018-04-19 misonyo Porting for gd32f30x - * 2019-03-31 xuzhuoyi Porting for gd32e230 - */ - -#include "drv_i2c.h" -#include -#include "gd32e230.h" - -#ifdef RT_USING_I2C - -#include - -#define DBG_TAG "drv.I2C" -#ifdef RT_I2C_DEBUG -#define DBG_LVL DBG_LOG -#else -#define DBG_LVL DBG_INFO -#endif -#include - -#ifdef RT_USING_I2C_BITOPS - -/*user can change this*/ -#define I2C_BUS_NAME "i2c2" - -/*user should change this to adapt specific board*/ -#define I2C_SCL_PIN GPIO_PIN_4 -#define I2C_SCL_PORT GPIOE -#define I2C_SCL_CLK RCU_GPIOE -#define I2C_SDA_PIN GPIO_PIN_5 -#define I2C_SDA_PORT GPIOE -#define I2C_SDA_CLK RCU_GPIOE - -struct gd32_i2c_bit_data -{ - struct - { - rcu_periph_enum clk; - rt_uint32_t port; - rt_uint32_t pin; - }scl, sda; -}; - -static void gpio_set_sda(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - - if (state) - { - gpio_bit_set(bd->sda.port, bd->sda.pin); - } - else - { - gpio_bit_reset(bd->sda.port, bd->sda.pin); - } -} - -static void gpio_set_scl(void *data, rt_int32_t state) -{ - struct gd32_i2c_bit_data* bd = data; - if (state) - { - gpio_bit_set(bd->scl.port, bd->scl.pin); - } - else - { - gpio_bit_reset(bd->scl.port, bd->scl.pin); - } -} - -static rt_int32_t gpio_get_sda(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->sda.port, bd->sda.pin); -} - -static rt_int32_t gpio_get_scl(void *data) -{ - struct gd32_i2c_bit_data* bd = data; - - return gpio_input_bit_get(bd->scl.port, bd->scl.pin); -} - -static void gpio_udelay(rt_uint32_t us) -{ - int i = ( rcu_clock_freq_get(CK_SYS) / 4000000 * us); - while(i) - { - i--; - } -} - -static void drv_i2c_gpio_init(const struct gd32_i2c_bit_data* bd) -{ - rcu_periph_clock_enable(bd->sda.clk); - rcu_periph_clock_enable(bd->scl.clk); - gpio_init(bd->sda.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->sda.pin); - gpio_init(bd->scl.port, GPIO_MODE_OUT_OD, GPIO_OSPEED_10MHZ, bd->scl.pin); - - gpio_bit_set(bd->sda.port, bd->sda.pin); - gpio_bit_set(bd->scl.port, bd->scl.pin); -} - -#else /* use hardware i2c */ - -struct gd32_i2c_bus -{ - struct rt_i2c_bus_device parent; - rt_uint32_t i2c_periph; -}; - -static int gd32_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_RECEIVER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - if(1 == data_byte){ - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - - /* while there is data to be read */ - while(data_byte) - { - /* wait until the RBNE bit is set and clear it */ - if(i2c_flag_get(i2c_periph, I2C_FLAG_RBNE)) - { - /* read a byte from the EEPROM */ - *p_buffer = i2c_data_receive(i2c_periph); - - /* point to the next location where the byte read will be saved */ - p_buffer++; - - /* decrement the read bytes counter */ - data_byte--; - if(1 == data_byte) - { - /* disable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_DISABLE); - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - } - } - } - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - /* enable acknowledge */ - i2c_ack_config(i2c_periph,I2C_ACK_ENABLE); - - i2c_ackpos_config(i2c_periph,I2C_ACKPOS_CURRENT); - - return 0; -} - -static int gd32_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte) -{ - /* wait until I2C bus is idle */ - while(i2c_flag_get(i2c_periph, I2C_FLAG_I2CBSY)); - - /* send a start condition to I2C bus */ - i2c_start_on_bus(i2c_periph); - - /* wait until SBSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_SBSEND)); - - /* send slave address to I2C bus */ - i2c_master_addressing(i2c_periph, slave_address<<1, I2C_TRANSMITTER); - - /* wait until ADDSEND bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_ADDSEND)); - - /* clear the ADDSEND bit */ - i2c_flag_clear(i2c_periph,I2C_FLAG_ADDSEND); - - /* wait until the transmit data buffer is empty */ - while(SET != i2c_flag_get( i2c_periph , I2C_FLAG_TBE)); - - /* while there is data to be read */ - while(data_byte) - { - i2c_data_transmit(i2c_periph, *p_buffer); - - /* point to the next byte to be written */ - p_buffer++; - - /* decrement the write bytes counter */ - data_byte --; - - /* wait until BTC bit is set */ - while(!i2c_flag_get(i2c_periph, I2C_FLAG_BTC)); - } - - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(i2c_periph); - - /* wait until the stop condition is finished */ - while(I2C_CTL0(i2c_periph)&0x0200); - - return 0; -} - -static rt_ssize_t gd32_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num) -{ - struct rt_i2c_msg *msg; - rt_uint32_t i; - rt_err_t ret = -RT_ERROR; - - struct gd32_i2c_bus *gd32_i2c = (struct gd32_i2c_bus *)bus; - - for (i = 0; i < num; i++) - { - msg = &msgs[i]; - - if (msg->flags & RT_I2C_ADDR_10BIT) - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_10BITS,0); - } - else - { - i2c_mode_addr_config(gd32_i2c->i2c_periph,I2C_I2CMODE_ENABLE,I2C_ADDFORMAT_7BITS,0); - } - if (msg->flags & RT_I2C_RD) - { - if (gd32_i2c_read(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - else - { - if (gd32_i2c_write(gd32_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0) - { - LOG_E("i2c bus write failed,i2c bus stop!"); - goto out; - } - } - } - - ret = i; - -out: - LOG_D("send stop condition"); - - return ret; -} - -static const struct rt_i2c_bus_device_ops i2c_ops = -{ - gd32_i2c_xfer, - RT_NULL, - RT_NULL -}; - -#endif /* RT_USING_I2C_BITOPS */ - -int rt_hw_i2c_init(void) -{ -#ifdef RT_USING_I2C_BITOPS - { - static struct rt_i2c_bus_device i2c_device; - static const struct gd32_i2c_bit_data _i2c_bdata = - { - /* SCL */ - { I2C_SCL_CLK, I2C_SCL_PORT, I2C_SCL_PIN}, - /* SDA */ - { I2C_SDA_CLK, I2C_SDA_PORT, I2C_SDA_PIN}, - }; - - static const struct rt_i2c_bit_ops _i2c_bit_ops = - { - (void*)&_i2c_bdata, - gpio_set_sda, - gpio_set_scl, - gpio_get_sda, - gpio_get_scl, - gpio_udelay, - 1, - 100 - }; - - drv_i2c_gpio_init(&_i2c_bdata); - - i2c_device.priv = (void *)&_i2c_bit_ops; - rt_i2c_bit_add_bus(&i2c_device, I2C_BUS_NAME); - } - -#else /* register hardware I2C */ - -#ifdef RT_USING_I2C0 -#define I2C0_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c0; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB6 to I2C0_SCL */ - gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_6); - /* connect PB7 to I2C0_SDA */ - gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_7); - /* configure GPIO pins of I2C0 */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_6); - gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_6); - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_7); - gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_7); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C0); - /* configure I2C clock */ - i2c_clock_config(I2C0,I2C0_SPEED,I2C_DTCY_2); - - i2c_enable(I2C0); - /* enable acknowledge */ - i2c_ack_config(I2C0,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c0, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c0.parent.ops = &i2c_ops; - gd32_i2c0.i2c_periph = I2C0; - rt_i2c_bus_device_register(&gd32_i2c0.parent, "i2c0"); -#endif - -#ifdef RT_USING_I2C1 -#define I2C1_SPEED 100000 - - static struct gd32_i2c_bus gd32_i2c1; - /* enable GPIOB clock */ - rcu_periph_clock_enable(RCU_GPIOB); - - /* connect PB10 to I2C1_SCL */ - gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_10); - /* connect PB11 to I2C1_SDA */ - gpio_af_set(GPIOB, GPIO_AF_1, GPIO_PIN_11); - /* configure GPIO pins of I2C1 */ - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_10); - gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_10); - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_PULLUP,GPIO_PIN_11); - gpio_output_options_set(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ,GPIO_PIN_11); - - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C1); - /* configure I2C clock */ - i2c_clock_config(I2C1,I2C1_SPEED,I2C_DTCY_2); - - i2c_enable(I2C1); - /* enable acknowledge */ - i2c_ack_config(I2C1,I2C_ACK_ENABLE); - - rt_memset((void *)&gd32_i2c1, 0, sizeof(struct gd32_i2c_bus)); - gd32_i2c1.parent.ops = &i2c_ops; - gd32_i2c1.i2c_periph = I2C1; - rt_i2c_bus_device_register(&gd32_i2c1.parent, "i2c1"); -#endif - -#endif /* RT_USING_I2C_BITOPS */ - - return 0; -} -INIT_DEVICE_EXPORT(rt_hw_i2c_init); - -#endif -/* end of i2c driver */ diff --git a/bsp/gd32e230k-start/drivers/drv_i2c.h b/bsp/gd32e230k-start/drivers/drv_i2c.h deleted file mode 100644 index c4b321594c..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_i2c.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-05 tanek first implementation. - */ - -#ifndef __DRV_I2C__ -#define __DRV_I2C__ - - -#endif diff --git a/bsp/gd32e230k-start/drivers/drv_spi.c b/bsp/gd32e230k-start/drivers/drv_spi.c deleted file mode 100644 index d57ff081c5..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_spi.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2017-06-05 tanek first implementation. - * 2018-04-19 misonyo Porting for gd32f30x - * 2019-03-31 xuzhuoyi Porting for gd32e230 - */ - -#include "drv_spi.h" -#include "gd32e230.h" -#include - -#if defined(RT_USING_SPI) && defined(RT_USING_PIN) -#include - -#if !defined(RT_USING_SPI0) && !defined(RT_USING_SPI1) -#error "Please define at least one SPIx" -#endif - -/* #define DEBUG */ -#ifdef DEBUG -#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__) -#else -#define DEBUG_PRINTF(...) -#endif - -/* private rt-thread spi ops function */ -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration); -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message); - -static struct rt_spi_ops gd32_spi_ops = -{ - configure, - xfer -}; - -static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration) -{ - spi_parameter_struct spi_init_struct; - - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - - RT_ASSERT(device != RT_NULL); - RT_ASSERT(configuration != RT_NULL); - - if(configuration->data_width <= 8) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT; - } - else if(configuration->data_width <= 16) - { - spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT; - } - else - { - return -RT_EIO; - } - - { - rcu_clock_freq_enum spi_src; - rt_uint32_t spi_apb_clock; - rt_uint32_t max_hz; - - max_hz = configuration->max_hz; - - DEBUG_PRINTF("sys freq: %d\n", rcu_clock_freq_get(CK_SYS)); - DEBUG_PRINTF("CK_APB2 freq: %d\n", rcu_clock_freq_get(CK_APB2)); - DEBUG_PRINTF("max freq: %d\n", max_hz); - - if (spi_periph == SPI1) - { - spi_src = CK_APB1; - } - else - { - spi_src = CK_APB2; - } - spi_apb_clock = rcu_clock_freq_get(spi_src); - - if(max_hz >= spi_apb_clock/2) - { - spi_init_struct.prescale = SPI_PSC_2; - } - else if (max_hz >= spi_apb_clock/4) - { - spi_init_struct.prescale = SPI_PSC_4; - } - else if (max_hz >= spi_apb_clock/8) - { - spi_init_struct.prescale = SPI_PSC_8; - } - else if (max_hz >= spi_apb_clock/16) - { - spi_init_struct.prescale = SPI_PSC_16; - } - else if (max_hz >= spi_apb_clock/32) - { - spi_init_struct.prescale = SPI_PSC_32; - } - else if (max_hz >= spi_apb_clock/64) - { - spi_init_struct.prescale = SPI_PSC_64; - } - else if (max_hz >= spi_apb_clock/128) - { - spi_init_struct.prescale = SPI_PSC_128; - } - else - { - /* min prescaler 256 */ - spi_init_struct.prescale = SPI_PSC_256; - } - } /* baudrate */ - - switch(configuration->mode & RT_SPI_MODE_3) - { - case RT_SPI_MODE_0: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - break; - case RT_SPI_MODE_1: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE; - break; - case RT_SPI_MODE_2: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE; - break; - case RT_SPI_MODE_3: - spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE; - break; - } - - /* MSB or LSB */ - if(configuration->mode & RT_SPI_MSB) - { - spi_init_struct.endian = SPI_ENDIAN_MSB; - } - else - { - spi_init_struct.endian = SPI_ENDIAN_LSB; - } - - spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_init_struct.device_mode = SPI_MASTER; - spi_init_struct.nss = SPI_NSS_SOFT; - - spi_init(spi_periph, &spi_init_struct); - - spi_crc_off(spi_periph); - - spi_enable(spi_periph); - - return RT_EOK; -}; - -static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message) -{ - rt_base_t gd32_cs_pin = (rt_base_t)device->parent.user_data; - rt_uint32_t spi_periph = (rt_uint32_t)device->bus->parent.user_data; - struct rt_spi_configuration * config = &device->config; - - RT_ASSERT(device != NULL); - RT_ASSERT(message != NULL); - - /* take CS */ - if(message->cs_take) - { - rt_pin_write(gd32_cs_pin, PIN_LOW); - DEBUG_PRINTF("spi take cs\n"); - } - - { - if(config->data_width <= 8) - { - const rt_uint8_t * send_ptr = message->send_buf; - rt_uint8_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - DEBUG_PRINTF("spi poll transfer start: %d\n", size); - - while(size--) - { - rt_uint8_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - // Todo: replace register read/write by gd32f3 lib - //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - // Send the byte - spi_i2s_data_transmit(spi_periph, data); - - //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - // Get the received data - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - DEBUG_PRINTF("spi poll transfer finsh\n"); - } - else if(config->data_width <= 16) - { - const rt_uint16_t * send_ptr = message->send_buf; - rt_uint16_t * recv_ptr = message->recv_buf; - rt_uint32_t size = message->length; - - while(size--) - { - rt_uint16_t data = 0xFF; - - if(send_ptr != RT_NULL) - { - data = *send_ptr++; - } - - //Wait until the transmit buffer is empty - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE)); - // Send the byte - spi_i2s_data_transmit(spi_periph, data); - - //Wait until a data is received - while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE)); - // Get the received data - data = spi_i2s_data_receive(spi_periph); - - if(recv_ptr != RT_NULL) - { - *recv_ptr++ = data; - } - } - } - } - - /* release CS */ - if(message->cs_release) - { - rt_pin_write(gd32_cs_pin, PIN_HIGH); - DEBUG_PRINTF("spi release cs\n"); - } - - return message->length; -}; - -int gd32_hw_spi_init(void) -{ - int result = 0; -#ifdef RT_USING_SPI0 - static struct rt_spi_bus spi_bus0; - spi_bus0.parent.user_data = (void *)SPI0; - - result = rt_spi_bus_register(&spi_bus0, "spi0", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_SPI0); - - /* SPI0 GPIO config: SCK/PA5, MISO/PA6, MOSI/PA7 */ - gpio_af_set(GPIOA, GPIO_AF_0, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); - gpio_mode_set(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); - gpio_output_options_set(GPIOA, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7); -#endif -#ifdef RT_USING_SPI1 - static struct rt_spi_bus spi_bus1; - spi_bus1.parent.user_data = (void *)SPI1; - - result = rt_spi_bus_register(&spi_bus1, "spi1", &gd32_spi_ops); - - rcu_periph_clock_enable(RCU_SPI1); - rcu_periph_clock_enable(RCU_GPIOB); - - /* SPI1 GPIO config: SCK/PB13, MISO/PB14, MOSI/PB15 */ - gpio_af_set(GPIOB, GPIO_AF_0, GPIO_PIN_13 | GPIO_PIN_14 |GPIO_PIN_15); - gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_13 | GPIO_PIN_14 |GPIO_PIN_15); - gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_13 | GPIO_PIN_14 |GPIO_PIN_15); -#endif - return result; -} -INIT_BOARD_EXPORT(gd32_hw_spi_init); -#endif diff --git a/bsp/gd32e230k-start/drivers/drv_spi.h b/bsp/gd32e230k-start/drivers/drv_spi.h deleted file mode 100644 index ba8e55916a..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_spi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-01-01 aozima first implementation. - */ - -#ifndef gd32F30X_SPI_H_INCLUDED -#define gd32F30X_SPI_H_INCLUDED - - -#endif // gd32F30X_SPI_H_INCLUDED diff --git a/bsp/gd32e230k-start/drivers/drv_usart.c b/bsp/gd32e230k-start/drivers/drv_usart.c deleted file mode 100644 index 204ffa1ca1..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_usart.c +++ /dev/null @@ -1,298 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - * 2018-04-19 misonyo Porting for gd32f30x - * 2019-03-31 xuzhuoyi Porting for gd32e230 - */ - -#include -#include -#include -#include "gd32e230.h" - -#ifdef RT_USING_SERIAL - -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -#if !defined(RT_USING_USART0) && !defined(RT_USING_USART1) -#error "Please define at least one UARTx" - -#endif - -#include - -/* GD32 uart driver */ -// Todo: compress uart info -struct gd32_uart -{ - uint32_t uart_periph; - IRQn_Type irqn; - rcu_periph_enum per_clk; - rcu_periph_enum tx_gpio_clk; - rcu_periph_enum rx_gpio_clk; - uint32_t tx_port; - uint32_t tx_af; - uint16_t tx_pin; - uint32_t rx_port; - uint32_t rx_af; - uint16_t rx_pin; - - struct rt_serial_device * serial; - char *device_name; -}; - -static void uart_isr(struct rt_serial_device *serial); - -#if defined(RT_USING_USART0) -struct rt_serial_device serial0; - -void USART0_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial0); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_USART0 */ - -#if defined(RT_USING_USART1) -struct rt_serial_device serial1; - -void USART1_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&serial1); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -#endif /* RT_USING_UART1 */ - -static const struct gd32_uart uarts[] = { - #ifdef RT_USING_USART0 - { - USART0, // uart peripheral index - USART0_IRQn, // uart iqrn - RCU_USART0, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_AF_1, GPIO_PIN_9, // tx port, tx pin - GPIOA, GPIO_AF_1, GPIO_PIN_10, // rx port, rx pin - &serial0, - "uart0", - }, - #endif - - #ifdef RT_USING_USART1 - { - USART1, // uart peripheral index - USART1_IRQn, // uart iqrn - RCU_USART1, RCU_GPIOA, RCU_GPIOA, // periph clock, tx gpio clock, rt gpio clock - GPIOA, GPIO_AF_1, GPIO_PIN_2, // tx port, tx pin - GPIOA, GPIO_AF_1, GPIO_PIN_3, // rx port, rx pin - &serial1, - "uart1", - }, - #endif -}; - - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example: -* - Peripheral's clock enable -* - Peripheral's GPIO Configuration -* - NVIC configuration for UART interrupt request enable -* @param uart: UART handle pointer -* @retval None -*/ -void gd32_uart_gpio_init(struct gd32_uart *uart) -{ - /* enable USART clock */ - rcu_periph_clock_enable(uart->tx_gpio_clk); - rcu_periph_clock_enable(uart->rx_gpio_clk); - rcu_periph_clock_enable(uart->per_clk); - - /* connect port to USARTx_Tx */ - gpio_af_set(uart->tx_port, uart->tx_af, uart->tx_pin); - gpio_mode_set(uart->tx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->tx_pin); - gpio_output_options_set(uart->tx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->tx_pin); - - /* connect port to USARTx_Rx */ - gpio_af_set(uart->rx_port, uart->rx_af, uart->rx_pin); - gpio_mode_set(uart->rx_port, GPIO_MODE_AF, GPIO_PUPD_NONE, uart->rx_pin); - gpio_output_options_set(uart->rx_port, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, uart->rx_pin); - - NVIC_SetPriority(uart->irqn, 0); - NVIC_EnableIRQ(uart->irqn); -} - -static rt_err_t gd32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = (struct gd32_uart *)serial->parent.user_data; - - gd32_uart_gpio_init(uart); - - usart_baudrate_set(uart->uart_periph, cfg->baud_rate); - - switch (cfg->data_bits) - { - case DATA_BITS_9: - usart_word_length_set(uart->uart_periph, USART_WL_9BIT); - break; - - default: - usart_word_length_set(uart->uart_periph, USART_WL_8BIT); - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - usart_stop_bit_set(uart->uart_periph, USART_STB_2BIT); - break; - default: - usart_stop_bit_set(uart->uart_periph, USART_STB_1BIT); - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - usart_parity_config(uart->uart_periph, USART_PM_ODD); - break; - case PARITY_EVEN: - usart_parity_config(uart->uart_periph, USART_PM_EVEN); - break; - default: - usart_parity_config(uart->uart_periph, USART_PM_NONE); - break; - } - - usart_receive_config(uart->uart_periph, USART_RECEIVE_ENABLE); - usart_transmit_config(uart->uart_periph, USART_TRANSMIT_ENABLE); - usart_enable(uart->uart_periph); - - return RT_EOK; -} - -static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irqn); - /* disable interrupt */ - usart_interrupt_disable(uart->uart_periph, USART_INT_RBNE); - - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irqn); - /* enable interrupt */ - usart_interrupt_enable(uart->uart_periph, USART_INT_RBNE); - break; - } - - return RT_EOK; -} - -static int gd32_putc(struct rt_serial_device *serial, char ch) -{ - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - usart_data_transmit(uart->uart_periph, ch); - while((usart_flag_get(uart->uart_periph, USART_FLAG_TC) == RESET)); - - return 1; -} - -static int gd32_getc(struct rt_serial_device *serial) -{ - int ch; - struct gd32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct gd32_uart *)serial->parent.user_data; - - ch = -1; - if (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET) - ch = usart_data_receive(uart->uart_periph); - return ch; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) -{ - struct gd32_uart *uart = (struct gd32_uart *) serial->parent.user_data; - - RT_ASSERT(uart != RT_NULL); - - /* UART in mode Receiver */ - if ((usart_interrupt_flag_get(uart->uart_periph, USART_INT_FLAG_RBNE) != RESET) && - (usart_flag_get(uart->uart_periph, USART_FLAG_RBNE) != RESET)) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - /* Clear RXNE interrupt flag */ - usart_flag_clear(uart->uart_periph, USART_FLAG_RBNE); - } -} - -static const struct rt_uart_ops gd32_uart_ops = -{ - gd32_configure, - gd32_control, - gd32_putc, - gd32_getc -}; - -int gd32_hw_usart_init(void) -{ - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - int i; - - for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++) - { - uarts[i].serial->ops = &gd32_uart_ops; - uarts[i].serial->config = config; - - /* register UART device */ - rt_hw_serial_register(uarts[i].serial, - uarts[i].device_name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - (void *)&uarts[i]); - } - - return 0; -} -INIT_BOARD_EXPORT(gd32_hw_usart_init); -#endif diff --git a/bsp/gd32e230k-start/drivers/drv_usart.h b/bsp/gd32e230k-start/drivers/drv_usart.h deleted file mode 100644 index 4059092706..0000000000 --- a/bsp/gd32e230k-start/drivers/drv_usart.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - */ - -#ifndef __USART_H__ -#define __USART_H__ - - -#endif diff --git a/bsp/gd32e230k-start/drivers/gd32e230_libopt.h b/bsp/gd32e230k-start/drivers/gd32e230_libopt.h deleted file mode 100644 index 767e929d8f..0000000000 --- a/bsp/gd32e230k-start/drivers/gd32e230_libopt.h +++ /dev/null @@ -1,60 +0,0 @@ -/*! - \file gd32e230_libopt.h - \brief library optional for gd32e230 - - \version 2018-06-19, V1.0.0, firmware for GD32E230 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E230_LIBOPT_H -#define GD32E230_LIBOPT_H - -#include "gd32e230_adc.h" -#include "gd32e230_crc.h" -#include "gd32e230_dbg.h" -#include "gd32e230_dma.h" -#include "gd32e230_exti.h" -#include "gd32e230_fmc.h" -#include "gd32e230_gpio.h" -#include "gd32e230_syscfg.h" -#include "gd32e230_i2c.h" -#include "gd32e230_fwdgt.h" -#include "gd32e230_pmu.h" -#include "gd32e230_rcu.h" -#include "gd32e230_rtc.h" -#include "gd32e230_spi.h" -#include "gd32e230_timer.h" -#include "gd32e230_usart.h" -#include "gd32e230_wwdgt.h" -#include "gd32e230_misc.h" -#include "gd32e230_cmp.h" - -#endif /* GD32E230_LIBOPT_H */ diff --git a/bsp/gd32e230k-start/gd32_rom.icf b/bsp/gd32e230k-start/gd32_rom.icf deleted file mode 100644 index 27790e4197..0000000000 --- a/bsp/gd32e230k-start/gd32_rom.icf +++ /dev/null @@ -1,40 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0807ffff; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_heap__ = 0x2000; -/**** End of ICF editor section. ###ICF###*/ - -export symbol __ICFEDIT_region_RAM_end__; - -define symbol __region_RAM1_start__ = 0x10000000; -define symbol __region_RAM1_end__ = 0x1000FFFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region RAM1_region = mem:[from __region_RAM1_start__ to __region_RAM1_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -keep { section .rti_fn* }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in RAM1_region { section .sram }; diff --git a/bsp/gd32e230k-start/gd32_rom.ld b/bsp/gd32e230k-start/gd32_rom.ld deleted file mode 100644 index a017d88f4d..0000000000 --- a/bsp/gd32e230k-start/gd32_rom.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * linker script for GD32F30x with GNU ld - * bernard.xiong 2009-10-14 - */ - -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ - DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 64KB sram */ -} -ENTRY(Reset_Handler) -_system_stack_size = 0x200; - -SECTIONS -{ - .text : - { - . = ALIGN(4); - _stext = .; - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - .stack : - { - . = . + _system_stack_size; - . = ALIGN(4); - _estack = .; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/gd32e230k-start/gd32_rom.sct b/bsp/gd32e230k-start/gd32_rom.sct deleted file mode 100644 index abc5462a3f..0000000000 --- a/bsp/gd32e230k-start/gd32_rom.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x08000000 0x000080000 { ; load region size_region - ER_IROM1 0x08000000 0x000080000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20000000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/bsp/gd32e230k-start/project.uvoptx b/bsp/gd32e230k-start/project.uvoptx deleted file mode 100644 index 090bdb9227..0000000000 --- a/bsp/gd32e230k-start/project.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32e230 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 19 - - - - - - - - - - - BIN\UL2V8M.DLL - - - - 0 - UL2V8M - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM)) - - - 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000 - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/gd32e230k-start/project.uvprojx b/bsp/gd32e230k-start/project.uvprojx deleted file mode 100644 index a468b3d84d..0000000000 --- a/bsp/gd32e230k-start/project.uvprojx +++ /dev/null @@ -1,1107 +0,0 @@ - - - 2.1 -
### uVision Project, (C) Keil Software
- - - rt-thread_gd32e230 - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 1 - - - GD32E230K8 - GigaDevice - GigaDevice.GD32E230_DFP.1.0.0 - http://gd32mcu.21ic.com/data/documents/yingyongruanjian - IRAM(0x20000000,0x0002000) IROM(0x08000000,0x0010000) CPUTYPE("Cortex-M23") CLOCK(12000000) ELITTLE - - - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM)) - 0 - $$Device:GD32E230K8$Device\Include\gd32e230.h - - - - - - - - - - $$Device:GD32E230K8$SVD\GD32E230.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-gd32e230 - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - - - - SARMV8M.DLL - -MPU - TCM.DLL - -pCM23 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2V8M.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M23" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x2000 - - - 1 - 0x8000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x10000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x2000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 7 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, GD32E230, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__ - - ..\..\components\drivers\include;Libraries\CMSIS;..\..\components\libc\posix\io\poll;..\..\components\libc\compilers\common\extension;Libraries\GD32E230_standard_peripheral\Include;..\..\components\libc\compilers\common\include;..\..\components\drivers\spi\sfud\inc;applications;..\..\include;..\..\components\drivers\spi;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\libc\posix\ipc;..\..\components\libc\posix\io\eventfd;..\..\components\drivers\include;drivers;..\..\libcpu\arm\common;..\..\components\libc\compilers\common\extension\fcntl\octal;Libraries\CMSIS\GD\GD32E230\Include;.;..\..\components\libc\posix\io\epoll;..\..\libcpu\arm\cortex-m23;..\..\components\finsh - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - - - - - - - - - Applications - - - main.c - 1 - applications\main.c - - - - - Compiler - - - syscall_mem.c - 1 - ..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\components\libc\compilers\common\cctype.c - - - - - cstdlib.c - 1 - ..\..\components\libc\compilers\common\cstdlib.c - - - - - cstring.c - 1 - ..\..\components\libc\compilers\common\cstring.c - - - - - ctime.c - 1 - ..\..\components\libc\compilers\common\ctime.c - - - - - cunistd.c - 1 - ..\..\components\libc\compilers\common\cunistd.c - - - - - cwchar.c - 1 - ..\..\components\libc\compilers\common\cwchar.c - - - - - CPU - - - div0.c - 1 - ..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\libcpu\arm\common\showmem.c - - - - - context_rvds.S - 2 - ..\..\libcpu\arm\cortex-m23\context_rvds.S - - - - - cpuport.c - 1 - ..\..\libcpu\arm\cortex-m23\cpuport.c - - - - - DeviceDrivers - - - device.c - 1 - ..\..\components\drivers\core\device.c - - - - - -std=c99 - - - - - - - - - - - - i2c_core.c - 1 - ..\..\components\drivers\i2c\i2c_core.c - - - - - -std=c99 - - - - - - - - - - - - i2c_dev.c - 1 - ..\..\components\drivers\i2c\i2c_dev.c - - - - - -std=c99 - - - - - - - - - - - - completion.c - 1 - ..\..\components\drivers\ipc\completion.c - - - - - -std=c99 - - - - - - - - - - - - dataqueue.c - 1 - ..\..\components\drivers\ipc\dataqueue.c - - - - - -std=c99 - - - - - - - - - - - - pipe.c - 1 - ..\..\components\drivers\ipc\pipe.c - - - - - -std=c99 - - - - - - - - - - - - ringblk_buf.c - 1 - ..\..\components\drivers\ipc\ringblk_buf.c - - - - - -std=c99 - - - - - - - - - - - - ringbuffer.c - 1 - ..\..\components\drivers\ipc\ringbuffer.c - - - - - -std=c99 - - - - - - - - - - - - waitqueue.c - 1 - ..\..\components\drivers\ipc\waitqueue.c - - - - - -std=c99 - - - - - - - - - - - - workqueue.c - 1 - ..\..\components\drivers\ipc\workqueue.c - - - - - -std=c99 - - - - - - - - - - - - pin.c - 1 - ..\..\components\drivers\misc\pin.c - - - - - -std=c99 - - - - - - - - - - - - serial.c - 1 - ..\..\components\drivers\serial\serial.c - - - - - -std=c99 - - - - - - - - - - - - sfud.c - 1 - ..\..\components\drivers\spi\sfud\src\sfud.c - - - - - -std=c99 - - - - - - - - - - - - spi_core.c - 1 - ..\..\components\drivers\spi\spi_core.c - - - - - -std=c99 - - - - - - - - - - - - spi_dev.c - 1 - ..\..\components\drivers\spi\spi_dev.c - - - - - -std=c99 - - - - - - - - - - - - spi_flash_sfud.c - 1 - ..\..\components\drivers\spi\spi_flash_sfud.c - - - - - -std=c99 - - - - - - - - - - - - Drivers - - - drv_i2c.c - 1 - drivers\drv_i2c.c - - - - - drv_gpio.c - 1 - drivers\drv_gpio.c - - - - - drv_usart.c - 1 - drivers\drv_usart.c - - - - - board.c - 1 - drivers\board.c - - - - - drv_spi.c - 1 - drivers\drv_spi.c - - - - - Finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - - - msh_parse.c - 1 - ..\..\components\finsh\msh_parse.c - - - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - Kernel - - - clock.c - 1 - ..\..\src\clock.c - - - - - components.c - 1 - ..\..\src\components.c - - - - - idle.c - 1 - ..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\src\mempool.c - - - - - object.c - 1 - ..\..\src\object.c - - - - - scheduler_up.c - 1 - ..\..\src\scheduler_up.c - - - - - thread.c - 1 - ..\..\src\thread.c - - - - - timer.c - 1 - ..\..\src\timer.c - - - - - Libraries - - - gd32e230_i2c.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_i2c.c - - - - - gd32e230_usart.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_usart.c - - - - - system_gd32e230.c - 1 - Libraries\CMSIS\GD\GD32E230\Source\system_gd32e230.c - - - - - gd32e230_dma.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_dma.c - - - - - startup_gd32e230.s - 2 - Libraries\CMSIS\GD\GD32E230\Source\ARM\startup_gd32e230.s - - - - - gd32e230_fwdgt.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_fwdgt.c - - - - - gd32e230_pmu.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_pmu.c - - - - - gd32e230_exti.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_exti.c - - - - - gd32e230_spi.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_spi.c - - - - - gd32e230_syscfg.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_syscfg.c - - - - - gd32e230_rcu.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_rcu.c - - - - - gd32e230_gpio.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_gpio.c - - - - - gd32e230_adc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_adc.c - - - - - gd32e230_crc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_crc.c - - - - - gd32e230_dbg.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_dbg.c - - - - - gd32e230_fmc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_fmc.c - - - - - gd32e230_wwdgt.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_wwdgt.c - - - - - gd32e230_rtc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_rtc.c - - - - - gd32e230_misc.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_misc.c - - - - - gd32e230_cmp.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_cmp.c - - - - - gd32e230_timer.c - 1 - Libraries\GD32E230_standard_peripheral\Source\gd32e230_timer.c - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32e230k-start/rtconfig.h b/bsp/gd32e230k-start/rtconfig.h deleted file mode 100644 index 7ed7272d29..0000000000 --- a/bsp/gd32e230k-start/rtconfig.h +++ /dev/null @@ -1,241 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 - -/* kservice optimization */ - -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50002 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_I2C -#define RT_USING_PIN -#define RT_USING_SPI -#define RT_USING_SFUD -#define RT_SFUD_USING_FLASH_INFO_TABLE -#define RT_SFUD_SPI_MAX_HZ 50000000 - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* sensors drivers */ - - -/* touch drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -#define SOC_GD32E230K -#define RT_USING_USART0 -#define RT_USING_USART1 -#define RT_USING_SPI0 -#define RT_USING_SPI1 -#define RT_USING_I2C0 - -#endif diff --git a/bsp/gd32e230k-start/rtconfig.py b/bsp/gd32e230k-start/rtconfig.py deleted file mode 100644 index 9aad0f59ae..0000000000 --- a/bsp/gd32e230k-start/rtconfig.py +++ /dev/null @@ -1,132 +0,0 @@ -import os - -# toolchains options -ARCH='arm' -CPU='cortex-m23' -CROSS_TOOL='keil' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armclang' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # tool-chains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m23 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2 -g' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armclang': - # toolchains - CC = 'armclang' - CXX = 'armclang' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu Cortex-M23 ' - CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-M23 ' - CFLAGS += ' -mcpu=cortex-M23 ' - CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' - CFLAGS += ' -gdwarf-3 -ffunction-sections ' - AFLAGS = DEVICE + ' --apcs=interwork ' - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' - LFLAGS += ' --list rt-thread-gd32.map ' - LFLAGS += r' --strict --scatter "gd32_rom.sct" ' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' - LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' - - EXEC_PATH += '/ARM/ARMCLANG/bin/' - - if BUILD == 'debug': - CFLAGS += ' -g -O1' # armclang recommend - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' -std=c99' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M23' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M23' - AFLAGS += ' --fpu None' - - LFLAGS = ' --config gd32_rom.icf' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH += '/arm/bin/' - POST_ACTION = '' - diff --git a/bsp/gd32e230k-start/template.uvoptx b/bsp/gd32e230k-start/template.uvoptx deleted file mode 100644 index 090bdb9227..0000000000 --- a/bsp/gd32e230k-start/template.uvoptx +++ /dev/null @@ -1,185 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rt-thread_gd32e230 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 19 - - - - - - - - - - - BIN\UL2V8M.DLL - - - - 0 - UL2V8M - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM)) - - - 0 - JL2CM3 - -U30000299 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0GD32F30x_HD -FS08000000 -FL080000 - - - - - 0 - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - - ::CMSIS - 0 - 0 - 0 - 1 - - - diff --git a/bsp/gd32e230k-start/template.uvprojx b/bsp/gd32e230k-start/template.uvprojx deleted file mode 100644 index 43c9f16629..0000000000 --- a/bsp/gd32e230k-start/template.uvprojx +++ /dev/null @@ -1,402 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rt-thread_gd32e230 - 0x4 - ARM-ADS - 5060750::V5.06 update 6 (build 750)::ARMCC - 1 - - - GD32E230K8 - GigaDevice - GigaDevice.GD32E230_DFP.1.0.0 - http://gd32mcu.21ic.com/data/documents/yingyongruanjian - IRAM(0x20000000,0x0002000) IROM(0x08000000,0x0010000) CPUTYPE("Cortex-M23") CLOCK(12000000) ELITTLE - - - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0GD32E230 -FS08000000 -FL010000 -FP0($$Device:GD32E230K8$Flash\GD32E230.FLM)) - 0 - $$Device:GD32E230K8$Device\Include\gd32e230.h - - - - - - - - - - $$Device:GD32E230K8$SVD\GD32E230.svd - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-gd32e230 - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 1 - 0 - fromelf --bin !L --output rtthread.bin - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - - - - SARMV8M.DLL - -MPU - TCM.DLL - -pCM23 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4096 - - 1 - BIN\UL2V8M.DLL - - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M23" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x2000 - - - 1 - 0x8000000 - 0x10000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x8000000 - 0x10000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x2000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 7 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 0 - - - - - applications;.;drivers;Libraries\CMSIS\GD\GD32F30x\Include;Libraries\CMSIS;Libraries\GD32F30x_standard_peripheral\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x08000000 - 0x20000000 - - - - - --keep *.o(RTMSymTab) --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - ::CMSIS - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32vf103v-eval/.config b/bsp/gd32vf103v-eval/.config deleted file mode 100644 index 4b2db121ba..0000000000 --- a/bsp/gd32vf103v-eval/.config +++ /dev/null @@ -1,1010 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_AMP is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=8 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_INIT is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_DM is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50002 -# CONFIG_RT_USING_STDC_ATOMIC is not set -# CONFIG_RT_USING_CACHE is not set -CONFIG_RT_USING_HW_ATOMIC=y -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_FINSH_USING_OPTION_COMPLETION=y - -# -# DFS: device virtual file system -# -# CONFIG_RT_USING_DFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -# CONFIG_RT_USING_NULL is not set -# CONFIG_RT_USING_ZERO is not set -# CONFIG_RT_USING_RANDOM is not set -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_FDT is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_LCD is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_VIRTIO is not set -# CONFIG_RT_USING_KTIME is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# - -# -# ISO-ANSI C layer -# - -# -# Timezone and Daylight Saving Time -# -# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set -CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y -CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 -CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 -CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RESOURCE_ID is not set -# CONFIG_RT_USING_ADT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_RYANMQTT is not set -# CONFIG_PKG_USING_RYANW5500 is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set -# CONFIG_PKG_USING_WOL is not set -# CONFIG_PKG_USING_ZEPHYR_POLLING is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_3GPP_AMRNB is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set -# CONFIG_PKG_USING_VOFA_PLUS is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set -# CONFIG_PKG_USING_AGILE_UPGRADE is not set -# CONFIG_PKG_USING_FLASH_BLOB is not set -# CONFIG_PKG_USING_MLIBC is not set - -# -# peripheral libraries and drivers -# - -# -# sensors drivers -# -# CONFIG_PKG_USING_LSM6DSM is not set -# CONFIG_PKG_USING_LSM6DSL is not set -# CONFIG_PKG_USING_LPS22HB is not set -# CONFIG_PKG_USING_HTS221 is not set -# CONFIG_PKG_USING_LSM303AGR is not set -# CONFIG_PKG_USING_BME280 is not set -# CONFIG_PKG_USING_BME680 is not set -# CONFIG_PKG_USING_BMA400 is not set -# CONFIG_PKG_USING_BMI160_BMX160 is not set -# CONFIG_PKG_USING_SPL0601 is not set -# CONFIG_PKG_USING_MS5805 is not set -# CONFIG_PKG_USING_DA270 is not set -# CONFIG_PKG_USING_DF220 is not set -# CONFIG_PKG_USING_HSHCAL001 is not set -# CONFIG_PKG_USING_BH1750 is not set -# CONFIG_PKG_USING_MPU6XXX is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_TSL4531 is not set -# CONFIG_PKG_USING_DS18B20 is not set -# CONFIG_PKG_USING_DHT11 is not set -# CONFIG_PKG_USING_DHTXX is not set -# CONFIG_PKG_USING_GY271 is not set -# CONFIG_PKG_USING_GP2Y10 is not set -# CONFIG_PKG_USING_SGP30 is not set -# CONFIG_PKG_USING_HDC1000 is not set -# CONFIG_PKG_USING_BMP180 is not set -# CONFIG_PKG_USING_BMP280 is not set -# CONFIG_PKG_USING_SHTC1 is not set -# CONFIG_PKG_USING_BMI088 is not set -# CONFIG_PKG_USING_HMC5883 is not set -# CONFIG_PKG_USING_MAX6675 is not set -# CONFIG_PKG_USING_TMP1075 is not set -# CONFIG_PKG_USING_SR04 is not set -# CONFIG_PKG_USING_CCS811 is not set -# CONFIG_PKG_USING_PMSXX is not set -# CONFIG_PKG_USING_RT3020 is not set -# CONFIG_PKG_USING_MLX90632 is not set -# CONFIG_PKG_USING_MLX90393 is not set -# CONFIG_PKG_USING_MLX90392 is not set -# CONFIG_PKG_USING_MLX90397 is not set -# CONFIG_PKG_USING_MS5611 is not set -# CONFIG_PKG_USING_MAX31865 is not set -# CONFIG_PKG_USING_VL53L0X is not set -# CONFIG_PKG_USING_INA260 is not set -# CONFIG_PKG_USING_MAX30102 is not set -# CONFIG_PKG_USING_INA226 is not set -# CONFIG_PKG_USING_LIS2DH12 is not set -# CONFIG_PKG_USING_HS300X is not set -# CONFIG_PKG_USING_ZMOD4410 is not set -# CONFIG_PKG_USING_ISL29035 is not set -# CONFIG_PKG_USING_MMC3680KJ is not set -# CONFIG_PKG_USING_QMP6989 is not set -# CONFIG_PKG_USING_BALANCE is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_STHS34PF80 is not set - -# -# touch drivers -# -# CONFIG_PKG_USING_GT9147 is not set -# CONFIG_PKG_USING_GT1151 is not set -# CONFIG_PKG_USING_GT917S is not set -# CONFIG_PKG_USING_GT911 is not set -# CONFIG_PKG_USING_FT6206 is not set -# CONFIG_PKG_USING_FT5426 is not set -# CONFIG_PKG_USING_FT6236 is not set -# CONFIG_PKG_USING_XPT2046_TOUCH is not set -# CONFIG_PKG_USING_CST816X is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_ILI9341 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set -# CONFIG_PKG_USING_LRF_NV7LIDAR is not set -# CONFIG_PKG_USING_AIP650 is not set -# CONFIG_PKG_USING_FINGERPRINT is not set -# CONFIG_PKG_USING_BT_ECB02C is not set -# CONFIG_PKG_USING_UAT is not set -# CONFIG_PKG_USING_SPI_TOOLS is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# Signal Processing and Control Algorithm Packages -# -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_QPID is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_KISSFFT is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_MORSE is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set -# CONFIG_PKG_USING_CorevMCU_CLI is not set - -# -# Arduino libraries -# -# CONFIG_PKG_USING_RTDUINO is not set - -# -# Projects and Demos -# -# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set -# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set -# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set -# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set - -# -# Sensors -# -# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set -# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set -# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set -# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set -# CONFIG_PKG_USING_SEEED_ITG3200 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set -# CONFIG_PKG_USING_SEEED_MP503 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set - -# -# Display -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set -# CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set -# CONFIG_PKG_USING_SEEED_TM1637 is not set - -# -# Timing -# -# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set -# CONFIG_PKG_USING_ARDUINO_TICKER is not set -# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set - -# -# Data Processing -# -# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set -# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set - -# -# Data Storage -# - -# -# Communication -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set - -# -# Device Control -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set -# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set - -# -# Other -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set - -# -# Signal IO -# -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set -# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set - -# -# Uncategorized -# - -# -# Hardware Drivers Config -# -CONFIG_SOC_GD32VF103V=y - -# -# Onboard Peripheral Drivers -# -CONFIG_BSP_USING_USART=y - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_GPIO=y -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y - -# -# Board extended module Drivers -# -CONFIG_SOC_GD32VF103=y diff --git a/bsp/gd32vf103v-eval/.cproject b/bsp/gd32vf103v-eval/.cproject deleted file mode 100644 index aea4ab4f37..0000000000 --- a/bsp/gd32vf103v-eval/.cproject +++ /dev/null @@ -1,205 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/gd32vf103v-eval/.project b/bsp/gd32vf103v-eval/.project deleted file mode 100644 index ee79a7f74b..0000000000 --- a/bsp/gd32vf103v-eval/.project +++ /dev/null @@ -1,88 +0,0 @@ - - - GD32V103V_EVAL - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - rt-thread - 2 - virtual:/virtual - - - rt-thread/components - 2 - virtual:/virtual - - - rt-thread/include - 2 - $%7BPARENT-2-PROJECT_LOC%7D/include - - - rt-thread/lipcpu - 2 - virtual:/virtual - - - rt-thread/src - 2 - $%7BPARENT-2-PROJECT_LOC%7D/src - - - rt-thread/components/drivers - 2 - virtual:/virtual - - - rt-thread/components/finsh - 2 - $%7BPARENT-2-PROJECT_LOC%7D/components/finsh - - - rt-thread/components/src - 2 - $%7BPARENT-2-PROJECT_LOC%7D/components/drivers/src - - - rt-thread/lipcpu/bumblebee - 2 - $%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/bumblebee - - - rt-thread/lipcpu/common - 2 - $%7BPARENT-2-PROJECT_LOC%7D/libcpu/risc-v/common - - - rt-thread/components/drivers/include - 2 - $%7BPARENT-2-PROJECT_LOC%7D/components/drivers/include - - - rt-thread/components/drivers/serial - 2 - $%7BPARENT-2-PROJECT_LOC%7D/components/drivers/serial - - - diff --git a/bsp/gd32vf103v-eval/.settings/language.settings.xml b/bsp/gd32vf103v-eval/.settings/language.settings.xml deleted file mode 100644 index c19958c02a..0000000000 --- a/bsp/gd32vf103v-eval/.settings/language.settings.xml +++ /dev/null @@ -1,14 +0,0 @@ - - - - - - - - - - - - - - diff --git a/bsp/gd32vf103v-eval/Kconfig b/bsp/gd32vf103v-eval/Kconfig deleted file mode 100644 index ce603362e1..0000000000 --- a/bsp/gd32vf103v-eval/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "board/Kconfig" - -config SOC_GD32VF103 - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y diff --git a/bsp/gd32vf103v-eval/README.md b/bsp/gd32vf103v-eval/README.md deleted file mode 100644 index d591e6e599..0000000000 --- a/bsp/gd32vf103v-eval/README.md +++ /dev/null @@ -1,119 +0,0 @@ -# GD32VF103 # - -## 简介 - -gd32vf103v-eval 是由兆易创新公å¸æŽ¨å‡ºçš„基于开æºæŒ‡ä»¤é›† RISC-V 架构的开å‘æ¿ã€‚ - -### æ¿è½½èµ„æºï¼š - -| 硬件 | æè¿° | -| -- | -- | -| 内核 | Bumblebee | -| 架构 | 32-bit RV32IMAC | -| 主频 | 108 MHz | - -## 编译说明 - -### 导入工程 -打开 Eclipse 选择工作空间 - -![指定工作空间](figures/open_eclipse.png) - -打开 Eclipse åŽéœ€è¦å¯¼å…¥ RT-Thread 工程 - -![导入工程](figures/file.png) - -选择以存在的工程，并指定工程路径 - -![选择存在工程](figures/exist.png) - -指定工程路径 - -![指定工程路径](figures/finish_port.png) - - -### 添加环境å˜é‡ -设置 Build Tools Path - -![build_path](figures/build_path.png) - -点击 MCU 列表中的 Build Tools Path 选项，为其选择 SDK 文件包中æ供的对应工具 - -设置 OpenOCD Path - -![open_ocd](figures/open_ocd.png) - -点击 MCU 列表中的 OpenOCD Path 选项，为其选择 SDK 文件包中æ供的对应工具。 - -设置 RISC-V Toolchains Path - -![risc-v](figures/risc-v-tool.png) - -点击 MCU 列表中的 RISC-V Toolchains Paths 选项，为其选择 SDK 文件包中æ供的对应工具。 - -按照以上步骤设置好路径点击编译å³å¯ç¼–译工程 - -![build](figures/build_project.png) - -## 烧写åŠæ‰§è¡Œ - -### 替æ¢é©±åŠ¨ - -1. 执行 JLink_Windows_V622c.exe (å¯ä»¥æ˜¯ä»»æ„版本)安装 JLink 驱动程åºã€‚ -2. 执行 Zadig.exe，点击 Options->List All Devices。 -3. 在下图 1 处选择 J-Link，2 处选择 WinUSB， 之åŽç‚¹å‡» 3 处 Replace Driver 进行驱动替æ¢ã€‚ - -![zadig](figures/zadig.png) - -安装完æˆä¹‹åŽä¼šå¼¹å‡ºå¦‚下窗å£ï¼š - -![close](figures/close.png) - -### é…ç½® GDB 调试 - -在èœå•æ ä¸­ï¼Œç‚¹å‡» Run->Debug Configurations，进入 Debug é…置界é¢ï¼Œå¦‚下图所示： - -![open_debug](figures/open_debug.png) - -这里使用 OpenOCD 作为 GDB Server，使用GCC工具链中的 GDB 工具作为 GDB Client。åŒå‡» GDB OpenOCD Debugging，新建一套 OpenOCD çš„é…置选项。 - -Main é€‰é¡¹å¡ - -Main 选项å¡é…ç½®ç•Œé¢ - -![main_select](figures/main_select.png) - -选择当å‰å·¥ç¨‹ GD32VF103，并且选择当å‰åž‹å·çš„å¯æ‰§è¡Œæ–‡ä»¶ï¼Œä¾‹å¦‚：GD32VF103xB\GD32VF103xB.elf。 - -Debugger é€‰é¡¹å¡ - Debugger 选项å¡é…ç½®ç•Œé¢ - -![debug_select](figures/debug_select.png) - -在 Debugger 选项å¡ä¸­ï¼Œç¡®è®¤çº¢åœˆä¸­çš„é…置正确。 -其中，“Config options†是为 OpenOCD 选择é…置文件，需è¦æ ¹æ®å½“å‰ä½¿ç”¨çš„下载器选择ä¸åŒçš„ cfg 文件。 - -上述é…置内容é…置好åŽï¼Œç‚¹å‡»åº”用调试。 -### è¿è¡Œç»“æžœ - -下载程åºä¹‹åŽï¼Œè¿žæŽ¥ä¸²å£(115200-N-8-1)，å¯ä»¥çœ‹åˆ° RT-Thread 的输出信æ¯ï¼š - -``` - \ | / -- RT - Thread Operating System - / | \ 4.0.2 build Jul 24 2019 - 2006 - 2019 Copyright by rt-thread team -msh > -``` - -## 驱动支æŒæƒ…况 - -| 驱动 | 支æŒæƒ…况 | 备注 | -| ------ | ---- | :------: | -| USART | æ”¯æŒ | UART0_TX/RX：GPIO 9/10 | - -## 5. è”ç³»äººä¿¡æ¯ - -维护人： -- [tyustli](https://github.com/tyustli) - diff --git a/bsp/gd32vf103v-eval/SConscript b/bsp/gd32vf103v-eval/SConscript deleted file mode 100644 index 9044e1496c..0000000000 --- a/bsp/gd32vf103v-eval/SConscript +++ /dev/null @@ -1,16 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') -from building import * - -cwd = str(Dir('#')) -src = Glob('*.c') -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/gd32vf103v-eval/SConstruct b/bsp/gd32vf103v-eval/SConstruct deleted file mode 100644 index 1de7e09b16..0000000000 --- a/bsp/gd32vf103v-eval/SConstruct +++ /dev/null @@ -1,31 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -DefaultEnvironment(tools=[]) -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) -env['ASCOM'] = env['ASPPCOM'] - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/gd32vf103v-eval/applications/SConscript b/bsp/gd32vf103v-eval/applications/SConscript deleted file mode 100644 index ef1c39fd83..0000000000 --- a/bsp/gd32vf103v-eval/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = GetCurrentDir() -src = Glob('*.c') -CPPPATH = [cwd, ] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32vf103v-eval/applications/main.c b/bsp/gd32vf103v-eval/applications/main.c deleted file mode 100644 index 9d7d2edafe..0000000000 --- a/bsp/gd32vf103v-eval/applications/main.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-23 tyustli first version - */ - -#include -#include - -int main(int argc, char *argv[]) { - return RT_EOK; -} - -/******************** end of file *******************/ - diff --git a/bsp/gd32vf103v-eval/board/Kconfig b/bsp/gd32vf103v-eval/board/Kconfig deleted file mode 100644 index 6ca5167e6a..0000000000 --- a/bsp/gd32vf103v-eval/board/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -menu "Hardware Drivers Config" - -config SOC_GD32VF103V - bool - select SOC_SERIES_GD32VF103V - select RT_USING_HW_ATOMIC - default y - -menu "Onboard Peripheral Drivers" - - config BSP_USING_USART - bool "Enable USART (usart0)" - select BSP_USING_UART - select BSP_USING_UART0 - default y -endmenu - -menu "On-chip Peripheral Drivers" - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menuconfig BSP_USING_UART - bool "Enable USART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART0 - bool "Enable USART0" - default y - endif - -endmenu - -menu "Board extended module Drivers" - -endmenu - -endmenu diff --git a/bsp/gd32vf103v-eval/board/SConscript b/bsp/gd32vf103v-eval/board/SConscript deleted file mode 100644 index 4e68c3dc89..0000000000 --- a/bsp/gd32vf103v-eval/board/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Split(''' -board.c -trap_gcc.S -''') -CPPPATH = [cwd] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32vf103v-eval/board/board.c b/bsp/gd32vf103v-eval/board/board.c deleted file mode 100644 index e8d61deec1..0000000000 --- a/bsp/gd32vf103v-eval/board/board.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-23 tyustli first version - * - */ -#include -#include -#include -#include "board.h" - -#ifdef RT_USING_SERIAL -#include -#endif - -/* System Tick Configuration */ -static void systick_config(rt_uint32_t ticks) { - /* set value */ - *(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIMECMP) = ticks; - /* enable interrupt */ - eclic_irq_enable(CLIC_INT_TMR, 0, 0); - /* clear value */ - *(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIME) = 0; -} - -/* This is the timer interrupt service routine. */ -void eclic_mtip_handler(void) { - /* clear value */ - *(rt_uint64_t *) (TMR_CTRL_ADDR + TMR_MTIME) = 0; - - /* enter interrupt */ - rt_interrupt_enter(); - /* tick increase */ - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/* fixed misaligned bug for qemu */ -void *__wrap_memset(void *s, int c, size_t n) -{ - return rt_memset(s, c, n); -} - -void rt_hw_board_init(void) { -extern void riscv_clock_init(void); - riscv_clock_init(); - systick_config(TMR_FREQ / RT_TICK_PER_SECOND); - -#ifdef RT_USING_HEAP - rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END); -#endif - - /* USART driver initialization is open by default */ -#ifdef RT_USING_SERIAL - rt_hw_usart_init(); -#endif - - /* Set the shell console output device */ -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - - /* Board underlying hardware initialization */ -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -} - -/******************** end of file *******************/ - diff --git a/bsp/gd32vf103v-eval/board/board.h b/bsp/gd32vf103v-eval/board/board.h deleted file mode 100644 index 860d71698b..0000000000 --- a/bsp/gd32vf103v-eval/board/board.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-23 tyustli first version - * - */ - -#ifndef __BOARD__ -#define __BOARD__ -#include "gd32vf103.h" - -extern void *_end; -extern void *_heap_end; -#define HEAP_BEGIN &_end -#define HEAP_END &_heap_end - -void rt_hw_board_init(void); - -#endif /* __BOARD__ */ - -/******************** end of file *******************/ diff --git a/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h b/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h deleted file mode 100644 index 58ef886900..0000000000 --- a/bsp/gd32vf103v-eval/board/gd32vf103_libopt.h +++ /dev/null @@ -1,64 +0,0 @@ -/*! - \file gd32vf103_libopt.h - \brief library optional for gd32vf103 - - \version 2019-6-5, V1.0.0, demo for GD32VF103 - */ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - */ - -#ifndef GD32VF103_LIBOPT_H -#define GD32VF103_LIBOPT_H - -#include "gd32vf103_adc.h" -#include "gd32vf103_bkp.h" -#include "gd32vf103_can.h" -#include "gd32vf103_crc.h" -#include "gd32vf103_dac.h" -#include "gd32vf103_dma.h" -#include "gd32vf103_eclic.h" -#include "gd32vf103_exmc.h" -#include "gd32vf103_exti.h" -#include "gd32vf103_fmc.h" -#include "gd32vf103_gpio.h" -#include "gd32vf103_i2c.h" -#include "gd32vf103_fwdgt.h" -#include "gd32vf103_dbg.h" -#include "gd32vf103_pmu.h" -#include "gd32vf103_rcu.h" -#include "gd32vf103_rtc.h" -#include "gd32vf103_spi.h" -#include "gd32vf103_timer.h" -#include "gd32vf103_usart.h" -#include "gd32vf103_wwdgt.h" -#include "n22_func.h" - -#endif /* GD32VF103_LIBOPT_H */ - -/******************** end of file *******************/ - diff --git a/bsp/gd32vf103v-eval/board/trap_gcc.S b/bsp/gd32vf103v-eval/board/trap_gcc.S deleted file mode 100644 index 745e430dee..0000000000 --- a/bsp/gd32vf103v-eval/board/trap_gcc.S +++ /dev/null @@ -1,18 +0,0 @@ -#include "cpuport.h" - - .globl rt_hw_do_after_save_above - .type rt_hw_do_after_save_above,@function -rt_hw_do_after_save_above: - addi sp, sp, -4 - STORE ra, 0 * REGBYTES(sp) - csrr a0, mcause - csrr a1, mepc - mv a2, sp - csrrw ra, 0x07ED, ra - - li t0, 0x08 - csrc mstatus, t0 - - LOAD ra, 0 * REGBYTES(sp) - addi sp, sp, 4 - ret diff --git a/bsp/gd32vf103v-eval/drivers/SConscript b/bsp/gd32vf103v-eval/drivers/SConscript deleted file mode 100644 index 62bdb1ffee..0000000000 --- a/bsp/gd32vf103v-eval/drivers/SConscript +++ /dev/null @@ -1,19 +0,0 @@ -# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Split(''' -drv_usart.c -''') -CPPPATH = [cwd] - -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.c b/bsp/gd32vf103v-eval/drivers/drv_gpio.c deleted file mode 100644 index d6d4cbded0..0000000000 --- a/bsp/gd32vf103v-eval/drivers/drv_gpio.c +++ /dev/null @@ -1,572 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-06-27 BalanceTWK first version - */ - -#include "drv_gpio.h" -#include - -#ifdef RT_USING_PIN - -#define EXTI_(x) BIT(x) - -static const struct pin_index pins[] = -{ -#if defined(GPIOA) - __GD32VF_PIN(0 , A, 0 ), - __GD32VF_PIN(1 , A, 1 ), - __GD32VF_PIN(2 , A, 2 ), - __GD32VF_PIN(3 , A, 3 ), - __GD32VF_PIN(4 , A, 4 ), - __GD32VF_PIN(5 , A, 5 ), - __GD32VF_PIN(6 , A, 6 ), - __GD32VF_PIN(7 , A, 7 ), - __GD32VF_PIN(8 , A, 8 ), - __GD32VF_PIN(9 , A, 9 ), - __GD32VF_PIN(10, A, 10), - __GD32VF_PIN(11, A, 11), - __GD32VF_PIN(12, A, 12), - __GD32VF_PIN(13, A, 13), - __GD32VF_PIN(14, A, 14), - __GD32VF_PIN(15, A, 15), -#if defined(GPIOB) - __GD32VF_PIN(16, B, 0), - __GD32VF_PIN(17, B, 1), - __GD32VF_PIN(18, B, 2), - __GD32VF_PIN(19, B, 3), - __GD32VF_PIN(20, B, 4), - __GD32VF_PIN(21, B, 5), - __GD32VF_PIN(22, B, 6), - __GD32VF_PIN(23, B, 7), - __GD32VF_PIN(24, B, 8), - __GD32VF_PIN(25, B, 9), - __GD32VF_PIN(26, B, 10), - __GD32VF_PIN(27, B, 11), - __GD32VF_PIN(28, B, 12), - __GD32VF_PIN(29, B, 13), - __GD32VF_PIN(30, B, 14), - __GD32VF_PIN(31, B, 15), -#if defined(GPIOC) - __GD32VF_PIN(32, C, 0), - __GD32VF_PIN(33, C, 1), - __GD32VF_PIN(34, C, 2), - __GD32VF_PIN(35, C, 3), - __GD32VF_PIN(36, C, 4), - __GD32VF_PIN(37, C, 5), - __GD32VF_PIN(38, C, 6), - __GD32VF_PIN(39, C, 7), - __GD32VF_PIN(40, C, 8), - __GD32VF_PIN(41, C, 9), - __GD32VF_PIN(42, C, 10), - __GD32VF_PIN(43, C, 11), - __GD32VF_PIN(44, C, 12), - __GD32VF_PIN(45, C, 13), - __GD32VF_PIN(46, C, 14), - __GD32VF_PIN(47, C, 15), -#if defined(GPIOD) - __GD32VF_PIN(48, D, 0), - __GD32VF_PIN(49, D, 1), - __GD32VF_PIN(50, D, 2), - __GD32VF_PIN(51, D, 3), - __GD32VF_PIN(52, D, 4), - __GD32VF_PIN(53, D, 5), - __GD32VF_PIN(54, D, 6), - __GD32VF_PIN(55, D, 7), - __GD32VF_PIN(56, D, 8), - __GD32VF_PIN(57, D, 9), - __GD32VF_PIN(58, D, 10), - __GD32VF_PIN(59, D, 11), - __GD32VF_PIN(60, D, 12), - __GD32VF_PIN(61, D, 13), - __GD32VF_PIN(62, D, 14), - __GD32VF_PIN(63, D, 15), -#if defined(GPIOE) - __GD32VF_PIN(64, E, 0), - __GD32VF_PIN(65, E, 1), - __GD32VF_PIN(66, E, 2), - __GD32VF_PIN(67, E, 3), - __GD32VF_PIN(68, E, 4), - __GD32VF_PIN(69, E, 5), - __GD32VF_PIN(70, E, 6), - __GD32VF_PIN(71, E, 7), - __GD32VF_PIN(72, E, 8), - __GD32VF_PIN(73, E, 9), - __GD32VF_PIN(74, E, 10), - __GD32VF_PIN(75, E, 11), - __GD32VF_PIN(76, E, 12), - __GD32VF_PIN(77, E, 13), - __GD32VF_PIN(78, E, 14), - __GD32VF_PIN(79, E, 15), -#endif /* defined(GPIOE) */ -#endif /* defined(GPIOD) */ -#endif /* defined(GPIOC) */ -#endif /* defined(GPIOB) */ -#endif /* defined(GPIOA) */ -}; - -static const struct pin_irq_map pin_irq_map[] = -{ - {GPIO_PIN_0, EXTI0_IRQn}, - {GPIO_PIN_1, EXTI1_IRQn}, - {GPIO_PIN_2, EXTI2_IRQn}, - {GPIO_PIN_3, EXTI3_IRQn}, - {GPIO_PIN_4, EXTI4_IRQn}, - {GPIO_PIN_5, EXTI5_9_IRQn}, - {GPIO_PIN_6, EXTI5_9_IRQn}, - {GPIO_PIN_7, EXTI5_9_IRQn}, - {GPIO_PIN_8, EXTI5_9_IRQn}, - {GPIO_PIN_9, EXTI5_9_IRQn}, - {GPIO_PIN_10, EXTI10_15_IRQn}, - {GPIO_PIN_11, EXTI10_15_IRQn}, - {GPIO_PIN_12, EXTI10_15_IRQn}, - {GPIO_PIN_13, EXTI10_15_IRQn}, - {GPIO_PIN_14, EXTI10_15_IRQn}, - {GPIO_PIN_15, EXTI10_15_IRQn}, -}; - -static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; -static uint32_t pin_irq_enable_mask=0; - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -static const struct pin_index *get_pin(uint8_t pin) -{ - const struct pin_index *index; - - if (pin < ITEM_NUM(pins)) - { - index = &pins[pin]; - if (index->index == -1) - index = RT_NULL; - } - else - { - index = RT_NULL; - } - - return index; -}; - -static void gd32vf_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) -{ - const struct pin_index *index; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - gpio_bit_write(index->gpio_periph, index->pin, (bit_status)value); -} - -static rt_int8_t gd32vf_pin_read(rt_device_t dev, rt_base_t pin) -{ - rt_int8_t value; - const struct pin_index *index; - - index = get_pin(pin); - if (index == RT_NULL) - { - return PIN_LOW; - } - - value = gpio_input_bit_get(index->gpio_periph, index->pin); - return value; -} - -static void gd32vf_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) -{ - const struct pin_index *index; - - index = get_pin(pin); - if (index == RT_NULL) - { - return; - } - - /* Configure GPIO_InitStructure */ - if (mode == PIN_MODE_OUTPUT) - { - /* output setting */ - gpio_init(index->gpio_periph, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, index->pin); - gpio_bit_reset(index->gpio_periph, index->pin); - } - else if (mode == PIN_MODE_INPUT) - { - /* input setting: not pull. */ - gpio_init(index->gpio_periph, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, index->pin); - gpio_bit_reset(index->gpio_periph, index->pin); - } - else if (mode == PIN_MODE_INPUT_PULLUP) - { - /* input setting: pull up. */ - gpio_init(index->gpio_periph, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, index->pin); - gpio_bit_reset(index->gpio_periph, index->pin); - } - else if (mode == PIN_MODE_INPUT_PULLDOWN) - { - /* input setting: pull down. */ - gpio_init(index->gpio_periph, GPIO_MODE_IPD, GPIO_OSPEED_50MHZ, index->pin); - gpio_bit_reset(index->gpio_periph, index->pin); - } - else if (mode == PIN_MODE_OUTPUT_OD) - { - /* output setting: od. */ - gpio_init(index->gpio_periph, GPIO_MODE_OUT_OD, GPIO_OSPEED_50MHZ, index->pin); - gpio_bit_reset(index->gpio_periph, index->pin); - } -} - -rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) -{ - int i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { - return i; - } - } - return -1; -} - -rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) -{ - rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) - { - return RT_NULL; - } - return &pin_irq_map[mapindex]; -}; - -static rt_err_t gd32vf_pin_attach_irq(struct rt_device *device, rt_base_t pin, - rt_uint8_t mode, void (*hdr)(void *args), void *args) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_ENOSYS; - } - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return -RT_ENOSYS; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[irqindex].pin != -1) - { - rt_hw_interrupt_enable(level); - return -RT_EBUSY; - } - pin_irq_hdr_tab[irqindex].pin = pin; - pin_irq_hdr_tab[irqindex].hdr = hdr; - pin_irq_hdr_tab[irqindex].mode = mode; - pin_irq_hdr_tab[irqindex].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -static rt_err_t gd32vf_pin_dettach_irq(struct rt_device *device, rt_base_t pin) -{ - const struct pin_index *index; - rt_base_t level; - rt_int32_t irqindex = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_ENOSYS; - } - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return -RT_ENOSYS; - } - - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - pin_irq_hdr_tab[irqindex].pin = -1; - pin_irq_hdr_tab[irqindex].hdr = RT_NULL; - pin_irq_hdr_tab[irqindex].mode = 0; - pin_irq_hdr_tab[irqindex].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -static rt_err_t gd32vf_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint8_t enabled) -{ - const struct pin_index *index; - const struct pin_irq_map *irqmap; - rt_base_t level; - rt_int32_t irqindex = -1; - - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_ENOSYS; - } - - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) - { - return -RT_ENOSYS; - } - - if (enabled == PIN_IRQ_ENABLE) - { - level = rt_hw_interrupt_disable(); - - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return -RT_ENOSYS; - } - - irqmap = &pin_irq_map[irqindex]; - - /* enable and set EXTI interrupt to the lowest priority */ - eclic_irq_enable(irqmap->irqno, 1, 1); - /* select SOURCE_PORT_x and SOURCE_PIN_x */ - gpio_exti_source_select(index->index >> 4, irqindex); - /* Configure GPIO_InitStructure */ - switch (pin_irq_hdr_tab[irqindex].mode) - { - case PIN_IRQ_MODE_RISING: - gpio_init( index->gpio_periph, GPIO_MODE_IPD, GPIO_OSPEED_50MHZ, - index->pin ); - exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_RISING); - break; - case PIN_IRQ_MODE_FALLING: - gpio_init( index->gpio_periph, GPIO_MODE_IPU, GPIO_OSPEED_50MHZ, - index->pin ); - exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_FALLING); - break; - case PIN_IRQ_MODE_RISING_FALLING: - gpio_init(index->gpio_periph, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, - index->pin); - exti_init(EXTI_(irqindex), EXTI_INTERRUPT, EXTI_TRIG_BOTH); - break; - } - - pin_irq_enable_mask |= irqmap->pinbit; - /* irqindex should be bitno and then EXTI_(x) can be the bit */ - exti_interrupt_flag_clear(EXTI_(irqindex)); - - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { - return -RT_ENOSYS; - } - - level = rt_hw_interrupt_disable(); - - gpio_bit_reset(index->gpio_periph, index->pin); - - pin_irq_enable_mask &= ~irqmap->pinbit; - - eclic_irq_disable(irqmap->irqno); - exti_interrupt_flag_clear(EXTI_(irqindex)); - - rt_hw_interrupt_enable(level); - } - else - { - return -RT_ENOSYS; - } - - return RT_EOK; -} -const static struct rt_pin_ops _gd32vf_pin_ops = -{ - gd32vf_pin_mode, - gd32vf_pin_write, - gd32vf_pin_read, - gd32vf_pin_attach_irq, - gd32vf_pin_dettach_irq, - gd32vf_pin_irq_enable, - RT_NULL, -}; - -rt_inline void pin_irq_hdr(int irqno) -{ - if (pin_irq_hdr_tab[irqno].hdr) - { - pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); - } -} - -/* IRQHandler start */ -void EXTI0_IRQHandler(void) -{ - if(EXTI_PD & (uint32_t) EXTI_0) - { - exti_interrupt_flag_clear(EXTI_0); - pin_irq_hdr(bit2bitno(GPIO_PIN_0)); - } -} -void EXTI1_IRQHandler(void) -{ - if(EXTI_PD & (uint32_t) EXTI_1) - { - exti_interrupt_flag_clear(EXTI_1); - pin_irq_hdr(bit2bitno(GPIO_PIN_1)); - } -} -void EXTI2_IRQHandler(void) -{ - if(EXTI_PD & (uint32_t) EXTI_2) - { - exti_interrupt_flag_clear(EXTI_2); - pin_irq_hdr(bit2bitno(GPIO_PIN_2)); - } -} -void EXTI3_IRQHandler(void) -{ - if(EXTI_PD & (uint32_t) EXTI_3) - { - exti_interrupt_flag_clear(EXTI_3); - pin_irq_hdr(bit2bitno(GPIO_PIN_3)); - } -} -void EXTI4_IRQHandler(void) -{ - if(EXTI_PD & (uint32_t) EXTI_4) - { - exti_interrupt_flag_clear(EXTI_4); - pin_irq_hdr(bit2bitno(GPIO_PIN_4)); - } -} -void EXTI5_9_IRQHandler(void) -{ - if(EXTI_PD & (uint32_t) EXTI_5) - { - exti_interrupt_flag_clear(EXTI_5); - pin_irq_hdr(bit2bitno(GPIO_PIN_5)); - } - - if(EXTI_PD & (uint32_t) EXTI_6) - { - exti_interrupt_flag_clear(EXTI_6); - pin_irq_hdr(bit2bitno(GPIO_PIN_6)); - } - - if(EXTI_PD & (uint32_t) EXTI_7) - { - exti_interrupt_flag_clear(EXTI_7); - pin_irq_hdr(bit2bitno(GPIO_PIN_7)); - } - - if(EXTI_PD & (uint32_t) EXTI_8) - { - exti_interrupt_flag_clear(EXTI_8); - pin_irq_hdr(bit2bitno(GPIO_PIN_8)); - } - - if(EXTI_PD & (uint32_t) EXTI_9) - { - exti_interrupt_flag_clear(EXTI_9); - pin_irq_hdr(bit2bitno(GPIO_PIN_9)); - } -} -void EXTI10_15_IRQHandler(void) -{ - if(EXTI_PD & (uint32_t) EXTI_10) - { - exti_interrupt_flag_clear(EXTI_10); - pin_irq_hdr(bit2bitno(GPIO_PIN_10)); - } - - if(EXTI_PD & (uint32_t) EXTI_11) - { - exti_interrupt_flag_clear(EXTI_11); - pin_irq_hdr(bit2bitno(GPIO_PIN_11)); - } - - if(EXTI_PD & (uint32_t) EXTI_12) - { - exti_interrupt_flag_clear(EXTI_12); - pin_irq_hdr(bit2bitno(GPIO_PIN_12)); - } - - if(EXTI_PD & (uint32_t) EXTI_13) - { - exti_interrupt_flag_clear(EXTI_13); - pin_irq_hdr(bit2bitno(GPIO_PIN_13)); - } - - if(EXTI_PD & (uint32_t) EXTI_14) - { - exti_interrupt_flag_clear(EXTI_14); - pin_irq_hdr(bit2bitno(GPIO_PIN_14)); - } - - if(EXTI_PD & (uint32_t) EXTI_15) - { - exti_interrupt_flag_clear(EXTI_15); - pin_irq_hdr(bit2bitno(GPIO_PIN_15)); - } -} -/* IRQHandler end */ - -int rt_hw_pin_init(void) -{ - rcu_periph_clock_enable(RCU_GPIOA); - rcu_periph_clock_enable(RCU_GPIOB); - rcu_periph_clock_enable(RCU_GPIOC); - rcu_periph_clock_enable(RCU_GPIOD); - rcu_periph_clock_enable(RCU_GPIOE); - - rcu_periph_clock_enable(RCU_AF); - return rt_device_pin_register("pin", &_gd32vf_pin_ops, RT_NULL); -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -#endif /* RT_USING_PIN */ diff --git a/bsp/gd32vf103v-eval/drivers/drv_gpio.h b/bsp/gd32vf103v-eval/drivers/drv_gpio.h deleted file mode 100644 index af1094e97d..0000000000 --- a/bsp/gd32vf103v-eval/drivers/drv_gpio.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-06-27 BalanceTWK first version - */ - -#ifndef __DRV_GPIO__H__ -#define __DRV_GPIO__H__ - -#include -#include -#include "board.h" - -/* GD32VF GPIO driver */ -struct pin_index -{ - int index; - uint32_t gpio_periph; - uint32_t pin; -}; - -#define __GD32VF_PIN(index, gpio, gpio_index) \ - { \ - index, GPIO##gpio, GPIO_PIN_##gpio_index \ - } - -struct pin_irq_map -{ - rt_uint16_t pinbit; - IRQn_Type irqno; -}; - -int rt_hw_gpio_init(void); - -#endif /* __DRV_GPIO__H__ */ - -/******************* end of file *******************/ diff --git a/bsp/gd32vf103v-eval/drivers/drv_usart.c b/bsp/gd32vf103v-eval/drivers/drv_usart.c deleted file mode 100644 index 9b6386550a..0000000000 --- a/bsp/gd32vf103v-eval/drivers/drv_usart.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-07-23 tyustli first version - */ - -#include - -#ifdef RT_USING_SERIAL - -#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \ - && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) - #error "Please define at least one BSP_USING_UARTx" - /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ -#endif - -struct gd32_usart { - char *name; - rt_uint32_t usart_base; - rt_uint32_t usart_clk; - rt_uint32_t gpio_clk; - rt_uint32_t gpio_port; - rt_uint32_t tx_pin; - rt_uint32_t rx_pin; - IRQn_Type irqn; - struct rt_serial_device serial; -}; - -enum { -#ifdef BSP_USING_UART0 - GDUSART0_INDEX, -#endif -}; - -static struct gd32_usart usart_config[] = { -#ifdef BSP_USING_UART0 - { "uart0", - USART0, - RCU_USART0, - RCU_GPIOA, - GPIOA, - GPIO_PIN_9, - GPIO_PIN_10, - USART0_IRQn, }, -#endif -}; - -static rt_err_t gd32_configure(struct rt_serial_device *serial, - struct serial_configure *cfg) { - struct gd32_usart *usart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - usart = (struct gd32_usart *) serial->parent.user_data; - RT_ASSERT(usart != RT_NULL); - - /* enable GPIO clock */ - rcu_periph_clock_enable(usart->gpio_clk); - /* enable USART clock */ - rcu_periph_clock_enable(usart->usart_clk); - /* connect port to USARTx_Tx */ - gpio_init(usart->gpio_port, GPIO_MODE_AF_PP, GPIO_OSPEED_50MHZ, - usart->tx_pin); - /* connect port to USARTx_Rx */ - gpio_init(usart->gpio_port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, - usart->rx_pin); - - usart_deinit(usart->usart_base); - usart_baudrate_set(usart->usart_base, cfg->baud_rate); - - switch (cfg->data_bits) { - case DATA_BITS_8: - usart_word_length_set(usart->usart_base, USART_WL_8BIT); - break; - - case DATA_BITS_9: - usart_word_length_set(usart->usart_base, USART_WL_9BIT); - break; - default: - usart_word_length_set(usart->usart_base, USART_WL_8BIT); - break; - } - - switch (cfg->stop_bits) { - case STOP_BITS_1: - usart_stop_bit_set(usart->usart_base, USART_STB_1BIT); - break; - case STOP_BITS_2: - usart_stop_bit_set(usart->usart_base, USART_STB_2BIT); - break; - default: - usart_stop_bit_set(usart->usart_base, USART_STB_1BIT); - break; - } - - switch (cfg->parity) { - case PARITY_NONE: - usart_parity_config(usart->usart_base, USART_PM_NONE); - break; - case PARITY_ODD: - usart_parity_config(usart->usart_base, USART_PM_ODD); - break; - case PARITY_EVEN: - usart_parity_config(usart->usart_base, USART_PM_EVEN); - break; - default: - usart_parity_config(usart->usart_base, USART_PM_NONE); - break; - } - usart_hardware_flow_rts_config(usart->usart_base, USART_RTS_DISABLE); - usart_hardware_flow_cts_config(usart->usart_base, USART_RTS_DISABLE); - usart_receive_config(usart->usart_base, USART_RECEIVE_ENABLE); - usart_transmit_config(usart->usart_base, USART_TRANSMIT_ENABLE); - usart_enable(usart->usart_base); - - return RT_EOK; -} - -static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd, - void *arg) { - struct gd32_usart *usart; - - RT_ASSERT(serial != RT_NULL); - usart = (struct gd32_usart *) serial->parent.user_data; - RT_ASSERT(usart != RT_NULL); - - switch (cmd) { - case RT_DEVICE_CTRL_CLR_INT: - eclic_irq_disable(usart->usart_base); - usart_interrupt_disable(usart->usart_base, USART_INT_RBNE); - break; - case RT_DEVICE_CTRL_SET_INT: - eclic_set_nlbits(ECLIC_GROUP_LEVEL3_PRIO1); - eclic_irq_enable(usart->irqn, 1, 0); - /* enable USART0 receive interrupt */ - usart_interrupt_enable(usart->usart_base, USART_INT_RBNE); - break; - } - - return RT_EOK; -} - -static int gd32_putc(struct rt_serial_device *serial, char ch) { - struct gd32_usart *usart; - - RT_ASSERT(serial != RT_NULL); - usart = (struct gd32_usart *) serial->parent.user_data; - RT_ASSERT(usart != RT_NULL); - - usart_data_transmit(usart->usart_base, (uint8_t) ch); - while (usart_flag_get(usart->usart_base, USART_FLAG_TBE) == RESET) - ; - - return 1; -} - -static int gd32_getc(struct rt_serial_device *serial) { - int ch; - struct gd32_usart *usart; - - RT_ASSERT(serial != RT_NULL); - usart = (struct gd32_usart *) serial->parent.user_data; - RT_ASSERT(usart != RT_NULL); - - ch = -1; - if (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE)) { - ch = usart_data_receive(usart->usart_base) & 0xff; - } - - return ch; -} - -static const struct rt_uart_ops gd32_usart_ops = { gd32_configure, gd32_control, - gd32_putc, gd32_getc, - RT_NULL }; - -static void usart_isr(struct rt_serial_device *serial) { - struct gd32_usart *usart; - - RT_ASSERT(serial != RT_NULL); - - usart = (struct gd32_usart *) serial->parent.user_data; - RT_ASSERT(usart != RT_NULL); - - if ((usart_interrupt_flag_get(usart->usart_base, USART_INT_FLAG_RBNE) - != RESET) - && (RESET != usart_flag_get(usart->usart_base, USART_FLAG_RBNE))) { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - usart_interrupt_flag_clear(usart->usart_base, USART_INT_FLAG_RBNE); - usart_flag_clear(usart->usart_base, USART_FLAG_RBNE); - } else { - if (usart_flag_get(usart->usart_base, USART_FLAG_CTSF) != RESET) { - usart_flag_clear(usart->usart_base, USART_FLAG_CTSF); - } - - if (usart_flag_get(usart->usart_base, USART_FLAG_LBDF) != RESET) { - usart_flag_clear(usart->usart_base, USART_FLAG_LBDF); - } - - if (usart_flag_get(usart->usart_base, USART_FLAG_TC) != RESET) { - usart_flag_clear(usart->usart_base, USART_FLAG_TC); - } - } -} -#ifdef BSP_USING_UART0 - -void USART0_IRQHandler(void) { - rt_interrupt_enter(); - - usart_isr(&usart_config[GDUSART0_INDEX].serial); - - rt_interrupt_leave(); -} - -#endif - -int rt_hw_usart_init(void) { - rt_size_t obj_num; - int index; - - obj_num = sizeof(usart_config) / sizeof(struct gd32_usart); - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - rt_err_t result = 0; - - for (index = 0; index < obj_num; index++) { - usart_config[index].serial.ops = &gd32_usart_ops; - usart_config[index].serial.config = config; - - /* register UART device */ - result = rt_hw_serial_register(&usart_config[index].serial, - usart_config[index].name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX - | RT_DEVICE_FLAG_INT_TX, &usart_config[index]); - RT_ASSERT(result == RT_EOK); - } - - return result; -} - -#endif /* RT_USING_SERIAL */ - -/******************** end of file *******************/ diff --git a/bsp/gd32vf103v-eval/drivers/drv_usart.h b/bsp/gd32vf103v-eval/drivers/drv_usart.h deleted file mode 100644 index d4883262ed..0000000000 --- a/bsp/gd32vf103v-eval/drivers/drv_usart.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __DRV_UART_H__ -#define __DRV_UART_H__ - -#include -#include -#include "board.h" - -int rt_hw_usart_init(void); - -#endif /* __DRV_USART_H__ */ - -/******************* end of file *******************/ diff --git a/bsp/gd32vf103v-eval/figures/build_path.png b/bsp/gd32vf103v-eval/figures/build_path.png deleted file mode 100644 index 9ae319c7c0..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/build_path.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/build_project.png b/bsp/gd32vf103v-eval/figures/build_project.png deleted file mode 100644 index 67e4e9955b..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/build_project.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/close.png b/bsp/gd32vf103v-eval/figures/close.png deleted file mode 100644 index 1714f78450..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/close.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/debug_select.png b/bsp/gd32vf103v-eval/figures/debug_select.png deleted file mode 100644 index 681d698701..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/debug_select.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/exist.png b/bsp/gd32vf103v-eval/figures/exist.png deleted file mode 100644 index 5501ef20dc..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/exist.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/file.png b/bsp/gd32vf103v-eval/figures/file.png deleted file mode 100644 index 989f8175b0..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/file.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/finish_port.png b/bsp/gd32vf103v-eval/figures/finish_port.png deleted file mode 100644 index cfed59b1b5..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/finish_port.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/main_select.png b/bsp/gd32vf103v-eval/figures/main_select.png deleted file mode 100644 index a53d6bdab3..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/main_select.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/open_debug.png b/bsp/gd32vf103v-eval/figures/open_debug.png deleted file mode 100644 index 55d5111a02..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/open_debug.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/open_eclipse.png b/bsp/gd32vf103v-eval/figures/open_eclipse.png deleted file mode 100644 index 4ae619b6ed..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/open_eclipse.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/open_ocd.png b/bsp/gd32vf103v-eval/figures/open_ocd.png deleted file mode 100644 index 09d3d7a83d..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/open_ocd.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/risc-v-tool.png b/bsp/gd32vf103v-eval/figures/risc-v-tool.png deleted file mode 100644 index 17a0c87ce9..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/risc-v-tool.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/figures/zadig.png b/bsp/gd32vf103v-eval/figures/zadig.png deleted file mode 100644 index d6fd72b6be..0000000000 Binary files a/bsp/gd32vf103v-eval/figures/zadig.png and /dev/null differ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h deleted file mode 100644 index 316c021a3f..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_adc.h +++ /dev/null @@ -1,396 +0,0 @@ -/*! - \file gd32vf103_adc.h - \brief definitions for the ADC - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_ADC_H -#define GD32VF103_ADC_H - -#include "gd32vf103.h" - -/* ADC definitions */ -#define ADC0 ADC_BASE -#define ADC1 (ADC_BASE + 0x400U) - -/* registers definitions */ -#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ -#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ - -/* ADC_SAMPTx x=0..1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx x=0..2 */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ -#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ - -/* ADC_OVSCR */ -#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ -#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */ - -/* constants definitions */ -/* adc_stat register value */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ - -/* scan mode */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ - -/* inserted channel group convert automatically */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ - -/* ADC sync mode */ -#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ -#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ -#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ -#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ -#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ - -/* adc_ctl1 register value */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ - -/* continuous mode */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -/* for ADC0 and ADC1 regular channel */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ -#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - -/* external trigger mode for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ -/* for ADC0 and ADC1 inserted channel */ -#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ -#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ -#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* adc_ioffx register value */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ - -/* adc_wdht register value */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ - -/* adc_wdlt register value */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ - -/* adc_rsqx register value */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ - -/* adc_isq register value */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ - -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ -#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ -#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ -#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ -#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ -#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ - -/* ADC interrupt */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* ADC resolution definitions */ -#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */ - -/* ADC oversampling mode */ -#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC oversampling shift */ -#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ - -/* ADC oversampling ratio */ -#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */ - -/* function declarations */ -/* initialization config */ -/* reset ADC */ -void adc_deinit(uint32_t adc_periph); -/* configure the ADC sync mode */ -void adc_mode_config(uint32_t mode); -/* enable or disable ADC special function */ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); -/* enable ADC interface */ -void adc_enable(uint32_t adc_periph); -/* disable ADC interface */ -void adc_disable(uint32_t adc_periph); -/* ADC calibration and reset calibration */ -void adc_calibration_enable(uint32_t adc_periph); -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); - -/* DMA config */ -/* enable DMA request */ -void adc_dma_mode_enable(uint32_t adc_periph); -/* disable DMA request */ -void adc_dma_mode_disable(uint32_t adc_periph); - -/* regular group and inserted group config */ -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); - -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); - -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); -/* configure ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); - -/* get channel data */ -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); -/* read the last ADC0 and ADC1 conversion result data in sync mode */ -uint32_t adc_sync_mode_convert_value_read(void); - -/* watchdog config */ -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(uint32_t adc_periph); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); - -/* interrupt & flag functions */ -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); -/* get the bit state of ADCx software start conversion */ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); -/* get the bit state of ADCx software inserted channel start conversion */ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); - -/* ADC resolution & oversample */ -/* ADC resolution config */ -void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); -/* ADC oversample mode config */ -void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio); -/* enable ADC oversample mode */ -void adc_oversample_mode_enable(uint32_t adc_periph); -/* disable ADC oversample mode */ -void adc_oversample_mode_disable(uint32_t adc_periph); - -#endif /* GD32VF103_ADC_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h deleted file mode 100644 index a6e1a3fd9e..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_bkp.h +++ /dev/null @@ -1,227 +0,0 @@ -/*! - \file gd32vf103_bkp.h - \brief definitions for the BKP - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_BKP_H -#define GD32VF103_BKP_H - -#include "gd32vf103.h" - -/* BKP definitions */ -#define BKP BKP_BASE /*!< BKP base address */ - -/* registers definitions */ -#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ -#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ -#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ -#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ -#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ -#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ -#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ -#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ -#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ -#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ -#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ -#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ -#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ -#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ -#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ -#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ -#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ -#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ -#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ -#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ -#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ -#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ -#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ -#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ -#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ -#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ -#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ -#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ -#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ -#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ -#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ -#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ -#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ -#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ -#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ -#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ -#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ -#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ -#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ -#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ -#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ -#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ -#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ -#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ -#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ - -/* bits definitions */ -/* BKP_DATA */ -#define BKP_DATA BITS(0,15) /*!< backup data */ - -/* BKP_OCTL */ -#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ -#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ -#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ -#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ - -/* BKP_TPCTL */ -#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ -#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ - -/* BKP_TPCS */ -#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ -#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ -#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ -#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ -#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ - -/* constants definitions */ -/* BKP data register number */ -typedef enum -{ - BKP_DATA_0 = 1, /*!< BKP data register 0 */ - BKP_DATA_1, /*!< BKP data register 1 */ - BKP_DATA_2, /*!< BKP data register 2 */ - BKP_DATA_3, /*!< BKP data register 3 */ - BKP_DATA_4, /*!< BKP data register 4 */ - BKP_DATA_5, /*!< BKP data register 5 */ - BKP_DATA_6, /*!< BKP data register 6 */ - BKP_DATA_7, /*!< BKP data register 7 */ - BKP_DATA_8, /*!< BKP data register 8 */ - BKP_DATA_9, /*!< BKP data register 9 */ - BKP_DATA_10, /*!< BKP data register 10 */ - BKP_DATA_11, /*!< BKP data register 11 */ - BKP_DATA_12, /*!< BKP data register 12 */ - BKP_DATA_13, /*!< BKP data register 13 */ - BKP_DATA_14, /*!< BKP data register 14 */ - BKP_DATA_15, /*!< BKP data register 15 */ - BKP_DATA_16, /*!< BKP data register 16 */ - BKP_DATA_17, /*!< BKP data register 17 */ - BKP_DATA_18, /*!< BKP data register 18 */ - BKP_DATA_19, /*!< BKP data register 19 */ - BKP_DATA_20, /*!< BKP data register 20 */ - BKP_DATA_21, /*!< BKP data register 21 */ - BKP_DATA_22, /*!< BKP data register 22 */ - BKP_DATA_23, /*!< BKP data register 23 */ - BKP_DATA_24, /*!< BKP data register 24 */ - BKP_DATA_25, /*!< BKP data register 25 */ - BKP_DATA_26, /*!< BKP data register 26 */ - BKP_DATA_27, /*!< BKP data register 27 */ - BKP_DATA_28, /*!< BKP data register 28 */ - BKP_DATA_29, /*!< BKP data register 29 */ - BKP_DATA_30, /*!< BKP data register 30 */ - BKP_DATA_31, /*!< BKP data register 31 */ - BKP_DATA_32, /*!< BKP data register 32 */ - BKP_DATA_33, /*!< BKP data register 33 */ - BKP_DATA_34, /*!< BKP data register 34 */ - BKP_DATA_35, /*!< BKP data register 35 */ - BKP_DATA_36, /*!< BKP data register 36 */ - BKP_DATA_37, /*!< BKP data register 37 */ - BKP_DATA_38, /*!< BKP data register 38 */ - BKP_DATA_39, /*!< BKP data register 39 */ - BKP_DATA_40, /*!< BKP data register 40 */ - BKP_DATA_41, /*!< BKP data register 41 */ -}bkp_data_register_enum; - -/* BKP register */ -#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) -#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) - -/* get data of BKP data register */ -#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) - -/* RTC clock calibration value */ -#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/* RTC output selection */ -#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ -#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ - -/* tamper pin active level */ -#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ -#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ - -/* tamper flag */ -#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ - -/* tamper interrupt flag */ -#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ - -/* function declarations */ -/* reset BKP registers */ -void bkp_deinit(void); -/* write BKP data register */ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); -/* read BKP data register */ -uint16_t bkp_data_read(bkp_data_register_enum register_number); - -/* RTC related functions */ -/* enable RTC clock calibration output */ -void bkp_rtc_calibration_output_enable(void); -/* disable RTC clock calibration output */ -void bkp_rtc_calibration_output_disable(void); -/* enable RTC alarm or second signal output */ -void bkp_rtc_signal_output_enable(void); -/* disable RTC alarm or second signal output */ -void bkp_rtc_signal_output_disable(void); -/* select RTC output */ -void bkp_rtc_output_select(uint16_t outputsel); -/* set RTC clock calibration value */ -void bkp_rtc_calibration_value_set(uint8_t value); - -/* tamper pin related functions */ -/* enable tamper pin detection */ -void bkp_tamper_detection_enable(void); -/* disable tamper pin detection */ -void bkp_tamper_detection_disable(void); -/* set tamper pin active level */ -void bkp_tamper_active_level_set(uint16_t level); - -/* interrupt & flag functions */ -/* enable tamper interrupt */ -void bkp_interrupt_enable(void); -/* disable tamper interrupt */ -void bkp_interrupt_disable(void); -/* get tamper flag state */ -FlagStatus bkp_flag_get(void); -/* clear tamper flag state */ -void bkp_flag_clear(void); -/* get tamper interrupt flag state */ -FlagStatus bkp_interrupt_flag_get(void); -/* clear tamper interrupt flag state */ -void bkp_interrupt_flag_clear(void); - -#endif /* GD32VF103_BKP_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_can.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_can.h deleted file mode 100644 index db12a5f982..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_can.h +++ /dev/null @@ -1,717 +0,0 @@ -/*! - \file gd32vf103_can.h - \brief definitions for the CAN - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_CAN_H -#define GD32VF103_CAN_H - -#include "gd32vf103.h" - -/* CAN definitions */ -#define CAN0 CAN_BASE /*!< CAN0 base address */ -#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ - -/* registers definitions */ -#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ -#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ -#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ -#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ -#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ -#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ -#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ -#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ -#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ -#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ -#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ -#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ -#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ -#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ -#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ -#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ -#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ -#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ -#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ -#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ -#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ -#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ -#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ -#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ -#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ -#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ -#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ -#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ -#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ -#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ -#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ -#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ -#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ -#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ -#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ -#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ -#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ -#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ -#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ -#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ -#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ -#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ -#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ -#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ -#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ -#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ -#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ -#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ -#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ -#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ -#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ -#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ -#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ -#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ -#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ -#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ -#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ -#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ -#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ -#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ -#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ -#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ -#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ -#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ -#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ -#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ -#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ -#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ -#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ -#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ -#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ -#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ -#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ -#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ -#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ -#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ -#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ -#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ -#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ -#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ -#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ -#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ -#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ -#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ -#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ -#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ -#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ - -/* CAN transmit mailbox bank */ -#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ -#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ -#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ -#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ - -/* CAN filter bank */ -#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ -#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ - -/* CAN receive fifo mailbox bank */ -#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ -#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ -#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ -#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ - -/* bits definitions */ -/* CAN_CTL */ -#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ -#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ -#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ -#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ -#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ -#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ -#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ -#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ -#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ -#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ - -/* CAN_STAT */ -#define CAN_STAT_IWS BIT(0) /*!< initial working state */ -#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ -#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ -#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ -#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ -#define CAN_STAT_TS BIT(8) /*!< transmitting state */ -#define CAN_STAT_RS BIT(9) /*!< receiving state */ -#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ -#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ - -/* CAN_TSTAT */ -#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ -#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ -#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ -#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ -#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ -#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ -#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ -#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ -#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ -#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ -#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ -#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ -#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ -#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ -#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ -#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ -#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ -#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ -#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ -#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ -#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ -#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ - -/* CAN_RFIFO0 */ -#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ -#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ -#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ -#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ - -/* CAN_RFIFO1 */ -#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ -#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ -#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ -#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ - -/* CAN_INTEN */ -#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ -#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ -#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ -#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ -#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ -#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ -#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ -#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ -#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ -#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ - -/* CAN_ERR */ -#define CAN_ERR_WERR BIT(0) /*!< warning error */ -#define CAN_ERR_PERR BIT(1) /*!< passive error */ -#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ -#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ -#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ -#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ - -/* CAN_BT */ -#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ -#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ -#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ -#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ -#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ -#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ - -/* CAN_TMIx */ -#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ -#define CAN_TMI_FT BIT(1) /*!< frame type */ -#define CAN_TMI_FF BIT(2) /*!< frame format */ -#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_TMPx */ -#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ -#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ -#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_TMDATA0x */ -#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ -#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ -#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ -#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ - -/* CAN_TMDATA1x */ -#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ -#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ -#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ -#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ - -/* CAN_RFIFOMIx */ -#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ -#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ -#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ -#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ - -/* CAN_RFIFOMPx */ -#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ -#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ -#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ - -/* CAN_RFIFOMDATA0x */ -#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ -#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ -#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ -#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ - -/* CAN_RFIFOMDATA1x */ -#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ -#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ -#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ -#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ - -/* CAN_FCTL */ -#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ -#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ - -/* CAN_FMCFG */ -#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ - -/* CAN_FSCFG */ -#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ - -/* CAN_FAFIFO */ -#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ - -/* CAN_FW */ -#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ - -/* CAN_FxDATAy */ -#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ - -/* consts definitions */ -/* define the CAN bit position and its register index offset */ -#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) -#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) -#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ -#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ -#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ -#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ -#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ - -/* CAN flags */ -typedef enum { - /* flags in TSTAT register */ - CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ - CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ - CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ - CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ - CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ - CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ - /* flags in RFIFO0 register */ - CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ - CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ - /* flags in RFIFO1 register */ - CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ - CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ - /* flags in ERR register */ - CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ - CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ - CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ -} can_flag_enum; - -/* CAN interrupt flags */ -typedef enum { - /* interrupt flags in STAT register */ - CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ - CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ - CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ - /* interrupt flags in TSTAT register */ - CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ - CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ - CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ - /* interrupt flags in RFIFO0 register */ - CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ - CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ -} can_interrupt_flag_enum; - -/* CAN initiliaze parameters struct */ -typedef struct { - uint8_t working_mode; /*!< CAN working mode */ - uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ - uint8_t time_segment_1; /*!< time segment 1 */ - uint8_t time_segment_2; /*!< time segment 2 */ - ControlStatus time_triggered; /*!< time triggered communication mode */ - ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ - ControlStatus auto_wake_up; /*!< automatic wake-up mode */ - ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ - ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ - ControlStatus trans_fifo_order; /*!< transmit FIFO order */ - uint16_t prescaler; /*!< baudrate prescaler */ -} can_parameter_struct; - -/* CAN transmit message struct */ -typedef struct { - uint32_t tx_sfid; /*!< standard format frame identifier */ - uint32_t tx_efid; /*!< extended format frame identifier */ - uint8_t tx_ff; /*!< format of frame, standard or extended format */ - uint8_t tx_ft; /*!< type of frame, data or remote */ - uint8_t tx_dlen; /*!< data length */ - uint8_t tx_data[8]; /*!< transmit data */ -} can_trasnmit_message_struct; - -/* CAN receive message struct */ -typedef struct { - uint32_t rx_sfid; /*!< standard format frame identifier */ - uint32_t rx_efid; /*!< extended format frame identifier */ - uint8_t rx_ff; /*!< format of frame, standard or extended format */ - uint8_t rx_ft; /*!< type of frame, data or remote */ - uint8_t rx_dlen; /*!< data length */ - uint8_t rx_data[8]; /*!< receive data */ - uint8_t rx_fi; /*!< filtering index */ -} can_receive_message_struct; - -/* CAN filter parameters struct */ -typedef struct { - uint16_t filter_list_high; /*!< filter list number high bits*/ - uint16_t filter_list_low; /*!< filter list number low bits */ - uint16_t filter_mask_high; /*!< filter mask number high bits */ - uint16_t filter_mask_low; /*!< filter mask number low bits */ - uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ - uint16_t filter_number; /*!< filter number */ - uint16_t filter_mode; /*!< filter mode, list or mask */ - uint16_t filter_bits; /*!< filter scale */ - ControlStatus filter_enable; /*!< filter work or not */ -} can_filter_parameter_struct; - -/* CAN errors */ -typedef enum { - CAN_ERROR_NONE = 0, /*!< no error */ - CAN_ERROR_FILL, /*!< fill error */ - CAN_ERROR_FORMATE, /*!< format error */ - CAN_ERROR_ACK, /*!< ACK error */ - CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ - CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ - CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG, /*!< software configure */ -} can_error_enum; - -/* transmit states */ -typedef enum { - CAN_TRANSMIT_FAILED = 0, /*!< CAN transmitted failure */ - CAN_TRANSMIT_OK = 1, /*!< CAN transmitted success */ - CAN_TRANSMIT_PENDING = 2, /*!< CAN transmitted pending */ - CAN_TRANSMIT_NOMAILBOX = 4, /*!< no empty mailbox to be used for CAN */ -} can_transmit_state_enum; - -typedef enum { - CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ - CAN_FILTER_STRUCT, /* CAN filter parameters struct */ - CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ - CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ -} can_struct_type_enum; - -/* CAN baudrate prescaler*/ -#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) - -/* CAN bit segment 1*/ -#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) - -/* CAN bit segment 2*/ -#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) - -/* CAN resynchronization jump width*/ -#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) - -/* CAN communication mode*/ -#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) - -/* CAN FDATA high 16 bits */ -#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) - -/* CAN FDATA low 16 bits */ -#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) - -/* CAN1 filter start bank_number*/ -#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) - -/* CAN transmit mailbox extended identifier*/ -#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) - -/* CAN transmit mailbox standard identifier*/ -#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) - -/* transmit data byte 0 */ -#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 1 */ -#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 2 */ -#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 3 */ -#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* transmit data byte 4 */ -#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* transmit data byte 5 */ -#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) - -/* transmit data byte 6 */ -#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) - -/* transmit data byte 7 */ -#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) - -/* receive mailbox extended identifier*/ -#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3, 31) - -/* receive mailbox standrad identifier*/ -#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21, 31) - -/* receive data length */ -#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0, 3) - -/* the index of the filter by which the frame is passed */ -#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 0 */ -#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 1 */ -#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 2 */ -#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 3 */ -#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* receive data byte 4 */ -#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* receive data byte 5 */ -#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8, 15) - -/* receive data byte 6 */ -#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive data byte 7 */ -#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* error number */ -#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4, 6) - -/* transmit error count */ -#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16, 23) - -/* receive error count */ -#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24, 31) - -/* CAN errors */ -#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) -#define CAN_ERRN_0 ERR_ERRN(0) /* no error */ -#define CAN_ERRN_1 ERR_ERRN(1) /*!< fill error */ -#define CAN_ERRN_2 ERR_ERRN(2) /*!< format error */ -#define CAN_ERRN_3 ERR_ERRN(3) /*!< ACK error */ -#define CAN_ERRN_4 ERR_ERRN(4) /*!< bit recessive error */ -#define CAN_ERRN_5 ERR_ERRN(5) /*!< bit dominant error */ -#define CAN_ERRN_6 ERR_ERRN(6) /*!< CRC error */ -#define CAN_ERRN_7 ERR_ERRN(7) /*!< software error */ - -#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ - -/* CAN communication mode */ -#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ -#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ -#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ -#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ - -/* CAN resynchronisation jump width */ -#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ - -/* CAN time segment 1 */ -#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ -#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ -#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ -#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ -#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ -#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ -#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ -#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ -#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ - -/* CAN time segment 2 */ -#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ -#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ -#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ -#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ -#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ -#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ -#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ -#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ - -/* CAN mailbox number */ -#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ -#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ -#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ -#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ - -/* CAN frame format */ -#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ -#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ - -/* CAN receive fifo */ -#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ -#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ - -/* frame number of receive fifo */ -#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ - -#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ -#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ - -/* CAN working mode */ -#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ -#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ -#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ - -/* filter bits */ -#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ -#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ - -/* filter mode */ -#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ -#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ - -/* filter 16 bits mask */ -#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ - -/* frame type */ -#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ -#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ - -/* CAN timeout */ -#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ - -/* interrupt enable bits */ -#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ -#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ -#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ -#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ -#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ -#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ -#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ -#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ -#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ -#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ -#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ -#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ -#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ -#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ - -/* function declarations */ -/* deinitialize CAN */ -void can_deinit(uint32_t can_periph); -/* initialize CAN struct */ -void can_struct_para_init(can_struct_type_enum type, void* p_struct); -/* initialize CAN */ -ErrStatus can_init(uint32_t can_periph, - can_parameter_struct* can_parameter_init); -/* CAN filter init */ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); -/* set can1 fliter start bank number */ -void can1_filter_start_bank(uint8_t start_bank); -/* enable functions */ -/* CAN debug freeze enable */ -void can_debug_freeze_enable(uint32_t can_periph); -/* CAN debug freeze disable */ -void can_debug_freeze_disable(uint32_t can_periph); -/* CAN time trigger mode enable */ -void can_time_trigger_mode_enable(uint32_t can_periph); -/* CAN time trigger mode disable */ -void can_time_trigger_mode_disable(uint32_t can_periph); - -/* transmit functions */ -/* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, - can_trasnmit_message_struct* transmit_message); -/* get CAN transmit state */ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, - uint8_t mailbox_number); -/* stop CAN transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); -/* CAN receive message */ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, - can_receive_message_struct* receive_message); -/* CAN release fifo */ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); -/* CAN receive message length */ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); -/* CAN working mode */ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); -/* CAN wakeup from sleep mode */ -ErrStatus can_wakeup(uint32_t can_periph); - -/* CAN get error */ -can_error_enum can_error_get(uint32_t can_periph); -/* get CAN receive error number */ -uint8_t can_receive_error_number_get(uint32_t can_periph); -/* get CAN transmit error number */ -uint8_t can_transmit_error_number_get(uint32_t can_periph); - -/* CAN interrupt enable */ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); -/* CAN interrupt disable */ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); -/* CAN get flag state */ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); -/* CAN clear flag state */ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag); -/* CAN get interrupt flag state */ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, - can_interrupt_flag_enum flag); -/* CAN clear interrupt flag state */ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); - -#endif /* GD32VF103_CAN_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h deleted file mode 100644 index c86fe995b3..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_crc.h +++ /dev/null @@ -1,78 +0,0 @@ -/*! - \file gd32vf103_crc.h - \brief definitions for the CRC - - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_CRC_H -#define GD32VF103_CRC_H - -#include "gd32vf103.h" - -/* CRC definitions */ -#define CRC CRC_BASE - -/* registers definitions */ -#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ -#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ -#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ -void crc_data_register_reset(void); -/* read the value of the data register */ -uint32_t crc_data_register_read(void); - -/* read the value of the free data register */ -uint8_t crc_free_data_register_read(void); -/* write data to the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* calculate the CRC value of a 32-bit data */ -uint32_t crc_single_data_calculate(uint32_t sdata); -/* calculate the CRC value of an array of 32-bit values */ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); - -#endif /* GD32VF103_CRC_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h deleted file mode 100644 index 165899f226..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dac.h +++ /dev/null @@ -1,242 +0,0 @@ -/*! - \file gd32vf103_dac.h - \brief definitions for the DAC - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_DAC_H -#define GD32VF103_DAC_H - -#include "gd32vf103.h" - -/* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 (0U) -#define DAC1 (1U) - -/* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ - -/* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ - -/* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ - -/* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ - -/* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ - -/* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ - -/* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ - -/* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ - -/* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ - -/* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ - -/* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ - -/* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ - -/* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ - -/* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ - -/* constants definitions */ -/* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ -#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ - -/* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ - -/* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ - -/* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ - -/* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ - -/* function declarations */ -/* initialization functions */ -/* deinitialize DAC */ -void dac_deinit(void); -/* enable DAC */ -void dac_enable(uint32_t dac_periph); -/* disable DAC */ -void dac_disable(uint32_t dac_periph); -/* enable DAC DMA */ -void dac_dma_enable(uint32_t dac_periph); -/* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); -/* enable DAC output buffer */ -void dac_output_buffer_enable(uint32_t dac_periph); -/* disable DAC output buffer */ -void dac_output_buffer_disable(uint32_t dac_periph); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); -/* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); - -/* DAC trigger configuration */ -/* enable DAC trigger */ -void dac_trigger_enable(uint32_t dac_periph); -/* disable DAC trigger */ -void dac_trigger_disable(uint32_t dac_periph); -/* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); -/* enable DAC software trigger */ -void dac_software_trigger_enable(uint32_t dac_periph); -/* disable DAC software trigger */ -void dac_software_trigger_disable(uint32_t dac_periph); - -/* DAC wave mode configuration */ -/* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); -/* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); -/* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); - -/* DAC concurrent mode configuration */ -/* enable DAC concurrent mode */ -void dac_concurrent_enable(void); -/* disable DAC concurrent mode */ -void dac_concurrent_disable(void); -/* enable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_enable(void); -/* disable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_disable(void); -/* enable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_enable(void); -/* disable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_disable(void); -/* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); - -#endif /* GD32VF103_DAC_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h deleted file mode 100644 index 244ca291b3..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dbg.h +++ /dev/null @@ -1,109 +0,0 @@ -/*! - \file gd32vf103_dbg.h - \brief definitions for the DBG - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_DBG_H -#define GD32VF103_DBG_H - -#include "gd32vf103.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL */ -#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ -#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ -#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ -#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ -#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ -#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */ -#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ -#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ - -/* constants definitions */ -/* debug hold when core is halted */ -typedef enum -{ - DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ - DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ - DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ - DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ - DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ - DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ - DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ - DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ - DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ - DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ - DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ - DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ - DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ -}dbg_periph_enum; - -/* DBG low power mode configurations */ -#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* function declarations */ -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* low power behavior configuration */ -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* peripheral behavior configuration */ -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -#endif /* GD32VF103_DBG_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h deleted file mode 100644 index ceeefe0dc8..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_dma.h +++ /dev/null @@ -1,282 +0,0 @@ -/*! - \file gd32vf103_dma.h - \brief definitions for the DMA - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_DMA_H -#define GD32VF103_DMA_H - -#include "gd32vf103.h" - -/* DMA definitions */ -#define DMA0 (DMA_BASE) /*!< DMA0 base address */ -#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ - -/* registers definitions */ -#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ - -#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ - -#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ - -#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ - -#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ - -#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ - -#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ -#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ -#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ -#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ - -#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ -#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ -#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ -#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL, x=0..6 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT, x=0..6 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR, x=0..6 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR, x=0..6 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA Channel0 */ - DMA_CH1, /*!< DMA Channel1 */ - DMA_CH2, /*!< DMA Channel2 */ - DMA_CH3, /*!< DMA Channel3 */ - DMA_CH4, /*!< DMA Channel4 */ - DMA_CH5, /*!< DMA Channel5 */ - DMA_CH6 /*!< DMA Channel6 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ - -} dma_parameter_struct; - -#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_register address */ -#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U) /*!< read from memory and write to peripheral */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ - -/* memory to memory mode */ -#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ -#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ - -/* function declarations */ -/* DMA deinitialization and initialization functions */ -/* deinitialize DMA a channel registers */ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); -/* initialize the parameters of DMA struct with the default values */ -void dma_struct_para_init(dma_parameter_struct* init_struct); -/* initialize DMA channel */ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); -/* enable DMA circulation mode */ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); - -/* DMA configuration functions */ -/* set DMA peripheral base address */ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set DMA memory base address */ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); - -/* flag and interrupt functions */ -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the flag of a DMA channel */ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* clear the interrupt flag of a DMA channel */ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); - -#endif /* GD32VF103_DMA_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h deleted file mode 100644 index 843ab4c254..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_eclic.h +++ /dev/null @@ -1,62 +0,0 @@ -/*! - \file gd32vf103_eclic.h - \brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller) - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_ECLIC_H -#define GD32VF103_ECLIC_H - -#include "gd32vf103.h" - -/* constants definitions */ -#define ECLIC_PRIGROUP_LEVEL0_PRIO4 0 /*!< 0 bits for level 4 bits for priority */ -#define ECLIC_PRIGROUP_LEVEL1_PRIO3 1 /*!< 1 bits for level 3 bits for priority */ -#define ECLIC_PRIGROUP_LEVEL2_PRIO2 2 /*!< 2 bits for level 2 bits for priority */ -#define ECLIC_PRIGROUP_LEVEL3_PRIO1 3 /*!< 3 bits for level 1 bits for priority */ -#define ECLIC_PRIGROUP_LEVEL4_PRIO0 4 /*!< 4 bits for level 0 bits for priority */ - -#define __SEV eclic_send_event - -/* function declarations */ -/* set the priority group */ -void eclic_priority_group_set(uint32_t prigroup); -/* enable the interrupt request */ -void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority); -/* disable the interrupt request */ -void eclic_irq_disable(uint32_t source); - -/* reset system */ -void eclic_system_reset(void); -/* send event(SEV) */ -void eclic_send_event(void); - -#endif /* GD32VF103_ECLIC_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h deleted file mode 100644 index 1c72014b49..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exmc.h +++ /dev/null @@ -1,126 +0,0 @@ -/*! - \file gd32vf103_exmc.h - \brief definitions for the EXMC - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_EXMC_H -#define GD32VF103_EXMC_H - -#include "gd32vf103.h" - -/* EXMC definitions */ -#define EXMC (EXMC_BASE) /*!< EXMC register base address */ - -/* registers definitions */ -/* NOR/PSRAM */ -#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ -#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ -#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ - -/* bits definitions */ -/* NOR/PSRAM */ -/* EXMC_SNCTLx, x=0 */ -#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ -#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ -#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ -#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ -#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ -#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ -#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ -#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ -#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ - -/* EXMC_SNTCFGx, x=0 */ -#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ -#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ -#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ -#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ - -/* constants definitions */ -/* EXMC NOR/SRAM timing initialize struct */ -typedef struct -{ - uint32_t bus_latency; /*!< configure the bus latency */ - uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ - uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ - uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ -}exmc_norsram_timing_parameter_struct; - -/* EXMC NOR/SRAM initialize struct */ -typedef struct -{ - uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ - uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ - uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */ - uint32_t memory_write; /*!< enable or disable the write operation */ - uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ - uint32_t databus_width; /*!< specifies the databus width of external memory */ - uint32_t memory_type; /*!< specifies the type of external memory */ - uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ - exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */ -}exmc_norsram_parameter_struct; - -/* EXMC register address */ -#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ -#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ - -/* NOR bank memory data bus width */ -#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ -#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ - -/* NOR bank memory type */ -#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ -#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ -#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ - -/* EXMC NOR/SRAM bank region definition */ -#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ - -/* EXMC NWAIT signal polarity configuration */ -#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ -#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ - -/* function declarations */ -/* deinitialize EXMC NOR/SRAM region */ -void exmc_norsram_deinit(uint32_t norsram_region); -/* exmc_norsram_parameter_struct parameter initialize */ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* initialize EXMC NOR/SRAM region */ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); -/* EXMC NOR/SRAM bank enable */ -void exmc_norsram_enable(uint32_t norsram_region); -/* EXMC NOR/SRAM bank disable */ -void exmc_norsram_disable(uint32_t norsram_region); - -#endif /* GD32VF103_EXMC_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h deleted file mode 100644 index 3a0d90901c..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_exti.h +++ /dev/null @@ -1,244 +0,0 @@ -/*! - \file gd32vf103_exti.h - \brief definitions for the EXTI - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_EXTI_H -#define GD32VF103_EXTI_H - -#include "gd32vf103.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ -#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum { - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ -} exti_line_enum; - -/* external interrupt and event */ -typedef enum { - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -} exti_mode_enum; - -/* interrupt trigger mode */ -typedef enum { - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH /*!< EXTI rising edge and falling edge trigger */ -} exti_trig_type_enum; - -/* function declarations */ -/* initialization, EXTI lines configuration functions */ -/* deinitialize the EXTI */ -void exti_deinit(void); -/* enable the configuration of EXTI initialize */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - -/* interrupt & flag functions */ -/* get EXTI lines pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI lines flag when the interrupt flag is set */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI lines pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); -/* enable the EXTI software interrupt event */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable the EXTI software interrupt event */ -void exti_software_interrupt_disable(exti_line_enum linex); - -#endif /* GD32VF103_EXTI_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h deleted file mode 100644 index 2e6693ab76..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fmc.h +++ /dev/null @@ -1,311 +0,0 @@ -/*! - \file gd32vf103_fmc.h - \brief definitions for the FMC - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_FMC_H -#define GD32VF103_FMC_H - -#include "gd32vf103.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option bytes base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ -#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ -#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ -#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ -#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ -#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ -#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ -#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ - -/* FMC_KEY0 */ -#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT0 */ -#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ -#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL0 */ -#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ -#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ -#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ -#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ -#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ - -/* FMC_ADDR0 */ -#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ -#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ -#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ -#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ - -/* FMC_WP */ -#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ - -/* FMC_WSEN */ -#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* define the FMC bit position and its register index offset */ -#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) -#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) -#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) -#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) -#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) -#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) - -/* configuration register */ -#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ -#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ -#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ - -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ -}fmc_state_enum; - -/* FMC interrupt enable */ -typedef enum -{ - FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ - FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ -}fmc_int_enum; - -/* FMC flags */ -typedef enum -{ - FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC busy flag */ - FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC operation error flag bit */ - FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */ - FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */ - FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ -}fmc_flag_enum; - -/* FMC interrupt flags */ -typedef enum -{ - FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */ - FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */ - FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */ -}fmc_interrupt_flag_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* FMC wait state counter */ -#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) -#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ -#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ -#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ - -/* option bytes software/hardware free watch dog timer */ -#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ -#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ - -/* option bytes reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ - -/* option bytes reset or not entering standby mode */ -#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ -#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ - -/* option bytes boot bank value */ -#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ - -#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ - -/* read protect configure */ -#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ -#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ - -/* OB_SPC */ -#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ -#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ - -/* OB_USER */ -#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ -#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ - -/* OB_WP0 */ -#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ - -/* OB_WP1 */ -#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ - -/* OB_WP2 */ -#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ - -/* OB_WP3 */ -#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ - -/* option bytes write protection */ -#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ -#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ -#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ -#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ -#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ -#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ -#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ -#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ -#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ -#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ -#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ -#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ -#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ -#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ -#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ -#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ -#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ -#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ -#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ -#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ -#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ -#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ -#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ -#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ -#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ -#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ -#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ -#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ -#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ -#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ -#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ -#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ -#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ - -/* FMC timeout */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ - -/* FMC BANK address */ -#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ -#define SRAM_SIZE (*(uint16_t *)0x1FFFF7E2U) /*!< SRAM size*/ - -/* function declarations */ -/* FMC main memory programming functions */ -/* set the FMC wait state counter */ -void fmc_wscnt_set(uint32_t wscnt); -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); -/* FMC program a half word at the corresponding address */ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* erase the FMC option byte */ -fmc_state_enum ob_erase(void); -/* enable write protect */ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); -/* configure the option byte security protection */ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc); -/* write the FMC option byte */ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); -/* program option bytes data */ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data); -/* get the FMC option byte user */ -uint8_t ob_user_get(void); -/* get OB_DATA in register FMC_OBSTAT */ -uint16_t ob_data_get(void); -/* get the FMC option byte write protection */ -uint32_t ob_write_protection_get(void); -/* get FMC option byte security protection code value */ -FlagStatus ob_spc_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* check flag is set or not */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC flag */ -void fmc_flag_clear(uint32_t flag); -/* get FMC interrupt flag state */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); -/* clear FMC interrupt flag state */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); -/* return the FMC state */ -fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(uint32_t timeout); - -#endif /* GD32VF103_FMC_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h deleted file mode 100644 index cedfa0fbda..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_fwdgt.h +++ /dev/null @@ -1,104 +0,0 @@ -/*! - \file gd32vf103_fwdgt.h - \brief definitions for the FWDGT - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_FWDGT_H -#define GD32VF103_FWDGT_H - -#include "gd32vf103.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE /*!< FWDGT base address */ - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ - -/* constants definitions */ -/* psc register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC and FWDGT_RLD */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32VF103_FWDGT_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h deleted file mode 100644 index 2583646faa..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_gpio.h +++ /dev/null @@ -1,423 +0,0 @@ -/*! - \file gd32vf103_gpio.h - \brief definitions for the GPIO - - \version 2019-06-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_GPIO_H -#define GD32VF103_GPIO_H - -#include "gd32vf103.h" - -/* GPIOx(x=A,B,C,D,E) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOD (GPIO_BASE + 0x00000C00U) -#define GPIOE (GPIO_BASE + 0x00001000U) - -/* AFIO definitions */ -#define AFIO AFIO_BASE - -/* registers definitions */ - -/* GPIO registers definitions */ -#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ -#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ - -/* AFIO registers definitions */ -#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ -#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ -#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ -#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ -#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ -#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ -#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ - -/* bits definitions */ -/* GPIO_CTL0 */ -#define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */ -#define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */ -#define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */ -#define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */ -#define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */ -#define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */ -#define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */ -#define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */ -#define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */ -#define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */ -#define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */ -#define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */ -#define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */ -#define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */ -#define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */ -#define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */ - -/* GPIO_CTL1 */ -#define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */ -#define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */ -#define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */ -#define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */ -#define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */ -#define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */ -#define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */ -#define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */ -#define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */ -#define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */ -#define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */ -#define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */ -#define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */ -#define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */ -#define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */ -#define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* AFIO_EC */ -#define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */ -#define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */ -#define AFIO_EC_EOE BIT(7) /*!< event output enable */ - -/* AFIO_PCF0 */ -/* memory map and bit definitions for GD32F10X_CL devices */ -#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ -#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ -#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ -#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ -#define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */ -#define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */ -#define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */ -#define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */ -#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ -#define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */ -#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ -#define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */ -#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ -#define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ - -/* AFIO_EXTISS0 */ -#define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */ -#define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */ -#define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */ -#define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */ - -/* AFIO_EXTISS1 */ -#define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */ -#define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */ -#define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */ -#define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */ - -/* AFIO_EXTISS2 */ -#define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */ -#define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */ -#define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */ -#define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */ - -/* AFIO_EXTISS3 */ -#define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */ -#define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */ -#define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */ -#define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */ - -/* AFIO_PCF1 */ -#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* GPIO mode values set */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) -#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) - -/* GPIO mode definitions */ -#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ -#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ -#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ -#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ -#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ -#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ -#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ -#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ - -/* GPIO output max speed value */ -#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ - -/* GPIO event output port definitions */ -#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ -#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ -#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ -#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ -#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ - -/* GPIO output port source definitions */ -#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ -#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ -#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ -#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ -#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ - -/* GPIO event output pin definitions */ -#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ -#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ -#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ -#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ -#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ -#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ -#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ -#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ -#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ -#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ -#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ -#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ -#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ -#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ -#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ -#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ - -/* GPIO output pin source definitions */ -#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ -#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ -#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ -#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ -#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ -#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ -#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ -#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ -#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ -#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ -#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ -#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ -#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ -#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ -#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ -#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */ - -/* GPIO remap definitions */ -#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ -#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ -#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ -#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ -#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ -#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ -#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ -#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ -#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ -#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ -#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ -#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ -#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping */ -#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping */ -#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ -#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping */ -#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping */ -#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ -#define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled */ -#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300400U) /*!< JTAG-DP disabled */ -#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping */ -#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping */ -#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* reset alternate function I/O(AFIO) */ -void gpio_afio_deinit(void); -/* GPIO parameter initialization */ -void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* configure GPIO pin remap */ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); - -/* select GPIO pin exti sources */ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); -/* configure GPIO pin event output */ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); -/* enable GPIO pin event output */ -void gpio_event_output_enable(void); -/* disable GPIO pin event output */ -void gpio_event_output_disable(void); - -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -#endif /* GD32VF103_GPIO_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h deleted file mode 100644 index caba0015b0..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_i2c.h +++ /dev/null @@ -1,342 +0,0 @@ -/*! - \file gd32vf103_i2c.h - \brief definitions for the I2C - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_I2C_H -#define GD32VF103_I2C_H - -#include "gd32vf103.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ - -/* I2C flags */ -typedef enum { - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ -} i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum { - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ -} i2c_interrupt_flag_enum; - -/* I2C interrupt enable or disable */ -typedef enum { - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ -} i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ - -/* I2C dual-address mode switch */ -#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ -#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ - -/* PEC transfer */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ - -/* function declarations */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr); -/* SMBus type selection */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection); -/* configure I2C saddress1 */ -void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr); -/* enable dual-address mode */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); -/* disable dual-address mode */ -void i2c_dualaddr_disable(uint32_t i2c_periph); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); - -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* enable I2C DMA mode */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* software reset I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); - -/* I2C PEC calculation on or off */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); -/* I2C whether to transfer PEC value */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); -/* packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* I2C issue alert through SMBA pin */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); -/* I2C ARP protocol in SMBus switch */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); - -/* check I2C flag is set or not */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* check I2C interrupt flag */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); - -#endif /* GD32VF103_I2C_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h deleted file mode 100644 index 244038127f..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_pmu.h +++ /dev/null @@ -1,125 +0,0 @@ -/*! - \file gd32vf103_pmu.h - \brief definitions for the PMU - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_PMU_H -#define GD32VF103_PMU_H - -#include "gd32vf103.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ - -/* constants definitions */ -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ - -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU registers */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* set PMU mode */ -/* PMU work at sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work at deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work at standby mode */ -void pmu_to_standbymode(uint8_t standbymodecmd); -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(void); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(void); - -/* backup related functions */ -/* enable write access to the registers in backup domain */ -void pmu_backup_write_enable(void); -/* disable write access to the registers in backup domain */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag_reset); - -#endif /* GD32VF103_PMU_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h deleted file mode 100644 index 56afb42ac7..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rcu.h +++ /dev/null @@ -1,720 +0,0 @@ -/*! - \file gd32vf103_rcu.h - \brief definitions for the RCU - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_RCU_H -#define GD32VF103_RCU_H - -#include "gd32vf103.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ - -#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ -#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ -#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ -#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ -#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ -#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ - - -/* bits definitions */ -/* RCU_CTL */ -#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ -#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ -#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ -#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ -#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ - - -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ -#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ -#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ -#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ -#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ -#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ - -/* RCU_INT */ -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ -#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ -#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ -#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ -#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ -#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ -#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ -#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ -#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ -#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ -#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ -#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ -#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ -#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ - -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ -#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ -#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ -#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ -#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ -#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ -#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ -#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ -#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ -#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ -#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ -#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ -#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ -#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ -#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ -#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ -#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ -#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ -#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ -#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ -#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ -#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ -#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -/* RCU_AHBRST */ -#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ - -/* RCU_CFG1 */ -#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ -#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ -#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ -#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ -#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ -#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ -#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register offset */ -/* peripherals enable */ -#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ -#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ -#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ - -/* peripherals reset */ -#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ -#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ -#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ -#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ - -/* clock control */ -#define CTL_REG_OFFSET 0x00U /*!< control register offset */ -#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ - -/* clock stabilization and stuck interrupt */ -#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ - -/* configuration register */ -#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ -#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ - -/* peripheral clock enable */ -typedef enum { - /* AHB peripherals */ - RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ - RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ - RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ - RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ - RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ - /* APB1 peripherals */ - RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ - RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ - RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ - RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ - RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ - RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ - RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ - RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ - RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ - RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ - RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ - RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ - RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ - RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ - RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ - RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ - RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ - /* APB2 peripherals */ - RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ - RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ - RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ - RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ - RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ - RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ - RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ -} rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum { -/* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ -} rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum { - /* AHB peripherals */ - RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ - /* APB1 peripherals */ - RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ - RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ - RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ - RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ - RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ - RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ - RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ - RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ - RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ - RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ - RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ - RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ - RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ - RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ - RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ - /* APB2 peripherals */ - RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ - RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ - RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ - RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ - RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ - RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ -} rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum { - /* clock stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ - RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ - RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ - /* reset source flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ -} rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum { - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ - RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ - RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ -} rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum { - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ - RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ -} rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum { - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ - RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ - RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ -} rcu_int_enum; - -/* oscillator types */ -typedef enum { - RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ - RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ - RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ - RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ -} rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum { - CK_SYS = 0, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ -} rcu_clock_freq_enum; - -/* RCU_CFG0 register bit define */ -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC prescaler select */ -#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ -#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ -#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ -#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ -#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ -#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ -#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ - -/* PLL clock multiplication factor */ -#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ - -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ - -/* USBFS prescaler select */ -#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) -#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ -#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ -#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ -#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ - -/* CKOUT0 clock source selection */ -#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ -#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ -#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ -#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ -#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ -#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ -#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ -#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected */ -#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ -#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ - -/* PREDV0 division factor */ -#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ -#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ -#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ -#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ -#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ -#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ -#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ -#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ -#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ -#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ -#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ -#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ -#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ -#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ -#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ -#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ - -/* PREDV1 division factor */ -#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ -#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ -#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ -#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ -#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ -#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ -#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ -#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ -#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ -#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ -#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ -#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ -#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ -#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ -#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ -#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ - -/* PLL1 clock multiplication factor */ -#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ -#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ -#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ -#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ -#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ -#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ -#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ -#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ -#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ -#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ - -/* PLL2 clock multiplication factor */ -#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) -#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ -#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ -#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ -#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ -#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ -#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ -#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ -#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ -#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ -#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ - - -/* PREDV0 input clock source selection */ -#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ -#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ - -/* I2S1 clock source selection */ -#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ -#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ - -/* I2S2 clock source selection */ -#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ -#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ - - -/* deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ - -/* function declarations */ -/* initialization, peripheral clock enable/disable functions */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP domain */ -void rcu_bkp_reset_enable(void); -/* disable the BKP domain reset */ -void rcu_bkp_reset_disable(void); - -/* clock configuration functions */ -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the CK_OUT0 clock source and divider */ -void rcu_ckout0_config(uint32_t ckout0_src); -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); - -/* configure the PREDV0 division factor and clock source */ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); -/* configure the PREDV1 division factor */ -void rcu_predv1_config(uint32_t predv1_div); -/* configure the PLL1 clock */ -void rcu_pll1_config(uint32_t pll_mul); -/* configure the PLL2 clock */ -void rcu_pll2_config(uint32_t pll_mul); - -/* peripheral clock configuration functions */ -/* configure the ADC division factor */ -void rcu_adc_clock_config(uint32_t adc_psc); -/* configure the USBD/USBFS prescaler factor */ -void rcu_usb_clock_config(uint32_t usb_psc); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); - -/* configure the I2S1 clock source selection */ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source); -/* configure the I2S2 clock source selection */ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source); - -/* interrupt & flag functions */ -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -/* oscillator configuration functions */ -/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -#endif /* GD32VF103_RCU_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h deleted file mode 100644 index e17cdaa62d..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_rtc.h +++ /dev/null @@ -1,148 +0,0 @@ -/*! - \file gd32vf103_rtc.h - \brief definitions for the RTC - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_RTC_H -#define GD32VF103_RTC_H - -#include "gd32vf103.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ -#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ -#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ -#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ -#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ -#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ -#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ -#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ -#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ -#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ - -/* bits definitions */ -/* RTC_INTEN */ -#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ -#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ -#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ - -/* RTC_CTL */ -#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ -#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ -#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ -#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ -#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ -#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ - -/* RTC_PSCH */ -#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ - -/* RTC_PSCL */ -#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ - -/* RTC_DIVH */ -#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ - -/* RTC_DIVL */ -#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ - -/* RTC_CNTH */ -#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ - -/* RTC_CNTL */ -#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ - -/* RTC_ALRMH */ -#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ - -/* RTC_ALRML */ -#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ - -/* constants definitions */ -/* RTC interrupt enable or disable definitions */ -#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ -#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ -#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ - -/* RTC interrupt flag definitions */ -#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ - -/* RTC flag definitions */ -#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ -#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ -#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ -#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ - -/* function declarations */ -/* initialization functions */ -/* enter RTC configuration mode */ -void rtc_configuration_mode_enter(void); -/* exit RTC configuration mode */ -void rtc_configuration_mode_exit(void); -/* set RTC counter value */ -void rtc_counter_set(uint32_t cnt); -/* set RTC prescaler value */ -void rtc_prescaler_set(uint32_t psc); - -/* operation functions */ -/* wait RTC last write operation finished flag set */ -void rtc_lwoff_wait(void); -/* wait RTC registers synchronized flag set */ -void rtc_register_sync_wait(void); -/* set RTC alarm value */ -void rtc_alarm_config(uint32_t alarm); -/* get RTC counter value */ -uint32_t rtc_counter_get(void); -/* get RTC divider value */ -uint32_t rtc_divider_get(void); - -/* flag & interrupt functions */ -/* get RTC flag status */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear RTC flag status */ -void rtc_flag_clear(uint32_t flag); -/* get RTC interrupt flag status */ -FlagStatus rtc_interrupt_flag_get(uint32_t flag); -/* clear RTC interrupt flag status */ -void rtc_interrupt_flag_clear(uint32_t flag); -/* enable RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disable RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); - -#endif /* GD32VF103_RTC_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h deleted file mode 100644 index 29c8180883..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_spi.h +++ /dev/null @@ -1,341 +0,0 @@ -/*! - \file gd32vf103_spi.h - \brief definitions for the SPI - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF10X_SPI_H -#define GD32VF10X_SPI_H - -#include "gd32vf103.h" - -/* SPIx(x=0,1,2) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE -#define SPI2 (SPI_BASE + 0x00000400U) - -/* SPI registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ -#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error bit */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct -{ - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transtype */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescale factor */ -}spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI frame size */ -#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ -#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescale factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ - -/* function declarations */ -/* SPI/I2S deinitialization and initialization functions */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI struct with the default values */ -void spi_struct_para_init(spi_parameter_struct* spi_struct); -/* initialize SPI parameter */ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* initialize I2S parameter */ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* NSS functions */ -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* DMA communication */ -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); - -/* normal mode communication */ -/* configure SPI/I2S data frame format */ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); - -/* SPI TI mode functions */ -/* enable SPI TI mode */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* disable SPI TI mode */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* SPI NSS pulse mode functions */ -/* enable SPI NSS pulse mode */ -void spi_nssp_mode_enable(uint32_t spi_periph); -/* disable SPI NSS pulse mode */ -void spi_nssp_mode_disable(uint32_t spi_periph); -/* flag and interrupt functions */ -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -#endif /* GD32VF103_SPI_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h deleted file mode 100644 index e9b475c37c..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_timer.h +++ /dev/null @@ -1,722 +0,0 @@ -/*! - \file gd32vf103_timer.h - \brief definitions for the TIMER - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_TIMER_H -#define GD32VF103_TIMER_H - -#include "gd32vf103.h" - -/* TIMERx(x=0..13) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER1 (TIMER_BASE + 0x00000000U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER3 (TIMER_BASE + 0x00000800U) -#define TIMER4 (TIMER_BASE + 0x00000C00U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER6 (TIMER_BASE + 0x00001400U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* constants definitions */ -/* TIMER init parameter struct definitions */ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint32_t period; /*!< period value */ - uint16_t clockdivision; /*!< clock division value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions */ -typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint16_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint16_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ -#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ -#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ -#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ -#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ -#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ -#define TIMER_INT_FLAG_BRK TIMER_INT_BRK - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel control update flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ - -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ - - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4)) */ - -/* channel enable state */ -#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ - -/* channel complementary output enable state */ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode */ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ - -/* TIMER input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ -#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ -#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ - -/* TIMERx(x=0..4) write CHxVAL register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ - -/* function declarations */ -/* TIMER timebase */ -/* deinit a timer */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct* initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a timer */ -void timer_enable(uint32_t timer_periph); -/* disable a timer */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); - -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint32_t update); - -/* TIMER DMA and event */ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); - -/* TIMER master and slave mode */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); - -/* TIMER interrupt and flag */ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flag */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flag */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -#endif /* GD32VF103_TIMER_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h deleted file mode 100644 index 5caf7d81f5..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_usart.h +++ /dev/null @@ -1,374 +0,0 @@ -/*! - \file gd32vf103_usart.h - \brief definitions for the USART - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2018, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_USART_H -#define GD32VF103_USART_H - -#include "gd32vf103.h" - -/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ -#define USART1 USART_BASE /*!< USART1 base address */ -#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ -#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ -#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ -#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ - -/* registers definitions */ -#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ -#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ -#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ -#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ -#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ - -/* bits definitions */ -/* USARTx_STAT */ -#define USART_STAT_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ -#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT_TC BIT(6) /*!< transmission complete */ -#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ -#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ - -/* USARTx_DATA */ -#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ - -/* USARTx_CTL0 */ -#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ -#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_UEN BIT(13) /*!< USART enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ -#define USART_CTL1_CLEN BIT(8) /*!< CK length */ -#define USART_CTL1_CPH BIT(9) /*!< CK phase */ -#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* constants definitions */ -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) - -/* register offset */ -#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ -#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ - -/* USART flags */ -typedef enum -{ - /* flags in STAT register */ - USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBDF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLEF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ -}usart_interrupt_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ - -/* USART CK length */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART DMA request for receive configure */ -#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ -#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ - -/* USART DMA request for transmission configure */ -#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ -#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ - -/* USART RTS configure */ -#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ -#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ - -/* USART CTS configure */ -#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ -#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); - -/* USART normal mode communication */ -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* LIN mode enable */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* LIN mode disable */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); -/* send break frame */ -void usart_send_break(uint32_t usart_periph); - -/* half-duplex communication */ -/* half-duplex enable */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* half-duplex disable */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* clock enable */ -void usart_synchronous_clock_enable(uint32_t usart_periph); -/* clock disable */ -void usart_synchronous_clock_disable(uint32_t usart_periph); -/* configure usart synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* guard time value configure in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut); -/* smartcard mode enable */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* smartcard mode disable */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* NACK enable in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* NACK disable in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); - -/* flag functions */ -/* get flag in STAT register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear flag in STAT register */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); - -/* interrupt functions */ -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); -/* clear interrupt flag in STAT register */ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag); -#endif /* GD32VF103_USART_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h deleted file mode 100644 index b972bba458..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Include/gd32vf103_wwdgt.h +++ /dev/null @@ -1,86 +0,0 @@ -/*! - \file gd32vf103_wwdgt.h - \brief definitions for the WWDGT - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_WWDGT_H -#define GD32VF103_WWDGT_H - -#include "gd32vf103.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE /*!< WWDGT base address */ - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); - -#endif /* GD32VF103_WWDGT_H */ diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c deleted file mode 100644 index 8a48676bc4..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_adc.c +++ /dev/null @@ -1,992 +0,0 @@ -/*! - \file gd32vf103_adc.c - \brief ADC driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_adc.h" - -/* discontinuous mode macro*/ -#define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U) - -/* ADC regular channel macro */ -#define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U) -#define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U) -#define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U) -#define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U) - -/* ADC sampling time macro */ -#define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U) -#define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U) -#define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U) - -/* ADC inserted channel macro */ -#define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U) -#define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U) - -/* ADC inserted channel offset macro */ -#define ADC_OFFSET_LENGTH ((uint8_t)3U) -#define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U) - -/*! - \brief reset ADC - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_deinit(uint32_t adc_periph) -{ - switch(adc_periph){ - case ADC0: - /* reset ADC0 */ - rcu_periph_reset_enable(RCU_ADC0RST); - rcu_periph_reset_disable(RCU_ADC0RST); - break; - case ADC1: - /* reset ADC1 */ - rcu_periph_reset_enable(RCU_ADC1RST); - rcu_periph_reset_disable(RCU_ADC1RST); - break; - default: - break; - } -} - -/*! - \brief configure the ADC sync mode - \param[in] mode: ADC mode - only one parameter can be selected which is shown as below: - \arg ADC_MODE_FREE: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode - \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only - \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only - \param[out] none - \retval none -*/ -void adc_mode_config(uint32_t mode) -{ - ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM); - ADC_CTL0(ADC0) |= mode; -} - -/*! - \brief enable or disable ADC special function - \param[in] adc_periph: ADCx, x=0,1 - \param[in] function: the function to config - only one parameter can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (function & ADC_SCAN_MODE)){ - /* enable scan mode */ - ADC_CTL0(adc_periph) |= ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* enable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* enable continuous mode */ - ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE; - } - }else{ - if(0U != (function & ADC_SCAN_MODE)){ - /* disable scan mode */ - ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE; - } - if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){ - /* disable inserted channel group convert automatically */ - ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO; - } - if(0U != (function & ADC_CONTINUOUS_MODE)){ - /* disable continuous mode */ - ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] adc_periph: ADCx, x=0,1 - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: LSB alignment - \arg ADC_DATAALIGN_LEFT: MSB alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment){ - /* MSB alignment */ - ADC_CTL1(adc_periph) |= ADC_CTL1_DAL; - }else{ - /* LSB alignment */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief enable ADC interface - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_enable(uint32_t adc_periph) -{ - if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){ - /* enable ADC */ - ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_disable(uint32_t adc_periph) -{ - /* disable ADC */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_calibration_enable(uint32_t adc_periph) -{ - /* reset the selected ADC1 calibration registers */ - ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){ - } - /* enable ADC calibration process */ - ADC_CTL1(adc_periph) |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){ - } -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief enable DMA request - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(uint32_t adc_periph) -{ - /* enable DMA request */ - ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(uint32_t adc_periph) -{ - /* disable DMA request */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief configure ADC discontinuous mode - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel - \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel, the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) -{ - /* disable discontinuous mode of regular & inserted channel */ - ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* config the number of conversions in discontinuous mode */ - ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - /* enable regular channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - /* enable inserted channel group discontinuous mode */ - ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - /* disable discontinuous mode of regular & inserted channel */ - default: - break; - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure the length of regular channel group */ - ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - case ADC_INSERTED_CHANNEL: - /* configure the length of inserted channel group */ - ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE)); - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] adc_periph: ADCx, x=0,1 - \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint32_t rsq,sampt; - - /* ADC regular sequence config */ - if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){ - /* the regular group sequence rank is smaller than six */ - rsq = ADC_RSQ2(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)); - ADC_RSQ2(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){ - /* the regular group sequence rank is smaller than twelve */ - rsq = ADC_RSQ1(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))); - ADC_RSQ1(adc_periph) = rsq; - }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){ - /* the regular group sequence rank is smaller than sixteen */ - rsq = ADC_RSQ0(adc_periph); - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)))); - /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */ - rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))); - ADC_RSQ0(adc_periph) = rsq; - }else{ - } - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the regular group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the regular group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] adc_periph: ADCx, x=0,1 - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq,sampt; - /* get inserted channel group length */ - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */ - isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH))); - isq |= ((uint32_t)adc_channel << (ADC_INSERTED_CHANNEL_SHIFT_LENGTH-(inserted_length-rank)*ADC_INSERTED_CHANNEL_RANK_LENGTH)); - ADC_ISQ(adc_periph) = isq; - - /* ADC sampling time config */ - if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){ - /* the inserted group sequence rank is smaller than ten */ - sampt = ADC_SAMPT1(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel))); - /* channel sample time set*/ - sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel); - ADC_SAMPT1(adc_periph) = sampt; - }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){ - /* the inserted group sequence rank is smaller than eighteen */ - sampt = ADC_SAMPT0(adc_periph); - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)))); - /* channel sample time set*/ - sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))); - ADC_SAMPT0(adc_periph) = sampt; - }else{ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] adc_periph: ADCx, x=0,1 - \param[in] inserted_channel: insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted channel3 - \param[in] offset: the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); - num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel)); - - if(num <= ADC_OFFSET_LENGTH){ - /* calculate the offset of the register */ - num = num * ADC_OFFSET_SHIFT_LENGTH; - /* config the offset of the selected channels */ - REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief configure ADC external trigger source - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected - for regular channel: - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: TIMER1 CH1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: TIMER3 CH3 event select - \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 - \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: TIMER1 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: TIMER1 CH0 event select - \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select - \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: TIMER3 TRGO event select - \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) -{ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* configure ADC regular group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* configure ADC inserted group external trigger source */ - ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief configure ADC external trigger - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) -{ - if(newvalue){ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* enable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* enable ADC inserted channel group external trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; - } - }else{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* disable ADC regular channel group external trigger */ - ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief enable ADC software trigger - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_channel_group: select the channel group - one or more parameters can be selected which are shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ - /* enable ADC regular channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; - } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ - /* enable ADC inserted channel group software trigger */ - ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] adc_periph: ADCx, x=0,1 - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(uint32_t adc_periph) -{ - return (uint16_t)(ADC_RDATA(adc_periph)); -} - -/*! - \brief read ADC inserted group data register - \param[in] adc_periph: ADCx, x=0,1 - \param[in] inserted_channel: insert channel select - only one parameter can be selected - \arg ADC_INSERTED_CHANNEL_0: inserted Channel0 - \arg ADC_INSERTED_CHANNEL_1: inserted channel1 - \arg ADC_INSERTED_CHANNEL_2: inserted Channel2 - \arg ADC_INSERTED_CHANNEL_3: inserted Channel3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel){ - case ADC_INSERTED_CHANNEL_0: - /* read the data of channel 0 */ - idata = ADC_IDATA0(adc_periph); - break; - case ADC_INSERTED_CHANNEL_1: - /* read the data of channel 1 */ - idata = ADC_IDATA1(adc_periph); - break; - case ADC_INSERTED_CHANNEL_2: - /* read the data of channel 2 */ - idata = ADC_IDATA2(adc_periph); - break; - case ADC_INSERTED_CHANNEL_3: - /* read the data of channel 3 */ - idata = ADC_IDATA3(adc_periph); - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief read the last ADC0 and ADC1 conversion result data in sync mode - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint32_t adc_sync_mode_convert_value_read(void) -{ - /* return conversion value */ - return ADC_RDATA(ADC0); -} - - -/*! - \brief configure ADC analog watchdog single channel - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0) - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - /* analog watchdog channel select */ - ADC_CTL0(adc_periph) |= (uint32_t)adc_channel; - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: - /* regular channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - /* inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - /* regular and inserted channel analog watchdog enable */ - ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_watchdog_disable(uint32_t adc_periph) -{ - ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] adc_periph: ADCx, x=0,1 - \param[in] low_threshold: analog watchdog low threshold, 0..4095 - \param[in] high_threshold: analog watchdog high threshold, 0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold) -{ - ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold); -} - -/*! - \brief get the ADC flag bits - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag) -{ - FlagStatus reval = RESET; - if(ADC_STAT(adc_periph) & adc_flag){ - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag bits - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_flag: the adc flag bits - one or more parameters can be selected which are shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag); -} - -/*! - \brief get the bit state of ADCx software start conversion - \param[in] adc_periph: ADCx, x=0,1 - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWRCST)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the bit state of ADCx software inserted channel start conversion - \param[in] adc_periph: ADCx, x=0,1 - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph) -{ - FlagStatus reval = RESET; - if((uint32_t)RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_SWICST)){ - reval = SET; - } - return reval; -} - -/*! - \brief get the ADC interrupt bits - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_interrupt: the adc interrupt bits - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - /* check the interrupt bits */ - switch(adc_interrupt){ - case ADC_INT_FLAG_WDE: - /* get the ADC analog watchdog interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_WDE; - if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - /* get the ADC end of group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){ - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - /* get the ADC end of inserted group conversion interrupt bits */ - state = ADC_STAT(adc_periph) & ADC_STAT_EOIC; - if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){ - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear the ADC flag - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_interrupt: the adc status flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt) -{ - ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt); -} - -/*! - \brief enable ADC interrupt - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_interrupt: the adc interrupt - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* enable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE; - } - /* enable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE; - } - /* enable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] adc_periph: ADCx, x=0,1 - \param[in] adc_interrupt: the adc interrupt flag - one or more parameters can be selected which are shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt) -{ - /* disable ADC analog watchdog interrupt */ - if(0U != (adc_interrupt & ADC_INT_WDE)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE; - } - /* disable ADC end of group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE; - } - /* disable ADC end of inserted group conversion interrupt */ - if(0U != (adc_interrupt & ADC_INT_EOIC)){ - ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE; - } -} - -/*! - \brief adc resolution config - \param[in] adc_periph: ADCx, x=0,1 - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t adc_periph, uint32_t resolution) -{ - ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_DRES); - ADC_OVSCR(adc_periph) |= (uint32_t)resolution; -} - -/*! - \brief adc oversample mode config - \param[in] adc_periph: ADCx, x=0,1 - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel - are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel - needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio X2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio X4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio X8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio X16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio X32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio X64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio X128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio X256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift,uint8_t ratio) -{ - if(mode){ - ADC_OVSCR(adc_periph) |= (uint32_t)ADC_OVSCR_TOVS; - }else{ - ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_TOVS); - } - /* config the shift and ratio */ - ADC_OVSCR(adc_periph) &= ~((uint32_t)(ADC_OVSCR_OVSR | ADC_OVSCR_OVSS)); - ADC_OVSCR(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief enable ADC oversample mode - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(uint32_t adc_periph) -{ - ADC_OVSCR(adc_periph) |= ADC_OVSCR_OVSEN; -} - -/*! - \brief disable ADC oversample mode - \param[in] adc_periph: ADCx, x=0,1 - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(uint32_t adc_periph) -{ - ADC_OVSCR(adc_periph) &= ~((uint32_t)ADC_OVSCR_OVSEN); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c deleted file mode 100644 index e3b01e4c66..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_bkp.c +++ /dev/null @@ -1,292 +0,0 @@ -/*! - \file gd32vf103_bkp.c - \brief BKP driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_bkp.h" - -/* BKP register bits offset */ -#define BKP_TAMPER_BITS_OFFSET ((uint32_t)8U) - -/*! - \brief reset BKP registers - \param[in] none - \param[out] none - \retval none -*/ -void bkp_deinit(void) -{ - /* reset BKP domain register*/ - rcu_bkp_reset_enable(); - rcu_bkp_reset_disable(); -} - -/*! - \brief write BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[in] data: the data to be write in BKP data register - \param[out] none - \retval none -*/ -void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) -{ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - BKP_DATA10_41(register_number - 1U) = data; - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - BKP_DATA0_9(register_number - 1U) = data; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief read BKP data register - \param[in] register_number: refer to bkp_data_register_enum - only one parameter can be selected which is shown as below: - \arg BKP_DATA_x(x = 0..41): bkp data register number x - \param[out] none - \retval data of BKP data register -*/ -uint16_t bkp_data_read(bkp_data_register_enum register_number) -{ - uint16_t data = 0U; - - /* get the data from the BKP data register */ - if((register_number >= BKP_DATA_10) && (register_number <= BKP_DATA_41)){ - data = BKP_DATA10_41(register_number - 1U); - }else if((register_number >= BKP_DATA_0) && (register_number <= BKP_DATA_9)){ - data = BKP_DATA0_9(register_number - 1U); - }else{ - /* illegal parameters */ - } - return data; -} - -/*! - \brief enable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_COEN; -} - -/*! - \brief disable RTC clock calibration output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_COEN; -} - -/*! - \brief enable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_enable(void) -{ - BKP_OCTL |= (uint16_t)BKP_OCTL_ASOEN; -} - -/*! - \brief disable RTC alarm or second signal output - \param[in] none - \param[out] none - \retval none -*/ -void bkp_rtc_signal_output_disable(void) -{ - BKP_OCTL &= (uint16_t)~BKP_OCTL_ASOEN; -} - -/*! - \brief select RTC output - \param[in] outputsel: RTC output selection - only one parameter can be selected which is shown as below: - \arg RTC_OUTPUT_ALARM_PULSE: RTC alarm pulse is selected as the RTC output - \arg RTC_OUTPUT_SECOND_PULSE: RTC second pulse is selected as the RTC output - \param[out] none - \retval none -*/ -void bkp_rtc_output_select(uint16_t outputsel) -{ - uint16_t ctl = 0U; - - /* configure BKP_OCTL_ROSEL with outputsel */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_ROSEL; - ctl |= outputsel; - BKP_OCTL = ctl; -} - -/*! - \brief set RTC clock calibration value - \param[in] value: RTC clock calibration value - \arg 0x00 - 0x7F - \param[out] none - \retval none -*/ -void bkp_rtc_calibration_value_set(uint8_t value) -{ - uint16_t ctl; - - /* configure BKP_OCTL_RCCV with value */ - ctl = BKP_OCTL; - ctl &= (uint16_t)~BKP_OCTL_RCCV; - ctl |= (uint16_t)OCTL_RCCV(value); - BKP_OCTL = ctl; -} - -/*! - \brief enable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_enable(void) -{ - BKP_TPCTL |= (uint16_t)BKP_TPCTL_TPEN; -} - -/*! - \brief disable tamper detection - \param[in] none - \param[out] none - \retval none -*/ -void bkp_tamper_detection_disable(void) -{ - BKP_TPCTL &= (uint16_t)~BKP_TPCTL_TPEN; -} - -/*! - \brief set tamper pin active level - \param[in] level: tamper active level - only one parameter can be selected which is shown as below: - \arg TAMPER_PIN_ACTIVE_HIGH: the tamper pin is active high - \arg TAMPER_PIN_ACTIVE_LOW: the tamper pin is active low - \param[out] none - \retval none -*/ -void bkp_tamper_active_level_set(uint16_t level) -{ - uint16_t ctl = 0U; - - /* configure BKP_TPCTL_TPAL with level */ - ctl = BKP_TPCTL; - ctl &= (uint16_t)~BKP_TPCTL_TPAL; - ctl |= level; - BKP_TPCTL = ctl; -} - -/*! - \brief enable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_enable(void) -{ - BKP_TPCS |= (uint16_t)BKP_TPCS_TPIE; -} - -/*! - \brief disable tamper interrupt - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_disable(void) -{ - BKP_TPCS &= (uint16_t)~BKP_TPCS_TPIE; -} - -/*! - \brief get tamper flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_flag_get(void) -{ - if(RESET != (BKP_TPCS & BKP_FLAG_TAMPER)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear tamper flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} - -/*! - \brief get tamper interrupt flag state - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus bkp_interrupt_flag_get(void) -{ - if(RESET != (BKP_TPCS & BKP_INT_FLAG_TAMPER)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear tamper interrupt flag state - \param[in] none - \param[out] none - \retval none -*/ -void bkp_interrupt_flag_clear(void) -{ - BKP_TPCS |= (uint16_t)(BKP_INT_FLAG_TAMPER >> BKP_TAMPER_BITS_OFFSET); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_can.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_can.c deleted file mode 100644 index b90131ab60..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_can.c +++ /dev/null @@ -1,989 +0,0 @@ -/*! - \file gd32vf103_can.c - \brief CAN driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_can.h" - -#define CAN_ERROR_HANDLE(s) do{}while(1) - -/*! - \brief deinitialize CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_deinit(uint32_t can_periph) -{ - if(CAN0 == can_periph){ - rcu_periph_reset_enable(RCU_CAN0RST); - rcu_periph_reset_disable(RCU_CAN0RST); - }else{ - rcu_periph_reset_enable(RCU_CAN1RST); - rcu_periph_reset_disable(RCU_CAN1RST); - } -} - -/*! - \brief initialize CAN parameter struct with a default value - \param[in] type: the type of CAN parameter struct - only one parameter can be selected which is shown as below: - \arg CAN_INIT_STRUCT: the CAN initial struct - \arg CAN_FILTER_STRUCT: the CAN filter struct - \arg CAN_TX_MESSAGE_STRUCT: the CAN TX message struct - \arg CAN_RX_MESSAGE_STRUCT: the CAN RX message struct - \param[in] p_struct: the pointer of the specific struct - \param[out] none - \retval none -*/ -void can_struct_para_init(can_struct_type_enum type, void* p_struct) -{ - uint8_t i; - - /* get type of the struct */ - switch(type){ - /* used for can_init() */ - case CAN_INIT_STRUCT: - ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; - ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE; - ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; - ((can_parameter_struct*)p_struct)->prescaler = 0x03FFU; - ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; - ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; - ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; - ((can_parameter_struct*)p_struct)->time_segment_2 = CAN_BT_BS2_1TQ; - ((can_parameter_struct*)p_struct)->time_triggered = DISABLE; - ((can_parameter_struct*)p_struct)->trans_fifo_order = DISABLE; - ((can_parameter_struct*)p_struct)->working_mode = CAN_NORMAL_MODE; - - break; - /* used for can_filter_init() */ - case CAN_FILTER_STRUCT: - ((can_filter_parameter_struct*)p_struct)->filter_bits = CAN_FILTERBITS_32BIT; - ((can_filter_parameter_struct*)p_struct)->filter_enable = DISABLE; - ((can_filter_parameter_struct*)p_struct)->filter_fifo_number = CAN_FIFO0; - ((can_filter_parameter_struct*)p_struct)->filter_list_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_list_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_high = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mask_low = 0x0000U; - ((can_filter_parameter_struct*)p_struct)->filter_mode = CAN_FILTERMODE_MASK; - ((can_filter_parameter_struct*)p_struct)->filter_number = 0U; - - break; - /* used for can_message_transmit() */ - case CAN_TX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_trasnmit_message_struct*)p_struct)->tx_data[i] = 0U; - } - - ((can_trasnmit_message_struct*)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct*)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct*)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct*)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct*)p_struct)->tx_sfid = 0U; - - break; - /* used for can_message_receive() */ - case CAN_RX_MESSAGE_STRUCT: - for(i = 0U; i < 8U; i++){ - ((can_receive_message_struct*)p_struct)->rx_data[i] = 0U; - } - - ((can_receive_message_struct*)p_struct)->rx_dlen = 0U; - ((can_receive_message_struct*)p_struct)->rx_efid = 0U; - ((can_receive_message_struct*)p_struct)->rx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_receive_message_struct*)p_struct)->rx_fi = 0U; - ((can_receive_message_struct*)p_struct)->rx_ft = (uint8_t)CAN_FT_DATA; - ((can_receive_message_struct*)p_struct)->rx_sfid = 0U; - - break; - - default: - CAN_ERROR_HANDLE("parameter is invalid \r\n"); - } -} - -/*! - \brief initialize CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] can_parameter_init: parameters for CAN initializtion - \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE - \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) - \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) - \arg time_segment_2: CAN_BT_BS2_xTQ(1..8) - \arg time_triggered: ENABLE or DISABLE - \arg auto_bus_off_recovery: ENABLE or DISABLE - \arg auto_wake_up: ENABLE or DISABLE - \arg auto_retrans: ENABLE or DISABLE - \arg rec_fifo_overwrite: ENABLE or DISABLE - \arg trans_fifo_order: ENABLE or DISABLE - \arg prescaler: 0x0000 - 0x03FF - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init) -{ - uint32_t timeout = CAN_TIMEOUT; - ErrStatus flag = ERROR; - - /* disable sleep mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - /* enable initialize mode */ - CAN_CTL(can_periph) |= CAN_CTL_IWMOD; - /* wait ACK */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check initialize working success */ - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - /* set the bit timing register */ - CAN_BT(can_periph) = (BT_MODE((uint32_t)can_parameter_init->working_mode) | \ - BT_SJW((uint32_t)can_parameter_init->resync_jump_width) | \ - BT_BS1((uint32_t)can_parameter_init->time_segment_1) | \ - BT_BS2((uint32_t)can_parameter_init->time_segment_2) | \ - BT_BAUDPSC(((uint32_t)(can_parameter_init->prescaler) - 1U))); - - /* time trigger communication mode */ - if(ENABLE == can_parameter_init->time_triggered){ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - } - /* automatic bus-off managment */ - if(ENABLE == can_parameter_init->auto_bus_off_recovery){ - CAN_CTL(can_periph) |= CAN_CTL_ABOR; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ABOR; - } - /* automatic wakeup mode */ - if(ENABLE == can_parameter_init->auto_wake_up){ - CAN_CTL(can_periph) |= CAN_CTL_AWU; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_AWU; - } - /* automatic retransmission mode disable*/ - if(ENABLE == can_parameter_init->auto_retrans){ - CAN_CTL(can_periph) |= CAN_CTL_ARD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_ARD; - } - /* receive fifo overwrite mode */ - if(ENABLE == can_parameter_init->rec_fifo_overwrite){ - CAN_CTL(can_periph) |= CAN_CTL_RFOD; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_RFOD; - } - /* transmit fifo order */ - if(ENABLE == can_parameter_init->trans_fifo_order){ - CAN_CTL(can_periph) |= CAN_CTL_TFO; - }else{ - CAN_CTL(can_periph) &= ~CAN_CTL_TFO; - } - /* disable initialize mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_IWMOD; - timeout = CAN_TIMEOUT; - /* wait the ACK */ - while((CAN_STAT_IWS == (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - /* check exit initialize mode */ - if(0U != timeout){ - flag = SUCCESS; - } - } - CAN_TMI0(can_periph) = 0x0; - CAN_TMI1(can_periph) = 0x0; - CAN_TMI2(can_periph) = 0x0; - CAN_TMP0(can_periph) = 0x0; - CAN_TMP1(can_periph) = 0x0; - CAN_TMP2(can_periph) = 0x0; - CAN_TMDATA00(can_periph) = 0x0; - CAN_TMDATA01(can_periph) = 0x0; - CAN_TMDATA02(can_periph) = 0x0; - CAN_TMDATA10(can_periph) = 0x0; - CAN_TMDATA11(can_periph) = 0x0; - CAN_TMDATA12(can_periph) = 0x0; - - return flag; -} - -/*! - \brief initialize CAN filter - \param[in] can_filter_parameter_init: struct for CAN filter initialization - \arg filter_list_high: 0x0000 - 0xFFFF - \arg filter_list_low: 0x0000 - 0xFFFF - \arg filter_mask_high: 0x0000 - 0xFFFF - \arg filter_mask_low: 0x0000 - 0xFFFF - \arg filter_fifo_number: CAN_FIFO0, CAN_FIFO1 - \arg filter_number: 0 - 27 - \arg filter_mode: CAN_FILTERMODE_MASK, CAN_FILTERMODE_LIST - \arg filter_bits: CAN_FILTERBITS_32BIT, CAN_FILTERBITS_16BIT - \arg filter_enable: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init) -{ - uint32_t val = 0U; - - val = ((uint32_t)1) << (can_filter_parameter_init->filter_number); - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* disable filter */ - CAN_FW(CAN0) &= ~(uint32_t)val; - - /* filter 16 bits */ - if(CAN_FILTERBITS_16BIT == can_filter_parameter_init->filter_bits){ - /* set filter 16 bits */ - CAN_FSCFG(CAN0) &= ~(uint32_t)val; - /* first 16 bits list and first 16 bits mask or first 16 bits list and second 16 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* second 16 bits list and second 16 bits mask or third 16 bits list and fourth 16 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | \ - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS); - } - /* filter 32 bits */ - if(CAN_FILTERBITS_32BIT == can_filter_parameter_init->filter_bits){ - /* set filter 32 bits */ - CAN_FSCFG(CAN0) |= (uint32_t)val; - /* 32 bits list or first 32 bits list */ - CAN_FDATA0(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_list_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_list_low) & CAN_FILTER_MASK_16BITS); - /* 32 bits mask or second 32 bits list */ - CAN_FDATA1(CAN0, can_filter_parameter_init->filter_number) = \ - FDATA_MASK_HIGH((can_filter_parameter_init->filter_mask_high) & CAN_FILTER_MASK_16BITS) | - FDATA_MASK_LOW((can_filter_parameter_init->filter_mask_low) & CAN_FILTER_MASK_16BITS); - } - - /* filter mode */ - if(CAN_FILTERMODE_MASK == can_filter_parameter_init->filter_mode){ - /* mask mode */ - CAN_FMCFG(CAN0) &= ~(uint32_t)val; - }else{ - /* list mode */ - CAN_FMCFG(CAN0) |= (uint32_t)val; - } - - /* filter FIFO */ - if(CAN_FIFO0 == (can_filter_parameter_init->filter_fifo_number)){ - /* FIFO0 */ - CAN_FAFIFO(CAN0) &= ~(uint32_t)val; - }else{ - /* FIFO1 */ - CAN_FAFIFO(CAN0) |= (uint32_t)val; - } - - /* filter working */ - if(ENABLE == can_filter_parameter_init->filter_enable){ - - CAN_FW(CAN0) |= (uint32_t)val; - } - - /* filter lock enable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief set CAN1 fliter start bank number - \param[in] start_bank: CAN1 start bank number - only one parameter can be selected which is shown as below: - \arg (1..27) - \param[out] none - \retval none -*/ -void can1_filter_start_bank(uint8_t start_bank) -{ - /* filter lock disable */ - CAN_FCTL(CAN0) |= CAN_FCTL_FLD; - /* set CAN1 filter start number */ - CAN_FCTL(CAN0) &= ~(uint32_t)CAN_FCTL_HBC1F; - CAN_FCTL(CAN0) |= FCTL_HBC1F(start_bank); - /* filter lock enaable */ - CAN_FCTL(CAN0) &= ~CAN_FCTL_FLD; -} - -/*! - \brief enable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_debug_freeze_enable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) |= CAN_CTL_DFZ; - if(CAN0 == can_periph){ - dbg_periph_enable(DBG_CAN0_HOLD); - }else{ - dbg_periph_enable(DBG_CAN1_HOLD); - } -} - -/*! - \brief disable CAN debug freeze - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_debug_freeze_disable(uint32_t can_periph) -{ - /* set DFZ bit */ - CAN_CTL(can_periph) &= ~CAN_CTL_DFZ; - if(CAN0 == can_periph){ - dbg_periph_disable(DBG_CAN0_HOLD); - }else{ - dbg_periph_disable(DBG_CAN1_HOLD); - } -} - -/*! - \brief enable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_time_trigger_mode_enable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* enable the tcc mode */ - CAN_CTL(can_periph) |= CAN_CTL_TTC; - /* enable time stamp */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) |= CAN_TMP_TSEN; - } -} - -/*! - \brief disable CAN time trigger mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval none -*/ -void can_time_trigger_mode_disable(uint32_t can_periph) -{ - uint8_t mailbox_number; - - /* disable the TCC mode */ - CAN_CTL(can_periph) &= ~CAN_CTL_TTC; - /* reset TSEN bits */ - for(mailbox_number = 0U; mailbox_number < 3U; mailbox_number++){ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_TSEN; - } -} - -/*! - \brief transmit CAN message - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] transmit_message: struct for CAN transmit message - \arg tx_sfid: 0x00000000 - 0x000007FF - \arg tx_efid: 0x00000000 - 0x1FFFFFFF - \arg tx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg tx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg tx_dlenc: 1 - 7 - \arg tx_data[]: 0x00 - 0xFF - \param[out] none - \retval mailbox_number -*/ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message) -{ - uint8_t mailbox_number = CAN_MAILBOX0; - - /* select one empty mailbox */ - if(CAN_TSTAT_TME0 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME0)){ - mailbox_number = CAN_MAILBOX0; - }else if(CAN_TSTAT_TME1 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME1)){ - mailbox_number = CAN_MAILBOX1; - }else if(CAN_TSTAT_TME2 == (CAN_TSTAT(can_periph)&CAN_TSTAT_TME2)){ - mailbox_number = CAN_MAILBOX2; - }else{ - mailbox_number = CAN_NOMAILBOX; - } - /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number){ - return CAN_NOMAILBOX; - } - - CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff){ - /* set transmit mailbox standard identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - }else{ - /* set transmit mailbox extended identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); - } - /* set the data length */ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; - CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; - /* set the data */ - CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); - CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); - /* enable transmission */ - CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; - - return mailbox_number; -} - -/*! - \brief get CAN transmit state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOX(x=0,1,2) - \param[out] none - \retval can_transmit_state_enum -*/ -can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number) -{ - can_transmit_state_enum state = CAN_TRANSMIT_FAILED; - uint32_t val = 0U; - - /* check selected mailbox state */ - switch(mailbox_number){ - /* mailbox0 */ - case CAN_MAILBOX0: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0); - break; - /* mailbox1 */ - case CAN_MAILBOX1: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1); - break; - /* mailbox2 */ - case CAN_MAILBOX2: - val = CAN_TSTAT(can_periph) & (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2); - break; - default: - val = CAN_TRANSMIT_FAILED; - break; - } - - switch(val){ - /* transmit pending */ - case (CAN_STATE_PENDING): - state = CAN_TRANSMIT_PENDING; - break; - /* mailbox0 transmit succeeded */ - case (CAN_TSTAT_MTF0 | CAN_TSTAT_MTFNERR0 | CAN_TSTAT_TME0): - state = CAN_TRANSMIT_OK; - break; - /* mailbox1 transmit succeeded */ - case (CAN_TSTAT_MTF1 | CAN_TSTAT_MTFNERR1 | CAN_TSTAT_TME1): - state = CAN_TRANSMIT_OK; - break; - /* mailbox2 transmit succeeded */ - case (CAN_TSTAT_MTF2 | CAN_TSTAT_MTFNERR2 | CAN_TSTAT_TME2): - state = CAN_TRANSMIT_OK; - break; - /* transmit failed */ - default: - state = CAN_TRANSMIT_FAILED; - break; - } - return state; -} - -/*! - \brief stop CAN transmission - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] mailbox_number - only one parameter can be selected which is shown as below: - \arg CAN_MAILBOXx(x=0,1,2) - \param[out] none - \retval none -*/ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) -{ - if(CAN_MAILBOX0 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ - } - }else if(CAN_MAILBOX1 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ - } - }else if(CAN_MAILBOX2 == mailbox_number){ - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ - } - }else{ - /* illegal parameters */ - } -} - -/*! - \brief CAN receive message - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - \arg CAN_FIFOx(x=0,1) - \param[out] receive_message: struct for CAN receive message - \arg rx_sfid: 0x00000000 - 0x000007FF - \arg rx_efid: 0x00000000 - 0x1FFFFFFF - \arg rx_ff: CAN_FF_STANDARD, CAN_FF_EXTENDED - \arg rx_ft: CAN_FT_DATA, CAN_FT_REMOTE - \arg rx_dlenc: 1 - 7 - \arg rx_data[]: 0x00 - 0xFF - \arg rx_fi: 0 - 27 - \retval none -*/ -void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message) -{ - /* get the frame format */ - receive_message->rx_ff = (uint8_t)(CAN_RFIFOMI_FF & CAN_RFIFOMI(can_periph, fifo_number)); - if(CAN_FF_STANDARD == receive_message->rx_ff){ - /* get standard identifier */ - receive_message->rx_sfid = (uint32_t)(GET_RFIFOMI_SFID(CAN_RFIFOMI(can_periph, fifo_number))); - }else{ - /* get extended identifier */ - receive_message->rx_efid = (uint32_t)(GET_RFIFOMI_EFID(CAN_RFIFOMI(can_periph, fifo_number))); - } - - /* get frame type */ - receive_message->rx_ft = (uint8_t)(CAN_RFIFOMI_FT & CAN_RFIFOMI(can_periph, fifo_number)); - /* filtering index */ - receive_message->rx_fi = (uint8_t)(GET_RFIFOMP_FI(CAN_RFIFOMP(can_periph, fifo_number))); - /* get recevie data length */ - receive_message->rx_dlen = (uint8_t)(GET_RFIFOMP_DLENC(CAN_RFIFOMP(can_periph, fifo_number))); - - /* receive data */ - receive_message -> rx_data[0] = (uint8_t)(GET_RFIFOMDATA0_DB0(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[1] = (uint8_t)(GET_RFIFOMDATA0_DB1(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[2] = (uint8_t)(GET_RFIFOMDATA0_DB2(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[3] = (uint8_t)(GET_RFIFOMDATA0_DB3(CAN_RFIFOMDATA0(can_periph, fifo_number))); - receive_message -> rx_data[4] = (uint8_t)(GET_RFIFOMDATA1_DB4(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[5] = (uint8_t)(GET_RFIFOMDATA1_DB5(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[6] = (uint8_t)(GET_RFIFOMDATA1_DB6(CAN_RFIFOMDATA1(can_periph, fifo_number))); - receive_message -> rx_data[7] = (uint8_t)(GET_RFIFOMDATA1_DB7(CAN_RFIFOMDATA1(can_periph, fifo_number))); - - /* release FIFO */ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else{ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - } -} - -/*! - \brief release FIFO0 - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval none -*/ -void can_fifo_release(uint32_t can_periph, uint8_t fifo_number) -{ - if(CAN_FIFO0 == fifo_number){ - CAN_RFIFO0(can_periph) |= CAN_RFIFO0_RFD0; - }else if(CAN_FIFO1 == fifo_number){ - CAN_RFIFO1(can_periph) |= CAN_RFIFO1_RFD1; - }else{ - /* illegal parameters */ - CAN_ERROR_HANDLE("CAN FIFO NUM is invalid \r\n"); - } -} - -/*! - \brief CAN receive message length - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] fifo_number - only one parameter can be selected which is shown as below: - \arg CAN_FIFOx(x=0,1) - \param[out] none - \retval message length -*/ -uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) -{ - uint8_t val = 0U; - - if(CAN_FIFO0 == fifo_number){ - /* FIFO0 */ - val = (uint8_t)(CAN_RFIFO0(can_periph) & CAN_RFIF_RFL_MASK); - }else if(CAN_FIFO1 == fifo_number){ - /* FIFO1 */ - val = (uint8_t)(CAN_RFIFO1(can_periph) & CAN_RFIF_RFL_MASK); - }else{ - /* illegal parameters */ - } - return val; -} - -/*! - \brief set CAN working mode - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] can_working_mode - only one parameter can be selected which is shown as below: - \arg CAN_MODE_INITIALIZE - \arg CAN_MODE_NORMAL - \arg CAN_MODE_SLEEP - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) -{ - ErrStatus flag = ERROR; - /* timeout for IWS or also for SLPWS bits */ - uint32_t timeout = CAN_TIMEOUT; - - if(CAN_MODE_INITIALIZE == working_mode){ - /* disable sleep mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); - /* set initialize mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ - while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_NORMAL == working_mode){ - /* enter normal mode */ - CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ - while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)){ - timeout--; - } - if(0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else if(CAN_MODE_SLEEP == working_mode){ - /* disable initialize mode */ - CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); - /* set sleep mode */ - CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; - /* wait the acknowledge */ - while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)){ - timeout--; - } - if(CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - }else{ - flag = ERROR; - } - return flag; -} - -/*! - \brief wake up CAN - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus can_wakeup(uint32_t can_periph) -{ - ErrStatus flag = ERROR; - uint32_t timeout = CAN_TIMEOUT; - - /* wakeup */ - CAN_CTL(can_periph) &= ~CAN_CTL_SLPWMOD; - - while((0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0x00U != timeout)){ - timeout--; - } - /* check state */ - if(0U != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)){ - flag = ERROR; - }else{ - flag = SUCCESS; - } - return flag; -} - -/*! - \brief get CAN error type - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval can_error_enum - \arg CAN_ERROR_NONE: no error - \arg CAN_ERROR_FILL: fill error - \arg CAN_ERROR_FORMATE: format error - \arg CAN_ERROR_ACK: ACK error - \arg CAN_ERROR_BITRECESSIVE: bit recessive - \arg CAN_ERROR_BITDOMINANTER: bit dominant error - \arg CAN_ERROR_CRC: CRC error - \arg CAN_ERROR_SOFTWARECFG: software configure -*/ -can_error_enum can_error_get(uint32_t can_periph) -{ - can_error_enum error; - error = CAN_ERROR_NONE; - - /* get error type */ - error = (can_error_enum)(GET_ERR_ERRN(CAN_ERR(can_periph))); - return error; -} - -/*! - \brief get CAN receive error number - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval error number -*/ -uint8_t can_receive_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - /* get error count */ - val = (uint8_t)(GET_ERR_RECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief get CAN transmit error number - \param[in] can_periph - \arg CANx(x=0,1) - \param[out] none - \retval error number -*/ -uint8_t can_transmit_error_number_get(uint32_t can_periph) -{ - uint8_t val; - - val = (uint8_t)(GET_ERR_TECNT(CAN_ERR(can_periph))); - return val; -} - -/*! - \brief enable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) |= interrupt; -} - -/*! - \brief disable CAN interrupt - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] interrupt - one or more parameters can be selected which are shown as below: - \arg CAN_INT_TME: transmit mailbox empty interrupt enable - \arg CAN_INT_RFNE0: receive FIFO0 not empty interrupt enable - \arg CAN_INT_RFF0: receive FIFO0 full interrupt enable - \arg CAN_INT_RFO0: receive FIFO0 overfull interrupt enable - \arg CAN_INT_RFNE1: receive FIFO1 not empty interrupt enable - \arg CAN_INT_RFF1: receive FIFO1 full interrupt enable - \arg CAN_INT_RFO1: receive FIFO1 overfull interrupt enable - \arg CAN_INT_WERR: warning error interrupt enable - \arg CAN_INT_PERR: passive error interrupt enable - \arg CAN_INT_BO: bus-off interrupt enable - \arg CAN_INT_ERRN: error number interrupt enable - \arg CAN_INT_ERR: error interrupt enable - \arg CAN_INT_WU: wakeup interrupt enable - \arg CAN_INT_SLPW: sleep working interrupt enable - \param[out] none - \retval none -*/ -void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt) -{ - CAN_INTEN(can_periph) &= ~interrupt; -} - -/*! - \brief get CAN flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) -{ - /* get flag and interrupt enable state */ - if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN flags, refer to can_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_FLAG_MTE2: mailbox 2 transmit error - \arg CAN_FLAG_MTE1: mailbox 1 transmit error - \arg CAN_FLAG_MTE0: mailbox 0 transmit error - \arg CAN_FLAG_MTF2: mailbox 2 transmit finished - \arg CAN_FLAG_MTF1: mailbox 1 transmit finished - \arg CAN_FLAG_MTF0: mailbox 0 transmit finished - \arg CAN_FLAG_RFO0: receive FIFO0 overfull - \arg CAN_FLAG_RFF0: receive FIFO0 full - \arg CAN_FLAG_RFO1: receive FIFO1 overfull - \arg CAN_FLAG_RFF1: receive FIFO1 full - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval none -*/ -void can_flag_clear(uint32_t can_periph, can_flag_enum flag) -{ - CAN_REG_VAL(can_periph, flag) = BIT(CAN_BIT_POS(flag)); -} - -/*! - \brief get CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - uint32_t ret1 = RESET; - uint32_t ret2 = RESET; - - /* get the staus of interrupt flag */ - ret1 = CAN_REG_VALS(can_periph, flag) & BIT(CAN_BIT_POS0(flag)); - /* get the staus of interrupt enale bit */ - ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear CAN interrupt flag state - \param[in] can_periph - \arg CANx(x=0,1) - \param[in] flag: CAN interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg CAN_INT_FLAG_SLPIF: status change interrupt flag of sleep working mode entering - \arg CAN_INT_FLAG_WUIF: status change interrupt flag of wakeup from sleep working mode - \arg CAN_INT_FLAG_ERRIF: error interrupt flag - \arg CAN_INT_FLAG_MTF2: mailbox 2 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF1: mailbox 1 transmit finished interrupt flag - \arg CAN_INT_FLAG_MTF0: mailbox 0 transmit finished interrupt flag - \arg CAN_INT_FLAG_RFO0: receive FIFO0 overfull interrupt flag - \arg CAN_INT_FLAG_RFF0: receive FIFO0 full interrupt flag - \arg CAN_INT_FLAG_RFO1: receive FIFO1 overfull interrupt flag - \arg CAN_INT_FLAG_RFF1: receive FIFO1 full interrupt flag - \arg CAN_FLAG_BOERR: bus-off error - \arg CAN_FLAG_PERR: passive error - \arg CAN_FLAG_WERR: warning error - \param[out] none - \retval none -*/ -void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag) -{ - CAN_REG_VALS(can_periph, flag) = BIT(CAN_BIT_POS0(flag)); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c deleted file mode 100644 index 5753485a58..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_crc.c +++ /dev/null @@ -1,127 +0,0 @@ -/*! - \file gd32vf103_crc.c - \brief CRC driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_crc.h" - -#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU) -#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U) - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_DATA = CRC_DATA_RESET_VALUE; - CRC_FDATA = CRC_FDATA_RESET_VALUE; - CRC_CTL = (uint32_t)CRC_CTL_RST; -} - -/*! - \brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the value of the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the value of the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write data to the free data register - \param[in] free_data: specified 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief calculate the CRC value of a 32-bit data - \param[in] sdata: specified 32-bit data - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_single_data_calculate(uint32_t sdata) -{ - CRC_DATA = sdata; - return (CRC_DATA); -} - -/*! - \brief calculate the CRC value of an array of 32-bit values - \param[in] array: pointer to an array of 32-bit values - \param[in] size: size of the array - \param[out] none - \retval 32-bit value calculated by CRC -*/ -uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size) -{ - uint32_t index; - for(index = 0U; index < size; index++){ - CRC_DATA = array[index]; - } - return (CRC_DATA); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c deleted file mode 100644 index 4ec51bf960..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dac.c +++ /dev/null @@ -1,537 +0,0 @@ -/*! - \file gd32vf103_dac.c - \brief DAC driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_dac.h" - -/* DAC register bit offset */ -#define DAC1_REG_OFFSET ((uint32_t)16U) -#define DH_12BIT_OFFSET ((uint32_t)16U) -#define DH_8BIT_OFFSET ((uint32_t)8U) - -/*! - \brief deinitialize DAC - \param[in] none - \param[out] none - \retval none -*/ -void dac_deinit(void) -{ - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); -} - -/*! - \brief enable DAC - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DEN0; - }else{ - DAC_CTL |= DAC_CTL_DEN1; - } -} - -/*! - \brief disable DAC - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DEN1; - } -} - -/*! - \brief enable DAC DMA function - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_dma_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDMAEN0; - }else{ - DAC_CTL |= DAC_CTL_DDMAEN1; - } -} - -/*! - \brief disable DAC DMA function - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_dma_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDMAEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DDMAEN1; - } -} - -/*! - \brief enable DAC output buffer - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DBOFF0; - }else{ - DAC_CTL &= ~DAC_CTL_DBOFF1; - } -} - -/*! - \brief disable DAC output buffer - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_output_buffer_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DBOFF0; - }else{ - DAC_CTL |= DAC_CTL_DBOFF1; - } -} - -/*! - \brief get DAC output value - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval DAC output data -*/ -uint16_t dac_output_value_get(uint32_t dac_periph) -{ - uint16_t data = 0U; - if(DAC0 == dac_periph){ - /* store the DAC0 output value */ - data = (uint16_t)DAC0_DO; - }else{ - /* store the DAC1 output value */ - data = (uint16_t)DAC1_DO; - } - return data; -} - -/*! - \brief set the DAC specified data holding register value - \param[in] dac_periph: DACx(x = 0,1) - \param[in] dac_align: data alignment - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8 bit alignment - \arg DAC_ALIGN_12B_R: data right 12 bit alignment - \arg DAC_ALIGN_12B_L: data left 12 bit alignment - \param[in] data: data to be loaded - \param[out] none - \retval none -*/ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) -{ - if(DAC0 == dac_periph){ - switch(dac_align){ - /* data right 12 bit alignment */ - case DAC_ALIGN_12B_R: - DAC0_R12DH = data; - break; - /* data left 12 bit alignment */ - case DAC_ALIGN_12B_L: - DAC0_L12DH = data; - break; - /* data right 8 bit alignment */ - case DAC_ALIGN_8B_R: - DAC0_R8DH = data; - break; - default: - break; - } - }else{ - switch(dac_align){ - /* data right 12 bit alignment */ - case DAC_ALIGN_12B_R: - DAC1_R12DH = data; - break; - /* data left 12 bit alignment */ - case DAC_ALIGN_12B_L: - DAC1_L12DH = data; - break; - /* data right 8 bit alignment */ - case DAC_ALIGN_8B_R: - DAC1_R8DH = data; - break; - default: - break; - } - } -} - -/*! - \brief enable DAC trigger - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DTEN0; - }else{ - DAC_CTL |= DAC_CTL_DTEN1; - } -} - -/*! - \brief disable DAC trigger - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTEN0; - }else{ - DAC_CTL &= ~DAC_CTL_DTEN1; - } -} - -/*! - \brief set DAC trigger source - \param[in] dac_periph: DACx(x = 0,1) - \param[in] triggersource: external triggers of DAC - only one parameter can be selected which is shown as below: - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO - \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO - \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event - \arg DAC_TRIGGER_SOFTWARE: software trigger - \param[out] none - \retval none -*/ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; - }else{ - /* configure DAC1 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC software trigger - \param[in] dac_periph: DACx(x = 0,1) - \retval none -*/ -void dac_software_trigger_enable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; - }else{ - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; - } -} - -/*! - \brief configure DAC wave mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] wave_mode: noise wave mode - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_DISABLE: wave disable - \arg DAC_WAVE_MODE_LFSR: LFSR noise mode - \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode - \param[out] none - \retval none -*/ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM0; - DAC_CTL |= wave_mode; - }else{ - /* configure DAC1 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC wave bit width - \param[in] dac_periph: DACx(x = 0,1) - \param[in] bit_width: noise wave bit width - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= bit_width; - }else{ - /* configure DAC1 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (bit_width << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC LFSR noise mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode - only one parameter can be selected which is shown as below: - \arg DAC_LFSR_BIT0: unmask the LFSR bit0 - \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] - \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0] - \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0] - \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0] - \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0] - \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0] - \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0] - \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0] - \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0] - \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0] - \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0] - \param[out] none - \retval none -*/ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= unmask_bits; - }else{ - /* configure DAC1 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC triangle noise mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] amplitude: triangle amplitude in DAC triangle noise mode - only one parameter can be selected which is shown as below: - \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 - \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 - \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7 - \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15 - \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31 - \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63 - \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127 - \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255 - \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511 - \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023 - \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047 - \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095 - \param[out] none - \retval none -*/ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= amplitude; - }else{ - /* configure DAC1 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (amplitude << DAC1_REG_OFFSET); - } -} - -/*! - \brief enable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL |= (ctl); -} - -/*! - \brief disable DAC concurrent mode - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL &= (~ctl); -} - -/*! - \brief enable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_enable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); -} - -/*! - \brief disable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_disable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT &= (~swt); -} - -/*! - \brief enable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_enable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL &= (~ctl); -} - -/*! - \brief disable DAC concurrent buffer function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_output_buffer_disable(void) -{ - uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL |= (ctl); -} - -/*! - \brief set DAC concurrent mode data holding register value - \param[in] dac_align: data alignment - only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded - \param[out] none - \retval none -*/ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) -{ - uint32_t data = 0U; - switch(dac_align){ - /* data right 12b alignment */ - case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_R12DH = data; - break; - /* data left 12b alignment */ - case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_L12DH = data; - break; - /* data right 8b alignment */ - case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; - DACC_R8DH = data; - break; - default: - break; - } -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c deleted file mode 100644 index 2e0dfe5277..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dbg.c +++ /dev/null @@ -1,110 +0,0 @@ -/*! - \file gd32vf103_dbg.c - \brief DBG driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_dbg.h" - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - one or more parameters can be selected which are shown as below: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1): hold CANx counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_CTL |= (uint32_t)dbg_periph; -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: refer to dbg_periph_enum - one or more parameters can be selected which are shown as below: - \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted - \arg DBG_CANx_HOLD (x=0,1): hold CAN0 counter when core is halted - \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted - \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6): hold TIMERx counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_CTL &= ~(uint32_t)dbg_periph; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c deleted file mode 100644 index 0d2c12c8fb..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_dma.c +++ /dev/null @@ -1,731 +0,0 @@ -/*! - \file gd32vf103_dma.c - \brief DMA driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_dma.h" - -#define DMA_WRONG_HANDLE while(1){} - -/* check whether peripheral matches channels or not */ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx); - -/*! - \brief deinitialize DMA a channel registers - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is deinitialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* disable DMA a channel */ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_struct_para_init(dma_parameter_struct* init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE; - init_struct->number = 0U; - init_struct->direction = DMA_PERIPHERAL_TO_MEMORY; - init_struct->priority = DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel is initialized - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT, DMA_PERIPHERAL_WIDTH_16BIT, DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE, DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT, DMA_MEMORY_WIDTH_16BIT, DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE, DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY, DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW, DMA_PRIORITY_MEDIUM, DMA_PRIORITY_HIGH, DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* configure peripheral base address */ - DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width and priority */ - ctl = DMA_CHCTL(dma_periph, channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); - DMA_CHCTL(dma_periph, channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc){ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; - }else{ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - }else{ - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set peripheral base address - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHPADDR(dma_periph, channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set memory base address - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHMADDR(dma_periph, channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] number: the number of remaining data to be transferred by the DMA - \param[out] none - \retval none -*/ -void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval uint32_t: the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - return (uint32_t)DMA_CHCNT(dma_periph, channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] priority: priority Level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] mwidth: transfer data width of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief configure transfer data size of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] pwidth: transfer data width of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(dma_periph, channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(dma_periph, channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - if(DMA_PERIPHERAL_TO_MEMORY == direction){ - DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - if(RESET != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))){ - reval = SET; - }else{ - reval = RESET; - } - - return reval; -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch(flag){ - case DMA_INT_FLAG_FTF: - /* check whether the full transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - /* check whether the half transfer finish interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - /* check whether the error interrupt flag is set and enabled */ - interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE; - break; - default: - DMA_WRONG_HANDLE - } - - /* when the interrupt flag is set and enabled, return SET */ - if(interrupt_flag && interrupt_enable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear DMA a channel flag - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: full transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish interrupt flag of channel - \arg DMA_INT_FLAG_ERR: error interrupt flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to enbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA0: DMA_CHx(x=0..6), DMA1: DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to disbale - one or more parameters can be selected which are shown as below - \arg DMA_INT_FTF: channel full transfer finish interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_ERR: channel error interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source) -{ - if(ERROR == dma_periph_and_channel_check(dma_periph, channelx)){ - DMA_WRONG_HANDLE - } - - DMA_CHCTL(dma_periph, channelx) &= ~source; -} - -/*! - \brief check whether peripheral and channels match - \param[in] dma_periph: DMAx(x=0,1) - \arg DMAx(x=0,1) - \param[in] channelx: specify which DMA channel - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..6) - \param[out] none - \retval none -*/ -static ErrStatus dma_periph_and_channel_check(uint32_t dma_periph, dma_channel_enum channelx) -{ - ErrStatus val = SUCCESS; - - if(DMA1 == dma_periph){ - /* for DMA1, the channel is from DMA_CH0 to DMA_CH4 */ - if(channelx > DMA_CH4){ - val = ERROR; - } - } - - return val; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c deleted file mode 100644 index d4385d6363..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_eclic.c +++ /dev/null @@ -1,99 +0,0 @@ -/*! - \file gd32vf103_eclic.c - \brief ECLIC(Enhancement Core-Local Interrupt Controller) driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_eclic.h" -#include "riscv_encoding.h" - -#define REG_DBGMCU2 ((uint32_t)0xE0042008) -#define REG_DBGMCU2EN ((uint32_t)0xE004200C) - -/*! - \brief set the priority group - \param[in] prigroup: specify the priority group - \arg ECLIC_PRIGROUP_LEVEL0_PRIO4 - \arg ECLIC_PRIGROUP_LEVEL1_PRIO3 - \arg ECLIC_PRIGROUP_LEVEL2_PRIO2 - \arg ECLIC_PRIGROUP_LEVEL3_PRIO1 - \arg ECLIC_PRIGROUP_LEVEL4_PRIO0 - \param[out] none - \retval none -*/ -void eclic_priority_group_set(uint32_t prigroup) { - eclic_set_nlbits(prigroup); -} - -/*! - \brief enable the interrupt request - \param[in] source: interrupt request, detailed in IRQn_Type - \param[in] level: the level needed to set (maximum is 16) - \param[in] priority: the priority needed to set (maximum is 16) - \param[out] none - \retval none -*/ -void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority) { - eclic_enable_interrupt(source); - eclic_set_int_level(source, level); - eclic_set_int_priority(source, priority); -} - -/*! - \brief disable the interrupt request - \param[in] source: interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void eclic_irq_disable(uint32_t source) { - eclic_disable_interrupt(source); -} - -/*! - \brief reset system - \param[in] none - \param[out] none - \retval none -*/ -void eclic_system_reset(void) { - REG32(REG_DBGMCU2EN) = 0x4b5a6978; - REG32(REG_DBGMCU2) = 0x1; -} - -/*! - \brief send event(SEV) - \param[in] none - \param[out] none - \retval none -*/ -void eclic_send_event(void) { - set_csr(0x812, 0x1); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c deleted file mode 100644 index d414e078e0..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exmc.c +++ /dev/null @@ -1,164 +0,0 @@ -/*! - \file gd32vf103_exmc.c - \brief EXMC driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_exmc.h" - -/* EXMC bank0 register reset value */ -#define BANK0_SNCTL0_REGION_RESET ((uint32_t)0x000030DAU) -#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU) - -/* EXMC register bit offset */ -#define SNCTL_NRMUX_OFFSET ((uint32_t)1U) -#define SNCTL_WREN_OFFSET ((uint32_t)12U) -#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U) -#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U) - -#define SNTCFG_AHLD_OFFSET ((uint32_t)4U) -#define SNTCFG_DSET_OFFSET ((uint32_t)8U) -#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U) - -/*! - \brief deinitialize EXMC NOR/SRAM region - \param[in] norsram_region: select the region of bank0 - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) - \param[out] none - \retval none -*/ -void exmc_norsram_deinit(uint32_t norsram_region) -{ - /* reset the registers */ - if(EXMC_BANK0_NORSRAM_REGION0 == norsram_region){ - EXMC_SNCTL(norsram_region) = BANK0_SNCTL0_REGION_RESET; - } - - EXMC_SNTCFG(norsram_region) = BANK0_SNTCFG_RESET; -} - -/*! - \brief initialize the structure exmc_norsram_parameter_struct - \param[in] none - \param[out] exmc_norsram_init_struct: the initialized structure exmc_norsram_parameter_struct pointer - \retval none -*/ -void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - /* configure the structure with default value */ - exmc_norsram_init_struct->norsram_region = EXMC_BANK0_NORSRAM_REGION0; - exmc_norsram_init_struct->address_data_mux = ENABLE; - exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_SRAM; - exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B; - exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW; - exmc_norsram_init_struct->memory_write = ENABLE; - exmc_norsram_init_struct->nwait_signal = ENABLE; - exmc_norsram_init_struct->asyn_wait = DISABLE; - - /* read/write timing configure */ - exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU; - exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU; - exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU; -} - -/*! - \brief initialize EXMC NOR/SRAM region - \param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter - norsram_region: EXMC_BANK0_NORSRAM_REGIONx,x=0 - asyn_wait: ENABLE or DISABLE - nwait_signal: ENABLE or DISABLE - memory_write: ENABLE or DISABLE - nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH - databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B - memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR - address_data_mux: ENABLE - read_write_timing: structure exmc_norsram_timing_parameter_struct set the time - \param[out] none - \retval none -*/ -void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct) -{ - uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U; - - /* get the register value */ - snctl = EXMC_SNCTL(exmc_norsram_init_struct->norsram_region); - - /* clear relative bits */ - snctl &= ((uint32_t)~(EXMC_SNCTL_NREN | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_NRWTPOL | - EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_ASYNCWAIT | EXMC_SNCTL_NRMUX)); - - snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) | - exmc_norsram_init_struct->memory_type | - exmc_norsram_init_struct->databus_width | - exmc_norsram_init_struct->nwait_polarity | - (exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) | - (exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) | - (exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET); - - sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )| - (((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) | - (((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) | - (((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT ); - - /* nor flash access enable */ - if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){ - snctl |= (uint32_t)EXMC_SNCTL_NREN; - } - - /* configure the registers */ - EXMC_SNCTL(exmc_norsram_init_struct->norsram_region) = snctl; - EXMC_SNTCFG(exmc_norsram_init_struct->norsram_region) = sntcfg; -} - -/*! - \brief enable EXMC NOR/PSRAM bank region - \param[in] norsram_region: specify the region of NOR/PSRAM bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) - \param[out] none - \retval none -*/ -void exmc_norsram_enable(uint32_t norsram_region) -{ - EXMC_SNCTL(norsram_region) |= (uint32_t)EXMC_SNCTL_NRBKEN; -} - -/*! - \brief disable EXMC NOR/PSRAM bank region - \param[in] norsram_region: specify the region of NOR/PSRAM bank - \arg EXMC_BANK0_NORSRAM_REGIONx(x=0) - \param[out] none - \retval none -*/ -void exmc_norsram_disable(uint32_t norsram_region) -{ - EXMC_SNCTL(norsram_region) &= ~(uint32_t)EXMC_SNCTL_NRBKEN; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c deleted file mode 100644 index 4833b213bd..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_exti.c +++ /dev/null @@ -1,252 +0,0 @@ -/*! - \file gd32vf103_exti.c - \brief EXTI driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_exti.h" - -#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U) - -/*! - \brief deinitialize the EXTI - \param[in] none - \param[out] none - \retval none - */ -void exti_deinit(void) -{ - /* reset the value of all the EXTI registers */ - EXTI_INTEN = EXTI_REG_RESET_VALUE; - EXTI_EVEN = EXTI_REG_RESET_VALUE; - EXTI_RTEN = EXTI_REG_RESET_VALUE; - EXTI_FTEN = EXTI_REG_RESET_VALUE; - EXTI_SWIEV = EXTI_REG_RESET_VALUE; -} - -/*! - \brief initialize the EXTI - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling edge trigger - \arg EXTI_TRIG_BOTH: rising edge and falling edge trigger - \param[out] none - \retval none - */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t) linex; - EXTI_EVEN &= ~(uint32_t) linex; - EXTI_RTEN &= ~(uint32_t) linex; - EXTI_FTEN &= ~(uint32_t) linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch (mode) { - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t) linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t) linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch (trig_type) { - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t) linex; - EXTI_FTEN &= ~(uint32_t) linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t) linex; - EXTI_FTEN |= (uint32_t) linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t) linex; - EXTI_FTEN |= (uint32_t) linex; - break; - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t) linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t) linex; -} - -/*! - \brief disable the interrupt from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t) linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t) linex; -} - -/*! - \brief get EXTI lines flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if (RESET != (EXTI_PD & (uint32_t) linex)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t) linex; -} - -/*! - \brief get EXTI lines flag when the interrupt flag is set - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - uint32_t flag_left, flag_right; - - flag_left = EXTI_PD & (uint32_t) linex; - flag_right = EXTI_INTEN & (uint32_t) linex; - - if ((RESET != flag_left) && (RESET != flag_right)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear EXTI lines pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t) linex; -} - -/*! - \brief enable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t) linex; -} - -/*! - \brief disable EXTI software interrupt event - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..18): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t) linex; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c deleted file mode 100644 index c219a79617..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fmc.c +++ /dev/null @@ -1,649 +0,0 @@ -/*! - \file gd32vf103_fmc.c - \brief FMC driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_fmc.h" - -/*! - \brief set the wait state counter value - \param[in] wscnt£ºwait state counter value - \arg WS_WSCNT_0: FMC 0 wait state - \arg WS_WSCNT_1: FMC 1 wait state - \arg WS_WSCNT_2: FMC 2 wait state - \param[out] none - \retval none - */ -void fmc_wscnt_set(uint32_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief unlock the main FMC operation - \param[in] none - \param[out] none - \retval none - */ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){ - /* write the FMC unlock key */ - FMC_KEY0 = UNLOCK_KEY0; - FMC_KEY0 = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - \param[in] none - \param[out] none - \retval none - */ -void fmc_lock(void) -{ - /* set the LK bit */ - FMC_CTL0 |= FMC_CTL0_LK; -} - - -/*! - \brief FMC erase page - \param[in] page_address: the page address to be erased. - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state; - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* if the last operation is completed, start page erase */ - if (FMC_READY == fmc_state) { - FMC_CTL0 |= FMC_CTL0_PER; - FMC_ADDR0 = page_address; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PER bit */ - FMC_CTL0 &= ~FMC_CTL0_PER; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief FMC erase whole chip - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state; - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* start whole chip erase */ - FMC_CTL0 |= FMC_CTL0_MER; - FMC_CTL0 |= FMC_CTL0_START; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the MER bit */ - FMC_CTL0 &= ~FMC_CTL0_MER; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief FMC program a word at the corresponding address - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - /* return the FMC state */ - return fmc_state; -} -/* - \brief FMC program a half word at the corresponding address - \param[in] address: address to program - \param[in] data: halfword to program - \param[out] none - \retval state of FMC, refer to fmc_state_enum -*/ -fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data) -{ - fmc_state_enum fmc_state = FMC_READY; - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the PG bit to start program */ - FMC_CTL0 |= FMC_CTL0_PG; - REG16(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - /* reset the PG bit */ - FMC_CTL0 &= ~FMC_CTL0_PG; - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - \param[in] none - \param[out] none - \retval none - */ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){ - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } - - /* wait until OBWEN bit is set by hardware */ - while (RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)) { - } -} - -/*! - \brief lock the option byte operation - \param[in] none - \param[out] none - \retval none - */ -void ob_lock(void) -{ - /* reset the OBWEN bit */ - FMC_CTL0 &= ~FMC_CTL0_OBWEN; -} - -/*! - \brief erase the FMC option byte - unlock the FMC_CTL0 and option byte before calling this function - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum ob_erase(void) -{ - uint16_t temp_spc = FMC_NSPC; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* check the option byte security protection value */ - if(RESET != ob_spc_get()){ - temp_spc = FMC_USPC; - } - - if(FMC_READY == fmc_state){ - - /* start erase the option byte */ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - /* no security protection */ - OB_SPC = (uint16_t) temp_spc; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable write protection - \param[in] ob_wp: specify sector to be write protected, set the bit to 1 if - you want to protect the corresponding pages. meanwhile, sector - macro could used to set specific sector write protected. - one or more parameters can be selected which are shown as below: - \arg OB_WPx(x = 0..31): write protect specify sector - \arg OB_WP_ALL: write protect all sector - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) -{ - uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - ob_wp = (uint32_t) (~ob_wp); - temp_wp0 = (uint16_t) (ob_wp & OB_WP0_WP0); - temp_wp1 = (uint16_t) ((ob_wp & OB_WP1_WP1) >> 8U); - temp_wp2 = (uint16_t) ((ob_wp & OB_WP2_WP2) >> 16U); - temp_wp3 = (uint16_t) ((ob_wp & OB_WP3_WP3) >> 24U); - - if(FMC_READY == fmc_state){ - - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - if(0xFFU != temp_wp0){ - OB_WP0 = temp_wp0; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){ - OB_WP1 = temp_wp1; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){ - OB_WP2 = temp_wp2; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){ - OB_WP3 = temp_wp3; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection - only one parameter can be selected which is shown as below: - \arg FMC_NSPC: no security protection - \arg FMC_USPC: under security protection - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum ob_security_protection_config(uint8_t ob_spc) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - FMC_CTL0 |= FMC_CTL0_OBER; - FMC_CTL0 |= FMC_CTL0_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - - /* start the option byte program */ - FMC_CTL0 |= FMC_CTL0_OBPG; - - OB_SPC = (uint16_t) ob_spc; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if (FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - }else{ - if (FMC_TOERR != fmc_state) { - /* reset the OBER bit */ - FMC_CTL0 &= ~FMC_CTL0_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option byte - \param[in] ob_fwdgt: option byte watchdog value - \arg OB_FWDGT_SW: software free watchdog - \arg OB_FWDGT_HW: hardware free watchdog - \param[in] ob_deepsleep: option byte deepsleep reset value - \arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode - \arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode - \param[in] ob_stdby:option byte standby reset value - \arg OB_STDBY_NRST: no reset when entering standby mode - \arg OB_STDBY_RST: generate a reset instead of entering standby mode - \param[in] ob_boot: specifies the option byte boot bank value - \arg OB_BOOT_B0: boot from bank0 - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot) -{ - fmc_state_enum fmc_state = FMC_READY; - uint8_t temp; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit*/ - FMC_CTL0 |= FMC_CTL0_OBPG; - - temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK); - OB_USER = (uint16_t) temp; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program option bytes data - \param[in] address: the option bytes address to be programmed - \param[in] data: the byte to be programmed - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum ob_data_program(uint32_t address, uint8_t data) { - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state){ - /* set the OBPG bit */ - FMC_CTL0 |= FMC_CTL0_OBPG; - REG16(address) = data; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state){ - /* reset the OBPG bit */ - FMC_CTL0 &= ~FMC_CTL0_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get the FMC user option byte - \param[in] none - \param[out] none - \retval the FMC user option byte values - */ -uint8_t ob_user_get(void) -{ - /* return the FMC user option byte value */ - return (uint8_t) (FMC_OBSTAT >> 2U); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data - */ -uint16_t ob_data_get(void) -{ - return (uint16_t) (FMC_OBSTAT >> 10U); -} - -/*! - \brief get the FMC option byte write protection - \param[in] none - \param[out] none - \retval the FMC write protection option byte value - */ -uint32_t ob_write_protection_get(void) -{ - /* return the FMC write protection option byte value */ - return FMC_WP; -} - -/*! - \brief get the FMC option byte security protection - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus ob_spc_get(void) -{ - FlagStatus spc_state = RESET; - - if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){ - spc_state = SET; - }else{ - spc_state = RESET; - } - return spc_state; -} - -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: enable FMC end of program interrupt - \arg FMC_INT_ERR: enable FMC error interrupt - \param[out] none - \retval none - */ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - only one parameter can be selected which is shown as below: - \arg FMC_INT_END: enable FMC end of program interrupt - \arg FMC_INT_ERR: enable FMC error interrupt - \param[out] none - \retval none - */ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt)); -} - -/*! - \brief check flag is set or not - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag bit - \arg FMC_FLAG_PGERR: FMC operation error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \arg FMC_FLAG_OBERR: FMC option bytes read error flag bit - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus fmc_flag_get(uint32_t flag) -{ - if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the FMC flag - \param[in] flag: clear FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC operation error flag bit - \arg FMC_FLAG_WPERR: FMC erase/program protection error flag bit - \arg FMC_FLAG_END: FMC end of operation flag bit - \param[out] none - \retval none - */ -void fmc_flag_clear(uint32_t flag) -{ - FMC_REG_VAL(flag) = (!FMC_REG_VAL(flag)) | BIT(FMC_BIT_POS(flag)); -} - -/*! - \brief get FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit - \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) -{ - FlagStatus ret1 = RESET; - FlagStatus ret2 = RESET; - - if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ - /* get the staus of interrupt flag */ - ret1 = (FlagStatus) (FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ - ret2 = (FlagStatus) (FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); - } - - if(ret1 && ret2){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear FMC interrupt flag state - \param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC operation error interrupt flag bit - \arg FMC_INT_FLAG_WPERR: FMC erase/program protection error interrupt flag bit - \arg FMC_INT_FLAG_END: FMC end of operation interrupt flag bit - \param[out] none - \retval none - */ -void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag) -{ - FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag)); -} - -/*! - \brief get the FMC state - \param[in] none - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum fmc_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){ - fmc_state = FMC_BUSY; - }else{ - if((uint32_t) 0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){ - fmc_state = FMC_WPERR; - }else{ - if((uint32_t) 0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){ - fmc_state = FMC_PGERR; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC is ready or not - \param[in] timeout: count of loop - \param[out] none - \retval state of FMC, refer to fmc_state_enum - */ -fmc_state_enum fmc_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do{ - /* get FMC state */ - fmc_state = fmc_state_get(); - timeout--; - }while((FMC_BUSY == fmc_state) && (0x00U != timeout)); - - if(FMC_BUSY == fmc_state){ - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c deleted file mode 100644 index c0f2a38e83..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_fwdgt.c +++ /dev/null @@ -1,151 +0,0 @@ -/*! - \file gd32vf103_fwdgt.c - \brief FWDGT driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_fwdgt.h" - -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC and FWDGT_RLD - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - /* wait until the PUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status){ - return ERROR; - } - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do{ - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - }while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status){ - return ERROR; - } - FWDGT_RLD = RLD_RLD(reload_value); - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(FWDGT_STAT & flag){ - return SET; - } - - return RESET; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c deleted file mode 100644 index cc0fd3f644..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_gpio.c +++ /dev/null @@ -1,503 +0,0 @@ -/*! - \file gd32vf103_gpio.c - \brief GPIO driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_gpio.h" - -#define AFIO_EXTI_SOURCE_MASK ((uint8_t)0x03U) /*!< AFIO exti source selection mask*/ -#define AFIO_EXTI_SOURCE_FIELDS ((uint8_t)0x04U) /*!< select AFIO exti source registers */ -#define LSB_16BIT_MASK ((uint16_t)0xFFFFU) /*!< LSB 16-bit mask */ -#define PCF_POSITION_MASK ((uint32_t)0x000F0000U) /*!< AFIO_PCF register position mask */ -#define PCF_SWJCFG_MASK ((uint32_t)0xF0FFFFFFU) /*!< AFIO_PCF register SWJCFG mask */ -#define PCF_LOCATION1_MASK ((uint32_t)0x00200000U) /*!< AFIO_PCF register location1 mask */ -#define PCF_LOCATION2_MASK ((uint32_t)0x00100000U) /*!< AFIO_PCF register location2 mask */ -#define AFIO_PCF1_FIELDS ((uint32_t)0x80000000U) /*!< select AFIO_PCF1 register */ -#define GPIO_OUTPUT_PORT_OFFSET ((uint32_t)4U) /*!< GPIO event output port offset*/ - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch (gpio_periph) { - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOD: - /* reset GPIOD */ - rcu_periph_reset_enable(RCU_GPIODRST); - rcu_periph_reset_disable(RCU_GPIODRST); - break; - case GPIOE: - /* reset GPIOE */ - rcu_periph_reset_enable(RCU_GPIOERST); - rcu_periph_reset_disable(RCU_GPIOERST); - break; - default: - break; - } -} - -/*! - \brief reset alternate function I/O(AFIO) - \param[in] none - \param[out] none - \retval none -*/ -void gpio_afio_deinit(void) -{ - rcu_periph_reset_enable(RCU_AFRST); - rcu_periph_reset_disable(RCU_AFRST); -} - -/*! - \brief GPIO parameter initialization - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] mode: gpio pin mode - only one parameter can be selected which is shown as below: - \arg GPIO_MODE_AIN: analog input mode - \arg GPIO_MODE_IN_FLOATING: floating input mode - \arg GPIO_MODE_IPD: pull-down input mode - \arg GPIO_MODE_IPU: pull-up input mode - \arg GPIO_MODE_OUT_OD: GPIO output with open-drain - \arg GPIO_MODE_OUT_PP: GPIO output with push-pull - \arg GPIO_MODE_AF_OD: AFIO output with open-drain - \arg GPIO_MODE_AF_PP: AFIO output with push-pull - \param[in] speed: gpio output max speed value - only one parameter can be selected which is shown as below: - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - - \param[out] none - \retval none -*/ -void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, - uint32_t pin) -{ - uint16_t i; - uint32_t temp_mode = 0U; - uint32_t reg = 0U; - - /* GPIO mode configuration */ - temp_mode = (uint32_t) (mode & ((uint32_t) 0x0FU)); - - /* GPIO speed configuration */ - if (((uint32_t) 0x00U) != ((uint32_t) mode & ((uint32_t) 0x10U))) { - /* output mode max speed:10MHz,2MHz,50MHz */ - temp_mode |= (uint32_t) speed; - } - - /* configure the eight low port pins with GPIO_CTL0 */ - for (i = 0U; i < 8U; i++) { - if ((1U << i) & pin) { - reg = GPIO_CTL0(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i, temp_mode); - - /* set IPD or IPU */ - if (GPIO_MODE_IPD == mode) { - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin); - } else { - /* set the corresponding OCTL bit */ - if (GPIO_MODE_IPU == mode) { - GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin); - } - } - /* set GPIO_CTL0 register */ - GPIO_CTL0(gpio_periph) = reg; - } - } - /* configure the eight high port pins with GPIO_CTL1 */ - for (i = 8U; i < 16U; i++) { - if ((1U << i) & pin) { - reg = GPIO_CTL1(gpio_periph); - - /* clear the specified pin mode bits */ - reg &= ~GPIO_MODE_MASK(i - 8U); - /* set the specified pin mode bits */ - reg |= GPIO_MODE_SET(i - 8U, temp_mode); - - /* set IPD or IPU */ - if (GPIO_MODE_IPD == mode) { - /* reset the corresponding OCTL bit */ - GPIO_BC(gpio_periph) = (uint32_t) ((1U << i) & pin); - } else { - /* set the corresponding OCTL bit */ - if (GPIO_MODE_IPU == mode) { - GPIO_BOP(gpio_periph) = (uint32_t) ((1U << i) & pin); - } - } - /* set GPIO_CTL1 register */ - GPIO_CTL1(gpio_periph) = reg; - } - } -} - -/*! - \brief set GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t) pin; -} - -/*! - \brief reset GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t) pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - only one parameter can be selected which is shown as below: - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if (RESET != bit_value) { - GPIO_BOP(gpio_periph) = (uint32_t) pin; - } else { - GPIO_BC(gpio_periph) = (uint32_t) pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] data: specify the value to be written to the port output data register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph, uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t) data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval input status of gpio pin: SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if ((uint32_t) RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief get GPIO port input status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[out] none - \retval input status of gpio all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t) (GPIO_ISTAT(gpio_periph)); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - only one parameter can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval output status of gpio pin: SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if ((uint32_t) RESET != (GPIO_OCTL(gpio_periph) & (pin))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief get GPIO port output status - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[out] none - \retval output status of gpio all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return ((uint16_t) GPIO_OCTL(gpio_periph)); -} - -/*! - \brief configure GPIO pin remap - \param[in] gpio_remap: select the pin to remap - only one parameter can be selected which are shown as below: - \arg GPIO_SPI0_REMAP: SPI0 remapping - \arg GPIO_I2C0_REMAP: I2C0 remapping - \arg GPIO_USART0_REMAP: USART0 remapping - \arg GPIO_USART1_REMAP: USART1 remapping - \arg GPIO_USART2_PARTIAL_REMAP: USART2 partial remapping - \arg GPIO_USART2_FULL_REMAP: USART2 full remapping - \arg GPIO_TIMER0_PARTIAL_REMAP: TIMER0 partial remapping - \arg GPIO_TIMER0_FULL_REMAP: TIMER0 full remapping - \arg GPIO_TIMER1_PARTIAL_REMAP0: TIMER1 partial remapping - \arg GPIO_TIMER1_PARTIAL_REMAP1: TIMER1 partial remapping - \arg GPIO_TIMER1_FULL_REMAP: TIMER1 full remapping - \arg GPIO_TIMER2_PARTIAL_REMAP: TIMER2 partial remapping - \arg GPIO_TIMER2_FULL_REMAP: TIMER2 full remapping - \arg GPIO_TIMER3_REMAP: TIMER3 remapping - \arg GPIO_CAN0_PARTIAL_REMAP: CAN0 partial remapping - \arg GPIO_CAN0_FULL_REMAP: CAN0 full remapping - \arg GPIO_PD01_REMAP: PD01 remapping - \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping - \arg GPIO_CAN1_REMAP: CAN1 remapping - \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP),but without NJTRST - \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled - \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled - \arg GPIO_SPI2_REMAP: SPI2 remapping - \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping - \arg GPIO_EXMC_NADV_REMAP: EXMC_NADV connect/disconnect - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue) -{ - uint32_t remap1 = 0U, remap2 = 0U, temp_reg = 0U, temp_mask = 0U; - - if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { - /* get AFIO_PCF1 regiter value */ - temp_reg = AFIO_PCF1; - } else { - /* get AFIO_PCF0 regiter value */ - temp_reg = AFIO_PCF0; - } - - temp_mask = (remap & PCF_POSITION_MASK) >> 0x10U; - remap1 = remap & LSB_16BIT_MASK; - - /* judge pin remap type */ - if ((PCF_LOCATION1_MASK | PCF_LOCATION2_MASK) - == (remap & (PCF_LOCATION1_MASK | PCF_LOCATION2_MASK))) { - temp_reg &= PCF_SWJCFG_MASK; - AFIO_PCF0 &= PCF_SWJCFG_MASK; - } else if (PCF_LOCATION2_MASK == (remap & PCF_LOCATION2_MASK)) { - remap2 = ((uint32_t) 0x03U) << temp_mask; - temp_reg &= ~remap2; - temp_reg |= ~PCF_SWJCFG_MASK; - } else { - temp_reg &= ~(remap1 << ((remap >> 0x15U) * 0x10U)); - temp_reg |= ~PCF_SWJCFG_MASK; - } - - /* set pin remap value */ - if (DISABLE != newvalue) { - temp_reg |= (remap1 << ((remap >> 0x15U) * 0x10U)); - } - - if (AFIO_PCF1_FIELDS == (remap & AFIO_PCF1_FIELDS)) { - /* set AFIO_PCF1 regiter value */ - AFIO_PCF1 = temp_reg; - } else { - /* set AFIO_PCF0 regiter value */ - AFIO_PCF0 = temp_reg; - } -} - -/*! - \brief select GPIO pin exti sources - \param[in] gpio_outputport: gpio event output port - only one parameter can be selected which are shown as below: - \arg GPIO_PORT_SOURCE_GPIOA: output port source A - \arg GPIO_PORT_SOURCE_GPIOB: output port source B - \arg GPIO_PORT_SOURCE_GPIOC: output port source C - \arg GPIO_PORT_SOURCE_GPIOD: output port source D - \arg GPIO_PORT_SOURCE_GPIOE: output port source E - \param[in] gpio_outputpin: GPIO_PIN_SOURCE_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin) -{ - uint32_t source = 0U; - source = ((uint32_t) 0x0FU) - << (AFIO_EXTI_SOURCE_FIELDS * (output_pin & AFIO_EXTI_SOURCE_MASK)); - - /* select EXTI sources */ - if (GPIO_PIN_SOURCE_4 > output_pin) { - /* select EXTI0/EXTI1/EXTI2/EXTI3 */ - AFIO_EXTISS0 &= ~source; - AFIO_EXTISS0 |= (((uint32_t) output_port) - << (AFIO_EXTI_SOURCE_FIELDS - * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } else if (GPIO_PIN_SOURCE_8 > output_pin) { - /* select EXTI4/EXTI5/EXTI6/EXTI7 */ - AFIO_EXTISS1 &= ~source; - AFIO_EXTISS1 |= (((uint32_t) output_port) - << (AFIO_EXTI_SOURCE_FIELDS - * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } else if (GPIO_PIN_SOURCE_12 > output_pin) { - /* select EXTI8/EXTI9/EXTI10/EXTI11 */ - AFIO_EXTISS2 &= ~source; - AFIO_EXTISS2 |= (((uint32_t) output_port) - << (AFIO_EXTI_SOURCE_FIELDS - * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } else { - /* select EXTI12/EXTI13/EXTI14/EXTI15 */ - AFIO_EXTISS3 &= ~source; - AFIO_EXTISS3 |= (((uint32_t) output_port) - << (AFIO_EXTI_SOURCE_FIELDS - * (output_pin & AFIO_EXTI_SOURCE_MASK))); - } -} - -/*! - \brief configure GPIO pin event output - \param[in] output_port: gpio event output port - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PORT_GPIOA: event output port A - \arg GPIO_EVENT_PORT_GPIOB: event output port B - \arg GPIO_EVENT_PORT_GPIOC: event output port C - \arg GPIO_EVENT_PORT_GPIOD: event output port D - \arg GPIO_EVENT_PORT_GPIOE: event output port E - \param[in] output_pin: - only one parameter can be selected which are shown as below: - \arg GPIO_EVENT_PIN_x(x=0..15) - \param[out] none - \retval none -*/ -void gpio_event_output_config(uint8_t output_port, uint8_t output_pin) -{ - uint32_t reg = 0U; - reg = AFIO_EC; - - /* clear AFIO_EC_PORT and AFIO_EC_PIN bits */ - reg &= (uint32_t) (~(AFIO_EC_PORT | AFIO_EC_PIN)); - - reg |= (uint32_t) ((uint32_t) output_port << GPIO_OUTPUT_PORT_OFFSET); - reg |= (uint32_t) output_pin; - - AFIO_EC = reg; -} - -/*! - \brief enable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_enable(void) -{ - AFIO_EC |= AFIO_EC_EOE; -} - -/*! - \brief disable GPIO pin event output - \param[in] none - \param[out] none - \retval none -*/ -void gpio_event_output_disable(void) -{ - AFIO_EC &= (uint32_t) (~AFIO_EC_EOE); -} - -/*! - \brief lock GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,D,E) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1 -> write 0 -> write 1 -> read 0 -> read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t) lock; - GPIO_LOCK(gpio_periph) = (uint32_t) pin; - GPIO_LOCK(gpio_periph) = (uint32_t) lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c deleted file mode 100644 index 1e6ab305c6..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_i2c.c +++ /dev/null @@ -1,726 +0,0 @@ -/*! - \file gd32vf103_i2c.c - \brief I2C driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x00000048U) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ -#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)8U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none - */ -void i2c_deinit(uint32_t i2c_periph) -{ - switch (i2c_periph) { - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - \param[in] dutycyc: duty cycle in fast mode - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high=2 - \arg I2C_DTCY_16_9: T_low/T_high=16/9 - \param[out] none - \retval none - */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t) (pclk1 / 1000000U); - if (freq >= I2CCLK_MAX) { - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if (100000U >= clkspeed) { - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t) ((pclk1 / 1000000U) + 1U); - if (risetime >= I2CCLK_MAX) { - I2C_RT(i2c_periph) = I2CCLK_MAX; - } else if (risetime <= I2CCLK_MIN) { - I2C_RT(i2c_periph) = I2CCLK_MIN; - } else { - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t) (pclk1 / (clkspeed * 2U)); - if (clkc < 0x04U) { - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - } else if (400000U >= clkspeed) { - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t) (((freq * (uint32_t) 300U) - / (uint32_t) 1000U) + (uint32_t) 1U); - if (I2C_DTCY_2 == dutycyc) { - /* I2C duty cycle is 2 */ - clkc = (uint32_t) (pclk1 / (clkspeed * 3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - } else { - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t) (pclk1 / (clkspeed * 25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if (0U == (clkc & I2C_CKCFG_CLKC)) { - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - } else { - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: 7bits - \arg I2C_ADDFORMAT_10BITS: 10bits - \param[in] addr: I2C address - \param[out] none - \retval none - */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief SMBus type selection - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: device - \arg I2C_SMBUS_HOST: host - \param[out] none - \retval none - */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if (I2C_SMBUS_HOST == type) { - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - } else { - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none - */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - if (I2C_ACK_ENABLE == ack) { - I2C_CTL0(i2c_periph) |= I2C_CTL0_ACKEN; - } else { - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_ACKEN); - } -} - -/*! - \brief configure I2C POAP position - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: whether to send ACK or not for the current - \arg I2C_ACKPOS_NEXT: whether to send ACK or not for the next byte - \param[out] none - \retval none - */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - /* configure I2C POAP position */ - if (I2C_ACKPOS_NEXT == pos) { - I2C_CTL0(i2c_periph) |= I2C_CTL0_POAP; - } else { - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_POAP); - } -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none - */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if (I2C_TRANSMITTER == trandirection) { - addr = addr & I2C_TRANSMITTER; - } else { - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief configure I2C saddress1 - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_saddr1_config(uint32_t i2c_periph,uint32_t addr) -{ - /* configure saddress1 */ - I2C_SADDR1(i2c_periph) = (0xFE & addr); -} - -/*! - \brief enable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: the second address in dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) -{ - /* configure address */ - addr = addr & I2C_ADDRESS2_MASK; - I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); -} - -/*! - \brief disable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_dualaddr_disable(uint32_t i2c_periph) -{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none - */ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none - */ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none - */ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none - */ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none - */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received - */ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t) DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief enable I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: DMA mode enable - \arg I2C_DMA_OFF: DMA mode disable - \param[out] none - \retval none - */ -void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none - */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: SCL stretching is enabled - \arg I2C_SCLSTRETCH_DISABLE: SCL stretching is disabled - \param[out] none - \retval none - */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SS); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none - */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief software reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none - */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C PEC calculation on or off - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none - */ -void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief I2C whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC - \arg I2C_PECTRANS_DISABLE: not transfer PEC - \param[out] none - \retval none - */ -void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value - */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t) ((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV)>> STAT1_PECV_OFFSET); -} - -/*! - \brief I2C issue alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none - */ -void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* issue alert through SMBA pin configure*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable or disable I2C ARP protocol in SMBus switch - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] arpstate: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none - */ -void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief check I2C flag is set or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition send out - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not Empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: overrun or underrun situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMODF: dual flag in slave mode indicating which address is matched in dual-address mode - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if (RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear I2C flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus Alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error - \arg I2C_FLAG_ADDSEND: cleared by reading I2C_STAT0 and reading I2C_STAT1 - \param[out] none - \retval none - */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - uint32_t temp; - if (I2C_FLAG_ADDSEND == flag) { - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - temp = I2C_STAT0(i2c_periph); - temp = I2C_STAT1(i2c_periph); - } else { - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none - */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt enable - \arg I2C_INT_EV: event interrupt enable - \arg I2C_INT_BUF: buffer interrupt enable - \param[out] none - \retval none - */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief check I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: etop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET - */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph) & I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag)& BIT(I2C_BIT_POS2(int_flag))); - - if ((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { - if (intenable && bufie) { - intenable = 1U; - } else { - intenable = 0U; - } - } - if ((0U != flagstatus) && (0U != intenable)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus Alert status interrupt flag - \param[out] none - \retval none - */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag) -{ - uint32_t temp; - if (I2C_INT_FLAG_ADDSEND == int_flag) { - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - temp = I2C_STAT0(i2c_periph); - temp = I2C_STAT1(i2c_periph); - } else { - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c deleted file mode 100644 index 905cec75c3..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_pmu.c +++ /dev/null @@ -1,270 +0,0 @@ -/*! - \file gd32vf103_pmu.c - \brief PMU driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_pmu.h" -#include "riscv_encoding.h" - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - only one parameter can be selected which is shown as below: - \arg PMU_LVDT_0: voltage threshold is 2.2V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.5V - \arg PMU_LVDT_4: voltage threshold is 2.6V - \arg PMU_LVDT_5: voltage threshold is 2.7V - \arg PMU_LVDT_6: voltage threshold is 2.8V - \arg PMU_LVDT_7: voltage threshold is 2.9V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M3 system control register */ - clear_csr(0x811, 0x1); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd){ - __WFI(); - }else{ - clear_csr(mstatus, MSTATUS_MIE); - set_csr(0x810, 0x1); - __WFI(); - clear_csr(0x810, 0x1); - set_csr(mstatus, MSTATUS_MIE); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo: - only one parameter can be selected which is shown as below: - \arg PMU_LDO_NORMAL: LDO work at normal power mode when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd) -{ - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - /* set CSR_SLEEPVALUE bit of RISC-V system control register */ - set_csr(0x811, 0x1); - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd){ - __WFI(); - }else{ - clear_csr(mstatus, MSTATUS_MIE); - set_csr(0x810, 0x1); - __WFI(); - clear_csr(0x810, 0x1); - set_csr(mstatus, MSTATUS_MIE); - } - /* reset sleepdeep bit of RISC-V system control register */ - clear_csr(0x811, 0x1); -} - -/*! - \brief pmu work at standby mode - \param[in] standbymodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_standbymode(uint8_t standbymodecmd) -{ - /* set CSR_SLEEPVALUE bit of RISC-V system control register */ - set_csr(0x811, 0x1); - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* select WFI or WFE command to enter standby mode */ - if(WFI_CMD == standbymodecmd){ - __WFI(); - }else{ - clear_csr(mstatus, MSTATUS_MIE); - set_csr(0x810, 0x1); - __WFI(); - clear_csr(0x810, 0x1); - set_csr(mstatus, MSTATUS_MIE); - } - clear_csr(0x811, 0x1); -} - -/*! - \brief enable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(void) -{ - PMU_CS |= PMU_CS_WUPEN; -} - -/*! - \brief disable wakeup pin - \param[in] none - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(void) -{ - PMU_CS &= ~PMU_CS_WUPEN; -} - -/*! - \brief enable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable write access to the registers in backup domain - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief get flag state - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \param[out] none - \retval FlagStatus SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - if(PMU_CS & flag){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag bit - \param[in] flag_reset: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag_reset) -{ - switch(flag_reset){ - case PMU_FLAG_RESET_WAKEUP: - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - break; - case PMU_FLAG_RESET_STANDBY: - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - break; - default : - break; - } -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c deleted file mode 100644 index b2c0d83052..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rcu.c +++ /dev/null @@ -1,1111 +0,0 @@ -/*! - \file gd32vf103_rcu.c - \brief RCU driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_rcu.h" - -/* define clock source */ -#define SEL_IRC8M ((uint16_t)0U) -#define SEL_HXTAL ((uint16_t)1U) -#define SEL_PLL ((uint16_t)2U) - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0xFFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x3FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - rcu_osci_stab_wait(RCU_IRC8M); - - /* reset CFG0 register */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_CKOUT0SEL | RCU_CFG0_ADCPSC_2 | RCU_CFG0_PLLMF_4); - /* reset CTL register */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - RCU_CTL &= ~RCU_CTL_HXTALBPS; - RCU_CTL &= ~(RCU_CTL_PLL1EN | RCU_CTL_PLL2EN); - /* reset INT and CFG1 register */ - RCU_INT = 0x00ff0000U; - RCU_CFG1 &= ~(RCU_CFG1_PREDV0 | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PLL2MF | - RCU_CFG1_PREDV0SEL | RCU_CFG1_I2S1SEL | RCU_CFG1_I2S2SEL); -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock - \arg RCU_AF : alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_USBFS: USBFS clock - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1): ADC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,D,E): GPIO ports clock - \arg RCU_AF: alternate function clock - \arg RCU_CRC: CRC clock - \arg RCU_DMAx (x=0,1): DMA clock - \arg RCU_USBFS: USBFS clock - \arg RCU_EXMC: EXMC clock - \arg RCU_TIMERx (x=0,1,2,3,4,5,6): TIMER clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_SPIx (x=0,1,2): SPI clock - \arg RCU_USARTx (x=0,1,2): USART clock - \arg RCU_UARTx (x=3,4): UART clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_CANx (x=0,1): CAN clock - \arg RCU_PMU: PMU clock - \arg RCU_DAC: DAC clock - \arg RCU_RTC: RTC clock - \arg RCU_ADCx (x=0,1): ADC clock - \arg RCU_BKPI: BKP interface clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_USBFSRST: reset USBFS - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1): reset ADC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,D,E): reset GPIO ports - \arg RCU_AFRST : reset alternate function clock - \arg RCU_USBFSRST: reset USBFS - \arg RCU_TIMERxRST (x=0,1,2,3,4,5,6): reset TIMER - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_SPIxRST (x=0,1,2): reset SPI - \arg RCU_USARTxRST (x=0,1,2): reset USART - \arg RCU_UARTxRST (x=3,4): reset UART - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_CANxRST (x=0,1): reset CAN - \arg RCU_PMURST: reset PMU - \arg RCU_DACRST: reset DAC - \arg RCU_ADCxRST (x=0,1): reset ADC - \arg RCU_BKPIRST: reset BKPI - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP domain - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP domain reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t reg; - - reg = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - reg &= ~RCU_CFG0_SCS; - RCU_CFG0 = (reg | ck_sys); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: CK_IRC8M is selected as the CK_SYS source - \arg RCU_SCSS_HXTAL: CK_HXTAL is selected as the CK_SYS source - \arg RCU_SCSS_PLL: CK_PLL is selected as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx, x=1, 2, 4, 8, 16, 64, 128, 256, 512 - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the AHBPSC bits and set according to ck_ahb */ - reg &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (reg | ck_ahb); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB1PSC and set according to ck_apb1 */ - reg &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (reg | ck_apb1); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the APB2PSC and set according to ck_apb2 */ - reg &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (reg | ck_apb2); -} - -/*! - \brief configure the CK_OUT0 clock source - \param[in] ckout0_src: CK_OUT0 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUT0SRC_NONE: no clock selected - \arg RCU_CKOUT0SRC_CKSYS: system clock selected - \arg RCU_CKOUT0SRC_IRC8M: high speed 8M internal oscillator clock selected - \arg RCU_CKOUT0SRC_HXTAL: HXTAL selected - \arg RCU_CKOUT0SRC_CKPLL_DIV2: CK_PLL/2 selected - \arg RCU_CKOUT0SRC_CKPLL1: CK_PLL1 selected - \arg RCU_CKOUT0SRC_CKPLL2_DIV2: CK_PLL2/2 selected - \arg RCU_CKOUT0SRC_EXT1: EXT1 selected - \arg RCU_CKOUT0SRC_CKPLL2: PLL2 selected - \param[out] none - \retval none -*/ -void rcu_ckout0_config(uint32_t ckout0_src) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* reset the CKOUT0SRC, set according to ckout0_src */ - reg &= ~RCU_CFG0_CKOUT0SEL; - RCU_CFG0 = (reg | ckout0_src); -} - -/*! - \brief configure the main PLL clock - \param[in] pll_src: PLL clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLLSRC_IRC8M_DIV2: IRC8M/2 clock selected as source clock of PLL - \arg RCU_PLLSRC_HXTAL: HXTAL selected as source clock of PLL - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL_MULx (x = 2..14, 6.5, 16..32) - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - uint32_t reg = 0U; - - reg = RCU_CFG0; - - /* PLL clock source and multiplication factor configuration */ - reg &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - reg |= (pll_src | pll_mul); - - RCU_CFG0 = reg; -} - -/*! - \brief configure the PREDV0 division factor and clock source - \param[in] predv0_source: PREDV0 input clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0SRC_HXTAL: HXTAL selected as PREDV0 input source clock - \arg RCU_PREDV0SRC_CKPLL1: CK_PLL1 selected as PREDV0 input source clock - \param[in] predv0_div: PREDV0 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV0_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset PREDV0SEL and PREDV0 bits */ - reg &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV0); - /* set the PREDV0SEL and PREDV0 division factor */ - reg |= (predv0_source | predv0_div); - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PREDV1 division factor - \param[in] predv1_div: PREDV1 division factor - only one parameter can be selected which is shown as below: - \arg RCU_PREDV1_DIVx, x = 1..16 - \param[out] none - \retval none -*/ -void rcu_predv1_config(uint32_t predv1_div) -{ - uint32_t reg = 0U; - - reg = RCU_CFG1; - /* reset the PREDV1 bits */ - reg &= ~RCU_CFG1_PREDV1; - /* set the PREDV1 division factor */ - reg |= predv1_div; - - RCU_CFG1 = reg; -} - -/*! - \brief configure the PLL1 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL1_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll1_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL1MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the PLL2 clock - \param[in] pll_mul: PLL clock multiplication factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL2_MULx (x = 8..16, 20) - \param[out] none - \retval none -*/ -void rcu_pll2_config(uint32_t pll_mul) -{ - RCU_CFG1 &= ~RCU_CFG1_PLL2MF; - RCU_CFG1 |= pll_mul; -} - -/*! - \brief configure the ADC prescaler factor - \param[in] adc_psc: ADC prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKADC_CKAPB2_DIV2: ADC prescaler select CK_APB2/2 - \arg RCU_CKADC_CKAPB2_DIV4: ADC prescaler select CK_APB2/4 - \arg RCU_CKADC_CKAPB2_DIV6: ADC prescaler select CK_APB2/6 - \arg RCU_CKADC_CKAPB2_DIV8: ADC prescaler select CK_APB2/8 - \arg RCU_CKADC_CKAPB2_DIV12: ADC prescaler select CK_APB2/12 - \arg RCU_CKADC_CKAPB2_DIV16: ADC prescaler select CK_APB2/16 - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(uint32_t adc_psc) -{ - uint32_t reg0; - - /* reset the ADCPSC bits */ - reg0 = RCU_CFG0; - reg0 &= ~(RCU_CFG0_ADCPSC_2 | RCU_CFG0_ADCPSC); - - /* set the ADC prescaler factor */ - switch(adc_psc){ - case RCU_CKADC_CKAPB2_DIV2: - case RCU_CKADC_CKAPB2_DIV4: - case RCU_CKADC_CKAPB2_DIV6: - case RCU_CKADC_CKAPB2_DIV8: - reg0 |= (adc_psc << 14); - break; - - case RCU_CKADC_CKAPB2_DIV12: - case RCU_CKADC_CKAPB2_DIV16: - adc_psc &= ~BIT(2); - reg0 |= (adc_psc << 14 | RCU_CFG0_ADCPSC_2); - break; - - default: - break; - } - - /* set the register */ - RCU_CFG0 = reg0; -} - -/*! - \brief configure the USBFS prescaler factor - \param[in] usb_psc: USB prescaler factor - only one parameter can be selected which is shown as below: - \arg RCU_CKUSB_CKPLL_DIV1_5: USBFS prescaler select CK_PLL/1.5 - \arg RCU_CKUSB_CKPLL_DIV1: USBFS prescaler select CK_PLL/1 - \arg RCU_CKUSB_CKPLL_DIV2_5: USBFS prescaler select CK_PLL/2.5 - \arg RCU_CKUSB_CKPLL_DIV2: USBFS prescaler select CK_PLL/2 - \param[out] none - \retval none -*/ -void rcu_usb_clock_config(uint32_t usb_psc) -{ - uint32_t reg; - - reg = RCU_CFG0; - - /* configure the USBFS prescaler factor */ - reg &= ~RCU_CFG0_USBFSPSC; - RCU_CFG0 = (reg | usb_psc); -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV_128: CK_HXTAL/128 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - uint32_t reg; - - reg = RCU_BDCTL; - /* reset the RTCSRC bits and set according to rtc_clock_source */ - reg &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL = (reg | rtc_clock_source); -} - -/*! - \brief configure the I2S1 clock source selection - \param[in] i2s_clock_source: I2S1 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S1SRC_CKSYS: System clock selected as I2S1 source clock - \arg RCU_I2S1SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S1 source clock - \param[out] none - \retval none -*/ -void rcu_i2s1_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S1SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S1SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief configure the I2S2 clock source selection - \param[in] i2s_clock_source: I2S2 clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_I2S2SRC_CKSYS: system clock selected as I2S2 source clock - \arg RCU_I2S2SRC_CKPLL2_MUL2: CK_PLL2x2 selected as I2S2 source clock - \param[out] none - \retval none -*/ -void rcu_i2s2_clock_config(uint32_t i2s_clock_source) -{ - uint32_t reg; - - reg = RCU_CFG1; - /* reset the I2S2SEL bit and set according to i2s_clock_source */ - reg &= ~RCU_CFG1_I2S2SEL; - RCU_CFG1 = (reg | i2s_clock_source); -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_PLL1STB: PLL1 stabilization flag - \arg RCU_FLAG_PLL2STB: PLL2 stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_EPRST: external PIN reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - /* get the rcu flag */ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear all the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_PLL1STB: PLL1 stabilization interrupt flag - \arg RCU_INT_FLAG_PLL2STB: PLL2 stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - /* get the rcu interrupt flag */ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL1STB_CLR: PLL1 stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLL2STB_CLR: PLL2 stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - Only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_PLL1STB: PLL1 stabilization interrupt enable - \arg RCU_INT_PLL2STB: PLL2 stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} - -/*! - \brief wait for oscillator stabilization flags is SET or oscillator startup is timeout - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1 - \arg RCU_PLL2_CK: phase locked loop 2 - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - - switch(osci){ - /* wait HXTAL stable */ - case RCU_HXTAL: - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)){ - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)){ - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)){ - reval = SUCCESS; - } - break; - /* wait PLL1 stable */ - case RCU_PLL1_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL1STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL1STB)){ - reval = SUCCESS; - } - break; - /* wait PLL2 stable */ - case RCU_PLL2_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)){ - osci_stat = rcu_flag_get(RCU_FLAG_PLL2STB); - stb_cnt++; - } - - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLL2STB)){ - reval = SUCCESS; - } - break; - - default: - break; - } - - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1 - \arg RCU_PLL2_CK: phase locked loop 2 - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \arg RCU_IRC8M: internal 8M RC oscillators(IRC8M) - \arg RCU_IRC40K: internal 40K RC oscillator(IRC40K) - \arg RCU_PLL_CK: phase locked loop(PLL) - \arg RCU_PLL1_CK: phase locked loop 1 - \arg RCU_PLL2_CK: phase locked loop 2 - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* enable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg | RCU_CTL_HXTALBPS); - break; - /* enable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC40K: - case RCU_PLL_CK: - case RCU_PLL1_CK: - case RCU_PLL2_CK: - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: high speed crystal oscillator(HXTAL) - \arg RCU_LXTAL: low speed crystal oscillator(LXTAL) - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - - switch(osci){ - /* disable HXTAL to bypass mode */ - case RCU_HXTAL: - reg = RCU_CTL; - RCU_CTL &= ~RCU_CTL_HXTALEN; - RCU_CTL = (reg & ~RCU_CTL_HXTALBPS); - break; - /* disable LXTAL to bypass mode */ - case RCU_LXTAL: - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & ~RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC40K: - case RCU_PLL_CK: - case RCU_PLL1_CK: - case RCU_PLL2_CK: - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ - -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL |= RCU_CTL_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL &= ~RCU_CTL_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval) -{ - uint32_t reg; - - reg = RCU_CTL; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - reg &= ~RCU_CTL_IRC8MADJ; - RCU_CTL = (reg | ((irc8m_adjval & 0x1FU) << 3)); -} - -/*! - \brief deep-sleep mode voltage select - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \arg RCU_DEEPSLEEP_V_1_1: the core voltage is 1.1V - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - dsvol &= RCU_DSV_DSLPVS; - RCU_DSV = dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws, ck_freq = 0U; - uint32_t cksys_freq, ahb_freq, apb1_freq, apb2_freq; - uint32_t pllsel, predv0sel, pllmf,ck_src, idx, clk_exp; - uint32_t predv0, predv1, pll1mf; - - /* exponent of AHB, APB1 and APB2 clock divider */ - uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws){ - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if(RCU_PLLSRC_HXTAL == pllsel) { - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - /* source clock use PLL1 */ - if(RCU_PREDV0SRC_CKPLL1 == predv0sel){ - predv1 = (uint32_t)((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = (uint32_t)((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if(17U == pll1mf){ - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; - }else{ - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE/2U; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){ - pllmf |= 0x10U; - } - if(pllmf < 15U){ - pllmf += 2U; - }else{ - pllmf += 1U; - } - - cksys_freq = ck_src * pllmf; - - if(15U == pllmf){ - /* PLL source clock multiply by 6.5 */ - cksys_freq = ck_src * 6U + ck_src / 2U; - } - - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock){ - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - default: - break; - } - return ck_freq; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c deleted file mode 100644 index e397d3a2cf..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_rtc.c +++ /dev/null @@ -1,273 +0,0 @@ -/*! - \file gd32vf103_rtc.c - \brief RTC driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_rtc.h" - -/* RTC register high / low bits mask */ -#define RTC_HIGH_BITS_MASK ((uint32_t)0x000F0000U) /* RTC high bits mask */ -#define RTC_LOW_BITS_MASK ((uint32_t)0x0000FFFFU) /* RTC low bits mask */ - -/* RTC register high bits offset */ -#define RTC_HIGH_BITS_OFFSET ((uint32_t)16U) - -/*! - \brief enter RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_enter(void) -{ - RTC_CTL |= RTC_CTL_CMF; -} - -/*! - \brief exit RTC configuration mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_configuration_mode_exit(void) -{ - RTC_CTL &= ~RTC_CTL_CMF; -} - -/*! - \brief set RTC counter value - \param[in] cnt: RTC counter value - \param[out] none - \retval none -*/ -void rtc_counter_set(uint32_t cnt) -{ - rtc_configuration_mode_enter(); - /* set the RTC counter high bits */ - RTC_CNTH = (cnt >> RTC_HIGH_BITS_OFFSET); - /* set the RTC counter low bits */ - RTC_CNTL = (cnt & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief set RTC prescaler value - \param[in] psc: RTC prescaler value - \param[out] none - \retval none -*/ -void rtc_prescaler_set(uint32_t psc) -{ - rtc_configuration_mode_enter(); - /* set the RTC prescaler high bits */ - RTC_PSCH = ((psc & RTC_HIGH_BITS_MASK) >> RTC_HIGH_BITS_OFFSET); - /* set the RTC prescaler low bits */ - RTC_PSCL = (psc & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief wait RTC last write operation finished flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_lwoff_wait(void) -{ - /* loop until LWOFF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_LWOFF)){ - } -} - -/*! - \brief wait RTC registers synchronized flag set - \param[in] none - \param[out] none - \retval none -*/ -void rtc_register_sync_wait(void) -{ - /* clear RSYNF flag */ - RTC_CTL &= ~RTC_CTL_RSYNF; - /* loop until RSYNF flag is set */ - while(RESET == (RTC_CTL & RTC_CTL_RSYNF)){ - } -} - -/*! - \brief set RTC alarm value - \param[in] alarm: RTC alarm value - \param[out] none - \retval none -*/ -void rtc_alarm_config(uint32_t alarm) -{ - rtc_configuration_mode_enter(); - /* set the alarm high bits */ - RTC_ALRMH = (alarm >> RTC_HIGH_BITS_OFFSET); - /* set the alarm low bits */ - RTC_ALRML = (alarm & RTC_LOW_BITS_MASK); - rtc_configuration_mode_exit(); -} - -/*! - \brief get RTC counter value - \param[in] none - \param[out] none - \retval RTC counter value -*/ -uint32_t rtc_counter_get(void) -{ - uint32_t temp = 0x0U; - - temp = RTC_CNTL; - temp |= (RTC_CNTH << RTC_HIGH_BITS_OFFSET); - return temp; -} - -/*! - \brief get RTC divider value - \param[in] none - \param[out] none - \retval RTC divider value -*/ -uint32_t rtc_divider_get(void) -{ - uint32_t temp = 0x00U; - - temp = ((RTC_DIVH & RTC_DIVH_DIV) << RTC_HIGH_BITS_OFFSET); - temp |= RTC_DIVL; - return temp; -} - -/*! - \brief get RTC flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \arg RTC_FLAG_LWOF: last write operation finished flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear RTC flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_FLAG_SECOND: second interrupt flag - \arg RTC_FLAG_ALARM: alarm interrupt flag - \arg RTC_FLAG_OVERFLOW: overflow interrupt flag - \arg RTC_FLAG_RSYN: registers synchronized flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - /* clear RTC flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief get RTC interrupt flag status - \param[in] flag: specify which flag status to get - only one parameter can be selected which is shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval SET or RESET -*/ -FlagStatus rtc_interrupt_flag_get(uint32_t flag) -{ - if(RESET != (RTC_CTL & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear RTC interrupt flag status - \param[in] flag: specify which flag status to clear - one or more parameters can be selected which are shown as below: - \arg RTC_INT_FLAG_SECOND: second interrupt flag - \arg RTC_INT_FLAG_ALARM: alarm interrupt flag - \arg RTC_INT_FLAG_OVERFLOW: overflow interrupt flag - \param[out] none - \retval none -*/ -void rtc_interrupt_flag_clear(uint32_t flag) -{ - /* clear RTC interrupt flag */ - RTC_CTL &= ~flag; -} - -/*! - \brief enable RTC interrupt - \param[in] interrupt: specify which interrupt to enbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - RTC_INTEN |= interrupt; -} - -/*! - \brief disable RTC interrupt - \param[in] interrupt: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg RTC_INT_SECOND: second interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_OVERFLOW: overflow interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - RTC_INTEN &= ~interrupt; -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c deleted file mode 100644 index 2e1b3a16bb..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_spi.c +++ /dev/null @@ -1,766 +0,0 @@ -/*! - \file gd32vf103_spi.c - \brief SPI driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_spi.h" - -/* SPI/I2S parameter initialization mask */ -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI parameter initialization mask */ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -/* I2S clock source selection, multiplication and division mask */ -#define I2S1_CLOCK_SEL ((uint32_t)0x00020000U) /* I2S1 clock source selection */ -#define I2S2_CLOCK_SEL ((uint32_t)0x00040000U) /* I2S2 clock source selection */ -#define I2S_CLOCK_MUL_MASK ((uint32_t)0x0000F000U) /* I2S clock multiplication mask */ -#define I2S_CLOCK_DIV_MASK ((uint32_t)0x000000F0U) /* I2S clock division mask */ - -/* default value and offset */ -#define SPI_I2SPSC_DEFAULT_VALUE ((uint32_t)0x00000002U) /* default value of SPI_I2SPSC register */ -#define RCU_CFG1_PREDV1_OFFSET 4U /* PREDV1 offset in RCU_CFG1 */ -#define RCU_CFG1_PLL2MF_OFFSET 12U /* PLL2MF offset in RCU_CFG1 */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph){ - case SPI0: - /* reset SPI0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 and I2S1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - case SPI2: - /* reset SPI2 and I2S2 */ - rcu_periph_reset_enable(RCU_SPI2RST); - rcu_periph_reset_disable(RCU_SPI2RST); - break; - default : - break; - } -} - -/*! - \brief initialize the parameters of SPI struct with the default values - \param[in] spi_struct: SPI parameter stuct - \param[out] none - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct* spi_struct) -{ - /* set the SPI struct with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; -} - -/*! - \brief initialize SPI parameter - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_16BIT, SPI_FRAMESIZE_8BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval none -*/ -void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct) -{ - uint32_t reg = 0U; - reg = SPI_CTL0(spi_periph); - reg &= SPI_INIT_MASK; - - /* select SPI as master or slave */ - reg |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg |= spi_struct->trans_mode; - /* select SPI frame size */ - reg |= spi_struct->frame_size; - /* select SPI NSS use hardware or software */ - reg |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg |= spi_struct->endian; - /* select SPI polarity and phase */ - reg |= spi_struct->clock_polarity_phase; - /* select SPI prescale to adjust transmit speed */ - reg |= spi_struct->prescale; - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg; - - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief initialize I2S parameter - \param[in] spi_periph: SPIx(x=1,2) - \param[in] mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg = 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPIx(x=1,2) - \param[in] audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: I2S master clock output enable - \arg I2S_MCKOUT_DISABLE: I2S master clock output disable - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - - /* deinit SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_DEFAULT_VALUE; - - /* get the I2S clock source */ - if(SPI1 == ((uint32_t)spi_periph)){ - /* I2S1 clock source selection */ - clks = I2S1_CLOCK_SEL; - }else{ - /* I2S2 clock source selection */ - clks = I2S2_CLOCK_SEL; - } - - if(0U != (RCU_CFG1 & clks)){ - /* get RCU PLL2 clock multiplication factor */ - clks = (uint32_t)((RCU_CFG1 & I2S_CLOCK_MUL_MASK) >> RCU_CFG1_PLL2MF_OFFSET); - - if((clks > 5U) && (clks < 15U)){ - /* multiplier is between 8 and 16 */ - clks += 2U; - }else{ - if(15U == clks){ - /* multiplier is 20 */ - clks = 20U; - } - } - - /* get the PREDV1 value */ - i2sclock = (uint32_t)(((RCU_CFG1 & I2S_CLOCK_DIV_MASK) >> RCU_CFG1_PREDV1_OFFSET) + 1U); - /* calculate I2S clock based on PLL2 and PREDV1 */ - i2sclock = (uint32_t)((HXTAL_VALUE / i2sclock) * clks * 2U); - }else{ - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - } - - /* config the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout){ - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - }else{ - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat){ - clks = (uint32_t)(((i2sclock / 32U) *10U ) / audiosample); - }else{ - clks = (uint32_t)(((i2sclock / 64U) *10U ) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)){ - i2sdiv = 2U; - i2sof = 0U; - } - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=1,2) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - }else{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma){ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - }else{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI/I2S data frame format - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_16BIT: SPI frame size is 16 bits - \arg SPI_FRAMESIZE_8BIT: SPI frame size is 8 bits - \param[out] none - \retval none -*/ -void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* configure SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= (uint32_t)frame_format; -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - SPI_DATA(spi_periph) = (uint32_t)data; -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - return ((uint16_t)SPI_DATA(spi_periph)); -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction){ - /* set the transmit-only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - }else{ - /* set the receive-only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief set SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc) -{ - if(SPI_CRC_TX == crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); - }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - -/*! - \brief enable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nssp_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; -} - -/*! - \brief disable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_nssp_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); -} - - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_RBNEIE; - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_ERRIE; - break; - default: - break; - } -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error,configuration error,reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_TBE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TBEIE); - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_RBNE: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RBNEIE); - break; - /* SPI/I2S error */ - case SPI_I2S_INT_ERR: - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_ERRIE); - break; - default: - break; - } -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] interrupt: SPI/I2S interrupt flag status - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(interrupt){ - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI/I2S format error interrupt */ - case SPI_I2S_INT_FLAG_FERR: - reg1 = reg1 & SPI_STAT_FERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default: - break; - } - /* get SPI/I2S interrupt flag status */ - if((0U != reg1) && (0U != reg2)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[in] flag: SPI/I2S flag status - one or more parameters can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(RESET != (SPI_STAT(spi_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1,2) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) &= (uint32_t)(~SPI_FLAG_CRCERR); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c deleted file mode 100644 index e13e1cd29b..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_timer.c +++ /dev/null @@ -1,1965 +0,0 @@ -/*! - \file gd32vf103_timer.c - \brief TIMER driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ -#include "gd32vf103_timer.h" - -/* TIMER init parameter mask */ -#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ -#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ -#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ - -/*! - \brief deinit a timer - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph){ - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER1: - /* reset TIMER1 */ - rcu_periph_reset_enable(RCU_TIMER1RST); - rcu_periph_reset_disable(RCU_TIMER1RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER3: - /* reset TIMER3 */ - rcu_periph_reset_enable(RCU_TIMER3RST); - rcu_periph_reset_disable(RCU_TIMER3RST); - break; - case TIMER4: - /* reset TIMER4 */ - rcu_periph_reset_enable(RCU_TIMER4RST); - rcu_periph_reset_disable(RCU_TIMER4RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER6: - /* reset TIMER6 */ - rcu_periph_reset_enable(RCU_TIMER6RST); - rcu_periph_reset_disable(RCU_TIMER6RST); - break; - - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct* initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock, 0~65535 - alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, - TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN - period: counter auto reload value, 0~65535 - clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value, 0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph) - || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) ){ - TIMER_CTL0(timer_periph) &= (~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM)); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->alignedmode & ALIGNEDMODE_MASK); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); - }else{ - TIMER_CTL0(timer_periph) &= (uint32_t)(~ TIMER_CTL0_DIR); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->counterdirection & COUNTERDIRECTION_MASK); - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)){ - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= (~(uint32_t)TIMER_CTL0_CKDIV); - TIMER_CTL0(timer_periph) |= (uint32_t)(initpara->clockdivision & CLOCKDIVISION_MASK); - } - - if (TIMER0 == timer_periph) { - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a timer - \param[in] timer_periph: TIMERx(x=0..6) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a timer - \param[in] timer_periph: TIMERx(x=0..13) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..6) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0..6) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0..6) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0..6) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= (uint32_t)(~TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0..4) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0..4) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] prescaler: prescaler value - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload){ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0) - \param[in] repetition: the counter repetition value, 0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] autoreload: the counter auto-reload value - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] counter: the counter value - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0..6) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0..6) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t) (TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - }else if(TIMER_SP_MODE_REPETITIVE == spmode){ - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow, - or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint32_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update){ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - }else if(TIMER_UPDATE_SRC_GLOBAL == update){ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] dma: specify which DMA to enable - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6) - \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0) - \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: TIMERxTIMERx(x=0..6) - \param[in] dma: specify which DMA to disbale - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA enable, TIMERx(x=0..6) - \arg TIMER_DMA_CH0D: channel 0 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CH1D: channel 1 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CH2D: channel 2 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CH3D: channel 3 DMA enable, TIMERx(x=0..4) - \arg TIMER_DMA_CMTD: channel commutation DMA request enable, TIMERx(x=0) - \arg TIMER_DMA_TRGD: trigger DMA enable, TIMERx(x=0..4,7) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel n is sent when channel n event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel n is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - }else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0..4) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0..4) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..6): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event generation, TIMERx(x=0..6) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0..4) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0..4) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0..4) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0..4) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0..4) - \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE, TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE, TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW, TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE, TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF, TIMER_CCHP_PROT_0, TIMER_CCHP_PROT_1, TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE, TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | - ((uint32_t)(breakpara->ideloffstate))| - ((uint32_t)(breakpara->deadtime)) | - ((uint32_t)(breakpara->breakpolarity)) | - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode)) | - ((uint32_t)(breakpara->breakstate))); -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief enable or disable TIMER primary output function - \param[in] timer_periph: TIMERx(x=0) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - }else{ - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - }else{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl){ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - }else if(TIMER_UPDATECTL_CCUTRI == ccuctl){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE, TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE, TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH, TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH, TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW, TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW, TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if (TIMER0 == timer_periph) { - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - - if (TIMER0 == timer_periph) { - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); - } - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - - if (TIMER0 == timer_periph) { - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); - } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &=(~(uint32_t)TIMER_CHCTL2_CH3EN); - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputstate) << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - - if (TIMER0 == timer_periph) { - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); - } - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM mode 0 - \arg TIMER_OC_MODE_PWM1: PWM mode 1 - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] pulse: channel output pulse value - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..41)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: TIMERx(x=0) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0 - \arg TIMER_CH_1: TIMER channel 1 - \arg TIMER_CH_2: TIMER channel 2 - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING, - TIMER_IC_POLARITY_BOTH_EDGE(only for TIMER1~TIMER8) - icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI, - TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, - TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch(channel){ - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel){ - case TIMER_CH_0: - /* read TIMER channel 0 capture compare register value */ - count_value = TIMER_CH0CV(timer_periph); - break; - case TIMER_CH_1: - /* read TIMER channel 1 capture compare register value */ - count_value = TIMER_CH1CV(timer_periph); - break; - case TIMER_CH_2: - /* read TIMER channel 2 capture compare register value */ - count_value = TIMER_CH2CV(timer_periph); - break; - case TIMER_CH_3: - /* read TIMER channel 3 capture compare register value */ - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0 - \arg TIMER_CH_1: TIMER channel 1 - \param[in] icpwm: TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING, TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI, TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1, TIMER_IC_PSC_DIV2, TIMER_IC_PSC_DIV4, - TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity){ - icpolarity = TIMER_IC_POLARITY_FALLING; - }else{ - icpolarity = TIMER_IC_POLARITY_RISING; - } - /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection){ - icselection = TIMER_IC_SELECTION_INDIRECTTI; - }else{ - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel){ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity<< 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - }else{ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode){ - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - }else if(TIMER_HALLINTERFACE_DISABLE == hallmode){ - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4)) - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4)) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4)) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4)) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4)) - \arg TIMER_SMCFG_TRGSEL_ETIFP: filtered external trigger input(TIMERx(x=0..4)) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..6)) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..6)) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..6)) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channel 0 as trigger output TRGO(TIMERx(x=0..4)) - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0 - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave){ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - }else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave){ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - }else{ - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity) -{ - /* configure the quadrature decoder mode */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - /* configure input capture selection */ - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - /* configure channel input capture polarity */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0..4) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0 - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1 - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2 - \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3 - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph, intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active low or falling edge active - \arg TIMER_IC_POLARITY_FALLING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger){ - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - }else{ - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph, extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0..4) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: specify which interrupt to enable - one or more parameters can be selected which are shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_CH3: channel 3 interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] interrupt: specify which interrupt to disbale - one or more parameters can be selected which are shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..6) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0) - \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] interrupt: the timer interrupt bits - one or more parameters can be selected which are shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0..6) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0..4) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0) - \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0) - \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: TIMERx(x=0..6) - \param[in] flag: the timer interrupt flags - one or more parameters can be selected which are shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0..6) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CMT: channel commutation flag, TIMERx(x=0) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0) - \arg TIMER_FLAG_BRK: break flag, TIMERx(x=0) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0..4) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0..4) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)flag); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c deleted file mode 100644 index 77c9a5159b..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_usart.c +++ /dev/null @@ -1,764 +0,0 @@ -/*! - \file gd32vf103_usart.c - \brief USART driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_usart.h" - -/*! - \brief reset USART/UART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph){ - case USART0: - /* reset USART0 */ - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - /* reset USART1 */ - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - case USART2: - /* reset USART2 */ - rcu_periph_reset_enable(RCU_USART2RST); - rcu_periph_reset_disable(RCU_USART2RST); - break; - case UART3: - /* reset UART3 */ - rcu_periph_reset_enable(RCU_UART3RST); - rcu_periph_reset_disable(RCU_UART3RST); - break; - case UART4: - /* reset UART4 */ - rcu_periph_reset_enable(RCU_UART4RST); - rcu_periph_reset_disable(RCU_UART4RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk=0U, intdiv=0U, fradiv=0U, udiv=0U; - switch(usart_periph){ - /* get clock frequency */ - case USART0: - /* get USART0 clock */ - uclk=rcu_clock_freq_get(CK_APB2); - break; - case USART1: - /* get USART1 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case USART2: - /* get USART2 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART3: - /* get UART3 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - case UART4: - /* get UART4 clock */ - uclk=rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk+baudval/2U)/baudval; - intdiv = udiv & (0x0000fff0U); - fradiv = udiv & (0x0000000fU); - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] paritycfg: configure USART parity - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg ; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5 bit, not available for UARTx(x=3,4) - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5 bits, not available for UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - /* configure USART stop bits */ - USART_CTL1(usart_periph) |= stblen; -} - -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: disable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_TEN; - ctl |= txconfig; - /* configure transfer mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL0(usart_periph); - ctl &= ~USART_CTL0_REN; - ctl |= rxconfig; - /* configure receiver mode */ - USART_CTL0(usart_periph) = ctl; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_DATA(usart_periph) = USART_DATA_DATA & data; -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); -} - -/*! - \brief configure the address of the USART in wake up by address match mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] addr: address of USART/UART - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & addr); -} - -/*! - \brief receiver in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_RWU; -} - -/*! - \brief receiver in active mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_RWU); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] wmethod: two methods be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mask - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief configure lin break frame length - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] lblen: lin break frame length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits - \arg USART_LBLEN_11B: 11 bits - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= (USART_CTL1_LBLEN & lblen); -} - -/*! - \brief send break frame - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_send_break(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_SBKCMD; -} - -/*! - \brief enable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half duplex mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable CK pin in synchronous mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_synchronous_clock_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] clen: CK length - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame - \arg USART_CLEN_EN: there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \Rag USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - uint32_t ctl = 0U; - - /* read USART_CTL1 register */ - ctl = USART_CTL1(usart_periph); - ctl &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - /* set CK length, CK phase, CK polarity */ - ctl |= (USART_CTL1_CLEN & clen) | (USART_CTL1_CPH & cph) | (USART_CTL1_CPL & cpl); - - USART_CTL1(usart_periph) = ctl; -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] gaut: guard time value - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph,uint32_t gaut) -{ - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((gaut)<<8)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0,1,2) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power mode - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] psc: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint8_t psc) -{ - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] irlp: IrDA low-power or normal - only one parameter can be selected which is shown as below: - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] rtsconfig: enable or disable RTS - only one parameter can be selected which is shown as below: - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_RTSEN; - ctl |= rtsconfig; - /* configure RTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1,2) - \param[in] ctsconfig: enable or disable CTS - only one parameter can be selected which is shown as below: - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_CTSEN; - ctl |= ctsconfig; - /* configure CTS */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for reception - only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENR; - ctl |= dmacmd; - /* configure DMA reception */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3) - \param[in] dmacmd: enable or disable DMA for transmission - only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - uint32_t ctl = 0U; - - ctl = USART_CTL2(usart_periph); - ctl &= ~USART_CTL2_DENT; - ctl |= dmacmd; - /* configure DMA transmission */ - USART_CTL2(usart_periph) = ctl; -} - -/*! - \brief get flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag - \arg USART_FLAG_TBE: transmit data buffer empty - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_IDLEF: IDLE frame detected flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_PERR: parity error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART flags, refer to usart_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_LBDF: LIN break detected flag - \arg USART_FLAG_TC: transmission complete - \arg USART_FLAG_RBNE: read data buffer not empty - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_REG_VAL(usart_periph, flag) &= ~BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) |= BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_TBE: transmitter buffer empty interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and overrun error interrupt - \arg USART_INT_IDLE: IDLE line detected interrupt - \arg USART_INT_LBD: LIN break detected interrupt - \arg USART_INT_ERR: error interrupt - \arg USART_INT_CTS: CTS interrupt - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, uint32_t int_flag) -{ - USART_REG_VAL(usart_periph, int_flag) &= ~BIT(USART_BIT_POS(int_flag)); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] int_flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_PERR: parity error interrupt and flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag - \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if(flagstatus && intenable){ - return SET; - }else{ - return RESET; - } -} - -/*! - \brief clear USART interrupt flag in STAT register - \param[in] usart_periph: USARTx(x=0,1,2)/UARTx(x=3,4) - \param[in] flag: USART interrupt flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_CTS: CTS change flag - \arg USART_INT_FLAG_LBD: LIN break detected flag - \arg USART_INT_FLAG_TC: transmission complete - \arg USART_INT_FLAG_RBNE: read data buffer not empty - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t flag) -{ - USART_REG_VAL2(usart_periph, flag) &= ~BIT(USART_BIT_POS2(flag)); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c deleted file mode 100644 index e441348602..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/Source/gd32vf103_wwdgt.c +++ /dev/null @@ -1,146 +0,0 @@ -/*! - \file gd32vf103_wwdgt.c - \brief WWDGT driver - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32vf103_wwdgt.h" - -/* write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) -/* write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00 - 0x7F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - uint32_t reg = 0U; - - reg = (WWDGT_CTL & (~WWDGT_CTL_CNT)); - reg |= CTL_CNT(counter_value); - - WWDGT_CTL = reg; -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00 - 0x7F - \param[in] window: 0x00 - 0x7F - \param[in] prescaler: wwdgt prescaler value - only one parameter can be selected which is shown as below: - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - uint32_t reg_cfg = 0U, reg_ctl = 0U; - - /* clear WIN and PSC bits, clear CNT bit */ - reg_cfg = (WWDGT_CFG &(~(WWDGT_CFG_WIN|WWDGT_CFG_PSC))); - reg_ctl = (WWDGT_CTL &(~WWDGT_CTL_CNT)); - - /* configure WIN and PSC bits, configure CNT bit */ - reg_cfg |= CFG_WIN(window); - reg_cfg |= prescaler; - reg_ctl |= CTL_CNT(counter); - - WWDGT_CTL = reg_ctl; - WWDGT_CFG = reg_cfg; -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if(WWDGT_STAT & WWDGT_STAT_EWIF){ - return SET; - } - - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (~WWDGT_STAT_EWIF); -} diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/gd32vf103.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/gd32vf103.h deleted file mode 100644 index 5bc3d94aec..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/gd32vf103.h +++ /dev/null @@ -1,230 +0,0 @@ -/*! - \file gd32vf103.h - \brief general definitions for GD32VF103 - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 -*/ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32VF103_H -#define GD32VF103_H - -#ifdef cplusplus - extern "C" { -#endif - - /* IO definitions (access restrictions to peripheral registers) */ - /** - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. - */ - #ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ - #else - #define __I volatile const /*!< Defines 'read only' permissions */ - #endif - #define __O volatile /*!< Defines 'write only' permissions */ - #define __IO volatile /*!< Defines 'read / write' permissions */ - - -#define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* define interrupt number */ -typedef enum IRQn -{ - CLIC_INT_RESERVED = 0, /*!< RISC-V reserved */ - CLIC_INT_SFT = 3, /*!< Software interrupt */ - CLIC_INT_TMR = 7, /*!< CPU Timer interrupt */ - CLIC_INT_BWEI = 17, /*!< Bus Error interrupt */ - CLIC_INT_PMOVI = 18, /*!< Performance Monitor */ - - /* interruput numbers */ - WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */ - LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */ - TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */ - RTC_IRQn = 22, /*!< RTC alarm interrupt */ - FMC_IRQn = 23, /*!< FMC interrupt */ - RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */ - EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */ - EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */ - EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */ - EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */ - EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */ - DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */ - DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */ - DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */ - DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */ - DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */ - DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */ - DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */ - ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */ - CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */ - CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */ - CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */ - CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */ - EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */ - TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */ - TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */ - TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */ - TIMER1_IRQn = 47, /*!< TIMER1 interrupt */ - TIMER2_IRQn = 48, /*!< TIMER2 interrupt */ - TIMER3_IRQn = 49, /*!< TIMER3 interrupts */ - I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */ - I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */ - I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */ - I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */ - SPI0_IRQn = 54, /*!< SPI0 interrupt */ - SPI1_IRQn = 55, /*!< SPI1 interrupt */ - USART0_IRQn = 56, /*!< USART0 interrupt */ - USART1_IRQn = 57, /*!< USART1 interrupt */ - USART2_IRQn = 58, /*!< USART2 interrupt */ - EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */ - RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */ - USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */ - - EXMC_IRQn = 67, /*!< EXMC global interrupt */ - - TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */ - SPI2_IRQn = 70, /*!< SPI2 global interrupt */ - UART3_IRQn = 71, /*!< UART3 global interrupt */ - UART4_IRQn = 72, /*!< UART4 global interrupt */ - TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */ - TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */ - DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */ - DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */ - DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */ - DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */ - DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */ - - CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */ - CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */ - CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */ - CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ - USBFS_IRQn = 86, /*!< USBFS global interrupt */ - - ECLIC_NUM_INTERRUPTS -} IRQn_Type; - -/* includes */ -#include "system_gd32vf103.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -typedef enum {RESET = 0, SET = 1,MAX = 0X7FFFFFFF} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ -#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ - -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ -#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ - -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ -#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ - -/* advanced peripheral bus 2 memory map */ -#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ - -/* advanced high performance bus 1 memory map */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ -#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ - -/* define marco USE_STDPERIPH_DRIVER */ -#if !defined USE_STDPERIPH_DRIVER -#define USE_STDPERIPH_DRIVER -#endif -#ifdef USE_STDPERIPH_DRIVER -#include "gd32vf103_libopt.h" -#endif /* USE_STDPERIPH_DRIVER */ - -#ifdef cplusplus -} -#endif -#endif diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.c b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.c deleted file mode 100644 index 613ef2fa75..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.c +++ /dev/null @@ -1,998 +0,0 @@ -/*! - \file system_gd32vf103.c - \brief RISC-V Device Peripheral Access Layer Source File for - GD32VF103 Device Series - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 - */ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - */ - -/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32vf103.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -/* select a system clock by uncommenting the following line */ -/* use IRC8M */ -//#define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000) -/********************************************************************/ -//#define __SYSTEM_CLOCK_HXTAL (HXTAL_VALUE) -//#define __SYSTEM_CLOCK_24M_PLL_HXTAL (uint32_t)(24000000) -/********************************************************************/ - -//#define __SYSTEM_CLOCK_36M_PLL_HXTAL (uint32_t)(36000000) -//#define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000) -//#define __SYSTEM_CLOCK_56M_PLL_HXTAL (uint32_t)(56000000) -//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000) -#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) - -#define SEL_IRC8M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLL 0x02U - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_48M_PLL_IRC8M -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M; -static void system_clock_48m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M; -static void system_clock_72m_irc8m(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M; -static void system_clock_108m_irc8m(void); - -#elif defined (__SYSTEM_CLOCK_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL; -static void system_clock_hxtal(void); -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_24M_PLL_HXTAL; -static void system_clock_24m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_36M_PLL_HXTAL; -static void system_clock_36m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL; -static void system_clock_48m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_56M_PLL_HXTAL; -static void system_clock_56m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL; -static void system_clock_96m_hxtal(void); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL; -static void system_clock_108m_hxtal(void); -#else -uint32_t SystemCoreClock = IRC8M_VALUE; -#endif /* __SYSTEM_CLOCK_48M_PLL_IRC8M */ - -/* configure the system clock */ -static void system_clock_config(void); - -/*! - \brief configure the system clock - \param[in] none - \param[out] none - \retval none - */ -static void system_clock_config(void) { -#ifdef __SYSTEM_CLOCK_HXTAL - system_clock_hxtal(); -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) - system_clock_24m_hxtal(); -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) - system_clock_36m_hxtal(); -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) - system_clock_48m_hxtal(); -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) - system_clock_56m_hxtal(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) - system_clock_72m_hxtal(); -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) - system_clock_96m_hxtal(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) - system_clock_108m_hxtal(); - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) - system_clock_48m_irc8m(); -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) - system_clock_72m_irc8m(); -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) - system_clock_108m_irc8m(); -#endif /* __SYSTEM_CLOCK_HXTAL */ -} - -/*! - \brief setup the microcontroller system, initialize the system - \param[in] none - \param[out] none - \retval none - */ -void SystemInit(void) { - /* reset the RCC clock configuration to the default reset state */ - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* reset SCS, AHBPSC, APB1PSC, APB2PSC, ADCPSC, CKOUT0SEL bits */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC - | RCU_CFG0_APB2PSC | - RCU_CFG0_ADCPSC | RCU_CFG0_ADCPSC_2 | RCU_CFG0_CKOUT0SEL); - - /* reset HXTALEN, CKMEN, PLLEN bits */ - RCU_CTL &= ~(RCU_CTL_HXTALEN | RCU_CTL_CKMEN | RCU_CTL_PLLEN); - - /* Reset HXTALBPS bit */ - RCU_CTL &= ~(RCU_CTL_HXTALBPS); - - /* reset PLLSEL, PREDV0_LSB, PLLMF, USBFSPSC bits */ - - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PREDV0_LSB | RCU_CFG0_PLLMF | - RCU_CFG0_USBFSPSC | RCU_CFG0_PLLMF_4); - RCU_CFG1 = 0x00000000U; - - /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */ - RCU_CTL &= ~(RCU_CTL_PLLEN | RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN - | RCU_CTL_HXTALEN); - /* disable all interrupts */ - RCU_INT = 0x00FF0000U; - - /* Configure the System clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */ - system_clock_config(); -} - -/*! - \brief update the SystemCoreClock with current core clock retrieved from cpu registers - \param[in] none - \param[out] none - \retval none - */ -void SystemCoreClockUpdate(void) { - uint32_t scss; - uint32_t pllsel, predv0sel, pllmf, ck_src; - uint32_t predv0, predv1, pll1mf; - - scss = GET_BITS(RCU_CFG0, 2, 3); - - switch (scss) { - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - SystemCoreClock = IRC8M_VALUE; - break; - - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - SystemCoreClock = HXTAL_VALUE; - break; - - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL); - - if (RCU_PLLSRC_IRC8M_DIV2 == pllsel) { - /* PLL clock source is IRC8M/2 */ - ck_src = IRC8M_VALUE / 2U; - } else { - /* PLL clock source is HXTAL */ - ck_src = HXTAL_VALUE; - - predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL); - - /* source clock use PLL1 */ - if (RCU_PREDV0SRC_CKPLL1 == predv0sel) { - predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U; - pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U; - if (17U == pll1mf) { - pll1mf = 20U; - } - ck_src = (ck_src / predv1) * pll1mf; - } - predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U; - ck_src /= predv0; - } - - /* PLL multiplication factor */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - - if ((RCU_CFG0 & RCU_CFG0_PLLMF_4)) { - pllmf |= 0x10U; - } - - if (pllmf >= 15U) { - pllmf += 1U; - } else { - pllmf += 2U; - } - - SystemCoreClock = ck_src * pllmf; - - if (15U == pllmf) { - /* PLL source clock multiply by 6.5 */ - SystemCoreClock = ck_src * 6U + ck_src / 2U; - } - - break; - - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } -} - -#ifdef __SYSTEM_CLOCK_HXTAL -/*! - \brief configure the system clock to HXTAL - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* select HXTAL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_HXTAL; - - /* wait until HXTAL is selected as system clock */ - while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_24M_PLL_HXTAL) -/*! - \brief configure the system clock to 24M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_24m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 6 = 24 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL6); - - if(HXTAL_VALUE==25000000){ - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } - - }else if(HXTAL_VALUE==8000000){ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_36M_PLL_HXTAL) -/*! - \brief configure the system clock to 36M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_36m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 9 = 36 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9); - - if(HXTAL_VALUE==25000000){ - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } - - }else if(HXTAL_VALUE==8000000){ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL) -/*! - \brief configure the system clock to 48M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL12); - - if(HXTAL_VALUE==25000000){ - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } - - }else if(HXTAL_VALUE==8000000){ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); - } - - - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_56M_PLL_HXTAL) -/*! - \brief configure the system clock to 56M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_56m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 14 = 56 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL14); - - if(HXTAL_VALUE==25000000){ - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } - - }else if(HXTAL_VALUE==8000000){ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -/*! - \brief configure the system clock to 72M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL18); - - - if(HXTAL_VALUE==25000000){ - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } - - }else if(HXTAL_VALUE==8000000){ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL) -/*! - \brief configure the system clock to 96M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_96m_hxtal(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - }while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){ - while(1){ - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - if(HXTAL_VALUE==25000000){ - - /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); - - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10); - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while((RCU_CTL & RCU_CTL_PLL1STB) == 0){ - } - - }else if(HXTAL_VALUE==8000000){ - /* CK_PLL = (CK_PREDIV0) * 24 = 96 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL24); - - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 ); - } - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL) -/*! - \brief configure the system clock to 108M by PLL which selects HXTAL(MD/HD/XD:8M; CL:25M) as its clock source - \param[in] none - \param[out] none - \retval none - */ - -static void system_clock_108m_hxtal(void) { - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable HXTAL */ - RCU_CTL |= RCU_CTL_HXTALEN; - - /* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */ - do { - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB); - } while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) { - while (1) { - } - } - - /* HXTAL is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27); - - if (HXTAL_VALUE == 25000000) { - /* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */ - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF - | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 - | RCU_PREDV0_DIV10); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) { - } - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL2EN; - /* wait till PLL1 is ready */ - while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) { - } - } else if (HXTAL_VALUE == 8000000) { - RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF - | RCU_CFG1_PREDV0); - RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 - | RCU_PLL1_MUL20 | RCU_PLL2_MUL20); - - /* enable PLL1 */ - RCU_CTL |= RCU_CTL_PLL1EN; - /* wait till PLL1 is ready */ - while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) { - } - - /* enable PLL2 */ - RCU_CTL |= RCU_CTL_PLL2EN; - /* wait till PLL1 is ready */ - while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) { - } - - } - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) { - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) { - } -} - -#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M) -/*! - \brief configure the system clock to 48M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_48m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL12; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M) -/*! - \brief configure the system clock to 72M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_72m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL18; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M) -/*! - \brief configure the system clock to 108M by PLL which selects IRC8M as its clock source - \param[in] none - \param[out] none - \retval none -*/ -static void system_clock_108m_irc8m(void) -{ - uint32_t timeout = 0U; - uint32_t stab_flag = 0U; - - /* enable IRC8M */ - RCU_CTL |= RCU_CTL_IRC8MEN; - - /* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */ - do{ - timeout++; - stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB); - } - while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout)); - - /* if fail */ - if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){ - while(1){ - } - } - - /* IRC8M is stable */ - /* AHB = SYSCLK */ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV1; - /* APB2 = AHB/1 */ - RCU_CFG0 |= RCU_APB2_CKAHB_DIV1; - /* APB1 = AHB/2 */ - RCU_CFG0 |= RCU_APB1_CKAHB_DIV2; - - /* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */ - RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4); - RCU_CFG0 |= RCU_PLL_MUL27; - - /* enable PLL */ - RCU_CTL |= RCU_CTL_PLLEN; - - /* wait until PLL is stable */ - while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){ - } - - /* select PLL as system clock */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CFG0 |= RCU_CKSYSSRC_PLL; - - /* wait until PLL is selected as system clock */ - while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){ - } -} - -#endif diff --git a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.h b/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.h deleted file mode 100644 index a31319bd75..0000000000 --- a/bsp/gd32vf103v-eval/libraries/GD32VF103_standard_peripheral/system_gd32vf103.h +++ /dev/null @@ -1,60 +0,0 @@ -/*! - \file system_gd32vf103.h - \brief RISC-V Device Peripheral Access Layer Header File for - GD32VF103 Device Series - - \version 2019-6-5, V1.0.0, firmware for GD32VF103 - */ - -/* - Copyright (c) 2019, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, - are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - OF SUCH DAMAGE. - */ - -/* This file refers the RISC-V standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32VF103_H -#define SYSTEM_GD32VF103_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit(void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32VF103_H */ diff --git a/bsp/gd32vf103v-eval/libraries/SConscript b/bsp/gd32vf103v-eval/libraries/SConscript deleted file mode 100644 index d8ee90a4ae..0000000000 --- a/bsp/gd32vf103v-eval/libraries/SConscript +++ /dev/null @@ -1,22 +0,0 @@ -# RT-Thread building script for component - -Import('rtconfig') -Import('RTT_ROOT') -from building import * - -cwd = GetCurrentDir() - -src = Glob('GD32VF103_standard_peripheral/Source/*.c') -src += Glob('n22/env_Eclipse/*.c') -src += ['GD32VF103_standard_peripheral/system_gd32vf103.c', - 'n22/drivers/n22_func.c', - 'n22/env_Eclipse/start.S', - 'n22/env_Eclipse/entry.S'] - -CPPPATH = [ cwd + '/GD32VF103_standard_peripheral/Include', - cwd + '/GD32VF103_standard_peripheral', - cwd + '/n22/drivers'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/core_v5.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/core_v5.h deleted file mode 100644 index 3ce586e90e..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/core_v5.h +++ /dev/null @@ -1,127 +0,0 @@ -#ifndef __CORE_V5_H__ -#define __CORE_V5_H__ - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_HPP 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_PUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS64_SD 0x8000000000000000 - -#if __riscv_xlen == 64 -#define MCAUSE_INT 0x8000000000000000UL -#define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL -#else -#define MCAUSE_INT 0x80000000UL -#define MCAUSE_CAUSE 0x7FFFFFFFUL -#endif - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -/* Machine mode MCAUSE */ -#define TRAP_M_I_ACC_FAULT 1 /* Instruction access fault */ -#define TRAP_M_L_ACC_FAULT 5 /* Data load access fault */ -#define TRAP_M_S_ACC_FAULT 7 /* Data store access fault */ -#define TRAP_U_ECALL 8 -#define TRAP_S_ECALL 9 -#define TRAP_H_ECALL 10 -#define TRAP_M_ECALL 11 -#define TRAP_M_I_PAGE_FAULT 12 /* Instruction page fault */ -#define TRAP_M_L_PAGE_FAULT 13 /* Data load page fault */ -#define TRAP_M_S_PAGE_FAULT 15 /* Data store page fault */ -#define TRAP_M_STACKOVF 32 -#define TRAP_M_STACKUDF 33 - -/* Supervisor mode SCAUSE */ -#define TRAP_S_I_ACC_FAULT 1 /* Instruction access fault */ -#define TRAP_S_L_ACC_FAULT 5 /* Data load access fault */ -#define TRAP_S_S_ACC_FAULT 7 /* Data store access fault */ -#define TRAP_S_I_PAGE_FAULT 12 /* Instruction page fault */ -#define TRAP_S_L_PAGE_FAULT 13 /* Data load page fault */ -#define TRAP_S_S_PAGE_FAULT 15 /* Data store page fault */ - -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) - -/* MILMB and MDLMB */ -#define MILMB_IEN (0x1UL) -#define MDLMB_DEN (0x1UL) - -#if __riscv_xlen == 64 -# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LWU lwu -# define LOG_REGBYTES 3 -#else -# define SLL32 sll -# define STORE sw -# define LOAD lw -# define LWU lw -# define LOG_REGBYTES 2 -#endif -#define REGBYTES (1 << LOG_REGBYTES) - -#if __riscv_flen == 64 -# define FPSTORE fsd -# define FPLOAD fld -# define LOG_FPREGBYTES 3 -#else -# define FPSTORE fsw -# define FPLOAD flw -# define LOG_FPREGBYTES 2 -#endif -#define FPREGBYTES (1 << LOG_FPREGBYTES) - -#define STR(S) #S -#define XSTR(S) STR(S) - -#define PUSH XSTR(STORE) -#define POP XSTR(LOAD) -#define REGSIZE XSTR(REGBYTES) -#define FPPUSH XSTR(FPSTORE) -#define FPPOP XSTR(FPLOAD) -#define FPREGSIZE XSTR(FPREGBYTES) - -#ifndef __ASSEMBLER__ - - -#define read_csr(reg) __nds__csrr(reg) -#define write_csr(reg, val) __nds__csrw(val, reg) -#define swap_csr(reg, val) __nds__csrrw(val, reg) -#define set_csr(reg, bit) __nds__csrrs(bit, reg) -#define clear_csr(reg, bit) __nds__csrrc(bit, reg) - -#endif - -#endif // __CORE_V5_H__ diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_eclic.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_eclic.h deleted file mode 100644 index a91c3aafc4..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_eclic.h +++ /dev/null @@ -1,47 +0,0 @@ -// See LICENSE file for licence details - -#ifndef N22_ECLIC_H -#define N22_ECLIC_H -#include - -#define ECLICINTCTLBITS 4 - -//ECLIC memory map -// Offset -// 0x0000 1B RW ecliccfg -#define ECLIC_CFG_OFFSET 0x0 -// 0x0004 4B R eclicinfo -#define ECLIC_INFO_OFFSET 0x4 -// 0x000B 1B RW mintthresh -#define ECLIC_MTH_OFFSET 0xB -// -// 0x1000+4*i 1B/input RW eclicintip[i] -#define ECLIC_INT_IP_OFFSET _AC(0x1000,UL) -// 0x1001+4*i 1B/input RW eclicintie[i] -#define ECLIC_INT_IE_OFFSET _AC(0x1001,UL) -// 0x1002+4*i 1B/input RW eclicintattr[i] -#define ECLIC_INT_ATTR_OFFSET _AC(0x1002,UL) - -#define ECLIC_INT_ATTR_SHV 0x01 -#define ECLIC_INT_ATTR_TRIG_LEVEL 0x00 -#define ECLIC_INT_ATTR_TRIG_EDGE 0x02 -#define ECLIC_INT_ATTR_TRIG_POS 0x00 -#define ECLIC_INT_ATTR_TRIG_NEG 0x04 - -// 0x1003+4*i 1B/input RW eclicintctl[i] -#define ECLIC_INT_CTRL_OFFSET _AC(0x1003,UL) -// -// ... -// -#define ECLIC_ADDR_BASE 0xd2000000 - - -#define ECLIC_CFG_NLBITS_MASK _AC(0x1E,UL) -#define ECLIC_CFG_NLBITS_LSB (1u) - -#define MSIP_HANDLER eclic_msip_handler -#define MTIME_HANDLER eclic_mtip_handler -#define BWEI_HANDLER eclic_bwei_handler -#define PMOVI_HANDLER eclic_pmovi_handler - -#endif diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.c b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.c deleted file mode 100644 index 1f89ffd8da..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.c +++ /dev/null @@ -1,279 +0,0 @@ -// See LICENSE for license details. -#include -#include -#include -#include -#include - -#include "riscv_encoding.h" -#include "n22_func.h" - -void switch_m2u_mode() { - clear_csr(mstatus, MSTATUS_MPP); - //printf("\nIn the m2u function, the mstatus is 0x%x\n", read_csr(mstatus)); - //printf("\nIn the m2u function, the mepc is 0x%x\n", read_csr(mepc)); - asm volatile ("la x6, 1f ":::"x6"); - asm volatile ("csrw mepc, x6":::); - asm volatile ("mret":::); - asm volatile ("1:":::); -} - -uint32_t mtime_lo(void) { - return *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME); -} - -uint32_t mtime_hi(void) { - return *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 4); -} - -void enable_timer_interrupt(void) { - *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xffc) = 1; -} - -void clear_timer_interrupt(void) { - *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xffc) = 0; -} - -void close_timer(void) { - *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xff8) = 1; -} - -void open_timer(void) { - *(volatile uint32_t *) (TMR_CTRL_ADDR + TMR_MTIME + 0xff8) = 0; -} - -uint64_t get_timer_value() { - while (1) { - uint32_t hi = mtime_hi(); - uint32_t lo = mtime_lo(); - - if (hi == mtime_hi()) - return ((uint64_t) hi << 32) | lo; - } -} - -uint32_t get_timer_freq() { - return TMR_FREQ; -} - -uint64_t get_instret_value() { - while (1) { - uint32_t hi = read_csr(minstreth); - uint32_t lo = read_csr(minstret); - if (hi == read_csr(minstreth)) - return ((uint64_t) hi << 32) | lo; - } -} - -uint64_t get_cycle_value() { - while (1) { - uint32_t hi = read_csr(mcycleh); - uint32_t lo = read_csr(mcycle); - if (hi == read_csr(mcycleh)) - return ((uint64_t) hi << 32) | lo; - } -} -// Note that there are no assertions or bounds checking on these -// parameter values. - -void eclic_init(uint32_t num_irq) { - typedef volatile uint32_t vuint32_t; - - //clear cfg register - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET) = 0; - - //clear minthresh register - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET) = 0; - - //clear all IP/IE/ATTR/CTRL bits for all interrupt sources - vuint32_t * ptr; - - vuint32_t * base = (vuint32_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET); - vuint32_t * upper = (vuint32_t*) (base + num_irq * 4); - - for (ptr = base; ptr < upper; ptr = ptr + 4) { - *ptr = 0; - } - eclic_set_nlbits(ECLIC_GROUP_LEVEL2_PRIO2); -} - -void eclic_enable_interrupt(uint32_t source) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IE_OFFSET + source * 4) = - 1; -} - -void eclic_disable_interrupt(uint32_t source) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IE_OFFSET + source * 4) = - 0; -} - -void eclic_set_pending(uint32_t source) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET + source * 4) = - 1; -} - -void eclic_clear_pending(uint32_t source) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_IP_OFFSET + source * 4) = - 0; -} - -void eclic_set_intctrl(uint32_t source, uint8_t intctrl) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_CTRL_OFFSET + source * 4) = - intctrl; -} - -uint8_t eclic_get_intctrl(uint32_t source) { - return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_CTRL_OFFSET - + source * 4); -} - -void eclic_set_intattr(uint32_t source, uint8_t intattr) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_ATTR_OFFSET + source * 4) = - intattr; -} - -uint8_t eclic_get_intattr(uint32_t source) { - return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_INT_ATTR_OFFSET - + source * 4); -} - -void eclic_set_ecliccfg(uint8_t ecliccfg) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET) = ecliccfg; -} - -uint8_t eclic_get_ecliccfg() { - return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_CFG_OFFSET); -} - -void eclic_set_mth(uint8_t mth) { - *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET) = mth; -} - -uint8_t eclic_get_mth() { - return *(volatile uint8_t*) (ECLIC_ADDR_BASE + ECLIC_MTH_OFFSET); -} - -void eclic_set_nlbits(uint8_t nlbits) { - //shift nlbits to correct position - uint8_t nlbits_shifted = nlbits << ECLIC_CFG_NLBITS_LSB; - - //read the current ecliccfg - uint8_t old_ecliccfg = eclic_get_ecliccfg(); - uint8_t new_ecliccfg = (old_ecliccfg & (~ECLIC_CFG_NLBITS_MASK)) - | (ECLIC_CFG_NLBITS_MASK & nlbits_shifted); - - eclic_set_ecliccfg(new_ecliccfg); -} - -uint8_t eclic_get_nlbits(void) { - //extract nlbits - uint8_t nlbits = eclic_get_ecliccfg(); - nlbits = (nlbits & ECLIC_CFG_NLBITS_MASK) >> ECLIC_CFG_NLBITS_LSB; - return nlbits; -} - -//sets an interrupt level based encoding of nlbits and ECLICINTCTLBITS -uint8_t eclic_set_int_level(uint32_t source, uint8_t level) { - //extract nlbits - uint8_t nlbits = eclic_get_nlbits(); - if (nlbits > ECLICINTCTLBITS) { - nlbits = ECLICINTCTLBITS; - } - - //shift level into correct bit position - level = level << (8 - nlbits); - - //write to eclicintctrl - uint8_t current_intctrl = eclic_get_intctrl(source); - //shift intctrl left to mask off unused bits - current_intctrl = current_intctrl << nlbits; - //shift intctrl into correct bit position - current_intctrl = current_intctrl >> nlbits; - - eclic_set_intctrl(source, (current_intctrl | level)); - - return level; -} - -//gets an interrupt level based encoding of nlbits -uint8_t eclic_get_int_level(uint32_t source) { - //extract nlbits - uint8_t nlbits = eclic_get_nlbits(); - if (nlbits > ECLICINTCTLBITS) { - nlbits = ECLICINTCTLBITS; - } - - uint8_t intctrl = eclic_get_intctrl(source); - - //shift intctrl - intctrl = intctrl >> (8 - nlbits); - //shift intctrl - uint8_t level = intctrl << (8 - nlbits); - - return level; -} - -//sets an interrupt priority based encoding of nlbits and ECLICINTCTLBITS -uint8_t eclic_set_int_priority(uint32_t source, uint8_t priority) { - //extract nlbits - uint8_t nlbits = eclic_get_nlbits(); - if (nlbits >= ECLICINTCTLBITS) { - nlbits = ECLICINTCTLBITS; - return 0; - } - - //shift priority into correct bit position - priority = priority << (8 - ECLICINTCTLBITS); - - //write to eclicintctrl - uint8_t current_intctrl = eclic_get_intctrl(source); - //shift intctrl right to mask off unused bits - current_intctrl = current_intctrl >> (8 - nlbits); - //shift intctrl into correct bit position - current_intctrl = current_intctrl << (8 - nlbits); - - eclic_set_intctrl(source, (current_intctrl | priority)); - - return priority; -} - -//gets an interrupt priority based encoding of nlbits -uint8_t eclic_get_int_priority(uint32_t source) { - //extract nlbits - uint8_t nlbits = eclic_get_nlbits(); - if (nlbits > ECLICINTCTLBITS) { - nlbits = ECLICINTCTLBITS; - } - - uint8_t intctrl = eclic_get_intctrl(source); - - //shift intctrl - intctrl = intctrl << nlbits; - //shift intctrl - uint8_t priority = intctrl >> (nlbits + (8 - ECLICINTCTLBITS)); - - return priority; -} - -void eclic_mode_enable() { - uint32_t mtvec_value = read_csr(mtvec); - mtvec_value = mtvec_value & 0xFFFFFFC0; - mtvec_value = mtvec_value | 0x00000003; - write_csr(mtvec, mtvec_value); -} - -void eclic_set_shv(uint32_t source, uint8_t shv) { - uint8_t attr = eclic_get_intattr(source); - if (shv) { - attr |= 0x01; - eclic_set_intattr(source, attr); - } -} - -void eclic_set_trig(uint32_t source, uint8_t trig) { - uint8_t attr = eclic_get_intattr(source); - if ((trig & 0x1)) { - attr |= (trig << 1); - eclic_set_intattr(source, attr); - } -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.h deleted file mode 100644 index 614efebec0..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_func.h +++ /dev/null @@ -1,82 +0,0 @@ -// See LICENSE file for licence details - -#ifndef N22_FUNC_H -#define N22_FUNC_H - - -#include "n22_tmr.h" -#include "n22_eclic.h" - -#define ECLIC_GROUP_LEVEL0_PRIO4 0 -#define ECLIC_GROUP_LEVEL1_PRIO3 1 -#define ECLIC_GROUP_LEVEL2_PRIO2 2 -#define ECLIC_GROUP_LEVEL3_PRIO1 3 -#define ECLIC_GROUP_LEVEL4_PRIO0 4 - -void switch_m2u_mode(); -uint32_t get_tmr_freq(); -uint32_t mtime_lo(void); -uint32_t mtime_hi(void); -uint64_t get_timer_value(); -uint64_t get_instret_value(); -uint64_t get_cycle_value(); - -void eclic_init(uint32_t num_irq); - -void eclic_enable_interrupt(uint32_t source); -void eclic_disable_interrupt(uint32_t source); - -void eclic_set_pending(uint32_t source); -void eclic_clear_pending(uint32_t source); - -void eclic_set_intctrl(uint32_t source, uint8_t intctrl); -uint8_t eclic_get_intctrl(uint32_t source); - -void eclic_set_intattr(uint32_t source, uint8_t intattr); -uint8_t eclic_get_intattr(uint32_t source); - -void eclic_set_ecliccfg(uint8_t ecliccfg); -uint8_t eclic_get_ecliccfg(); - -void eclic_set_mth(uint8_t mth); -uint8_t eclic_get_mth(); - -void eclic_set_nlbits(uint8_t nlbits); -uint8_t eclic_get_nlbits(); - -uint8_t eclic_set_int_level(uint32_t source, uint8_t level); -uint8_t eclic_get_int_level(uint32_t source); - -uint8_t eclic_set_int_priority(uint32_t source, uint8_t priority); -uint8_t eclic_get_int_priority(uint32_t source); - -void eclic_mode_enable(); -void eclic_set_shv(uint32_t source, uint8_t shv); -void eclic_set_trig(uint32_t source, uint8_t trig); - -///** \brief Wait For Interrupt -// -// Wait For Interrupt is a hint instruction that suspends execution -// until one of a number of events occurs. -// */ -__attribute__( ( always_inline ) ) static inline void __WFI(void) { - __asm volatile ("wfi"); -} -// -// -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static inline void __WFE(void) -{ - __asm volatile ("wfi"); -} - -void close_timer(void); -void open_timer(void); -void enable_timer_interrupt(void); -void clear_timer_interrupt(void); - -#endif diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_tmr.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_tmr.h deleted file mode 100644 index 2645f73304..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/n22_tmr.h +++ /dev/null @@ -1,17 +0,0 @@ -// See LICENSE file for licence details - -#ifndef N22_TMR_H -#define N22_TMR_H - -#define TMR_MSIP 0xFFC -#define TMR_MSIP_size 0x4 -#define TMR_MTIMECMP 0x8 -#define TMR_MTIMECMP_size 0x8 -#define TMR_MTIME 0x0 -#define TMR_MTIME_size 0x8 - -#define TMR_CTRL_ADDR 0xd1000000 -#define TMR_REG(offset) _REG32(TMR_CTRL_ADDR, offset) -#define TMR_FREQ ((uint32_t)SystemCoreClock/4) //units HZ - -#endif diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_bits.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_bits.h deleted file mode 100644 index bfe656feb0..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_bits.h +++ /dev/null @@ -1,36 +0,0 @@ -// See LICENSE for license details. -#ifndef _RISCV_BITS_H -#define _RISCV_BITS_H - -#define likely(x) __builtin_expect((x), 1) -#define unlikely(x) __builtin_expect((x), 0) - -#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) -#define ROUNDDOWN(a, b) ((a)/(b)*(b)) - -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) - -#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) -#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) - -#define STR(x) XSTR(x) -#define XSTR(x) #x - -#if __riscv_xlen == 64 -# define SLL32 sllw -# define STORE sd -# define LOAD ld -# define LWU lwu -# define LOG_REGBYTES 3 -#else -# define SLL32 sll -# define STORE sw -# define LOAD lw -# define LWU lw -# define LOG_REGBYTES 2 -#endif -#define REGBYTES (1 << LOG_REGBYTES) - -#endif diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_const.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_const.h deleted file mode 100644 index d5dec8acaa..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_const.h +++ /dev/null @@ -1,18 +0,0 @@ -// See LICENSE for license details. -/* Derived from */ - -#ifndef _RISCV_CONST_H -#define _RISCV_CONST_H - -#ifdef __ASSEMBLER__ -#define _AC(X,Y) X -#define _AT(T,X) X -#else -#define _AC(X,Y) (X##Y) -#define _AT(T,X) ((T)(X)) -#endif /* !__ASSEMBLER__*/ - -#define _BITUL(x) (_AC(1,UL) << (x)) -#define _BITULL(x) (_AC(1,ULL) << (x)) - -#endif /* _NUCLEI_CONST_H */ diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_encoding.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_encoding.h deleted file mode 100644 index 6f0ac416ca..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/riscv_encoding.h +++ /dev/null @@ -1,1342 +0,0 @@ -// See LICENSE for license details. - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_PUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_PUM 0x00040000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) - -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) - -#define MIE_SSIE MIP_SSIP -#define MIE_HSIE MIP_HSIP -#define MIE_MSIE MIP_MSIP -#define MIE_STIE MIP_STIP -#define MIE_HTIE MIP_HTIP -#define MIE_MTIE MIP_MTIP -#define MIE_SEIE MIP_SEIP -#define MIE_HEIE MIP_HEIP -#define MIE_MEIE MIP_MEIP - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define VM_MBARE 0 -#define VM_MBB 1 -#define VM_MBBID 2 -#define VM_SV32 8 -#define VM_SV39 9 -#define VM_SV48 10 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define DEFAULT_NMIVEC 0x00001004 -#define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Accessed -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#ifdef __riscv64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse-opcodes */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_HRET 0x20200073 -#define MASK_HRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VM 0x10400073 -#define MASK_SFENCE_VM 0xfff07fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 -#define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 -#define CSR_MIP 0x344 -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f - -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 - -#define CSR_MNVEC 0x7C3 - -#define CSR_MIRQ_ENTRY 0x7EC -#define CSR_MINTSEL_JAL 0x7ED -#define CSR_PUSHMCAUSE 0x7EE -#define CSR_PUSHMEPC 0x7EF -#define CSR_PUSHMXSTATUS 0x7EB -#define CSR_WFE 0x810 -#define CSR_SLEEPVALUE 0x811 -#define CSR_TXEVT 0x812 - -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MXSTATUS 0x7c4 - - -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -#endif diff --git a/bsp/gd32vf103v-eval/libraries/n22/drivers/sections.h b/bsp/gd32vf103v-eval/libraries/n22/drivers/sections.h deleted file mode 100644 index 6e1f0518bc..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/drivers/sections.h +++ /dev/null @@ -1,17 +0,0 @@ -// See LICENSE for license details. -#ifndef _SECTIONS_H -#define _SECTIONS_H - -extern unsigned char _rom[]; -extern unsigned char _rom_end[]; - -extern unsigned char _ram[]; -extern unsigned char _ram_end[]; - -extern unsigned char _ftext[]; -extern unsigned char _etext[]; -extern unsigned char _fbss[]; -extern unsigned char _ebss[]; -extern unsigned char _end[]; - -#endif /* _SECTIONS_H */ diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds deleted file mode 100644 index 709ed76361..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x4.lds +++ /dev/null @@ -1,175 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -ENTRY( _start ) - -MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 16k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 6k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 4k - ram (wxa!ri) : ORIGIN = 0x20001000, LENGTH = 2K -*/ -} - - -SECTIONS -{ - __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; - - - .init : - { - KEEP (*(SORT_NONE(.init))) - } >flash AT>flash - - .ilalign : - { - . = ALIGN(4); - PROVIDE( _ilm_lma = . ); - } >flash AT>flash - - .ialign : - { - PROVIDE( _ilm = . ); - } >flash AT>flash - - .text : - { - *(.rodata .rodata.*) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >flash AT>flash - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash - - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .);/*0x80022c8*/ - PROVIDE (etext = .);/*0x80022c8*/ - PROVIDE( _eilm = . ); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >flash AT>flash - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >flash AT>flash - - . = ALIGN(4); - PROVIDE( _eilm = . ); - - .lalign : - { - . = ALIGN(4); - PROVIDE( _data_lma = . ); - } >flash AT>flash - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >ram AT>flash - - - .data : - { - *(.rdata) - - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram AT>flash - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram AT>ram - - . = ALIGN(8); - PROVIDE( _end = . ); /*0X2000,0340*/ - PROVIDE( end = . ); - - .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds deleted file mode 100644 index 6d2e894d28..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x6.lds +++ /dev/null @@ -1,175 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -ENTRY( _start ) - -MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 32k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 10k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 7k - ram (wxa!ri) : ORIGIN = 0x20001C00, LENGTH = 3K -*/ -} - - -SECTIONS -{ - __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; - - - .init : - { - KEEP (*(SORT_NONE(.init))) - } >flash AT>flash - - .ilalign : - { - . = ALIGN(4); - PROVIDE( _ilm_lma = . ); - } >flash AT>flash - - .ialign : - { - PROVIDE( _ilm = . ); - } >flash AT>flash - - .text : - { - *(.rodata .rodata.*) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >flash AT>flash - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash - - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .);/*0x80022c8*/ - PROVIDE (etext = .);/*0x80022c8*/ - PROVIDE( _eilm = . ); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >flash AT>flash - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >flash AT>flash - - . = ALIGN(4); - PROVIDE( _eilm = . ); - - .lalign : - { - . = ALIGN(4); - PROVIDE( _data_lma = . ); - } >flash AT>flash - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >ram AT>flash - - - .data : - { - *(.rdata) - - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram AT>flash - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram AT>ram - - . = ALIGN(8); - PROVIDE( _end = . ); /*0X2000,0340*/ - PROVIDE( end = . ); - - .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds deleted file mode 100644 index 36563311b6..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103x8.lds +++ /dev/null @@ -1,175 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -ENTRY( _start ) - -MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 64k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 20k - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 15k - ram (wxa!ri) : ORIGIN = 0x20003C00, LENGTH = 5K -*/ -} - - -SECTIONS -{ - __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; - - - .init : - { - KEEP (*(SORT_NONE(.init))) - } >flash AT>flash - - .ilalign : - { - . = ALIGN(4); - PROVIDE( _ilm_lma = . ); - } >flash AT>flash - - .ialign : - { - PROVIDE( _ilm = . ); - } >flash AT>flash - - .text : - { - *(.rodata .rodata.*) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >flash AT>flash - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash - - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .);/*0x80022c8*/ - PROVIDE (etext = .);/*0x80022c8*/ - PROVIDE( _eilm = . ); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >flash AT>flash - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >flash AT>flash - - . = ALIGN(4); - PROVIDE( _eilm = . ); - - .lalign : - { - . = ALIGN(4); - PROVIDE( _data_lma = . ); - } >flash AT>flash - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >ram AT>flash - - - .data : - { - *(.rdata) - - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram AT>flash - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram AT>ram - - . = ALIGN(8); - PROVIDE( _end = . ); /*0X2000,0340*/ - PROVIDE( end = . ); - - .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds deleted file mode 100644 index cc20d133a0..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB.lds +++ /dev/null @@ -1,200 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -ENTRY( _start ) - -MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k - ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K -*/ -} - - -SECTIONS -{ - __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; - - - .init : - { - KEEP (*(SORT_NONE(.init))) - } >flash AT>flash - - .ilalign : - { - . = ALIGN(4); - PROVIDE( _ilm_lma = . ); - } >flash AT>flash - - .ialign : - { - PROVIDE( _ilm = . ); - } >flash AT>flash - - .text : - { - *(.rodata .rodata.*) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - /* section information for initial. */ - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - } >flash AT>flash - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash - - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .);/*0x80022c8*/ - PROVIDE (etext = .);/*0x80022c8*/ - PROVIDE( _eilm = . ); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >flash AT>flash - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >flash AT>flash - - . = ALIGN(4); - PROVIDE( _eilm = . ); - - .lalign : - { - . = ALIGN(4); - PROVIDE( _data_lma = . ); - } >flash AT>flash - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >ram AT>flash - - - .data : - { - *(.rdata) - - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram AT>flash - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram AT>ram - - . = ALIGN(8); - PROVIDE( _end = . ); /*0X2000,0340*/ - PROVIDE( end = . ); - - .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - PROVIDE( __rt_rvstack = .); - } >ram AT>ram -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds deleted file mode 100644 index cfb0b88107..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/GD32VF103xB_I2S.lds +++ /dev/null @@ -1,182 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -ENTRY( _start ) - -MEMORY -{ - /* Run in FLASH */ - flash (rxai!w) : ORIGIN = 0x08000000, LENGTH = 128k - ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 32K - - /* Run in RAM */ -/* flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 24k - ram (wxa!ri) : ORIGIN = 0x20006000, LENGTH = 8K -*/ -} - - -SECTIONS -{ - __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; - - - .init : - { - KEEP (*(SORT_NONE(.init))) - } >flash AT>flash - - .ilalign : - { - . = ALIGN(4); - PROVIDE( _ilm_lma = . ); - } >flash AT>flash - - .ialign : - { - PROVIDE( _ilm = . ); - } >flash AT>flash - - .PrgData ALIGN(0x08004000,4) : AT(ALIGN(0x08004000,4)) - { - KEEP(*(.PrgData)) - } - - .text : - { - *(.rodata .rodata.*) - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - *(.sdata2 .sdata2. *) - } >flash AT>flash - - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash - - . = ALIGN(4); - - PROVIDE (__etext = .); - PROVIDE (_etext = .);/*0x80022c8*/ - PROVIDE (etext = .);/*0x80022c8*/ - PROVIDE( _eilm = . ); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >flash AT>flash - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >flash AT>flash - - . = ALIGN(4); - PROVIDE( _eilm = . ); - - .lalign : - { - . = ALIGN(4); - PROVIDE( _data_lma = . ); - } >flash AT>flash - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >ram AT>flash - - - .data : - { - *(.rdata) - - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram AT>flash - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); /*0X200052A0 0X200002A0*/ - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram AT>ram - - . = ALIGN(8); - PROVIDE( _end = . ); /*0X2000,0340*/ - PROVIDE( end = . ); - - .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/entry.S b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/entry.S deleted file mode 100644 index f6b18aa71b..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/entry.S +++ /dev/null @@ -1,204 +0,0 @@ -// See LICENSE for license details - -#ifndef ENTRY_S -#define ENTRY_S - -#include "riscv_encoding.h" -#include "riscv_bits.h" -#include "n22_eclic.h" -#include "n22_tmr.h" - -############################################### -############################################### -# Disable Interrupt -# -.macro DISABLE_MIE - csrc CSR_MSTATUS, MSTATUS_MIE -.endm - - -############################################### -############################################### -#Save caller registers -.macro SAVE_CONTEXT - - STORE x1, 0*REGBYTES(sp) - STORE x5, 1*REGBYTES(sp) - STORE x6, 2*REGBYTES(sp) - STORE x7, 3*REGBYTES(sp) - STORE x10, 4*REGBYTES(sp) - STORE x11, 5*REGBYTES(sp) - STORE x12, 6*REGBYTES(sp) - STORE x13, 7*REGBYTES(sp) - STORE x14, 8*REGBYTES(sp) - STORE x15, 9*REGBYTES(sp) - STORE x16, 10*REGBYTES(sp) - STORE x17, 11*REGBYTES(sp) - STORE x28, 12*REGBYTES(sp) - STORE x29, 13*REGBYTES(sp) - STORE x30, 14*REGBYTES(sp) - STORE x31, 15*REGBYTES(sp) -.endm - - -############################################### -############################################### -#restore caller registers -.macro RESTORE_CONTEXT - LOAD x1, 0*REGBYTES(sp) - LOAD x5, 1*REGBYTES(sp) - LOAD x6, 2*REGBYTES(sp) - LOAD x7, 3*REGBYTES(sp) - LOAD x10, 4*REGBYTES(sp) - LOAD x11, 5*REGBYTES(sp) - LOAD x12, 6*REGBYTES(sp) - LOAD x13, 7*REGBYTES(sp) - LOAD x14, 8*REGBYTES(sp) - LOAD x15, 9*REGBYTES(sp) - LOAD x16, 10*REGBYTES(sp) - LOAD x17, 11*REGBYTES(sp) - LOAD x28, 12*REGBYTES(sp) - LOAD x29, 13*REGBYTES(sp) - LOAD x30, 14*REGBYTES(sp) - LOAD x31, 15*REGBYTES(sp) - -.endm - -############################################### -############################################### -#restore caller registers -.macro RESTORE_CONTEXT_EXCPT_X5 - LOAD x1, 0*REGBYTES(sp) - LOAD x6, 2*REGBYTES(sp) - LOAD x7, 3*REGBYTES(sp) - LOAD x10, 4*REGBYTES(sp) - LOAD x11, 5*REGBYTES(sp) - LOAD x12, 6*REGBYTES(sp) - LOAD x13, 7*REGBYTES(sp) - LOAD x14, 8*REGBYTES(sp) - LOAD x15, 9*REGBYTES(sp) - LOAD x16, 10*REGBYTES(sp) - LOAD x17, 11*REGBYTES(sp) - LOAD x28, 12*REGBYTES(sp) - LOAD x29, 13*REGBYTES(sp) - LOAD x30, 14*REGBYTES(sp) - LOAD x31, 15*REGBYTES(sp) - -.endm - -############################################### -############################################### -#restore caller registers -.macro RESTORE_CONTEXT_ONLY_X5 - LOAD x5, 1*REGBYTES(sp) -.endm - -############################################### -############################################### -# Save the mepc and mstatus -# -.macro SAVE_MEPC_MSTATUS - csrr x5, CSR_MEPC - STORE x5, 16*REGBYTES(sp) - csrr x5, CSR_MSTATUS - STORE x5, 17*REGBYTES(sp) - csrr x5, CSR_MXSTATUS - STORE x5, 18*REGBYTES(sp) -.endm - -############################################### -############################################### -# Restore the mepc and mstatus -# -.macro RESTORE_MEPC_MSTATUS - LOAD x5, 16*REGBYTES(sp) - csrw CSR_MEPC, x5 - LOAD x5, 17*REGBYTES(sp) - csrw CSR_MSTATUS, x5 - LOAD x5, 18*REGBYTES(sp) - csrw CSR_MXSTATUS, x5 -.endm - -############################################### -############################################### -// trap entry point -// - .section .text.entry - .align 6 // In ECLIC mode, the trap entry must be 64bytes aligned - .global trap_entry -.weak trap_entry -trap_entry: - // Allocate the stack space - addi sp, sp, -19*REGBYTES - - // Save the caller saving registers (context) - SAVE_CONTEXT - // Save the MEPC/MStatus reg - SAVE_MEPC_MSTATUS - - // Set the function argument - csrr a0, mcause - mv a1, sp - // Call the function - call handle_trap - - // Restore the MEPC/MStatus reg - RESTORE_MEPC_MSTATUS - // Restore the caller saving registers (context) - RESTORE_CONTEXT - - // De-allocate the stack space - addi sp, sp, 19*REGBYTES - // Return to regular code - mret -############################################### -############################################### -// IRQ entry point -// - .section .text.irq - .align 2 - .global irq_entry -.weak irq_entry -irq_entry: // -------------> This label will be set to MTVT2 register - // Allocate the stack space - addi sp, sp, -19*REGBYTES - - SAVE_CONTEXT// Save 16 regs - - //------This special CSR read operation, which is actually use mcause as operand to directly store it to memory - csrrwi x0, CSR_PUSHMCAUSE, 16 - //------This special CSR read operation, which is actually use mepc as operand to directly store it to memory - csrrwi x0, CSR_PUSHMEPC, 17 - //------This special CSR read operation, which is actually use mxstatus as operand to directly store it to memory - csrrwi x0, CSR_PUSHMXSTATUS, 18 - -service_loop: - //------This special CSR read/write operation, which is actually Claim the ECLIC to find its pending highest - // ID, if the ID is not 0, then automatically enable the mstatus.MIE, and jump to its vector-entry-label, and - // update the link register - csrrw ra, CSR_MINTSEL_JAL, ra - - RESTORE_CONTEXT_EXCPT_X5 - - #---- Critical section with interrupts disabled ----------------------- - DISABLE_MIE # Disable interrupts - - LOAD x5, 18*REGBYTES(sp) - csrw CSR_MXSTATUS, x5 - LOAD x5, 17*REGBYTES(sp) - csrw CSR_MEPC, x5 - LOAD x5, 16*REGBYTES(sp) - csrw CSR_MCAUSE, x5 - - - RESTORE_CONTEXT_ONLY_X5 - - // De-allocate the stack space - addi sp, sp, 19*REGBYTES - // Return to regular code - mret - - - - -#endif diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/handlers.c b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/handlers.c deleted file mode 100644 index 5d147f288b..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/handlers.c +++ /dev/null @@ -1,20 +0,0 @@ -//See LICENSE for license details. -#include -#include -#include "riscv_encoding.h" -#include "n22_func.h" -#include - -__attribute__((weak)) uintptr_t handle_nmi() { - rt_kprintf("nmi\n"); - return 0; -} - -__attribute__((weak)) uintptr_t handle_trap(uintptr_t mcause, uintptr_t sp) { - if (mcause == 0xFFF) { - handle_nmi(); - } - rt_kprintf("trap\n"); - return 0; -} - diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/init.c b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/init.c deleted file mode 100644 index 4a959cd9a6..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/init.c +++ /dev/null @@ -1,24 +0,0 @@ -//See LICENSE for license details. -#include -#include -#include -#include -#include "riscv_encoding.h" -#include "n22_func.h" - -void _init() { - -} - -void _fini() { -} - -void riscv_clock_init(void) { - SystemInit(); - - //ECLIC init - eclic_init(ECLIC_NUM_INTERRUPTS); - eclic_mode_enable(); - set_csr(mstatus, MSTATUS_MIE); - -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/start.S b/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/start.S deleted file mode 100644 index be68e7f08c..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/env_Eclipse/start.S +++ /dev/null @@ -1,247 +0,0 @@ -// See LICENSE for license details. - -// See LICENSE for license details. - -#include "riscv_encoding.h" - - .section .init - - .weak eclic_msip_handler - .weak eclic_mtip_handler - .weak eclic_bwei_handler - .weak eclic_pmovi_handler - .weak WWDGT_IRQHandler - .weak LVD_IRQHandler - .weak TAMPER_IRQHandler - .weak RTC_IRQHandler - .weak FMC_IRQHandler - .weak RCU_IRQHandler - .weak EXTI0_IRQHandler - .weak EXTI1_IRQHandler - .weak EXTI2_IRQHandler - .weak EXTI3_IRQHandler - .weak EXTI4_IRQHandler - .weak DMA0_Channel0_IRQHandler - .weak DMA0_Channel1_IRQHandler - .weak DMA0_Channel2_IRQHandler - .weak DMA0_Channel3_IRQHandler - .weak DMA0_Channel4_IRQHandler - .weak DMA0_Channel5_IRQHandler - .weak DMA0_Channel6_IRQHandler - .weak ADC0_1_IRQHandler - .weak CAN0_TX_IRQHandler - .weak CAN0_RX0_IRQHandler - .weak CAN0_RX1_IRQHandler - .weak CAN0_EWMC_IRQHandler - .weak EXTI5_9_IRQHandler - .weak TIMER0_BRK_IRQHandler - .weak TIMER0_UP_IRQHandler - .weak TIMER0_TRG_CMT_IRQHandler - .weak TIMER0_Channel_IRQHandler - .weak TIMER1_IRQHandler - .weak TIMER2_IRQHandler - .weak TIMER3_IRQHandler - .weak I2C0_EV_IRQHandler - .weak I2C0_ER_IRQHandler - .weak I2C1_EV_IRQHandler - .weak I2C1_ER_IRQHandler - .weak SPI0_IRQHandler - .weak SPI1_IRQHandler - .weak USART0_IRQHandler - .weak USART1_IRQHandler - .weak USART2_IRQHandler - .weak EXTI10_15_IRQHandler - .weak RTC_Alarm_IRQHandler - .weak USBFS_WKUP_IRQHandler - .weak EXMC_IRQHandler - .weak TIMER4_IRQHandler - .weak SPI2_IRQHandler - .weak UART3_IRQHandler - .weak UART4_IRQHandler - .weak TIMER5_IRQHandler - .weak TIMER6_IRQHandler - .weak DMA1_Channel0_IRQHandler - .weak DMA1_Channel1_IRQHandler - .weak DMA1_Channel2_IRQHandler - .weak DMA1_Channel3_IRQHandler - .weak DMA1_Channel4_IRQHandler - .weak CAN1_TX_IRQHandler - .weak CAN1_RX0_IRQHandler - .weak CAN1_RX1_IRQHandler - .weak CAN1_EWMC_IRQHandler - .weak USBFS_IRQHandler - - -vector_base: - j _start - .align 2 - .word 0 - .word 0 - .word eclic_msip_handler - .word 0 - .word 0 - .word 0 - .word eclic_mtip_handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word eclic_bwei_handler - .word eclic_pmovi_handler - .word WWDGT_IRQHandler - .word LVD_IRQHandler - .word TAMPER_IRQHandler - .word RTC_IRQHandler - .word FMC_IRQHandler - .word RCU_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA0_Channel0_IRQHandler - .word DMA0_Channel1_IRQHandler - .word DMA0_Channel2_IRQHandler - .word DMA0_Channel3_IRQHandler - .word DMA0_Channel4_IRQHandler - .word DMA0_Channel5_IRQHandler - .word DMA0_Channel6_IRQHandler - .word ADC0_1_IRQHandler - .word CAN0_TX_IRQHandler - .word CAN0_RX0_IRQHandler - .word CAN0_RX1_IRQHandler - .word CAN0_EWMC_IRQHandler - .word EXTI5_9_IRQHandler - .word TIMER0_BRK_IRQHandler - .word TIMER0_UP_IRQHandler - .word TIMER0_TRG_CMT_IRQHandler - .word TIMER0_Channel_IRQHandler - .word TIMER1_IRQHandler - .word TIMER2_IRQHandler - .word TIMER3_IRQHandler - .word I2C0_EV_IRQHandler - .word I2C0_ER_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word SPI0_IRQHandler - .word SPI1_IRQHandler - .word USART0_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word EXTI10_15_IRQHandler - .word RTC_Alarm_IRQHandler - .word USBFS_WKUP_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word EXMC_IRQHandler - .word 0 - .word TIMER4_IRQHandler - .word SPI2_IRQHandler - .word UART3_IRQHandler - .word UART4_IRQHandler - .word TIMER5_IRQHandler - .word TIMER6_IRQHandler - .word DMA1_Channel0_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word 0 - .word 0 - .word CAN1_TX_IRQHandler - .word CAN1_RX0_IRQHandler - .word CAN1_RX1_IRQHandler - .word CAN1_EWMC_IRQHandler - .word USBFS_IRQHandler - - .globl _start - .type _start,@function - -_start: - - /* Jump to logical address first to ensure correct operation of RAM region */ - la a0, _start - li a1, 1 - slli a1, a1, 29 - bleu a1, a0, _start0800 - srli a1, a1, 2 - bleu a1, a0, _start0800 - la a0, _start0800 - add a0, a0, a1 - jr a0 - -_start0800: - - /* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */ - li t0, 0x200 - csrs CSR_MMISC_CTL, t0 - - /* Intial the mtvt*/ - la t0, vector_base - csrw CSR_MTVT, t0 - - /* Intial the mtvt2 and enable it*/ - la t0, irq_entry - csrw CSR_MIRQ_ENTRY, t0 - csrs CSR_MIRQ_ENTRY, 0x1 - - /* Intial the CSR MTVEC for the Trap ane NMI base addr*/ - la t0, trap_entry - csrw CSR_MTVEC, t0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, MSTATUS_FS - csrs mstatus, t0 - csrw fcsr, x0 -#endif - -.option push -.option norelax - la gp, __global_pointer$ -.option pop - la sp, _sp - - /* Load data section */ - la a0, _data_lma - la a1, _data - la a2, _edata - bgeu a1, a2, 2f -1: - lw t0, (a0) - sw t0, (a1) - addi a0, a0, 4 - addi a1, a1, 4 - bltu a1, a2, 1b -2: - /* Clear bss section */ - la a0, __bss_start - la a1, _end - bgeu a0, a1, 2f -1: - sw zero, (a0) - addi a0, a0, 4 - bltu a0, a1, 1b -2: - /* Call global constructors */ - la a0, __libc_fini_array - call atexit - call __libc_init_array - - - /* argc = argv = 0 */ - li a0, 0 - li a1, 0 - call entry - /* tail exit */ - -1: - j 1b diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c deleted file mode 100644 index 8d49dc21f6..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/_exit.c +++ /dev/null @@ -1,17 +0,0 @@ -/* See LICENSE of license details. */ - -#include - -#include "stub.h" - - -void _exit(int code) -{ - const char message[] = "\nProgram has exited with code:"; - - write(STDERR_FILENO, message, sizeof(message) - 1); -// write_hex(STDERR_FILENO, code); -// write(STDERR_FILENO, "\n", 1); - - for (;;); -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/close.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/close.c deleted file mode 100644 index 618cc6de96..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/close.c +++ /dev/null @@ -1,8 +0,0 @@ -/* See LICENSE of license details. */ - -#include -#include "stub.h" - -int _close(int fd) { - return _stub(EBADF); -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c deleted file mode 100644 index c30d27cba6..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/fstat.c +++ /dev/null @@ -1,16 +0,0 @@ -/* See LICENSE of license details. */ - -#include -#include -#include -#include "stub.h" - -int _fstat(int fd, struct stat* st) -{ - if (isatty(fd)) { - st->st_mode = S_IFCHR; - return 0; - } - - return _stub(EBADF); -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c deleted file mode 100644 index 8bb63e1e37..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/isatty.c +++ /dev/null @@ -1,10 +0,0 @@ -/* See LICENSE of license details. */ - -#include - -int _isatty(int fd) { - if (fd == STDOUT_FILENO || fd == STDERR_FILENO) - return 1; - - return 0; -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c deleted file mode 100644 index c7be7a93c6..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/lseek.c +++ /dev/null @@ -1,13 +0,0 @@ -/* See LICENSE of license details. */ - -#include -#include -#include -#include "stub.h" - -off_t _lseek(int fd, off_t ptr, int dir) { - if (isatty(fd)) - return 0; - - return _stub(EBADF); -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/read.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/read.c deleted file mode 100644 index 54e15f6a30..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/read.c +++ /dev/null @@ -1,31 +0,0 @@ -/* See LICENSE of license details. */ - -#include -#include -#include -#include - -#include "stub.h" - -ssize_t _read(int fd, void* ptr, size_t len) -{ - // The below code was copied from freedom-e-sdk, but seems it is definitely wrong, so just comment it out - // Need to implement this function in the future, otherwise cannot use the C scanf function - //uint8_t * current = (uint8_t *)ptr; - //volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO); - //volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2); - - //ssize_t result = 0; - - //if (isatty(fd)) { - // for (current = (uint8_t *)ptr; - // (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); - // current ++) { - // *current = *uart_rx; - // result++; - // } - // return result; - //} - - return _stub(EBADF); -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c deleted file mode 100644 index e86debdec6..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/sbrk.c +++ /dev/null @@ -1,19 +0,0 @@ -/* See LICENSE of license details. */ - -#include - -void *_sbrk(ptrdiff_t incr) { - extern char _end[]; - - static char *curbrk = _end; -#ifndef __ANDES__ - extern char _heap_end[]; - if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) -#else - if ((curbrk + incr < _end) ) -#endif - return NULL - 1; - - curbrk += incr; - return curbrk - incr; -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h b/bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h deleted file mode 100644 index e075daeb8c..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/stub.h +++ /dev/null @@ -1,15 +0,0 @@ -/* See LICENSE of license details. */ -#ifndef _NUCLEI_SYS_STUB_H -#define _NUCLEI_SYS_STUB_H - -#include -#include - -void write_hex(int fd, unsigned long int hex); - -static inline int _stub(int err) -{ - return -1; -} - -#endif /* _NUCLEI_SYS_STUB_H */ diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/write.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/write.c deleted file mode 100644 index 699ba193f9..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/write.c +++ /dev/null @@ -1,45 +0,0 @@ -/* See LICENSE of license details. */ - -#include -#include -#include -#include -#include -#include - -#include "stub.h" -#include "gd32vf103.h" - -typedef unsigned int size_t; - -extern int _put_char(int ch) __attribute__((weak)); - -ssize_t _write(int fd, const void* ptr, size_t len) { - const uint8_t * current = (const uint8_t *) ptr; - -// if (isatty(fd)) - { - for (size_t jj = 0; jj < len; jj++) { - _put_char(current[jj]); - - if (current[jj] == '\n') { - _put_char('\r'); - } - } - return len; - } - - return _stub(EBADF); -} - -int puts(const char* string) { - return _write(0, (const void *) string, strlen(string)); -} - -int _put_char(int ch) { - usart_data_transmit(USART0, (uint8_t) ch); - while (usart_flag_get(USART0, USART_FLAG_TBE) == RESET) { - } - - return ch; -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/stubs/write_hex.c b/bsp/gd32vf103v-eval/libraries/n22/stubs/write_hex.c deleted file mode 100644 index 2f499b5ee5..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/stubs/write_hex.c +++ /dev/null @@ -1,17 +0,0 @@ -/* See LICENSE of license details. */ - -#include -#include - -void write_hex(int fd, unsigned long int hex) { - uint8_t ii; - uint8_t jj; - char towrite; - write(fd, "0x", 2); - for (ii = sizeof(unsigned long int) * 2; ii > 0; ii--) { - jj = ii - 1; - uint8_t digit = ((hex & (0xF << (jj * 4))) >> (jj * 4)); - towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA)); - write(fd, &towrite, 1); - } -} diff --git a/bsp/gd32vf103v-eval/libraries/n22/tools/openocd_upload.sh b/bsp/gd32vf103v-eval/libraries/n22/tools/openocd_upload.sh deleted file mode 100644 index 3e987a7bf9..0000000000 --- a/bsp/gd32vf103v-eval/libraries/n22/tools/openocd_upload.sh +++ /dev/null @@ -1,5 +0,0 @@ -#! /bin/bash -x - -work/build/openocd/prefix/bin/openocd -f ${2} \ - -c "flash protect 0 0 last off; program ${1} verify; resume 0x20000000; exit" \ - 2>&1 | tee openocd_upload.log diff --git a/bsp/gd32vf103v-eval/rtconfig.h b/bsp/gd32vf103v-eval/rtconfig.h deleted file mode 100644 index ee368a98f3..0000000000 --- a/bsp/gd32vf103v-eval/rtconfig.h +++ /dev/null @@ -1,250 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 8 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 - -/* kservice optimization */ - -#define RT_USING_DEBUG -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50002 -#define RT_USING_HW_ATOMIC - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define FINSH_USING_OPTION_COMPLETION - -/* DFS: device virtual file system */ - - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_UNAMED_PIPE_NUMBER 64 -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -/* ISO-ANSI C layer */ - -/* Timezone and Daylight Saving Time */ - -#define RT_LIBC_USING_LIGHT_TZ_DST -#define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - -/* sensors drivers */ - - -/* touch drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* Signal Processing and Control Algorithm Packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Arduino libraries */ - - -/* Projects and Demos */ - - -/* Sensors */ - - -/* Display */ - - -/* Timing */ - - -/* Data Processing */ - - -/* Data Storage */ - -/* Communication */ - - -/* Device Control */ - - -/* Other */ - - -/* Signal IO */ - - -/* Uncategorized */ - -/* Hardware Drivers Config */ - -#define SOC_GD32VF103V - -/* Onboard Peripheral Drivers */ - -#define BSP_USING_USART - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO -#define BSP_USING_UART -#define BSP_USING_UART0 - -/* Board extended module Drivers */ - -#define SOC_GD32VF103 - -#endif diff --git a/bsp/gd32vf103v-eval/rtconfig.py b/bsp/gd32vf103v-eval/rtconfig.py deleted file mode 100644 index 2d767412bb..0000000000 --- a/bsp/gd32vf103v-eval/rtconfig.py +++ /dev/null @@ -1,63 +0,0 @@ -import os -ARCH = 'risc-v' -CPU = 'bumblebee' -# toolchains options -CROSS_TOOL = 'gcc' - -#------- toolchains path ------------------------------------------------------- -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'/opt/unknown-gcc/bin' -else: - print('Please make sure your toolchains is GNU GCC!') - exit(0) - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' -#BUILD = 'release' - -CORE = 'risc-v' -MAP_FILE = 'rtthread.map' -LINK_FILE = './libraries/n22/env_Eclipse/GD32VF103xB.lds' -TARGET_NAME = 'rtthread.bin' - -#------- GCC settings ---------------------------------------------------------- -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'riscv-none-embed-' - CC = PREFIX + 'gcc' - CXX= PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L. -nostartfiles -lc ' - CFLAGS = DEVICE - CFLAGS += ' -save-temps=obj' - AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp' - AFLAGS += ' -Iplatform -Ilibraries/n22/include -Ilibraries/n22/env_Eclipse' - LFLAGS = DEVICE - LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE - LFLAGS += ' -T ' + LINK_FILE - LFLAGS += ' -Wl,-wrap=memset' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -g3' - AFLAGS += ' -g3' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' - POST_ACTION += SIZE + ' $TARGET\n' -- cgit v1.3.1